[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / sun3_scsi.c

/*
 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
 *
 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
 *
 * VME support added by Sam Creasey
 *
 * TODO: modify this driver to support multiple Sun3 SCSI VME boards
 *
 * Adapted from mac_scsinew.c:
 */
/*
 * Generic Macintosh NCR5380 driver
 *
 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
 *
 * derived in part from:
 */
/*
 * Generic Generic NCR5380 driver
 *
 * Copyright 1995, Russell King
 */

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/platform_device.h>

#include <asm/io.h>
#include <asm/dvma.h>

#include <scsi/scsi_host.h>
#include "sun3_scsi.h"

/* minimum number of bytes to do dma on */
#define DMA_MIN_SIZE                    129

/* Definitions for the core NCR5380 driver. */

#define NCR5380_implementation_fields   /* none */

#define NCR5380_read(reg)               in_8(hostdata->io + (reg))
#define NCR5380_write(reg, value)       out_8(hostdata->io + (reg), value)

#define NCR5380_queue_command           sun3scsi_queue_command
#define NCR5380_bus_reset               sun3scsi_bus_reset
#define NCR5380_abort                   sun3scsi_abort
#define NCR5380_info                    sun3scsi_info

#define NCR5380_dma_recv_setup(instance, data, count) (count)
#define NCR5380_dma_send_setup(instance, data, count) (count)
#define NCR5380_dma_residual(instance) \
        sun3scsi_dma_residual(instance)
#define NCR5380_dma_xfer_len(instance, cmd, phase) \
        sun3scsi_dma_xfer_len(cmd->SCp.this_residual, cmd)

#define NCR5380_acquire_dma_irq(instance)    (1)
#define NCR5380_release_dma_irq(instance)

#include "NCR5380.h"


extern int sun3_map_test(unsigned long, char *);

static int setup_can_queue = -1;
module_param(setup_can_queue, int, 0);
static int setup_cmd_per_lun = -1;
module_param(setup_cmd_per_lun, int, 0);
static int setup_sg_tablesize = -1;
module_param(setup_sg_tablesize, int, 0);
static int setup_hostid = -1;
module_param(setup_hostid, int, 0);

/* ms to wait after hitting dma regs */
#define SUN3_DMA_DELAY 10

/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
#define SUN3_DVMA_BUFSIZE 0xe000

static struct scsi_cmnd *sun3_dma_setup_done;
static volatile struct sun3_dma_regs *dregs;
static struct sun3_udc_regs *udc_regs;
static unsigned char *sun3_dma_orig_addr;
static unsigned long sun3_dma_orig_count;
static int sun3_dma_active;
static unsigned long last_residual;

#ifndef SUN3_SCSI_VME
/* dma controller register access functions */

static inline unsigned short sun3_udc_read(unsigned char reg)
{
	unsigned short ret;

	dregs->udc_addr = UDC_CSR;
	udelay(SUN3_DMA_DELAY);
	ret = dregs->udc_data;
	udelay(SUN3_DMA_DELAY);
	
	return ret;
}

static inline void sun3_udc_write(unsigned short val, unsigned char reg)
{
	dregs->udc_addr = reg;
	udelay(SUN3_DMA_DELAY);
	dregs->udc_data = val;
	udelay(SUN3_DMA_DELAY);
}
#endif

// safe bits for the CSR
#define CSR_GOOD 0x060f

static irqreturn_t scsi_sun3_intr(int irq, void *dev)
{
	struct Scsi_Host *instance = dev;
	unsigned short csr = dregs->csr;
	int handled = 0;

#ifdef SUN3_SCSI_VME
	dregs->csr &= ~CSR_DMA_ENABLE;
#endif

	if(csr & ~CSR_GOOD) {
		if (csr & CSR_DMA_BUSERR)
			shost_printk(KERN_ERR, instance, "bus error in DMA\n");
		if (csr & CSR_DMA_CONFLICT)
			shost_printk(KERN_ERR, instance, "DMA conflict\n");
		handled = 1;
	}

	if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
		NCR5380_intr(irq, dev);
		handled = 1;
	}

	return IRQ_RETVAL(handled);
}

/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
static unsigned long sun3scsi_dma_setup(struct Scsi_Host *instance,
                                void *data, unsigned long count, int write_flag)
{
	void *addr;

	if(sun3_dma_orig_addr != NULL)
		dvma_unmap(sun3_dma_orig_addr);

#ifdef SUN3_SCSI_VME
	addr = (void *)dvma_map_vme((unsigned long) data, count);
#else
	addr = (void *)dvma_map((unsigned long) data, count);
#endif
		
	sun3_dma_orig_addr = addr;
	sun3_dma_orig_count = count;

#ifndef SUN3_SCSI_VME
	dregs->fifo_count = 0;
	sun3_udc_write(UDC_RESET, UDC_CSR);
	
	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
#endif
	
	/* set direction */
	if(write_flag)
		dregs->csr |= CSR_SEND;
	else
		dregs->csr &= ~CSR_SEND;
	
#ifdef SUN3_SCSI_VME
	dregs->csr |= CSR_PACK_ENABLE;

	dregs->dma_addr_hi = ((unsigned long)addr >> 16);
	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);

	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;
	dregs->fifo_count_hi = 0;
	dregs->fifo_count = 0;
#else
	/* byte count for fifo */
	dregs->fifo_count = count;

	sun3_udc_write(UDC_RESET, UDC_CSR);
	
	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
	
	if(dregs->fifo_count != count) { 
		shost_printk(KERN_ERR, instance, "FIFO mismatch %04x not %04x\n",
		             dregs->fifo_count, (unsigned int) count);
		NCR5380_dprint(NDEBUG_DMA, instance);
	}

	/* setup udc */
	udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
	udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
	udc_regs->count = count/2; /* count in words */
	udc_regs->mode_hi = UDC_MODE_HIWORD;
	if(write_flag) {
		if(count & 1)
			udc_regs->count++;
		udc_regs->mode_lo = UDC_MODE_LSEND;
		udc_regs->rsel = UDC_RSEL_SEND;
	} else {
		udc_regs->mode_lo = UDC_MODE_LRECV;
		udc_regs->rsel = UDC_RSEL_RECV;
	}
	
	/* announce location of regs block */
	sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
		       UDC_CHN_HI); 

	sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);

	/* set dma master on */
	sun3_udc_write(0xd, UDC_MODE);

	/* interrupt enable */
	sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
#endif
	
       	return count;

}

static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance)
{
	return last_residual;
}

static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted_len,
                                                  struct scsi_cmnd *cmd)
{
	if (wanted_len < DMA_MIN_SIZE || cmd->request->cmd_type != REQ_TYPE_FS)
		return 0;

	return wanted_len;
}

static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
{
#ifdef SUN3_SCSI_VME
	unsigned short csr;

	csr = dregs->csr;

	dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);

	dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);

/*	if(!(csr & CSR_DMA_ENABLE))
 *		dregs->csr |= CSR_DMA_ENABLE;
 */
#else
    sun3_udc_write(UDC_CHN_START, UDC_CSR);
#endif
    
    return 0;
}

/* clean up after our dma is done */
static int sun3scsi_dma_finish(int write_flag)
{
	unsigned short __maybe_unused count;
	unsigned short fifo;
	int ret = 0;
	
	sun3_dma_active = 0;

#ifdef SUN3_SCSI_VME
	dregs->csr &= ~CSR_DMA_ENABLE;

	fifo = dregs->fifo_count;
	if (write_flag) {
		if ((fifo > 0) && (fifo < sun3_dma_orig_count))
			fifo++;
	}

	last_residual = fifo;
	/* empty bytes from the fifo which didn't make it */
	if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
		unsigned char *vaddr;

		vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);

		vaddr += (sun3_dma_orig_count - fifo);
		vaddr--;

		switch (dregs->csr & CSR_LEFT) {
		case CSR_LEFT_3:
			*vaddr = (dregs->bpack_lo & 0xff00) >> 8;
			vaddr--;

		case CSR_LEFT_2:
			*vaddr = (dregs->bpack_hi & 0x00ff);
			vaddr--;

		case CSR_LEFT_1:
			*vaddr = (dregs->bpack_hi & 0xff00) >> 8;
			break;
		}
	}
#else
	// check to empty the fifo on a read
	if(!write_flag) {
		int tmo = 20000; /* .2 sec */
		
		while(1) {
			if(dregs->csr & CSR_FIFO_EMPTY)
				break;

			if(--tmo <= 0) {
				printk("sun3scsi: fifo failed to empty!\n");
				return 1;
			}
			udelay(10);
		}
	}

	dregs->udc_addr = 0x32;
	udelay(SUN3_DMA_DELAY);
	count = 2 * dregs->udc_data;
	udelay(SUN3_DMA_DELAY);

	fifo = dregs->fifo_count;
	last_residual = fifo;

	/* empty bytes from the fifo which didn't make it */
	if((!write_flag) && (count - fifo) == 2) {
		unsigned short data;
		unsigned char *vaddr;

		data = dregs->fifo_data;
		vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
		
		vaddr += (sun3_dma_orig_count - fifo);

		vaddr[-2] = (data & 0xff00) >> 8;
		vaddr[-1] = (data & 0xff);
	}
#endif

	dvma_unmap(sun3_dma_orig_addr);
	sun3_dma_orig_addr = NULL;

#ifdef SUN3_SCSI_VME
	dregs->dma_addr_hi = 0;
	dregs->dma_addr_lo = 0;
	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;

	dregs->fifo_count = 0;
	dregs->fifo_count_hi = 0;

	dregs->csr &= ~CSR_SEND;
/*	dregs->csr |= CSR_DMA_ENABLE; */
#else
	sun3_udc_write(UDC_RESET, UDC_CSR);
	dregs->fifo_count = 0;
	dregs->csr &= ~CSR_SEND;

	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
#endif
	
	sun3_dma_setup_done = NULL;

	return ret;

}
	
#include "NCR5380.c"

#ifdef SUN3_SCSI_VME
#define SUN3_SCSI_NAME          "Sun3 NCR5380 VME SCSI"
#define DRV_MODULE_NAME         "sun3_scsi_vme"
#else
#define SUN3_SCSI_NAME          "Sun3 NCR5380 SCSI"
#define DRV_MODULE_NAME         "sun3_scsi"
#endif

#define PFX                     DRV_MODULE_NAME ": "

static struct scsi_host_template sun3_scsi_template = {
	.module			= THIS_MODULE,
	.proc_name		= DRV_MODULE_NAME,
	.name			= SUN3_SCSI_NAME,
	.info			= sun3scsi_info,
	.queuecommand		= sun3scsi_queue_command,
	.eh_abort_handler	= sun3scsi_abort,
	.eh_bus_reset_handler	= sun3scsi_bus_reset,
	.can_queue		= 16,
	.this_id		= 7,
	.sg_tablesize		= SG_NONE,
	.cmd_per_lun		= 2,
	.use_clustering		= DISABLE_CLUSTERING,
	.cmd_size		= NCR5380_CMD_SIZE,
};

static int __init sun3_scsi_probe(struct platform_device *pdev)
{
	struct Scsi_Host *instance;
	struct NCR5380_hostdata *hostdata;
	int error;
	struct resource *irq, *mem;
	void __iomem *ioaddr;
	int host_flags = 0;
#ifdef SUN3_SCSI_VME
	int i;
#endif

	if (setup_can_queue > 0)
		sun3_scsi_template.can_queue = setup_can_queue;
	if (setup_cmd_per_lun > 0)
		sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
	if (setup_sg_tablesize >= 0)
		sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
	if (setup_hostid >= 0)
		sun3_scsi_template.this_id = setup_hostid & 7;

#ifdef SUN3_SCSI_VME
	ioaddr = NULL;
	for (i = 0; i < 2; i++) {
		unsigned char x;

		irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
		if (!irq || !mem)
			break;

		ioaddr = sun3_ioremap(mem->start, resource_size(mem),
		                      SUN3_PAGE_TYPE_VME16);
		dregs = (struct sun3_dma_regs *)(ioaddr + 8);

		if (sun3_map_test((unsigned long)dregs, &x)) {
			unsigned short oldcsr;

			oldcsr = dregs->csr;
			dregs->csr = 0;
			udelay(SUN3_DMA_DELAY);
			if (dregs->csr == 0x1400)
				break;

			dregs->csr = oldcsr;
		}

		iounmap(ioaddr);
		ioaddr = NULL;
	}
	if (!ioaddr)
		return -ENODEV;
#else
	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!irq || !mem)
		return -ENODEV;

	ioaddr = ioremap(mem->start, resource_size(mem));
	dregs = (struct sun3_dma_regs *)(ioaddr + 8);

	udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
	if (!udc_regs) {
		pr_err(PFX "couldn't allocate DVMA memory!\n");
		iounmap(ioaddr);
		return -ENOMEM;
	}
#endif

	instance = scsi_host_alloc(&sun3_scsi_template,
	                           sizeof(struct NCR5380_hostdata));
	if (!instance) {
		error = -ENOMEM;
		goto fail_alloc;
	}

	instance->irq = irq->start;

	hostdata = shost_priv(instance);
	hostdata->base = mem->start;
	hostdata->io = ioaddr;

	error = NCR5380_init(instance, host_flags);
	if (error)
		goto fail_init;

	error = request_irq(instance->irq, scsi_sun3_intr, 0,
	                    "NCR5380", instance);
	if (error) {
		pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
		       instance->host_no, instance->irq);
		goto fail_irq;
	}

	dregs->csr = 0;
	udelay(SUN3_DMA_DELAY);
	dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
	udelay(SUN3_DMA_DELAY);
	dregs->fifo_count = 0;
#ifdef SUN3_SCSI_VME
	dregs->fifo_count_hi = 0;
	dregs->dma_addr_hi = 0;
	dregs->dma_addr_lo = 0;
	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;

	dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
#endif

	NCR5380_maybe_reset_bus(instance);

	error = scsi_add_host(instance, NULL);
	if (error)
		goto fail_host;

	platform_set_drvdata(pdev, instance);

	scsi_scan_host(instance);
	return 0;

fail_host:
	free_irq(instance->irq, instance);
fail_irq:
	NCR5380_exit(instance);
fail_init:
	scsi_host_put(instance);
fail_alloc:
	if (udc_regs)
		dvma_free(udc_regs);
	iounmap(ioaddr);
	return error;
}

static int __exit sun3_scsi_remove(struct platform_device *pdev)
{
	struct Scsi_Host *instance = platform_get_drvdata(pdev);
	struct NCR5380_hostdata *hostdata = shost_priv(instance);
	void __iomem *ioaddr = hostdata->io;

	scsi_remove_host(instance);
	free_irq(instance->irq, instance);
	NCR5380_exit(instance);
	scsi_host_put(instance);
	if (udc_regs)
		dvma_free(udc_regs);
	iounmap(ioaddr);
	return 0;
}

static struct platform_driver sun3_scsi_driver = {
	.remove = __exit_p(sun3_scsi_remove),
	.driver = {
		.name	= DRV_MODULE_NAME,
	},
};

module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);

MODULE_ALIAS("platform:" DRV_MODULE_NAME);
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
	3	*
	4	* Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
	5	*
757f5bad FT	6	* VME support added by Sam Creasey
	7	*
	8	* TODO: modify this driver to support multiple Sun3 SCSI VME boards
	9	*
1da177e4 LT	10	* Adapted from mac_scsinew.c:
	11	*/
	12	/*
	13	* Generic Macintosh NCR5380 driver
	14	*
	15	* Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
	16	*
	17	* derived in part from:
	18	*/
	19	/*
	20	* Generic Generic NCR5380 driver
	21	*
	22	* Copyright 1995, Russell King
1da177e4 LT	23	*/
1da177e4 LT	24
1da177e4	25	#include <linux/types.h>
1da177e4	26	#include <linux/delay.h>
1da177e4	27	#include <linux/module.h>
1da177e4 LT	28	#include <linux/ioport.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
0d31f875	31	#include <linux/platform_device.h>
1da177e4 LT	32
1da177e4 LT	33	#include <asm/io.h>
1da177e4	34	#include <asm/dvma.h>
1da177e4	35
1da177e4 LT	36	#include <scsi/scsi_host.h>
1da177e4 LT	37	#include "sun3_scsi.h"
1da177e4	38
8dad0c51 FT	39	/* minimum number of bytes to do dma on */
8dad0c51 FT	40	#define DMA_MIN_SIZE 129
1da177e4	41
e63449c4 FT	42	/* Definitions for the core NCR5380 driver. */
e63449c4 FT	43
2231ef87 FT	44	#define NCR5380_implementation_fields /* none */
2231ef87 FT	45
61e1ce58 FT	46	#define NCR5380_read(reg) in_8(hostdata->io + (reg))
61e1ce58 FT	47	#define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
2231ef87 FT	48
	49	#define NCR5380_queue_command sun3scsi_queue_command
	50	#define NCR5380_bus_reset sun3scsi_bus_reset
	51	#define NCR5380_abort sun3scsi_abort
2231ef87 FT	52	#define NCR5380_info sun3scsi_info
2231ef87 FT	53
e9db3198 FT	54	#define NCR5380_dma_recv_setup(instance, data, count) (count)
e9db3198 FT	55	#define NCR5380_dma_send_setup(instance, data, count) (count)
2231ef87 FT	56	#define NCR5380_dma_residual(instance) \
	57	sun3scsi_dma_residual(instance)
	58	#define NCR5380_dma_xfer_len(instance, cmd, phase) \
e63449c4	59	sun3scsi_dma_xfer_len(cmd->SCp.this_residual, cmd)
2231ef87	60
8dad0c51 FT	61	#define NCR5380_acquire_dma_irq(instance) (1)
	62	#define NCR5380_release_dma_irq(instance)
	63
2231ef87 FT	64	#include "NCR5380.h"
	65
	66
	67	extern int sun3_map_test(unsigned long, char *);
	68
1da177e4 LT	69	static int setup_can_queue = -1;
	70	module_param(setup_can_queue, int, 0);
	71	static int setup_cmd_per_lun = -1;
	72	module_param(setup_cmd_per_lun, int, 0);
	73	static int setup_sg_tablesize = -1;
	74	module_param(setup_sg_tablesize, int, 0);
1da177e4 LT	75	static int setup_hostid = -1;
	76	module_param(setup_hostid, int, 0);
	77
1da177e4 LT	78	/* ms to wait after hitting dma regs */
	79	#define SUN3_DMA_DELAY 10
	80
	81	/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
	82	#define SUN3_DVMA_BUFSIZE 0xe000
	83
2231ef87	84	static struct scsi_cmnd *sun3_dma_setup_done;
1da177e4	85	static volatile struct sun3_dma_regs *dregs;
0d31f875	86	static struct sun3_udc_regs *udc_regs;
d5f7e65d FT	87	static unsigned char *sun3_dma_orig_addr;
	88	static unsigned long sun3_dma_orig_count;
	89	static int sun3_dma_active;
	90	static unsigned long last_residual;
1da177e4	91
757f5bad	92	#ifndef SUN3_SCSI_VME
1da177e4 LT	93	/* dma controller register access functions */
	94
	95	static inline unsigned short sun3_udc_read(unsigned char reg)
	96	{
	97	unsigned short ret;
	98
	99	dregs->udc_addr = UDC_CSR;
	100	udelay(SUN3_DMA_DELAY);
	101	ret = dregs->udc_data;
	102	udelay(SUN3_DMA_DELAY);
	103
	104	return ret;
	105	}
	106
	107	static inline void sun3_udc_write(unsigned short val, unsigned char reg)
	108	{
	109	dregs->udc_addr = reg;
	110	udelay(SUN3_DMA_DELAY);
	111	dregs->udc_data = val;
	112	udelay(SUN3_DMA_DELAY);
	113	}
757f5bad	114	#endif
1da177e4	115
1da177e4 LT	116	// safe bits for the CSR
	117	#define CSR_GOOD 0x060f
	118
cd46140a	119	static irqreturn_t scsi_sun3_intr(int irq, void *dev)
1da177e4	120	{
cd46140a	121	struct Scsi_Host *instance = dev;
1da177e4 LT	122	unsigned short csr = dregs->csr;
	123	int handled = 0;
	124
757f5bad FT	125	#ifdef SUN3_SCSI_VME
	126	dregs->csr &= ~CSR_DMA_ENABLE;
	127	#endif
	128
1da177e4	129	if(csr & ~CSR_GOOD) {
cd46140a FT	130	if (csr & CSR_DMA_BUSERR)
	131	shost_printk(KERN_ERR, instance, "bus error in DMA\n");
	132	if (csr & CSR_DMA_CONFLICT)
	133	shost_printk(KERN_ERR, instance, "DMA conflict\n");
1da177e4 LT	134	handled = 1;
	135	}
	136
	137	if(csr & (CSR_SDB_INT \| CSR_DMA_INT)) {
cd46140a	138	NCR5380_intr(irq, dev);
1da177e4 LT	139	handled = 1;
	140	}
	141
	142	return IRQ_RETVAL(handled);
	143	}
	144
1da177e4	145	/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
cd46140a FT	146	static unsigned long sun3scsi_dma_setup(struct Scsi_Host *instance,
cd46140a FT	147	void *data, unsigned long count, int write_flag)
1da177e4	148	{
1da177e4 LT	149	void *addr;
	150
	151	if(sun3_dma_orig_addr != NULL)
	152	dvma_unmap(sun3_dma_orig_addr);
	153
757f5bad FT	154	#ifdef SUN3_SCSI_VME
	155	addr = (void *)dvma_map_vme((unsigned long) data, count);
	156	#else
1da177e4	157	addr = (void *)dvma_map((unsigned long) data, count);
757f5bad	158	#endif
1da177e4 LT	159
	160	sun3_dma_orig_addr = addr;
	161	sun3_dma_orig_count = count;
757f5bad FT	162
757f5bad FT	163	#ifndef SUN3_SCSI_VME
1da177e4 LT	164	dregs->fifo_count = 0;
	165	sun3_udc_write(UDC_RESET, UDC_CSR);
	166
	167	/* reset fifo */
	168	dregs->csr &= ~CSR_FIFO;
	169	dregs->csr \|= CSR_FIFO;
757f5bad	170	#endif
1da177e4 LT	171
	172	/* set direction */
	173	if(write_flag)
	174	dregs->csr \|= CSR_SEND;
	175	else
	176	dregs->csr &= ~CSR_SEND;
	177
757f5bad FT	178	#ifdef SUN3_SCSI_VME
	179	dregs->csr \|= CSR_PACK_ENABLE;
	180
	181	dregs->dma_addr_hi = ((unsigned long)addr >> 16);
	182	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
	183
	184	dregs->dma_count_hi = 0;
	185	dregs->dma_count_lo = 0;
	186	dregs->fifo_count_hi = 0;
	187	dregs->fifo_count = 0;
	188	#else
1da177e4 LT	189	/* byte count for fifo */
	190	dregs->fifo_count = count;
	191
	192	sun3_udc_write(UDC_RESET, UDC_CSR);
	193
	194	/* reset fifo */
	195	dregs->csr &= ~CSR_FIFO;
	196	dregs->csr \|= CSR_FIFO;
	197
	198	if(dregs->fifo_count != count) {
cd46140a FT	199	shost_printk(KERN_ERR, instance, "FIFO mismatch %04x not %04x\n",
	200	dregs->fifo_count, (unsigned int) count);
	201	NCR5380_dprint(NDEBUG_DMA, instance);
1da177e4 LT	202	}
	203
	204	/* setup udc */
1da177e4 LT	205	udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
1da177e4 LT	206	udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
1da177e4 LT	207	udc_regs->count = count/2; /* count in words */
	208	udc_regs->mode_hi = UDC_MODE_HIWORD;
	209	if(write_flag) {
	210	if(count & 1)
	211	udc_regs->count++;
	212	udc_regs->mode_lo = UDC_MODE_LSEND;
	213	udc_regs->rsel = UDC_RSEL_SEND;
	214	} else {
	215	udc_regs->mode_lo = UDC_MODE_LRECV;
	216	udc_regs->rsel = UDC_RSEL_RECV;
	217	}
	218
	219	/* announce location of regs block */
	220	sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
	221	UDC_CHN_HI);
	222
	223	sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
	224
	225	/* set dma master on */
	226	sun3_udc_write(0xd, UDC_MODE);
	227
	228	/* interrupt enable */
	229	sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
757f5bad	230	#endif
1da177e4 LT	231
	232	return count;
	233
	234	}
	235
1da177e4 LT	236	static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance)
	237	{
	238	return last_residual;
	239	}
	240
e63449c4 FT	241	static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted_len,
e63449c4 FT	242	struct scsi_cmnd *cmd)
1da177e4	243	{
e63449c4	244	if (wanted_len < DMA_MIN_SIZE \|\| cmd->request->cmd_type != REQ_TYPE_FS)
1da177e4	245	return 0;
e63449c4 FT	246
e63449c4 FT	247	return wanted_len;
1da177e4 LT	248	}
	249
	250	static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
	251	{
757f5bad FT	252	#ifdef SUN3_SCSI_VME
	253	unsigned short csr;
	254
	255	csr = dregs->csr;
	256
	257	dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
	258	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
1da177e4	259
757f5bad FT	260	dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
	261	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
	262
	263	/* if(!(csr & CSR_DMA_ENABLE))
	264	* dregs->csr \|= CSR_DMA_ENABLE;
	265	*/
	266	#else
1da177e4	267	sun3_udc_write(UDC_CHN_START, UDC_CSR);
757f5bad	268	#endif
1da177e4 LT	269
	270	return 0;
	271	}
	272
	273	/* clean up after our dma is done */
	274	static int sun3scsi_dma_finish(int write_flag)
	275	{
757f5bad	276	unsigned short __maybe_unused count;
1da177e4 LT	277	unsigned short fifo;
	278	int ret = 0;
	279
	280	sun3_dma_active = 0;
757f5bad FT	281
	282	#ifdef SUN3_SCSI_VME
	283	dregs->csr &= ~CSR_DMA_ENABLE;
	284
	285	fifo = dregs->fifo_count;
	286	if (write_flag) {
	287	if ((fifo > 0) && (fifo < sun3_dma_orig_count))
	288	fifo++;
	289	}
	290
	291	last_residual = fifo;
	292	/* empty bytes from the fifo which didn't make it */
	293	if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
	294	unsigned char *vaddr;
	295
	296	vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
	297
	298	vaddr += (sun3_dma_orig_count - fifo);
	299	vaddr--;
	300
	301	switch (dregs->csr & CSR_LEFT) {
	302	case CSR_LEFT_3:
	303	*vaddr = (dregs->bpack_lo & 0xff00) >> 8;
	304	vaddr--;
	305
	306	case CSR_LEFT_2:
	307	*vaddr = (dregs->bpack_hi & 0x00ff);
	308	vaddr--;
	309
	310	case CSR_LEFT_1:
	311	*vaddr = (dregs->bpack_hi & 0xff00) >> 8;
	312	break;
	313	}
	314	}
	315	#else
1da177e4 LT	316	// check to empty the fifo on a read
	317	if(!write_flag) {
	318	int tmo = 20000; /* .2 sec */
	319
	320	while(1) {
	321	if(dregs->csr & CSR_FIFO_EMPTY)
	322	break;
	323
	324	if(--tmo <= 0) {
	325	printk("sun3scsi: fifo failed to empty!\n");
	326	return 1;
	327	}
	328	udelay(10);
	329	}
	330	}
1da177e4	331
cd46140a FT	332	dregs->udc_addr = 0x32;
	333	udelay(SUN3_DMA_DELAY);
	334	count = 2 * dregs->udc_data;
	335	udelay(SUN3_DMA_DELAY);
1da177e4 LT	336
	337	fifo = dregs->fifo_count;
	338	last_residual = fifo;
	339
	340	/* empty bytes from the fifo which didn't make it */
	341	if((!write_flag) && (count - fifo) == 2) {
	342	unsigned short data;
	343	unsigned char *vaddr;
	344
	345	data = dregs->fifo_data;
	346	vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
	347
	348	vaddr += (sun3_dma_orig_count - fifo);
	349
	350	vaddr[-2] = (data & 0xff00) >> 8;
	351	vaddr[-1] = (data & 0xff);
	352	}
757f5bad	353	#endif
1da177e4 LT	354
	355	dvma_unmap(sun3_dma_orig_addr);
	356	sun3_dma_orig_addr = NULL;
757f5bad FT	357
	358	#ifdef SUN3_SCSI_VME
	359	dregs->dma_addr_hi = 0;
	360	dregs->dma_addr_lo = 0;
	361	dregs->dma_count_hi = 0;
	362	dregs->dma_count_lo = 0;
	363
	364	dregs->fifo_count = 0;
	365	dregs->fifo_count_hi = 0;
	366
	367	dregs->csr &= ~CSR_SEND;
	368	/* dregs->csr \|= CSR_DMA_ENABLE; */
	369	#else
1da177e4 LT	370	sun3_udc_write(UDC_RESET, UDC_CSR);
	371	dregs->fifo_count = 0;
	372	dregs->csr &= ~CSR_SEND;
	373
	374	/* reset fifo */
	375	dregs->csr &= ~CSR_FIFO;
	376	dregs->csr \|= CSR_FIFO;
757f5bad	377	#endif
1da177e4 LT	378
	379	sun3_dma_setup_done = NULL;
	380
	381	return ret;
	382
	383	}
	384
e9db3198	385	#include "NCR5380.c"
1da177e4	386
0d31f875 FT	387	#ifdef SUN3_SCSI_VME
	388	#define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
	389	#define DRV_MODULE_NAME "sun3_scsi_vme"
	390	#else
	391	#define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
	392	#define DRV_MODULE_NAME "sun3_scsi"
	393	#endif
	394
	395	#define PFX DRV_MODULE_NAME ": "
	396
	397	static struct scsi_host_template sun3_scsi_template = {
	398	.module = THIS_MODULE,
	399	.proc_name = DRV_MODULE_NAME,
1da177e4	400	.name = SUN3_SCSI_NAME,
1da177e4 LT	401	.info = sun3scsi_info,
1da177e4 LT	402	.queuecommand = sun3scsi_queue_command,
aa2e2cb1 FT	403	.eh_abort_handler = sun3scsi_abort,
aa2e2cb1 FT	404	.eh_bus_reset_handler = sun3scsi_bus_reset,
d572f65f	405	.can_queue = 16,
1da177e4	406	.this_id = 7,
d572f65f FT	407	.sg_tablesize = SG_NONE,
d572f65f FT	408	.cmd_per_lun = 2,
aa2e2cb1	409	.use_clustering = DISABLE_CLUSTERING,
32b26a10	410	.cmd_size = NCR5380_CMD_SIZE,
1da177e4 LT	411	};
1da177e4 LT	412
0d31f875 FT	413	static int __init sun3_scsi_probe(struct platform_device *pdev)
	414	{
	415	struct Scsi_Host *instance;
820682b1	416	struct NCR5380_hostdata *hostdata;
0d31f875 FT	417	int error;
0d31f875 FT	418	struct resource irq, mem;
61e1ce58	419	void __iomem *ioaddr;
ca513fc9	420	int host_flags = 0;
0d31f875 FT	421	#ifdef SUN3_SCSI_VME
	422	int i;
	423	#endif
	424
	425	if (setup_can_queue > 0)
	426	sun3_scsi_template.can_queue = setup_can_queue;
	427	if (setup_cmd_per_lun > 0)
	428	sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
	429	if (setup_sg_tablesize >= 0)
	430	sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
	431	if (setup_hostid >= 0)
	432	sun3_scsi_template.this_id = setup_hostid & 7;
	433
0d31f875 FT	434	#ifdef SUN3_SCSI_VME
	435	ioaddr = NULL;
	436	for (i = 0; i < 2; i++) {
	437	unsigned char x;
	438
	439	irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	440	mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
	441	if (!irq \|\| !mem)
	442	break;
	443
	444	ioaddr = sun3_ioremap(mem->start, resource_size(mem),
	445	SUN3_PAGE_TYPE_VME16);
	446	dregs = (struct sun3_dma_regs *)(ioaddr + 8);
	447
	448	if (sun3_map_test((unsigned long)dregs, &x)) {
	449	unsigned short oldcsr;
	450
	451	oldcsr = dregs->csr;
	452	dregs->csr = 0;
	453	udelay(SUN3_DMA_DELAY);
	454	if (dregs->csr == 0x1400)
	455	break;
	456
	457	dregs->csr = oldcsr;
	458	}
	459
	460	iounmap(ioaddr);
	461	ioaddr = NULL;
	462	}
	463	if (!ioaddr)
	464	return -ENODEV;
	465	#else
	466	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	467	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	468	if (!irq \|\| !mem)
	469	return -ENODEV;
	470
	471	ioaddr = ioremap(mem->start, resource_size(mem));
	472	dregs = (struct sun3_dma_regs *)(ioaddr + 8);
	473
	474	udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
	475	if (!udc_regs) {
	476	pr_err(PFX "couldn't allocate DVMA memory!\n");
	477	iounmap(ioaddr);
	478	return -ENOMEM;
	479	}
	480	#endif
	481
0d31f875 FT	482	instance = scsi_host_alloc(&sun3_scsi_template,
	483	sizeof(struct NCR5380_hostdata));
	484	if (!instance) {
	485	error = -ENOMEM;
	486	goto fail_alloc;
	487	}
0d31f875	488
0d31f875 FT	489	instance->irq = irq->start;
0d31f875 FT	490
820682b1	491	hostdata = shost_priv(instance);
61e1ce58 FT	492	hostdata->base = mem->start;
61e1ce58 FT	493	hostdata->io = ioaddr;
820682b1	494
0ad0eff9 FT	495	error = NCR5380_init(instance, host_flags);
	496	if (error)
	497	goto fail_init;
0d31f875 FT	498
	499	error = request_irq(instance->irq, scsi_sun3_intr, 0,
	500	"NCR5380", instance);
	501	if (error) {
0d31f875 FT	502	pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
	503	instance->host_no, instance->irq);
	504	goto fail_irq;
0d31f875 FT	505	}
	506
	507	dregs->csr = 0;
	508	udelay(SUN3_DMA_DELAY);
	509	dregs->csr = CSR_SCSI \| CSR_FIFO \| CSR_INTR;
	510	udelay(SUN3_DMA_DELAY);
	511	dregs->fifo_count = 0;
	512	#ifdef SUN3_SCSI_VME
	513	dregs->fifo_count_hi = 0;
	514	dregs->dma_addr_hi = 0;
	515	dregs->dma_addr_lo = 0;
	516	dregs->dma_count_hi = 0;
	517	dregs->dma_count_lo = 0;
	518
	519	dregs->ivect = VME_DATA24 \| (instance->irq & 0xff);
	520	#endif
	521
9c3f0e2b	522	NCR5380_maybe_reset_bus(instance);
0d31f875 FT	523
	524	error = scsi_add_host(instance, NULL);
	525	if (error)
	526	goto fail_host;
	527
	528	platform_set_drvdata(pdev, instance);
	529
	530	scsi_scan_host(instance);
	531	return 0;
	532
	533	fail_host:
e4dec680	534	free_irq(instance->irq, instance);
0d31f875 FT	535	fail_irq:
0d31f875 FT	536	NCR5380_exit(instance);
0ad0eff9	537	fail_init:
0d31f875 FT	538	scsi_host_put(instance);
	539	fail_alloc:
	540	if (udc_regs)
	541	dvma_free(udc_regs);
61e1ce58	542	iounmap(ioaddr);
0d31f875 FT	543	return error;
	544	}
	545
	546	static int __exit sun3_scsi_remove(struct platform_device *pdev)
	547	{
	548	struct Scsi_Host *instance = platform_get_drvdata(pdev);
61e1ce58 FT	549	struct NCR5380_hostdata *hostdata = shost_priv(instance);
61e1ce58 FT	550	void __iomem *ioaddr = hostdata->io;
0d31f875 FT	551
0d31f875 FT	552	scsi_remove_host(instance);
e4dec680	553	free_irq(instance->irq, instance);
0d31f875 FT	554	NCR5380_exit(instance);
	555	scsi_host_put(instance);
	556	if (udc_regs)
	557	dvma_free(udc_regs);
61e1ce58	558	iounmap(ioaddr);
0d31f875 FT	559	return 0;
	560	}
	561
	562	static struct platform_driver sun3_scsi_driver = {
	563	.remove = __exit_p(sun3_scsi_remove),
	564	.driver = {
	565	.name = DRV_MODULE_NAME,
0d31f875 FT	566	},
0d31f875 FT	567	};
1da177e4	568
0d31f875	569	module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
1da177e4	570
0d31f875	571	MODULE_ALIAS("platform:" DRV_MODULE_NAME);
1da177e4	572	MODULE_LICENSE("GPL");