[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / sun_esp.c

/* sun_esp.c: ESP front-end for Sparc SBUS systems.
 *
 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include <asm/irq.h>
#include <asm/io.h>
#include <asm/dma.h>

#include <scsi/scsi_host.h>

#include "esp_scsi.h"

#define DRV_MODULE_NAME		"sun_esp"
#define PFX DRV_MODULE_NAME	": "
#define DRV_VERSION		"1.100"
#define DRV_MODULE_RELDATE	"August 27, 2008"

#define dma_read32(REG) \
	sbus_readl(esp->dma_regs + (REG))
#define dma_write32(VAL, REG) \
	sbus_writel((VAL), esp->dma_regs + (REG))

/* DVMA chip revisions */
enum dvma_rev {
	dvmarev0,
	dvmaesc1,
	dvmarev1,
	dvmarev2,
	dvmarev3,
	dvmarevplus,
	dvmahme
};

static int __devinit esp_sbus_setup_dma(struct esp *esp,
					struct of_device *dma_of)
{
	esp->dma = dma_of;

	esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
				   resource_size(&dma_of->resource[0]),
				   "espdma");
	if (!esp->dma_regs)
		return -ENOMEM;

	switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
	case DMA_VERS0:
		esp->dmarev = dvmarev0;
		break;
	case DMA_ESCV1:
		esp->dmarev = dvmaesc1;
		break;
	case DMA_VERS1:
		esp->dmarev = dvmarev1;
		break;
	case DMA_VERS2:
		esp->dmarev = dvmarev2;
		break;
	case DMA_VERHME:
		esp->dmarev = dvmahme;
		break;
	case DMA_VERSPLUS:
		esp->dmarev = dvmarevplus;
		break;
	}

	return 0;

}

static int __devinit esp_sbus_map_regs(struct esp *esp, int hme)
{
	struct of_device *op = esp->dev;
	struct resource *res;

	/* On HME, two reg sets exist, first is DVMA,
	 * second is ESP registers.
	 */
	if (hme)
		res = &op->resource[1];
	else
		res = &op->resource[0];

	esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
	if (!esp->regs)
		return -ENOMEM;

	return 0;
}

static int __devinit esp_sbus_map_command_block(struct esp *esp)
{
	struct of_device *op = esp->dev;

	esp->command_block = dma_alloc_coherent(&op->dev, 16,
						&esp->command_block_dma,
						GFP_ATOMIC);
	if (!esp->command_block)
		return -ENOMEM;
	return 0;
}

static int __devinit esp_sbus_register_irq(struct esp *esp)
{
	struct Scsi_Host *host = esp->host;
	struct of_device *op = esp->dev;

	host->irq = op->irqs[0];
	return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
}

static void __devinit esp_get_scsi_id(struct esp *esp, struct of_device *espdma)
{
	struct of_device *op = esp->dev;
	struct device_node *dp;

	dp = op->node;
	esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
	if (esp->scsi_id != 0xff)
		goto done;

	esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
	if (esp->scsi_id != 0xff)
		goto done;

	esp->scsi_id = of_getintprop_default(espdma->node,
					     "scsi-initiator-id", 7);

done:
	esp->host->this_id = esp->scsi_id;
	esp->scsi_id_mask = (1 << esp->scsi_id);
}

static void __devinit esp_get_differential(struct esp *esp)
{
	struct of_device *op = esp->dev;
	struct device_node *dp;

	dp = op->node;
	if (of_find_property(dp, "differential", NULL))
		esp->flags |= ESP_FLAG_DIFFERENTIAL;
	else
		esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
}

static void __devinit esp_get_clock_params(struct esp *esp)
{
	struct of_device *op = esp->dev;
	struct device_node *bus_dp, *dp;
	int fmhz;

	dp = op->node;
	bus_dp = dp->parent;

	fmhz = of_getintprop_default(dp, "clock-frequency", 0);
	if (fmhz == 0)
		fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0);

	esp->cfreq = fmhz;
}

static void __devinit esp_get_bursts(struct esp *esp, struct of_device *dma_of)
{
	struct device_node *dma_dp = dma_of->node;
	struct of_device *op = esp->dev;
	struct device_node *dp;
	u8 bursts, val;

	dp = op->node;
	bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
	val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
	if (val != 0xff)
		bursts &= val;

	val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
	if (val != 0xff)
		bursts &= val;

	if (bursts == 0xff ||
	    (bursts & DMA_BURST16) == 0 ||
	    (bursts & DMA_BURST32) == 0)
		bursts = (DMA_BURST32 - 1);

	esp->bursts = bursts;
}

static void __devinit esp_sbus_get_props(struct esp *esp, struct of_device *espdma)
{
	esp_get_scsi_id(esp, espdma);
	esp_get_differential(esp);
	esp_get_clock_params(esp);
	esp_get_bursts(esp, espdma);
}

static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
{
	sbus_writeb(val, esp->regs + (reg * 4UL));
}

static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
{
	return sbus_readb(esp->regs + (reg * 4UL));
}

static dma_addr_t sbus_esp_map_single(struct esp *esp, void *buf,
				      size_t sz, int dir)
{
	struct of_device *op = esp->dev;

	return dma_map_single(&op->dev, buf, sz, dir);
}

static int sbus_esp_map_sg(struct esp *esp, struct scatterlist *sg,
				  int num_sg, int dir)
{
	struct of_device *op = esp->dev;

	return dma_map_sg(&op->dev, sg, num_sg, dir);
}

static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
				  size_t sz, int dir)
{
	struct of_device *op = esp->dev;

	dma_unmap_single(&op->dev, addr, sz, dir);
}

static void sbus_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
			      int num_sg, int dir)
{
	struct of_device *op = esp->dev;

	dma_unmap_sg(&op->dev, sg, num_sg, dir);
}

static int sbus_esp_irq_pending(struct esp *esp)
{
	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
		return 1;
	return 0;
}

static void sbus_esp_reset_dma(struct esp *esp)
{
	int can_do_burst16, can_do_burst32, can_do_burst64;
	int can_do_sbus64, lim;
	struct of_device *op;
	u32 val;

	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
	can_do_burst64 = 0;
	can_do_sbus64 = 0;
	op = esp->dev;
	if (sbus_can_dma_64bit())
		can_do_sbus64 = 1;
	if (sbus_can_burst64())
		can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;

	/* Put the DVMA into a known state. */
	if (esp->dmarev != dvmahme) {
		val = dma_read32(DMA_CSR);
		dma_write32(val | DMA_RST_SCSI, DMA_CSR);
		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	}
	switch (esp->dmarev) {
	case dvmahme:
		dma_write32(DMA_RESET_FAS366, DMA_CSR);
		dma_write32(DMA_RST_SCSI, DMA_CSR);

		esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
					DMA_SCSI_DISAB | DMA_INT_ENAB);

		esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
					  DMA_BRST_SZ);

		if (can_do_burst64)
			esp->prev_hme_dmacsr |= DMA_BRST64;
		else if (can_do_burst32)
			esp->prev_hme_dmacsr |= DMA_BRST32;

		if (can_do_sbus64) {
			esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
			sbus_set_sbus64(&op->dev, esp->bursts);
		}

		lim = 1000;
		while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
			if (--lim == 0) {
				printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
				       "will not clear!\n",
				       esp->host->unique_id);
				break;
			}
			udelay(1);
		}

		dma_write32(0, DMA_CSR);
		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);

		dma_write32(0, DMA_ADDR);
		break;

	case dvmarev2:
		if (esp->rev != ESP100) {
			val = dma_read32(DMA_CSR);
			dma_write32(val | DMA_3CLKS, DMA_CSR);
		}
		break;

	case dvmarev3:
		val = dma_read32(DMA_CSR);
		val &= ~DMA_3CLKS;
		val |= DMA_2CLKS;
		if (can_do_burst32) {
			val &= ~DMA_BRST_SZ;
			val |= DMA_BRST32;
		}
		dma_write32(val, DMA_CSR);
		break;

	case dvmaesc1:
		val = dma_read32(DMA_CSR);
		val |= DMA_ADD_ENABLE;
		val &= ~DMA_BCNT_ENAB;
		if (!can_do_burst32 && can_do_burst16) {
			val |= DMA_ESC_BURST;
		} else {
			val &= ~(DMA_ESC_BURST);
		}
		dma_write32(val, DMA_CSR);
		break;

	default:
		break;
	}

	/* Enable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val | DMA_INT_ENAB, DMA_CSR);
}

static void sbus_esp_dma_drain(struct esp *esp)
{
	u32 csr;
	int lim;

	if (esp->dmarev == dvmahme)
		return;

	csr = dma_read32(DMA_CSR);
	if (!(csr & DMA_FIFO_ISDRAIN))
		return;

	if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
		dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);

	lim = 1000;
	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
		if (--lim == 0) {
			printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
			       esp->host->unique_id);
			break;
		}
		udelay(1);
	}
}

static void sbus_esp_dma_invalidate(struct esp *esp)
{
	if (esp->dmarev == dvmahme) {
		dma_write32(DMA_RST_SCSI, DMA_CSR);

		esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
					 (DMA_PARITY_OFF | DMA_2CLKS |
					  DMA_SCSI_DISAB | DMA_INT_ENAB)) &
					~(DMA_ST_WRITE | DMA_ENABLE));

		dma_write32(0, DMA_CSR);
		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);

		/* This is necessary to avoid having the SCSI channel
		 * engine lock up on us.
		 */
		dma_write32(0, DMA_ADDR);
	} else {
		u32 val;
		int lim;

		lim = 1000;
		while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
			if (--lim == 0) {
				printk(KERN_ALERT PFX "esp%d: DMA will not "
				       "invalidate!\n", esp->host->unique_id);
				break;
			}
			udelay(1);
		}

		val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
		val |= DMA_FIFO_INV;
		dma_write32(val, DMA_CSR);
		val &= ~DMA_FIFO_INV;
		dma_write32(val, DMA_CSR);
	}
}

static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
				  u32 dma_count, int write, u8 cmd)
{
	u32 csr;

	BUG_ON(!(cmd & ESP_CMD_DMA));

	sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	if (esp->rev == FASHME) {
		sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
		sbus_esp_write8(esp, 0, FAS_RHI);

		scsi_esp_cmd(esp, cmd);

		csr = esp->prev_hme_dmacsr;
		csr |= DMA_SCSI_DISAB | DMA_ENABLE;
		if (write)
			csr |= DMA_ST_WRITE;
		else
			csr &= ~DMA_ST_WRITE;
		esp->prev_hme_dmacsr = csr;

		dma_write32(dma_count, DMA_COUNT);
		dma_write32(addr, DMA_ADDR);
		dma_write32(csr, DMA_CSR);
	} else {
		csr = dma_read32(DMA_CSR);
		csr |= DMA_ENABLE;
		if (write)
			csr |= DMA_ST_WRITE;
		else
			csr &= ~DMA_ST_WRITE;
		dma_write32(csr, DMA_CSR);
		if (esp->dmarev == dvmaesc1) {
			u32 end = PAGE_ALIGN(addr + dma_count + 16U);
			dma_write32(end - addr, DMA_COUNT);
		}
		dma_write32(addr, DMA_ADDR);

		scsi_esp_cmd(esp, cmd);
	}

}

static int sbus_esp_dma_error(struct esp *esp)
{
	u32 csr = dma_read32(DMA_CSR);

	if (csr & DMA_HNDL_ERROR)
		return 1;

	return 0;
}

static const struct esp_driver_ops sbus_esp_ops = {
	.esp_write8	=	sbus_esp_write8,
	.esp_read8	=	sbus_esp_read8,
	.map_single	=	sbus_esp_map_single,
	.map_sg		=	sbus_esp_map_sg,
	.unmap_single	=	sbus_esp_unmap_single,
	.unmap_sg	=	sbus_esp_unmap_sg,
	.irq_pending	=	sbus_esp_irq_pending,
	.reset_dma	=	sbus_esp_reset_dma,
	.dma_drain	=	sbus_esp_dma_drain,
	.dma_invalidate	=	sbus_esp_dma_invalidate,
	.send_dma_cmd	=	sbus_esp_send_dma_cmd,
	.dma_error	=	sbus_esp_dma_error,
};

static int __devinit esp_sbus_probe_one(struct of_device *op,
					struct of_device *espdma,
					int hme)
{
	struct scsi_host_template *tpnt = &scsi_esp_template;
	struct Scsi_Host *host;
	struct esp *esp;
	int err;

	host = scsi_host_alloc(tpnt, sizeof(struct esp));

	err = -ENOMEM;
	if (!host)
		goto fail;

	host->max_id = (hme ? 16 : 8);
	esp = shost_priv(host);

	esp->host = host;
	esp->dev = op;
	esp->ops = &sbus_esp_ops;

	if (hme)
		esp->flags |= ESP_FLAG_WIDE_CAPABLE;

	err = esp_sbus_setup_dma(esp, espdma);
	if (err < 0)
		goto fail_unlink;

	err = esp_sbus_map_regs(esp, hme);
	if (err < 0)
		goto fail_unlink;

	err = esp_sbus_map_command_block(esp);
	if (err < 0)
		goto fail_unmap_regs;

	err = esp_sbus_register_irq(esp);
	if (err < 0)
		goto fail_unmap_command_block;

	esp_sbus_get_props(esp, espdma);

	/* Before we try to touch the ESP chip, ESC1 dma can
	 * come up with the reset bit set, so make sure that
	 * is clear first.
	 */
	if (esp->dmarev == dvmaesc1) {
		u32 val = dma_read32(DMA_CSR);

		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	}

	dev_set_drvdata(&op->dev, esp);

	err = scsi_esp_register(esp, &op->dev);
	if (err)
		goto fail_free_irq;

	return 0;

fail_free_irq:
	free_irq(host->irq, esp);
fail_unmap_command_block:
	dma_free_coherent(&op->dev, 16,
			  esp->command_block,
			  esp->command_block_dma);
fail_unmap_regs:
	of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE);
fail_unlink:
	scsi_host_put(host);
fail:
	return err;
}

static int __devinit esp_sbus_probe(struct of_device *op, const struct of_device_id *match)
{
	struct device_node *dma_node = NULL;
	struct device_node *dp = op->node;
	struct of_device *dma_of = NULL;
	int hme = 0;

	if (dp->parent &&
	    (!strcmp(dp->parent->name, "espdma") ||
	     !strcmp(dp->parent->name, "dma")))
		dma_node = dp->parent;
	else if (!strcmp(dp->name, "SUNW,fas")) {
		dma_node = op->node;
		hme = 1;
	}
	if (dma_node)
		dma_of = of_find_device_by_node(dma_node);
	if (!dma_of)
		return -ENODEV;

	return esp_sbus_probe_one(op, dma_of, hme);
}

static int __devexit esp_sbus_remove(struct of_device *op)
{
	struct esp *esp = dev_get_drvdata(&op->dev);
	struct of_device *dma_of = esp->dma;
	unsigned int irq = esp->host->irq;
	bool is_hme;
	u32 val;

	scsi_esp_unregister(esp);

	/* Disable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);

	free_irq(irq, esp);

	is_hme = (esp->dmarev == dvmahme);

	dma_free_coherent(&op->dev, 16,
			  esp->command_block,
			  esp->command_block_dma);
	of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs,
		   SBUS_ESP_REG_SIZE);
	of_iounmap(&dma_of->resource[0], esp->dma_regs,
		   resource_size(&dma_of->resource[0]));

	scsi_host_put(esp->host);

	dev_set_drvdata(&op->dev, NULL);

	return 0;
}

static const struct of_device_id esp_match[] = {
	{
		.name = "SUNW,esp",
	},
	{
		.name = "SUNW,fas",
	},
	{
		.name = "esp",
	},
	{},
};
MODULE_DEVICE_TABLE(of, esp_match);

static struct of_platform_driver esp_sbus_driver = {
	.name		= "esp",
	.match_table	= esp_match,
	.probe		= esp_sbus_probe,
	.remove		= __devexit_p(esp_sbus_remove),
};

static int __init sunesp_init(void)
{
	return of_register_driver(&esp_sbus_driver, &of_bus_type);
}

static void __exit sunesp_exit(void)
{
	of_unregister_driver(&esp_sbus_driver);
}

MODULE_DESCRIPTION("Sun ESP SCSI driver");
MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

module_init(sunesp_init);
module_exit(sunesp_exit);
Commit	Line	Data
cd9ad58d DM	1	/* sun_esp.c: ESP front-end for Sparc SBUS systems.
cd9ad58d DM	2	*
334ae614	3	* Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
cd9ad58d DM	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/types.h>
6025dfe5	8	#include <linux/delay.h>
cd9ad58d	9	#include <linux/module.h>
27ac792c	10	#include <linux/mm.h>
cd9ad58d	11	#include <linux/init.h>
738f2b7b	12	#include <linux/dma-mapping.h>
05bb5e93 DM	13	#include <linux/of.h>
05bb5e93 DM	14	#include <linux/of_device.h>
cd9ad58d DM	15
	16	#include <asm/irq.h>
	17	#include <asm/io.h>
	18	#include <asm/dma.h>
	19
cd9ad58d DM	20	#include <scsi/scsi_host.h>
	21
	22	#include "esp_scsi.h"
	23
	24	#define DRV_MODULE_NAME "sun_esp"
	25	#define PFX DRV_MODULE_NAME ": "
05bb5e93 DM	26	#define DRV_VERSION "1.100"
05bb5e93 DM	27	#define DRV_MODULE_RELDATE "August 27, 2008"
cd9ad58d DM	28
	29	#define dma_read32(REG) \
	30	sbus_readl(esp->dma_regs + (REG))
	31	#define dma_write32(VAL, REG) \
	32	sbus_writel((VAL), esp->dma_regs + (REG))
	33
334ae614 DM	34	/* DVMA chip revisions */
	35	enum dvma_rev {
	36	dvmarev0,
	37	dvmaesc1,
	38	dvmarev1,
	39	dvmarev2,
	40	dvmarev3,
	41	dvmarevplus,
	42	dvmahme
	43	};
cd9ad58d	44
334ae614 DM	45	static int __devinit esp_sbus_setup_dma(struct esp *esp,
	46	struct of_device *dma_of)
	47	{
	48	esp->dma = dma_of;
cd9ad58d	49
334ae614 DM	50	esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
	51	resource_size(&dma_of->resource[0]),
	52	"espdma");
	53	if (!esp->dma_regs)
	54	return -ENOMEM;
cd9ad58d	55
334ae614 DM	56	switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
	57	case DMA_VERS0:
	58	esp->dmarev = dvmarev0;
	59	break;
	60	case DMA_ESCV1:
	61	esp->dmarev = dvmaesc1;
	62	break;
	63	case DMA_VERS1:
	64	esp->dmarev = dvmarev1;
	65	break;
	66	case DMA_VERS2:
	67	esp->dmarev = dvmarev2;
	68	break;
	69	case DMA_VERHME:
	70	esp->dmarev = dvmahme;
	71	break;
	72	case DMA_VERSPLUS:
	73	esp->dmarev = dvmarevplus;
	74	break;
cd9ad58d	75	}
cd9ad58d DM	76
	77	return 0;
	78
	79	}
	80
	81	static int __devinit esp_sbus_map_regs(struct esp *esp, int hme)
	82	{
05bb5e93	83	struct of_device *op = esp->dev;
cd9ad58d DM	84	struct resource *res;
	85
	86	/* On HME, two reg sets exist, first is DVMA,
	87	* second is ESP registers.
	88	*/
	89	if (hme)
05bb5e93	90	res = &op->resource[1];
cd9ad58d	91	else
05bb5e93	92	res = &op->resource[0];
cd9ad58d	93
05bb5e93	94	esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
cd9ad58d DM	95	if (!esp->regs)
	96	return -ENOMEM;
	97
	98	return 0;
	99	}
	100
	101	static int __devinit esp_sbus_map_command_block(struct esp *esp)
	102	{
05bb5e93	103	struct of_device *op = esp->dev;
cd9ad58d	104
05bb5e93	105	esp->command_block = dma_alloc_coherent(&op->dev, 16,
738f2b7b DM	106	&esp->command_block_dma,
738f2b7b DM	107	GFP_ATOMIC);
cd9ad58d DM	108	if (!esp->command_block)
	109	return -ENOMEM;
	110	return 0;
	111	}
	112
	113	static int __devinit esp_sbus_register_irq(struct esp *esp)
	114	{
	115	struct Scsi_Host *host = esp->host;
05bb5e93	116	struct of_device *op = esp->dev;
cd9ad58d	117
05bb5e93	118	host->irq = op->irqs[0];
cd9ad58d DM	119	return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
	120	}
	121
05bb5e93	122	static void __devinit esp_get_scsi_id(struct esp esp, struct of_device espdma)
cd9ad58d	123	{
05bb5e93 DM	124	struct of_device *op = esp->dev;
05bb5e93 DM	125	struct device_node *dp;
cd9ad58d	126
05bb5e93	127	dp = op->node;
cd9ad58d DM	128	esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
	129	if (esp->scsi_id != 0xff)
	130	goto done;
	131
	132	esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
	133	if (esp->scsi_id != 0xff)
	134	goto done;
	135
05bb5e93	136	esp->scsi_id = of_getintprop_default(espdma->node,
cd9ad58d DM	137	"scsi-initiator-id", 7);
	138
	139	done:
	140	esp->host->this_id = esp->scsi_id;
	141	esp->scsi_id_mask = (1 << esp->scsi_id);
	142	}
	143
	144	static void __devinit esp_get_differential(struct esp *esp)
	145	{
05bb5e93 DM	146	struct of_device *op = esp->dev;
05bb5e93 DM	147	struct device_node *dp;
cd9ad58d	148
05bb5e93	149	dp = op->node;
cd9ad58d DM	150	if (of_find_property(dp, "differential", NULL))
	151	esp->flags \|= ESP_FLAG_DIFFERENTIAL;
	152	else
	153	esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
	154	}
	155
	156	static void __devinit esp_get_clock_params(struct esp *esp)
	157	{
05bb5e93 DM	158	struct of_device *op = esp->dev;
05bb5e93 DM	159	struct device_node bus_dp, dp;
cd9ad58d DM	160	int fmhz;
cd9ad58d DM	161
05bb5e93 DM	162	dp = op->node;
05bb5e93 DM	163	bus_dp = dp->parent;
cd9ad58d DM	164
	165	fmhz = of_getintprop_default(dp, "clock-frequency", 0);
	166	if (fmhz == 0)
05bb5e93	167	fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0);
cd9ad58d DM	168
	169	esp->cfreq = fmhz;
	170	}
	171
334ae614	172	static void __devinit esp_get_bursts(struct esp esp, struct of_device dma_of)
cd9ad58d	173	{
334ae614	174	struct device_node *dma_dp = dma_of->node;
05bb5e93	175	struct of_device *op = esp->dev;
334ae614 DM	176	struct device_node *dp;
334ae614 DM	177	u8 bursts, val;
cd9ad58d	178
05bb5e93	179	dp = op->node;
cd9ad58d	180	bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
334ae614 DM	181	val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
	182	if (val != 0xff)
	183	bursts &= val;
cd9ad58d	184
05bb5e93 DM	185	val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
	186	if (val != 0xff)
	187	bursts &= val;
cd9ad58d DM	188
	189	if (bursts == 0xff \|\|
	190	(bursts & DMA_BURST16) == 0 \|\|
	191	(bursts & DMA_BURST32) == 0)
	192	bursts = (DMA_BURST32 - 1);
	193
	194	esp->bursts = bursts;
	195	}
	196
334ae614	197	static void __devinit esp_sbus_get_props(struct esp esp, struct of_device espdma)
cd9ad58d	198	{
05bb5e93	199	esp_get_scsi_id(esp, espdma);
cd9ad58d DM	200	esp_get_differential(esp);
	201	esp_get_clock_params(esp);
	202	esp_get_bursts(esp, espdma);
	203	}
	204
	205	static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
	206	{
	207	sbus_writeb(val, esp->regs + (reg * 4UL));
	208	}
	209
	210	static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
	211	{
	212	return sbus_readb(esp->regs + (reg * 4UL));
	213	}
	214
	215	static dma_addr_t sbus_esp_map_single(struct esp esp, void buf,
	216	size_t sz, int dir)
	217	{
05bb5e93	218	struct of_device *op = esp->dev;
7a715f46	219
05bb5e93	220	return dma_map_single(&op->dev, buf, sz, dir);
cd9ad58d DM	221	}
	222
	223	static int sbus_esp_map_sg(struct esp esp, struct scatterlist sg,
	224	int num_sg, int dir)
	225	{
05bb5e93	226	struct of_device *op = esp->dev;
7a715f46	227
05bb5e93	228	return dma_map_sg(&op->dev, sg, num_sg, dir);
cd9ad58d DM	229	}
	230
	231	static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
	232	size_t sz, int dir)
	233	{
05bb5e93	234	struct of_device *op = esp->dev;
7a715f46	235
05bb5e93	236	dma_unmap_single(&op->dev, addr, sz, dir);
cd9ad58d DM	237	}
	238
	239	static void sbus_esp_unmap_sg(struct esp esp, struct scatterlist sg,
	240	int num_sg, int dir)
	241	{
05bb5e93	242	struct of_device *op = esp->dev;
7a715f46	243
05bb5e93	244	dma_unmap_sg(&op->dev, sg, num_sg, dir);
cd9ad58d DM	245	}
	246
	247	static int sbus_esp_irq_pending(struct esp *esp)
	248	{
	249	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR \| DMA_HNDL_ERROR))
	250	return 1;
	251	return 0;
	252	}
	253
	254	static void sbus_esp_reset_dma(struct esp *esp)
	255	{
	256	int can_do_burst16, can_do_burst32, can_do_burst64;
	257	int can_do_sbus64, lim;
05bb5e93	258	struct of_device *op;
cd9ad58d DM	259	u32 val;
	260
	261	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
	262	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
	263	can_do_burst64 = 0;
	264	can_do_sbus64 = 0;
05bb5e93	265	op = esp->dev;
63237eeb	266	if (sbus_can_dma_64bit())
cd9ad58d	267	can_do_sbus64 = 1;
63237eeb	268	if (sbus_can_burst64())
cd9ad58d DM	269	can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
	270
	271	/* Put the DVMA into a known state. */
334ae614	272	if (esp->dmarev != dvmahme) {
cd9ad58d DM	273	val = dma_read32(DMA_CSR);
	274	dma_write32(val \| DMA_RST_SCSI, DMA_CSR);
	275	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	276	}
334ae614	277	switch (esp->dmarev) {
cd9ad58d DM	278	case dvmahme:
	279	dma_write32(DMA_RESET_FAS366, DMA_CSR);
	280	dma_write32(DMA_RST_SCSI, DMA_CSR);
	281
	282	esp->prev_hme_dmacsr = (DMA_PARITY_OFF \| DMA_2CLKS \|
	283	DMA_SCSI_DISAB \| DMA_INT_ENAB);
	284
	285	esp->prev_hme_dmacsr &= ~(DMA_ENABLE \| DMA_ST_WRITE \|
	286	DMA_BRST_SZ);
	287
	288	if (can_do_burst64)
	289	esp->prev_hme_dmacsr \|= DMA_BRST64;
	290	else if (can_do_burst32)
	291	esp->prev_hme_dmacsr \|= DMA_BRST32;
	292
	293	if (can_do_sbus64) {
	294	esp->prev_hme_dmacsr \|= DMA_SCSI_SBUS64;
05bb5e93	295	sbus_set_sbus64(&op->dev, esp->bursts);
cd9ad58d DM	296	}
	297
	298	lim = 1000;
	299	while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
	300	if (--lim == 0) {
	301	printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
	302	"will not clear!\n",
	303	esp->host->unique_id);
	304	break;
	305	}
	306	udelay(1);
	307	}
	308
	309	dma_write32(0, DMA_CSR);
	310	dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
	311
	312	dma_write32(0, DMA_ADDR);
	313	break;
	314
	315	case dvmarev2:
	316	if (esp->rev != ESP100) {
	317	val = dma_read32(DMA_CSR);
	318	dma_write32(val \| DMA_3CLKS, DMA_CSR);
	319	}
	320	break;
	321
	322	case dvmarev3:
	323	val = dma_read32(DMA_CSR);
	324	val &= ~DMA_3CLKS;
	325	val \|= DMA_2CLKS;
	326	if (can_do_burst32) {
	327	val &= ~DMA_BRST_SZ;
	328	val \|= DMA_BRST32;
	329	}
	330	dma_write32(val, DMA_CSR);
	331	break;
	332
	333	case dvmaesc1:
	334	val = dma_read32(DMA_CSR);
	335	val \|= DMA_ADD_ENABLE;
	336	val &= ~DMA_BCNT_ENAB;
	337	if (!can_do_burst32 && can_do_burst16) {
	338	val \|= DMA_ESC_BURST;
	339	} else {
	340	val &= ~(DMA_ESC_BURST);
	341	}
	342	dma_write32(val, DMA_CSR);
	343	break;
	344
	345	default:
	346	break;
	347	}
	348
	349	/* Enable interrupts. */
	350	val = dma_read32(DMA_CSR);
	351	dma_write32(val \| DMA_INT_ENAB, DMA_CSR);
	352	}
	353
	354	static void sbus_esp_dma_drain(struct esp *esp)
	355	{
	356	u32 csr;
	357	int lim;
	358
334ae614	359	if (esp->dmarev == dvmahme)
cd9ad58d DM	360	return;
	361
	362	csr = dma_read32(DMA_CSR);
	363	if (!(csr & DMA_FIFO_ISDRAIN))
	364	return;
	365
334ae614	366	if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
cd9ad58d DM	367	dma_write32(csr \| DMA_FIFO_STDRAIN, DMA_CSR);
	368
	369	lim = 1000;
	370	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
	371	if (--lim == 0) {
	372	printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
	373	esp->host->unique_id);
	374	break;
	375	}
	376	udelay(1);
	377	}
	378	}
	379
	380	static void sbus_esp_dma_invalidate(struct esp *esp)
	381	{
334ae614	382	if (esp->dmarev == dvmahme) {
cd9ad58d DM	383	dma_write32(DMA_RST_SCSI, DMA_CSR);
	384
	385	esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr \|
	386	(DMA_PARITY_OFF \| DMA_2CLKS \|
	387	DMA_SCSI_DISAB \| DMA_INT_ENAB)) &
	388	~(DMA_ST_WRITE \| DMA_ENABLE));
	389
	390	dma_write32(0, DMA_CSR);
	391	dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
	392
	393	/* This is necessary to avoid having the SCSI channel
	394	* engine lock up on us.
	395	*/
	396	dma_write32(0, DMA_ADDR);
	397	} else {
	398	u32 val;
	399	int lim;
	400
	401	lim = 1000;
	402	while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
	403	if (--lim == 0) {
	404	printk(KERN_ALERT PFX "esp%d: DMA will not "
	405	"invalidate!\n", esp->host->unique_id);
	406	break;
	407	}
	408	udelay(1);
	409	}
	410
	411	val &= ~(DMA_ENABLE \| DMA_ST_WRITE \| DMA_BCNT_ENAB);
	412	val \|= DMA_FIFO_INV;
	413	dma_write32(val, DMA_CSR);
	414	val &= ~DMA_FIFO_INV;
	415	dma_write32(val, DMA_CSR);
	416	}
	417	}
	418
	419	static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
	420	u32 dma_count, int write, u8 cmd)
	421	{
	422	u32 csr;
	423
	424	BUG_ON(!(cmd & ESP_CMD_DMA));
	425
	426	sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	427	sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	428	if (esp->rev == FASHME) {
	429	sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
	430	sbus_esp_write8(esp, 0, FAS_RHI);
	431
	432	scsi_esp_cmd(esp, cmd);
	433
	434	csr = esp->prev_hme_dmacsr;
	435	csr \|= DMA_SCSI_DISAB \| DMA_ENABLE;
	436	if (write)
	437	csr \|= DMA_ST_WRITE;
	438	else
	439	csr &= ~DMA_ST_WRITE;
	440	esp->prev_hme_dmacsr = csr;
	441
	442	dma_write32(dma_count, DMA_COUNT);
	443	dma_write32(addr, DMA_ADDR);
	444	dma_write32(csr, DMA_CSR);
	445	} else {
	446	csr = dma_read32(DMA_CSR);
447	csr \|= DMA_ENABLE;
448	if (write)
449	csr \|= DMA_ST_WRITE;
450	else
451	csr &= ~DMA_ST_WRITE;
452	dma_write32(csr, DMA_CSR);
334ae614	453	if (esp->dmarev == dvmaesc1) {
cd9ad58d DM	454	u32 end = PAGE_ALIGN(addr + dma_count + 16U);
	455	dma_write32(end - addr, DMA_COUNT);
	456	}
	457	dma_write32(addr, DMA_ADDR);
	458
	459	scsi_esp_cmd(esp, cmd);
	460	}
	461
	462	}
	463
	464	static int sbus_esp_dma_error(struct esp *esp)
	465	{
	466	u32 csr = dma_read32(DMA_CSR);
	467
	468	if (csr & DMA_HNDL_ERROR)
	469	return 1;
	470
	471	return 0;
	472	}
	473
	474	static const struct esp_driver_ops sbus_esp_ops = {
	475	.esp_write8 = sbus_esp_write8,
	476	.esp_read8 = sbus_esp_read8,
	477	.map_single = sbus_esp_map_single,
	478	.map_sg = sbus_esp_map_sg,
	479	.unmap_single = sbus_esp_unmap_single,
	480	.unmap_sg = sbus_esp_unmap_sg,
	481	.irq_pending = sbus_esp_irq_pending,
	482	.reset_dma = sbus_esp_reset_dma,
	483	.dma_drain = sbus_esp_dma_drain,
	484	.dma_invalidate = sbus_esp_dma_invalidate,
	485	.send_dma_cmd = sbus_esp_send_dma_cmd,
	486	.dma_error = sbus_esp_dma_error,
	487	};
	488
05bb5e93	489	static int __devinit esp_sbus_probe_one(struct of_device *op,
334ae614	490	struct of_device *espdma,
cd9ad58d DM	491	int hme)
	492	{
	493	struct scsi_host_template *tpnt = &scsi_esp_template;
	494	struct Scsi_Host *host;
	495	struct esp *esp;
	496	int err;
	497
	498	host = scsi_host_alloc(tpnt, sizeof(struct esp));
	499
	500	err = -ENOMEM;
	501	if (!host)
	502	goto fail;
	503
	504	host->max_id = (hme ? 16 : 8);
2b14ec78	505	esp = shost_priv(host);
cd9ad58d DM	506
cd9ad58d DM	507	esp->host = host;
05bb5e93	508	esp->dev = op;
cd9ad58d DM	509	esp->ops = &sbus_esp_ops;
	510
	511	if (hme)
	512	esp->flags \|= ESP_FLAG_WIDE_CAPABLE;
	513
334ae614	514	err = esp_sbus_setup_dma(esp, espdma);
cd9ad58d DM	515	if (err < 0)
	516	goto fail_unlink;
	517
	518	err = esp_sbus_map_regs(esp, hme);
	519	if (err < 0)
	520	goto fail_unlink;
	521
	522	err = esp_sbus_map_command_block(esp);
	523	if (err < 0)
	524	goto fail_unmap_regs;
	525
	526	err = esp_sbus_register_irq(esp);
	527	if (err < 0)
	528	goto fail_unmap_command_block;
	529
	530	esp_sbus_get_props(esp, espdma);
	531
	532	/* Before we try to touch the ESP chip, ESC1 dma can
	533	* come up with the reset bit set, so make sure that
	534	* is clear first.
	535	*/
334ae614	536	if (esp->dmarev == dvmaesc1) {
cd9ad58d DM	537	u32 val = dma_read32(DMA_CSR);
	538
	539	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	540	}
	541
05bb5e93	542	dev_set_drvdata(&op->dev, esp);
cd9ad58d	543
05bb5e93	544	err = scsi_esp_register(esp, &op->dev);
cd9ad58d DM	545	if (err)
	546	goto fail_free_irq;
	547
	548	return 0;
	549
	550	fail_free_irq:
	551	free_irq(host->irq, esp);
	552	fail_unmap_command_block:
05bb5e93	553	dma_free_coherent(&op->dev, 16,
738f2b7b DM	554	esp->command_block,
738f2b7b DM	555	esp->command_block_dma);
cd9ad58d	556	fail_unmap_regs:
05bb5e93	557	of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE);
cd9ad58d DM	558	fail_unlink:
	559	scsi_host_put(host);
	560	fail:
	561	return err;
	562	}
	563
05bb5e93	564	static int __devinit esp_sbus_probe(struct of_device op, const struct of_device_id match)
cd9ad58d	565	{
334ae614	566	struct device_node *dma_node = NULL;
05bb5e93	567	struct device_node *dp = op->node;
334ae614	568	struct of_device *dma_of = NULL;
cd9ad58d DM	569	int hme = 0;
	570
	571	if (dp->parent &&
	572	(!strcmp(dp->parent->name, "espdma") \|\|
	573	!strcmp(dp->parent->name, "dma")))
334ae614	574	dma_node = dp->parent;
cd9ad58d	575	else if (!strcmp(dp->name, "SUNW,fas")) {
05bb5e93	576	dma_node = op->node;
cd9ad58d DM	577	hme = 1;
cd9ad58d DM	578	}
334ae614 DM	579	if (dma_node)
	580	dma_of = of_find_device_by_node(dma_node);
	581	if (!dma_of)
	582	return -ENODEV;
cd9ad58d	583
05bb5e93	584	return esp_sbus_probe_one(op, dma_of, hme);
cd9ad58d DM	585	}
cd9ad58d DM	586
05bb5e93	587	static int __devexit esp_sbus_remove(struct of_device *op)
cd9ad58d	588	{
05bb5e93	589	struct esp *esp = dev_get_drvdata(&op->dev);
334ae614	590	struct of_device *dma_of = esp->dma;
cd9ad58d	591	unsigned int irq = esp->host->irq;
05bb5e93	592	bool is_hme;
cd9ad58d DM	593	u32 val;
	594
	595	scsi_esp_unregister(esp);
	596
	597	/* Disable interrupts. */
	598	val = dma_read32(DMA_CSR);
	599	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
	600
	601	free_irq(irq, esp);
05bb5e93 DM	602
	603	is_hme = (esp->dmarev == dvmahme);
	604
	605	dma_free_coherent(&op->dev, 16,
738f2b7b DM	606	esp->command_block,
738f2b7b DM	607	esp->command_block_dma);
05bb5e93 DM	608	of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs,
05bb5e93 DM	609	SBUS_ESP_REG_SIZE);
334ae614 DM	610	of_iounmap(&dma_of->resource[0], esp->dma_regs,
334ae614 DM	611	resource_size(&dma_of->resource[0]));
cd9ad58d DM	612
	613	scsi_host_put(esp->host);
	614
05bb5e93 DM	615	dev_set_drvdata(&op->dev, NULL);
05bb5e93 DM	616
cd9ad58d DM	617	return 0;
	618	}
	619
fd098316	620	static const struct of_device_id esp_match[] = {
cd9ad58d DM	621	{
	622	.name = "SUNW,esp",
	623	},
	624	{
	625	.name = "SUNW,fas",
	626	},
	627	{
	628	.name = "esp",
	629	},
	630	{},
	631	};
	632	MODULE_DEVICE_TABLE(of, esp_match);
	633
	634	static struct of_platform_driver esp_sbus_driver = {
	635	.name = "esp",
	636	.match_table = esp_match,
	637	.probe = esp_sbus_probe,
	638	.remove = __devexit_p(esp_sbus_remove),
	639	};
	640
	641	static int __init sunesp_init(void)
	642	{
05bb5e93	643	return of_register_driver(&esp_sbus_driver, &of_bus_type);
cd9ad58d DM	644	}
	645
	646	static void __exit sunesp_exit(void)
	647	{
	648	of_unregister_driver(&esp_sbus_driver);
	649	}
	650
	651	MODULE_DESCRIPTION("Sun ESP SCSI driver");
	652	MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
	653	MODULE_LICENSE("GPL");
	654	MODULE_VERSION(DRV_VERSION);
	655
	656	module_init(sunesp_init);
	657	module_exit(sunesp_exit);