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cd9ad58d DM |
1 | /* sun_esp.c: ESP front-end for Sparc SBUS systems. |
2 | * | |
334ae614 | 3 | * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net) |
cd9ad58d DM |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/types.h> | |
6025dfe5 | 8 | #include <linux/delay.h> |
cd9ad58d | 9 | #include <linux/module.h> |
27ac792c | 10 | #include <linux/mm.h> |
cd9ad58d DM |
11 | #include <linux/init.h> |
12 | ||
13 | #include <asm/irq.h> | |
14 | #include <asm/io.h> | |
15 | #include <asm/dma.h> | |
16 | ||
17 | #include <asm/sbus.h> | |
18 | ||
19 | #include <scsi/scsi_host.h> | |
20 | ||
21 | #include "esp_scsi.h" | |
22 | ||
23 | #define DRV_MODULE_NAME "sun_esp" | |
24 | #define PFX DRV_MODULE_NAME ": " | |
25 | #define DRV_VERSION "1.000" | |
26 | #define DRV_MODULE_RELDATE "April 19, 2007" | |
27 | ||
28 | #define dma_read32(REG) \ | |
29 | sbus_readl(esp->dma_regs + (REG)) | |
30 | #define dma_write32(VAL, REG) \ | |
31 | sbus_writel((VAL), esp->dma_regs + (REG)) | |
32 | ||
334ae614 DM |
33 | /* DVMA chip revisions */ |
34 | enum dvma_rev { | |
35 | dvmarev0, | |
36 | dvmaesc1, | |
37 | dvmarev1, | |
38 | dvmarev2, | |
39 | dvmarev3, | |
40 | dvmarevplus, | |
41 | dvmahme | |
42 | }; | |
cd9ad58d | 43 | |
334ae614 DM |
44 | static int __devinit esp_sbus_setup_dma(struct esp *esp, |
45 | struct of_device *dma_of) | |
46 | { | |
47 | esp->dma = dma_of; | |
cd9ad58d | 48 | |
334ae614 DM |
49 | esp->dma_regs = of_ioremap(&dma_of->resource[0], 0, |
50 | resource_size(&dma_of->resource[0]), | |
51 | "espdma"); | |
52 | if (!esp->dma_regs) | |
53 | return -ENOMEM; | |
cd9ad58d | 54 | |
334ae614 DM |
55 | switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) { |
56 | case DMA_VERS0: | |
57 | esp->dmarev = dvmarev0; | |
58 | break; | |
59 | case DMA_ESCV1: | |
60 | esp->dmarev = dvmaesc1; | |
61 | break; | |
62 | case DMA_VERS1: | |
63 | esp->dmarev = dvmarev1; | |
64 | break; | |
65 | case DMA_VERS2: | |
66 | esp->dmarev = dvmarev2; | |
67 | break; | |
68 | case DMA_VERHME: | |
69 | esp->dmarev = dvmahme; | |
70 | break; | |
71 | case DMA_VERSPLUS: | |
72 | esp->dmarev = dvmarevplus; | |
73 | break; | |
cd9ad58d | 74 | } |
cd9ad58d DM |
75 | |
76 | return 0; | |
77 | ||
78 | } | |
79 | ||
80 | static int __devinit esp_sbus_map_regs(struct esp *esp, int hme) | |
81 | { | |
82 | struct sbus_dev *sdev = esp->dev; | |
83 | struct resource *res; | |
84 | ||
85 | /* On HME, two reg sets exist, first is DVMA, | |
86 | * second is ESP registers. | |
87 | */ | |
88 | if (hme) | |
89 | res = &sdev->resource[1]; | |
90 | else | |
91 | res = &sdev->resource[0]; | |
92 | ||
93 | esp->regs = sbus_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP"); | |
94 | if (!esp->regs) | |
95 | return -ENOMEM; | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | static int __devinit esp_sbus_map_command_block(struct esp *esp) | |
101 | { | |
102 | struct sbus_dev *sdev = esp->dev; | |
103 | ||
104 | esp->command_block = sbus_alloc_consistent(sdev, 16, | |
105 | &esp->command_block_dma); | |
106 | if (!esp->command_block) | |
107 | return -ENOMEM; | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static int __devinit esp_sbus_register_irq(struct esp *esp) | |
112 | { | |
113 | struct Scsi_Host *host = esp->host; | |
114 | struct sbus_dev *sdev = esp->dev; | |
115 | ||
116 | host->irq = sdev->irqs[0]; | |
117 | return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp); | |
118 | } | |
119 | ||
120 | static void __devinit esp_get_scsi_id(struct esp *esp) | |
121 | { | |
122 | struct sbus_dev *sdev = esp->dev; | |
123 | struct device_node *dp = sdev->ofdev.node; | |
124 | ||
125 | esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff); | |
126 | if (esp->scsi_id != 0xff) | |
127 | goto done; | |
128 | ||
129 | esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff); | |
130 | if (esp->scsi_id != 0xff) | |
131 | goto done; | |
132 | ||
133 | if (!sdev->bus) { | |
134 | /* SUN4 */ | |
135 | esp->scsi_id = 7; | |
136 | goto done; | |
137 | } | |
138 | ||
139 | esp->scsi_id = of_getintprop_default(sdev->bus->ofdev.node, | |
140 | "scsi-initiator-id", 7); | |
141 | ||
142 | done: | |
143 | esp->host->this_id = esp->scsi_id; | |
144 | esp->scsi_id_mask = (1 << esp->scsi_id); | |
145 | } | |
146 | ||
147 | static void __devinit esp_get_differential(struct esp *esp) | |
148 | { | |
149 | struct sbus_dev *sdev = esp->dev; | |
150 | struct device_node *dp = sdev->ofdev.node; | |
151 | ||
152 | if (of_find_property(dp, "differential", NULL)) | |
153 | esp->flags |= ESP_FLAG_DIFFERENTIAL; | |
154 | else | |
155 | esp->flags &= ~ESP_FLAG_DIFFERENTIAL; | |
156 | } | |
157 | ||
158 | static void __devinit esp_get_clock_params(struct esp *esp) | |
159 | { | |
160 | struct sbus_dev *sdev = esp->dev; | |
161 | struct device_node *dp = sdev->ofdev.node; | |
162 | struct device_node *bus_dp; | |
163 | int fmhz; | |
164 | ||
165 | bus_dp = NULL; | |
166 | if (sdev != NULL && sdev->bus != NULL) | |
167 | bus_dp = sdev->bus->ofdev.node; | |
168 | ||
169 | fmhz = of_getintprop_default(dp, "clock-frequency", 0); | |
170 | if (fmhz == 0) | |
171 | fmhz = (!bus_dp) ? 0 : | |
172 | of_getintprop_default(bus_dp, "clock-frequency", 0); | |
173 | ||
174 | esp->cfreq = fmhz; | |
175 | } | |
176 | ||
334ae614 | 177 | static void __devinit esp_get_bursts(struct esp *esp, struct of_device *dma_of) |
cd9ad58d | 178 | { |
334ae614 | 179 | struct device_node *dma_dp = dma_of->node; |
cd9ad58d | 180 | struct sbus_dev *sdev = esp->dev; |
334ae614 DM |
181 | struct device_node *dp; |
182 | u8 bursts, val; | |
cd9ad58d | 183 | |
334ae614 | 184 | dp = sdev->ofdev.node; |
cd9ad58d | 185 | bursts = of_getintprop_default(dp, "burst-sizes", 0xff); |
334ae614 DM |
186 | val = of_getintprop_default(dma_dp, "burst-sizes", 0xff); |
187 | if (val != 0xff) | |
188 | bursts &= val; | |
cd9ad58d DM |
189 | |
190 | if (sdev->bus) { | |
191 | u8 val = of_getintprop_default(sdev->bus->ofdev.node, | |
192 | "burst-sizes", 0xff); | |
193 | if (val != 0xff) | |
194 | bursts &= val; | |
195 | } | |
196 | ||
197 | if (bursts == 0xff || | |
198 | (bursts & DMA_BURST16) == 0 || | |
199 | (bursts & DMA_BURST32) == 0) | |
200 | bursts = (DMA_BURST32 - 1); | |
201 | ||
202 | esp->bursts = bursts; | |
203 | } | |
204 | ||
334ae614 | 205 | static void __devinit esp_sbus_get_props(struct esp *esp, struct of_device *espdma) |
cd9ad58d DM |
206 | { |
207 | esp_get_scsi_id(esp); | |
208 | esp_get_differential(esp); | |
209 | esp_get_clock_params(esp); | |
210 | esp_get_bursts(esp, espdma); | |
211 | } | |
212 | ||
213 | static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg) | |
214 | { | |
215 | sbus_writeb(val, esp->regs + (reg * 4UL)); | |
216 | } | |
217 | ||
218 | static u8 sbus_esp_read8(struct esp *esp, unsigned long reg) | |
219 | { | |
220 | return sbus_readb(esp->regs + (reg * 4UL)); | |
221 | } | |
222 | ||
223 | static dma_addr_t sbus_esp_map_single(struct esp *esp, void *buf, | |
224 | size_t sz, int dir) | |
225 | { | |
226 | return sbus_map_single(esp->dev, buf, sz, dir); | |
227 | } | |
228 | ||
229 | static int sbus_esp_map_sg(struct esp *esp, struct scatterlist *sg, | |
230 | int num_sg, int dir) | |
231 | { | |
232 | return sbus_map_sg(esp->dev, sg, num_sg, dir); | |
233 | } | |
234 | ||
235 | static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr, | |
236 | size_t sz, int dir) | |
237 | { | |
238 | sbus_unmap_single(esp->dev, addr, sz, dir); | |
239 | } | |
240 | ||
241 | static void sbus_esp_unmap_sg(struct esp *esp, struct scatterlist *sg, | |
242 | int num_sg, int dir) | |
243 | { | |
244 | sbus_unmap_sg(esp->dev, sg, num_sg, dir); | |
245 | } | |
246 | ||
247 | static int sbus_esp_irq_pending(struct esp *esp) | |
248 | { | |
249 | if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)) | |
250 | return 1; | |
251 | return 0; | |
252 | } | |
253 | ||
254 | static void sbus_esp_reset_dma(struct esp *esp) | |
255 | { | |
256 | int can_do_burst16, can_do_burst32, can_do_burst64; | |
257 | int can_do_sbus64, lim; | |
258 | u32 val; | |
259 | ||
260 | can_do_burst16 = (esp->bursts & DMA_BURST16) != 0; | |
261 | can_do_burst32 = (esp->bursts & DMA_BURST32) != 0; | |
262 | can_do_burst64 = 0; | |
263 | can_do_sbus64 = 0; | |
264 | if (sbus_can_dma_64bit(esp->dev)) | |
265 | can_do_sbus64 = 1; | |
266 | if (sbus_can_burst64(esp->sdev)) | |
267 | can_do_burst64 = (esp->bursts & DMA_BURST64) != 0; | |
268 | ||
269 | /* Put the DVMA into a known state. */ | |
334ae614 | 270 | if (esp->dmarev != dvmahme) { |
cd9ad58d DM |
271 | val = dma_read32(DMA_CSR); |
272 | dma_write32(val | DMA_RST_SCSI, DMA_CSR); | |
273 | dma_write32(val & ~DMA_RST_SCSI, DMA_CSR); | |
274 | } | |
334ae614 | 275 | switch (esp->dmarev) { |
cd9ad58d DM |
276 | case dvmahme: |
277 | dma_write32(DMA_RESET_FAS366, DMA_CSR); | |
278 | dma_write32(DMA_RST_SCSI, DMA_CSR); | |
279 | ||
280 | esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS | | |
281 | DMA_SCSI_DISAB | DMA_INT_ENAB); | |
282 | ||
283 | esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE | | |
284 | DMA_BRST_SZ); | |
285 | ||
286 | if (can_do_burst64) | |
287 | esp->prev_hme_dmacsr |= DMA_BRST64; | |
288 | else if (can_do_burst32) | |
289 | esp->prev_hme_dmacsr |= DMA_BRST32; | |
290 | ||
291 | if (can_do_sbus64) { | |
292 | esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64; | |
293 | sbus_set_sbus64(esp->dev, esp->bursts); | |
294 | } | |
295 | ||
296 | lim = 1000; | |
297 | while (dma_read32(DMA_CSR) & DMA_PEND_READ) { | |
298 | if (--lim == 0) { | |
299 | printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ " | |
300 | "will not clear!\n", | |
301 | esp->host->unique_id); | |
302 | break; | |
303 | } | |
304 | udelay(1); | |
305 | } | |
306 | ||
307 | dma_write32(0, DMA_CSR); | |
308 | dma_write32(esp->prev_hme_dmacsr, DMA_CSR); | |
309 | ||
310 | dma_write32(0, DMA_ADDR); | |
311 | break; | |
312 | ||
313 | case dvmarev2: | |
314 | if (esp->rev != ESP100) { | |
315 | val = dma_read32(DMA_CSR); | |
316 | dma_write32(val | DMA_3CLKS, DMA_CSR); | |
317 | } | |
318 | break; | |
319 | ||
320 | case dvmarev3: | |
321 | val = dma_read32(DMA_CSR); | |
322 | val &= ~DMA_3CLKS; | |
323 | val |= DMA_2CLKS; | |
324 | if (can_do_burst32) { | |
325 | val &= ~DMA_BRST_SZ; | |
326 | val |= DMA_BRST32; | |
327 | } | |
328 | dma_write32(val, DMA_CSR); | |
329 | break; | |
330 | ||
331 | case dvmaesc1: | |
332 | val = dma_read32(DMA_CSR); | |
333 | val |= DMA_ADD_ENABLE; | |
334 | val &= ~DMA_BCNT_ENAB; | |
335 | if (!can_do_burst32 && can_do_burst16) { | |
336 | val |= DMA_ESC_BURST; | |
337 | } else { | |
338 | val &= ~(DMA_ESC_BURST); | |
339 | } | |
340 | dma_write32(val, DMA_CSR); | |
341 | break; | |
342 | ||
343 | default: | |
344 | break; | |
345 | } | |
346 | ||
347 | /* Enable interrupts. */ | |
348 | val = dma_read32(DMA_CSR); | |
349 | dma_write32(val | DMA_INT_ENAB, DMA_CSR); | |
350 | } | |
351 | ||
352 | static void sbus_esp_dma_drain(struct esp *esp) | |
353 | { | |
354 | u32 csr; | |
355 | int lim; | |
356 | ||
334ae614 | 357 | if (esp->dmarev == dvmahme) |
cd9ad58d DM |
358 | return; |
359 | ||
360 | csr = dma_read32(DMA_CSR); | |
361 | if (!(csr & DMA_FIFO_ISDRAIN)) | |
362 | return; | |
363 | ||
334ae614 | 364 | if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1) |
cd9ad58d DM |
365 | dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); |
366 | ||
367 | lim = 1000; | |
368 | while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) { | |
369 | if (--lim == 0) { | |
370 | printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n", | |
371 | esp->host->unique_id); | |
372 | break; | |
373 | } | |
374 | udelay(1); | |
375 | } | |
376 | } | |
377 | ||
378 | static void sbus_esp_dma_invalidate(struct esp *esp) | |
379 | { | |
334ae614 | 380 | if (esp->dmarev == dvmahme) { |
cd9ad58d DM |
381 | dma_write32(DMA_RST_SCSI, DMA_CSR); |
382 | ||
383 | esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr | | |
384 | (DMA_PARITY_OFF | DMA_2CLKS | | |
385 | DMA_SCSI_DISAB | DMA_INT_ENAB)) & | |
386 | ~(DMA_ST_WRITE | DMA_ENABLE)); | |
387 | ||
388 | dma_write32(0, DMA_CSR); | |
389 | dma_write32(esp->prev_hme_dmacsr, DMA_CSR); | |
390 | ||
391 | /* This is necessary to avoid having the SCSI channel | |
392 | * engine lock up on us. | |
393 | */ | |
394 | dma_write32(0, DMA_ADDR); | |
395 | } else { | |
396 | u32 val; | |
397 | int lim; | |
398 | ||
399 | lim = 1000; | |
400 | while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) { | |
401 | if (--lim == 0) { | |
402 | printk(KERN_ALERT PFX "esp%d: DMA will not " | |
403 | "invalidate!\n", esp->host->unique_id); | |
404 | break; | |
405 | } | |
406 | udelay(1); | |
407 | } | |
408 | ||
409 | val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB); | |
410 | val |= DMA_FIFO_INV; | |
411 | dma_write32(val, DMA_CSR); | |
412 | val &= ~DMA_FIFO_INV; | |
413 | dma_write32(val, DMA_CSR); | |
414 | } | |
415 | } | |
416 | ||
417 | static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count, | |
418 | u32 dma_count, int write, u8 cmd) | |
419 | { | |
420 | u32 csr; | |
421 | ||
422 | BUG_ON(!(cmd & ESP_CMD_DMA)); | |
423 | ||
424 | sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); | |
425 | sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); | |
426 | if (esp->rev == FASHME) { | |
427 | sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO); | |
428 | sbus_esp_write8(esp, 0, FAS_RHI); | |
429 | ||
430 | scsi_esp_cmd(esp, cmd); | |
431 | ||
432 | csr = esp->prev_hme_dmacsr; | |
433 | csr |= DMA_SCSI_DISAB | DMA_ENABLE; | |
434 | if (write) | |
435 | csr |= DMA_ST_WRITE; | |
436 | else | |
437 | csr &= ~DMA_ST_WRITE; | |
438 | esp->prev_hme_dmacsr = csr; | |
439 | ||
440 | dma_write32(dma_count, DMA_COUNT); | |
441 | dma_write32(addr, DMA_ADDR); | |
442 | dma_write32(csr, DMA_CSR); | |
443 | } else { | |
444 | csr = dma_read32(DMA_CSR); | |
445 | csr |= DMA_ENABLE; | |
446 | if (write) | |
447 | csr |= DMA_ST_WRITE; | |
448 | else | |
449 | csr &= ~DMA_ST_WRITE; | |
450 | dma_write32(csr, DMA_CSR); | |
334ae614 | 451 | if (esp->dmarev == dvmaesc1) { |
cd9ad58d DM |
452 | u32 end = PAGE_ALIGN(addr + dma_count + 16U); |
453 | dma_write32(end - addr, DMA_COUNT); | |
454 | } | |
455 | dma_write32(addr, DMA_ADDR); | |
456 | ||
457 | scsi_esp_cmd(esp, cmd); | |
458 | } | |
459 | ||
460 | } | |
461 | ||
462 | static int sbus_esp_dma_error(struct esp *esp) | |
463 | { | |
464 | u32 csr = dma_read32(DMA_CSR); | |
465 | ||
466 | if (csr & DMA_HNDL_ERROR) | |
467 | return 1; | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
472 | static const struct esp_driver_ops sbus_esp_ops = { | |
473 | .esp_write8 = sbus_esp_write8, | |
474 | .esp_read8 = sbus_esp_read8, | |
475 | .map_single = sbus_esp_map_single, | |
476 | .map_sg = sbus_esp_map_sg, | |
477 | .unmap_single = sbus_esp_unmap_single, | |
478 | .unmap_sg = sbus_esp_unmap_sg, | |
479 | .irq_pending = sbus_esp_irq_pending, | |
480 | .reset_dma = sbus_esp_reset_dma, | |
481 | .dma_drain = sbus_esp_dma_drain, | |
482 | .dma_invalidate = sbus_esp_dma_invalidate, | |
483 | .send_dma_cmd = sbus_esp_send_dma_cmd, | |
484 | .dma_error = sbus_esp_dma_error, | |
485 | }; | |
486 | ||
487 | static int __devinit esp_sbus_probe_one(struct device *dev, | |
488 | struct sbus_dev *esp_dev, | |
334ae614 | 489 | struct of_device *espdma, |
cd9ad58d DM |
490 | struct sbus_bus *sbus, |
491 | int hme) | |
492 | { | |
493 | struct scsi_host_template *tpnt = &scsi_esp_template; | |
494 | struct Scsi_Host *host; | |
495 | struct esp *esp; | |
496 | int err; | |
497 | ||
498 | host = scsi_host_alloc(tpnt, sizeof(struct esp)); | |
499 | ||
500 | err = -ENOMEM; | |
501 | if (!host) | |
502 | goto fail; | |
503 | ||
504 | host->max_id = (hme ? 16 : 8); | |
2b14ec78 | 505 | esp = shost_priv(host); |
cd9ad58d DM |
506 | |
507 | esp->host = host; | |
508 | esp->dev = esp_dev; | |
509 | esp->ops = &sbus_esp_ops; | |
510 | ||
511 | if (hme) | |
512 | esp->flags |= ESP_FLAG_WIDE_CAPABLE; | |
513 | ||
334ae614 | 514 | err = esp_sbus_setup_dma(esp, espdma); |
cd9ad58d DM |
515 | if (err < 0) |
516 | goto fail_unlink; | |
517 | ||
518 | err = esp_sbus_map_regs(esp, hme); | |
519 | if (err < 0) | |
520 | goto fail_unlink; | |
521 | ||
522 | err = esp_sbus_map_command_block(esp); | |
523 | if (err < 0) | |
524 | goto fail_unmap_regs; | |
525 | ||
526 | err = esp_sbus_register_irq(esp); | |
527 | if (err < 0) | |
528 | goto fail_unmap_command_block; | |
529 | ||
530 | esp_sbus_get_props(esp, espdma); | |
531 | ||
532 | /* Before we try to touch the ESP chip, ESC1 dma can | |
533 | * come up with the reset bit set, so make sure that | |
534 | * is clear first. | |
535 | */ | |
334ae614 | 536 | if (esp->dmarev == dvmaesc1) { |
cd9ad58d DM |
537 | u32 val = dma_read32(DMA_CSR); |
538 | ||
539 | dma_write32(val & ~DMA_RST_SCSI, DMA_CSR); | |
540 | } | |
541 | ||
542 | dev_set_drvdata(&esp_dev->ofdev.dev, esp); | |
543 | ||
544 | err = scsi_esp_register(esp, dev); | |
545 | if (err) | |
546 | goto fail_free_irq; | |
547 | ||
548 | return 0; | |
549 | ||
550 | fail_free_irq: | |
551 | free_irq(host->irq, esp); | |
552 | fail_unmap_command_block: | |
553 | sbus_free_consistent(esp->dev, 16, | |
554 | esp->command_block, | |
555 | esp->command_block_dma); | |
556 | fail_unmap_regs: | |
557 | sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE); | |
558 | fail_unlink: | |
559 | scsi_host_put(host); | |
560 | fail: | |
561 | return err; | |
562 | } | |
563 | ||
564 | static int __devinit esp_sbus_probe(struct of_device *dev, const struct of_device_id *match) | |
565 | { | |
566 | struct sbus_dev *sdev = to_sbus_device(&dev->dev); | |
334ae614 | 567 | struct device_node *dma_node = NULL; |
cd9ad58d | 568 | struct device_node *dp = dev->node; |
334ae614 | 569 | struct of_device *dma_of = NULL; |
cd9ad58d DM |
570 | int hme = 0; |
571 | ||
572 | if (dp->parent && | |
573 | (!strcmp(dp->parent->name, "espdma") || | |
574 | !strcmp(dp->parent->name, "dma"))) | |
334ae614 | 575 | dma_node = dp->parent; |
cd9ad58d | 576 | else if (!strcmp(dp->name, "SUNW,fas")) { |
334ae614 | 577 | dma_node = sdev->ofdev.node; |
cd9ad58d DM |
578 | hme = 1; |
579 | } | |
334ae614 DM |
580 | if (dma_node) |
581 | dma_of = of_find_device_by_node(dma_node); | |
582 | if (!dma_of) | |
583 | return -ENODEV; | |
cd9ad58d | 584 | |
334ae614 | 585 | return esp_sbus_probe_one(&dev->dev, sdev, dma_of, |
cd9ad58d DM |
586 | sdev->bus, hme); |
587 | } | |
588 | ||
589 | static int __devexit esp_sbus_remove(struct of_device *dev) | |
590 | { | |
591 | struct esp *esp = dev_get_drvdata(&dev->dev); | |
334ae614 | 592 | struct of_device *dma_of = esp->dma; |
cd9ad58d DM |
593 | unsigned int irq = esp->host->irq; |
594 | u32 val; | |
595 | ||
596 | scsi_esp_unregister(esp); | |
597 | ||
598 | /* Disable interrupts. */ | |
599 | val = dma_read32(DMA_CSR); | |
600 | dma_write32(val & ~DMA_INT_ENAB, DMA_CSR); | |
601 | ||
602 | free_irq(irq, esp); | |
603 | sbus_free_consistent(esp->dev, 16, | |
604 | esp->command_block, | |
605 | esp->command_block_dma); | |
606 | sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE); | |
334ae614 DM |
607 | of_iounmap(&dma_of->resource[0], esp->dma_regs, |
608 | resource_size(&dma_of->resource[0])); | |
cd9ad58d DM |
609 | |
610 | scsi_host_put(esp->host); | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
615 | static struct of_device_id esp_match[] = { | |
616 | { | |
617 | .name = "SUNW,esp", | |
618 | }, | |
619 | { | |
620 | .name = "SUNW,fas", | |
621 | }, | |
622 | { | |
623 | .name = "esp", | |
624 | }, | |
625 | {}, | |
626 | }; | |
627 | MODULE_DEVICE_TABLE(of, esp_match); | |
628 | ||
629 | static struct of_platform_driver esp_sbus_driver = { | |
630 | .name = "esp", | |
631 | .match_table = esp_match, | |
632 | .probe = esp_sbus_probe, | |
633 | .remove = __devexit_p(esp_sbus_remove), | |
634 | }; | |
635 | ||
636 | static int __init sunesp_init(void) | |
637 | { | |
638 | return of_register_driver(&esp_sbus_driver, &sbus_bus_type); | |
639 | } | |
640 | ||
641 | static void __exit sunesp_exit(void) | |
642 | { | |
643 | of_unregister_driver(&esp_sbus_driver); | |
644 | } | |
645 | ||
646 | MODULE_DESCRIPTION("Sun ESP SCSI driver"); | |
647 | MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); | |
648 | MODULE_LICENSE("GPL"); | |
649 | MODULE_VERSION(DRV_VERSION); | |
650 | ||
651 | module_init(sunesp_init); | |
652 | module_exit(sunesp_exit); |