[mirror_ubuntu-artful-kernel.git] / drivers / scsi / sun_esp.c

/* sun_esp.c: ESP front-end for Sparc SBUS systems.
 *
 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/init.h>

#include <asm/irq.h>
#include <asm/io.h>
#include <asm/dma.h>

#include <asm/sbus.h>

#include <scsi/scsi_host.h>

#include "esp_scsi.h"

#define DRV_MODULE_NAME		"sun_esp"
#define PFX DRV_MODULE_NAME	": "
#define DRV_VERSION		"1.000"
#define DRV_MODULE_RELDATE	"April 19, 2007"

#define dma_read32(REG) \
	sbus_readl(esp->dma_regs + (REG))
#define dma_write32(VAL, REG) \
	sbus_writel((VAL), esp->dma_regs + (REG))

/* DVMA chip revisions */
enum dvma_rev {
	dvmarev0,
	dvmaesc1,
	dvmarev1,
	dvmarev2,
	dvmarev3,
	dvmarevplus,
	dvmahme
};

static int __devinit esp_sbus_setup_dma(struct esp *esp,
					struct of_device *dma_of)
{
	esp->dma = dma_of;

	esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
				   resource_size(&dma_of->resource[0]),
				   "espdma");
	if (!esp->dma_regs)
		return -ENOMEM;

	switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
	case DMA_VERS0:
		esp->dmarev = dvmarev0;
		break;
	case DMA_ESCV1:
		esp->dmarev = dvmaesc1;
		break;
	case DMA_VERS1:
		esp->dmarev = dvmarev1;
		break;
	case DMA_VERS2:
		esp->dmarev = dvmarev2;
		break;
	case DMA_VERHME:
		esp->dmarev = dvmahme;
		break;
	case DMA_VERSPLUS:
		esp->dmarev = dvmarevplus;
		break;
	}

	return 0;

}

static int __devinit esp_sbus_map_regs(struct esp *esp, int hme)
{
	struct sbus_dev *sdev = esp->dev;
	struct resource *res;

	/* On HME, two reg sets exist, first is DVMA,
	 * second is ESP registers.
	 */
	if (hme)
		res = &sdev->resource[1];
	else
		res = &sdev->resource[0];

	esp->regs = sbus_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
	if (!esp->regs)
		return -ENOMEM;

	return 0;
}

static int __devinit esp_sbus_map_command_block(struct esp *esp)
{
	struct sbus_dev *sdev = esp->dev;

	esp->command_block = sbus_alloc_consistent(&sdev->ofdev.dev, 16,
						   &esp->command_block_dma);
	if (!esp->command_block)
		return -ENOMEM;
	return 0;
}

static int __devinit esp_sbus_register_irq(struct esp *esp)
{
	struct Scsi_Host *host = esp->host;
	struct sbus_dev *sdev = esp->dev;

	host->irq = sdev->irqs[0];
	return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
}

static void __devinit esp_get_scsi_id(struct esp *esp)
{
	struct sbus_dev *sdev = esp->dev;
	struct device_node *dp = sdev->ofdev.node;

	esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
	if (esp->scsi_id != 0xff)
		goto done;

	esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
	if (esp->scsi_id != 0xff)
		goto done;

	if (!sdev->bus) {
		/* SUN4 */
		esp->scsi_id = 7;
		goto done;
	}

	esp->scsi_id = of_getintprop_default(sdev->bus->ofdev.node,
					     "scsi-initiator-id", 7);

done:
	esp->host->this_id = esp->scsi_id;
	esp->scsi_id_mask = (1 << esp->scsi_id);
}

static void __devinit esp_get_differential(struct esp *esp)
{
	struct sbus_dev *sdev = esp->dev;
	struct device_node *dp = sdev->ofdev.node;

	if (of_find_property(dp, "differential", NULL))
		esp->flags |= ESP_FLAG_DIFFERENTIAL;
	else
		esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
}

static void __devinit esp_get_clock_params(struct esp *esp)
{
	struct sbus_dev *sdev = esp->dev;
	struct device_node *dp = sdev->ofdev.node;
	struct device_node *bus_dp;
	int fmhz;

	bus_dp = NULL;
	if (sdev != NULL && sdev->bus != NULL)
		bus_dp = sdev->bus->ofdev.node;

	fmhz = of_getintprop_default(dp, "clock-frequency", 0);
	if (fmhz == 0)
		fmhz = (!bus_dp) ? 0 :
			of_getintprop_default(bus_dp, "clock-frequency", 0);

	esp->cfreq = fmhz;
}

static void __devinit esp_get_bursts(struct esp *esp, struct of_device *dma_of)
{
	struct device_node *dma_dp = dma_of->node;
	struct sbus_dev *sdev = esp->dev;
	struct device_node *dp;
	u8 bursts, val;

	dp = sdev->ofdev.node;
	bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
	val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
	if (val != 0xff)
		bursts &= val;

	if (sdev->bus) {
		u8 val = of_getintprop_default(sdev->bus->ofdev.node,
					       "burst-sizes", 0xff);
		if (val != 0xff)
			bursts &= val;
	}

	if (bursts == 0xff ||
	    (bursts & DMA_BURST16) == 0 ||
	    (bursts & DMA_BURST32) == 0)
		bursts = (DMA_BURST32 - 1);

	esp->bursts = bursts;
}

static void __devinit esp_sbus_get_props(struct esp *esp, struct of_device *espdma)
{
	esp_get_scsi_id(esp);
	esp_get_differential(esp);
	esp_get_clock_params(esp);
	esp_get_bursts(esp, espdma);
}

static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
{
	sbus_writeb(val, esp->regs + (reg * 4UL));
}

static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
{
	return sbus_readb(esp->regs + (reg * 4UL));
}

static dma_addr_t sbus_esp_map_single(struct esp *esp, void *buf,
				      size_t sz, int dir)
{
	struct sbus_dev *sdev = esp->dev;

	return sbus_map_single(&sdev->ofdev.dev, buf, sz, dir);
}

static int sbus_esp_map_sg(struct esp *esp, struct scatterlist *sg,
				  int num_sg, int dir)
{
	struct sbus_dev *sdev = esp->dev;

	return sbus_map_sg(&sdev->ofdev.dev, sg, num_sg, dir);
}

static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
				  size_t sz, int dir)
{
	struct sbus_dev *sdev = esp->dev;

	sbus_unmap_single(&sdev->ofdev.dev, addr, sz, dir);
}

static void sbus_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
			      int num_sg, int dir)
{
	struct sbus_dev *sdev = esp->dev;

	sbus_unmap_sg(&sdev->ofdev.dev, sg, num_sg, dir);
}

static int sbus_esp_irq_pending(struct esp *esp)
{
	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
		return 1;
	return 0;
}

static void sbus_esp_reset_dma(struct esp *esp)
{
	int can_do_burst16, can_do_burst32, can_do_burst64;
	int can_do_sbus64, lim;
	u32 val;

	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
	can_do_burst64 = 0;
	can_do_sbus64 = 0;
	if (sbus_can_dma_64bit(esp->dev))
		can_do_sbus64 = 1;
	if (sbus_can_burst64(esp->sdev))
		can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;

	/* Put the DVMA into a known state. */
	if (esp->dmarev != dvmahme) {
		val = dma_read32(DMA_CSR);
		dma_write32(val | DMA_RST_SCSI, DMA_CSR);
		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	}
	switch (esp->dmarev) {
	case dvmahme:
		dma_write32(DMA_RESET_FAS366, DMA_CSR);
		dma_write32(DMA_RST_SCSI, DMA_CSR);

		esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
					DMA_SCSI_DISAB | DMA_INT_ENAB);

		esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
					  DMA_BRST_SZ);

		if (can_do_burst64)
			esp->prev_hme_dmacsr |= DMA_BRST64;
		else if (can_do_burst32)
			esp->prev_hme_dmacsr |= DMA_BRST32;

		if (can_do_sbus64) {
			esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
			sbus_set_sbus64(esp->dev, esp->bursts);
		}

		lim = 1000;
		while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
			if (--lim == 0) {
				printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
				       "will not clear!\n",
				       esp->host->unique_id);
				break;
			}
			udelay(1);
		}

		dma_write32(0, DMA_CSR);
		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);

		dma_write32(0, DMA_ADDR);
		break;

	case dvmarev2:
		if (esp->rev != ESP100) {
			val = dma_read32(DMA_CSR);
			dma_write32(val | DMA_3CLKS, DMA_CSR);
		}
		break;

	case dvmarev3:
		val = dma_read32(DMA_CSR);
		val &= ~DMA_3CLKS;
		val |= DMA_2CLKS;
		if (can_do_burst32) {
			val &= ~DMA_BRST_SZ;
			val |= DMA_BRST32;
		}
		dma_write32(val, DMA_CSR);
		break;

	case dvmaesc1:
		val = dma_read32(DMA_CSR);
		val |= DMA_ADD_ENABLE;
		val &= ~DMA_BCNT_ENAB;
		if (!can_do_burst32 && can_do_burst16) {
			val |= DMA_ESC_BURST;
		} else {
			val &= ~(DMA_ESC_BURST);
		}
		dma_write32(val, DMA_CSR);
		break;

	default:
		break;
	}

	/* Enable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val | DMA_INT_ENAB, DMA_CSR);
}

static void sbus_esp_dma_drain(struct esp *esp)
{
	u32 csr;
	int lim;

	if (esp->dmarev == dvmahme)
		return;

	csr = dma_read32(DMA_CSR);
	if (!(csr & DMA_FIFO_ISDRAIN))
		return;

	if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
		dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);

	lim = 1000;
	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
		if (--lim == 0) {
			printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
			       esp->host->unique_id);
			break;
		}
		udelay(1);
	}
}

static void sbus_esp_dma_invalidate(struct esp *esp)
{
	if (esp->dmarev == dvmahme) {
		dma_write32(DMA_RST_SCSI, DMA_CSR);

		esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
					 (DMA_PARITY_OFF | DMA_2CLKS |
					  DMA_SCSI_DISAB | DMA_INT_ENAB)) &
					~(DMA_ST_WRITE | DMA_ENABLE));

		dma_write32(0, DMA_CSR);
		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);

		/* This is necessary to avoid having the SCSI channel
		 * engine lock up on us.
		 */
		dma_write32(0, DMA_ADDR);
	} else {
		u32 val;
		int lim;

		lim = 1000;
		while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
			if (--lim == 0) {
				printk(KERN_ALERT PFX "esp%d: DMA will not "
				       "invalidate!\n", esp->host->unique_id);
				break;
			}
			udelay(1);
		}

		val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
		val |= DMA_FIFO_INV;
		dma_write32(val, DMA_CSR);
		val &= ~DMA_FIFO_INV;
		dma_write32(val, DMA_CSR);
	}
}

static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
				  u32 dma_count, int write, u8 cmd)
{
	u32 csr;

	BUG_ON(!(cmd & ESP_CMD_DMA));

	sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	if (esp->rev == FASHME) {
		sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
		sbus_esp_write8(esp, 0, FAS_RHI);

		scsi_esp_cmd(esp, cmd);

		csr = esp->prev_hme_dmacsr;
		csr |= DMA_SCSI_DISAB | DMA_ENABLE;
		if (write)
			csr |= DMA_ST_WRITE;
		else
			csr &= ~DMA_ST_WRITE;
		esp->prev_hme_dmacsr = csr;

		dma_write32(dma_count, DMA_COUNT);
		dma_write32(addr, DMA_ADDR);
		dma_write32(csr, DMA_CSR);
	} else {
		csr = dma_read32(DMA_CSR);
		csr |= DMA_ENABLE;
		if (write)
			csr |= DMA_ST_WRITE;
		else
			csr &= ~DMA_ST_WRITE;
		dma_write32(csr, DMA_CSR);
		if (esp->dmarev == dvmaesc1) {
			u32 end = PAGE_ALIGN(addr + dma_count + 16U);
			dma_write32(end - addr, DMA_COUNT);
		}
		dma_write32(addr, DMA_ADDR);

		scsi_esp_cmd(esp, cmd);
	}

}

static int sbus_esp_dma_error(struct esp *esp)
{
	u32 csr = dma_read32(DMA_CSR);

	if (csr & DMA_HNDL_ERROR)
		return 1;

	return 0;
}

static const struct esp_driver_ops sbus_esp_ops = {
	.esp_write8	=	sbus_esp_write8,
	.esp_read8	=	sbus_esp_read8,
	.map_single	=	sbus_esp_map_single,
	.map_sg		=	sbus_esp_map_sg,
	.unmap_single	=	sbus_esp_unmap_single,
	.unmap_sg	=	sbus_esp_unmap_sg,
	.irq_pending	=	sbus_esp_irq_pending,
	.reset_dma	=	sbus_esp_reset_dma,
	.dma_drain	=	sbus_esp_dma_drain,
	.dma_invalidate	=	sbus_esp_dma_invalidate,
	.send_dma_cmd	=	sbus_esp_send_dma_cmd,
	.dma_error	=	sbus_esp_dma_error,
};

static int __devinit esp_sbus_probe_one(struct device *dev,
					struct sbus_dev *esp_dev,
					struct of_device *espdma,
					struct sbus_bus *sbus,
					int hme)
{
	struct scsi_host_template *tpnt = &scsi_esp_template;
	struct Scsi_Host *host;
	struct esp *esp;
	int err;

	host = scsi_host_alloc(tpnt, sizeof(struct esp));

	err = -ENOMEM;
	if (!host)
		goto fail;

	host->max_id = (hme ? 16 : 8);
	esp = shost_priv(host);

	esp->host = host;
	esp->dev = esp_dev;
	esp->ops = &sbus_esp_ops;

	if (hme)
		esp->flags |= ESP_FLAG_WIDE_CAPABLE;

	err = esp_sbus_setup_dma(esp, espdma);
	if (err < 0)
		goto fail_unlink;

	err = esp_sbus_map_regs(esp, hme);
	if (err < 0)
		goto fail_unlink;

	err = esp_sbus_map_command_block(esp);
	if (err < 0)
		goto fail_unmap_regs;

	err = esp_sbus_register_irq(esp);
	if (err < 0)
		goto fail_unmap_command_block;

	esp_sbus_get_props(esp, espdma);

	/* Before we try to touch the ESP chip, ESC1 dma can
	 * come up with the reset bit set, so make sure that
	 * is clear first.
	 */
	if (esp->dmarev == dvmaesc1) {
		u32 val = dma_read32(DMA_CSR);

		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	}

	dev_set_drvdata(&esp_dev->ofdev.dev, esp);

	err = scsi_esp_register(esp, dev);
	if (err)
		goto fail_free_irq;

	return 0;

fail_free_irq:
	free_irq(host->irq, esp);
fail_unmap_command_block:
	sbus_free_consistent(&esp_dev->ofdev.dev, 16,
			     esp->command_block,
			     esp->command_block_dma);
fail_unmap_regs:
	sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE);
fail_unlink:
	scsi_host_put(host);
fail:
	return err;
}

static int __devinit esp_sbus_probe(struct of_device *dev, const struct of_device_id *match)
{
	struct sbus_dev *sdev = to_sbus_device(&dev->dev);
	struct device_node *dma_node = NULL;
	struct device_node *dp = dev->node;
	struct of_device *dma_of = NULL;
	int hme = 0;

	if (dp->parent &&
	    (!strcmp(dp->parent->name, "espdma") ||
	     !strcmp(dp->parent->name, "dma")))
		dma_node = dp->parent;
	else if (!strcmp(dp->name, "SUNW,fas")) {
		dma_node = sdev->ofdev.node;
		hme = 1;
	}
	if (dma_node)
		dma_of = of_find_device_by_node(dma_node);
	if (!dma_of)
		return -ENODEV;

	return esp_sbus_probe_one(&dev->dev, sdev, dma_of,
				  sdev->bus, hme);
}

static int __devexit esp_sbus_remove(struct of_device *dev)
{
	struct esp *esp = dev_get_drvdata(&dev->dev);
	struct sbus_dev *sdev = esp->dev;
	struct of_device *dma_of = esp->dma;
	unsigned int irq = esp->host->irq;
	u32 val;

	scsi_esp_unregister(esp);

	/* Disable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);

	free_irq(irq, esp);
	sbus_free_consistent(&sdev->ofdev.dev, 16,
			     esp->command_block,
			     esp->command_block_dma);
	sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE);
	of_iounmap(&dma_of->resource[0], esp->dma_regs,
		   resource_size(&dma_of->resource[0]));

	scsi_host_put(esp->host);

	return 0;
}

static struct of_device_id esp_match[] = {
	{
		.name = "SUNW,esp",
	},
	{
		.name = "SUNW,fas",
	},
	{
		.name = "esp",
	},
	{},
};
MODULE_DEVICE_TABLE(of, esp_match);

static struct of_platform_driver esp_sbus_driver = {
	.name		= "esp",
	.match_table	= esp_match,
	.probe		= esp_sbus_probe,
	.remove		= __devexit_p(esp_sbus_remove),
};

static int __init sunesp_init(void)
{
	return of_register_driver(&esp_sbus_driver, &sbus_bus_type);
}

static void __exit sunesp_exit(void)
{
	of_unregister_driver(&esp_sbus_driver);
}

MODULE_DESCRIPTION("Sun ESP SCSI driver");
MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

module_init(sunesp_init);
module_exit(sunesp_exit);
Commit	Line	Data
cd9ad58d DM	1	/* sun_esp.c: ESP front-end for Sparc SBUS systems.
cd9ad58d DM	2	*
334ae614	3	* Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
cd9ad58d DM	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/types.h>
6025dfe5	8	#include <linux/delay.h>
cd9ad58d	9	#include <linux/module.h>
27ac792c	10	#include <linux/mm.h>
cd9ad58d DM	11	#include <linux/init.h>
	12
	13	#include <asm/irq.h>
	14	#include <asm/io.h>
	15	#include <asm/dma.h>
	16
	17	#include <asm/sbus.h>
	18
	19	#include <scsi/scsi_host.h>
	20
	21	#include "esp_scsi.h"
	22
	23	#define DRV_MODULE_NAME "sun_esp"
	24	#define PFX DRV_MODULE_NAME ": "
	25	#define DRV_VERSION "1.000"
	26	#define DRV_MODULE_RELDATE "April 19, 2007"
	27
	28	#define dma_read32(REG) \
	29	sbus_readl(esp->dma_regs + (REG))
	30	#define dma_write32(VAL, REG) \
	31	sbus_writel((VAL), esp->dma_regs + (REG))
	32
334ae614 DM	33	/* DVMA chip revisions */
	34	enum dvma_rev {
	35	dvmarev0,
	36	dvmaesc1,
	37	dvmarev1,
	38	dvmarev2,
	39	dvmarev3,
	40	dvmarevplus,
	41	dvmahme
	42	};
cd9ad58d	43
334ae614 DM	44	static int __devinit esp_sbus_setup_dma(struct esp *esp,
	45	struct of_device *dma_of)
	46	{
	47	esp->dma = dma_of;
cd9ad58d	48
334ae614 DM	49	esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
	50	resource_size(&dma_of->resource[0]),
	51	"espdma");
	52	if (!esp->dma_regs)
	53	return -ENOMEM;
cd9ad58d	54
334ae614 DM	55	switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
	56	case DMA_VERS0:
	57	esp->dmarev = dvmarev0;
	58	break;
	59	case DMA_ESCV1:
	60	esp->dmarev = dvmaesc1;
	61	break;
	62	case DMA_VERS1:
	63	esp->dmarev = dvmarev1;
	64	break;
	65	case DMA_VERS2:
	66	esp->dmarev = dvmarev2;
	67	break;
	68	case DMA_VERHME:
	69	esp->dmarev = dvmahme;
	70	break;
	71	case DMA_VERSPLUS:
	72	esp->dmarev = dvmarevplus;
	73	break;
cd9ad58d	74	}
cd9ad58d DM	75
	76	return 0;
	77
	78	}
	79
	80	static int __devinit esp_sbus_map_regs(struct esp *esp, int hme)
	81	{
	82	struct sbus_dev *sdev = esp->dev;
	83	struct resource *res;
	84
	85	/* On HME, two reg sets exist, first is DVMA,
	86	* second is ESP registers.
	87	*/
	88	if (hme)
	89	res = &sdev->resource[1];
	90	else
	91	res = &sdev->resource[0];
	92
	93	esp->regs = sbus_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
	94	if (!esp->regs)
	95	return -ENOMEM;
	96
	97	return 0;
	98	}
	99
	100	static int __devinit esp_sbus_map_command_block(struct esp *esp)
	101	{
	102	struct sbus_dev *sdev = esp->dev;
	103
7a715f46	104	esp->command_block = sbus_alloc_consistent(&sdev->ofdev.dev, 16,
cd9ad58d DM	105	&esp->command_block_dma);
	106	if (!esp->command_block)
	107	return -ENOMEM;
	108	return 0;
	109	}
	110
	111	static int __devinit esp_sbus_register_irq(struct esp *esp)
	112	{
	113	struct Scsi_Host *host = esp->host;
	114	struct sbus_dev *sdev = esp->dev;
	115
	116	host->irq = sdev->irqs[0];
	117	return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
	118	}
	119
	120	static void __devinit esp_get_scsi_id(struct esp *esp)
	121	{
	122	struct sbus_dev *sdev = esp->dev;
	123	struct device_node *dp = sdev->ofdev.node;
	124
	125	esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
	126	if (esp->scsi_id != 0xff)
	127	goto done;
	128
	129	esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
	130	if (esp->scsi_id != 0xff)
	131	goto done;
	132
	133	if (!sdev->bus) {
	134	/* SUN4 */
	135	esp->scsi_id = 7;
	136	goto done;
	137	}
	138
	139	esp->scsi_id = of_getintprop_default(sdev->bus->ofdev.node,
	140	"scsi-initiator-id", 7);
	141
	142	done:
	143	esp->host->this_id = esp->scsi_id;
	144	esp->scsi_id_mask = (1 << esp->scsi_id);
	145	}
	146
	147	static void __devinit esp_get_differential(struct esp *esp)
	148	{
	149	struct sbus_dev *sdev = esp->dev;
	150	struct device_node *dp = sdev->ofdev.node;
	151
	152	if (of_find_property(dp, "differential", NULL))
	153	esp->flags \|= ESP_FLAG_DIFFERENTIAL;
	154	else
	155	esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
	156	}
	157
	158	static void __devinit esp_get_clock_params(struct esp *esp)
	159	{
	160	struct sbus_dev *sdev = esp->dev;
	161	struct device_node *dp = sdev->ofdev.node;
	162	struct device_node *bus_dp;
	163	int fmhz;
	164
	165	bus_dp = NULL;
	166	if (sdev != NULL && sdev->bus != NULL)
	167	bus_dp = sdev->bus->ofdev.node;
	168
169	fmhz = of_getintprop_default(dp, "clock-frequency", 0);
170	if (fmhz == 0)
171	fmhz = (!bus_dp) ? 0 :
172	of_getintprop_default(bus_dp, "clock-frequency", 0);
173
174	esp->cfreq = fmhz;
175	}
176
334ae614	177	static void __devinit esp_get_bursts(struct esp esp, struct of_device dma_of)
cd9ad58d	178	{
334ae614	179	struct device_node *dma_dp = dma_of->node;
cd9ad58d	180	struct sbus_dev *sdev = esp->dev;
334ae614 DM	181	struct device_node *dp;
334ae614 DM	182	u8 bursts, val;
cd9ad58d	183
334ae614	184	dp = sdev->ofdev.node;
cd9ad58d	185	bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
334ae614 DM	186	val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
	187	if (val != 0xff)
	188	bursts &= val;
cd9ad58d DM	189
	190	if (sdev->bus) {
	191	u8 val = of_getintprop_default(sdev->bus->ofdev.node,
	192	"burst-sizes", 0xff);
	193	if (val != 0xff)
	194	bursts &= val;
	195	}
	196
	197	if (bursts == 0xff \|\|
	198	(bursts & DMA_BURST16) == 0 \|\|
	199	(bursts & DMA_BURST32) == 0)
	200	bursts = (DMA_BURST32 - 1);
	201
	202	esp->bursts = bursts;
	203	}
	204
334ae614	205	static void __devinit esp_sbus_get_props(struct esp esp, struct of_device espdma)
cd9ad58d DM	206	{
	207	esp_get_scsi_id(esp);
	208	esp_get_differential(esp);
	209	esp_get_clock_params(esp);
	210	esp_get_bursts(esp, espdma);
	211	}
	212
	213	static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
	214	{
	215	sbus_writeb(val, esp->regs + (reg * 4UL));
	216	}
	217
	218	static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
	219	{
	220	return sbus_readb(esp->regs + (reg * 4UL));
	221	}
	222
	223	static dma_addr_t sbus_esp_map_single(struct esp esp, void buf,
	224	size_t sz, int dir)
	225	{
7a715f46 DM	226	struct sbus_dev *sdev = esp->dev;
	227
	228	return sbus_map_single(&sdev->ofdev.dev, buf, sz, dir);
cd9ad58d DM	229	}
	230
	231	static int sbus_esp_map_sg(struct esp esp, struct scatterlist sg,
	232	int num_sg, int dir)
	233	{
7a715f46 DM	234	struct sbus_dev *sdev = esp->dev;
	235
	236	return sbus_map_sg(&sdev->ofdev.dev, sg, num_sg, dir);
cd9ad58d DM	237	}
	238
	239	static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
	240	size_t sz, int dir)
	241	{
7a715f46 DM	242	struct sbus_dev *sdev = esp->dev;
	243
	244	sbus_unmap_single(&sdev->ofdev.dev, addr, sz, dir);
cd9ad58d DM	245	}
	246
	247	static void sbus_esp_unmap_sg(struct esp esp, struct scatterlist sg,
	248	int num_sg, int dir)
	249	{
7a715f46 DM	250	struct sbus_dev *sdev = esp->dev;
	251
	252	sbus_unmap_sg(&sdev->ofdev.dev, sg, num_sg, dir);
cd9ad58d DM	253	}
	254
	255	static int sbus_esp_irq_pending(struct esp *esp)
	256	{
	257	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR \| DMA_HNDL_ERROR))
	258	return 1;
	259	return 0;
	260	}
	261
	262	static void sbus_esp_reset_dma(struct esp *esp)
	263	{
	264	int can_do_burst16, can_do_burst32, can_do_burst64;
	265	int can_do_sbus64, lim;
	266	u32 val;
	267
	268	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
	269	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
	270	can_do_burst64 = 0;
	271	can_do_sbus64 = 0;
	272	if (sbus_can_dma_64bit(esp->dev))
	273	can_do_sbus64 = 1;
	274	if (sbus_can_burst64(esp->sdev))
	275	can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
	276
	277	/* Put the DVMA into a known state. */
334ae614	278	if (esp->dmarev != dvmahme) {
cd9ad58d DM	279	val = dma_read32(DMA_CSR);
	280	dma_write32(val \| DMA_RST_SCSI, DMA_CSR);
	281	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	282	}
334ae614	283	switch (esp->dmarev) {
cd9ad58d DM	284	case dvmahme:
	285	dma_write32(DMA_RESET_FAS366, DMA_CSR);
	286	dma_write32(DMA_RST_SCSI, DMA_CSR);
	287
	288	esp->prev_hme_dmacsr = (DMA_PARITY_OFF \| DMA_2CLKS \|
	289	DMA_SCSI_DISAB \| DMA_INT_ENAB);
	290
	291	esp->prev_hme_dmacsr &= ~(DMA_ENABLE \| DMA_ST_WRITE \|
	292	DMA_BRST_SZ);
	293
	294	if (can_do_burst64)
	295	esp->prev_hme_dmacsr \|= DMA_BRST64;
	296	else if (can_do_burst32)
	297	esp->prev_hme_dmacsr \|= DMA_BRST32;
	298
	299	if (can_do_sbus64) {
	300	esp->prev_hme_dmacsr \|= DMA_SCSI_SBUS64;
	301	sbus_set_sbus64(esp->dev, esp->bursts);
	302	}
	303
	304	lim = 1000;
	305	while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
	306	if (--lim == 0) {
	307	printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
	308	"will not clear!\n",
	309	esp->host->unique_id);
	310	break;
	311	}
	312	udelay(1);
	313	}
	314
	315	dma_write32(0, DMA_CSR);
	316	dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
	317
	318	dma_write32(0, DMA_ADDR);
	319	break;
	320
	321	case dvmarev2:
	322	if (esp->rev != ESP100) {
	323	val = dma_read32(DMA_CSR);
	324	dma_write32(val \| DMA_3CLKS, DMA_CSR);
	325	}
	326	break;
	327
	328	case dvmarev3:
	329	val = dma_read32(DMA_CSR);
	330	val &= ~DMA_3CLKS;
	331	val \|= DMA_2CLKS;
	332	if (can_do_burst32) {
	333	val &= ~DMA_BRST_SZ;
	334	val \|= DMA_BRST32;
	335	}
	336	dma_write32(val, DMA_CSR);
	337	break;
	338
	339	case dvmaesc1:
	340	val = dma_read32(DMA_CSR);
	341	val \|= DMA_ADD_ENABLE;
	342	val &= ~DMA_BCNT_ENAB;
	343	if (!can_do_burst32 && can_do_burst16) {
	344	val \|= DMA_ESC_BURST;
	345	} else {
	346	val &= ~(DMA_ESC_BURST);
	347	}
348	dma_write32(val, DMA_CSR);
349	break;
350
351	default:
352	break;
353	}
354
355	/* Enable interrupts. */
356	val = dma_read32(DMA_CSR);
357	dma_write32(val \| DMA_INT_ENAB, DMA_CSR);
358	}
359
360	static void sbus_esp_dma_drain(struct esp *esp)
361	{
362	u32 csr;
363	int lim;
364
334ae614	365	if (esp->dmarev == dvmahme)
cd9ad58d DM	366	return;
	367
	368	csr = dma_read32(DMA_CSR);
	369	if (!(csr & DMA_FIFO_ISDRAIN))
	370	return;
	371
334ae614	372	if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
cd9ad58d DM	373	dma_write32(csr \| DMA_FIFO_STDRAIN, DMA_CSR);
	374
	375	lim = 1000;
	376	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
	377	if (--lim == 0) {
	378	printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
	379	esp->host->unique_id);
	380	break;
	381	}
	382	udelay(1);
	383	}
	384	}
	385
	386	static void sbus_esp_dma_invalidate(struct esp *esp)
	387	{
334ae614	388	if (esp->dmarev == dvmahme) {
cd9ad58d DM	389	dma_write32(DMA_RST_SCSI, DMA_CSR);
	390
	391	esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr \|
	392	(DMA_PARITY_OFF \| DMA_2CLKS \|
	393	DMA_SCSI_DISAB \| DMA_INT_ENAB)) &
	394	~(DMA_ST_WRITE \| DMA_ENABLE));
	395
	396	dma_write32(0, DMA_CSR);
	397	dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
	398
	399	/* This is necessary to avoid having the SCSI channel
	400	* engine lock up on us.
	401	*/
	402	dma_write32(0, DMA_ADDR);
	403	} else {
	404	u32 val;
	405	int lim;
	406
	407	lim = 1000;
	408	while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
	409	if (--lim == 0) {
	410	printk(KERN_ALERT PFX "esp%d: DMA will not "
	411	"invalidate!\n", esp->host->unique_id);
	412	break;
	413	}
	414	udelay(1);
	415	}
	416
	417	val &= ~(DMA_ENABLE \| DMA_ST_WRITE \| DMA_BCNT_ENAB);
	418	val \|= DMA_FIFO_INV;
	419	dma_write32(val, DMA_CSR);
	420	val &= ~DMA_FIFO_INV;
	421	dma_write32(val, DMA_CSR);
	422	}
	423	}
	424
	425	static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
	426	u32 dma_count, int write, u8 cmd)
	427	{
	428	u32 csr;
	429
	430	BUG_ON(!(cmd & ESP_CMD_DMA));
	431
	432	sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	433	sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	434	if (esp->rev == FASHME) {
	435	sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
	436	sbus_esp_write8(esp, 0, FAS_RHI);
	437
	438	scsi_esp_cmd(esp, cmd);
	439
	440	csr = esp->prev_hme_dmacsr;
	441	csr \|= DMA_SCSI_DISAB \| DMA_ENABLE;
	442	if (write)
	443	csr \|= DMA_ST_WRITE;
	444	else
	445	csr &= ~DMA_ST_WRITE;
	446	esp->prev_hme_dmacsr = csr;
	447
	448	dma_write32(dma_count, DMA_COUNT);
	449	dma_write32(addr, DMA_ADDR);
	450	dma_write32(csr, DMA_CSR);
	451	} else {
	452	csr = dma_read32(DMA_CSR);
453	csr \|= DMA_ENABLE;
454	if (write)
455	csr \|= DMA_ST_WRITE;
456	else
457	csr &= ~DMA_ST_WRITE;
458	dma_write32(csr, DMA_CSR);
334ae614	459	if (esp->dmarev == dvmaesc1) {
cd9ad58d DM	460	u32 end = PAGE_ALIGN(addr + dma_count + 16U);
	461	dma_write32(end - addr, DMA_COUNT);
	462	}
	463	dma_write32(addr, DMA_ADDR);
	464
	465	scsi_esp_cmd(esp, cmd);
	466	}
	467
	468	}
	469
	470	static int sbus_esp_dma_error(struct esp *esp)
	471	{
	472	u32 csr = dma_read32(DMA_CSR);
	473
	474	if (csr & DMA_HNDL_ERROR)
	475	return 1;
	476
	477	return 0;
	478	}
	479
	480	static const struct esp_driver_ops sbus_esp_ops = {
	481	.esp_write8 = sbus_esp_write8,
	482	.esp_read8 = sbus_esp_read8,
	483	.map_single = sbus_esp_map_single,
	484	.map_sg = sbus_esp_map_sg,
	485	.unmap_single = sbus_esp_unmap_single,
	486	.unmap_sg = sbus_esp_unmap_sg,
	487	.irq_pending = sbus_esp_irq_pending,
	488	.reset_dma = sbus_esp_reset_dma,
	489	.dma_drain = sbus_esp_dma_drain,
	490	.dma_invalidate = sbus_esp_dma_invalidate,
	491	.send_dma_cmd = sbus_esp_send_dma_cmd,
	492	.dma_error = sbus_esp_dma_error,
	493	};
	494
	495	static int __devinit esp_sbus_probe_one(struct device *dev,
	496	struct sbus_dev *esp_dev,
334ae614	497	struct of_device *espdma,
cd9ad58d DM	498	struct sbus_bus *sbus,
	499	int hme)
	500	{
	501	struct scsi_host_template *tpnt = &scsi_esp_template;
	502	struct Scsi_Host *host;
	503	struct esp *esp;
	504	int err;
	505
	506	host = scsi_host_alloc(tpnt, sizeof(struct esp));
	507
	508	err = -ENOMEM;
	509	if (!host)
	510	goto fail;
	511
	512	host->max_id = (hme ? 16 : 8);
2b14ec78	513	esp = shost_priv(host);
cd9ad58d DM	514
	515	esp->host = host;
	516	esp->dev = esp_dev;
	517	esp->ops = &sbus_esp_ops;
	518
	519	if (hme)
	520	esp->flags \|= ESP_FLAG_WIDE_CAPABLE;
	521
334ae614	522	err = esp_sbus_setup_dma(esp, espdma);
cd9ad58d DM	523	if (err < 0)
	524	goto fail_unlink;
	525
	526	err = esp_sbus_map_regs(esp, hme);
	527	if (err < 0)
	528	goto fail_unlink;
	529
	530	err = esp_sbus_map_command_block(esp);
	531	if (err < 0)
	532	goto fail_unmap_regs;
	533
	534	err = esp_sbus_register_irq(esp);
	535	if (err < 0)
	536	goto fail_unmap_command_block;
	537
	538	esp_sbus_get_props(esp, espdma);
	539
	540	/* Before we try to touch the ESP chip, ESC1 dma can
	541	* come up with the reset bit set, so make sure that
	542	* is clear first.
	543	*/
334ae614	544	if (esp->dmarev == dvmaesc1) {
cd9ad58d DM	545	u32 val = dma_read32(DMA_CSR);
	546
	547	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	548	}
	549
	550	dev_set_drvdata(&esp_dev->ofdev.dev, esp);
	551
	552	err = scsi_esp_register(esp, dev);
	553	if (err)
	554	goto fail_free_irq;
	555
	556	return 0;
	557
	558	fail_free_irq:
	559	free_irq(host->irq, esp);
	560	fail_unmap_command_block:
7a715f46	561	sbus_free_consistent(&esp_dev->ofdev.dev, 16,
cd9ad58d DM	562	esp->command_block,
	563	esp->command_block_dma);
	564	fail_unmap_regs:
	565	sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE);
	566	fail_unlink:
	567	scsi_host_put(host);
	568	fail:
	569	return err;
	570	}
	571
	572	static int __devinit esp_sbus_probe(struct of_device dev, const struct of_device_id match)
	573	{
	574	struct sbus_dev *sdev = to_sbus_device(&dev->dev);
334ae614	575	struct device_node *dma_node = NULL;
cd9ad58d	576	struct device_node *dp = dev->node;
334ae614	577	struct of_device *dma_of = NULL;
cd9ad58d DM	578	int hme = 0;
	579
	580	if (dp->parent &&
	581	(!strcmp(dp->parent->name, "espdma") \|\|
	582	!strcmp(dp->parent->name, "dma")))
334ae614	583	dma_node = dp->parent;
cd9ad58d	584	else if (!strcmp(dp->name, "SUNW,fas")) {
334ae614	585	dma_node = sdev->ofdev.node;
cd9ad58d DM	586	hme = 1;
cd9ad58d DM	587	}
334ae614 DM	588	if (dma_node)
	589	dma_of = of_find_device_by_node(dma_node);
	590	if (!dma_of)
	591	return -ENODEV;
cd9ad58d	592
334ae614	593	return esp_sbus_probe_one(&dev->dev, sdev, dma_of,
cd9ad58d DM	594	sdev->bus, hme);
	595	}
	596
	597	static int __devexit esp_sbus_remove(struct of_device *dev)
	598	{
	599	struct esp *esp = dev_get_drvdata(&dev->dev);
7a715f46	600	struct sbus_dev *sdev = esp->dev;
334ae614	601	struct of_device *dma_of = esp->dma;
cd9ad58d DM	602	unsigned int irq = esp->host->irq;
	603	u32 val;
	604
	605	scsi_esp_unregister(esp);
	606
	607	/* Disable interrupts. */
	608	val = dma_read32(DMA_CSR);
	609	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
	610
	611	free_irq(irq, esp);
7a715f46	612	sbus_free_consistent(&sdev->ofdev.dev, 16,
cd9ad58d DM	613	esp->command_block,
	614	esp->command_block_dma);
	615	sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE);
334ae614 DM	616	of_iounmap(&dma_of->resource[0], esp->dma_regs,
334ae614 DM	617	resource_size(&dma_of->resource[0]));
cd9ad58d DM	618
	619	scsi_host_put(esp->host);
	620
	621	return 0;
	622	}
	623
	624	static struct of_device_id esp_match[] = {
	625	{
	626	.name = "SUNW,esp",
	627	},
	628	{
	629	.name = "SUNW,fas",
	630	},
	631	{
	632	.name = "esp",
	633	},
	634	{},
	635	};
	636	MODULE_DEVICE_TABLE(of, esp_match);
	637
	638	static struct of_platform_driver esp_sbus_driver = {
	639	.name = "esp",
	640	.match_table = esp_match,
	641	.probe = esp_sbus_probe,
	642	.remove = __devexit_p(esp_sbus_remove),
	643	};
	644
	645	static int __init sunesp_init(void)
	646	{
	647	return of_register_driver(&esp_sbus_driver, &sbus_bus_type);
	648	}
	649
	650	static void __exit sunesp_exit(void)
	651	{
	652	of_unregister_driver(&esp_sbus_driver);
	653	}
	654
	655	MODULE_DESCRIPTION("Sun ESP SCSI driver");
	656	MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
	657	MODULE_LICENSE("GPL");
	658	MODULE_VERSION(DRV_VERSION);
	659
	660	module_init(sunesp_init);
	661	module_exit(sunesp_exit);