]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/scsi/ufs/ufshcd.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
scsi: ufs: continue to boot even with Boot LUN is disabled
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
7ff5ab47
SJ		 48#define CREATE_TRACE_POINTS
49#include <trace/events/ufs.h>
50
dcea0bfb
GB		 51#define UFSHCD_REQ_SENSE_SIZE 18
52
2fbd009b
SJ		 53#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
54 UTP_TASK_REQ_COMPL |\
55 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 56/* UIC command timeout, unit: ms */
57#define UIC_CMD_TIMEOUT 500
2fbd009b 58
5a0b0cb9
SRT		 59/* NOP OUT retries waiting for NOP IN response */
60#define NOP_OUT_RETRIES 10
61/* Timeout after 30 msecs if NOP OUT hangs without response */
62#define NOP_OUT_TIMEOUT 30 /* msecs */
63
68078d5c 64/* Query request retries */
10fe5888 65#define QUERY_REQ_RETRIES 3
68078d5c 66/* Query request timeout */
10fe5888 67#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 68
e2933132
SRT		 69/* Task management command timeout */
70#define TM_CMD_TIMEOUT 100 /* msecs */
71
64238fbd
YG		 72/* maximum number of retries for a general UIC command */
73#define UFS_UIC_COMMAND_RETRIES 3
74
1d337ec2
SRT		 75/* maximum number of link-startup retries */
76#define DME_LINKSTARTUP_RETRIES 3
77
87d0b4a6
YG		 78/* Maximum retries for Hibern8 enter */
79#define UIC_HIBERN8_ENTER_RETRIES 3
80
1d337ec2
SRT		 81/* maximum number of reset retries before giving up */
82#define MAX_HOST_RESET_RETRIES 5
83
68078d5c
DR		 84/* Expose the flag value from utp_upiu_query.value */
85#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
86
7d568652
SJ		 87/* Interrupt aggregation default timeout, unit: 40us */
88#define INT_AGGR_DEF_TO 0x02
89
aa497613
SRT		 90#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
91 ({ \
92 int _ret; \
93 if (_on) \
94 _ret = ufshcd_enable_vreg(_dev, _vreg); \
95 else \
96 _ret = ufshcd_disable_vreg(_dev, _vreg); \
97 _ret; \
98 })
99
66cc820f
DR		 100#define ufshcd_hex_dump(prefix_str, buf, len) \
101print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false)
102
7a3e97b0
SY		 103enum {
104 UFSHCD_MAX_CHANNEL = 0,
105 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 106 UFSHCD_CMD_PER_LUN = 32,
107 UFSHCD_CAN_QUEUE = 32,
108};
109
110/* UFSHCD states */
111enum {
7a3e97b0
SY		 112 UFSHCD_STATE_RESET,
113 UFSHCD_STATE_ERROR,
3441da7d 114 UFSHCD_STATE_OPERATIONAL,
141f8165 115 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 116};
117
118/* UFSHCD error handling flags */
119enum {
120 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 121};
122
e8e7f271
SRT		 123/* UFSHCD UIC layer error flags */
124enum {
125 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 126 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
127 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
128 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
129 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
130 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 131};
132
3441da7d 133#define ufshcd_set_eh_in_progress(h) \
9c490d2d 134 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 135#define ufshcd_eh_in_progress(h) \
9c490d2d 136 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 137#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 138 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 139
57d104c1
SJ		 140#define ufshcd_set_ufs_dev_active(h) \
141 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
142#define ufshcd_set_ufs_dev_sleep(h) \
143 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
144#define ufshcd_set_ufs_dev_poweroff(h) \
145 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
146#define ufshcd_is_ufs_dev_active(h) \
147 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
148#define ufshcd_is_ufs_dev_sleep(h) \
149 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
150#define ufshcd_is_ufs_dev_poweroff(h) \
151 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
152
153static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
154 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
155 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
156 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
157 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
158 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
159 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
160};
161
162static inline enum ufs_dev_pwr_mode
163ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
164{
165 return ufs_pm_lvl_states[lvl].dev_state;
166}
167
168static inline enum uic_link_state
169ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
170{
171 return ufs_pm_lvl_states[lvl].link_state;
172}
173
0c8f7586
SJ		 174static inline enum ufs_pm_level
175ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
176 enum uic_link_state link_state)
177{
178 enum ufs_pm_level lvl;
179
180 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
181 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
182 (ufs_pm_lvl_states[lvl].link_state == link_state))
183 return lvl;
184 }
185
186 /* if no match found, return the level 0 */
187 return UFS_PM_LVL_0;
188}
189
56d4a186
SJ		 190static struct ufs_dev_fix ufs_fixups[] = {
191 /* UFS cards deviations table */
192 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
193 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
194 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
195 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
196 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
197 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
198 UFS_DEVICE_NO_FASTAUTO),
199 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
200 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
201 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
202 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
203 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
204 UFS_DEVICE_QUIRK_PA_TACTIVATE),
205 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
206 UFS_DEVICE_QUIRK_PA_TACTIVATE),
207 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
208 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
209 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
210
211 END_FIX
212};
213
3441da7d
SRT		 214static void ufshcd_tmc_handler(struct ufs_hba *hba);
215static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 216static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 217static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 218static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 219static void ufshcd_hba_exit(struct ufs_hba *hba);
220static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 221static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
222 bool skip_ref_clk);
223static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 224static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 225static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
226static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 227static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 228static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 229static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
230static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 231static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 232static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 233static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 234static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
235 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 236static int ufshcd_change_power_mode(struct ufs_hba *hba,
237 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 238static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
239{
240 return tag >= 0 && tag < hba->nutrs;
241}
57d104c1
SJ		 242
243static inline int ufshcd_enable_irq(struct ufs_hba *hba)
244{
245 int ret = 0;
246
247 if (!hba->is_irq_enabled) {
248 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
249 hba);
250 if (ret)
251 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
252 __func__, ret);
253 hba->is_irq_enabled = true;
254 }
255
256 return ret;
257}
258
259static inline void ufshcd_disable_irq(struct ufs_hba *hba)
260{
261 if (hba->is_irq_enabled) {
262 free_irq(hba->irq, hba);
263 hba->is_irq_enabled = false;
264 }
265}
3441da7d 266
b573d484
YG		 267/* replace non-printable or non-ASCII characters with spaces */
268static inline void ufshcd_remove_non_printable(char *val)
269{
270 if (!val)
271 return;
272
273 if (*val < 0x20 || *val > 0x7e)
274 *val = ' ';
275}
276
1a07f2d9
LS		 277static void ufshcd_add_command_trace(struct ufs_hba *hba,
278 unsigned int tag, const char *str)
279{
280 sector_t lba = -1;
281 u8 opcode = 0;
282 u32 intr, doorbell;
283 struct ufshcd_lrb *lrbp;
284 int transfer_len = -1;
285
286 if (!trace_ufshcd_command_enabled())
287 return;
288
289 lrbp = &hba->lrb[tag];
290
291 if (lrbp->cmd) { /* data phase exists */
292 opcode = (u8)(*lrbp->cmd->cmnd);
293 if ((opcode == READ_10) || (opcode == WRITE_10)) {
294 /*
295 * Currently we only fully trace read(10) and write(10)
296 * commands
297 */
298 if (lrbp->cmd->request && lrbp->cmd->request->bio)
299 lba =
300 lrbp->cmd->request->bio->bi_iter.bi_sector;
301 transfer_len = be32_to_cpu(
302 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
303 }
304 }
305
306 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
307 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
308 trace_ufshcd_command(dev_name(hba->dev), str, tag,
309 doorbell, transfer_len, intr, lba, opcode);
310}
311
ff8e20c6
DR		 312static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
313{
314 struct ufs_clk_info *clki;
315 struct list_head *head = &hba->clk_list_head;
316
566ec9ad 317 if (list_empty(head))
ff8e20c6
DR		 318 return;
319
320 list_for_each_entry(clki, head, list) {
321 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
322 clki->max_freq)
323 dev_err(hba->dev, "clk: %s, rate: %u\n",
324 clki->name, clki->curr_freq);
325 }
326}
327
328static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
329 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
330{
331 int i;
332
333 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
334 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
335
336 if (err_hist->reg[p] == 0)
337 continue;
338 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
339 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
340 }
341}
342
66cc820f
DR		 343static void ufshcd_print_host_regs(struct ufs_hba *hba)
344{
345 /*
346 * hex_dump reads its data without the readl macro. This might
347 * cause inconsistency issues on some platform, as the printed
348 * values may be from cache and not the most recent value.
349 * To know whether you are looking at an un-cached version verify
350 * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked
351 * during platform/pci probe function.
352 */
353 ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE);
354 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
355 hba->ufs_version, hba->capabilities);
356 dev_err(hba->dev,
357 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
358 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 359 dev_err(hba->dev,
360 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
361 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
362 hba->ufs_stats.hibern8_exit_cnt);
363
364 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
365 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
366 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
367 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
368 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
369
370 ufshcd_print_clk_freqs(hba);
371
372 if (hba->vops && hba->vops->dbg_register_dump)
373 hba->vops->dbg_register_dump(hba);
66cc820f
DR		 374}
375
376static
377void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
378{
379 struct ufshcd_lrb *lrbp;
7fabb77b 380 int prdt_length;
66cc820f
DR		 381 int tag;
382
383 for_each_set_bit(tag, &bitmap, hba->nutrs) {
384 lrbp = &hba->lrb[tag];
385
ff8e20c6
DR		 386 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
387 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 388 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
389 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 390 dev_err(hba->dev,
391 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
392 tag, (u64)lrbp->utrd_dma_addr);
393
66cc820f
DR		 394 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
395 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 396 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
397 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 398 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
399 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 400 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
401 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 402 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
403 sizeof(struct utp_upiu_rsp));
66cc820f 404
7fabb77b
GB		 405 prdt_length = le16_to_cpu(
406 lrbp->utr_descriptor_ptr->prd_table_length);
407 dev_err(hba->dev,
408 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
409 tag, prdt_length,
410 (u64)lrbp->ucd_prdt_dma_addr);
411
412 if (pr_prdt)
66cc820f 413 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 414 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 415 }
416}
417
418static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
419{
420 struct utp_task_req_desc *tmrdp;
421 int tag;
422
423 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
424 tmrdp = &hba->utmrdl_base_addr[tag];
425 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
426 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
427 sizeof(struct request_desc_header));
428 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
429 tag);
430 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
431 sizeof(struct utp_upiu_req));
432 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
433 tag);
434 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
435 sizeof(struct utp_task_req_desc));
436 }
437}
438
6ba65588
GB		 439static void ufshcd_print_host_state(struct ufs_hba *hba)
440{
441 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
442 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
e002e651 443 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 444 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
445 hba->saved_err, hba->saved_uic_err);
446 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
447 hba->curr_dev_pwr_mode, hba->uic_link_state);
448 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
449 hba->pm_op_in_progress, hba->is_sys_suspended);
450 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
451 hba->auto_bkops_enabled, hba->host->host_self_blocked);
452 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
453 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
454 hba->eh_flags, hba->req_abort_count);
455 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
456 hba->capabilities, hba->caps);
457 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
458 hba->dev_quirks);
459}
460
ff8e20c6
DR		 461/**
462 * ufshcd_print_pwr_info - print power params as saved in hba
463 * power info
464 * @hba: per-adapter instance
465 */
466static void ufshcd_print_pwr_info(struct ufs_hba *hba)
467{
468 static const char * const names[] = {
469 "INVALID MODE",
470 "FAST MODE",
471 "SLOW_MODE",
472 "INVALID MODE",
473 "FASTAUTO_MODE",
474 "SLOWAUTO_MODE",
475 "INVALID MODE",
476 };
477
478 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
479 __func__,
480 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
481 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
482 names[hba->pwr_info.pwr_rx],
483 names[hba->pwr_info.pwr_tx],
484 hba->pwr_info.hs_rate);
485}
486
5a0b0cb9
SRT		 487/*
488 * ufshcd_wait_for_register - wait for register value to change
489 * @hba - per-adapter interface
490 * @reg - mmio register offset
491 * @mask - mask to apply to read register value
492 * @val - wait condition
493 * @interval_us - polling interval in microsecs
494 * @timeout_ms - timeout in millisecs
596585a2 495 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 496 *
497 * Returns -ETIMEDOUT on error, zero on success
498 */
596585a2
YG		 499int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
500 u32 val, unsigned long interval_us,
501 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 502{
503 int err = 0;
504 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
505
506 /* ignore bits that we don't intend to wait on */
507 val = val & mask;
508
509 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 510 if (can_sleep)
511 usleep_range(interval_us, interval_us + 50);
512 else
513 udelay(interval_us);
5a0b0cb9
SRT		 514 if (time_after(jiffies, timeout)) {
515 if ((ufshcd_readl(hba, reg) & mask) != val)
516 err = -ETIMEDOUT;
517 break;
518 }
519 }
520
521 return err;
522}
523
2fbd009b
SJ		 524/**
525 * ufshcd_get_intr_mask - Get the interrupt bit mask
526 * @hba - Pointer to adapter instance
527 *
528 * Returns interrupt bit mask per version
529 */
530static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
531{
c01848c6
YG		 532 u32 intr_mask = 0;
533
534 switch (hba->ufs_version) {
535 case UFSHCI_VERSION_10:
536 intr_mask = INTERRUPT_MASK_ALL_VER_10;
537 break;
c01848c6
YG		 538 case UFSHCI_VERSION_11:
539 case UFSHCI_VERSION_20:
540 intr_mask = INTERRUPT_MASK_ALL_VER_11;
541 break;
c01848c6
YG		 542 case UFSHCI_VERSION_21:
543 default:
544 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 545 break;
c01848c6
YG		 546 }
547
548 return intr_mask;
2fbd009b
SJ		 549}
550
7a3e97b0
SY		 551/**
552 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
553 * @hba - Pointer to adapter instance
554 *
555 * Returns UFSHCI version supported by the controller
556 */
557static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
558{
0263bcd0
YG		 559 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
560 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 561
b873a275 562 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 563}
564
565/**
566 * ufshcd_is_device_present - Check if any device connected to
567 * the host controller
5c0c28a8 568 * @hba: pointer to adapter instance
7a3e97b0 569 *
c9e6010b 570 * Returns true if device present, false if no device detected
7a3e97b0 571 */
c9e6010b 572static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 573{
5c0c28a8 574 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 575 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 576}
577
578/**
579 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
580 * @lrb: pointer to local command reference block
581 *
582 * This function is used to get the OCS field from UTRD
583 * Returns the OCS field in the UTRD
584 */
585static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
586{
e8c8e82a 587 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 588}
589
590/**
591 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
592 * @task_req_descp: pointer to utp_task_req_desc structure
593 *
594 * This function is used to get the OCS field from UTMRD
595 * Returns the OCS field in the UTMRD
596 */
597static inline int
598ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
599{
e8c8e82a 600 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 601}
602
603/**
604 * ufshcd_get_tm_free_slot - get a free slot for task management request
605 * @hba: per adapter instance
e2933132 606 * @free_slot: pointer to variable with available slot value
7a3e97b0 607 *
e2933132
SRT		 608 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
609 * Returns 0 if free slot is not available, else return 1 with tag value
610 * in @free_slot.
7a3e97b0 611 */
e2933132 612static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 613{
e2933132
SRT		 614 int tag;
615 bool ret = false;
616
617 if (!free_slot)
618 goto out;
619
620 do {
621 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
622 if (tag >= hba->nutmrs)
623 goto out;
624 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
625
626 *free_slot = tag;
627 ret = true;
628out:
629 return ret;
630}
631
632static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
633{
634 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 635}
636
637/**
638 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
639 * @hba: per adapter instance
640 * @pos: position of the bit to be cleared
641 */
642static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
643{
b873a275 644 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 645}
646
a48353f6
YG		 647/**
648 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
649 * @hba: per adapter instance
650 * @tag: position of the bit to be cleared
651 */
652static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
653{
654 __clear_bit(tag, &hba->outstanding_reqs);
655}
656
7a3e97b0
SY		 657/**
658 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
659 * @reg: Register value of host controller status
660 *
661 * Returns integer, 0 on Success and positive value if failed
662 */
663static inline int ufshcd_get_lists_status(u32 reg)
664{
6cf16115 665 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 666}
667
668/**
669 * ufshcd_get_uic_cmd_result - Get the UIC command result
670 * @hba: Pointer to adapter instance
671 *
672 * This function gets the result of UIC command completion
673 * Returns 0 on success, non zero value on error
674 */
675static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
676{
b873a275 677 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 678 MASK_UIC_COMMAND_RESULT;
679}
680
12b4fdb4
SJ		 681/**
682 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
683 * @hba: Pointer to adapter instance
684 *
685 * This function gets UIC command argument3
686 * Returns 0 on success, non zero value on error
687 */
688static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
689{
690 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
691}
692
7a3e97b0 693/**
5a0b0cb9 694 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 695 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 696 */
697static inline int
5a0b0cb9 698ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 699{
5a0b0cb9 700 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 701}
702
703/**
704 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
705 * @ucd_rsp_ptr: pointer to response UPIU
706 *
707 * This function gets the response status and scsi_status from response UPIU
708 * Returns the response result code.
709 */
710static inline int
711ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
712{
713 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
714}
715
1c2623c5
SJ		 716/*
717 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
718 * from response UPIU
719 * @ucd_rsp_ptr: pointer to response UPIU
720 *
721 * Return the data segment length.
722 */
723static inline unsigned int
724ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
725{
726 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
727 MASK_RSP_UPIU_DATA_SEG_LEN;
728}
729
66ec6d59
SRT		 730/**
731 * ufshcd_is_exception_event - Check if the device raised an exception event
732 * @ucd_rsp_ptr: pointer to response UPIU
733 *
734 * The function checks if the device raised an exception event indicated in
735 * the Device Information field of response UPIU.
736 *
737 * Returns true if exception is raised, false otherwise.
738 */
739static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
740{
741 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
742 MASK_RSP_EXCEPTION_EVENT ? true : false;
743}
744
7a3e97b0 745/**
7d568652 746 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 747 * @hba: per adapter instance
7a3e97b0
SY		 748 */
749static inline void
7d568652 750ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 751{
7d568652
SJ		 752 ufshcd_writel(hba, INT_AGGR_ENABLE |
753 INT_AGGR_COUNTER_AND_TIMER_RESET,
754 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
755}
756
757/**
758 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
759 * @hba: per adapter instance
760 * @cnt: Interrupt aggregation counter threshold
761 * @tmout: Interrupt aggregation timeout value
762 */
763static inline void
764ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
765{
766 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
767 INT_AGGR_COUNTER_THLD_VAL(cnt) |
768 INT_AGGR_TIMEOUT_VAL(tmout),
769 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 770}
771
b852190e
YG		 772/**
773 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
774 * @hba: per adapter instance
775 */
776static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
777{
778 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
779}
780
7a3e97b0
SY		 781/**
782 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
783 * When run-stop registers are set to 1, it indicates the
784 * host controller that it can process the requests
785 * @hba: per adapter instance
786 */
787static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
788{
b873a275
SJ		 789 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
790 REG_UTP_TASK_REQ_LIST_RUN_STOP);
791 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
792 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 793}
794
7a3e97b0
SY		 795/**
796 * ufshcd_hba_start - Start controller initialization sequence
797 * @hba: per adapter instance
798 */
799static inline void ufshcd_hba_start(struct ufs_hba *hba)
800{
b873a275 801 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 802}
803
804/**
805 * ufshcd_is_hba_active - Get controller state
806 * @hba: per adapter instance
807 *
c9e6010b 808 * Returns false if controller is active, true otherwise
7a3e97b0 809 */
c9e6010b 810static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 811{
4a8eec2b
TK		 812 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
813 ? false : true;
7a3e97b0
SY		 814}
815
09690d5a
SJ		 816static const char *ufschd_uic_link_state_to_string(
817 enum uic_link_state state)
818{
819 switch (state) {
820 case UIC_LINK_OFF_STATE: return "OFF";
821 case UIC_LINK_ACTIVE_STATE: return "ACTIVE";
822 case UIC_LINK_HIBERN8_STATE: return "HIBERN8";
823 default: return "UNKNOWN";
824 }
825}
826
827static const char *ufschd_ufs_dev_pwr_mode_to_string(
828 enum ufs_dev_pwr_mode state)
829{
830 switch (state) {
831 case UFS_ACTIVE_PWR_MODE: return "ACTIVE";
832 case UFS_SLEEP_PWR_MODE: return "SLEEP";
833 case UFS_POWERDOWN_PWR_MODE: return "POWERDOWN";
834 default: return "UNKNOWN";
835 }
836}
837
37113106
YG		 838u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
839{
840 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
841 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
842 (hba->ufs_version == UFSHCI_VERSION_11))
843 return UFS_UNIPRO_VER_1_41;
844 else
845 return UFS_UNIPRO_VER_1_6;
846}
847EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
848
849static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
850{
851 /*
852 * If both host and device support UniPro ver1.6 or later, PA layer
853 * parameters tuning happens during link startup itself.
854 *
855 * We can manually tune PA layer parameters if either host or device
856 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
857 * logic simple, we will only do manual tuning if local unipro version
858 * doesn't support ver1.6 or later.
859 */
860 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
861 return true;
862 else
863 return false;
864}
865
a3cd5ec5
SJ		 866static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
867{
868 int ret = 0;
869 struct ufs_clk_info *clki;
870 struct list_head *head = &hba->clk_list_head;
871 ktime_t start = ktime_get();
872 bool clk_state_changed = false;
873
566ec9ad 874 if (list_empty(head))
a3cd5ec5
SJ		 875 goto out;
876
877 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
878 if (ret)
879 return ret;
880
881 list_for_each_entry(clki, head, list) {
882 if (!IS_ERR_OR_NULL(clki->clk)) {
883 if (scale_up && clki->max_freq) {
884 if (clki->curr_freq == clki->max_freq)
885 continue;
886
887 clk_state_changed = true;
888 ret = clk_set_rate(clki->clk, clki->max_freq);
889 if (ret) {
890 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
891 __func__, clki->name,
892 clki->max_freq, ret);
893 break;
894 }
895 trace_ufshcd_clk_scaling(dev_name(hba->dev),
896 "scaled up", clki->name,
897 clki->curr_freq,
898 clki->max_freq);
899
900 clki->curr_freq = clki->max_freq;
901
902 } else if (!scale_up && clki->min_freq) {
903 if (clki->curr_freq == clki->min_freq)
904 continue;
905
906 clk_state_changed = true;
907 ret = clk_set_rate(clki->clk, clki->min_freq);
908 if (ret) {
909 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
910 __func__, clki->name,
911 clki->min_freq, ret);
912 break;
913 }
914 trace_ufshcd_clk_scaling(dev_name(hba->dev),
915 "scaled down", clki->name,
916 clki->curr_freq,
917 clki->min_freq);
918 clki->curr_freq = clki->min_freq;
919 }
920 }
921 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
922 clki->name, clk_get_rate(clki->clk));
923 }
924
925 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
926
927out:
928 if (clk_state_changed)
929 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
930 (scale_up ? "up" : "down"),
931 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
932 return ret;
933}
934
935/**
936 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
937 * @hba: per adapter instance
938 * @scale_up: True if scaling up and false if scaling down
939 *
940 * Returns true if scaling is required, false otherwise.
941 */
942static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
943 bool scale_up)
944{
945 struct ufs_clk_info *clki;
946 struct list_head *head = &hba->clk_list_head;
947
566ec9ad 948 if (list_empty(head))
a3cd5ec5
SJ		 949 return false;
950
951 list_for_each_entry(clki, head, list) {
952 if (!IS_ERR_OR_NULL(clki->clk)) {
953 if (scale_up && clki->max_freq) {
954 if (clki->curr_freq == clki->max_freq)
955 continue;
956 return true;
957 } else if (!scale_up && clki->min_freq) {
958 if (clki->curr_freq == clki->min_freq)
959 continue;
960 return true;
961 }
962 }
963 }
964
965 return false;
966}
967
968static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
969 u64 wait_timeout_us)
970{
971 unsigned long flags;
972 int ret = 0;
973 u32 tm_doorbell;
974 u32 tr_doorbell;
975 bool timeout = false, do_last_check = false;
976 ktime_t start;
977
978 ufshcd_hold(hba, false);
979 spin_lock_irqsave(hba->host->host_lock, flags);
980 /*
981 * Wait for all the outstanding tasks/transfer requests.
982 * Verify by checking the doorbell registers are clear.
983 */
984 start = ktime_get();
985 do {
986 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
987 ret = -EBUSY;
988 goto out;
989 }
990
991 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
992 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
993 if (!tm_doorbell && !tr_doorbell) {
994 timeout = false;
995 break;
996 } else if (do_last_check) {
997 break;
998 }
999
1000 spin_unlock_irqrestore(hba->host->host_lock, flags);
1001 schedule();
1002 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1003 wait_timeout_us) {
1004 timeout = true;
1005 /*
1006 * We might have scheduled out for long time so make
1007 * sure to check if doorbells are cleared by this time
1008 * or not.
1009 */
1010 do_last_check = true;
1011 }
1012 spin_lock_irqsave(hba->host->host_lock, flags);
1013 } while (tm_doorbell || tr_doorbell);
1014
1015 if (timeout) {
1016 dev_err(hba->dev,
1017 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1018 __func__, tm_doorbell, tr_doorbell);
1019 ret = -EBUSY;
1020 }
1021out:
1022 spin_unlock_irqrestore(hba->host->host_lock, flags);
1023 ufshcd_release(hba);
1024 return ret;
1025}
1026
1027/**
1028 * ufshcd_scale_gear - scale up/down UFS gear
1029 * @hba: per adapter instance
1030 * @scale_up: True for scaling up gear and false for scaling down
1031 *
1032 * Returns 0 for success,
1033 * Returns -EBUSY if scaling can't happen at this time
1034 * Returns non-zero for any other errors
1035 */
1036static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1037{
1038 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1039 int ret = 0;
1040 struct ufs_pa_layer_attr new_pwr_info;
1041
1042 if (scale_up) {
1043 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1044 sizeof(struct ufs_pa_layer_attr));
1045 } else {
1046 memcpy(&new_pwr_info, &hba->pwr_info,
1047 sizeof(struct ufs_pa_layer_attr));
1048
1049 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1050 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1051 /* save the current power mode */
1052 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1053 &hba->pwr_info,
1054 sizeof(struct ufs_pa_layer_attr));
1055
1056 /* scale down gear */
1057 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1058 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1059 }
1060 }
1061
1062 /* check if the power mode needs to be changed or not? */
1063 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1064
1065 if (ret)
1066 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1067 __func__, ret,
1068 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1069 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1070
1071 return ret;
1072}
1073
1074static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1075{
1076 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1077 int ret = 0;
1078 /*
1079 * make sure that there are no outstanding requests when
1080 * clock scaling is in progress
1081 */
1082 scsi_block_requests(hba->host);
1083 down_write(&hba->clk_scaling_lock);
1084 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1085 ret = -EBUSY;
1086 up_write(&hba->clk_scaling_lock);
1087 scsi_unblock_requests(hba->host);
1088 }
1089
1090 return ret;
1091}
1092
1093static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1094{
1095 up_write(&hba->clk_scaling_lock);
1096 scsi_unblock_requests(hba->host);
1097}
1098
1099/**
1100 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1101 * @hba: per adapter instance
1102 * @scale_up: True for scaling up and false for scalin down
1103 *
1104 * Returns 0 for success,
1105 * Returns -EBUSY if scaling can't happen at this time
1106 * Returns non-zero for any other errors
1107 */
1108static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1109{
1110 int ret = 0;
1111
401f1e44
SJ		 1112 /* let's not get into low power until clock scaling is completed */
1113 ufshcd_hold(hba, false);
1114
a3cd5ec5
SJ		 1115 ret = ufshcd_clock_scaling_prepare(hba);
1116 if (ret)
1117 return ret;
1118
1119 /* scale down the gear before scaling down clocks */
1120 if (!scale_up) {
1121 ret = ufshcd_scale_gear(hba, false);
1122 if (ret)
1123 goto out;
1124 }
1125
1126 ret = ufshcd_scale_clks(hba, scale_up);
1127 if (ret) {
1128 if (!scale_up)
1129 ufshcd_scale_gear(hba, true);
1130 goto out;
1131 }
1132
1133 /* scale up the gear after scaling up clocks */
1134 if (scale_up) {
1135 ret = ufshcd_scale_gear(hba, true);
1136 if (ret) {
1137 ufshcd_scale_clks(hba, false);
1138 goto out;
1139 }
1140 }
1141
1142 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1143
1144out:
1145 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1146 ufshcd_release(hba);
a3cd5ec5
SJ		 1147 return ret;
1148}
1149
401f1e44
SJ		 1150static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1151{
1152 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1153 clk_scaling.suspend_work);
1154 unsigned long irq_flags;
1155
1156 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1157 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1158 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1159 return;
1160 }
1161 hba->clk_scaling.is_suspended = true;
1162 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1163
1164 __ufshcd_suspend_clkscaling(hba);
1165}
1166
1167static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1168{
1169 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1170 clk_scaling.resume_work);
1171 unsigned long irq_flags;
1172
1173 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1174 if (!hba->clk_scaling.is_suspended) {
1175 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1176 return;
1177 }
1178 hba->clk_scaling.is_suspended = false;
1179 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1180
1181 devfreq_resume_device(hba->devfreq);
1182}
1183
a3cd5ec5
SJ		 1184static int ufshcd_devfreq_target(struct device *dev,
1185 unsigned long *freq, u32 flags)
1186{
1187 int ret = 0;
1188 struct ufs_hba *hba = dev_get_drvdata(dev);
1189 ktime_t start;
401f1e44 1190 bool scale_up, sched_clk_scaling_suspend_work = false;
a3cd5ec5
SJ		 1191 unsigned long irq_flags;
1192
1193 if (!ufshcd_is_clkscaling_supported(hba))
1194 return -EINVAL;
1195
1196 if ((*freq > 0) && (*freq < UINT_MAX)) {
1197 dev_err(hba->dev, "%s: invalid freq = %lu\n", __func__, *freq);
1198 return -EINVAL;
1199 }
1200
a3cd5ec5
SJ		 1201 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1202 if (ufshcd_eh_in_progress(hba)) {
1203 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1204 return 0;
1205 }
1206
401f1e44
SJ		 1207 if (!hba->clk_scaling.active_reqs)
1208 sched_clk_scaling_suspend_work = true;
1209
1210 scale_up = (*freq == UINT_MAX) ? true : false;
1211 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1212 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1213 ret = 0;
1214 goto out; /* no state change required */
a3cd5ec5
SJ		 1215 }
1216 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1217
1218 start = ktime_get();
a3cd5ec5
SJ		 1219 ret = ufshcd_devfreq_scale(hba, scale_up);
1220
a3cd5ec5
SJ		 1221 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1222 (scale_up ? "up" : "down"),
1223 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1224
401f1e44
SJ		 1225out:
1226 if (sched_clk_scaling_suspend_work)
1227 queue_work(hba->clk_scaling.workq,
1228 &hba->clk_scaling.suspend_work);
1229
a3cd5ec5
SJ		 1230 return ret;
1231}
1232
1233
1234static int ufshcd_devfreq_get_dev_status(struct device *dev,
1235 struct devfreq_dev_status *stat)
1236{
1237 struct ufs_hba *hba = dev_get_drvdata(dev);
1238 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1239 unsigned long flags;
1240
1241 if (!ufshcd_is_clkscaling_supported(hba))
1242 return -EINVAL;
1243
1244 memset(stat, 0, sizeof(*stat));
1245
1246 spin_lock_irqsave(hba->host->host_lock, flags);
1247 if (!scaling->window_start_t)
1248 goto start_window;
1249
1250 if (scaling->is_busy_started)
1251 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1252 scaling->busy_start_t));
1253
1254 stat->total_time = jiffies_to_usecs((long)jiffies -
1255 (long)scaling->window_start_t);
1256 stat->busy_time = scaling->tot_busy_t;
1257start_window:
1258 scaling->window_start_t = jiffies;
1259 scaling->tot_busy_t = 0;
1260
1261 if (hba->outstanding_reqs) {
1262 scaling->busy_start_t = ktime_get();
1263 scaling->is_busy_started = true;
1264 } else {
1265 scaling->busy_start_t = 0;
1266 scaling->is_busy_started = false;
1267 }
1268 spin_unlock_irqrestore(hba->host->host_lock, flags);
1269 return 0;
1270}
1271
1272static struct devfreq_dev_profile ufs_devfreq_profile = {
1273 .polling_ms = 100,
1274 .target = ufshcd_devfreq_target,
1275 .get_dev_status = ufshcd_devfreq_get_dev_status,
1276};
1277
401f1e44
SJ		 1278static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1279{
1280 unsigned long flags;
1281
1282 devfreq_suspend_device(hba->devfreq);
1283 spin_lock_irqsave(hba->host->host_lock, flags);
1284 hba->clk_scaling.window_start_t = 0;
1285 spin_unlock_irqrestore(hba->host->host_lock, flags);
1286}
a3cd5ec5 1287
a508253d
GB		 1288static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1289{
401f1e44
SJ		 1290 unsigned long flags;
1291 bool suspend = false;
1292
fcb0c4b0
ST		 1293 if (!ufshcd_is_clkscaling_supported(hba))
1294 return;
1295
401f1e44
SJ		 1296 spin_lock_irqsave(hba->host->host_lock, flags);
1297 if (!hba->clk_scaling.is_suspended) {
1298 suspend = true;
1299 hba->clk_scaling.is_suspended = true;
1300 }
1301 spin_unlock_irqrestore(hba->host->host_lock, flags);
1302
1303 if (suspend)
1304 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1305}
1306
1307static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1308{
401f1e44
SJ		 1309 unsigned long flags;
1310 bool resume = false;
1311
1312 if (!ufshcd_is_clkscaling_supported(hba))
1313 return;
1314
1315 spin_lock_irqsave(hba->host->host_lock, flags);
1316 if (hba->clk_scaling.is_suspended) {
1317 resume = true;
1318 hba->clk_scaling.is_suspended = false;
1319 }
1320 spin_unlock_irqrestore(hba->host->host_lock, flags);
1321
1322 if (resume)
1323 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1324}
1325
1326static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1327 struct device_attribute *attr, char *buf)
1328{
1329 struct ufs_hba *hba = dev_get_drvdata(dev);
1330
1331 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1332}
1333
1334static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1335 struct device_attribute *attr, const char *buf, size_t count)
1336{
1337 struct ufs_hba *hba = dev_get_drvdata(dev);
1338 u32 value;
1339 int err;
1340
1341 if (kstrtou32(buf, 0, &value))
1342 return -EINVAL;
1343
1344 value = !!value;
1345 if (value == hba->clk_scaling.is_allowed)
1346 goto out;
1347
1348 pm_runtime_get_sync(hba->dev);
1349 ufshcd_hold(hba, false);
1350
401f1e44
SJ		 1351 cancel_work_sync(&hba->clk_scaling.suspend_work);
1352 cancel_work_sync(&hba->clk_scaling.resume_work);
1353
1354 hba->clk_scaling.is_allowed = value;
1355
fcb0c4b0
ST		 1356 if (value) {
1357 ufshcd_resume_clkscaling(hba);
1358 } else {
1359 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1360 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1361 if (err)
1362 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1363 __func__, err);
1364 }
fcb0c4b0
ST		 1365
1366 ufshcd_release(hba);
1367 pm_runtime_put_sync(hba->dev);
1368out:
1369 return count;
a508253d
GB		 1370}
1371
a3cd5ec5
SJ		 1372static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1373{
1374 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1375 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1376 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1377 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1378 hba->clk_scaling.enable_attr.attr.mode = 0644;
1379 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1380 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1381}
1382
1ab27c9c
ST		 1383static void ufshcd_ungate_work(struct work_struct *work)
1384{
1385 int ret;
1386 unsigned long flags;
1387 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1388 clk_gating.ungate_work);
1389
1390 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1391
1392 spin_lock_irqsave(hba->host->host_lock, flags);
1393 if (hba->clk_gating.state == CLKS_ON) {
1394 spin_unlock_irqrestore(hba->host->host_lock, flags);
1395 goto unblock_reqs;
1396 }
1397
1398 spin_unlock_irqrestore(hba->host->host_lock, flags);
1399 ufshcd_setup_clocks(hba, true);
1400
1401 /* Exit from hibern8 */
1402 if (ufshcd_can_hibern8_during_gating(hba)) {
1403 /* Prevent gating in this path */
1404 hba->clk_gating.is_suspended = true;
1405 if (ufshcd_is_link_hibern8(hba)) {
1406 ret = ufshcd_uic_hibern8_exit(hba);
1407 if (ret)
1408 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1409 __func__, ret);
1410 else
1411 ufshcd_set_link_active(hba);
1412 }
1413 hba->clk_gating.is_suspended = false;
1414 }
1415unblock_reqs:
1416 scsi_unblock_requests(hba->host);
1417}
1418
1419/**
1420 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1421 * Also, exit from hibern8 mode and set the link as active.
1422 * @hba: per adapter instance
1423 * @async: This indicates whether caller should ungate clocks asynchronously.
1424 */
1425int ufshcd_hold(struct ufs_hba *hba, bool async)
1426{
1427 int rc = 0;
1428 unsigned long flags;
1429
1430 if (!ufshcd_is_clkgating_allowed(hba))
1431 goto out;
1ab27c9c
ST		 1432 spin_lock_irqsave(hba->host->host_lock, flags);
1433 hba->clk_gating.active_reqs++;
1434
53c12d0e
YG		 1435 if (ufshcd_eh_in_progress(hba)) {
1436 spin_unlock_irqrestore(hba->host->host_lock, flags);
1437 return 0;
1438 }
1439
856b3483 1440start:
1ab27c9c
ST		 1441 switch (hba->clk_gating.state) {
1442 case CLKS_ON:
f2a785ac
VG		 1443 /*
1444 * Wait for the ungate work to complete if in progress.
1445 * Though the clocks may be in ON state, the link could
1446 * still be in hibner8 state if hibern8 is allowed
1447 * during clock gating.
1448 * Make sure we exit hibern8 state also in addition to
1449 * clocks being ON.
1450 */
1451 if (ufshcd_can_hibern8_during_gating(hba) &&
1452 ufshcd_is_link_hibern8(hba)) {
1453 spin_unlock_irqrestore(hba->host->host_lock, flags);
1454 flush_work(&hba->clk_gating.ungate_work);
1455 spin_lock_irqsave(hba->host->host_lock, flags);
1456 goto start;
1457 }
1ab27c9c
ST		 1458 break;
1459 case REQ_CLKS_OFF:
1460 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1461 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1462 trace_ufshcd_clk_gating(dev_name(hba->dev),
1463 hba->clk_gating.state);
1ab27c9c
ST		 1464 break;
1465 }
1466 /*
9c490d2d 1467 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1468 * currently running. Hence, fall through to cancel gating
1469 * work and to enable clocks.
1470 */
1471 case CLKS_OFF:
1472 scsi_block_requests(hba->host);
1473 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47
SJ		 1474 trace_ufshcd_clk_gating(dev_name(hba->dev),
1475 hba->clk_gating.state);
1ab27c9c
ST		 1476 schedule_work(&hba->clk_gating.ungate_work);
1477 /*
1478 * fall through to check if we should wait for this
1479 * work to be done or not.
1480 */
1481 case REQ_CLKS_ON:
1482 if (async) {
1483 rc = -EAGAIN;
1484 hba->clk_gating.active_reqs--;
1485 break;
1486 }
1487
1488 spin_unlock_irqrestore(hba->host->host_lock, flags);
1489 flush_work(&hba->clk_gating.ungate_work);
1490 /* Make sure state is CLKS_ON before returning */
856b3483 1491 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1492 goto start;
1493 default:
1494 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1495 __func__, hba->clk_gating.state);
1496 break;
1497 }
1498 spin_unlock_irqrestore(hba->host->host_lock, flags);
1499out:
1500 return rc;
1501}
6e3fd44d 1502EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1503
1504static void ufshcd_gate_work(struct work_struct *work)
1505{
1506 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1507 clk_gating.gate_work.work);
1508 unsigned long flags;
1509
1510 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1511 /*
1512 * In case you are here to cancel this work the gating state
1513 * would be marked as REQ_CLKS_ON. In this case save time by
1514 * skipping the gating work and exit after changing the clock
1515 * state to CLKS_ON.
1516 */
1517 if (hba->clk_gating.is_suspended ||
1518 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1519 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1520 trace_ufshcd_clk_gating(dev_name(hba->dev),
1521 hba->clk_gating.state);
1ab27c9c
ST		 1522 goto rel_lock;
1523 }
1524
1525 if (hba->clk_gating.active_reqs
1526 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1527 || hba->lrb_in_use || hba->outstanding_tasks
1528 || hba->active_uic_cmd || hba->uic_async_done)
1529 goto rel_lock;
1530
1531 spin_unlock_irqrestore(hba->host->host_lock, flags);
1532
1533 /* put the link into hibern8 mode before turning off clocks */
1534 if (ufshcd_can_hibern8_during_gating(hba)) {
1535 if (ufshcd_uic_hibern8_enter(hba)) {
1536 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1537 trace_ufshcd_clk_gating(dev_name(hba->dev),
1538 hba->clk_gating.state);
1ab27c9c
ST		 1539 goto out;
1540 }
1541 ufshcd_set_link_hibern8(hba);
1542 }
1543
1544 if (!ufshcd_is_link_active(hba))
1545 ufshcd_setup_clocks(hba, false);
1546 else
1547 /* If link is active, device ref_clk can't be switched off */
1548 __ufshcd_setup_clocks(hba, false, true);
1549
1550 /*
1551 * In case you are here to cancel this work the gating state
1552 * would be marked as REQ_CLKS_ON. In this case keep the state
1553 * as REQ_CLKS_ON which would anyway imply that clocks are off
1554 * and a request to turn them on is pending. By doing this way,
1555 * we keep the state machine in tact and this would ultimately
1556 * prevent from doing cancel work multiple times when there are
1557 * new requests arriving before the current cancel work is done.
1558 */
1559 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1560 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1561 hba->clk_gating.state = CLKS_OFF;
7ff5ab47
SJ		 1562 trace_ufshcd_clk_gating(dev_name(hba->dev),
1563 hba->clk_gating.state);
1564 }
1ab27c9c
ST		 1565rel_lock:
1566 spin_unlock_irqrestore(hba->host->host_lock, flags);
1567out:
1568 return;
1569}
1570
1571/* host lock must be held before calling this variant */
1572static void __ufshcd_release(struct ufs_hba *hba)
1573{
1574 if (!ufshcd_is_clkgating_allowed(hba))
1575 return;
1576
1577 hba->clk_gating.active_reqs--;
1578
1579 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1580 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1581 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 1582 || hba->active_uic_cmd || hba->uic_async_done
1583 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1584 return;
1585
1586 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1587 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1ab27c9c
ST		 1588 schedule_delayed_work(&hba->clk_gating.gate_work,
1589 msecs_to_jiffies(hba->clk_gating.delay_ms));
1590}
1591
1592void ufshcd_release(struct ufs_hba *hba)
1593{
1594 unsigned long flags;
1595
1596 spin_lock_irqsave(hba->host->host_lock, flags);
1597 __ufshcd_release(hba);
1598 spin_unlock_irqrestore(hba->host->host_lock, flags);
1599}
6e3fd44d 1600EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1601
1602static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1603 struct device_attribute *attr, char *buf)
1604{
1605 struct ufs_hba *hba = dev_get_drvdata(dev);
1606
1607 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1608}
1609
1610static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1611 struct device_attribute *attr, const char *buf, size_t count)
1612{
1613 struct ufs_hba *hba = dev_get_drvdata(dev);
1614 unsigned long flags, value;
1615
1616 if (kstrtoul(buf, 0, &value))
1617 return -EINVAL;
1618
1619 spin_lock_irqsave(hba->host->host_lock, flags);
1620 hba->clk_gating.delay_ms = value;
1621 spin_unlock_irqrestore(hba->host->host_lock, flags);
1622 return count;
1623}
1624
b427411a
ST		 1625static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1626 struct device_attribute *attr, char *buf)
1627{
1628 struct ufs_hba *hba = dev_get_drvdata(dev);
1629
1630 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1631}
1632
1633static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1634 struct device_attribute *attr, const char *buf, size_t count)
1635{
1636 struct ufs_hba *hba = dev_get_drvdata(dev);
1637 unsigned long flags;
1638 u32 value;
1639
1640 if (kstrtou32(buf, 0, &value))
1641 return -EINVAL;
1642
1643 value = !!value;
1644 if (value == hba->clk_gating.is_enabled)
1645 goto out;
1646
1647 if (value) {
1648 ufshcd_release(hba);
1649 } else {
1650 spin_lock_irqsave(hba->host->host_lock, flags);
1651 hba->clk_gating.active_reqs++;
1652 spin_unlock_irqrestore(hba->host->host_lock, flags);
1653 }
1654
1655 hba->clk_gating.is_enabled = value;
1656out:
1657 return count;
1658}
1659
1ab27c9c
ST		 1660static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1661{
1662 if (!ufshcd_is_clkgating_allowed(hba))
1663 return;
1664
1665 hba->clk_gating.delay_ms = 150;
1666 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1667 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1668
b427411a
ST		 1669 hba->clk_gating.is_enabled = true;
1670
1ab27c9c
ST		 1671 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1672 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1673 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1674 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1675 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1676 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1677 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1678
1679 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1680 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1681 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1682 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1683 hba->clk_gating.enable_attr.attr.mode = 0644;
1684 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1685 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1686}
1687
1688static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1689{
1690 if (!ufshcd_is_clkgating_allowed(hba))
1691 return;
1692 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1693 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1694 cancel_work_sync(&hba->clk_gating.ungate_work);
1695 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 1696}
1697
856b3483
ST		 1698/* Must be called with host lock acquired */
1699static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1700{
401f1e44
SJ		 1701 bool queue_resume_work = false;
1702
fcb0c4b0 1703 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1704 return;
1705
401f1e44
SJ		 1706 if (!hba->clk_scaling.active_reqs++)
1707 queue_resume_work = true;
1708
1709 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1710 return;
1711
1712 if (queue_resume_work)
1713 queue_work(hba->clk_scaling.workq,
1714 &hba->clk_scaling.resume_work);
1715
1716 if (!hba->clk_scaling.window_start_t) {
1717 hba->clk_scaling.window_start_t = jiffies;
1718 hba->clk_scaling.tot_busy_t = 0;
1719 hba->clk_scaling.is_busy_started = false;
1720 }
1721
856b3483
ST		 1722 if (!hba->clk_scaling.is_busy_started) {
1723 hba->clk_scaling.busy_start_t = ktime_get();
1724 hba->clk_scaling.is_busy_started = true;
1725 }
1726}
1727
1728static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1729{
1730 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1731
fcb0c4b0 1732 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1733 return;
1734
1735 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1736 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1737 scaling->busy_start_t));
8b0e1953 1738 scaling->busy_start_t = 0;
856b3483
ST		 1739 scaling->is_busy_started = false;
1740 }
1741}
7a3e97b0
SY		 1742/**
1743 * ufshcd_send_command - Send SCSI or device management commands
1744 * @hba: per adapter instance
1745 * @task_tag: Task tag of the command
1746 */
1747static inline
1748void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1749{
ff8e20c6 1750 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1751 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
856b3483 1752 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1753 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1754 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1755 /* Make sure that doorbell is committed immediately */
1756 wmb();
1a07f2d9 1757 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY		 1758}
1759
1760/**
1761 * ufshcd_copy_sense_data - Copy sense data in case of check condition
1762 * @lrb - pointer to local reference block
1763 */
1764static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1765{
1766 int len;
1c2623c5
SJ		 1767 if (lrbp->sense_buffer &&
1768 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1769 int len_to_copy;
1770
5a0b0cb9 1771 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1772 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1773
7a3e97b0 1774 memcpy(lrbp->sense_buffer,
5a0b0cb9 1775 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1776 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1777 }
1778}
1779
68078d5c
DR		 1780/**
1781 * ufshcd_copy_query_response() - Copy the Query Response and the data
1782 * descriptor
1783 * @hba: per adapter instance
1784 * @lrb - pointer to local reference block
1785 */
1786static
c6d4a831 1787int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1788{
1789 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1790
68078d5c 1791 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1792
68078d5c
DR		 1793 /* Get the descriptor */
1794 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1795 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1796 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1797 u16 resp_len;
1798 u16 buf_len;
68078d5c
DR		 1799
1800 /* data segment length */
c6d4a831 1801 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1802 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1803 buf_len = be16_to_cpu(
1804 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1805 if (likely(buf_len >= resp_len)) {
1806 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1807 } else {
1808 dev_warn(hba->dev,
1809 "%s: Response size is bigger than buffer",
1810 __func__);
1811 return -EINVAL;
1812 }
68078d5c 1813 }
c6d4a831
DR		 1814
1815 return 0;
68078d5c
DR		 1816}
1817
7a3e97b0
SY		 1818/**
1819 * ufshcd_hba_capabilities - Read controller capabilities
1820 * @hba: per adapter instance
1821 */
1822static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1823{
b873a275 1824 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1825
1826 /* nutrs and nutmrs are 0 based values */
1827 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1828 hba->nutmrs =
1829 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1830}
1831
1832/**
6ccf44fe
SJ		 1833 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1834 * to accept UIC commands
7a3e97b0 1835 * @hba: per adapter instance
6ccf44fe
SJ		 1836 * Return true on success, else false
1837 */
1838static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1839{
1840 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1841 return true;
1842 else
1843 return false;
1844}
1845
53b3d9c3
SJ		 1846/**
1847 * ufshcd_get_upmcrs - Get the power mode change request status
1848 * @hba: Pointer to adapter instance
1849 *
1850 * This function gets the UPMCRS field of HCS register
1851 * Returns value of UPMCRS field
1852 */
1853static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1854{
1855 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1856}
1857
6ccf44fe
SJ		 1858/**
1859 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1860 * @hba: per adapter instance
1861 * @uic_cmd: UIC command
1862 *
1863 * Mutex must be held.
7a3e97b0
SY		 1864 */
1865static inline void
6ccf44fe 1866ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1867{
6ccf44fe
SJ		 1868 WARN_ON(hba->active_uic_cmd);
1869
1870 hba->active_uic_cmd = uic_cmd;
1871
7a3e97b0 1872 /* Write Args */
6ccf44fe
SJ		 1873 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1874 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1875 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1876
1877 /* Write UIC Cmd */
6ccf44fe 1878 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1879 REG_UIC_COMMAND);
7a3e97b0
SY		 1880}
1881
6ccf44fe
SJ		 1882/**
1883 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1884 * @hba: per adapter instance
1885 * @uic_command: UIC command
1886 *
1887 * Must be called with mutex held.
1888 * Returns 0 only if success.
1889 */
1890static int
1891ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1892{
1893 int ret;
1894 unsigned long flags;
1895
1896 if (wait_for_completion_timeout(&uic_cmd->done,
1897 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1898 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1899 else
1900 ret = -ETIMEDOUT;
1901
1902 spin_lock_irqsave(hba->host->host_lock, flags);
1903 hba->active_uic_cmd = NULL;
1904 spin_unlock_irqrestore(hba->host->host_lock, flags);
1905
1906 return ret;
1907}
1908
1909/**
1910 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1911 * @hba: per adapter instance
1912 * @uic_cmd: UIC command
d75f7fe4 1913 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1914 *
1915 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1916 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1917 * Returns 0 only if success.
1918 */
1919static int
d75f7fe4
YG		 1920__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1921 bool completion)
6ccf44fe 1922{
6ccf44fe
SJ		 1923 if (!ufshcd_ready_for_uic_cmd(hba)) {
1924 dev_err(hba->dev,
1925 "Controller not ready to accept UIC commands\n");
1926 return -EIO;
1927 }
1928
d75f7fe4
YG		 1929 if (completion)
1930 init_completion(&uic_cmd->done);
6ccf44fe 1931
6ccf44fe 1932 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1933
57d104c1 1934 return 0;
6ccf44fe
SJ		 1935}
1936
1937/**
1938 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1939 * @hba: per adapter instance
1940 * @uic_cmd: UIC command
1941 *
1942 * Returns 0 only if success.
1943 */
1944static int
1945ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1946{
1947 int ret;
57d104c1 1948 unsigned long flags;
6ccf44fe 1949
1ab27c9c 1950 ufshcd_hold(hba, false);
6ccf44fe 1951 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1952 ufshcd_add_delay_before_dme_cmd(hba);
1953
57d104c1 1954 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1955 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 1956 spin_unlock_irqrestore(hba->host->host_lock, flags);
1957 if (!ret)
1958 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1959
6ccf44fe
SJ		 1960 mutex_unlock(&hba->uic_cmd_mutex);
1961
1ab27c9c 1962 ufshcd_release(hba);
6ccf44fe
SJ		 1963 return ret;
1964}
1965
7a3e97b0
SY		 1966/**
1967 * ufshcd_map_sg - Map scatter-gather list to prdt
1968 * @lrbp - pointer to local reference block
1969 *
1970 * Returns 0 in case of success, non-zero value in case of failure
1971 */
75b1cc4a 1972static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 1973{
1974 struct ufshcd_sg_entry *prd_table;
1975 struct scatterlist *sg;
1976 struct scsi_cmnd *cmd;
1977 int sg_segments;
1978 int i;
1979
1980 cmd = lrbp->cmd;
1981 sg_segments = scsi_dma_map(cmd);
1982 if (sg_segments < 0)
1983 return sg_segments;
1984
1985 if (sg_segments) {
75b1cc4a
KK		 1986 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
1987 lrbp->utr_descriptor_ptr->prd_table_length =
1988 cpu_to_le16((u16)(sg_segments *
1989 sizeof(struct ufshcd_sg_entry)));
1990 else
1991 lrbp->utr_descriptor_ptr->prd_table_length =
1992 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 1993
1994 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1995
1996 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1997 prd_table[i].size =
1998 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1999 prd_table[i].base_addr =
2000 cpu_to_le32(lower_32_bits(sg->dma_address));
2001 prd_table[i].upper_addr =
2002 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2003 prd_table[i].reserved = 0;
7a3e97b0
SY		 2004 }
2005 } else {
2006 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2007 }
2008
2009 return 0;
2010}
2011
2012/**
2fbd009b 2013 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2014 * @hba: per adapter instance
2fbd009b 2015 * @intrs: interrupt bits
7a3e97b0 2016 */
2fbd009b 2017static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2018{
2fbd009b
SJ		 2019 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2020
2021 if (hba->ufs_version == UFSHCI_VERSION_10) {
2022 u32 rw;
2023 rw = set & INTERRUPT_MASK_RW_VER_10;
2024 set = rw | ((set ^ intrs) & intrs);
2025 } else {
2026 set |= intrs;
2027 }
2028
2029 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2030}
2031
2032/**
2033 * ufshcd_disable_intr - disable interrupts
2034 * @hba: per adapter instance
2035 * @intrs: interrupt bits
2036 */
2037static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2038{
2039 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2040
2041 if (hba->ufs_version == UFSHCI_VERSION_10) {
2042 u32 rw;
2043 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2044 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2045 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2046
2047 } else {
2048 set &= ~intrs;
7a3e97b0 2049 }
2fbd009b
SJ		 2050
2051 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2052}
2053
5a0b0cb9
SRT		 2054/**
2055 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2056 * descriptor according to request
2057 * @lrbp: pointer to local reference block
2058 * @upiu_flags: flags required in the header
2059 * @cmd_dir: requests data direction
2060 */
2061static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2062 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2063{
2064 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2065 u32 data_direction;
2066 u32 dword_0;
2067
2068 if (cmd_dir == DMA_FROM_DEVICE) {
2069 data_direction = UTP_DEVICE_TO_HOST;
2070 *upiu_flags = UPIU_CMD_FLAGS_READ;
2071 } else if (cmd_dir == DMA_TO_DEVICE) {
2072 data_direction = UTP_HOST_TO_DEVICE;
2073 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2074 } else {
2075 data_direction = UTP_NO_DATA_TRANSFER;
2076 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2077 }
2078
2079 dword_0 = data_direction | (lrbp->command_type
2080 << UPIU_COMMAND_TYPE_OFFSET);
2081 if (lrbp->intr_cmd)
2082 dword_0 |= UTP_REQ_DESC_INT_CMD;
2083
2084 /* Transfer request descriptor header fields */
2085 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2086 /* dword_1 is reserved, hence it is set to 0 */
2087 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2088 /*
2089 * assigning invalid value for command status. Controller
2090 * updates OCS on command completion, with the command
2091 * status
2092 */
2093 req_desc->header.dword_2 =
2094 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2095 /* dword_3 is reserved, hence it is set to 0 */
2096 req_desc->header.dword_3 = 0;
51047266
YG		 2097
2098 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2099}
2100
2101/**
2102 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2103 * for scsi commands
2104 * @lrbp - local reference block pointer
2105 * @upiu_flags - flags
2106 */
2107static
2108void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2109{
2110 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2111 unsigned short cdb_len;
5a0b0cb9
SRT		 2112
2113 /* command descriptor fields */
2114 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2115 UPIU_TRANSACTION_COMMAND, upiu_flags,
2116 lrbp->lun, lrbp->task_tag);
2117 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2118 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2119
2120 /* Total EHS length and Data segment length will be zero */
2121 ucd_req_ptr->header.dword_2 = 0;
2122
2123 ucd_req_ptr->sc.exp_data_transfer_len =
2124 cpu_to_be32(lrbp->cmd->sdb.length);
2125
52ac95fe
YG		 2126 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
2127 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
2128 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2129
2130 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2131}
2132
68078d5c
DR		 2133/**
2134 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2135 * for query requsts
2136 * @hba: UFS hba
2137 * @lrbp: local reference block pointer
2138 * @upiu_flags: flags
2139 */
2140static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2141 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2142{
2143 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2144 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2145 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2146 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2147
2148 /* Query request header */
2149 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2150 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2151 lrbp->lun, lrbp->task_tag);
2152 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2153 0, query->request.query_func, 0, 0);
2154
6861285c
ZL		 2155 /* Data segment length only need for WRITE_DESC */
2156 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2157 ucd_req_ptr->header.dword_2 =
2158 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2159 else
2160 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2161
2162 /* Copy the Query Request buffer as is */
2163 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2164 QUERY_OSF_SIZE);
68078d5c
DR		 2165
2166 /* Copy the Descriptor */
c6d4a831
DR		 2167 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2168 memcpy(descp, query->descriptor, len);
2169
51047266 2170 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2171}
2172
5a0b0cb9
SRT		 2173static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2174{
2175 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2176
2177 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2178
2179 /* command descriptor fields */
2180 ucd_req_ptr->header.dword_0 =
2181 UPIU_HEADER_DWORD(
2182 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2183 /* clear rest of the fields of basic header */
2184 ucd_req_ptr->header.dword_1 = 0;
2185 ucd_req_ptr->header.dword_2 = 0;
2186
2187 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2188}
2189
7a3e97b0 2190/**
300bb13f
JP		 2191 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2192 * for Device Management Purposes
5a0b0cb9 2193 * @hba - per adapter instance
7a3e97b0
SY		 2194 * @lrb - pointer to local reference block
2195 */
300bb13f 2196static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2197{
7a3e97b0 2198 u32 upiu_flags;
5a0b0cb9 2199 int ret = 0;
7a3e97b0 2200
300bb13f
JP		 2201 if (hba->ufs_version == UFSHCI_VERSION_20)
2202 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2203 else
2204 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2205
2206 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2207 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2208 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2209 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2210 ufshcd_prepare_utp_nop_upiu(lrbp);
2211 else
2212 ret = -EINVAL;
2213
2214 return ret;
2215}
2216
2217/**
2218 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2219 * for SCSI Purposes
2220 * @hba - per adapter instance
2221 * @lrb - pointer to local reference block
2222 */
2223static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2224{
2225 u32 upiu_flags;
2226 int ret = 0;
2227
2228 if (hba->ufs_version == UFSHCI_VERSION_20)
2229 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2230 else
2231 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2232
2233 if (likely(lrbp->cmd)) {
2234 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2235 lrbp->cmd->sc_data_direction);
2236 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2237 } else {
2238 ret = -EINVAL;
2239 }
5a0b0cb9
SRT		 2240
2241 return ret;
7a3e97b0
SY		 2242}
2243
0ce147d4
SJ		 2244/*
2245 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
2246 * @scsi_lun: scsi LUN id
2247 *
2248 * Returns UPIU LUN id
2249 */
2250static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
2251{
2252 if (scsi_is_wlun(scsi_lun))
2253 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
2254 | UFS_UPIU_WLUN_ID;
2255 else
2256 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
2257}
2258
2a8fa600
SJ		 2259/**
2260 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2261 * @scsi_lun: UPIU W-LUN id
2262 *
2263 * Returns SCSI W-LUN id
2264 */
2265static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2266{
2267 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2268}
2269
7a3e97b0
SY		 2270/**
2271 * ufshcd_queuecommand - main entry point for SCSI requests
2272 * @cmd: command from SCSI Midlayer
2273 * @done: call back function
2274 *
2275 * Returns 0 for success, non-zero in case of failure
2276 */
2277static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2278{
2279 struct ufshcd_lrb *lrbp;
2280 struct ufs_hba *hba;
2281 unsigned long flags;
2282 int tag;
2283 int err = 0;
2284
2285 hba = shost_priv(host);
2286
2287 tag = cmd->request->tag;
14497328
YG		 2288 if (!ufshcd_valid_tag(hba, tag)) {
2289 dev_err(hba->dev,
2290 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2291 __func__, tag, cmd, cmd->request);
2292 BUG();
2293 }
7a3e97b0 2294
a3cd5ec5
SJ		 2295 if (!down_read_trylock(&hba->clk_scaling_lock))
2296 return SCSI_MLQUEUE_HOST_BUSY;
2297
3441da7d
SRT		 2298 spin_lock_irqsave(hba->host->host_lock, flags);
2299 switch (hba->ufshcd_state) {
2300 case UFSHCD_STATE_OPERATIONAL:
2301 break;
141f8165 2302 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2303 case UFSHCD_STATE_RESET:
7a3e97b0 2304 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2305 goto out_unlock;
2306 case UFSHCD_STATE_ERROR:
2307 set_host_byte(cmd, DID_ERROR);
2308 cmd->scsi_done(cmd);
2309 goto out_unlock;
2310 default:
2311 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2312 __func__, hba->ufshcd_state);
2313 set_host_byte(cmd, DID_BAD_TARGET);
2314 cmd->scsi_done(cmd);
2315 goto out_unlock;
7a3e97b0 2316 }
53c12d0e
YG		 2317
2318 /* if error handling is in progress, don't issue commands */
2319 if (ufshcd_eh_in_progress(hba)) {
2320 set_host_byte(cmd, DID_ERROR);
2321 cmd->scsi_done(cmd);
2322 goto out_unlock;
2323 }
3441da7d 2324 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2325
7fabb77b
GB		 2326 hba->req_abort_count = 0;
2327
5a0b0cb9
SRT		 2328 /* acquire the tag to make sure device cmds don't use it */
2329 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2330 /*
2331 * Dev manage command in progress, requeue the command.
2332 * Requeuing the command helps in cases where the request *may*
2333 * find different tag instead of waiting for dev manage command
2334 * completion.
2335 */
2336 err = SCSI_MLQUEUE_HOST_BUSY;
2337 goto out;
2338 }
2339
1ab27c9c
ST		 2340 err = ufshcd_hold(hba, true);
2341 if (err) {
2342 err = SCSI_MLQUEUE_HOST_BUSY;
2343 clear_bit_unlock(tag, &hba->lrb_in_use);
2344 goto out;
2345 }
2346 WARN_ON(hba->clk_gating.state != CLKS_ON);
2347
7a3e97b0
SY		 2348 lrbp = &hba->lrb[tag];
2349
5a0b0cb9 2350 WARN_ON(lrbp->cmd);
7a3e97b0 2351 lrbp->cmd = cmd;
dcea0bfb 2352 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 2353 lrbp->sense_buffer = cmd->sense_buffer;
2354 lrbp->task_tag = tag;
0ce147d4 2355 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2356 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2357 lrbp->req_abort_skip = false;
7a3e97b0 2358
300bb13f
JP		 2359 ufshcd_comp_scsi_upiu(hba, lrbp);
2360
75b1cc4a 2361 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2362 if (err) {
2363 lrbp->cmd = NULL;
2364 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2365 goto out;
5a0b0cb9 2366 }
ad1a1b9c
GB		 2367 /* Make sure descriptors are ready before ringing the doorbell */
2368 wmb();
7a3e97b0
SY		 2369
2370 /* issue command to the controller */
2371 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2372 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 2373 ufshcd_send_command(hba, tag);
3441da7d 2374out_unlock:
7a3e97b0
SY		 2375 spin_unlock_irqrestore(hba->host->host_lock, flags);
2376out:
a3cd5ec5 2377 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2378 return err;
2379}
2380
5a0b0cb9
SRT		 2381static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2382 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2383{
2384 lrbp->cmd = NULL;
2385 lrbp->sense_bufflen = 0;
2386 lrbp->sense_buffer = NULL;
2387 lrbp->task_tag = tag;
2388 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2389 lrbp->intr_cmd = true; /* No interrupt aggregation */
2390 hba->dev_cmd.type = cmd_type;
2391
300bb13f 2392 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2393}
2394
2395static int
2396ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2397{
2398 int err = 0;
2399 unsigned long flags;
2400 u32 mask = 1 << tag;
2401
2402 /* clear outstanding transaction before retry */
2403 spin_lock_irqsave(hba->host->host_lock, flags);
2404 ufshcd_utrl_clear(hba, tag);
2405 spin_unlock_irqrestore(hba->host->host_lock, flags);
2406
2407 /*
2408 * wait for for h/w to clear corresponding bit in door-bell.
2409 * max. wait is 1 sec.
2410 */
2411 err = ufshcd_wait_for_register(hba,
2412 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2413 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2414
2415 return err;
2416}
2417
c6d4a831
DR		 2418static int
2419ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2420{
2421 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2422
2423 /* Get the UPIU response */
2424 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2425 UPIU_RSP_CODE_OFFSET;
2426 return query_res->response;
2427}
2428
5a0b0cb9
SRT		 2429/**
2430 * ufshcd_dev_cmd_completion() - handles device management command responses
2431 * @hba: per adapter instance
2432 * @lrbp: pointer to local reference block
2433 */
2434static int
2435ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2436{
2437 int resp;
2438 int err = 0;
2439
ff8e20c6 2440 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2441 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2442
2443 switch (resp) {
2444 case UPIU_TRANSACTION_NOP_IN:
2445 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2446 err = -EINVAL;
2447 dev_err(hba->dev, "%s: unexpected response %x\n",
2448 __func__, resp);
2449 }
2450 break;
68078d5c 2451 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2452 err = ufshcd_check_query_response(hba, lrbp);
2453 if (!err)
2454 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2455 break;
5a0b0cb9
SRT		 2456 case UPIU_TRANSACTION_REJECT_UPIU:
2457 /* TODO: handle Reject UPIU Response */
2458 err = -EPERM;
2459 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2460 __func__);
2461 break;
2462 default:
2463 err = -EINVAL;
2464 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2465 __func__, resp);
2466 break;
2467 }
2468
2469 return err;
2470}
2471
2472static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2473 struct ufshcd_lrb *lrbp, int max_timeout)
2474{
2475 int err = 0;
2476 unsigned long time_left;
2477 unsigned long flags;
2478
2479 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2480 msecs_to_jiffies(max_timeout));
2481
ad1a1b9c
GB		 2482 /* Make sure descriptors are ready before ringing the doorbell */
2483 wmb();
5a0b0cb9
SRT		 2484 spin_lock_irqsave(hba->host->host_lock, flags);
2485 hba->dev_cmd.complete = NULL;
2486 if (likely(time_left)) {
2487 err = ufshcd_get_tr_ocs(lrbp);
2488 if (!err)
2489 err = ufshcd_dev_cmd_completion(hba, lrbp);
2490 }
2491 spin_unlock_irqrestore(hba->host->host_lock, flags);
2492
2493 if (!time_left) {
2494 err = -ETIMEDOUT;
a48353f6
YG		 2495 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2496 __func__, lrbp->task_tag);
5a0b0cb9 2497 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2498 /* successfully cleared the command, retry if needed */
5a0b0cb9 2499 err = -EAGAIN;
a48353f6
YG		 2500 /*
2501 * in case of an error, after clearing the doorbell,
2502 * we also need to clear the outstanding_request
2503 * field in hba
2504 */
2505 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2506 }
2507
2508 return err;
2509}
2510
2511/**
2512 * ufshcd_get_dev_cmd_tag - Get device management command tag
2513 * @hba: per-adapter instance
2514 * @tag: pointer to variable with available slot value
2515 *
2516 * Get a free slot and lock it until device management command
2517 * completes.
2518 *
2519 * Returns false if free slot is unavailable for locking, else
2520 * return true with tag value in @tag.
2521 */
2522static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2523{
2524 int tag;
2525 bool ret = false;
2526 unsigned long tmp;
2527
2528 if (!tag_out)
2529 goto out;
2530
2531 do {
2532 tmp = ~hba->lrb_in_use;
2533 tag = find_last_bit(&tmp, hba->nutrs);
2534 if (tag >= hba->nutrs)
2535 goto out;
2536 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2537
2538 *tag_out = tag;
2539 ret = true;
2540out:
2541 return ret;
2542}
2543
2544static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2545{
2546 clear_bit_unlock(tag, &hba->lrb_in_use);
2547}
2548
2549/**
2550 * ufshcd_exec_dev_cmd - API for sending device management requests
2551 * @hba - UFS hba
2552 * @cmd_type - specifies the type (NOP, Query...)
2553 * @timeout - time in seconds
2554 *
68078d5c
DR		 2555 * NOTE: Since there is only one available tag for device management commands,
2556 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2557 */
2558static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2559 enum dev_cmd_type cmd_type, int timeout)
2560{
2561 struct ufshcd_lrb *lrbp;
2562 int err;
2563 int tag;
2564 struct completion wait;
2565 unsigned long flags;
2566
a3cd5ec5
SJ		 2567 down_read(&hba->clk_scaling_lock);
2568
5a0b0cb9
SRT		 2569 /*
2570 * Get free slot, sleep if slots are unavailable.
2571 * Even though we use wait_event() which sleeps indefinitely,
2572 * the maximum wait time is bounded by SCSI request timeout.
2573 */
2574 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2575
2576 init_completion(&wait);
2577 lrbp = &hba->lrb[tag];
2578 WARN_ON(lrbp->cmd);
2579 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2580 if (unlikely(err))
2581 goto out_put_tag;
2582
2583 hba->dev_cmd.complete = &wait;
2584
e3dfdc53
YG		 2585 /* Make sure descriptors are ready before ringing the doorbell */
2586 wmb();
5a0b0cb9 2587 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2588 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 2589 ufshcd_send_command(hba, tag);
2590 spin_unlock_irqrestore(hba->host->host_lock, flags);
2591
2592 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2593
2594out_put_tag:
2595 ufshcd_put_dev_cmd_tag(hba, tag);
2596 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2597 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2598 return err;
2599}
2600
d44a5f98
DR		 2601/**
2602 * ufshcd_init_query() - init the query response and request parameters
2603 * @hba: per-adapter instance
2604 * @request: address of the request pointer to be initialized
2605 * @response: address of the response pointer to be initialized
2606 * @opcode: operation to perform
2607 * @idn: flag idn to access
2608 * @index: LU number to access
2609 * @selector: query/flag/descriptor further identification
2610 */
2611static inline void ufshcd_init_query(struct ufs_hba *hba,
2612 struct ufs_query_req **request, struct ufs_query_res **response,
2613 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2614{
2615 *request = &hba->dev_cmd.query.request;
2616 *response = &hba->dev_cmd.query.response;
2617 memset(*request, 0, sizeof(struct ufs_query_req));
2618 memset(*response, 0, sizeof(struct ufs_query_res));
2619 (*request)->upiu_req.opcode = opcode;
2620 (*request)->upiu_req.idn = idn;
2621 (*request)->upiu_req.index = index;
2622 (*request)->upiu_req.selector = selector;
2623}
2624
dc3c8d3a
YG		 2625static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2626 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2627{
2628 int ret;
2629 int retries;
2630
2631 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2632 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2633 if (ret)
2634 dev_dbg(hba->dev,
2635 "%s: failed with error %d, retries %d\n",
2636 __func__, ret, retries);
2637 else
2638 break;
2639 }
2640
2641 if (ret)
2642 dev_err(hba->dev,
2643 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2644 __func__, opcode, idn, ret, retries);
2645 return ret;
2646}
2647
68078d5c
DR		 2648/**
2649 * ufshcd_query_flag() - API function for sending flag query requests
2650 * hba: per-adapter instance
2651 * query_opcode: flag query to perform
2652 * idn: flag idn to access
2653 * flag_res: the flag value after the query request completes
2654 *
2655 * Returns 0 for success, non-zero in case of failure
2656 */
dc3c8d3a 2657int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2658 enum flag_idn idn, bool *flag_res)
2659{
d44a5f98
DR		 2660 struct ufs_query_req *request = NULL;
2661 struct ufs_query_res *response = NULL;
2662 int err, index = 0, selector = 0;
e5ad406c 2663 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2664
2665 BUG_ON(!hba);
2666
1ab27c9c 2667 ufshcd_hold(hba, false);
68078d5c 2668 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2669 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2670 selector);
68078d5c
DR		 2671
2672 switch (opcode) {
2673 case UPIU_QUERY_OPCODE_SET_FLAG:
2674 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2675 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2676 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2677 break;
2678 case UPIU_QUERY_OPCODE_READ_FLAG:
2679 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2680 if (!flag_res) {
2681 /* No dummy reads */
2682 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2683 __func__);
2684 err = -EINVAL;
2685 goto out_unlock;
2686 }
2687 break;
2688 default:
2689 dev_err(hba->dev,
2690 "%s: Expected query flag opcode but got = %d\n",
2691 __func__, opcode);
2692 err = -EINVAL;
2693 goto out_unlock;
2694 }
68078d5c 2695
e5ad406c 2696 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2697
2698 if (err) {
2699 dev_err(hba->dev,
2700 "%s: Sending flag query for idn %d failed, err = %d\n",
2701 __func__, idn, err);
2702 goto out_unlock;
2703 }
2704
2705 if (flag_res)
e8c8e82a 2706 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2707 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2708
2709out_unlock:
2710 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2711 ufshcd_release(hba);
68078d5c
DR		 2712 return err;
2713}
2714
66ec6d59
SRT		 2715/**
2716 * ufshcd_query_attr - API function for sending attribute requests
2717 * hba: per-adapter instance
2718 * opcode: attribute opcode
2719 * idn: attribute idn to access
2720 * index: index field
2721 * selector: selector field
2722 * attr_val: the attribute value after the query request completes
2723 *
2724 * Returns 0 for success, non-zero in case of failure
2725*/
bdbe5d2f 2726static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 2727 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2728{
d44a5f98
DR		 2729 struct ufs_query_req *request = NULL;
2730 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2731 int err;
2732
2733 BUG_ON(!hba);
2734
1ab27c9c 2735 ufshcd_hold(hba, false);
66ec6d59
SRT		 2736 if (!attr_val) {
2737 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2738 __func__, opcode);
2739 err = -EINVAL;
2740 goto out;
2741 }
2742
2743 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2744 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2745 selector);
66ec6d59
SRT		 2746
2747 switch (opcode) {
2748 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2749 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2750 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2751 break;
2752 case UPIU_QUERY_OPCODE_READ_ATTR:
2753 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2754 break;
2755 default:
2756 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2757 __func__, opcode);
2758 err = -EINVAL;
2759 goto out_unlock;
2760 }
2761
d44a5f98 2762 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2763
2764 if (err) {
4b761b58
YG		 2765 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2766 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2767 goto out_unlock;
2768 }
2769
e8c8e82a 2770 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2771
2772out_unlock:
2773 mutex_unlock(&hba->dev_cmd.lock);
2774out:
1ab27c9c 2775 ufshcd_release(hba);
66ec6d59
SRT		 2776 return err;
2777}
2778
5e86ae44
YG		 2779/**
2780 * ufshcd_query_attr_retry() - API function for sending query
2781 * attribute with retries
2782 * @hba: per-adapter instance
2783 * @opcode: attribute opcode
2784 * @idn: attribute idn to access
2785 * @index: index field
2786 * @selector: selector field
2787 * @attr_val: the attribute value after the query request
2788 * completes
2789 *
2790 * Returns 0 for success, non-zero in case of failure
2791*/
2792static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2793 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2794 u32 *attr_val)
2795{
2796 int ret = 0;
2797 u32 retries;
2798
2799 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2800 ret = ufshcd_query_attr(hba, opcode, idn, index,
2801 selector, attr_val);
2802 if (ret)
2803 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2804 __func__, ret, retries);
2805 else
2806 break;
2807 }
2808
2809 if (ret)
2810 dev_err(hba->dev,
2811 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2812 __func__, idn, ret, QUERY_REQ_RETRIES);
2813 return ret;
2814}
2815
a70e91b8 2816static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2817 enum query_opcode opcode, enum desc_idn idn, u8 index,
2818 u8 selector, u8 *desc_buf, int *buf_len)
2819{
2820 struct ufs_query_req *request = NULL;
2821 struct ufs_query_res *response = NULL;
2822 int err;
2823
2824 BUG_ON(!hba);
2825
1ab27c9c 2826 ufshcd_hold(hba, false);
d44a5f98
DR		 2827 if (!desc_buf) {
2828 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2829 __func__, opcode);
2830 err = -EINVAL;
2831 goto out;
2832 }
2833
a4b0e8a4 2834 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2835 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2836 __func__, *buf_len);
2837 err = -EINVAL;
2838 goto out;
2839 }
2840
2841 mutex_lock(&hba->dev_cmd.lock);
2842 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2843 selector);
2844 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2845 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2846
2847 switch (opcode) {
2848 case UPIU_QUERY_OPCODE_WRITE_DESC:
2849 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2850 break;
2851 case UPIU_QUERY_OPCODE_READ_DESC:
2852 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2853 break;
2854 default:
2855 dev_err(hba->dev,
2856 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2857 __func__, opcode);
2858 err = -EINVAL;
2859 goto out_unlock;
2860 }
2861
2862 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2863
2864 if (err) {
4b761b58
YG		 2865 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2866 __func__, opcode, idn, index, err);
d44a5f98
DR		 2867 goto out_unlock;
2868 }
2869
2870 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2871 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2872
2873out_unlock:
2874 mutex_unlock(&hba->dev_cmd.lock);
2875out:
1ab27c9c 2876 ufshcd_release(hba);
d44a5f98
DR		 2877 return err;
2878}
2879
a70e91b8
YG		 2880/**
2881 * ufshcd_query_descriptor_retry - API function for sending descriptor
2882 * requests
2883 * hba: per-adapter instance
2884 * opcode: attribute opcode
2885 * idn: attribute idn to access
2886 * index: index field
2887 * selector: selector field
2888 * desc_buf: the buffer that contains the descriptor
2889 * buf_len: length parameter passed to the device
2890 *
2891 * Returns 0 for success, non-zero in case of failure.
2892 * The buf_len parameter will contain, on return, the length parameter
2893 * received on the response.
2894 */
26cf9155
TW		 2895static int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2896 enum query_opcode opcode,
2897 enum desc_idn idn, u8 index,
2898 u8 selector,
2899 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 2900{
2901 int err;
2902 int retries;
2903
2904 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2905 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2906 selector, desc_buf, buf_len);
2907 if (!err || err == -EINVAL)
2908 break;
2909 }
2910
2911 return err;
2912}
a70e91b8 2913
a4b0e8a4
PM		 2914/**
2915 * ufshcd_read_desc_length - read the specified descriptor length from header
2916 * @hba: Pointer to adapter instance
2917 * @desc_id: descriptor idn value
2918 * @desc_index: descriptor index
2919 * @desc_length: pointer to variable to read the length of descriptor
2920 *
2921 * Return 0 in case of success, non-zero otherwise
2922 */
2923static int ufshcd_read_desc_length(struct ufs_hba *hba,
2924 enum desc_idn desc_id,
2925 int desc_index,
2926 int *desc_length)
2927{
2928 int ret;
2929 u8 header[QUERY_DESC_HDR_SIZE];
2930 int header_len = QUERY_DESC_HDR_SIZE;
2931
2932 if (desc_id >= QUERY_DESC_IDN_MAX)
2933 return -EINVAL;
2934
2935 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2936 desc_id, desc_index, 0, header,
2937 &header_len);
2938
2939 if (ret) {
2940 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
2941 __func__, desc_id);
2942 return ret;
2943 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
2944 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
2945 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
2946 desc_id);
2947 ret = -EINVAL;
2948 }
2949
2950 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
2951 return ret;
2952
2953}
2954
2955/**
2956 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
2957 * @hba: Pointer to adapter instance
2958 * @desc_id: descriptor idn value
2959 * @desc_len: mapped desc length (out)
2960 *
2961 * Return 0 in case of success, non-zero otherwise
2962 */
2963int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
2964 enum desc_idn desc_id, int *desc_len)
2965{
2966 switch (desc_id) {
2967 case QUERY_DESC_IDN_DEVICE:
2968 *desc_len = hba->desc_size.dev_desc;
2969 break;
2970 case QUERY_DESC_IDN_POWER:
2971 *desc_len = hba->desc_size.pwr_desc;
2972 break;
2973 case QUERY_DESC_IDN_GEOMETRY:
2974 *desc_len = hba->desc_size.geom_desc;
2975 break;
2976 case QUERY_DESC_IDN_CONFIGURATION:
2977 *desc_len = hba->desc_size.conf_desc;
2978 break;
2979 case QUERY_DESC_IDN_UNIT:
2980 *desc_len = hba->desc_size.unit_desc;
2981 break;
2982 case QUERY_DESC_IDN_INTERCONNECT:
2983 *desc_len = hba->desc_size.interc_desc;
2984 break;
2985 case QUERY_DESC_IDN_STRING:
2986 *desc_len = QUERY_DESC_MAX_SIZE;
2987 break;
2988 case QUERY_DESC_IDN_RFU_0:
2989 case QUERY_DESC_IDN_RFU_1:
2990 *desc_len = 0;
2991 break;
2992 default:
2993 *desc_len = 0;
2994 return -EINVAL;
2995 }
2996 return 0;
2997}
2998EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
2999
da461cec
SJ		 3000/**
3001 * ufshcd_read_desc_param - read the specified descriptor parameter
3002 * @hba: Pointer to adapter instance
3003 * @desc_id: descriptor idn value
3004 * @desc_index: descriptor index
3005 * @param_offset: offset of the parameter to read
3006 * @param_read_buf: pointer to buffer where parameter would be read
3007 * @param_size: sizeof(param_read_buf)
3008 *
3009 * Return 0 in case of success, non-zero otherwise
3010 */
3011static int ufshcd_read_desc_param(struct ufs_hba *hba,
3012 enum desc_idn desc_id,
3013 int desc_index,
a4b0e8a4 3014 u8 param_offset,
da461cec 3015 u8 *param_read_buf,
a4b0e8a4 3016 u8 param_size)
da461cec
SJ		 3017{
3018 int ret;
3019 u8 *desc_buf;
a4b0e8a4 3020 int buff_len;
da461cec
SJ		 3021 bool is_kmalloc = true;
3022
a4b0e8a4
PM		 3023 /* Safety check */
3024 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3025 return -EINVAL;
3026
a4b0e8a4
PM		 3027 /* Get the max length of descriptor from structure filled up at probe
3028 * time.
3029 */
3030 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3031
a4b0e8a4
PM		 3032 /* Sanity checks */
3033 if (ret || !buff_len) {
3034 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3035 __func__);
3036 return ret;
3037 }
3038
3039 /* Check whether we need temp memory */
3040 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3041 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3042 if (!desc_buf)
3043 return -ENOMEM;
a4b0e8a4
PM		 3044 } else {
3045 desc_buf = param_read_buf;
3046 is_kmalloc = false;
da461cec
SJ		 3047 }
3048
a4b0e8a4 3049 /* Request for full descriptor */
a70e91b8 3050 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3051 desc_id, desc_index, 0,
3052 desc_buf, &buff_len);
da461cec 3053
bde44bb6
SJ		 3054 if (ret) {
3055 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3056 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3057 goto out;
3058 }
3059
bde44bb6
SJ		 3060 /* Sanity check */
3061 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3062 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3063 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3064 ret = -EINVAL;
3065 goto out;
3066 }
3067
a4b0e8a4
PM		 3068 /* Check wherher we will not copy more data, than available */
3069 if (is_kmalloc && param_size > buff_len)
3070 param_size = buff_len;
bde44bb6 3071
da461cec
SJ		 3072 if (is_kmalloc)
3073 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3074out:
3075 if (is_kmalloc)
3076 kfree(desc_buf);
3077 return ret;
3078}
3079
3080static inline int ufshcd_read_desc(struct ufs_hba *hba,
3081 enum desc_idn desc_id,
3082 int desc_index,
3083 u8 *buf,
3084 u32 size)
3085{
3086 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3087}
3088
3089static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3090 u8 *buf,
3091 u32 size)
3092{
dbd34a61 3093 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
da461cec
SJ		 3094}
3095
8209b6d5 3096static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3097{
3098 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3099}
b573d484
YG		 3100
3101/**
3102 * ufshcd_read_string_desc - read string descriptor
3103 * @hba: pointer to adapter instance
3104 * @desc_index: descriptor index
3105 * @buf: pointer to buffer where descriptor would be read
3106 * @size: size of buf
3107 * @ascii: if true convert from unicode to ascii characters
3108 *
3109 * Return 0 in case of success, non-zero otherwise
3110 */
8209b6d5
TW		 3111#define ASCII_STD true
3112static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3113 u8 *buf, u32 size, bool ascii)
b573d484
YG		 3114{
3115 int err = 0;
3116
3117 err = ufshcd_read_desc(hba,
3118 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3119
3120 if (err) {
3121 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3122 __func__, QUERY_REQ_RETRIES, err);
3123 goto out;
3124 }
3125
3126 if (ascii) {
3127 int desc_len;
3128 int ascii_len;
3129 int i;
3130 char *buff_ascii;
3131
3132 desc_len = buf[0];
3133 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3134 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3135 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3136 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3137 __func__);
3138 err = -ENOMEM;
3139 goto out;
3140 }
3141
3142 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3143 if (!buff_ascii) {
3144 err = -ENOMEM;
fcbefc3b 3145 goto out;
b573d484
YG		 3146 }
3147
3148 /*
3149 * the descriptor contains string in UTF16 format
3150 * we need to convert to utf-8 so it can be displayed
3151 */
3152 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3153 desc_len - QUERY_DESC_HDR_SIZE,
3154 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3155
3156 /* replace non-printable or non-ASCII characters with spaces */
3157 for (i = 0; i < ascii_len; i++)
3158 ufshcd_remove_non_printable(&buff_ascii[i]);
3159
3160 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3161 size - QUERY_DESC_HDR_SIZE);
3162 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3163 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 3164 kfree(buff_ascii);
3165 }
3166out:
3167 return err;
3168}
b573d484 3169
da461cec
SJ		 3170/**
3171 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3172 * @hba: Pointer to adapter instance
3173 * @lun: lun id
3174 * @param_offset: offset of the parameter to read
3175 * @param_read_buf: pointer to buffer where parameter would be read
3176 * @param_size: sizeof(param_read_buf)
3177 *
3178 * Return 0 in case of success, non-zero otherwise
3179 */
3180static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3181 int lun,
3182 enum unit_desc_param param_offset,
3183 u8 *param_read_buf,
3184 u32 param_size)
3185{
3186 /*
3187 * Unit descriptors are only available for general purpose LUs (LUN id
3188 * from 0 to 7) and RPMB Well known LU.
3189 */
0ce147d4 3190 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 3191 return -EOPNOTSUPP;
3192
3193 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3194 param_offset, param_read_buf, param_size);
3195}
3196
7a3e97b0
SY		 3197/**
3198 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3199 * @hba: per adapter instance
3200 *
3201 * 1. Allocate DMA memory for Command Descriptor array
3202 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3203 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3204 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3205 * (UTMRDL)
3206 * 4. Allocate memory for local reference block(lrb).
3207 *
3208 * Returns 0 for success, non-zero in case of failure
3209 */
3210static int ufshcd_memory_alloc(struct ufs_hba *hba)
3211{
3212 size_t utmrdl_size, utrdl_size, ucdl_size;
3213
3214 /* Allocate memory for UTP command descriptors */
3215 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3216 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3217 ucdl_size,
3218 &hba->ucdl_dma_addr,
3219 GFP_KERNEL);
7a3e97b0
SY		 3220
3221 /*
3222 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3223 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3224 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3225 * be aligned to 128 bytes as well
3226 */
3227 if (!hba->ucdl_base_addr ||
3228 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3229 dev_err(hba->dev,
7a3e97b0
SY		 3230 "Command Descriptor Memory allocation failed\n");
3231 goto out;
3232 }
3233
3234 /*
3235 * Allocate memory for UTP Transfer descriptors
3236 * UFSHCI requires 1024 byte alignment of UTRD
3237 */
3238 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3239 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3240 utrdl_size,
3241 &hba->utrdl_dma_addr,
3242 GFP_KERNEL);
7a3e97b0
SY		 3243 if (!hba->utrdl_base_addr ||
3244 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3245 dev_err(hba->dev,
7a3e97b0
SY		 3246 "Transfer Descriptor Memory allocation failed\n");
3247 goto out;
3248 }
3249
3250 /*
3251 * Allocate memory for UTP Task Management descriptors
3252 * UFSHCI requires 1024 byte alignment of UTMRD
3253 */
3254 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3255 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3256 utmrdl_size,
3257 &hba->utmrdl_dma_addr,
3258 GFP_KERNEL);
7a3e97b0
SY		 3259 if (!hba->utmrdl_base_addr ||
3260 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3261 dev_err(hba->dev,
7a3e97b0
SY		 3262 "Task Management Descriptor Memory allocation failed\n");
3263 goto out;
3264 }
3265
3266 /* Allocate memory for local reference block */
2953f850
SJ		 3267 hba->lrb = devm_kzalloc(hba->dev,
3268 hba->nutrs * sizeof(struct ufshcd_lrb),
3269 GFP_KERNEL);
7a3e97b0 3270 if (!hba->lrb) {
3b1d0580 3271 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3272 goto out;
3273 }
3274 return 0;
3275out:
7a3e97b0
SY		 3276 return -ENOMEM;
3277}
3278
3279/**
3280 * ufshcd_host_memory_configure - configure local reference block with
3281 * memory offsets
3282 * @hba: per adapter instance
3283 *
3284 * Configure Host memory space
3285 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3286 * address.
3287 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3288 * and PRDT offset.
3289 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3290 * into local reference block.
3291 */
3292static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3293{
3294 struct utp_transfer_cmd_desc *cmd_descp;
3295 struct utp_transfer_req_desc *utrdlp;
3296 dma_addr_t cmd_desc_dma_addr;
3297 dma_addr_t cmd_desc_element_addr;
3298 u16 response_offset;
3299 u16 prdt_offset;
3300 int cmd_desc_size;
3301 int i;
3302
3303 utrdlp = hba->utrdl_base_addr;
3304 cmd_descp = hba->ucdl_base_addr;
3305
3306 response_offset =
3307 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3308 prdt_offset =
3309 offsetof(struct utp_transfer_cmd_desc, prd_table);
3310
3311 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3312 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3313
3314 for (i = 0; i < hba->nutrs; i++) {
3315 /* Configure UTRD with command descriptor base address */
3316 cmd_desc_element_addr =
3317 (cmd_desc_dma_addr + (cmd_desc_size * i));
3318 utrdlp[i].command_desc_base_addr_lo =
3319 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3320 utrdlp[i].command_desc_base_addr_hi =
3321 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3322
3323 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3324 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3325 utrdlp[i].response_upiu_offset =
3326 cpu_to_le16(response_offset);
3327 utrdlp[i].prd_table_offset =
3328 cpu_to_le16(prdt_offset);
3329 utrdlp[i].response_upiu_length =
3330 cpu_to_le16(ALIGNED_UPIU_SIZE);
3331 } else {
3332 utrdlp[i].response_upiu_offset =
7a3e97b0 3333 cpu_to_le16((response_offset >> 2));
75b1cc4a 3334 utrdlp[i].prd_table_offset =
7a3e97b0 3335 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3336 utrdlp[i].response_upiu_length =
3ca316c5 3337 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3338 }
7a3e97b0
SY		 3339
3340 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3341 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3342 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3343 hba->lrb[i].ucd_req_ptr =
3344 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3345 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3346 hba->lrb[i].ucd_rsp_ptr =
3347 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3348 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3349 response_offset;
7a3e97b0
SY		 3350 hba->lrb[i].ucd_prdt_ptr =
3351 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3352 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3353 prdt_offset;
7a3e97b0
SY		 3354 }
3355}
3356
3357/**
3358 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3359 * @hba: per adapter instance
3360 *
3361 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3362 * in order to initialize the Unipro link startup procedure.
3363 * Once the Unipro links are up, the device connected to the controller
3364 * is detected.
3365 *
3366 * Returns 0 on success, non-zero value on failure
3367 */
3368static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3369{
6ccf44fe
SJ		 3370 struct uic_command uic_cmd = {0};
3371 int ret;
7a3e97b0 3372
6ccf44fe 3373 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3374
6ccf44fe
SJ		 3375 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3376 if (ret)
ff8e20c6 3377 dev_dbg(hba->dev,
6ccf44fe
SJ		 3378 "dme-link-startup: error code %d\n", ret);
3379 return ret;
7a3e97b0
SY		 3380}
3381
cad2e03d
YG		 3382static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3383{
3384 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3385 unsigned long min_sleep_time_us;
3386
3387 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3388 return;
3389
3390 /*
3391 * last_dme_cmd_tstamp will be 0 only for 1st call to
3392 * this function
3393 */
3394 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3395 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3396 } else {
3397 unsigned long delta =
3398 (unsigned long) ktime_to_us(
3399 ktime_sub(ktime_get(),
3400 hba->last_dme_cmd_tstamp));
3401
3402 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3403 min_sleep_time_us =
3404 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3405 else
3406 return; /* no more delay required */
3407 }
3408
3409 /* allow sleep for extra 50us if needed */
3410 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3411}
3412
12b4fdb4
SJ		 3413/**
3414 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3415 * @hba: per adapter instance
3416 * @attr_sel: uic command argument1
3417 * @attr_set: attribute set type as uic command argument2
3418 * @mib_val: setting value as uic command argument3
3419 * @peer: indicate whether peer or local
3420 *
3421 * Returns 0 on success, non-zero value on failure
3422 */
3423int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3424 u8 attr_set, u32 mib_val, u8 peer)
3425{
3426 struct uic_command uic_cmd = {0};
3427 static const char *const action[] = {
3428 "dme-set",
3429 "dme-peer-set"
3430 };
3431 const char *set = action[!!peer];
3432 int ret;
64238fbd 3433 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3434
3435 uic_cmd.command = peer ?
3436 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3437 uic_cmd.argument1 = attr_sel;
3438 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3439 uic_cmd.argument3 = mib_val;
3440
64238fbd
YG		 3441 do {
3442 /* for peer attributes we retry upon failure */
3443 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3444 if (ret)
3445 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3446 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3447 } while (ret && peer && --retries);
3448
f37e9f8c 3449 if (ret)
64238fbd 3450 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3451 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3452 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3453
3454 return ret;
3455}
3456EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3457
3458/**
3459 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3460 * @hba: per adapter instance
3461 * @attr_sel: uic command argument1
3462 * @mib_val: the value of the attribute as returned by the UIC command
3463 * @peer: indicate whether peer or local
3464 *
3465 * Returns 0 on success, non-zero value on failure
3466 */
3467int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3468 u32 *mib_val, u8 peer)
3469{
3470 struct uic_command uic_cmd = {0};
3471 static const char *const action[] = {
3472 "dme-get",
3473 "dme-peer-get"
3474 };
3475 const char *get = action[!!peer];
3476 int ret;
64238fbd 3477 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3478 struct ufs_pa_layer_attr orig_pwr_info;
3479 struct ufs_pa_layer_attr temp_pwr_info;
3480 bool pwr_mode_change = false;
3481
3482 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3483 orig_pwr_info = hba->pwr_info;
3484 temp_pwr_info = orig_pwr_info;
3485
3486 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3487 orig_pwr_info.pwr_rx == FAST_MODE) {
3488 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3489 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3490 pwr_mode_change = true;
3491 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3492 orig_pwr_info.pwr_rx == SLOW_MODE) {
3493 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3494 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3495 pwr_mode_change = true;
3496 }
3497 if (pwr_mode_change) {
3498 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3499 if (ret)
3500 goto out;
3501 }
3502 }
12b4fdb4
SJ		 3503
3504 uic_cmd.command = peer ?
3505 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3506 uic_cmd.argument1 = attr_sel;
3507
64238fbd
YG		 3508 do {
3509 /* for peer attributes we retry upon failure */
3510 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3511 if (ret)
3512 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3513 get, UIC_GET_ATTR_ID(attr_sel), ret);
3514 } while (ret && peer && --retries);
3515
f37e9f8c 3516 if (ret)
64238fbd 3517 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3518 get, UIC_GET_ATTR_ID(attr_sel),
3519 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3520
64238fbd 3521 if (mib_val && !ret)
12b4fdb4 3522 *mib_val = uic_cmd.argument3;
874237f7
YG		 3523
3524 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3525 && pwr_mode_change)
3526 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3527out:
3528 return ret;
3529}
3530EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3531
53b3d9c3 3532/**
57d104c1
SJ		 3533 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3534 * state) and waits for it to take effect.
3535 *
53b3d9c3 3536 * @hba: per adapter instance
57d104c1
SJ		 3537 * @cmd: UIC command to execute
3538 *
3539 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3540 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3541 * and device UniPro link and hence it's final completion would be indicated by
3542 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3543 * addition to normal UIC command completion Status (UCCS). This function only
3544 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3545 *
3546 * Returns 0 on success, non-zero value on failure
3547 */
57d104c1 3548static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3549{
57d104c1 3550 struct completion uic_async_done;
53b3d9c3
SJ		 3551 unsigned long flags;
3552 u8 status;
3553 int ret;
d75f7fe4 3554 bool reenable_intr = false;
53b3d9c3 3555
53b3d9c3 3556 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3557 init_completion(&uic_async_done);
cad2e03d 3558 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3559
3560 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3561 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3562 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3563 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3564 /*
3565 * Make sure UIC command completion interrupt is disabled before
3566 * issuing UIC command.
3567 */
3568 wmb();
3569 reenable_intr = true;
57d104c1 3570 }
d75f7fe4
YG		 3571 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3572 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3573 if (ret) {
3574 dev_err(hba->dev,
3575 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3576 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3577 goto out;
3578 }
3579
57d104c1 3580 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3581 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3582 dev_err(hba->dev,
57d104c1
SJ		 3583 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3584 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3585 ret = -ETIMEDOUT;
3586 goto out;
3587 }
3588
3589 status = ufshcd_get_upmcrs(hba);
3590 if (status != PWR_LOCAL) {
3591 dev_err(hba->dev,
479da360 3592 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3593 cmd->command, status);
53b3d9c3
SJ		 3594 ret = (status != PWR_OK) ? status : -1;
3595 }
3596out:
7942f7b5
VG		 3597 if (ret) {
3598 ufshcd_print_host_state(hba);
3599 ufshcd_print_pwr_info(hba);
3600 ufshcd_print_host_regs(hba);
3601 }
3602
53b3d9c3 3603 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3604 hba->active_uic_cmd = NULL;
57d104c1 3605 hba->uic_async_done = NULL;
d75f7fe4
YG		 3606 if (reenable_intr)
3607 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3608 spin_unlock_irqrestore(hba->host->host_lock, flags);
3609 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3610
53b3d9c3
SJ		 3611 return ret;
3612}
3613
57d104c1
SJ		 3614/**
3615 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3616 * using DME_SET primitives.
3617 * @hba: per adapter instance
3618 * @mode: powr mode value
3619 *
3620 * Returns 0 on success, non-zero value on failure
3621 */
3622static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3623{
3624 struct uic_command uic_cmd = {0};
1ab27c9c 3625 int ret;
57d104c1 3626
c3a2f9ee
YG		 3627 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3628 ret = ufshcd_dme_set(hba,
3629 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3630 if (ret) {
3631 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3632 __func__, ret);
3633 goto out;
3634 }
3635 }
3636
57d104c1
SJ		 3637 uic_cmd.command = UIC_CMD_DME_SET;
3638 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3639 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3640 ufshcd_hold(hba, false);
3641 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3642 ufshcd_release(hba);
57d104c1 3643
c3a2f9ee 3644out:
1ab27c9c 3645 return ret;
57d104c1
SJ		 3646}
3647
53c12d0e
YG		 3648static int ufshcd_link_recovery(struct ufs_hba *hba)
3649{
3650 int ret;
3651 unsigned long flags;
3652
3653 spin_lock_irqsave(hba->host->host_lock, flags);
3654 hba->ufshcd_state = UFSHCD_STATE_RESET;
3655 ufshcd_set_eh_in_progress(hba);
3656 spin_unlock_irqrestore(hba->host->host_lock, flags);
3657
3658 ret = ufshcd_host_reset_and_restore(hba);
3659
3660 spin_lock_irqsave(hba->host->host_lock, flags);
3661 if (ret)
3662 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3663 ufshcd_clear_eh_in_progress(hba);
3664 spin_unlock_irqrestore(hba->host->host_lock, flags);
3665
3666 if (ret)
3667 dev_err(hba->dev, "%s: link recovery failed, err %d",
3668 __func__, ret);
3669
3670 return ret;
3671}
3672
87d0b4a6 3673static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3674{
87d0b4a6 3675 int ret;
57d104c1 3676 struct uic_command uic_cmd = {0};
911a0771 3677 ktime_t start = ktime_get();
57d104c1 3678
ee32c909
KK		 3679 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3680
57d104c1 3681 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3682 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3683 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3684 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3685
53c12d0e 3686 if (ret) {
87d0b4a6
YG		 3687 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3688 __func__, ret);
3689
53c12d0e
YG		 3690 /*
3691 * If link recovery fails then return error so that caller
3692 * don't retry the hibern8 enter again.
3693 */
3694 if (ufshcd_link_recovery(hba))
3695 ret = -ENOLINK;
ee32c909
KK		 3696 } else
3697 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3698 POST_CHANGE);
53c12d0e 3699
87d0b4a6
YG		 3700 return ret;
3701}
3702
3703static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3704{
3705 int ret = 0, retries;
57d104c1 3706
87d0b4a6
YG		 3707 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3708 ret = __ufshcd_uic_hibern8_enter(hba);
3709 if (!ret || ret == -ENOLINK)
3710 goto out;
3711 }
3712out:
3713 return ret;
57d104c1
SJ		 3714}
3715
3716static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3717{
3718 struct uic_command uic_cmd = {0};
3719 int ret;
911a0771 3720 ktime_t start = ktime_get();
57d104c1 3721
ee32c909
KK		 3722 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3723
57d104c1
SJ		 3724 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3725 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3726 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3727 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3728
57d104c1 3729 if (ret) {
53c12d0e
YG		 3730 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3731 __func__, ret);
3732 ret = ufshcd_link_recovery(hba);
ff8e20c6 3733 } else {
ee32c909
KK		 3734 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3735 POST_CHANGE);
ff8e20c6
DR		 3736 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3737 hba->ufs_stats.hibern8_exit_cnt++;
3738 }
57d104c1
SJ		 3739
3740 return ret;
3741}
3742
5064636c
YG		 3743 /**
3744 * ufshcd_init_pwr_info - setting the POR (power on reset)
3745 * values in hba power info
3746 * @hba: per-adapter instance
3747 */
3748static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3749{
3750 hba->pwr_info.gear_rx = UFS_PWM_G1;
3751 hba->pwr_info.gear_tx = UFS_PWM_G1;
3752 hba->pwr_info.lane_rx = 1;
3753 hba->pwr_info.lane_tx = 1;
3754 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3755 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3756 hba->pwr_info.hs_rate = 0;
3757}
3758
d3e89bac 3759/**
7eb584db
DR		 3760 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3761 * @hba: per-adapter instance
d3e89bac 3762 */
7eb584db 3763static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3764{
7eb584db
DR		 3765 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3766
3767 if (hba->max_pwr_info.is_valid)
3768 return 0;
3769
2349b533
SJ		 3770 pwr_info->pwr_tx = FAST_MODE;
3771 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3772 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3773
3774 /* Get the connected lane count */
7eb584db
DR		 3775 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3776 &pwr_info->lane_rx);
3777 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3778 &pwr_info->lane_tx);
3779
3780 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3781 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3782 __func__,
3783 pwr_info->lane_rx,
3784 pwr_info->lane_tx);
3785 return -EINVAL;
3786 }
d3e89bac
SJ		 3787
3788 /*
3789 * First, get the maximum gears of HS speed.
3790 * If a zero value, it means there is no HSGEAR capability.
3791 * Then, get the maximum gears of PWM speed.
3792 */
7eb584db
DR		 3793 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3794 if (!pwr_info->gear_rx) {
3795 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3796 &pwr_info->gear_rx);
3797 if (!pwr_info->gear_rx) {
3798 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3799 __func__, pwr_info->gear_rx);
3800 return -EINVAL;
3801 }
2349b533 3802 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3803 }
3804
7eb584db
DR		 3805 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3806 &pwr_info->gear_tx);
3807 if (!pwr_info->gear_tx) {
d3e89bac 3808 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3809 &pwr_info->gear_tx);
3810 if (!pwr_info->gear_tx) {
3811 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3812 __func__, pwr_info->gear_tx);
3813 return -EINVAL;
3814 }
2349b533 3815 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3816 }
3817
3818 hba->max_pwr_info.is_valid = true;
3819 return 0;
3820}
3821
3822static int ufshcd_change_power_mode(struct ufs_hba *hba,
3823 struct ufs_pa_layer_attr *pwr_mode)
3824{
3825 int ret;
3826
3827 /* if already configured to the requested pwr_mode */
3828 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3829 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3830 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3831 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
3832 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
3833 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
3834 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
3835 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
3836 return 0;
d3e89bac
SJ		 3837 }
3838
3839 /*
3840 * Configure attributes for power mode change with below.
3841 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
3842 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
3843 * - PA_HSSERIES
3844 */
7eb584db
DR		 3845 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
3846 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
3847 pwr_mode->lane_rx);
3848 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3849 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 3850 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 3851 else
3852 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 3853
7eb584db
DR		 3854 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
3855 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
3856 pwr_mode->lane_tx);
3857 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
3858 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 3859 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 3860 else
3861 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 3862
7eb584db
DR		 3863 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3864 pwr_mode->pwr_tx == FASTAUTO_MODE ||
3865 pwr_mode->pwr_rx == FAST_MODE ||
3866 pwr_mode->pwr_tx == FAST_MODE)
3867 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
3868 pwr_mode->hs_rate);
d3e89bac 3869
7eb584db
DR		 3870 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
3871 | pwr_mode->pwr_tx);
3872
3873 if (ret) {
d3e89bac 3874 dev_err(hba->dev,
7eb584db
DR		 3875 "%s: power mode change failed %d\n", __func__, ret);
3876 } else {
0263bcd0
YG		 3877 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
3878 pwr_mode);
7eb584db
DR		 3879
3880 memcpy(&hba->pwr_info, pwr_mode,
3881 sizeof(struct ufs_pa_layer_attr));
3882 }
3883
3884 return ret;
3885}
3886
3887/**
3888 * ufshcd_config_pwr_mode - configure a new power mode
3889 * @hba: per-adapter instance
3890 * @desired_pwr_mode: desired power configuration
3891 */
3892static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
3893 struct ufs_pa_layer_attr *desired_pwr_mode)
3894{
3895 struct ufs_pa_layer_attr final_params = { 0 };
3896 int ret;
3897
0263bcd0
YG		 3898 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
3899 desired_pwr_mode, &final_params);
3900
3901 if (ret)
7eb584db
DR		 3902 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
3903
3904 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5
SJ		 3905 if (!ret)
3906 ufshcd_print_pwr_info(hba);
d3e89bac
SJ		 3907
3908 return ret;
3909}
3910
68078d5c
DR		 3911/**
3912 * ufshcd_complete_dev_init() - checks device readiness
3913 * hba: per-adapter instance
3914 *
3915 * Set fDeviceInit flag and poll until device toggles it.
3916 */
3917static int ufshcd_complete_dev_init(struct ufs_hba *hba)
3918{
dc3c8d3a
YG		 3919 int i;
3920 int err;
68078d5c
DR		 3921 bool flag_res = 1;
3922
dc3c8d3a
YG		 3923 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3924 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 3925 if (err) {
3926 dev_err(hba->dev,
3927 "%s setting fDeviceInit flag failed with error %d\n",
3928 __func__, err);
3929 goto out;
3930 }
3931
dc3c8d3a
YG		 3932 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
3933 for (i = 0; i < 1000 && !err && flag_res; i++)
3934 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
3935 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
3936
68078d5c
DR		 3937 if (err)
3938 dev_err(hba->dev,
3939 "%s reading fDeviceInit flag failed with error %d\n",
3940 __func__, err);
3941 else if (flag_res)
3942 dev_err(hba->dev,
3943 "%s fDeviceInit was not cleared by the device\n",
3944 __func__);
3945
3946out:
3947 return err;
3948}
3949
7a3e97b0
SY		 3950/**
3951 * ufshcd_make_hba_operational - Make UFS controller operational
3952 * @hba: per adapter instance
3953 *
3954 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 3955 * 1. Enable required interrupts
3956 * 2. Configure interrupt aggregation
897efe62 3957 * 3. Program UTRL and UTMRL base address
5c0c28a8 3958 * 4. Configure run-stop-registers
7a3e97b0
SY		 3959 *
3960 * Returns 0 on success, non-zero value on failure
3961 */
3962static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3963{
3964 int err = 0;
3965 u32 reg;
3966
6ccf44fe
SJ		 3967 /* Enable required interrupts */
3968 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3969
3970 /* Configure interrupt aggregation */
b852190e
YG		 3971 if (ufshcd_is_intr_aggr_allowed(hba))
3972 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3973 else
3974 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 3975
3976 /* Configure UTRL and UTMRL base address registers */
3977 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3978 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3979 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3980 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3981 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3982 REG_UTP_TASK_REQ_LIST_BASE_L);
3983 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3984 REG_UTP_TASK_REQ_LIST_BASE_H);
3985
897efe62
YG		 3986 /*
3987 * Make sure base address and interrupt setup are updated before
3988 * enabling the run/stop registers below.
3989 */
3990 wmb();
3991
7a3e97b0
SY		 3992 /*
3993 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 3994 */
5c0c28a8 3995 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 3996 if (!(ufshcd_get_lists_status(reg))) {
3997 ufshcd_enable_run_stop_reg(hba);
3998 } else {
3b1d0580 3999 dev_err(hba->dev,
7a3e97b0
SY		 4000 "Host controller not ready to process requests");
4001 err = -EIO;
4002 goto out;
4003 }
4004
7a3e97b0
SY		 4005out:
4006 return err;
4007}
4008
596585a2
YG		 4009/**
4010 * ufshcd_hba_stop - Send controller to reset state
4011 * @hba: per adapter instance
4012 * @can_sleep: perform sleep or just spin
4013 */
4014static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4015{
4016 int err;
4017
4018 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4019 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4020 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4021 10, 1, can_sleep);
4022 if (err)
4023 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4024}
4025
7a3e97b0
SY		 4026/**
4027 * ufshcd_hba_enable - initialize the controller
4028 * @hba: per adapter instance
4029 *
4030 * The controller resets itself and controller firmware initialization
4031 * sequence kicks off. When controller is ready it will set
4032 * the Host Controller Enable bit to 1.
4033 *
4034 * Returns 0 on success, non-zero value on failure
4035 */
4036static int ufshcd_hba_enable(struct ufs_hba *hba)
4037{
4038 int retry;
4039
4040 /*
4041 * msleep of 1 and 5 used in this function might result in msleep(20),
4042 * but it was necessary to send the UFS FPGA to reset mode during
4043 * development and testing of this driver. msleep can be changed to
4044 * mdelay and retry count can be reduced based on the controller.
4045 */
596585a2 4046 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4047 /* change controller state to "reset state" */
596585a2 4048 ufshcd_hba_stop(hba, true);
7a3e97b0 4049
57d104c1
SJ		 4050 /* UniPro link is disabled at this point */
4051 ufshcd_set_link_off(hba);
4052
0263bcd0 4053 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4054
7a3e97b0
SY		 4055 /* start controller initialization sequence */
4056 ufshcd_hba_start(hba);
4057
4058 /*
4059 * To initialize a UFS host controller HCE bit must be set to 1.
4060 * During initialization the HCE bit value changes from 1->0->1.
4061 * When the host controller completes initialization sequence
4062 * it sets the value of HCE bit to 1. The same HCE bit is read back
4063 * to check if the controller has completed initialization sequence.
4064 * So without this delay the value HCE = 1, set in the previous
4065 * instruction might be read back.
4066 * This delay can be changed based on the controller.
4067 */
4068 msleep(1);
4069
4070 /* wait for the host controller to complete initialization */
4071 retry = 10;
4072 while (ufshcd_is_hba_active(hba)) {
4073 if (retry) {
4074 retry--;
4075 } else {
3b1d0580 4076 dev_err(hba->dev,
7a3e97b0
SY		 4077 "Controller enable failed\n");
4078 return -EIO;
4079 }
4080 msleep(5);
4081 }
5c0c28a8 4082
1d337ec2 4083 /* enable UIC related interrupts */
57d104c1 4084 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4085
0263bcd0 4086 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4087
7a3e97b0
SY		 4088 return 0;
4089}
4090
7ca38cf3
YG		 4091static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4092{
4093 int tx_lanes, i, err = 0;
4094
4095 if (!peer)
4096 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4097 &tx_lanes);
4098 else
4099 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4100 &tx_lanes);
4101 for (i = 0; i < tx_lanes; i++) {
4102 if (!peer)
4103 err = ufshcd_dme_set(hba,
4104 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4105 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4106 0);
4107 else
4108 err = ufshcd_dme_peer_set(hba,
4109 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4110 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4111 0);
4112 if (err) {
4113 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4114 __func__, peer, i, err);
4115 break;
4116 }
4117 }
4118
4119 return err;
4120}
4121
4122static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4123{
4124 return ufshcd_disable_tx_lcc(hba, true);
4125}
4126
7a3e97b0 4127/**
6ccf44fe 4128 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4129 * @hba: per adapter instance
4130 *
6ccf44fe 4131 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4132 */
6ccf44fe 4133static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4134{
6ccf44fe 4135 int ret;
1d337ec2 4136 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4137 bool link_startup_again = false;
7a3e97b0 4138
7caf489b
SJ		 4139 /*
4140 * If UFS device isn't active then we will have to issue link startup
4141 * 2 times to make sure the device state move to active.
4142 */
4143 if (!ufshcd_is_ufs_dev_active(hba))
4144 link_startup_again = true;
7a3e97b0 4145
7caf489b 4146link_startup:
1d337ec2 4147 do {
0263bcd0 4148 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4149
1d337ec2 4150 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4151
1d337ec2
SRT		 4152 /* check if device is detected by inter-connect layer */
4153 if (!ret && !ufshcd_is_device_present(hba)) {
4154 dev_err(hba->dev, "%s: Device not present\n", __func__);
4155 ret = -ENXIO;
4156 goto out;
4157 }
6ccf44fe 4158
1d337ec2
SRT		 4159 /*
4160 * DME link lost indication is only received when link is up,
4161 * but we can't be sure if the link is up until link startup
4162 * succeeds. So reset the local Uni-Pro and try again.
4163 */
4164 if (ret && ufshcd_hba_enable(hba))
4165 goto out;
4166 } while (ret && retries--);
4167
4168 if (ret)
4169 /* failed to get the link up... retire */
5c0c28a8 4170 goto out;
5c0c28a8 4171
7caf489b
SJ		 4172 if (link_startup_again) {
4173 link_startup_again = false;
4174 retries = DME_LINKSTARTUP_RETRIES;
4175 goto link_startup;
4176 }
4177
d2aebb9b
SJ		 4178 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4179 ufshcd_init_pwr_info(hba);
4180 ufshcd_print_pwr_info(hba);
4181
7ca38cf3
YG		 4182 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4183 ret = ufshcd_disable_device_tx_lcc(hba);
4184 if (ret)
4185 goto out;
4186 }
4187
5c0c28a8 4188 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4189 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4190 if (ret)
4191 goto out;
7a3e97b0 4192
5c0c28a8 4193 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4194out:
7942f7b5 4195 if (ret) {
6ccf44fe 4196 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4197 ufshcd_print_host_state(hba);
4198 ufshcd_print_pwr_info(hba);
4199 ufshcd_print_host_regs(hba);
4200 }
6ccf44fe 4201 return ret;
7a3e97b0
SY		 4202}
4203
5a0b0cb9
SRT		 4204/**
4205 * ufshcd_verify_dev_init() - Verify device initialization
4206 * @hba: per-adapter instance
4207 *
4208 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4209 * device Transport Protocol (UTP) layer is ready after a reset.
4210 * If the UTP layer at the device side is not initialized, it may
4211 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4212 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4213 */
4214static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4215{
4216 int err = 0;
4217 int retries;
4218
1ab27c9c 4219 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4220 mutex_lock(&hba->dev_cmd.lock);
4221 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4222 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4223 NOP_OUT_TIMEOUT);
4224
4225 if (!err || err == -ETIMEDOUT)
4226 break;
4227
4228 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4229 }
4230 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4231 ufshcd_release(hba);
5a0b0cb9
SRT		 4232
4233 if (err)
4234 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4235 return err;
4236}
4237
0ce147d4
SJ		 4238/**
4239 * ufshcd_set_queue_depth - set lun queue depth
4240 * @sdev: pointer to SCSI device
4241 *
4242 * Read bLUQueueDepth value and activate scsi tagged command
4243 * queueing. For WLUN, queue depth is set to 1. For best-effort
4244 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4245 * value that host can queue.
4246 */
4247static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4248{
4249 int ret = 0;
4250 u8 lun_qdepth;
4251 struct ufs_hba *hba;
4252
4253 hba = shost_priv(sdev->host);
4254
4255 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4256 ret = ufshcd_read_unit_desc_param(hba,
4257 ufshcd_scsi_to_upiu_lun(sdev->lun),
4258 UNIT_DESC_PARAM_LU_Q_DEPTH,
4259 &lun_qdepth,
4260 sizeof(lun_qdepth));
0ce147d4
SJ		 4261
4262 /* Some WLUN doesn't support unit descriptor */
4263 if (ret == -EOPNOTSUPP)
4264 lun_qdepth = 1;
4265 else if (!lun_qdepth)
4266 /* eventually, we can figure out the real queue depth */
4267 lun_qdepth = hba->nutrs;
4268 else
4269 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4270
4271 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4272 __func__, lun_qdepth);
db5ed4df 4273 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4274}
4275
57d104c1
SJ		 4276/*
4277 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4278 * @hba: per-adapter instance
4279 * @lun: UFS device lun id
4280 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4281 *
4282 * Returns 0 in case of success and b_lu_write_protect status would be returned
4283 * @b_lu_write_protect parameter.
4284 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4285 * Returns -EINVAL in case of invalid parameters passed to this function.
4286 */
4287static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4288 u8 lun,
4289 u8 *b_lu_write_protect)
4290{
4291 int ret;
4292
4293 if (!b_lu_write_protect)
4294 ret = -EINVAL;
4295 /*
4296 * According to UFS device spec, RPMB LU can't be write
4297 * protected so skip reading bLUWriteProtect parameter for
4298 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4299 */
4300 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4301 ret = -ENOTSUPP;
4302 else
4303 ret = ufshcd_read_unit_desc_param(hba,
4304 lun,
4305 UNIT_DESC_PARAM_LU_WR_PROTECT,
4306 b_lu_write_protect,
4307 sizeof(*b_lu_write_protect));
4308 return ret;
4309}
4310
4311/**
4312 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4313 * status
4314 * @hba: per-adapter instance
4315 * @sdev: pointer to SCSI device
4316 *
4317 */
4318static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4319 struct scsi_device *sdev)
4320{
4321 if (hba->dev_info.f_power_on_wp_en &&
4322 !hba->dev_info.is_lu_power_on_wp) {
4323 u8 b_lu_write_protect;
4324
4325 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4326 &b_lu_write_protect) &&
4327 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4328 hba->dev_info.is_lu_power_on_wp = true;
4329 }
4330}
4331
7a3e97b0
SY		 4332/**
4333 * ufshcd_slave_alloc - handle initial SCSI device configurations
4334 * @sdev: pointer to SCSI device
4335 *
4336 * Returns success
4337 */
4338static int ufshcd_slave_alloc(struct scsi_device *sdev)
4339{
4340 struct ufs_hba *hba;
4341
4342 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4343
4344 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4345 sdev->use_10_for_ms = 1;
7a3e97b0 4346
e8e7f271
SRT		 4347 /* allow SCSI layer to restart the device in case of errors */
4348 sdev->allow_restart = 1;
4264fd61 4349
b2a6c522
SRT		 4350 /* REPORT SUPPORTED OPERATION CODES is not supported */
4351 sdev->no_report_opcodes = 1;
4352
e8e7f271 4353
0ce147d4 4354 ufshcd_set_queue_depth(sdev);
4264fd61 4355
57d104c1
SJ		 4356 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4357
7a3e97b0
SY		 4358 return 0;
4359}
4360
4264fd61
SRT		 4361/**
4362 * ufshcd_change_queue_depth - change queue depth
4363 * @sdev: pointer to SCSI device
4364 * @depth: required depth to set
4264fd61 4365 *
db5ed4df 4366 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4367 */
db5ed4df 4368static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4369{
4370 struct ufs_hba *hba = shost_priv(sdev->host);
4371
4372 if (depth > hba->nutrs)
4373 depth = hba->nutrs;
db5ed4df 4374 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4375}
4376
eeda4749
AM		 4377/**
4378 * ufshcd_slave_configure - adjust SCSI device configurations
4379 * @sdev: pointer to SCSI device
4380 */
4381static int ufshcd_slave_configure(struct scsi_device *sdev)
4382{
4383 struct request_queue *q = sdev->request_queue;
4384
4385 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4386 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4387
4388 return 0;
4389}
4390
7a3e97b0
SY		 4391/**
4392 * ufshcd_slave_destroy - remove SCSI device configurations
4393 * @sdev: pointer to SCSI device
4394 */
4395static void ufshcd_slave_destroy(struct scsi_device *sdev)
4396{
4397 struct ufs_hba *hba;
4398
4399 hba = shost_priv(sdev->host);
0ce147d4 4400 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4401 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4402 unsigned long flags;
4403
4404 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4405 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4406 spin_unlock_irqrestore(hba->host->host_lock, flags);
4407 }
7a3e97b0
SY		 4408}
4409
4410/**
4411 * ufshcd_task_req_compl - handle task management request completion
4412 * @hba: per adapter instance
4413 * @index: index of the completed request
e2933132 4414 * @resp: task management service response
7a3e97b0 4415 *
e2933132 4416 * Returns non-zero value on error, zero on success
7a3e97b0 4417 */
e2933132 4418static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 4419{
4420 struct utp_task_req_desc *task_req_descp;
4421 struct utp_upiu_task_rsp *task_rsp_upiup;
4422 unsigned long flags;
4423 int ocs_value;
4424 int task_result;
4425
4426 spin_lock_irqsave(hba->host->host_lock, flags);
4427
4428 /* Clear completed tasks from outstanding_tasks */
4429 __clear_bit(index, &hba->outstanding_tasks);
4430
4431 task_req_descp = hba->utmrdl_base_addr;
4432 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
4433
4434 if (ocs_value == OCS_SUCCESS) {
4435 task_rsp_upiup = (struct utp_upiu_task_rsp *)
4436 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 4437 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
4438 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 4439 if (resp)
4440 *resp = (u8)task_result;
7a3e97b0 4441 } else {
e2933132
SRT		 4442 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
4443 __func__, ocs_value);
7a3e97b0
SY		 4444 }
4445 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 4446
4447 return ocs_value;
7a3e97b0
SY		 4448}
4449
7a3e97b0
SY		 4450/**
4451 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
4452 * @lrb: pointer to local reference block of completed command
4453 * @scsi_status: SCSI command status
4454 *
4455 * Returns value base on SCSI command status
4456 */
4457static inline int
4458ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4459{
4460 int result = 0;
4461
4462 switch (scsi_status) {
7a3e97b0 4463 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 4464 ufshcd_copy_sense_data(lrbp);
4465 case SAM_STAT_GOOD:
7a3e97b0
SY		 4466 result |= DID_OK << 16 |
4467 COMMAND_COMPLETE << 8 |
1c2623c5 4468 scsi_status;
7a3e97b0
SY		 4469 break;
4470 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4471 case SAM_STAT_BUSY:
7a3e97b0 4472 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4473 ufshcd_copy_sense_data(lrbp);
4474 result |= scsi_status;
7a3e97b0
SY		 4475 break;
4476 default:
4477 result |= DID_ERROR << 16;
4478 break;
4479 } /* end of switch */
4480
4481 return result;
4482}
4483
4484/**
4485 * ufshcd_transfer_rsp_status - Get overall status of the response
4486 * @hba: per adapter instance
4487 * @lrb: pointer to local reference block of completed command
4488 *
4489 * Returns result of the command to notify SCSI midlayer
4490 */
4491static inline int
4492ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4493{
4494 int result = 0;
4495 int scsi_status;
4496 int ocs;
4497
4498 /* overall command status of utrd */
4499 ocs = ufshcd_get_tr_ocs(lrbp);
4500
4501 switch (ocs) {
4502 case OCS_SUCCESS:
5a0b0cb9 4503 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4504 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4505 switch (result) {
4506 case UPIU_TRANSACTION_RESPONSE:
4507 /*
4508 * get the response UPIU result to extract
4509 * the SCSI command status
4510 */
4511 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4512
4513 /*
4514 * get the result based on SCSI status response
4515 * to notify the SCSI midlayer of the command status
4516 */
4517 scsi_status = result & MASK_SCSI_STATUS;
4518 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4519
f05ac2e5
YG		 4520 /*
4521 * Currently we are only supporting BKOPs exception
4522 * events hence we can ignore BKOPs exception event
4523 * during power management callbacks. BKOPs exception
4524 * event is not expected to be raised in runtime suspend
4525 * callback as it allows the urgent bkops.
4526 * During system suspend, we are anyway forcefully
4527 * disabling the bkops and if urgent bkops is needed
4528 * it will be enabled on system resume. Long term
4529 * solution could be to abort the system suspend if
4530 * UFS device needs urgent BKOPs.
4531 */
4532 if (!hba->pm_op_in_progress &&
4533 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 4534 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 4535 break;
4536 case UPIU_TRANSACTION_REJECT_UPIU:
4537 /* TODO: handle Reject UPIU Response */
4538 result = DID_ERROR << 16;
3b1d0580 4539 dev_err(hba->dev,
5a0b0cb9
SRT		 4540 "Reject UPIU not fully implemented\n");
4541 break;
4542 default:
4543 result = DID_ERROR << 16;
4544 dev_err(hba->dev,
4545 "Unexpected request response code = %x\n",
4546 result);
7a3e97b0
SY		 4547 break;
4548 }
7a3e97b0
SY		 4549 break;
4550 case OCS_ABORTED:
4551 result |= DID_ABORT << 16;
4552 break;
e8e7f271
SRT		 4553 case OCS_INVALID_COMMAND_STATUS:
4554 result |= DID_REQUEUE << 16;
4555 break;
7a3e97b0
SY		 4556 case OCS_INVALID_CMD_TABLE_ATTR:
4557 case OCS_INVALID_PRDT_ATTR:
4558 case OCS_MISMATCH_DATA_BUF_SIZE:
4559 case OCS_MISMATCH_RESP_UPIU_SIZE:
4560 case OCS_PEER_COMM_FAILURE:
4561 case OCS_FATAL_ERROR:
4562 default:
4563 result |= DID_ERROR << 16;
3b1d0580 4564 dev_err(hba->dev,
ff8e20c6
DR		 4565 "OCS error from controller = %x for tag %d\n",
4566 ocs, lrbp->task_tag);
4567 ufshcd_print_host_regs(hba);
6ba65588 4568 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4569 break;
4570 } /* end of switch */
4571
66cc820f
DR		 4572 if (host_byte(result) != DID_OK)
4573 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4574 return result;
4575}
4576
6ccf44fe
SJ		 4577/**
4578 * ufshcd_uic_cmd_compl - handle completion of uic command
4579 * @hba: per adapter instance
53b3d9c3 4580 * @intr_status: interrupt status generated by the controller
6ccf44fe 4581 */
53b3d9c3 4582static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4583{
53b3d9c3 4584 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4585 hba->active_uic_cmd->argument2 |=
4586 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4587 hba->active_uic_cmd->argument3 =
4588 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 4589 complete(&hba->active_uic_cmd->done);
4590 }
53b3d9c3 4591
57d104c1
SJ		 4592 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4593 complete(hba->uic_async_done);
6ccf44fe
SJ		 4594}
4595
7a3e97b0 4596/**
9a47ec7c 4597 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4598 * @hba: per adapter instance
9a47ec7c 4599 * @completed_reqs: requests to complete
7a3e97b0 4600 */
9a47ec7c
YG		 4601static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4602 unsigned long completed_reqs)
7a3e97b0 4603{
5a0b0cb9
SRT		 4604 struct ufshcd_lrb *lrbp;
4605 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4606 int result;
4607 int index;
e9d501b1 4608
e9d501b1
DR		 4609 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4610 lrbp = &hba->lrb[index];
4611 cmd = lrbp->cmd;
4612 if (cmd) {
1a07f2d9 4613 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4614 result = ufshcd_transfer_rsp_status(hba, lrbp);
4615 scsi_dma_unmap(cmd);
4616 cmd->result = result;
4617 /* Mark completed command as NULL in LRB */
4618 lrbp->cmd = NULL;
4619 clear_bit_unlock(index, &hba->lrb_in_use);
4620 /* Do not touch lrbp after scsi done */
4621 cmd->scsi_done(cmd);
1ab27c9c 4622 __ufshcd_release(hba);
300bb13f
JP		 4623 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4624 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 4625 if (hba->dev_cmd.complete) {
4626 ufshcd_add_command_trace(hba, index,
4627 "dev_complete");
e9d501b1 4628 complete(hba->dev_cmd.complete);
1a07f2d9 4629 }
e9d501b1 4630 }
401f1e44
SJ		 4631 if (ufshcd_is_clkscaling_supported(hba))
4632 hba->clk_scaling.active_reqs--;
09017188
ZL		 4633
4634 lrbp->compl_time_stamp = ktime_get();
e9d501b1 4635 }
7a3e97b0
SY		 4636
4637 /* clear corresponding bits of completed commands */
4638 hba->outstanding_reqs ^= completed_reqs;
4639
856b3483
ST		 4640 ufshcd_clk_scaling_update_busy(hba);
4641
5a0b0cb9
SRT		 4642 /* we might have free'd some tags above */
4643 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 4644}
4645
9a47ec7c
YG		 4646/**
4647 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4648 * @hba: per adapter instance
4649 */
4650static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4651{
4652 unsigned long completed_reqs;
4653 u32 tr_doorbell;
4654
4655 /* Resetting interrupt aggregation counters first and reading the
4656 * DOOR_BELL afterward allows us to handle all the completed requests.
4657 * In order to prevent other interrupts starvation the DB is read once
4658 * after reset. The down side of this solution is the possibility of
4659 * false interrupt if device completes another request after resetting
4660 * aggregation and before reading the DB.
4661 */
4662 if (ufshcd_is_intr_aggr_allowed(hba))
4663 ufshcd_reset_intr_aggr(hba);
4664
4665 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4666 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4667
4668 __ufshcd_transfer_req_compl(hba, completed_reqs);
4669}
4670
66ec6d59
SRT		 4671/**
4672 * ufshcd_disable_ee - disable exception event
4673 * @hba: per-adapter instance
4674 * @mask: exception event to disable
4675 *
4676 * Disables exception event in the device so that the EVENT_ALERT
4677 * bit is not set.
4678 *
4679 * Returns zero on success, non-zero error value on failure.
4680 */
4681static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4682{
4683 int err = 0;
4684 u32 val;
4685
4686 if (!(hba->ee_ctrl_mask & mask))
4687 goto out;
4688
4689 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4690 val &= MASK_EE_STATUS;
5e86ae44 4691 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4692 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4693 if (!err)
4694 hba->ee_ctrl_mask &= ~mask;
4695out:
4696 return err;
4697}
4698
4699/**
4700 * ufshcd_enable_ee - enable exception event
4701 * @hba: per-adapter instance
4702 * @mask: exception event to enable
4703 *
4704 * Enable corresponding exception event in the device to allow
4705 * device to alert host in critical scenarios.
4706 *
4707 * Returns zero on success, non-zero error value on failure.
4708 */
4709static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4710{
4711 int err = 0;
4712 u32 val;
4713
4714 if (hba->ee_ctrl_mask & mask)
4715 goto out;
4716
4717 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4718 val &= MASK_EE_STATUS;
5e86ae44 4719 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4720 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4721 if (!err)
4722 hba->ee_ctrl_mask |= mask;
4723out:
4724 return err;
4725}
4726
4727/**
4728 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4729 * @hba: per-adapter instance
4730 *
4731 * Allow device to manage background operations on its own. Enabling
4732 * this might lead to inconsistent latencies during normal data transfers
4733 * as the device is allowed to manage its own way of handling background
4734 * operations.
4735 *
4736 * Returns zero on success, non-zero on failure.
4737 */
4738static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4739{
4740 int err = 0;
4741
4742 if (hba->auto_bkops_enabled)
4743 goto out;
4744
dc3c8d3a 4745 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4746 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4747 if (err) {
4748 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4749 __func__, err);
4750 goto out;
4751 }
4752
4753 hba->auto_bkops_enabled = true;
7ff5ab47 4754 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4755
4756 /* No need of URGENT_BKOPS exception from the device */
4757 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4758 if (err)
4759 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4760 __func__, err);
4761out:
4762 return err;
4763}
4764
4765/**
4766 * ufshcd_disable_auto_bkops - block device in doing background operations
4767 * @hba: per-adapter instance
4768 *
4769 * Disabling background operations improves command response latency but
4770 * has drawback of device moving into critical state where the device is
4771 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4772 * host is idle so that BKOPS are managed effectively without any negative
4773 * impacts.
4774 *
4775 * Returns zero on success, non-zero on failure.
4776 */
4777static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4778{
4779 int err = 0;
4780
4781 if (!hba->auto_bkops_enabled)
4782 goto out;
4783
4784 /*
4785 * If host assisted BKOPs is to be enabled, make sure
4786 * urgent bkops exception is allowed.
4787 */
4788 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4789 if (err) {
4790 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4791 __func__, err);
4792 goto out;
4793 }
4794
dc3c8d3a 4795 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 4796 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4797 if (err) {
4798 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4799 __func__, err);
4800 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4801 goto out;
4802 }
4803
4804 hba->auto_bkops_enabled = false;
7ff5ab47 4805 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 4806out:
4807 return err;
4808}
4809
4810/**
4e768e76 4811 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 4812 * @hba: per adapter instance
4813 *
4814 * After a device reset the device may toggle the BKOPS_EN flag
4815 * to default value. The s/w tracking variables should be updated
4e768e76
SJ		 4816 * as well. This function would change the auto-bkops state based on
4817 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 4818 */
4e768e76 4819static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 4820{
4e768e76
SJ		 4821 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4822 hba->auto_bkops_enabled = false;
4823 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4824 ufshcd_enable_auto_bkops(hba);
4825 } else {
4826 hba->auto_bkops_enabled = true;
4827 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4828 ufshcd_disable_auto_bkops(hba);
4829 }
66ec6d59
SRT		 4830}
4831
4832static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4833{
5e86ae44 4834 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4835 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
4836}
4837
4838/**
57d104c1 4839 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 4840 * @hba: per-adapter instance
57d104c1 4841 * @status: bkops_status value
66ec6d59 4842 *
57d104c1
SJ		 4843 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
4844 * flag in the device to permit background operations if the device
4845 * bkops_status is greater than or equal to "status" argument passed to
4846 * this function, disable otherwise.
4847 *
4848 * Returns 0 for success, non-zero in case of failure.
4849 *
4850 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
4851 * to know whether auto bkops is enabled or disabled after this function
4852 * returns control to it.
66ec6d59 4853 */
57d104c1
SJ		 4854static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
4855 enum bkops_status status)
66ec6d59
SRT		 4856{
4857 int err;
57d104c1 4858 u32 curr_status = 0;
66ec6d59 4859
57d104c1 4860 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 4861 if (err) {
4862 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4863 __func__, err);
4864 goto out;
57d104c1
SJ		 4865 } else if (curr_status > BKOPS_STATUS_MAX) {
4866 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
4867 __func__, curr_status);
4868 err = -EINVAL;
4869 goto out;
66ec6d59
SRT		 4870 }
4871
57d104c1 4872 if (curr_status >= status)
66ec6d59 4873 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 4874 else
4875 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 4876out:
4877 return err;
4878}
4879
57d104c1
SJ		 4880/**
4881 * ufshcd_urgent_bkops - handle urgent bkops exception event
4882 * @hba: per-adapter instance
4883 *
4884 * Enable fBackgroundOpsEn flag in the device to permit background
4885 * operations.
4886 *
4887 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
4888 * and negative error value for any other failure.
4889 */
4890static int ufshcd_urgent_bkops(struct ufs_hba *hba)
4891{
afdfff59 4892 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 4893}
4894
66ec6d59
SRT		 4895static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
4896{
5e86ae44 4897 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4898 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
4899}
4900
afdfff59
YG		 4901static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
4902{
4903 int err;
4904 u32 curr_status = 0;
4905
4906 if (hba->is_urgent_bkops_lvl_checked)
4907 goto enable_auto_bkops;
4908
4909 err = ufshcd_get_bkops_status(hba, &curr_status);
4910 if (err) {
4911 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4912 __func__, err);
4913 goto out;
4914 }
4915
4916 /*
4917 * We are seeing that some devices are raising the urgent bkops
4918 * exception events even when BKOPS status doesn't indicate performace
4919 * impacted or critical. Handle these device by determining their urgent
4920 * bkops status at runtime.
4921 */
4922 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
4923 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
4924 __func__, curr_status);
4925 /* update the current status as the urgent bkops level */
4926 hba->urgent_bkops_lvl = curr_status;
4927 hba->is_urgent_bkops_lvl_checked = true;
4928 }
4929
4930enable_auto_bkops:
4931 err = ufshcd_enable_auto_bkops(hba);
4932out:
4933 if (err < 0)
4934 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
4935 __func__, err);
4936}
4937
66ec6d59
SRT		 4938/**
4939 * ufshcd_exception_event_handler - handle exceptions raised by device
4940 * @work: pointer to work data
4941 *
4942 * Read bExceptionEventStatus attribute from the device and handle the
4943 * exception event accordingly.
4944 */
4945static void ufshcd_exception_event_handler(struct work_struct *work)
4946{
4947 struct ufs_hba *hba;
4948 int err;
4949 u32 status = 0;
4950 hba = container_of(work, struct ufs_hba, eeh_work);
4951
62694735 4952 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 4953 err = ufshcd_get_ee_status(hba, &status);
4954 if (err) {
4955 dev_err(hba->dev, "%s: failed to get exception status %d\n",
4956 __func__, err);
4957 goto out;
4958 }
4959
4960 status &= hba->ee_ctrl_mask;
afdfff59
YG		 4961
4962 if (status & MASK_EE_URGENT_BKOPS)
4963 ufshcd_bkops_exception_event_handler(hba);
4964
66ec6d59 4965out:
62694735 4966 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 4967 return;
4968}
4969
9a47ec7c
YG		 4970/* Complete requests that have door-bell cleared */
4971static void ufshcd_complete_requests(struct ufs_hba *hba)
4972{
4973 ufshcd_transfer_req_compl(hba);
4974 ufshcd_tmc_handler(hba);
4975}
4976
583fa62d
YG		 4977/**
4978 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
4979 * to recover from the DL NAC errors or not.
4980 * @hba: per-adapter instance
4981 *
4982 * Returns true if error handling is required, false otherwise
4983 */
4984static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
4985{
4986 unsigned long flags;
4987 bool err_handling = true;
4988
4989 spin_lock_irqsave(hba->host->host_lock, flags);
4990 /*
4991 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
4992 * device fatal error and/or DL NAC & REPLAY timeout errors.
4993 */
4994 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
4995 goto out;
4996
4997 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
4998 ((hba->saved_err & UIC_ERROR) &&
4999 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5000 goto out;
5001
5002 if ((hba->saved_err & UIC_ERROR) &&
5003 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5004 int err;
5005 /*
5006 * wait for 50ms to see if we can get any other errors or not.
5007 */
5008 spin_unlock_irqrestore(hba->host->host_lock, flags);
5009 msleep(50);
5010 spin_lock_irqsave(hba->host->host_lock, flags);
5011
5012 /*
5013 * now check if we have got any other severe errors other than
5014 * DL NAC error?
5015 */
5016 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5017 ((hba->saved_err & UIC_ERROR) &&
5018 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5019 goto out;
5020
5021 /*
5022 * As DL NAC is the only error received so far, send out NOP
5023 * command to confirm if link is still active or not.
5024 * - If we don't get any response then do error recovery.
5025 * - If we get response then clear the DL NAC error bit.
5026 */
5027
5028 spin_unlock_irqrestore(hba->host->host_lock, flags);
5029 err = ufshcd_verify_dev_init(hba);
5030 spin_lock_irqsave(hba->host->host_lock, flags);
5031
5032 if (err)
5033 goto out;
5034
5035 /* Link seems to be alive hence ignore the DL NAC errors */
5036 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5037 hba->saved_err &= ~UIC_ERROR;
5038 /* clear NAC error */
5039 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5040 if (!hba->saved_uic_err) {
5041 err_handling = false;
5042 goto out;
5043 }
5044 }
5045out:
5046 spin_unlock_irqrestore(hba->host->host_lock, flags);
5047 return err_handling;
5048}
5049
7a3e97b0 5050/**
e8e7f271
SRT		 5051 * ufshcd_err_handler - handle UFS errors that require s/w attention
5052 * @work: pointer to work structure
7a3e97b0 5053 */
e8e7f271 5054static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5055{
5056 struct ufs_hba *hba;
e8e7f271
SRT		 5057 unsigned long flags;
5058 u32 err_xfer = 0;
5059 u32 err_tm = 0;
5060 int err = 0;
5061 int tag;
9a47ec7c 5062 bool needs_reset = false;
e8e7f271
SRT		 5063
5064 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5065
62694735 5066 pm_runtime_get_sync(hba->dev);
1ab27c9c 5067 ufshcd_hold(hba, false);
e8e7f271
SRT		 5068
5069 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5070 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5071 goto out;
e8e7f271
SRT		 5072
5073 hba->ufshcd_state = UFSHCD_STATE_RESET;
5074 ufshcd_set_eh_in_progress(hba);
5075
5076 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5077 ufshcd_complete_requests(hba);
583fa62d
YG		 5078
5079 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5080 bool ret;
5081
5082 spin_unlock_irqrestore(hba->host->host_lock, flags);
5083 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5084 ret = ufshcd_quirk_dl_nac_errors(hba);
5085 spin_lock_irqsave(hba->host->host_lock, flags);
5086 if (!ret)
5087 goto skip_err_handling;
5088 }
9a47ec7c
YG		 5089 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5090 ((hba->saved_err & UIC_ERROR) &&
5091 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5092 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5093 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5094 needs_reset = true;
e8e7f271 5095
9a47ec7c
YG		 5096 /*
5097 * if host reset is required then skip clearing the pending
5098 * transfers forcefully because they will automatically get
5099 * cleared after link startup.
5100 */
5101 if (needs_reset)
5102 goto skip_pending_xfer_clear;
5103
5104 /* release lock as clear command might sleep */
5105 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5106 /* Clear pending transfer requests */
9a47ec7c
YG		 5107 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5108 if (ufshcd_clear_cmd(hba, tag)) {
5109 err_xfer = true;
5110 goto lock_skip_pending_xfer_clear;
5111 }
5112 }
e8e7f271
SRT		 5113
5114 /* Clear pending task management requests */
9a47ec7c
YG		 5115 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5116 if (ufshcd_clear_tm_cmd(hba, tag)) {
5117 err_tm = true;
5118 goto lock_skip_pending_xfer_clear;
5119 }
5120 }
e8e7f271 5121
9a47ec7c 5122lock_skip_pending_xfer_clear:
e8e7f271 5123 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5124
9a47ec7c
YG		 5125 /* Complete the requests that are cleared by s/w */
5126 ufshcd_complete_requests(hba);
5127
5128 if (err_xfer || err_tm)
5129 needs_reset = true;
5130
5131skip_pending_xfer_clear:
e8e7f271 5132 /* Fatal errors need reset */
9a47ec7c
YG		 5133 if (needs_reset) {
5134 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5135
5136 /*
5137 * ufshcd_reset_and_restore() does the link reinitialization
5138 * which will need atleast one empty doorbell slot to send the
5139 * device management commands (NOP and query commands).
5140 * If there is no slot empty at this moment then free up last
5141 * slot forcefully.
5142 */
5143 if (hba->outstanding_reqs == max_doorbells)
5144 __ufshcd_transfer_req_compl(hba,
5145 (1UL << (hba->nutrs - 1)));
5146
5147 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5148 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5149 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5150 if (err) {
5151 dev_err(hba->dev, "%s: reset and restore failed\n",
5152 __func__);
5153 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5154 }
5155 /*
5156 * Inform scsi mid-layer that we did reset and allow to handle
5157 * Unit Attention properly.
5158 */
5159 scsi_report_bus_reset(hba->host, 0);
5160 hba->saved_err = 0;
5161 hba->saved_uic_err = 0;
5162 }
9a47ec7c 5163
583fa62d 5164skip_err_handling:
9a47ec7c
YG		 5165 if (!needs_reset) {
5166 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5167 if (hba->saved_err || hba->saved_uic_err)
5168 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5169 __func__, hba->saved_err, hba->saved_uic_err);
5170 }
5171
e8e7f271
SRT		 5172 ufshcd_clear_eh_in_progress(hba);
5173
5174out:
9a47ec7c 5175 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5176 scsi_unblock_requests(hba->host);
1ab27c9c 5177 ufshcd_release(hba);
62694735 5178 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5179}
5180
ff8e20c6
DR		 5181static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5182 u32 reg)
5183{
5184 reg_hist->reg[reg_hist->pos] = reg;
5185 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5186 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5187}
5188
7a3e97b0 5189/**
e8e7f271
SRT		 5190 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5191 * @hba: per-adapter instance
7a3e97b0 5192 */
e8e7f271 5193static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5194{
5195 u32 reg;
5196
fb7b45f0
DR		 5197 /* PHY layer lane error */
5198 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5199 /* Ignore LINERESET indication, as this is not an error */
5200 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5201 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5202 /*
5203 * To know whether this error is fatal or not, DB timeout
5204 * must be checked but this error is handled separately.
5205 */
5206 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR		 5207 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5208 }
fb7b45f0 5209
e8e7f271
SRT		 5210 /* PA_INIT_ERROR is fatal and needs UIC reset */
5211 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR		 5212 if (reg)
5213 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5214
e8e7f271
SRT		 5215 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5216 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 5217 else if (hba->dev_quirks &
5218 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5219 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5220 hba->uic_error |=
5221 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5222 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5223 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5224 }
e8e7f271
SRT		 5225
5226 /* UIC NL/TL/DME errors needs software retry */
5227 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR		 5228 if (reg) {
5229 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5230 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5231 }
e8e7f271
SRT		 5232
5233 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR		 5234 if (reg) {
5235 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5236 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5237 }
e8e7f271
SRT		 5238
5239 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR		 5240 if (reg) {
5241 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5242 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5243 }
e8e7f271
SRT		 5244
5245 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5246 __func__, hba->uic_error);
5247}
5248
5249/**
5250 * ufshcd_check_errors - Check for errors that need s/w attention
5251 * @hba: per-adapter instance
5252 */
5253static void ufshcd_check_errors(struct ufs_hba *hba)
5254{
5255 bool queue_eh_work = false;
5256
7a3e97b0 5257 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5258 queue_eh_work = true;
7a3e97b0
SY		 5259
5260 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 5261 hba->uic_error = 0;
5262 ufshcd_update_uic_error(hba);
5263 if (hba->uic_error)
5264 queue_eh_work = true;
7a3e97b0 5265 }
e8e7f271
SRT		 5266
5267 if (queue_eh_work) {
9a47ec7c
YG		 5268 /*
5269 * update the transfer error masks to sticky bits, let's do this
5270 * irrespective of current ufshcd_state.
5271 */
5272 hba->saved_err |= hba->errors;
5273 hba->saved_uic_err |= hba->uic_error;
5274
e8e7f271
SRT		 5275 /* handle fatal errors only when link is functional */
5276 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5277 /* block commands from scsi mid-layer */
5278 scsi_block_requests(hba->host);
5279
141f8165 5280 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5281
5282 /* dump controller state before resetting */
5283 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5284 bool pr_prdt = !!(hba->saved_err &
5285 SYSTEM_BUS_FATAL_ERROR);
5286
5287 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5288 __func__, hba->saved_err,
5289 hba->saved_uic_err);
5290
5291 ufshcd_print_host_regs(hba);
5292 ufshcd_print_pwr_info(hba);
5293 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5294 ufshcd_print_trs(hba, hba->outstanding_reqs,
5295 pr_prdt);
5296 }
e8e7f271
SRT		 5297 schedule_work(&hba->eh_work);
5298 }
3441da7d 5299 }
e8e7f271
SRT		 5300 /*
5301 * if (!queue_eh_work) -
5302 * Other errors are either non-fatal where host recovers
5303 * itself without s/w intervention or errors that will be
5304 * handled by the SCSI core layer.
5305 */
7a3e97b0
SY		 5306}
5307
5308/**
5309 * ufshcd_tmc_handler - handle task management function completion
5310 * @hba: per adapter instance
5311 */
5312static void ufshcd_tmc_handler(struct ufs_hba *hba)
5313{
5314 u32 tm_doorbell;
5315
b873a275 5316 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5317 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 5318 wake_up(&hba->tm_wq);
7a3e97b0
SY		 5319}
5320
5321/**
5322 * ufshcd_sl_intr - Interrupt service routine
5323 * @hba: per adapter instance
5324 * @intr_status: contains interrupts generated by the controller
5325 */
5326static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5327{
5328 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5329 if (hba->errors)
e8e7f271 5330 ufshcd_check_errors(hba);
7a3e97b0 5331
53b3d9c3
SJ		 5332 if (intr_status & UFSHCD_UIC_MASK)
5333 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5334
5335 if (intr_status & UTP_TASK_REQ_COMPL)
5336 ufshcd_tmc_handler(hba);
5337
5338 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5339 ufshcd_transfer_req_compl(hba);
5340}
5341
5342/**
5343 * ufshcd_intr - Main interrupt service routine
5344 * @irq: irq number
5345 * @__hba: pointer to adapter instance
5346 *
5347 * Returns IRQ_HANDLED - If interrupt is valid
5348 * IRQ_NONE - If invalid interrupt
5349 */
5350static irqreturn_t ufshcd_intr(int irq, void *__hba)
5351{
d75f7fe4 5352 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5353 irqreturn_t retval = IRQ_NONE;
5354 struct ufs_hba *hba = __hba;
5355
5356 spin_lock(hba->host->host_lock);
b873a275 5357 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5358 enabled_intr_status =
5359 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 5360
d75f7fe4 5361 if (intr_status)
261ea452 5362 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5363
5364 if (enabled_intr_status) {
5365 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 5366 retval = IRQ_HANDLED;
5367 }
5368 spin_unlock(hba->host->host_lock);
5369 return retval;
5370}
5371
e2933132
SRT		 5372static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5373{
5374 int err = 0;
5375 u32 mask = 1 << tag;
5376 unsigned long flags;
5377
5378 if (!test_bit(tag, &hba->outstanding_tasks))
5379 goto out;
5380
5381 spin_lock_irqsave(hba->host->host_lock, flags);
5382 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
5383 spin_unlock_irqrestore(hba->host->host_lock, flags);
5384
5385 /* poll for max. 1 sec to clear door bell register by h/w */
5386 err = ufshcd_wait_for_register(hba,
5387 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5388 mask, 0, 1000, 1000, true);
e2933132
SRT		 5389out:
5390 return err;
5391}
5392
7a3e97b0
SY		 5393/**
5394 * ufshcd_issue_tm_cmd - issues task management commands to controller
5395 * @hba: per adapter instance
e2933132
SRT		 5396 * @lun_id: LUN ID to which TM command is sent
5397 * @task_id: task ID to which the TM command is applicable
5398 * @tm_function: task management function opcode
5399 * @tm_response: task management service response return value
7a3e97b0 5400 *
e2933132 5401 * Returns non-zero value on error, zero on success.
7a3e97b0 5402 */
e2933132
SRT		 5403static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5404 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 5405{
5406 struct utp_task_req_desc *task_req_descp;
5407 struct utp_upiu_task_req *task_req_upiup;
5408 struct Scsi_Host *host;
5409 unsigned long flags;
e2933132 5410 int free_slot;
7a3e97b0 5411 int err;
e2933132 5412 int task_tag;
7a3e97b0
SY		 5413
5414 host = hba->host;
5415
e2933132
SRT		 5416 /*
5417 * Get free slot, sleep if slots are unavailable.
5418 * Even though we use wait_event() which sleeps indefinitely,
5419 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5420 */
5421 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5422 ufshcd_hold(hba, false);
7a3e97b0 5423
e2933132 5424 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 5425 task_req_descp = hba->utmrdl_base_addr;
5426 task_req_descp += free_slot;
5427
5428 /* Configure task request descriptor */
5429 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5430 task_req_descp->header.dword_2 =
5431 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5432
5433 /* Configure task request UPIU */
5434 task_req_upiup =
5435 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 5436 task_tag = hba->nutrs + free_slot;
7a3e97b0 5437 task_req_upiup->header.dword_0 =
5a0b0cb9 5438 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 5439 lun_id, task_tag);
7a3e97b0 5440 task_req_upiup->header.dword_1 =
5a0b0cb9 5441 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 5442 /*
5443 * The host shall provide the same value for LUN field in the basic
5444 * header and for Input Parameter.
5445 */
e2933132
SRT		 5446 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
5447 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 5448
d2877be4
KK		 5449 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5450
7a3e97b0
SY		 5451 /* send command to the controller */
5452 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5453
5454 /* Make sure descriptors are ready before ringing the task doorbell */
5455 wmb();
5456
b873a275 5457 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5458 /* Make sure that doorbell is committed immediately */
5459 wmb();
7a3e97b0
SY		 5460
5461 spin_unlock_irqrestore(host->host_lock, flags);
5462
5463 /* wait until the task management command is completed */
e2933132
SRT		 5464 err = wait_event_timeout(hba->tm_wq,
5465 test_bit(free_slot, &hba->tm_condition),
5466 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5467 if (!err) {
e2933132
SRT		 5468 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5469 __func__, tm_function);
5470 if (ufshcd_clear_tm_cmd(hba, free_slot))
5471 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5472 __func__, free_slot);
5473 err = -ETIMEDOUT;
5474 } else {
5475 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 5476 }
e2933132 5477
7a3e97b0 5478 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 5479 ufshcd_put_tm_slot(hba, free_slot);
5480 wake_up(&hba->tm_tag_wq);
5481
1ab27c9c 5482 ufshcd_release(hba);
7a3e97b0
SY		 5483 return err;
5484}
5485
5486/**
3441da7d
SRT		 5487 * ufshcd_eh_device_reset_handler - device reset handler registered to
5488 * scsi layer.
7a3e97b0
SY		 5489 * @cmd: SCSI command pointer
5490 *
5491 * Returns SUCCESS/FAILED
5492 */
3441da7d 5493static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5494{
5495 struct Scsi_Host *host;
5496 struct ufs_hba *hba;
5497 unsigned int tag;
5498 u32 pos;
5499 int err;
e2933132
SRT		 5500 u8 resp = 0xF;
5501 struct ufshcd_lrb *lrbp;
3441da7d 5502 unsigned long flags;
7a3e97b0
SY		 5503
5504 host = cmd->device->host;
5505 hba = shost_priv(host);
5506 tag = cmd->request->tag;
5507
e2933132
SRT		 5508 lrbp = &hba->lrb[tag];
5509 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5510 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 5511 if (!err)
5512 err = resp;
7a3e97b0 5513 goto out;
e2933132 5514 }
7a3e97b0 5515
3441da7d
SRT		 5516 /* clear the commands that were pending for corresponding LUN */
5517 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5518 if (hba->lrb[pos].lun == lrbp->lun) {
5519 err = ufshcd_clear_cmd(hba, pos);
5520 if (err)
5521 break;
7a3e97b0 5522 }
3441da7d
SRT		 5523 }
5524 spin_lock_irqsave(host->host_lock, flags);
5525 ufshcd_transfer_req_compl(hba);
5526 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5527
7a3e97b0 5528out:
7fabb77b 5529 hba->req_abort_count = 0;
3441da7d
SRT		 5530 if (!err) {
5531 err = SUCCESS;
5532 } else {
5533 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5534 err = FAILED;
5535 }
7a3e97b0
SY		 5536 return err;
5537}
5538
e0b299e3
GB		 5539static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5540{
5541 struct ufshcd_lrb *lrbp;
5542 int tag;
5543
5544 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5545 lrbp = &hba->lrb[tag];
5546 lrbp->req_abort_skip = true;
5547 }
5548}
5549
7a3e97b0
SY		 5550/**
5551 * ufshcd_abort - abort a specific command
5552 * @cmd: SCSI command pointer
5553 *
f20810d8
SRT		 5554 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5555 * command, and in host controller by clearing the door-bell register. There can
5556 * be race between controller sending the command to the device while abort is
5557 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5558 * really issued and then try to abort it.
5559 *
7a3e97b0
SY		 5560 * Returns SUCCESS/FAILED
5561 */
5562static int ufshcd_abort(struct scsi_cmnd *cmd)
5563{
5564 struct Scsi_Host *host;
5565 struct ufs_hba *hba;
5566 unsigned long flags;
5567 unsigned int tag;
f20810d8
SRT		 5568 int err = 0;
5569 int poll_cnt;
e2933132
SRT		 5570 u8 resp = 0xF;
5571 struct ufshcd_lrb *lrbp;
e9d501b1 5572 u32 reg;
7a3e97b0
SY		 5573
5574 host = cmd->device->host;
5575 hba = shost_priv(host);
5576 tag = cmd->request->tag;
e7d38257 5577 lrbp = &hba->lrb[tag];
14497328
YG		 5578 if (!ufshcd_valid_tag(hba, tag)) {
5579 dev_err(hba->dev,
5580 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5581 __func__, tag, cmd, cmd->request);
5582 BUG();
5583 }
7a3e97b0 5584
e7d38257
DR		 5585 /*
5586 * Task abort to the device W-LUN is illegal. When this command
5587 * will fail, due to spec violation, scsi err handling next step
5588 * will be to send LU reset which, again, is a spec violation.
5589 * To avoid these unnecessary/illegal step we skip to the last error
5590 * handling stage: reset and restore.
5591 */
5592 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5593 return ufshcd_eh_host_reset_handler(cmd);
5594
1ab27c9c 5595 ufshcd_hold(hba, false);
14497328 5596 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5597 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 5598 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5599 dev_err(hba->dev,
5600 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5601 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 5602 goto out;
14497328 5603 }
7a3e97b0 5604
e9d501b1
DR		 5605 if (!(reg & (1 << tag))) {
5606 dev_err(hba->dev,
5607 "%s: cmd was completed, but without a notifying intr, tag = %d",
5608 __func__, tag);
5609 }
5610
66cc820f
DR		 5611 /* Print Transfer Request of aborted task */
5612 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 5613
7fabb77b
GB		 5614 /*
5615 * Print detailed info about aborted request.
5616 * As more than one request might get aborted at the same time,
5617 * print full information only for the first aborted request in order
5618 * to reduce repeated printouts. For other aborted requests only print
5619 * basic details.
5620 */
5621 scsi_print_command(hba->lrb[tag].cmd);
5622 if (!hba->req_abort_count) {
5623 ufshcd_print_host_regs(hba);
6ba65588 5624 ufshcd_print_host_state(hba);
7fabb77b
GB		 5625 ufshcd_print_pwr_info(hba);
5626 ufshcd_print_trs(hba, 1 << tag, true);
5627 } else {
5628 ufshcd_print_trs(hba, 1 << tag, false);
5629 }
5630 hba->req_abort_count++;
e0b299e3
GB		 5631
5632 /* Skip task abort in case previous aborts failed and report failure */
5633 if (lrbp->req_abort_skip) {
5634 err = -EIO;
5635 goto out;
5636 }
5637
f20810d8
SRT		 5638 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
5639 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5640 UFS_QUERY_TASK, &resp);
5641 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
5642 /* cmd pending in the device */
ff8e20c6
DR		 5643 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
5644 __func__, tag);
f20810d8
SRT		 5645 break;
5646 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 5647 /*
5648 * cmd not pending in the device, check if it is
5649 * in transition.
5650 */
ff8e20c6
DR		 5651 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
5652 __func__, tag);
f20810d8
SRT		 5653 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5654 if (reg & (1 << tag)) {
5655 /* sleep for max. 200us to stabilize */
5656 usleep_range(100, 200);
5657 continue;
5658 }
5659 /* command completed already */
ff8e20c6
DR		 5660 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
5661 __func__, tag);
f20810d8
SRT		 5662 goto out;
5663 } else {
ff8e20c6
DR		 5664 dev_err(hba->dev,
5665 "%s: no response from device. tag = %d, err %d\n",
5666 __func__, tag, err);
f20810d8
SRT		 5667 if (!err)
5668 err = resp; /* service response error */
5669 goto out;
5670 }
5671 }
5672
5673 if (!poll_cnt) {
5674 err = -EBUSY;
7a3e97b0
SY		 5675 goto out;
5676 }
7a3e97b0 5677
e2933132
SRT		 5678 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5679 UFS_ABORT_TASK, &resp);
5680 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 5681 if (!err) {
f20810d8 5682 err = resp; /* service response error */
ff8e20c6
DR		 5683 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
5684 __func__, tag, err);
5685 }
7a3e97b0 5686 goto out;
e2933132 5687 }
7a3e97b0 5688
f20810d8 5689 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 5690 if (err) {
5691 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
5692 __func__, tag, err);
f20810d8 5693 goto out;
ff8e20c6 5694 }
f20810d8 5695
7a3e97b0
SY		 5696 scsi_dma_unmap(cmd);
5697
5698 spin_lock_irqsave(host->host_lock, flags);
a48353f6 5699 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 5700 hba->lrb[tag].cmd = NULL;
5701 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 5702
5703 clear_bit_unlock(tag, &hba->lrb_in_use);
5704 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 5705
7a3e97b0 5706out:
f20810d8
SRT		 5707 if (!err) {
5708 err = SUCCESS;
5709 } else {
5710 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 5711 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 5712 err = FAILED;
5713 }
5714
1ab27c9c
ST		 5715 /*
5716 * This ufshcd_release() corresponds to the original scsi cmd that got
5717 * aborted here (as we won't get any IRQ for it).
5718 */
5719 ufshcd_release(hba);
7a3e97b0
SY		 5720 return err;
5721}
5722
3441da7d
SRT		 5723/**
5724 * ufshcd_host_reset_and_restore - reset and restore host controller
5725 * @hba: per-adapter instance
5726 *
5727 * Note that host controller reset may issue DME_RESET to
5728 * local and remote (device) Uni-Pro stack and the attributes
5729 * are reset to default state.
5730 *
5731 * Returns zero on success, non-zero on failure
5732 */
5733static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
5734{
5735 int err;
3441da7d
SRT		 5736 unsigned long flags;
5737
5738 /* Reset the host controller */
5739 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 5740 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 5741 spin_unlock_irqrestore(hba->host->host_lock, flags);
5742
a3cd5ec5
SJ		 5743 /* scale up clocks to max frequency before full reinitialization */
5744 ufshcd_scale_clks(hba, true);
5745
3441da7d
SRT		 5746 err = ufshcd_hba_enable(hba);
5747 if (err)
5748 goto out;
5749
5750 /* Establish the link again and restore the device */
1d337ec2
SRT		 5751 err = ufshcd_probe_hba(hba);
5752
5753 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 5754 err = -EIO;
5755out:
5756 if (err)
5757 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
5758
5759 return err;
5760}
5761
5762/**
5763 * ufshcd_reset_and_restore - reset and re-initialize host/device
5764 * @hba: per-adapter instance
5765 *
5766 * Reset and recover device, host and re-establish link. This
5767 * is helpful to recover the communication in fatal error conditions.
5768 *
5769 * Returns zero on success, non-zero on failure
5770 */
5771static int ufshcd_reset_and_restore(struct ufs_hba *hba)
5772{
5773 int err = 0;
5774 unsigned long flags;
1d337ec2 5775 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 5776
1d337ec2
SRT		 5777 do {
5778 err = ufshcd_host_reset_and_restore(hba);
5779 } while (err && --retries);
3441da7d
SRT		 5780
5781 /*
5782 * After reset the door-bell might be cleared, complete
5783 * outstanding requests in s/w here.
5784 */
5785 spin_lock_irqsave(hba->host->host_lock, flags);
5786 ufshcd_transfer_req_compl(hba);
5787 ufshcd_tmc_handler(hba);
5788 spin_unlock_irqrestore(hba->host->host_lock, flags);
5789
5790 return err;
5791}
5792
5793/**
5794 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
5795 * @cmd - SCSI command pointer
5796 *
5797 * Returns SUCCESS/FAILED
5798 */
5799static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
5800{
5801 int err;
5802 unsigned long flags;
5803 struct ufs_hba *hba;
5804
5805 hba = shost_priv(cmd->device->host);
5806
1ab27c9c 5807 ufshcd_hold(hba, false);
3441da7d
SRT		 5808 /*
5809 * Check if there is any race with fatal error handling.
5810 * If so, wait for it to complete. Even though fatal error
5811 * handling does reset and restore in some cases, don't assume
5812 * anything out of it. We are just avoiding race here.
5813 */
5814 do {
5815 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5816 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 5817 hba->ufshcd_state == UFSHCD_STATE_RESET ||
5818 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 5819 break;
5820 spin_unlock_irqrestore(hba->host->host_lock, flags);
5821 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 5822 flush_work(&hba->eh_work);
3441da7d
SRT		 5823 } while (1);
5824
5825 hba->ufshcd_state = UFSHCD_STATE_RESET;
5826 ufshcd_set_eh_in_progress(hba);
5827 spin_unlock_irqrestore(hba->host->host_lock, flags);
5828
5829 err = ufshcd_reset_and_restore(hba);
5830
5831 spin_lock_irqsave(hba->host->host_lock, flags);
5832 if (!err) {
5833 err = SUCCESS;
5834 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5835 } else {
5836 err = FAILED;
5837 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5838 }
5839 ufshcd_clear_eh_in_progress(hba);
5840 spin_unlock_irqrestore(hba->host->host_lock, flags);
5841
1ab27c9c 5842 ufshcd_release(hba);
3441da7d
SRT		 5843 return err;
5844}
5845
3a4bf06d
YG		 5846/**
5847 * ufshcd_get_max_icc_level - calculate the ICC level
5848 * @sup_curr_uA: max. current supported by the regulator
5849 * @start_scan: row at the desc table to start scan from
5850 * @buff: power descriptor buffer
5851 *
5852 * Returns calculated max ICC level for specific regulator
5853 */
5854static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
5855{
5856 int i;
5857 int curr_uA;
5858 u16 data;
5859 u16 unit;
5860
5861 for (i = start_scan; i >= 0; i--) {
d79713f9 5862 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 5863 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
5864 ATTR_ICC_LVL_UNIT_OFFSET;
5865 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
5866 switch (unit) {
5867 case UFSHCD_NANO_AMP:
5868 curr_uA = curr_uA / 1000;
5869 break;
5870 case UFSHCD_MILI_AMP:
5871 curr_uA = curr_uA * 1000;
5872 break;
5873 case UFSHCD_AMP:
5874 curr_uA = curr_uA * 1000 * 1000;
5875 break;
5876 case UFSHCD_MICRO_AMP:
5877 default:
5878 break;
5879 }
5880 if (sup_curr_uA >= curr_uA)
5881 break;
5882 }
5883 if (i < 0) {
5884 i = 0;
5885 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
5886 }
5887
5888 return (u32)i;
5889}
5890
5891/**
5892 * ufshcd_calc_icc_level - calculate the max ICC level
5893 * In case regulators are not initialized we'll return 0
5894 * @hba: per-adapter instance
5895 * @desc_buf: power descriptor buffer to extract ICC levels from.
5896 * @len: length of desc_buff
5897 *
5898 * Returns calculated ICC level
5899 */
5900static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
5901 u8 *desc_buf, int len)
5902{
5903 u32 icc_level = 0;
5904
5905 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
5906 !hba->vreg_info.vccq2) {
5907 dev_err(hba->dev,
5908 "%s: Regulator capability was not set, actvIccLevel=%d",
5909 __func__, icc_level);
5910 goto out;
5911 }
5912
5913 if (hba->vreg_info.vcc)
5914 icc_level = ufshcd_get_max_icc_level(
5915 hba->vreg_info.vcc->max_uA,
5916 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
5917 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
5918
5919 if (hba->vreg_info.vccq)
5920 icc_level = ufshcd_get_max_icc_level(
5921 hba->vreg_info.vccq->max_uA,
5922 icc_level,
5923 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
5924
5925 if (hba->vreg_info.vccq2)
5926 icc_level = ufshcd_get_max_icc_level(
5927 hba->vreg_info.vccq2->max_uA,
5928 icc_level,
5929 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
5930out:
5931 return icc_level;
5932}
5933
5934static void ufshcd_init_icc_levels(struct ufs_hba *hba)
5935{
5936 int ret;
a4b0e8a4
PM		 5937 int buff_len = hba->desc_size.pwr_desc;
5938 u8 desc_buf[hba->desc_size.pwr_desc];
3a4bf06d
YG		 5939
5940 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
5941 if (ret) {
5942 dev_err(hba->dev,
5943 "%s: Failed reading power descriptor.len = %d ret = %d",
5944 __func__, buff_len, ret);
5945 return;
5946 }
5947
5948 hba->init_prefetch_data.icc_level =
5949 ufshcd_find_max_sup_active_icc_level(hba,
5950 desc_buf, buff_len);
5951 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
5952 __func__, hba->init_prefetch_data.icc_level);
5953
dbd34a61
SM		 5954 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5955 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
5956 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 5957
5958 if (ret)
5959 dev_err(hba->dev,
5960 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
5961 __func__, hba->init_prefetch_data.icc_level , ret);
5962
5963}
5964
2a8fa600
SJ		 5965/**
5966 * ufshcd_scsi_add_wlus - Adds required W-LUs
5967 * @hba: per-adapter instance
5968 *
5969 * UFS device specification requires the UFS devices to support 4 well known
5970 * logical units:
5971 * "REPORT_LUNS" (address: 01h)
5972 * "UFS Device" (address: 50h)
5973 * "RPMB" (address: 44h)
5974 * "BOOT" (address: 30h)
5975 * UFS device's power management needs to be controlled by "POWER CONDITION"
5976 * field of SSU (START STOP UNIT) command. But this "power condition" field
5977 * will take effect only when its sent to "UFS device" well known logical unit
5978 * hence we require the scsi_device instance to represent this logical unit in
5979 * order for the UFS host driver to send the SSU command for power management.
5980
5981 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
5982 * Block) LU so user space process can control this LU. User space may also
5983 * want to have access to BOOT LU.
5984
5985 * This function adds scsi device instances for each of all well known LUs
5986 * (except "REPORT LUNS" LU).
5987 *
5988 * Returns zero on success (all required W-LUs are added successfully),
5989 * non-zero error value on failure (if failed to add any of the required W-LU).
5990 */
5991static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
5992{
5993 int ret = 0;
7c48bfd0
AM		 5994 struct scsi_device *sdev_rpmb;
5995 struct scsi_device *sdev_boot;
2a8fa600
SJ		 5996
5997 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
5998 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
5999 if (IS_ERR(hba->sdev_ufs_device)) {
6000 ret = PTR_ERR(hba->sdev_ufs_device);
6001 hba->sdev_ufs_device = NULL;
6002 goto out;
6003 }
7c48bfd0 6004 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6005
7c48bfd0 6006 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6007 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6008 if (IS_ERR(sdev_rpmb)) {
6009 ret = PTR_ERR(sdev_rpmb);
3d21fbde 6010 goto remove_sdev_ufs_device;
2a8fa600 6011 }
7c48bfd0 6012 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 6013
6014 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6015 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
6016 if (IS_ERR(sdev_boot))
6017 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
6018 else
6019 scsi_device_put(sdev_boot);
2a8fa600
SJ		 6020 goto out;
6021
2a8fa600
SJ		 6022remove_sdev_ufs_device:
6023 scsi_remove_device(hba->sdev_ufs_device);
6024out:
6025 return ret;
6026}
6027
93fdd5ac
TW		 6028static int ufs_get_device_desc(struct ufs_hba *hba,
6029 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6030{
6031 int err;
6032 u8 model_index;
a4b0e8a4
PM		 6033 u8 str_desc_buf[QUERY_DESC_MAX_SIZE + 1] = {0};
6034 u8 desc_buf[hba->desc_size.dev_desc];
c58ab7aa 6035
a4b0e8a4 6036 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
c58ab7aa
YG		 6037 if (err) {
6038 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6039 __func__, err);
6040 goto out;
6041 }
6042
6043 /*
6044 * getting vendor (manufacturerID) and Bank Index in big endian
6045 * format
6046 */
93fdd5ac 6047 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6048 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6049
6050 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6051
6052 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
a4b0e8a4 6053 QUERY_DESC_MAX_SIZE, ASCII_STD);
c58ab7aa
YG		 6054 if (err) {
6055 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6056 __func__, err);
6057 goto out;
6058 }
6059
a4b0e8a4 6060 str_desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
93fdd5ac 6061 strlcpy(dev_desc->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
c58ab7aa
YG		 6062 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
6063 MAX_MODEL_LEN));
6064
6065 /* Null terminate the model string */
93fdd5ac 6066 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG		 6067
6068out:
6069 return err;
6070}
6071
93fdd5ac
TW		 6072static void ufs_fixup_device_setup(struct ufs_hba *hba,
6073 struct ufs_dev_desc *dev_desc)
c58ab7aa 6074{
c58ab7aa 6075 struct ufs_dev_fix *f;
c58ab7aa
YG		 6076
6077 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6078 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6079 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6080 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG		 6081 !strcmp(f->card.model, UFS_ANY_MODEL)))
6082 hba->dev_quirks |= f->quirk;
6083 }
6084}
6085
37113106
YG		 6086/**
6087 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6088 * @hba: per-adapter instance
6089 *
6090 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6091 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6092 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6093 * the hibern8 exit latency.
6094 *
6095 * Returns zero on success, non-zero error value on failure.
6096 */
6097static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6098{
6099 int ret = 0;
6100 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6101
6102 ret = ufshcd_dme_peer_get(hba,
6103 UIC_ARG_MIB_SEL(
6104 RX_MIN_ACTIVATETIME_CAPABILITY,
6105 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6106 &peer_rx_min_activatetime);
6107 if (ret)
6108 goto out;
6109
6110 /* make sure proper unit conversion is applied */
6111 tuned_pa_tactivate =
6112 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6113 / PA_TACTIVATE_TIME_UNIT_US);
6114 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6115 tuned_pa_tactivate);
6116
6117out:
6118 return ret;
6119}
6120
6121/**
6122 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6123 * @hba: per-adapter instance
6124 *
6125 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6126 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6127 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6128 * This optimal value can help reduce the hibern8 exit latency.
6129 *
6130 * Returns zero on success, non-zero error value on failure.
6131 */
6132static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6133{
6134 int ret = 0;
6135 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6136 u32 max_hibern8_time, tuned_pa_hibern8time;
6137
6138 ret = ufshcd_dme_get(hba,
6139 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6140 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6141 &local_tx_hibern8_time_cap);
6142 if (ret)
6143 goto out;
6144
6145 ret = ufshcd_dme_peer_get(hba,
6146 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6147 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6148 &peer_rx_hibern8_time_cap);
6149 if (ret)
6150 goto out;
6151
6152 max_hibern8_time = max(local_tx_hibern8_time_cap,
6153 peer_rx_hibern8_time_cap);
6154 /* make sure proper unit conversion is applied */
6155 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6156 / PA_HIBERN8_TIME_UNIT_US);
6157 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6158 tuned_pa_hibern8time);
6159out:
6160 return ret;
6161}
6162
c6a6db43
SJ		 6163/**
6164 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6165 * less than device PA_TACTIVATE time.
6166 * @hba: per-adapter instance
6167 *
6168 * Some UFS devices require host PA_TACTIVATE to be lower than device
6169 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6170 * for such devices.
6171 *
6172 * Returns zero on success, non-zero error value on failure.
6173 */
6174static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6175{
6176 int ret = 0;
6177 u32 granularity, peer_granularity;
6178 u32 pa_tactivate, peer_pa_tactivate;
6179 u32 pa_tactivate_us, peer_pa_tactivate_us;
6180 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6181
6182 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6183 &granularity);
6184 if (ret)
6185 goto out;
6186
6187 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6188 &peer_granularity);
6189 if (ret)
6190 goto out;
6191
6192 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6193 (granularity > PA_GRANULARITY_MAX_VAL)) {
6194 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6195 __func__, granularity);
6196 return -EINVAL;
6197 }
6198
6199 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6200 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6201 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6202 __func__, peer_granularity);
6203 return -EINVAL;
6204 }
6205
6206 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6207 if (ret)
6208 goto out;
6209
6210 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6211 &peer_pa_tactivate);
6212 if (ret)
6213 goto out;
6214
6215 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6216 peer_pa_tactivate_us = peer_pa_tactivate *
6217 gran_to_us_table[peer_granularity - 1];
6218
6219 if (pa_tactivate_us > peer_pa_tactivate_us) {
6220 u32 new_peer_pa_tactivate;
6221
6222 new_peer_pa_tactivate = pa_tactivate_us /
6223 gran_to_us_table[peer_granularity - 1];
6224 new_peer_pa_tactivate++;
6225 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6226 new_peer_pa_tactivate);
6227 }
6228
6229out:
6230 return ret;
6231}
6232
37113106
YG		 6233static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6234{
6235 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6236 ufshcd_tune_pa_tactivate(hba);
6237 ufshcd_tune_pa_hibern8time(hba);
6238 }
6239
6240 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6241 /* set 1ms timeout for PA_TACTIVATE */
6242 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43
SJ		 6243
6244 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6245 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6246
6247 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6248}
6249
ff8e20c6
DR		 6250static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6251{
6252 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6253
6254 hba->ufs_stats.hibern8_exit_cnt = 0;
6255 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6256
6257 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6258 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6259 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6260 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6261 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB		 6262
6263 hba->req_abort_count = 0;
ff8e20c6
DR		 6264}
6265
a4b0e8a4
PM		 6266static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6267{
6268 int err;
6269
6270 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6271 &hba->desc_size.dev_desc);
6272 if (err)
6273 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6274
6275 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6276 &hba->desc_size.pwr_desc);
6277 if (err)
6278 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6279
6280 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6281 &hba->desc_size.interc_desc);
6282 if (err)
6283 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6284
6285 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6286 &hba->desc_size.conf_desc);
6287 if (err)
6288 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6289
6290 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6291 &hba->desc_size.unit_desc);
6292 if (err)
6293 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6294
6295 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6296 &hba->desc_size.geom_desc);
6297 if (err)
6298 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6299}
6300
6301static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6302{
6303 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6304 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6305 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6306 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6307 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6308 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6309}
6310
6ccf44fe 6311/**
1d337ec2
SRT		 6312 * ufshcd_probe_hba - probe hba to detect device and initialize
6313 * @hba: per-adapter instance
6314 *
6315 * Execute link-startup and verify device initialization
6ccf44fe 6316 */
1d337ec2 6317static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6318{
93fdd5ac 6319 struct ufs_dev_desc card = {0};
6ccf44fe 6320 int ret;
7ff5ab47 6321 ktime_t start = ktime_get();
6ccf44fe
SJ		 6322
6323 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6324 if (ret)
6325 goto out;
6326
afdfff59
YG		 6327 /* set the default level for urgent bkops */
6328 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6329 hba->is_urgent_bkops_lvl_checked = false;
6330
ff8e20c6
DR		 6331 /* Debug counters initialization */
6332 ufshcd_clear_dbg_ufs_stats(hba);
6333
57d104c1
SJ		 6334 /* UniPro link is active now */
6335 ufshcd_set_link_active(hba);
d3e89bac 6336
5a0b0cb9
SRT		 6337 ret = ufshcd_verify_dev_init(hba);
6338 if (ret)
6339 goto out;
68078d5c
DR		 6340
6341 ret = ufshcd_complete_dev_init(hba);
6342 if (ret)
6343 goto out;
5a0b0cb9 6344
a4b0e8a4
PM		 6345 /* Init check for device descriptor sizes */
6346 ufshcd_init_desc_sizes(hba);
6347
93fdd5ac
TW		 6348 ret = ufs_get_device_desc(hba, &card);
6349 if (ret) {
6350 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6351 __func__, ret);
6352 goto out;
6353 }
6354
6355 ufs_fixup_device_setup(hba, &card);
37113106 6356 ufshcd_tune_unipro_params(hba);
60f01870
YG		 6357
6358 ret = ufshcd_set_vccq_rail_unused(hba,
6359 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6360 if (ret)
6361 goto out;
6362
57d104c1
SJ		 6363 /* UFS device is also active now */
6364 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6365 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6366 hba->wlun_dev_clr_ua = true;
6367
7eb584db
DR		 6368 if (ufshcd_get_max_pwr_mode(hba)) {
6369 dev_err(hba->dev,
6370 "%s: Failed getting max supported power mode\n",
6371 __func__);
6372 } else {
6373 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6374 if (ret) {
7eb584db
DR		 6375 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6376 __func__, ret);
8643ae66
DL		 6377 goto out;
6378 }
7eb584db 6379 }
57d104c1 6380
53c12d0e
YG		 6381 /* set the state as operational after switching to desired gear */
6382 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 6383
57d104c1
SJ		 6384 /*
6385 * If we are in error handling context or in power management callbacks
6386 * context, no need to scan the host
6387 */
6388 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6389 bool flag;
6390
6391 /* clear any previous UFS device information */
6392 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 6393 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6394 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6395 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6396
3a4bf06d
YG		 6397 if (!hba->is_init_prefetch)
6398 ufshcd_init_icc_levels(hba);
6399
2a8fa600
SJ		 6400 /* Add required well known logical units to scsi mid layer */
6401 if (ufshcd_scsi_add_wlus(hba))
6402 goto out;
6403
0701e49d
SJ		 6404 /* Initialize devfreq after UFS device is detected */
6405 if (ufshcd_is_clkscaling_supported(hba)) {
6406 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6407 &hba->pwr_info,
6408 sizeof(struct ufs_pa_layer_attr));
6409 hba->clk_scaling.saved_pwr_info.is_valid = true;
6410 if (!hba->devfreq) {
6411 hba->devfreq = devm_devfreq_add_device(hba->dev,
6412 &ufs_devfreq_profile,
6413 "simple_ondemand",
6414 NULL);
6415 if (IS_ERR(hba->devfreq)) {
6416 ret = PTR_ERR(hba->devfreq);
6417 dev_err(hba->dev, "Unable to register with devfreq %d\n",
6418 ret);
6419 goto out;
6420 }
6421 }
6422 hba->clk_scaling.is_allowed = true;
6423 }
6424
3441da7d
SRT		 6425 scsi_scan_host(hba->host);
6426 pm_runtime_put_sync(hba->dev);
6427 }
3a4bf06d
YG		 6428
6429 if (!hba->is_init_prefetch)
6430 hba->is_init_prefetch = true;
6431
5a0b0cb9 6432out:
1d337ec2
SRT		 6433 /*
6434 * If we failed to initialize the device or the device is not
6435 * present, turn off the power/clocks etc.
6436 */
57d104c1
SJ		 6437 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6438 pm_runtime_put_sync(hba->dev);
1d337ec2 6439 ufshcd_hba_exit(hba);
57d104c1 6440 }
1d337ec2 6441
7ff5ab47
SJ		 6442 trace_ufshcd_init(dev_name(hba->dev), ret,
6443 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6444 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 6445 return ret;
6446}
6447
6448/**
6449 * ufshcd_async_scan - asynchronous execution for probing hba
6450 * @data: data pointer to pass to this function
6451 * @cookie: cookie data
6452 */
6453static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6454{
6455 struct ufs_hba *hba = (struct ufs_hba *)data;
6456
6457 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 6458}
6459
f550c65b
YG		 6460static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6461{
6462 unsigned long flags;
6463 struct Scsi_Host *host;
6464 struct ufs_hba *hba;
6465 int index;
6466 bool found = false;
6467
6468 if (!scmd || !scmd->device || !scmd->device->host)
6469 return BLK_EH_NOT_HANDLED;
6470
6471 host = scmd->device->host;
6472 hba = shost_priv(host);
6473 if (!hba)
6474 return BLK_EH_NOT_HANDLED;
6475
6476 spin_lock_irqsave(host->host_lock, flags);
6477
6478 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6479 if (hba->lrb[index].cmd == scmd) {
6480 found = true;
6481 break;
6482 }
6483 }
6484
6485 spin_unlock_irqrestore(host->host_lock, flags);
6486
6487 /*
6488 * Bypass SCSI error handling and reset the block layer timer if this
6489 * SCSI command was not actually dispatched to UFS driver, otherwise
6490 * let SCSI layer handle the error as usual.
6491 */
6492 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
6493}
6494
7a3e97b0
SY		 6495static struct scsi_host_template ufshcd_driver_template = {
6496 .module = THIS_MODULE,
6497 .name = UFSHCD,
6498 .proc_name = UFSHCD,
6499 .queuecommand = ufshcd_queuecommand,
6500 .slave_alloc = ufshcd_slave_alloc,
eeda4749 6501 .slave_configure = ufshcd_slave_configure,
7a3e97b0 6502 .slave_destroy = ufshcd_slave_destroy,
4264fd61 6503 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 6504 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 6505 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6506 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 6507 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 6508 .this_id = -1,
6509 .sg_tablesize = SG_ALL,
6510 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6511 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 6512 .max_host_blocked = 1,
c40ecc12 6513 .track_queue_depth = 1,
7a3e97b0
SY		 6514};
6515
57d104c1
SJ		 6516static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6517 int ua)
6518{
7b16a07c 6519 int ret;
57d104c1 6520
7b16a07c
BA		 6521 if (!vreg)
6522 return 0;
57d104c1 6523
7b16a07c
BA		 6524 ret = regulator_set_load(vreg->reg, ua);
6525 if (ret < 0) {
6526 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6527 __func__, vreg->name, ua, ret);
57d104c1
SJ		 6528 }
6529
6530 return ret;
6531}
6532
6533static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6534 struct ufs_vreg *vreg)
6535{
60f01870
YG		 6536 if (!vreg)
6537 return 0;
6538 else if (vreg->unused)
6539 return 0;
6540 else
6541 return ufshcd_config_vreg_load(hba->dev, vreg,
6542 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 6543}
6544
6545static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6546 struct ufs_vreg *vreg)
6547{
60f01870
YG		 6548 if (!vreg)
6549 return 0;
6550 else if (vreg->unused)
6551 return 0;
6552 else
6553 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 6554}
6555
aa497613
SRT		 6556static int ufshcd_config_vreg(struct device *dev,
6557 struct ufs_vreg *vreg, bool on)
6558{
6559 int ret = 0;
6560 struct regulator *reg = vreg->reg;
6561 const char *name = vreg->name;
6562 int min_uV, uA_load;
6563
6564 BUG_ON(!vreg);
6565
6566 if (regulator_count_voltages(reg) > 0) {
6567 min_uV = on ? vreg->min_uV : 0;
6568 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6569 if (ret) {
6570 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6571 __func__, name, ret);
6572 goto out;
6573 }
6574
6575 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 6576 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6577 if (ret)
aa497613 6578 goto out;
aa497613
SRT		 6579 }
6580out:
6581 return ret;
6582}
6583
6584static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6585{
6586 int ret = 0;
6587
60f01870
YG		 6588 if (!vreg)
6589 goto out;
6590 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 6591 goto out;
6592
6593 ret = ufshcd_config_vreg(dev, vreg, true);
6594 if (!ret)
6595 ret = regulator_enable(vreg->reg);
6596
6597 if (!ret)
6598 vreg->enabled = true;
6599 else
6600 dev_err(dev, "%s: %s enable failed, err=%d\n",
6601 __func__, vreg->name, ret);
6602out:
6603 return ret;
6604}
6605
6606static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
6607{
6608 int ret = 0;
6609
60f01870
YG		 6610 if (!vreg)
6611 goto out;
6612 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 6613 goto out;
6614
6615 ret = regulator_disable(vreg->reg);
6616
6617 if (!ret) {
6618 /* ignore errors on applying disable config */
6619 ufshcd_config_vreg(dev, vreg, false);
6620 vreg->enabled = false;
6621 } else {
6622 dev_err(dev, "%s: %s disable failed, err=%d\n",
6623 __func__, vreg->name, ret);
6624 }
6625out:
6626 return ret;
6627}
6628
6629static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
6630{
6631 int ret = 0;
6632 struct device *dev = hba->dev;
6633 struct ufs_vreg_info *info = &hba->vreg_info;
6634
6635 if (!info)
6636 goto out;
6637
6638 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
6639 if (ret)
6640 goto out;
6641
6642 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
6643 if (ret)
6644 goto out;
6645
6646 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
6647 if (ret)
6648 goto out;
6649
6650out:
6651 if (ret) {
6652 ufshcd_toggle_vreg(dev, info->vccq2, false);
6653 ufshcd_toggle_vreg(dev, info->vccq, false);
6654 ufshcd_toggle_vreg(dev, info->vcc, false);
6655 }
6656 return ret;
6657}
6658
6a771a65
RS		 6659static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
6660{
6661 struct ufs_vreg_info *info = &hba->vreg_info;
6662
6663 if (info)
6664 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6665
6666 return 0;
6667}
6668
aa497613
SRT		 6669static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
6670{
6671 int ret = 0;
6672
6673 if (!vreg)
6674 goto out;
6675
6676 vreg->reg = devm_regulator_get(dev, vreg->name);
6677 if (IS_ERR(vreg->reg)) {
6678 ret = PTR_ERR(vreg->reg);
6679 dev_err(dev, "%s: %s get failed, err=%d\n",
6680 __func__, vreg->name, ret);
6681 }
6682out:
6683 return ret;
6684}
6685
6686static int ufshcd_init_vreg(struct ufs_hba *hba)
6687{
6688 int ret = 0;
6689 struct device *dev = hba->dev;
6690 struct ufs_vreg_info *info = &hba->vreg_info;
6691
6692 if (!info)
6693 goto out;
6694
6695 ret = ufshcd_get_vreg(dev, info->vcc);
6696 if (ret)
6697 goto out;
6698
6699 ret = ufshcd_get_vreg(dev, info->vccq);
6700 if (ret)
6701 goto out;
6702
6703 ret = ufshcd_get_vreg(dev, info->vccq2);
6704out:
6705 return ret;
6706}
6707
6a771a65
RS		 6708static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
6709{
6710 struct ufs_vreg_info *info = &hba->vreg_info;
6711
6712 if (info)
6713 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
6714
6715 return 0;
6716}
6717
60f01870
YG		 6718static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
6719{
6720 int ret = 0;
6721 struct ufs_vreg_info *info = &hba->vreg_info;
6722
6723 if (!info)
6724 goto out;
6725 else if (!info->vccq)
6726 goto out;
6727
6728 if (unused) {
6729 /* shut off the rail here */
6730 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
6731 /*
6732 * Mark this rail as no longer used, so it doesn't get enabled
6733 * later by mistake
6734 */
6735 if (!ret)
6736 info->vccq->unused = true;
6737 } else {
6738 /*
6739 * rail should have been already enabled hence just make sure
6740 * that unused flag is cleared.
6741 */
6742 info->vccq->unused = false;
6743 }
6744out:
6745 return ret;
6746}
6747
57d104c1
SJ		 6748static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
6749 bool skip_ref_clk)
c6e79dac
SRT		 6750{
6751 int ret = 0;
6752 struct ufs_clk_info *clki;
6753 struct list_head *head = &hba->clk_list_head;
1ab27c9c 6754 unsigned long flags;
911a0771
SJ		 6755 ktime_t start = ktime_get();
6756 bool clk_state_changed = false;
c6e79dac 6757
566ec9ad 6758 if (list_empty(head))
c6e79dac
SRT		 6759 goto out;
6760
1e879e8f
SJ		 6761 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
6762 if (ret)
6763 return ret;
6764
c6e79dac
SRT		 6765 list_for_each_entry(clki, head, list) {
6766 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 6767 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
6768 continue;
6769
911a0771 6770 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 6771 if (on && !clki->enabled) {
6772 ret = clk_prepare_enable(clki->clk);
6773 if (ret) {
6774 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
6775 __func__, clki->name, ret);
6776 goto out;
6777 }
6778 } else if (!on && clki->enabled) {
6779 clk_disable_unprepare(clki->clk);
6780 }
6781 clki->enabled = on;
6782 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
6783 clki->name, on ? "en" : "dis");
6784 }
6785 }
1ab27c9c 6786
1e879e8f
SJ		 6787 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
6788 if (ret)
6789 return ret;
6790
c6e79dac
SRT		 6791out:
6792 if (ret) {
6793 list_for_each_entry(clki, head, list) {
6794 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
6795 clk_disable_unprepare(clki->clk);
6796 }
7ff5ab47 6797 } else if (!ret && on) {
1ab27c9c
ST		 6798 spin_lock_irqsave(hba->host->host_lock, flags);
6799 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 6800 trace_ufshcd_clk_gating(dev_name(hba->dev),
6801 hba->clk_gating.state);
1ab27c9c 6802 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 6803 }
7ff5ab47 6804
911a0771
SJ		 6805 if (clk_state_changed)
6806 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
6807 (on ? "on" : "off"),
6808 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 6809 return ret;
6810}
6811
57d104c1
SJ		 6812static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
6813{
6814 return __ufshcd_setup_clocks(hba, on, false);
6815}
6816
c6e79dac
SRT		 6817static int ufshcd_init_clocks(struct ufs_hba *hba)
6818{
6819 int ret = 0;
6820 struct ufs_clk_info *clki;
6821 struct device *dev = hba->dev;
6822 struct list_head *head = &hba->clk_list_head;
6823
566ec9ad 6824 if (list_empty(head))
c6e79dac
SRT		 6825 goto out;
6826
6827 list_for_each_entry(clki, head, list) {
6828 if (!clki->name)
6829 continue;
6830
6831 clki->clk = devm_clk_get(dev, clki->name);
6832 if (IS_ERR(clki->clk)) {
6833 ret = PTR_ERR(clki->clk);
6834 dev_err(dev, "%s: %s clk get failed, %d\n",
6835 __func__, clki->name, ret);
6836 goto out;
6837 }
6838
6839 if (clki->max_freq) {
6840 ret = clk_set_rate(clki->clk, clki->max_freq);
6841 if (ret) {
6842 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6843 __func__, clki->name,
6844 clki->max_freq, ret);
6845 goto out;
6846 }
856b3483 6847 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 6848 }
6849 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
6850 clki->name, clk_get_rate(clki->clk));
6851 }
6852out:
6853 return ret;
6854}
6855
5c0c28a8
SRT		 6856static int ufshcd_variant_hba_init(struct ufs_hba *hba)
6857{
6858 int err = 0;
6859
6860 if (!hba->vops)
6861 goto out;
6862
0263bcd0
YG		 6863 err = ufshcd_vops_init(hba);
6864 if (err)
6865 goto out;
5c0c28a8 6866
0263bcd0
YG		 6867 err = ufshcd_vops_setup_regulators(hba, true);
6868 if (err)
6869 goto out_exit;
5c0c28a8
SRT		 6870
6871 goto out;
6872
5c0c28a8 6873out_exit:
0263bcd0 6874 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 6875out:
6876 if (err)
6877 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 6878 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 6879 return err;
6880}
6881
6882static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
6883{
6884 if (!hba->vops)
6885 return;
6886
0263bcd0 6887 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 6888
0263bcd0 6889 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 6890}
6891
aa497613
SRT		 6892static int ufshcd_hba_init(struct ufs_hba *hba)
6893{
6894 int err;
6895
6a771a65
RS		 6896 /*
6897 * Handle host controller power separately from the UFS device power
6898 * rails as it will help controlling the UFS host controller power
6899 * collapse easily which is different than UFS device power collapse.
6900 * Also, enable the host controller power before we go ahead with rest
6901 * of the initialization here.
6902 */
6903 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 6904 if (err)
6905 goto out;
6906
6a771a65 6907 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 6908 if (err)
6909 goto out;
6910
6a771a65
RS		 6911 err = ufshcd_init_clocks(hba);
6912 if (err)
6913 goto out_disable_hba_vreg;
6914
6915 err = ufshcd_setup_clocks(hba, true);
6916 if (err)
6917 goto out_disable_hba_vreg;
6918
c6e79dac
SRT		 6919 err = ufshcd_init_vreg(hba);
6920 if (err)
6921 goto out_disable_clks;
6922
6923 err = ufshcd_setup_vreg(hba, true);
6924 if (err)
6925 goto out_disable_clks;
6926
aa497613
SRT		 6927 err = ufshcd_variant_hba_init(hba);
6928 if (err)
6929 goto out_disable_vreg;
6930
1d337ec2 6931 hba->is_powered = true;
aa497613
SRT		 6932 goto out;
6933
6934out_disable_vreg:
6935 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 6936out_disable_clks:
6937 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 6938out_disable_hba_vreg:
6939 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 6940out:
6941 return err;
6942}
6943
6944static void ufshcd_hba_exit(struct ufs_hba *hba)
6945{
1d337ec2
SRT		 6946 if (hba->is_powered) {
6947 ufshcd_variant_hba_exit(hba);
6948 ufshcd_setup_vreg(hba, false);
a508253d 6949 ufshcd_suspend_clkscaling(hba);
401f1e44 6950 if (ufshcd_is_clkscaling_supported(hba)) {
0701e49d
SJ		 6951 if (hba->devfreq)
6952 ufshcd_suspend_clkscaling(hba);
401f1e44
SJ		 6953 destroy_workqueue(hba->clk_scaling.workq);
6954 }
1d337ec2
SRT		 6955 ufshcd_setup_clocks(hba, false);
6956 ufshcd_setup_hba_vreg(hba, false);
6957 hba->is_powered = false;
6958 }
aa497613
SRT		 6959}
6960
57d104c1
SJ		 6961static int
6962ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
6963{
6964 unsigned char cmd[6] = {REQUEST_SENSE,
6965 0,
6966 0,
6967 0,
dcea0bfb 6968 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 6969 0};
6970 char *buffer;
6971 int ret;
6972
dcea0bfb 6973 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 6974 if (!buffer) {
6975 ret = -ENOMEM;
6976 goto out;
6977 }
6978
fcbfffe2
CH		 6979 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
6980 UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
6981 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 6982 if (ret)
6983 pr_err("%s: failed with err %d\n", __func__, ret);
6984
6985 kfree(buffer);
6986out:
6987 return ret;
6988}
6989
6990/**
6991 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
6992 * power mode
6993 * @hba: per adapter instance
6994 * @pwr_mode: device power mode to set
6995 *
6996 * Returns 0 if requested power mode is set successfully
6997 * Returns non-zero if failed to set the requested power mode
6998 */
6999static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7000 enum ufs_dev_pwr_mode pwr_mode)
7001{
7002 unsigned char cmd[6] = { START_STOP };
7003 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7004 struct scsi_device *sdp;
7005 unsigned long flags;
57d104c1
SJ		 7006 int ret;
7007
7c48bfd0
AM		 7008 spin_lock_irqsave(hba->host->host_lock, flags);
7009 sdp = hba->sdev_ufs_device;
7010 if (sdp) {
7011 ret = scsi_device_get(sdp);
7012 if (!ret && !scsi_device_online(sdp)) {
7013 ret = -ENODEV;
7014 scsi_device_put(sdp);
7015 }
7016 } else {
7017 ret = -ENODEV;
7018 }
7019 spin_unlock_irqrestore(hba->host->host_lock, flags);
7020
7021 if (ret)
7022 return ret;
57d104c1
SJ		 7023
7024 /*
7025 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7026 * handling, which would wait for host to be resumed. Since we know
7027 * we are functional while we are here, skip host resume in error
7028 * handling context.
7029 */
7030 hba->host->eh_noresume = 1;
7031 if (hba->wlun_dev_clr_ua) {
7032 ret = ufshcd_send_request_sense(hba, sdp);
7033 if (ret)
7034 goto out;
7035 /* Unit attention condition is cleared now */
7036 hba->wlun_dev_clr_ua = false;
7037 }
7038
7039 cmd[4] = pwr_mode << 4;
7040
7041 /*
7042 * Current function would be generally called from the power management
e8064021 7043 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7044 * already suspended childs.
7045 */
fcbfffe2
CH		 7046 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7047 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7048 if (ret) {
7049 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7050 "START_STOP failed for power mode: %d, result %x\n",
7051 pwr_mode, ret);
21045519
HR		 7052 if (driver_byte(ret) & DRIVER_SENSE)
7053 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7054 }
7055
7056 if (!ret)
7057 hba->curr_dev_pwr_mode = pwr_mode;
7058out:
7c48bfd0 7059 scsi_device_put(sdp);
57d104c1
SJ		 7060 hba->host->eh_noresume = 0;
7061 return ret;
7062}
7063
7064static int ufshcd_link_state_transition(struct ufs_hba *hba,
7065 enum uic_link_state req_link_state,
7066 int check_for_bkops)
7067{
7068 int ret = 0;
7069
7070 if (req_link_state == hba->uic_link_state)
7071 return 0;
7072
7073 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7074 ret = ufshcd_uic_hibern8_enter(hba);
7075 if (!ret)
7076 ufshcd_set_link_hibern8(hba);
7077 else
7078 goto out;
7079 }
7080 /*
7081 * If autobkops is enabled, link can't be turned off because
7082 * turning off the link would also turn off the device.
7083 */
7084 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7085 (!check_for_bkops || (check_for_bkops &&
7086 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 7087 /*
7088 * Let's make sure that link is in low power mode, we are doing
7089 * this currently by putting the link in Hibern8. Otherway to
7090 * put the link in low power mode is to send the DME end point
7091 * to device and then send the DME reset command to local
7092 * unipro. But putting the link in hibern8 is much faster.
7093 */
7094 ret = ufshcd_uic_hibern8_enter(hba);
7095 if (ret)
7096 goto out;
57d104c1
SJ		 7097 /*
7098 * Change controller state to "reset state" which
7099 * should also put the link in off/reset state
7100 */
596585a2 7101 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 7102 /*
7103 * TODO: Check if we need any delay to make sure that
7104 * controller is reset
7105 */
7106 ufshcd_set_link_off(hba);
7107 }
7108
7109out:
7110 return ret;
7111}
7112
7113static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7114{
b799fdf7
YG		 7115 /*
7116 * It seems some UFS devices may keep drawing more than sleep current
7117 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7118 * To avoid this situation, add 2ms delay before putting these UFS
7119 * rails in LPM mode.
7120 */
7121 if (!ufshcd_is_link_active(hba) &&
7122 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7123 usleep_range(2000, 2100);
7124
57d104c1
SJ		 7125 /*
7126 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7127 * power.
7128 *
7129 * If UFS device and link is in OFF state, all power supplies (VCC,
7130 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7131 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7132 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7133 *
7134 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7135 * in low power state which would save some power.
7136 */
7137 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7138 !hba->dev_info.is_lu_power_on_wp) {
7139 ufshcd_setup_vreg(hba, false);
7140 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7141 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7142 if (!ufshcd_is_link_active(hba)) {
7143 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7144 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7145 }
7146 }
7147}
7148
7149static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7150{
7151 int ret = 0;
7152
7153 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7154 !hba->dev_info.is_lu_power_on_wp) {
7155 ret = ufshcd_setup_vreg(hba, true);
7156 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7157 if (!ret && !ufshcd_is_link_active(hba)) {
7158 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7159 if (ret)
7160 goto vcc_disable;
7161 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7162 if (ret)
7163 goto vccq_lpm;
7164 }
69d72ac8 7165 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7166 }
7167 goto out;
7168
7169vccq_lpm:
7170 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7171vcc_disable:
7172 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7173out:
7174 return ret;
7175}
7176
7177static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7178{
7179 if (ufshcd_is_link_off(hba))
7180 ufshcd_setup_hba_vreg(hba, false);
7181}
7182
7183static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7184{
7185 if (ufshcd_is_link_off(hba))
7186 ufshcd_setup_hba_vreg(hba, true);
7187}
7188
7a3e97b0 7189/**
57d104c1 7190 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7191 * @hba: per adapter instance
57d104c1
SJ		 7192 * @pm_op: desired low power operation type
7193 *
7194 * This function will try to put the UFS device and link into low power
7195 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7196 * (System PM level).
7197 *
7198 * If this function is called during shutdown, it will make sure that
7199 * both UFS device and UFS link is powered off.
7a3e97b0 7200 *
57d104c1
SJ		 7201 * NOTE: UFS device & link must be active before we enter in this function.
7202 *
7203 * Returns 0 for success and non-zero for failure
7a3e97b0 7204 */
57d104c1 7205static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7206{
57d104c1
SJ		 7207 int ret = 0;
7208 enum ufs_pm_level pm_lvl;
7209 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7210 enum uic_link_state req_link_state;
7211
7212 hba->pm_op_in_progress = 1;
7213 if (!ufshcd_is_shutdown_pm(pm_op)) {
7214 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7215 hba->rpm_lvl : hba->spm_lvl;
7216 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7217 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7218 } else {
7219 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7220 req_link_state = UIC_LINK_OFF_STATE;
7221 }
7222
7a3e97b0 7223 /*
57d104c1
SJ		 7224 * If we can't transition into any of the low power modes
7225 * just gate the clocks.
7a3e97b0 7226 */
1ab27c9c
ST		 7227 ufshcd_hold(hba, false);
7228 hba->clk_gating.is_suspended = true;
7229
401f1e44
SJ		 7230 if (hba->clk_scaling.is_allowed) {
7231 cancel_work_sync(&hba->clk_scaling.suspend_work);
7232 cancel_work_sync(&hba->clk_scaling.resume_work);
7233 ufshcd_suspend_clkscaling(hba);
7234 }
d6fcf81a 7235
57d104c1
SJ		 7236 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7237 req_link_state == UIC_LINK_ACTIVE_STATE) {
7238 goto disable_clks;
7239 }
7a3e97b0 7240
57d104c1
SJ		 7241 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7242 (req_link_state == hba->uic_link_state))
d6fcf81a 7243 goto enable_gating;
57d104c1
SJ		 7244
7245 /* UFS device & link must be active before we enter in this function */
7246 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7247 ret = -EINVAL;
d6fcf81a 7248 goto enable_gating;
57d104c1
SJ		 7249 }
7250
7251 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7252 if (ufshcd_can_autobkops_during_suspend(hba)) {
7253 /*
7254 * The device is idle with no requests in the queue,
7255 * allow background operations if bkops status shows
7256 * that performance might be impacted.
7257 */
7258 ret = ufshcd_urgent_bkops(hba);
7259 if (ret)
7260 goto enable_gating;
7261 } else {
7262 /* make sure that auto bkops is disabled */
7263 ufshcd_disable_auto_bkops(hba);
7264 }
57d104c1
SJ		 7265 }
7266
7267 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7268 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7269 !ufshcd_is_runtime_pm(pm_op))) {
7270 /* ensure that bkops is disabled */
7271 ufshcd_disable_auto_bkops(hba);
7272 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7273 if (ret)
1ab27c9c 7274 goto enable_gating;
57d104c1
SJ		 7275 }
7276
7277 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7278 if (ret)
7279 goto set_dev_active;
7280
7281 ufshcd_vreg_set_lpm(hba);
7282
7283disable_clks:
7284 /*
7285 * Call vendor specific suspend callback. As these callbacks may access
7286 * vendor specific host controller register space call them before the
7287 * host clocks are ON.
7288 */
0263bcd0
YG		 7289 ret = ufshcd_vops_suspend(hba, pm_op);
7290 if (ret)
7291 goto set_link_active;
57d104c1 7292
57d104c1
SJ		 7293 if (!ufshcd_is_link_active(hba))
7294 ufshcd_setup_clocks(hba, false);
7295 else
7296 /* If link is active, device ref_clk can't be switched off */
7297 __ufshcd_setup_clocks(hba, false, true);
7298
1ab27c9c 7299 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7300 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1
SJ		 7301 /*
7302 * Disable the host irq as host controller as there won't be any
0263bcd0 7303 * host controller transaction expected till resume.
57d104c1
SJ		 7304 */
7305 ufshcd_disable_irq(hba);
7306 /* Put the host controller in low power mode if possible */
7307 ufshcd_hba_vreg_set_lpm(hba);
7308 goto out;
7309
57d104c1 7310set_link_active:
401f1e44
SJ		 7311 if (hba->clk_scaling.is_allowed)
7312 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 7313 ufshcd_vreg_set_hpm(hba);
7314 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7315 ufshcd_set_link_active(hba);
7316 else if (ufshcd_is_link_off(hba))
7317 ufshcd_host_reset_and_restore(hba);
7318set_dev_active:
7319 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7320 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7321enable_gating:
401f1e44
SJ		 7322 if (hba->clk_scaling.is_allowed)
7323 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7324 hba->clk_gating.is_suspended = false;
7325 ufshcd_release(hba);
57d104c1
SJ		 7326out:
7327 hba->pm_op_in_progress = 0;
7328 return ret;
7a3e97b0
SY		 7329}
7330
7331/**
57d104c1 7332 * ufshcd_resume - helper function for resume operations
3b1d0580 7333 * @hba: per adapter instance
57d104c1 7334 * @pm_op: runtime PM or system PM
7a3e97b0 7335 *
57d104c1
SJ		 7336 * This function basically brings the UFS device, UniPro link and controller
7337 * to active state.
7338 *
7339 * Returns 0 for success and non-zero for failure
7a3e97b0 7340 */
57d104c1 7341static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7342{
57d104c1
SJ		 7343 int ret;
7344 enum uic_link_state old_link_state;
7345
7346 hba->pm_op_in_progress = 1;
7347 old_link_state = hba->uic_link_state;
7348
7349 ufshcd_hba_vreg_set_hpm(hba);
7350 /* Make sure clocks are enabled before accessing controller */
7351 ret = ufshcd_setup_clocks(hba, true);
7352 if (ret)
7353 goto out;
7354
57d104c1
SJ		 7355 /* enable the host irq as host controller would be active soon */
7356 ret = ufshcd_enable_irq(hba);
7357 if (ret)
7358 goto disable_irq_and_vops_clks;
7359
7360 ret = ufshcd_vreg_set_hpm(hba);
7361 if (ret)
7362 goto disable_irq_and_vops_clks;
7363
7a3e97b0 7364 /*
57d104c1
SJ		 7365 * Call vendor specific resume callback. As these callbacks may access
7366 * vendor specific host controller register space call them when the
7367 * host clocks are ON.
7a3e97b0 7368 */
0263bcd0
YG		 7369 ret = ufshcd_vops_resume(hba, pm_op);
7370 if (ret)
7371 goto disable_vreg;
57d104c1
SJ		 7372
7373 if (ufshcd_is_link_hibern8(hba)) {
7374 ret = ufshcd_uic_hibern8_exit(hba);
7375 if (!ret)
7376 ufshcd_set_link_active(hba);
7377 else
7378 goto vendor_suspend;
7379 } else if (ufshcd_is_link_off(hba)) {
7380 ret = ufshcd_host_reset_and_restore(hba);
7381 /*
7382 * ufshcd_host_reset_and_restore() should have already
7383 * set the link state as active
7384 */
7385 if (ret || !ufshcd_is_link_active(hba))
7386 goto vendor_suspend;
7387 }
7388
7389 if (!ufshcd_is_ufs_dev_active(hba)) {
7390 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7391 if (ret)
7392 goto set_old_link_state;
7393 }
7394
4e768e76
SJ		 7395 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7396 ufshcd_enable_auto_bkops(hba);
7397 else
7398 /*
7399 * If BKOPs operations are urgently needed at this moment then
7400 * keep auto-bkops enabled or else disable it.
7401 */
7402 ufshcd_urgent_bkops(hba);
7403
1ab27c9c
ST		 7404 hba->clk_gating.is_suspended = false;
7405
fcb0c4b0
ST		 7406 if (hba->clk_scaling.is_allowed)
7407 ufshcd_resume_clkscaling(hba);
856b3483 7408
1ab27c9c
ST		 7409 /* Schedule clock gating in case of no access to UFS device yet */
7410 ufshcd_release(hba);
57d104c1
SJ		 7411 goto out;
7412
7413set_old_link_state:
7414 ufshcd_link_state_transition(hba, old_link_state, 0);
7415vendor_suspend:
0263bcd0 7416 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 7417disable_vreg:
7418 ufshcd_vreg_set_lpm(hba);
7419disable_irq_and_vops_clks:
7420 ufshcd_disable_irq(hba);
401f1e44
SJ		 7421 if (hba->clk_scaling.is_allowed)
7422 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 7423 ufshcd_setup_clocks(hba, false);
7424out:
7425 hba->pm_op_in_progress = 0;
7426 return ret;
7427}
7428
7429/**
7430 * ufshcd_system_suspend - system suspend routine
7431 * @hba: per adapter instance
7432 * @pm_op: runtime PM or system PM
7433 *
7434 * Check the description of ufshcd_suspend() function for more details.
7435 *
7436 * Returns 0 for success and non-zero for failure
7437 */
7438int ufshcd_system_suspend(struct ufs_hba *hba)
7439{
7440 int ret = 0;
7ff5ab47 7441 ktime_t start = ktime_get();
57d104c1
SJ		 7442
7443 if (!hba || !hba->is_powered)
233b594b 7444 return 0;
57d104c1 7445
0b257734
SJ		 7446 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7447 hba->curr_dev_pwr_mode) &&
7448 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7449 hba->uic_link_state))
7450 goto out;
57d104c1 7451
0b257734 7452 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 7453 /*
7454 * UFS device and/or UFS link low power states during runtime
7455 * suspend seems to be different than what is expected during
7456 * system suspend. Hence runtime resume the devic & link and
7457 * let the system suspend low power states to take effect.
7458 * TODO: If resume takes longer time, we might have optimize
7459 * it in future by not resuming everything if possible.
7460 */
7461 ret = ufshcd_runtime_resume(hba);
7462 if (ret)
7463 goto out;
7464 }
7465
7466 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7467out:
7ff5ab47
SJ		 7468 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7469 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7470 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 7471 if (!ret)
7472 hba->is_sys_suspended = true;
57d104c1
SJ		 7473 return ret;
7474}
7475EXPORT_SYMBOL(ufshcd_system_suspend);
7476
7477/**
7478 * ufshcd_system_resume - system resume routine
7479 * @hba: per adapter instance
7480 *
7481 * Returns 0 for success and non-zero for failure
7482 */
7a3e97b0 7483
57d104c1
SJ		 7484int ufshcd_system_resume(struct ufs_hba *hba)
7485{
7ff5ab47
SJ		 7486 int ret = 0;
7487 ktime_t start = ktime_get();
7488
e3ce73d6
YG		 7489 if (!hba)
7490 return -EINVAL;
7491
7492 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 7493 /*
7494 * Let the runtime resume take care of resuming
7495 * if runtime suspended.
7496 */
7ff5ab47
SJ		 7497 goto out;
7498 else
7499 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7500out:
7501 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7502 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7503 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7504 return ret;
7a3e97b0 7505}
57d104c1 7506EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 7507
57d104c1
SJ		 7508/**
7509 * ufshcd_runtime_suspend - runtime suspend routine
7510 * @hba: per adapter instance
7511 *
7512 * Check the description of ufshcd_suspend() function for more details.
7513 *
7514 * Returns 0 for success and non-zero for failure
7515 */
66ec6d59
SRT		 7516int ufshcd_runtime_suspend(struct ufs_hba *hba)
7517{
7ff5ab47
SJ		 7518 int ret = 0;
7519 ktime_t start = ktime_get();
7520
e3ce73d6
YG		 7521 if (!hba)
7522 return -EINVAL;
7523
7524 if (!hba->is_powered)
7ff5ab47
SJ		 7525 goto out;
7526 else
7527 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7528out:
7529 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7530 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7531 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7532 return ret;
66ec6d59
SRT		 7533}
7534EXPORT_SYMBOL(ufshcd_runtime_suspend);
7535
57d104c1
SJ		 7536/**
7537 * ufshcd_runtime_resume - runtime resume routine
7538 * @hba: per adapter instance
7539 *
7540 * This function basically brings the UFS device, UniPro link and controller
7541 * to active state. Following operations are done in this function:
7542 *
7543 * 1. Turn on all the controller related clocks
7544 * 2. Bring the UniPro link out of Hibernate state
7545 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7546 * to active state.
7547 * 4. If auto-bkops is enabled on the device, disable it.
7548 *
7549 * So following would be the possible power state after this function return
7550 * successfully:
7551 * S1: UFS device in Active state with VCC rail ON
7552 * UniPro link in Active state
7553 * All the UFS/UniPro controller clocks are ON
7554 *
7555 * Returns 0 for success and non-zero for failure
7556 */
66ec6d59
SRT		 7557int ufshcd_runtime_resume(struct ufs_hba *hba)
7558{
7ff5ab47
SJ		 7559 int ret = 0;
7560 ktime_t start = ktime_get();
7561
e3ce73d6
YG		 7562 if (!hba)
7563 return -EINVAL;
7564
7565 if (!hba->is_powered)
7ff5ab47
SJ		 7566 goto out;
7567 else
7568 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7569out:
7570 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7571 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7572 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7573 return ret;
66ec6d59
SRT		 7574}
7575EXPORT_SYMBOL(ufshcd_runtime_resume);
7576
7577int ufshcd_runtime_idle(struct ufs_hba *hba)
7578{
7579 return 0;
7580}
7581EXPORT_SYMBOL(ufshcd_runtime_idle);
7582
09690d5a
SJ		 7583static inline ssize_t ufshcd_pm_lvl_store(struct device *dev,
7584 struct device_attribute *attr,
7585 const char *buf, size_t count,
7586 bool rpm)
7587{
7588 struct ufs_hba *hba = dev_get_drvdata(dev);
7589 unsigned long flags, value;
7590
7591 if (kstrtoul(buf, 0, &value))
7592 return -EINVAL;
7593
949d7fa1 7594 if (value >= UFS_PM_LVL_MAX)
09690d5a
SJ		 7595 return -EINVAL;
7596
7597 spin_lock_irqsave(hba->host->host_lock, flags);
7598 if (rpm)
7599 hba->rpm_lvl = value;
7600 else
7601 hba->spm_lvl = value;
7602 spin_unlock_irqrestore(hba->host->host_lock, flags);
7603 return count;
7604}
7605
7606static ssize_t ufshcd_rpm_lvl_show(struct device *dev,
7607 struct device_attribute *attr, char *buf)
7608{
7609 struct ufs_hba *hba = dev_get_drvdata(dev);
7610 int curr_len;
7611 u8 lvl;
7612
7613 curr_len = snprintf(buf, PAGE_SIZE,
7614 "\nCurrent Runtime PM level [%d] => dev_state [%s] link_state [%s]\n",
7615 hba->rpm_lvl,
7616 ufschd_ufs_dev_pwr_mode_to_string(
7617 ufs_pm_lvl_states[hba->rpm_lvl].dev_state),
7618 ufschd_uic_link_state_to_string(
7619 ufs_pm_lvl_states[hba->rpm_lvl].link_state));
7620
7621 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7622 "\nAll available Runtime PM levels info:\n");
7623 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7624 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7625 "\tRuntime PM level [%d] => dev_state [%s] link_state [%s]\n",
7626 lvl,
7627 ufschd_ufs_dev_pwr_mode_to_string(
7628 ufs_pm_lvl_states[lvl].dev_state),
7629 ufschd_uic_link_state_to_string(
7630 ufs_pm_lvl_states[lvl].link_state));
7631
7632 return curr_len;
7633}
7634
7635static ssize_t ufshcd_rpm_lvl_store(struct device *dev,
7636 struct device_attribute *attr, const char *buf, size_t count)
7637{
7638 return ufshcd_pm_lvl_store(dev, attr, buf, count, true);
7639}
7640
7641static void ufshcd_add_rpm_lvl_sysfs_nodes(struct ufs_hba *hba)
7642{
7643 hba->rpm_lvl_attr.show = ufshcd_rpm_lvl_show;
7644 hba->rpm_lvl_attr.store = ufshcd_rpm_lvl_store;
7645 sysfs_attr_init(&hba->rpm_lvl_attr.attr);
7646 hba->rpm_lvl_attr.attr.name = "rpm_lvl";
7647 hba->rpm_lvl_attr.attr.mode = 0644;
7648 if (device_create_file(hba->dev, &hba->rpm_lvl_attr))
7649 dev_err(hba->dev, "Failed to create sysfs for rpm_lvl\n");
7650}
7651
7652static ssize_t ufshcd_spm_lvl_show(struct device *dev,
7653 struct device_attribute *attr, char *buf)
7654{
7655 struct ufs_hba *hba = dev_get_drvdata(dev);
7656 int curr_len;
7657 u8 lvl;
7658
7659 curr_len = snprintf(buf, PAGE_SIZE,
7660 "\nCurrent System PM level [%d] => dev_state [%s] link_state [%s]\n",
7661 hba->spm_lvl,
7662 ufschd_ufs_dev_pwr_mode_to_string(
7663 ufs_pm_lvl_states[hba->spm_lvl].dev_state),
7664 ufschd_uic_link_state_to_string(
7665 ufs_pm_lvl_states[hba->spm_lvl].link_state));
7666
7667 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7668 "\nAll available System PM levels info:\n");
7669 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7670 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7671 "\tSystem PM level [%d] => dev_state [%s] link_state [%s]\n",
7672 lvl,
7673 ufschd_ufs_dev_pwr_mode_to_string(
7674 ufs_pm_lvl_states[lvl].dev_state),
7675 ufschd_uic_link_state_to_string(
7676 ufs_pm_lvl_states[lvl].link_state));
7677
7678 return curr_len;
7679}
7680
7681static ssize_t ufshcd_spm_lvl_store(struct device *dev,
7682 struct device_attribute *attr, const char *buf, size_t count)
7683{
7684 return ufshcd_pm_lvl_store(dev, attr, buf, count, false);
7685}
7686
7687static void ufshcd_add_spm_lvl_sysfs_nodes(struct ufs_hba *hba)
7688{
7689 hba->spm_lvl_attr.show = ufshcd_spm_lvl_show;
7690 hba->spm_lvl_attr.store = ufshcd_spm_lvl_store;
7691 sysfs_attr_init(&hba->spm_lvl_attr.attr);
7692 hba->spm_lvl_attr.attr.name = "spm_lvl";
7693 hba->spm_lvl_attr.attr.mode = 0644;
7694 if (device_create_file(hba->dev, &hba->spm_lvl_attr))
7695 dev_err(hba->dev, "Failed to create sysfs for spm_lvl\n");
7696}
7697
7698static inline void ufshcd_add_sysfs_nodes(struct ufs_hba *hba)
7699{
7700 ufshcd_add_rpm_lvl_sysfs_nodes(hba);
7701 ufshcd_add_spm_lvl_sysfs_nodes(hba);
7702}
7703
463f620b
MP		 7704static inline void ufshcd_remove_sysfs_nodes(struct ufs_hba *hba)
7705{
7706 device_remove_file(hba->dev, &hba->rpm_lvl_attr);
7707 device_remove_file(hba->dev, &hba->spm_lvl_attr);
7708}
7709
57d104c1
SJ		 7710/**
7711 * ufshcd_shutdown - shutdown routine
7712 * @hba: per adapter instance
7713 *
7714 * This function would power off both UFS device and UFS link.
7715 *
7716 * Returns 0 always to allow force shutdown even in case of errors.
7717 */
7718int ufshcd_shutdown(struct ufs_hba *hba)
7719{
7720 int ret = 0;
7721
7722 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
7723 goto out;
7724
7725 if (pm_runtime_suspended(hba->dev)) {
7726 ret = ufshcd_runtime_resume(hba);
7727 if (ret)
7728 goto out;
7729 }
7730
7731 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
7732out:
7733 if (ret)
7734 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
7735 /* allow force shutdown even in case of errors */
7736 return 0;
7737}
7738EXPORT_SYMBOL(ufshcd_shutdown);
7739
7a3e97b0 7740/**
3b1d0580 7741 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 7742 * data structure memory
3b1d0580 7743 * @hba - per adapter instance
7a3e97b0 7744 */
3b1d0580 7745void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 7746{
463f620b 7747 ufshcd_remove_sysfs_nodes(hba);
cfdf9c91 7748 scsi_remove_host(hba->host);
7a3e97b0 7749 /* disable interrupts */
2fbd009b 7750 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 7751 ufshcd_hba_stop(hba, true);
7a3e97b0 7752
1ab27c9c 7753 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 7754 if (ufshcd_is_clkscaling_supported(hba))
7755 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 7756 ufshcd_hba_exit(hba);
3b1d0580
VH		 7757}
7758EXPORT_SYMBOL_GPL(ufshcd_remove);
7759
47555a5c
YG		 7760/**
7761 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
7762 * @hba: pointer to Host Bus Adapter (HBA)
7763 */
7764void ufshcd_dealloc_host(struct ufs_hba *hba)
7765{
7766 scsi_host_put(hba->host);
7767}
7768EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
7769
ca3d7bf9
AM		 7770/**
7771 * ufshcd_set_dma_mask - Set dma mask based on the controller
7772 * addressing capability
7773 * @hba: per adapter instance
7774 *
7775 * Returns 0 for success, non-zero for failure
7776 */
7777static int ufshcd_set_dma_mask(struct ufs_hba *hba)
7778{
7779 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
7780 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
7781 return 0;
7782 }
7783 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
7784}
7785
7a3e97b0 7786/**
5c0c28a8 7787 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 7788 * @dev: pointer to device handle
7789 * @hba_handle: driver private handle
7a3e97b0
SY		 7790 * Returns 0 on success, non-zero value on failure
7791 */
5c0c28a8 7792int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 7793{
7794 struct Scsi_Host *host;
7795 struct ufs_hba *hba;
5c0c28a8 7796 int err = 0;
7a3e97b0 7797
3b1d0580
VH		 7798 if (!dev) {
7799 dev_err(dev,
7800 "Invalid memory reference for dev is NULL\n");
7801 err = -ENODEV;
7a3e97b0
SY		 7802 goto out_error;
7803 }
7804
7a3e97b0
SY		 7805 host = scsi_host_alloc(&ufshcd_driver_template,
7806 sizeof(struct ufs_hba));
7807 if (!host) {
3b1d0580 7808 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 7809 err = -ENOMEM;
3b1d0580 7810 goto out_error;
7a3e97b0
SY		 7811 }
7812 hba = shost_priv(host);
7a3e97b0 7813 hba->host = host;
3b1d0580 7814 hba->dev = dev;
5c0c28a8
SRT		 7815 *hba_handle = hba;
7816
566ec9ad
SM		 7817 INIT_LIST_HEAD(&hba->clk_list_head);
7818
5c0c28a8
SRT		 7819out_error:
7820 return err;
7821}
7822EXPORT_SYMBOL(ufshcd_alloc_host);
7823
7824/**
7825 * ufshcd_init - Driver initialization routine
7826 * @hba: per-adapter instance
7827 * @mmio_base: base register address
7828 * @irq: Interrupt line of device
7829 * Returns 0 on success, non-zero value on failure
7830 */
7831int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
7832{
7833 int err;
7834 struct Scsi_Host *host = hba->host;
7835 struct device *dev = hba->dev;
7836
7837 if (!mmio_base) {
7838 dev_err(hba->dev,
7839 "Invalid memory reference for mmio_base is NULL\n");
7840 err = -ENODEV;
7841 goto out_error;
7842 }
7843
3b1d0580
VH		 7844 hba->mmio_base = mmio_base;
7845 hba->irq = irq;
7a3e97b0 7846
a4b0e8a4
PM		 7847 /* Set descriptor lengths to specification defaults */
7848 ufshcd_def_desc_sizes(hba);
7849
aa497613 7850 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 7851 if (err)
7852 goto out_error;
7853
7a3e97b0
SY		 7854 /* Read capabilities registers */
7855 ufshcd_hba_capabilities(hba);
7856
7857 /* Get UFS version supported by the controller */
7858 hba->ufs_version = ufshcd_get_ufs_version(hba);
7859
c01848c6
YG		 7860 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
7861 (hba->ufs_version != UFSHCI_VERSION_11) &&
7862 (hba->ufs_version != UFSHCI_VERSION_20) &&
7863 (hba->ufs_version != UFSHCI_VERSION_21))
7864 dev_err(hba->dev, "invalid UFS version 0x%x\n",
7865 hba->ufs_version);
7866
2fbd009b
SJ		 7867 /* Get Interrupt bit mask per version */
7868 hba->intr_mask = ufshcd_get_intr_mask(hba);
7869
ca3d7bf9
AM		 7870 err = ufshcd_set_dma_mask(hba);
7871 if (err) {
7872 dev_err(hba->dev, "set dma mask failed\n");
7873 goto out_disable;
7874 }
7875
7a3e97b0
SY		 7876 /* Allocate memory for host memory space */
7877 err = ufshcd_memory_alloc(hba);
7878 if (err) {
3b1d0580
VH		 7879 dev_err(hba->dev, "Memory allocation failed\n");
7880 goto out_disable;
7a3e97b0
SY		 7881 }
7882
7883 /* Configure LRB */
7884 ufshcd_host_memory_configure(hba);
7885
7886 host->can_queue = hba->nutrs;
7887 host->cmd_per_lun = hba->nutrs;
7888 host->max_id = UFSHCD_MAX_ID;
0ce147d4 7889 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 7890 host->max_channel = UFSHCD_MAX_CHANNEL;
7891 host->unique_id = host->host_no;
7892 host->max_cmd_len = MAX_CDB_SIZE;
7893
7eb584db
DR		 7894 hba->max_pwr_info.is_valid = false;
7895
7a3e97b0 7896 /* Initailize wait queue for task management */
e2933132
SRT		 7897 init_waitqueue_head(&hba->tm_wq);
7898 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 7899
7900 /* Initialize work queues */
e8e7f271 7901 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 7902 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 7903
6ccf44fe
SJ		 7904 /* Initialize UIC command mutex */
7905 mutex_init(&hba->uic_cmd_mutex);
7906
5a0b0cb9
SRT		 7907 /* Initialize mutex for device management commands */
7908 mutex_init(&hba->dev_cmd.lock);
7909
a3cd5ec5
SJ		 7910 init_rwsem(&hba->clk_scaling_lock);
7911
5a0b0cb9
SRT		 7912 /* Initialize device management tag acquire wait queue */
7913 init_waitqueue_head(&hba->dev_cmd.tag_wq);
7914
1ab27c9c 7915 ufshcd_init_clk_gating(hba);
199ef13c
YG		 7916
7917 /*
7918 * In order to avoid any spurious interrupt immediately after
7919 * registering UFS controller interrupt handler, clear any pending UFS
7920 * interrupt status and disable all the UFS interrupts.
7921 */
7922 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
7923 REG_INTERRUPT_STATUS);
7924 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
7925 /*
7926 * Make sure that UFS interrupts are disabled and any pending interrupt
7927 * status is cleared before registering UFS interrupt handler.
7928 */
7929 mb();
7930
7a3e97b0 7931 /* IRQ registration */
2953f850 7932 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 7933 if (err) {
3b1d0580 7934 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 7935 goto exit_gating;
57d104c1
SJ		 7936 } else {
7937 hba->is_irq_enabled = true;
7a3e97b0
SY		 7938 }
7939
3b1d0580 7940 err = scsi_add_host(host, hba->dev);
7a3e97b0 7941 if (err) {
3b1d0580 7942 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 7943 goto exit_gating;
7a3e97b0
SY		 7944 }
7945
6ccf44fe
SJ		 7946 /* Host controller enable */
7947 err = ufshcd_hba_enable(hba);
7a3e97b0 7948 if (err) {
6ccf44fe 7949 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 7950 ufshcd_print_host_regs(hba);
6ba65588 7951 ufshcd_print_host_state(hba);
3b1d0580 7952 goto out_remove_scsi_host;
7a3e97b0 7953 }
6ccf44fe 7954
fcb0c4b0 7955 if (ufshcd_is_clkscaling_supported(hba)) {
401f1e44
SJ		 7956 char wq_name[sizeof("ufs_clkscaling_00")];
7957
401f1e44
SJ		 7958 INIT_WORK(&hba->clk_scaling.suspend_work,
7959 ufshcd_clk_scaling_suspend_work);
7960 INIT_WORK(&hba->clk_scaling.resume_work,
7961 ufshcd_clk_scaling_resume_work);
7962
d985c6ea 7963 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
401f1e44
SJ		 7964 host->host_no);
7965 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
7966
fcb0c4b0 7967 ufshcd_clkscaling_init_sysfs(hba);
856b3483
ST		 7968 }
7969
0c8f7586
SJ		 7970 /*
7971 * Set the default power management level for runtime and system PM.
7972 * Default power saving mode is to keep UFS link in Hibern8 state
7973 * and UFS device in sleep state.
7974 */
7975 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7976 UFS_SLEEP_PWR_MODE,
7977 UIC_LINK_HIBERN8_STATE);
7978 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7979 UFS_SLEEP_PWR_MODE,
7980 UIC_LINK_HIBERN8_STATE);
7981
62694735
SRT		 7982 /* Hold auto suspend until async scan completes */
7983 pm_runtime_get_sync(dev);
7984
57d104c1 7985 /*
7caf489b
SJ		 7986 * We are assuming that device wasn't put in sleep/power-down
7987 * state exclusively during the boot stage before kernel.
7988 * This assumption helps avoid doing link startup twice during
7989 * ufshcd_probe_hba().
57d104c1 7990 */
7caf489b 7991 ufshcd_set_ufs_dev_active(hba);
57d104c1 7992
6ccf44fe 7993 async_schedule(ufshcd_async_scan, hba);
09690d5a 7994 ufshcd_add_sysfs_nodes(hba);
6ccf44fe 7995
7a3e97b0
SY		 7996 return 0;
7997
3b1d0580
VH		 7998out_remove_scsi_host:
7999 scsi_remove_host(hba->host);
1ab27c9c
ST		 8000exit_gating:
8001 ufshcd_exit_clk_gating(hba);
3b1d0580 8002out_disable:
57d104c1 8003 hba->is_irq_enabled = false;
aa497613 8004 ufshcd_hba_exit(hba);
3b1d0580
VH		 8005out_error:
8006 return err;
8007}
8008EXPORT_SYMBOL_GPL(ufshcd_init);
8009
3b1d0580
VH		 8010MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8011MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8012MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8013MODULE_LICENSE("GPL");
8014MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Ubuntu Jammy Linux kernel mirror