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scsi: ufs: don't suspend clock scaling during clock gating
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
7ff5ab47
SJ		 48#define CREATE_TRACE_POINTS
49#include <trace/events/ufs.h>
50
dcea0bfb
GB		 51#define UFSHCD_REQ_SENSE_SIZE 18
52
2fbd009b
SJ		 53#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
54 UTP_TASK_REQ_COMPL |\
55 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 56/* UIC command timeout, unit: ms */
57#define UIC_CMD_TIMEOUT 500
2fbd009b 58
5a0b0cb9
SRT		 59/* NOP OUT retries waiting for NOP IN response */
60#define NOP_OUT_RETRIES 10
61/* Timeout after 30 msecs if NOP OUT hangs without response */
62#define NOP_OUT_TIMEOUT 30 /* msecs */
63
68078d5c 64/* Query request retries */
10fe5888 65#define QUERY_REQ_RETRIES 3
68078d5c 66/* Query request timeout */
10fe5888 67#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 68
e2933132
SRT		 69/* Task management command timeout */
70#define TM_CMD_TIMEOUT 100 /* msecs */
71
64238fbd
YG		 72/* maximum number of retries for a general UIC command */
73#define UFS_UIC_COMMAND_RETRIES 3
74
1d337ec2
SRT		 75/* maximum number of link-startup retries */
76#define DME_LINKSTARTUP_RETRIES 3
77
87d0b4a6
YG		 78/* Maximum retries for Hibern8 enter */
79#define UIC_HIBERN8_ENTER_RETRIES 3
80
1d337ec2
SRT		 81/* maximum number of reset retries before giving up */
82#define MAX_HOST_RESET_RETRIES 5
83
68078d5c
DR		 84/* Expose the flag value from utp_upiu_query.value */
85#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
86
7d568652
SJ		 87/* Interrupt aggregation default timeout, unit: 40us */
88#define INT_AGGR_DEF_TO 0x02
89
aa497613
SRT		 90#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
91 ({ \
92 int _ret; \
93 if (_on) \
94 _ret = ufshcd_enable_vreg(_dev, _vreg); \
95 else \
96 _ret = ufshcd_disable_vreg(_dev, _vreg); \
97 _ret; \
98 })
99
66cc820f
DR		 100#define ufshcd_hex_dump(prefix_str, buf, len) \
101print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false)
102
da461cec
SJ		 103static u32 ufs_query_desc_max_size[] = {
104 QUERY_DESC_DEVICE_MAX_SIZE,
105 QUERY_DESC_CONFIGURAION_MAX_SIZE,
106 QUERY_DESC_UNIT_MAX_SIZE,
107 QUERY_DESC_RFU_MAX_SIZE,
108 QUERY_DESC_INTERCONNECT_MAX_SIZE,
109 QUERY_DESC_STRING_MAX_SIZE,
110 QUERY_DESC_RFU_MAX_SIZE,
1ce21794 111 QUERY_DESC_GEOMETRY_MAX_SIZE,
da461cec
SJ		 112 QUERY_DESC_POWER_MAX_SIZE,
113 QUERY_DESC_RFU_MAX_SIZE,
114};
115
7a3e97b0
SY		 116enum {
117 UFSHCD_MAX_CHANNEL = 0,
118 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 119 UFSHCD_CMD_PER_LUN = 32,
120 UFSHCD_CAN_QUEUE = 32,
121};
122
123/* UFSHCD states */
124enum {
7a3e97b0
SY		 125 UFSHCD_STATE_RESET,
126 UFSHCD_STATE_ERROR,
3441da7d 127 UFSHCD_STATE_OPERATIONAL,
141f8165 128 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 129};
130
131/* UFSHCD error handling flags */
132enum {
133 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 134};
135
e8e7f271
SRT		 136/* UFSHCD UIC layer error flags */
137enum {
138 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 139 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
140 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
141 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
142 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
143 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 144};
145
7a3e97b0
SY		 146/* Interrupt configuration options */
147enum {
148 UFSHCD_INT_DISABLE,
149 UFSHCD_INT_ENABLE,
150 UFSHCD_INT_CLEAR,
151};
152
3441da7d
SRT		 153#define ufshcd_set_eh_in_progress(h) \
154 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
155#define ufshcd_eh_in_progress(h) \
156 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
157#define ufshcd_clear_eh_in_progress(h) \
158 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
159
57d104c1
SJ		 160#define ufshcd_set_ufs_dev_active(h) \
161 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
162#define ufshcd_set_ufs_dev_sleep(h) \
163 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
164#define ufshcd_set_ufs_dev_poweroff(h) \
165 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
166#define ufshcd_is_ufs_dev_active(h) \
167 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
168#define ufshcd_is_ufs_dev_sleep(h) \
169 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
170#define ufshcd_is_ufs_dev_poweroff(h) \
171 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
172
173static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
174 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
175 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
176 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
177 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
178 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
179 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
180};
181
182static inline enum ufs_dev_pwr_mode
183ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
184{
185 return ufs_pm_lvl_states[lvl].dev_state;
186}
187
188static inline enum uic_link_state
189ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
190{
191 return ufs_pm_lvl_states[lvl].link_state;
192}
193
0c8f7586
SJ		 194static inline enum ufs_pm_level
195ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
196 enum uic_link_state link_state)
197{
198 enum ufs_pm_level lvl;
199
200 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
201 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
202 (ufs_pm_lvl_states[lvl].link_state == link_state))
203 return lvl;
204 }
205
206 /* if no match found, return the level 0 */
207 return UFS_PM_LVL_0;
208}
209
56d4a186
SJ		 210static struct ufs_dev_fix ufs_fixups[] = {
211 /* UFS cards deviations table */
212 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
213 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
214 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
215 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
216 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
217 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
218 UFS_DEVICE_NO_FASTAUTO),
219 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
220 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
221 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
222 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
223 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
224 UFS_DEVICE_QUIRK_PA_TACTIVATE),
225 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
226 UFS_DEVICE_QUIRK_PA_TACTIVATE),
227 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
228 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
229 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
230
231 END_FIX
232};
233
3441da7d
SRT		 234static void ufshcd_tmc_handler(struct ufs_hba *hba);
235static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 236static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 237static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 238static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 239static void ufshcd_hba_exit(struct ufs_hba *hba);
240static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 241static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
242 bool skip_ref_clk);
243static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 244static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 245static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
246static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 247static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 248static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 249static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
250static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 251static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 252static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 253static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 254static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
255 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 256static int ufshcd_change_power_mode(struct ufs_hba *hba,
257 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 258static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
259{
260 return tag >= 0 && tag < hba->nutrs;
261}
57d104c1
SJ		 262
263static inline int ufshcd_enable_irq(struct ufs_hba *hba)
264{
265 int ret = 0;
266
267 if (!hba->is_irq_enabled) {
268 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
269 hba);
270 if (ret)
271 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
272 __func__, ret);
273 hba->is_irq_enabled = true;
274 }
275
276 return ret;
277}
278
279static inline void ufshcd_disable_irq(struct ufs_hba *hba)
280{
281 if (hba->is_irq_enabled) {
282 free_irq(hba->irq, hba);
283 hba->is_irq_enabled = false;
284 }
285}
3441da7d 286
b573d484
YG		 287/* replace non-printable or non-ASCII characters with spaces */
288static inline void ufshcd_remove_non_printable(char *val)
289{
290 if (!val)
291 return;
292
293 if (*val < 0x20 || *val > 0x7e)
294 *val = ' ';
295}
296
1a07f2d9
LS		 297static void ufshcd_add_command_trace(struct ufs_hba *hba,
298 unsigned int tag, const char *str)
299{
300 sector_t lba = -1;
301 u8 opcode = 0;
302 u32 intr, doorbell;
303 struct ufshcd_lrb *lrbp;
304 int transfer_len = -1;
305
306 if (!trace_ufshcd_command_enabled())
307 return;
308
309 lrbp = &hba->lrb[tag];
310
311 if (lrbp->cmd) { /* data phase exists */
312 opcode = (u8)(*lrbp->cmd->cmnd);
313 if ((opcode == READ_10) || (opcode == WRITE_10)) {
314 /*
315 * Currently we only fully trace read(10) and write(10)
316 * commands
317 */
318 if (lrbp->cmd->request && lrbp->cmd->request->bio)
319 lba =
320 lrbp->cmd->request->bio->bi_iter.bi_sector;
321 transfer_len = be32_to_cpu(
322 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
323 }
324 }
325
326 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
327 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
328 trace_ufshcd_command(dev_name(hba->dev), str, tag,
329 doorbell, transfer_len, intr, lba, opcode);
330}
331
ff8e20c6
DR		 332static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
333{
334 struct ufs_clk_info *clki;
335 struct list_head *head = &hba->clk_list_head;
336
337 if (!head || list_empty(head))
338 return;
339
340 list_for_each_entry(clki, head, list) {
341 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
342 clki->max_freq)
343 dev_err(hba->dev, "clk: %s, rate: %u\n",
344 clki->name, clki->curr_freq);
345 }
346}
347
348static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
349 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
350{
351 int i;
352
353 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
354 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
355
356 if (err_hist->reg[p] == 0)
357 continue;
358 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
359 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
360 }
361}
362
66cc820f
DR		 363static void ufshcd_print_host_regs(struct ufs_hba *hba)
364{
365 /*
366 * hex_dump reads its data without the readl macro. This might
367 * cause inconsistency issues on some platform, as the printed
368 * values may be from cache and not the most recent value.
369 * To know whether you are looking at an un-cached version verify
370 * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked
371 * during platform/pci probe function.
372 */
373 ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE);
374 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
375 hba->ufs_version, hba->capabilities);
376 dev_err(hba->dev,
377 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
378 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 379 dev_err(hba->dev,
380 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
381 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
382 hba->ufs_stats.hibern8_exit_cnt);
383
384 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
385 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
386 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
387 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
388 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
389
390 ufshcd_print_clk_freqs(hba);
391
392 if (hba->vops && hba->vops->dbg_register_dump)
393 hba->vops->dbg_register_dump(hba);
66cc820f
DR		 394}
395
396static
397void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
398{
399 struct ufshcd_lrb *lrbp;
7fabb77b 400 int prdt_length;
66cc820f
DR		 401 int tag;
402
403 for_each_set_bit(tag, &bitmap, hba->nutrs) {
404 lrbp = &hba->lrb[tag];
405
ff8e20c6
DR		 406 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
407 tag, ktime_to_us(lrbp->issue_time_stamp));
408 dev_err(hba->dev,
409 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
410 tag, (u64)lrbp->utrd_dma_addr);
411
66cc820f
DR		 412 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
413 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 414 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
415 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 416 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
417 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 418 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
419 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 420 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
421 sizeof(struct utp_upiu_rsp));
66cc820f 422
7fabb77b
GB		 423 prdt_length = le16_to_cpu(
424 lrbp->utr_descriptor_ptr->prd_table_length);
425 dev_err(hba->dev,
426 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
427 tag, prdt_length,
428 (u64)lrbp->ucd_prdt_dma_addr);
429
430 if (pr_prdt)
66cc820f 431 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 432 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 433 }
434}
435
436static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
437{
438 struct utp_task_req_desc *tmrdp;
439 int tag;
440
441 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
442 tmrdp = &hba->utmrdl_base_addr[tag];
443 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
444 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
445 sizeof(struct request_desc_header));
446 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
447 tag);
448 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
449 sizeof(struct utp_upiu_req));
450 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
451 tag);
452 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
453 sizeof(struct utp_task_req_desc));
454 }
455}
456
6ba65588
GB		 457static void ufshcd_print_host_state(struct ufs_hba *hba)
458{
459 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
460 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
461 hba->lrb_in_use, hba->outstanding_tasks, hba->outstanding_reqs);
462 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
463 hba->saved_err, hba->saved_uic_err);
464 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
465 hba->curr_dev_pwr_mode, hba->uic_link_state);
466 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
467 hba->pm_op_in_progress, hba->is_sys_suspended);
468 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
469 hba->auto_bkops_enabled, hba->host->host_self_blocked);
470 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
471 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
472 hba->eh_flags, hba->req_abort_count);
473 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
474 hba->capabilities, hba->caps);
475 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
476 hba->dev_quirks);
477}
478
ff8e20c6
DR		 479/**
480 * ufshcd_print_pwr_info - print power params as saved in hba
481 * power info
482 * @hba: per-adapter instance
483 */
484static void ufshcd_print_pwr_info(struct ufs_hba *hba)
485{
486 static const char * const names[] = {
487 "INVALID MODE",
488 "FAST MODE",
489 "SLOW_MODE",
490 "INVALID MODE",
491 "FASTAUTO_MODE",
492 "SLOWAUTO_MODE",
493 "INVALID MODE",
494 };
495
496 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
497 __func__,
498 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
499 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
500 names[hba->pwr_info.pwr_rx],
501 names[hba->pwr_info.pwr_tx],
502 hba->pwr_info.hs_rate);
503}
504
5a0b0cb9
SRT		 505/*
506 * ufshcd_wait_for_register - wait for register value to change
507 * @hba - per-adapter interface
508 * @reg - mmio register offset
509 * @mask - mask to apply to read register value
510 * @val - wait condition
511 * @interval_us - polling interval in microsecs
512 * @timeout_ms - timeout in millisecs
596585a2 513 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 514 *
515 * Returns -ETIMEDOUT on error, zero on success
516 */
596585a2
YG		 517int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
518 u32 val, unsigned long interval_us,
519 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 520{
521 int err = 0;
522 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
523
524 /* ignore bits that we don't intend to wait on */
525 val = val & mask;
526
527 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 528 if (can_sleep)
529 usleep_range(interval_us, interval_us + 50);
530 else
531 udelay(interval_us);
5a0b0cb9
SRT		 532 if (time_after(jiffies, timeout)) {
533 if ((ufshcd_readl(hba, reg) & mask) != val)
534 err = -ETIMEDOUT;
535 break;
536 }
537 }
538
539 return err;
540}
541
2fbd009b
SJ		 542/**
543 * ufshcd_get_intr_mask - Get the interrupt bit mask
544 * @hba - Pointer to adapter instance
545 *
546 * Returns interrupt bit mask per version
547 */
548static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
549{
c01848c6
YG		 550 u32 intr_mask = 0;
551
552 switch (hba->ufs_version) {
553 case UFSHCI_VERSION_10:
554 intr_mask = INTERRUPT_MASK_ALL_VER_10;
555 break;
556 /* allow fall through */
557 case UFSHCI_VERSION_11:
558 case UFSHCI_VERSION_20:
559 intr_mask = INTERRUPT_MASK_ALL_VER_11;
560 break;
561 /* allow fall through */
562 case UFSHCI_VERSION_21:
563 default:
564 intr_mask = INTERRUPT_MASK_ALL_VER_21;
565 }
566
567 return intr_mask;
2fbd009b
SJ		 568}
569
7a3e97b0
SY		 570/**
571 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
572 * @hba - Pointer to adapter instance
573 *
574 * Returns UFSHCI version supported by the controller
575 */
576static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
577{
0263bcd0
YG		 578 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
579 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 580
b873a275 581 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 582}
583
584/**
585 * ufshcd_is_device_present - Check if any device connected to
586 * the host controller
5c0c28a8 587 * @hba: pointer to adapter instance
7a3e97b0 588 *
73ec513a 589 * Returns 1 if device present, 0 if no device detected
7a3e97b0 590 */
5c0c28a8 591static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 592{
5c0c28a8
SRT		 593 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
594 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 595}
596
597/**
598 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
599 * @lrb: pointer to local command reference block
600 *
601 * This function is used to get the OCS field from UTRD
602 * Returns the OCS field in the UTRD
603 */
604static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
605{
e8c8e82a 606 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 607}
608
609/**
610 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
611 * @task_req_descp: pointer to utp_task_req_desc structure
612 *
613 * This function is used to get the OCS field from UTMRD
614 * Returns the OCS field in the UTMRD
615 */
616static inline int
617ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
618{
e8c8e82a 619 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 620}
621
622/**
623 * ufshcd_get_tm_free_slot - get a free slot for task management request
624 * @hba: per adapter instance
e2933132 625 * @free_slot: pointer to variable with available slot value
7a3e97b0 626 *
e2933132
SRT		 627 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
628 * Returns 0 if free slot is not available, else return 1 with tag value
629 * in @free_slot.
7a3e97b0 630 */
e2933132 631static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 632{
e2933132
SRT		 633 int tag;
634 bool ret = false;
635
636 if (!free_slot)
637 goto out;
638
639 do {
640 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
641 if (tag >= hba->nutmrs)
642 goto out;
643 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
644
645 *free_slot = tag;
646 ret = true;
647out:
648 return ret;
649}
650
651static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
652{
653 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 654}
655
656/**
657 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
658 * @hba: per adapter instance
659 * @pos: position of the bit to be cleared
660 */
661static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
662{
b873a275 663 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 664}
665
a48353f6
YG		 666/**
667 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
668 * @hba: per adapter instance
669 * @tag: position of the bit to be cleared
670 */
671static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
672{
673 __clear_bit(tag, &hba->outstanding_reqs);
674}
675
7a3e97b0
SY		 676/**
677 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
678 * @reg: Register value of host controller status
679 *
680 * Returns integer, 0 on Success and positive value if failed
681 */
682static inline int ufshcd_get_lists_status(u32 reg)
683{
684 /*
685 * The mask 0xFF is for the following HCS register bits
686 * Bit Description
687 * 0 Device Present
688 * 1 UTRLRDY
689 * 2 UTMRLRDY
690 * 3 UCRDY
897efe62 691 * 4-7 reserved
7a3e97b0 692 */
897efe62 693 return ((reg & 0xFF) >> 1) ^ 0x07;
7a3e97b0
SY		 694}
695
696/**
697 * ufshcd_get_uic_cmd_result - Get the UIC command result
698 * @hba: Pointer to adapter instance
699 *
700 * This function gets the result of UIC command completion
701 * Returns 0 on success, non zero value on error
702 */
703static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
704{
b873a275 705 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 706 MASK_UIC_COMMAND_RESULT;
707}
708
12b4fdb4
SJ		 709/**
710 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
711 * @hba: Pointer to adapter instance
712 *
713 * This function gets UIC command argument3
714 * Returns 0 on success, non zero value on error
715 */
716static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
717{
718 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
719}
720
7a3e97b0 721/**
5a0b0cb9 722 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 723 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 724 */
725static inline int
5a0b0cb9 726ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 727{
5a0b0cb9 728 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 729}
730
731/**
732 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
733 * @ucd_rsp_ptr: pointer to response UPIU
734 *
735 * This function gets the response status and scsi_status from response UPIU
736 * Returns the response result code.
737 */
738static inline int
739ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
740{
741 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
742}
743
1c2623c5
SJ		 744/*
745 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
746 * from response UPIU
747 * @ucd_rsp_ptr: pointer to response UPIU
748 *
749 * Return the data segment length.
750 */
751static inline unsigned int
752ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
753{
754 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
755 MASK_RSP_UPIU_DATA_SEG_LEN;
756}
757
66ec6d59
SRT		 758/**
759 * ufshcd_is_exception_event - Check if the device raised an exception event
760 * @ucd_rsp_ptr: pointer to response UPIU
761 *
762 * The function checks if the device raised an exception event indicated in
763 * the Device Information field of response UPIU.
764 *
765 * Returns true if exception is raised, false otherwise.
766 */
767static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
768{
769 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
770 MASK_RSP_EXCEPTION_EVENT ? true : false;
771}
772
7a3e97b0 773/**
7d568652 774 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 775 * @hba: per adapter instance
7a3e97b0
SY		 776 */
777static inline void
7d568652 778ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 779{
7d568652
SJ		 780 ufshcd_writel(hba, INT_AGGR_ENABLE |
781 INT_AGGR_COUNTER_AND_TIMER_RESET,
782 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
783}
784
785/**
786 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
787 * @hba: per adapter instance
788 * @cnt: Interrupt aggregation counter threshold
789 * @tmout: Interrupt aggregation timeout value
790 */
791static inline void
792ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
793{
794 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
795 INT_AGGR_COUNTER_THLD_VAL(cnt) |
796 INT_AGGR_TIMEOUT_VAL(tmout),
797 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 798}
799
b852190e
YG		 800/**
801 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
802 * @hba: per adapter instance
803 */
804static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
805{
806 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
807}
808
7a3e97b0
SY		 809/**
810 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
811 * When run-stop registers are set to 1, it indicates the
812 * host controller that it can process the requests
813 * @hba: per adapter instance
814 */
815static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
816{
b873a275
SJ		 817 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
818 REG_UTP_TASK_REQ_LIST_RUN_STOP);
819 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
820 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 821}
822
7a3e97b0
SY		 823/**
824 * ufshcd_hba_start - Start controller initialization sequence
825 * @hba: per adapter instance
826 */
827static inline void ufshcd_hba_start(struct ufs_hba *hba)
828{
b873a275 829 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 830}
831
832/**
833 * ufshcd_is_hba_active - Get controller state
834 * @hba: per adapter instance
835 *
836 * Returns zero if controller is active, 1 otherwise
837 */
838static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
839{
b873a275 840 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 841}
842
09690d5a
SJ		 843static const char *ufschd_uic_link_state_to_string(
844 enum uic_link_state state)
845{
846 switch (state) {
847 case UIC_LINK_OFF_STATE: return "OFF";
848 case UIC_LINK_ACTIVE_STATE: return "ACTIVE";
849 case UIC_LINK_HIBERN8_STATE: return "HIBERN8";
850 default: return "UNKNOWN";
851 }
852}
853
854static const char *ufschd_ufs_dev_pwr_mode_to_string(
855 enum ufs_dev_pwr_mode state)
856{
857 switch (state) {
858 case UFS_ACTIVE_PWR_MODE: return "ACTIVE";
859 case UFS_SLEEP_PWR_MODE: return "SLEEP";
860 case UFS_POWERDOWN_PWR_MODE: return "POWERDOWN";
861 default: return "UNKNOWN";
862 }
863}
864
37113106
YG		 865u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
866{
867 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
868 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
869 (hba->ufs_version == UFSHCI_VERSION_11))
870 return UFS_UNIPRO_VER_1_41;
871 else
872 return UFS_UNIPRO_VER_1_6;
873}
874EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
875
876static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
877{
878 /*
879 * If both host and device support UniPro ver1.6 or later, PA layer
880 * parameters tuning happens during link startup itself.
881 *
882 * We can manually tune PA layer parameters if either host or device
883 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
884 * logic simple, we will only do manual tuning if local unipro version
885 * doesn't support ver1.6 or later.
886 */
887 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
888 return true;
889 else
890 return false;
891}
892
a3cd5ec5
SJ		 893static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
894{
895 int ret = 0;
896 struct ufs_clk_info *clki;
897 struct list_head *head = &hba->clk_list_head;
898 ktime_t start = ktime_get();
899 bool clk_state_changed = false;
900
901 if (!head || list_empty(head))
902 goto out;
903
904 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
905 if (ret)
906 return ret;
907
908 list_for_each_entry(clki, head, list) {
909 if (!IS_ERR_OR_NULL(clki->clk)) {
910 if (scale_up && clki->max_freq) {
911 if (clki->curr_freq == clki->max_freq)
912 continue;
913
914 clk_state_changed = true;
915 ret = clk_set_rate(clki->clk, clki->max_freq);
916 if (ret) {
917 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
918 __func__, clki->name,
919 clki->max_freq, ret);
920 break;
921 }
922 trace_ufshcd_clk_scaling(dev_name(hba->dev),
923 "scaled up", clki->name,
924 clki->curr_freq,
925 clki->max_freq);
926
927 clki->curr_freq = clki->max_freq;
928
929 } else if (!scale_up && clki->min_freq) {
930 if (clki->curr_freq == clki->min_freq)
931 continue;
932
933 clk_state_changed = true;
934 ret = clk_set_rate(clki->clk, clki->min_freq);
935 if (ret) {
936 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
937 __func__, clki->name,
938 clki->min_freq, ret);
939 break;
940 }
941 trace_ufshcd_clk_scaling(dev_name(hba->dev),
942 "scaled down", clki->name,
943 clki->curr_freq,
944 clki->min_freq);
945 clki->curr_freq = clki->min_freq;
946 }
947 }
948 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
949 clki->name, clk_get_rate(clki->clk));
950 }
951
952 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
953
954out:
955 if (clk_state_changed)
956 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
957 (scale_up ? "up" : "down"),
958 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
959 return ret;
960}
961
962/**
963 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
964 * @hba: per adapter instance
965 * @scale_up: True if scaling up and false if scaling down
966 *
967 * Returns true if scaling is required, false otherwise.
968 */
969static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
970 bool scale_up)
971{
972 struct ufs_clk_info *clki;
973 struct list_head *head = &hba->clk_list_head;
974
975 if (!head || list_empty(head))
976 return false;
977
978 list_for_each_entry(clki, head, list) {
979 if (!IS_ERR_OR_NULL(clki->clk)) {
980 if (scale_up && clki->max_freq) {
981 if (clki->curr_freq == clki->max_freq)
982 continue;
983 return true;
984 } else if (!scale_up && clki->min_freq) {
985 if (clki->curr_freq == clki->min_freq)
986 continue;
987 return true;
988 }
989 }
990 }
991
992 return false;
993}
994
995static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
996 u64 wait_timeout_us)
997{
998 unsigned long flags;
999 int ret = 0;
1000 u32 tm_doorbell;
1001 u32 tr_doorbell;
1002 bool timeout = false, do_last_check = false;
1003 ktime_t start;
1004
1005 ufshcd_hold(hba, false);
1006 spin_lock_irqsave(hba->host->host_lock, flags);
1007 /*
1008 * Wait for all the outstanding tasks/transfer requests.
1009 * Verify by checking the doorbell registers are clear.
1010 */
1011 start = ktime_get();
1012 do {
1013 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1014 ret = -EBUSY;
1015 goto out;
1016 }
1017
1018 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1019 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1020 if (!tm_doorbell && !tr_doorbell) {
1021 timeout = false;
1022 break;
1023 } else if (do_last_check) {
1024 break;
1025 }
1026
1027 spin_unlock_irqrestore(hba->host->host_lock, flags);
1028 schedule();
1029 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1030 wait_timeout_us) {
1031 timeout = true;
1032 /*
1033 * We might have scheduled out for long time so make
1034 * sure to check if doorbells are cleared by this time
1035 * or not.
1036 */
1037 do_last_check = true;
1038 }
1039 spin_lock_irqsave(hba->host->host_lock, flags);
1040 } while (tm_doorbell || tr_doorbell);
1041
1042 if (timeout) {
1043 dev_err(hba->dev,
1044 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1045 __func__, tm_doorbell, tr_doorbell);
1046 ret = -EBUSY;
1047 }
1048out:
1049 spin_unlock_irqrestore(hba->host->host_lock, flags);
1050 ufshcd_release(hba);
1051 return ret;
1052}
1053
1054/**
1055 * ufshcd_scale_gear - scale up/down UFS gear
1056 * @hba: per adapter instance
1057 * @scale_up: True for scaling up gear and false for scaling down
1058 *
1059 * Returns 0 for success,
1060 * Returns -EBUSY if scaling can't happen at this time
1061 * Returns non-zero for any other errors
1062 */
1063static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1064{
1065 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1066 int ret = 0;
1067 struct ufs_pa_layer_attr new_pwr_info;
1068
1069 if (scale_up) {
1070 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1071 sizeof(struct ufs_pa_layer_attr));
1072 } else {
1073 memcpy(&new_pwr_info, &hba->pwr_info,
1074 sizeof(struct ufs_pa_layer_attr));
1075
1076 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1077 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1078 /* save the current power mode */
1079 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1080 &hba->pwr_info,
1081 sizeof(struct ufs_pa_layer_attr));
1082
1083 /* scale down gear */
1084 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1085 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1086 }
1087 }
1088
1089 /* check if the power mode needs to be changed or not? */
1090 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1091
1092 if (ret)
1093 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1094 __func__, ret,
1095 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1096 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1097
1098 return ret;
1099}
1100
1101static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1102{
1103 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1104 int ret = 0;
1105 /*
1106 * make sure that there are no outstanding requests when
1107 * clock scaling is in progress
1108 */
1109 scsi_block_requests(hba->host);
1110 down_write(&hba->clk_scaling_lock);
1111 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1112 ret = -EBUSY;
1113 up_write(&hba->clk_scaling_lock);
1114 scsi_unblock_requests(hba->host);
1115 }
1116
1117 return ret;
1118}
1119
1120static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1121{
1122 up_write(&hba->clk_scaling_lock);
1123 scsi_unblock_requests(hba->host);
1124}
1125
1126/**
1127 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1128 * @hba: per adapter instance
1129 * @scale_up: True for scaling up and false for scalin down
1130 *
1131 * Returns 0 for success,
1132 * Returns -EBUSY if scaling can't happen at this time
1133 * Returns non-zero for any other errors
1134 */
1135static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1136{
1137 int ret = 0;
1138
401f1e44
SJ		 1139 /* let's not get into low power until clock scaling is completed */
1140 ufshcd_hold(hba, false);
1141
a3cd5ec5
SJ		 1142 ret = ufshcd_clock_scaling_prepare(hba);
1143 if (ret)
1144 return ret;
1145
1146 /* scale down the gear before scaling down clocks */
1147 if (!scale_up) {
1148 ret = ufshcd_scale_gear(hba, false);
1149 if (ret)
1150 goto out;
1151 }
1152
1153 ret = ufshcd_scale_clks(hba, scale_up);
1154 if (ret) {
1155 if (!scale_up)
1156 ufshcd_scale_gear(hba, true);
1157 goto out;
1158 }
1159
1160 /* scale up the gear after scaling up clocks */
1161 if (scale_up) {
1162 ret = ufshcd_scale_gear(hba, true);
1163 if (ret) {
1164 ufshcd_scale_clks(hba, false);
1165 goto out;
1166 }
1167 }
1168
1169 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1170
1171out:
1172 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1173 ufshcd_release(hba);
a3cd5ec5
SJ		 1174 return ret;
1175}
1176
401f1e44
SJ		 1177static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1178{
1179 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1180 clk_scaling.suspend_work);
1181 unsigned long irq_flags;
1182
1183 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1184 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1185 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1186 return;
1187 }
1188 hba->clk_scaling.is_suspended = true;
1189 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1190
1191 __ufshcd_suspend_clkscaling(hba);
1192}
1193
1194static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1195{
1196 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1197 clk_scaling.resume_work);
1198 unsigned long irq_flags;
1199
1200 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1201 if (!hba->clk_scaling.is_suspended) {
1202 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1203 return;
1204 }
1205 hba->clk_scaling.is_suspended = false;
1206 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1207
1208 devfreq_resume_device(hba->devfreq);
1209}
1210
a3cd5ec5
SJ		 1211static int ufshcd_devfreq_target(struct device *dev,
1212 unsigned long *freq, u32 flags)
1213{
1214 int ret = 0;
1215 struct ufs_hba *hba = dev_get_drvdata(dev);
1216 ktime_t start;
401f1e44 1217 bool scale_up, sched_clk_scaling_suspend_work = false;
a3cd5ec5
SJ		 1218 unsigned long irq_flags;
1219
1220 if (!ufshcd_is_clkscaling_supported(hba))
1221 return -EINVAL;
1222
1223 if ((*freq > 0) && (*freq < UINT_MAX)) {
1224 dev_err(hba->dev, "%s: invalid freq = %lu\n", __func__, *freq);
1225 return -EINVAL;
1226 }
1227
a3cd5ec5
SJ		 1228 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1229 if (ufshcd_eh_in_progress(hba)) {
1230 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1231 return 0;
1232 }
1233
401f1e44
SJ		 1234 if (!hba->clk_scaling.active_reqs)
1235 sched_clk_scaling_suspend_work = true;
1236
1237 scale_up = (*freq == UINT_MAX) ? true : false;
1238 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1239 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1240 ret = 0;
1241 goto out; /* no state change required */
a3cd5ec5
SJ		 1242 }
1243 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1244
1245 start = ktime_get();
a3cd5ec5
SJ		 1246 ret = ufshcd_devfreq_scale(hba, scale_up);
1247
a3cd5ec5
SJ		 1248 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1249 (scale_up ? "up" : "down"),
1250 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1251
401f1e44
SJ		 1252out:
1253 if (sched_clk_scaling_suspend_work)
1254 queue_work(hba->clk_scaling.workq,
1255 &hba->clk_scaling.suspend_work);
1256
a3cd5ec5
SJ		 1257 return ret;
1258}
1259
1260
1261static int ufshcd_devfreq_get_dev_status(struct device *dev,
1262 struct devfreq_dev_status *stat)
1263{
1264 struct ufs_hba *hba = dev_get_drvdata(dev);
1265 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1266 unsigned long flags;
1267
1268 if (!ufshcd_is_clkscaling_supported(hba))
1269 return -EINVAL;
1270
1271 memset(stat, 0, sizeof(*stat));
1272
1273 spin_lock_irqsave(hba->host->host_lock, flags);
1274 if (!scaling->window_start_t)
1275 goto start_window;
1276
1277 if (scaling->is_busy_started)
1278 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1279 scaling->busy_start_t));
1280
1281 stat->total_time = jiffies_to_usecs((long)jiffies -
1282 (long)scaling->window_start_t);
1283 stat->busy_time = scaling->tot_busy_t;
1284start_window:
1285 scaling->window_start_t = jiffies;
1286 scaling->tot_busy_t = 0;
1287
1288 if (hba->outstanding_reqs) {
1289 scaling->busy_start_t = ktime_get();
1290 scaling->is_busy_started = true;
1291 } else {
1292 scaling->busy_start_t = 0;
1293 scaling->is_busy_started = false;
1294 }
1295 spin_unlock_irqrestore(hba->host->host_lock, flags);
1296 return 0;
1297}
1298
1299static struct devfreq_dev_profile ufs_devfreq_profile = {
1300 .polling_ms = 100,
1301 .target = ufshcd_devfreq_target,
1302 .get_dev_status = ufshcd_devfreq_get_dev_status,
1303};
1304
401f1e44
SJ		 1305static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1306{
1307 unsigned long flags;
1308
1309 devfreq_suspend_device(hba->devfreq);
1310 spin_lock_irqsave(hba->host->host_lock, flags);
1311 hba->clk_scaling.window_start_t = 0;
1312 spin_unlock_irqrestore(hba->host->host_lock, flags);
1313}
a3cd5ec5 1314
a508253d
GB		 1315static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1316{
401f1e44
SJ		 1317 unsigned long flags;
1318 bool suspend = false;
1319
fcb0c4b0
ST		 1320 if (!ufshcd_is_clkscaling_supported(hba))
1321 return;
1322
401f1e44
SJ		 1323 spin_lock_irqsave(hba->host->host_lock, flags);
1324 if (!hba->clk_scaling.is_suspended) {
1325 suspend = true;
1326 hba->clk_scaling.is_suspended = true;
1327 }
1328 spin_unlock_irqrestore(hba->host->host_lock, flags);
1329
1330 if (suspend)
1331 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1332}
1333
1334static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1335{
401f1e44
SJ		 1336 unsigned long flags;
1337 bool resume = false;
1338
1339 if (!ufshcd_is_clkscaling_supported(hba))
1340 return;
1341
1342 spin_lock_irqsave(hba->host->host_lock, flags);
1343 if (hba->clk_scaling.is_suspended) {
1344 resume = true;
1345 hba->clk_scaling.is_suspended = false;
1346 }
1347 spin_unlock_irqrestore(hba->host->host_lock, flags);
1348
1349 if (resume)
1350 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1351}
1352
1353static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1354 struct device_attribute *attr, char *buf)
1355{
1356 struct ufs_hba *hba = dev_get_drvdata(dev);
1357
1358 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1359}
1360
1361static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1362 struct device_attribute *attr, const char *buf, size_t count)
1363{
1364 struct ufs_hba *hba = dev_get_drvdata(dev);
1365 u32 value;
1366 int err;
1367
1368 if (kstrtou32(buf, 0, &value))
1369 return -EINVAL;
1370
1371 value = !!value;
1372 if (value == hba->clk_scaling.is_allowed)
1373 goto out;
1374
1375 pm_runtime_get_sync(hba->dev);
1376 ufshcd_hold(hba, false);
1377
401f1e44
SJ		 1378 cancel_work_sync(&hba->clk_scaling.suspend_work);
1379 cancel_work_sync(&hba->clk_scaling.resume_work);
1380
1381 hba->clk_scaling.is_allowed = value;
1382
fcb0c4b0
ST		 1383 if (value) {
1384 ufshcd_resume_clkscaling(hba);
1385 } else {
1386 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1387 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1388 if (err)
1389 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1390 __func__, err);
1391 }
fcb0c4b0
ST		 1392
1393 ufshcd_release(hba);
1394 pm_runtime_put_sync(hba->dev);
1395out:
1396 return count;
a508253d
GB		 1397}
1398
a3cd5ec5
SJ		 1399static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1400{
1401 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1402 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1403 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1404 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1405 hba->clk_scaling.enable_attr.attr.mode = 0644;
1406 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1407 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1408}
1409
1ab27c9c
ST		 1410static void ufshcd_ungate_work(struct work_struct *work)
1411{
1412 int ret;
1413 unsigned long flags;
1414 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1415 clk_gating.ungate_work);
1416
1417 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1418
1419 spin_lock_irqsave(hba->host->host_lock, flags);
1420 if (hba->clk_gating.state == CLKS_ON) {
1421 spin_unlock_irqrestore(hba->host->host_lock, flags);
1422 goto unblock_reqs;
1423 }
1424
1425 spin_unlock_irqrestore(hba->host->host_lock, flags);
1426 ufshcd_setup_clocks(hba, true);
1427
1428 /* Exit from hibern8 */
1429 if (ufshcd_can_hibern8_during_gating(hba)) {
1430 /* Prevent gating in this path */
1431 hba->clk_gating.is_suspended = true;
1432 if (ufshcd_is_link_hibern8(hba)) {
1433 ret = ufshcd_uic_hibern8_exit(hba);
1434 if (ret)
1435 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1436 __func__, ret);
1437 else
1438 ufshcd_set_link_active(hba);
1439 }
1440 hba->clk_gating.is_suspended = false;
1441 }
1442unblock_reqs:
1443 scsi_unblock_requests(hba->host);
1444}
1445
1446/**
1447 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1448 * Also, exit from hibern8 mode and set the link as active.
1449 * @hba: per adapter instance
1450 * @async: This indicates whether caller should ungate clocks asynchronously.
1451 */
1452int ufshcd_hold(struct ufs_hba *hba, bool async)
1453{
1454 int rc = 0;
1455 unsigned long flags;
1456
1457 if (!ufshcd_is_clkgating_allowed(hba))
1458 goto out;
1ab27c9c
ST		 1459 spin_lock_irqsave(hba->host->host_lock, flags);
1460 hba->clk_gating.active_reqs++;
1461
53c12d0e
YG		 1462 if (ufshcd_eh_in_progress(hba)) {
1463 spin_unlock_irqrestore(hba->host->host_lock, flags);
1464 return 0;
1465 }
1466
856b3483 1467start:
1ab27c9c
ST		 1468 switch (hba->clk_gating.state) {
1469 case CLKS_ON:
f2a785ac
VG		 1470 /*
1471 * Wait for the ungate work to complete if in progress.
1472 * Though the clocks may be in ON state, the link could
1473 * still be in hibner8 state if hibern8 is allowed
1474 * during clock gating.
1475 * Make sure we exit hibern8 state also in addition to
1476 * clocks being ON.
1477 */
1478 if (ufshcd_can_hibern8_during_gating(hba) &&
1479 ufshcd_is_link_hibern8(hba)) {
1480 spin_unlock_irqrestore(hba->host->host_lock, flags);
1481 flush_work(&hba->clk_gating.ungate_work);
1482 spin_lock_irqsave(hba->host->host_lock, flags);
1483 goto start;
1484 }
1ab27c9c
ST		 1485 break;
1486 case REQ_CLKS_OFF:
1487 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1488 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1489 trace_ufshcd_clk_gating(dev_name(hba->dev),
1490 hba->clk_gating.state);
1ab27c9c
ST		 1491 break;
1492 }
1493 /*
1494 * If we here, it means gating work is either done or
1495 * currently running. Hence, fall through to cancel gating
1496 * work and to enable clocks.
1497 */
1498 case CLKS_OFF:
1499 scsi_block_requests(hba->host);
1500 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47
SJ		 1501 trace_ufshcd_clk_gating(dev_name(hba->dev),
1502 hba->clk_gating.state);
1ab27c9c
ST		 1503 schedule_work(&hba->clk_gating.ungate_work);
1504 /*
1505 * fall through to check if we should wait for this
1506 * work to be done or not.
1507 */
1508 case REQ_CLKS_ON:
1509 if (async) {
1510 rc = -EAGAIN;
1511 hba->clk_gating.active_reqs--;
1512 break;
1513 }
1514
1515 spin_unlock_irqrestore(hba->host->host_lock, flags);
1516 flush_work(&hba->clk_gating.ungate_work);
1517 /* Make sure state is CLKS_ON before returning */
856b3483 1518 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1519 goto start;
1520 default:
1521 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1522 __func__, hba->clk_gating.state);
1523 break;
1524 }
1525 spin_unlock_irqrestore(hba->host->host_lock, flags);
1526out:
1527 return rc;
1528}
6e3fd44d 1529EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1530
1531static void ufshcd_gate_work(struct work_struct *work)
1532{
1533 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1534 clk_gating.gate_work.work);
1535 unsigned long flags;
1536
1537 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1538 /*
1539 * In case you are here to cancel this work the gating state
1540 * would be marked as REQ_CLKS_ON. In this case save time by
1541 * skipping the gating work and exit after changing the clock
1542 * state to CLKS_ON.
1543 */
1544 if (hba->clk_gating.is_suspended ||
1545 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1546 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1547 trace_ufshcd_clk_gating(dev_name(hba->dev),
1548 hba->clk_gating.state);
1ab27c9c
ST		 1549 goto rel_lock;
1550 }
1551
1552 if (hba->clk_gating.active_reqs
1553 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1554 || hba->lrb_in_use || hba->outstanding_tasks
1555 || hba->active_uic_cmd || hba->uic_async_done)
1556 goto rel_lock;
1557
1558 spin_unlock_irqrestore(hba->host->host_lock, flags);
1559
1560 /* put the link into hibern8 mode before turning off clocks */
1561 if (ufshcd_can_hibern8_during_gating(hba)) {
1562 if (ufshcd_uic_hibern8_enter(hba)) {
1563 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1564 trace_ufshcd_clk_gating(dev_name(hba->dev),
1565 hba->clk_gating.state);
1ab27c9c
ST		 1566 goto out;
1567 }
1568 ufshcd_set_link_hibern8(hba);
1569 }
1570
1571 if (!ufshcd_is_link_active(hba))
1572 ufshcd_setup_clocks(hba, false);
1573 else
1574 /* If link is active, device ref_clk can't be switched off */
1575 __ufshcd_setup_clocks(hba, false, true);
1576
1577 /*
1578 * In case you are here to cancel this work the gating state
1579 * would be marked as REQ_CLKS_ON. In this case keep the state
1580 * as REQ_CLKS_ON which would anyway imply that clocks are off
1581 * and a request to turn them on is pending. By doing this way,
1582 * we keep the state machine in tact and this would ultimately
1583 * prevent from doing cancel work multiple times when there are
1584 * new requests arriving before the current cancel work is done.
1585 */
1586 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1587 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1588 hba->clk_gating.state = CLKS_OFF;
7ff5ab47
SJ		 1589 trace_ufshcd_clk_gating(dev_name(hba->dev),
1590 hba->clk_gating.state);
1591 }
1ab27c9c
ST		 1592rel_lock:
1593 spin_unlock_irqrestore(hba->host->host_lock, flags);
1594out:
1595 return;
1596}
1597
1598/* host lock must be held before calling this variant */
1599static void __ufshcd_release(struct ufs_hba *hba)
1600{
1601 if (!ufshcd_is_clkgating_allowed(hba))
1602 return;
1603
1604 hba->clk_gating.active_reqs--;
1605
1606 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1607 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1608 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 1609 || hba->active_uic_cmd || hba->uic_async_done
1610 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1611 return;
1612
1613 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1614 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1ab27c9c
ST		 1615 schedule_delayed_work(&hba->clk_gating.gate_work,
1616 msecs_to_jiffies(hba->clk_gating.delay_ms));
1617}
1618
1619void ufshcd_release(struct ufs_hba *hba)
1620{
1621 unsigned long flags;
1622
1623 spin_lock_irqsave(hba->host->host_lock, flags);
1624 __ufshcd_release(hba);
1625 spin_unlock_irqrestore(hba->host->host_lock, flags);
1626}
6e3fd44d 1627EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1628
1629static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1630 struct device_attribute *attr, char *buf)
1631{
1632 struct ufs_hba *hba = dev_get_drvdata(dev);
1633
1634 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1635}
1636
1637static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1638 struct device_attribute *attr, const char *buf, size_t count)
1639{
1640 struct ufs_hba *hba = dev_get_drvdata(dev);
1641 unsigned long flags, value;
1642
1643 if (kstrtoul(buf, 0, &value))
1644 return -EINVAL;
1645
1646 spin_lock_irqsave(hba->host->host_lock, flags);
1647 hba->clk_gating.delay_ms = value;
1648 spin_unlock_irqrestore(hba->host->host_lock, flags);
1649 return count;
1650}
1651
b427411a
ST		 1652static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1653 struct device_attribute *attr, char *buf)
1654{
1655 struct ufs_hba *hba = dev_get_drvdata(dev);
1656
1657 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1658}
1659
1660static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1661 struct device_attribute *attr, const char *buf, size_t count)
1662{
1663 struct ufs_hba *hba = dev_get_drvdata(dev);
1664 unsigned long flags;
1665 u32 value;
1666
1667 if (kstrtou32(buf, 0, &value))
1668 return -EINVAL;
1669
1670 value = !!value;
1671 if (value == hba->clk_gating.is_enabled)
1672 goto out;
1673
1674 if (value) {
1675 ufshcd_release(hba);
1676 } else {
1677 spin_lock_irqsave(hba->host->host_lock, flags);
1678 hba->clk_gating.active_reqs++;
1679 spin_unlock_irqrestore(hba->host->host_lock, flags);
1680 }
1681
1682 hba->clk_gating.is_enabled = value;
1683out:
1684 return count;
1685}
1686
1ab27c9c
ST		 1687static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1688{
1689 if (!ufshcd_is_clkgating_allowed(hba))
1690 return;
1691
1692 hba->clk_gating.delay_ms = 150;
1693 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1694 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1695
b427411a
ST		 1696 hba->clk_gating.is_enabled = true;
1697
1ab27c9c
ST		 1698 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1699 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1700 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1701 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1702 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1703 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1704 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1705
1706 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1707 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1708 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1709 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1710 hba->clk_gating.enable_attr.attr.mode = 0644;
1711 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1712 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1713}
1714
1715static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1716{
1717 if (!ufshcd_is_clkgating_allowed(hba))
1718 return;
1719 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1720 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1721 cancel_work_sync(&hba->clk_gating.ungate_work);
1722 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 1723}
1724
856b3483
ST		 1725/* Must be called with host lock acquired */
1726static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1727{
401f1e44
SJ		 1728 bool queue_resume_work = false;
1729
fcb0c4b0 1730 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1731 return;
1732
401f1e44
SJ		 1733 if (!hba->clk_scaling.active_reqs++)
1734 queue_resume_work = true;
1735
1736 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1737 return;
1738
1739 if (queue_resume_work)
1740 queue_work(hba->clk_scaling.workq,
1741 &hba->clk_scaling.resume_work);
1742
1743 if (!hba->clk_scaling.window_start_t) {
1744 hba->clk_scaling.window_start_t = jiffies;
1745 hba->clk_scaling.tot_busy_t = 0;
1746 hba->clk_scaling.is_busy_started = false;
1747 }
1748
856b3483
ST		 1749 if (!hba->clk_scaling.is_busy_started) {
1750 hba->clk_scaling.busy_start_t = ktime_get();
1751 hba->clk_scaling.is_busy_started = true;
1752 }
1753}
1754
1755static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1756{
1757 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1758
fcb0c4b0 1759 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1760 return;
1761
1762 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1763 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1764 scaling->busy_start_t));
8b0e1953 1765 scaling->busy_start_t = 0;
856b3483
ST		 1766 scaling->is_busy_started = false;
1767 }
1768}
7a3e97b0
SY		 1769/**
1770 * ufshcd_send_command - Send SCSI or device management commands
1771 * @hba: per adapter instance
1772 * @task_tag: Task tag of the command
1773 */
1774static inline
1775void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1776{
ff8e20c6 1777 hba->lrb[task_tag].issue_time_stamp = ktime_get();
856b3483 1778 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1779 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1780 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1781 /* Make sure that doorbell is committed immediately */
1782 wmb();
1a07f2d9 1783 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY		 1784}
1785
1786/**
1787 * ufshcd_copy_sense_data - Copy sense data in case of check condition
1788 * @lrb - pointer to local reference block
1789 */
1790static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1791{
1792 int len;
1c2623c5
SJ		 1793 if (lrbp->sense_buffer &&
1794 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1795 int len_to_copy;
1796
5a0b0cb9 1797 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1798 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1799
7a3e97b0 1800 memcpy(lrbp->sense_buffer,
5a0b0cb9 1801 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1802 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1803 }
1804}
1805
68078d5c
DR		 1806/**
1807 * ufshcd_copy_query_response() - Copy the Query Response and the data
1808 * descriptor
1809 * @hba: per adapter instance
1810 * @lrb - pointer to local reference block
1811 */
1812static
c6d4a831 1813int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1814{
1815 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1816
68078d5c 1817 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1818
68078d5c
DR		 1819 /* Get the descriptor */
1820 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1821 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1822 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1823 u16 resp_len;
1824 u16 buf_len;
68078d5c
DR		 1825
1826 /* data segment length */
c6d4a831 1827 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1828 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1829 buf_len = be16_to_cpu(
1830 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1831 if (likely(buf_len >= resp_len)) {
1832 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1833 } else {
1834 dev_warn(hba->dev,
1835 "%s: Response size is bigger than buffer",
1836 __func__);
1837 return -EINVAL;
1838 }
68078d5c 1839 }
c6d4a831
DR		 1840
1841 return 0;
68078d5c
DR		 1842}
1843
7a3e97b0
SY		 1844/**
1845 * ufshcd_hba_capabilities - Read controller capabilities
1846 * @hba: per adapter instance
1847 */
1848static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1849{
b873a275 1850 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1851
1852 /* nutrs and nutmrs are 0 based values */
1853 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1854 hba->nutmrs =
1855 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1856}
1857
1858/**
6ccf44fe
SJ		 1859 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1860 * to accept UIC commands
7a3e97b0 1861 * @hba: per adapter instance
6ccf44fe
SJ		 1862 * Return true on success, else false
1863 */
1864static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1865{
1866 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1867 return true;
1868 else
1869 return false;
1870}
1871
53b3d9c3
SJ		 1872/**
1873 * ufshcd_get_upmcrs - Get the power mode change request status
1874 * @hba: Pointer to adapter instance
1875 *
1876 * This function gets the UPMCRS field of HCS register
1877 * Returns value of UPMCRS field
1878 */
1879static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1880{
1881 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1882}
1883
6ccf44fe
SJ		 1884/**
1885 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1886 * @hba: per adapter instance
1887 * @uic_cmd: UIC command
1888 *
1889 * Mutex must be held.
7a3e97b0
SY		 1890 */
1891static inline void
6ccf44fe 1892ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1893{
6ccf44fe
SJ		 1894 WARN_ON(hba->active_uic_cmd);
1895
1896 hba->active_uic_cmd = uic_cmd;
1897
7a3e97b0 1898 /* Write Args */
6ccf44fe
SJ		 1899 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1900 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1901 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1902
1903 /* Write UIC Cmd */
6ccf44fe 1904 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1905 REG_UIC_COMMAND);
7a3e97b0
SY		 1906}
1907
6ccf44fe
SJ		 1908/**
1909 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1910 * @hba: per adapter instance
1911 * @uic_command: UIC command
1912 *
1913 * Must be called with mutex held.
1914 * Returns 0 only if success.
1915 */
1916static int
1917ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1918{
1919 int ret;
1920 unsigned long flags;
1921
1922 if (wait_for_completion_timeout(&uic_cmd->done,
1923 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1924 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1925 else
1926 ret = -ETIMEDOUT;
1927
1928 spin_lock_irqsave(hba->host->host_lock, flags);
1929 hba->active_uic_cmd = NULL;
1930 spin_unlock_irqrestore(hba->host->host_lock, flags);
1931
1932 return ret;
1933}
1934
1935/**
1936 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1937 * @hba: per adapter instance
1938 * @uic_cmd: UIC command
d75f7fe4 1939 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1940 *
1941 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1942 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1943 * Returns 0 only if success.
1944 */
1945static int
d75f7fe4
YG		 1946__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1947 bool completion)
6ccf44fe 1948{
6ccf44fe
SJ		 1949 if (!ufshcd_ready_for_uic_cmd(hba)) {
1950 dev_err(hba->dev,
1951 "Controller not ready to accept UIC commands\n");
1952 return -EIO;
1953 }
1954
d75f7fe4
YG		 1955 if (completion)
1956 init_completion(&uic_cmd->done);
6ccf44fe 1957
6ccf44fe 1958 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1959
57d104c1 1960 return 0;
6ccf44fe
SJ		 1961}
1962
1963/**
1964 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1965 * @hba: per adapter instance
1966 * @uic_cmd: UIC command
1967 *
1968 * Returns 0 only if success.
1969 */
1970static int
1971ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1972{
1973 int ret;
57d104c1 1974 unsigned long flags;
6ccf44fe 1975
1ab27c9c 1976 ufshcd_hold(hba, false);
6ccf44fe 1977 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1978 ufshcd_add_delay_before_dme_cmd(hba);
1979
57d104c1 1980 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1981 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 1982 spin_unlock_irqrestore(hba->host->host_lock, flags);
1983 if (!ret)
1984 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1985
6ccf44fe
SJ		 1986 mutex_unlock(&hba->uic_cmd_mutex);
1987
1ab27c9c 1988 ufshcd_release(hba);
6ccf44fe
SJ		 1989 return ret;
1990}
1991
7a3e97b0
SY		 1992/**
1993 * ufshcd_map_sg - Map scatter-gather list to prdt
1994 * @lrbp - pointer to local reference block
1995 *
1996 * Returns 0 in case of success, non-zero value in case of failure
1997 */
75b1cc4a 1998static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 1999{
2000 struct ufshcd_sg_entry *prd_table;
2001 struct scatterlist *sg;
2002 struct scsi_cmnd *cmd;
2003 int sg_segments;
2004 int i;
2005
2006 cmd = lrbp->cmd;
2007 sg_segments = scsi_dma_map(cmd);
2008 if (sg_segments < 0)
2009 return sg_segments;
2010
2011 if (sg_segments) {
75b1cc4a
KK		 2012 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2013 lrbp->utr_descriptor_ptr->prd_table_length =
2014 cpu_to_le16((u16)(sg_segments *
2015 sizeof(struct ufshcd_sg_entry)));
2016 else
2017 lrbp->utr_descriptor_ptr->prd_table_length =
2018 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2019
2020 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2021
2022 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2023 prd_table[i].size =
2024 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2025 prd_table[i].base_addr =
2026 cpu_to_le32(lower_32_bits(sg->dma_address));
2027 prd_table[i].upper_addr =
2028 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2029 prd_table[i].reserved = 0;
7a3e97b0
SY		 2030 }
2031 } else {
2032 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2033 }
2034
2035 return 0;
2036}
2037
2038/**
2fbd009b 2039 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2040 * @hba: per adapter instance
2fbd009b 2041 * @intrs: interrupt bits
7a3e97b0 2042 */
2fbd009b 2043static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2044{
2fbd009b
SJ		 2045 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2046
2047 if (hba->ufs_version == UFSHCI_VERSION_10) {
2048 u32 rw;
2049 rw = set & INTERRUPT_MASK_RW_VER_10;
2050 set = rw | ((set ^ intrs) & intrs);
2051 } else {
2052 set |= intrs;
2053 }
2054
2055 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2056}
2057
2058/**
2059 * ufshcd_disable_intr - disable interrupts
2060 * @hba: per adapter instance
2061 * @intrs: interrupt bits
2062 */
2063static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2064{
2065 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2066
2067 if (hba->ufs_version == UFSHCI_VERSION_10) {
2068 u32 rw;
2069 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2070 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2071 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2072
2073 } else {
2074 set &= ~intrs;
7a3e97b0 2075 }
2fbd009b
SJ		 2076
2077 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2078}
2079
5a0b0cb9
SRT		 2080/**
2081 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2082 * descriptor according to request
2083 * @lrbp: pointer to local reference block
2084 * @upiu_flags: flags required in the header
2085 * @cmd_dir: requests data direction
2086 */
2087static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2088 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2089{
2090 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2091 u32 data_direction;
2092 u32 dword_0;
2093
2094 if (cmd_dir == DMA_FROM_DEVICE) {
2095 data_direction = UTP_DEVICE_TO_HOST;
2096 *upiu_flags = UPIU_CMD_FLAGS_READ;
2097 } else if (cmd_dir == DMA_TO_DEVICE) {
2098 data_direction = UTP_HOST_TO_DEVICE;
2099 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2100 } else {
2101 data_direction = UTP_NO_DATA_TRANSFER;
2102 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2103 }
2104
2105 dword_0 = data_direction | (lrbp->command_type
2106 << UPIU_COMMAND_TYPE_OFFSET);
2107 if (lrbp->intr_cmd)
2108 dword_0 |= UTP_REQ_DESC_INT_CMD;
2109
2110 /* Transfer request descriptor header fields */
2111 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2112 /* dword_1 is reserved, hence it is set to 0 */
2113 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2114 /*
2115 * assigning invalid value for command status. Controller
2116 * updates OCS on command completion, with the command
2117 * status
2118 */
2119 req_desc->header.dword_2 =
2120 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2121 /* dword_3 is reserved, hence it is set to 0 */
2122 req_desc->header.dword_3 = 0;
51047266
YG		 2123
2124 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2125}
2126
2127/**
2128 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2129 * for scsi commands
2130 * @lrbp - local reference block pointer
2131 * @upiu_flags - flags
2132 */
2133static
2134void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2135{
2136 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2137 unsigned short cdb_len;
5a0b0cb9
SRT		 2138
2139 /* command descriptor fields */
2140 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2141 UPIU_TRANSACTION_COMMAND, upiu_flags,
2142 lrbp->lun, lrbp->task_tag);
2143 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2144 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2145
2146 /* Total EHS length and Data segment length will be zero */
2147 ucd_req_ptr->header.dword_2 = 0;
2148
2149 ucd_req_ptr->sc.exp_data_transfer_len =
2150 cpu_to_be32(lrbp->cmd->sdb.length);
2151
52ac95fe
YG		 2152 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
2153 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
2154 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2155
2156 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2157}
2158
68078d5c
DR		 2159/**
2160 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2161 * for query requsts
2162 * @hba: UFS hba
2163 * @lrbp: local reference block pointer
2164 * @upiu_flags: flags
2165 */
2166static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2167 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2168{
2169 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2170 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2171 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2172 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2173
2174 /* Query request header */
2175 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2176 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2177 lrbp->lun, lrbp->task_tag);
2178 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2179 0, query->request.query_func, 0, 0);
2180
6861285c
ZL		 2181 /* Data segment length only need for WRITE_DESC */
2182 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2183 ucd_req_ptr->header.dword_2 =
2184 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2185 else
2186 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2187
2188 /* Copy the Query Request buffer as is */
2189 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2190 QUERY_OSF_SIZE);
68078d5c
DR		 2191
2192 /* Copy the Descriptor */
c6d4a831
DR		 2193 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2194 memcpy(descp, query->descriptor, len);
2195
51047266 2196 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2197}
2198
5a0b0cb9
SRT		 2199static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2200{
2201 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2202
2203 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2204
2205 /* command descriptor fields */
2206 ucd_req_ptr->header.dword_0 =
2207 UPIU_HEADER_DWORD(
2208 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2209 /* clear rest of the fields of basic header */
2210 ucd_req_ptr->header.dword_1 = 0;
2211 ucd_req_ptr->header.dword_2 = 0;
2212
2213 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2214}
2215
7a3e97b0 2216/**
300bb13f
JP		 2217 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2218 * for Device Management Purposes
5a0b0cb9 2219 * @hba - per adapter instance
7a3e97b0
SY		 2220 * @lrb - pointer to local reference block
2221 */
300bb13f 2222static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2223{
7a3e97b0 2224 u32 upiu_flags;
5a0b0cb9 2225 int ret = 0;
7a3e97b0 2226
300bb13f
JP		 2227 if (hba->ufs_version == UFSHCI_VERSION_20)
2228 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2229 else
2230 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2231
2232 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2233 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2234 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2235 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2236 ufshcd_prepare_utp_nop_upiu(lrbp);
2237 else
2238 ret = -EINVAL;
2239
2240 return ret;
2241}
2242
2243/**
2244 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2245 * for SCSI Purposes
2246 * @hba - per adapter instance
2247 * @lrb - pointer to local reference block
2248 */
2249static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2250{
2251 u32 upiu_flags;
2252 int ret = 0;
2253
2254 if (hba->ufs_version == UFSHCI_VERSION_20)
2255 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2256 else
2257 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2258
2259 if (likely(lrbp->cmd)) {
2260 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2261 lrbp->cmd->sc_data_direction);
2262 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2263 } else {
2264 ret = -EINVAL;
2265 }
5a0b0cb9
SRT		 2266
2267 return ret;
7a3e97b0
SY		 2268}
2269
0ce147d4
SJ		 2270/*
2271 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
2272 * @scsi_lun: scsi LUN id
2273 *
2274 * Returns UPIU LUN id
2275 */
2276static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
2277{
2278 if (scsi_is_wlun(scsi_lun))
2279 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
2280 | UFS_UPIU_WLUN_ID;
2281 else
2282 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
2283}
2284
2a8fa600
SJ		 2285/**
2286 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2287 * @scsi_lun: UPIU W-LUN id
2288 *
2289 * Returns SCSI W-LUN id
2290 */
2291static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2292{
2293 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2294}
2295
7a3e97b0
SY		 2296/**
2297 * ufshcd_queuecommand - main entry point for SCSI requests
2298 * @cmd: command from SCSI Midlayer
2299 * @done: call back function
2300 *
2301 * Returns 0 for success, non-zero in case of failure
2302 */
2303static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2304{
2305 struct ufshcd_lrb *lrbp;
2306 struct ufs_hba *hba;
2307 unsigned long flags;
2308 int tag;
2309 int err = 0;
2310
2311 hba = shost_priv(host);
2312
2313 tag = cmd->request->tag;
14497328
YG		 2314 if (!ufshcd_valid_tag(hba, tag)) {
2315 dev_err(hba->dev,
2316 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2317 __func__, tag, cmd, cmd->request);
2318 BUG();
2319 }
7a3e97b0 2320
a3cd5ec5
SJ		 2321 if (!down_read_trylock(&hba->clk_scaling_lock))
2322 return SCSI_MLQUEUE_HOST_BUSY;
2323
3441da7d
SRT		 2324 spin_lock_irqsave(hba->host->host_lock, flags);
2325 switch (hba->ufshcd_state) {
2326 case UFSHCD_STATE_OPERATIONAL:
2327 break;
141f8165 2328 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2329 case UFSHCD_STATE_RESET:
7a3e97b0 2330 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2331 goto out_unlock;
2332 case UFSHCD_STATE_ERROR:
2333 set_host_byte(cmd, DID_ERROR);
2334 cmd->scsi_done(cmd);
2335 goto out_unlock;
2336 default:
2337 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2338 __func__, hba->ufshcd_state);
2339 set_host_byte(cmd, DID_BAD_TARGET);
2340 cmd->scsi_done(cmd);
2341 goto out_unlock;
7a3e97b0 2342 }
53c12d0e
YG		 2343
2344 /* if error handling is in progress, don't issue commands */
2345 if (ufshcd_eh_in_progress(hba)) {
2346 set_host_byte(cmd, DID_ERROR);
2347 cmd->scsi_done(cmd);
2348 goto out_unlock;
2349 }
3441da7d 2350 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2351
7fabb77b
GB		 2352 hba->req_abort_count = 0;
2353
5a0b0cb9
SRT		 2354 /* acquire the tag to make sure device cmds don't use it */
2355 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2356 /*
2357 * Dev manage command in progress, requeue the command.
2358 * Requeuing the command helps in cases where the request *may*
2359 * find different tag instead of waiting for dev manage command
2360 * completion.
2361 */
2362 err = SCSI_MLQUEUE_HOST_BUSY;
2363 goto out;
2364 }
2365
1ab27c9c
ST		 2366 err = ufshcd_hold(hba, true);
2367 if (err) {
2368 err = SCSI_MLQUEUE_HOST_BUSY;
2369 clear_bit_unlock(tag, &hba->lrb_in_use);
2370 goto out;
2371 }
2372 WARN_ON(hba->clk_gating.state != CLKS_ON);
2373
7a3e97b0
SY		 2374 lrbp = &hba->lrb[tag];
2375
5a0b0cb9 2376 WARN_ON(lrbp->cmd);
7a3e97b0 2377 lrbp->cmd = cmd;
dcea0bfb 2378 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 2379 lrbp->sense_buffer = cmd->sense_buffer;
2380 lrbp->task_tag = tag;
0ce147d4 2381 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2382 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2383 lrbp->req_abort_skip = false;
7a3e97b0 2384
300bb13f
JP		 2385 ufshcd_comp_scsi_upiu(hba, lrbp);
2386
75b1cc4a 2387 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2388 if (err) {
2389 lrbp->cmd = NULL;
2390 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2391 goto out;
5a0b0cb9 2392 }
ad1a1b9c
GB		 2393 /* Make sure descriptors are ready before ringing the doorbell */
2394 wmb();
7a3e97b0
SY		 2395
2396 /* issue command to the controller */
2397 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2398 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 2399 ufshcd_send_command(hba, tag);
3441da7d 2400out_unlock:
7a3e97b0
SY		 2401 spin_unlock_irqrestore(hba->host->host_lock, flags);
2402out:
a3cd5ec5 2403 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2404 return err;
2405}
2406
5a0b0cb9
SRT		 2407static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2408 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2409{
2410 lrbp->cmd = NULL;
2411 lrbp->sense_bufflen = 0;
2412 lrbp->sense_buffer = NULL;
2413 lrbp->task_tag = tag;
2414 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2415 lrbp->intr_cmd = true; /* No interrupt aggregation */
2416 hba->dev_cmd.type = cmd_type;
2417
300bb13f 2418 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2419}
2420
2421static int
2422ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2423{
2424 int err = 0;
2425 unsigned long flags;
2426 u32 mask = 1 << tag;
2427
2428 /* clear outstanding transaction before retry */
2429 spin_lock_irqsave(hba->host->host_lock, flags);
2430 ufshcd_utrl_clear(hba, tag);
2431 spin_unlock_irqrestore(hba->host->host_lock, flags);
2432
2433 /*
2434 * wait for for h/w to clear corresponding bit in door-bell.
2435 * max. wait is 1 sec.
2436 */
2437 err = ufshcd_wait_for_register(hba,
2438 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2439 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2440
2441 return err;
2442}
2443
c6d4a831
DR		 2444static int
2445ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2446{
2447 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2448
2449 /* Get the UPIU response */
2450 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2451 UPIU_RSP_CODE_OFFSET;
2452 return query_res->response;
2453}
2454
5a0b0cb9
SRT		 2455/**
2456 * ufshcd_dev_cmd_completion() - handles device management command responses
2457 * @hba: per adapter instance
2458 * @lrbp: pointer to local reference block
2459 */
2460static int
2461ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2462{
2463 int resp;
2464 int err = 0;
2465
ff8e20c6 2466 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2467 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2468
2469 switch (resp) {
2470 case UPIU_TRANSACTION_NOP_IN:
2471 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2472 err = -EINVAL;
2473 dev_err(hba->dev, "%s: unexpected response %x\n",
2474 __func__, resp);
2475 }
2476 break;
68078d5c 2477 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2478 err = ufshcd_check_query_response(hba, lrbp);
2479 if (!err)
2480 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2481 break;
5a0b0cb9
SRT		 2482 case UPIU_TRANSACTION_REJECT_UPIU:
2483 /* TODO: handle Reject UPIU Response */
2484 err = -EPERM;
2485 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2486 __func__);
2487 break;
2488 default:
2489 err = -EINVAL;
2490 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2491 __func__, resp);
2492 break;
2493 }
2494
2495 return err;
2496}
2497
2498static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2499 struct ufshcd_lrb *lrbp, int max_timeout)
2500{
2501 int err = 0;
2502 unsigned long time_left;
2503 unsigned long flags;
2504
2505 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2506 msecs_to_jiffies(max_timeout));
2507
ad1a1b9c
GB		 2508 /* Make sure descriptors are ready before ringing the doorbell */
2509 wmb();
5a0b0cb9
SRT		 2510 spin_lock_irqsave(hba->host->host_lock, flags);
2511 hba->dev_cmd.complete = NULL;
2512 if (likely(time_left)) {
2513 err = ufshcd_get_tr_ocs(lrbp);
2514 if (!err)
2515 err = ufshcd_dev_cmd_completion(hba, lrbp);
2516 }
2517 spin_unlock_irqrestore(hba->host->host_lock, flags);
2518
2519 if (!time_left) {
2520 err = -ETIMEDOUT;
a48353f6
YG		 2521 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2522 __func__, lrbp->task_tag);
5a0b0cb9 2523 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2524 /* successfully cleared the command, retry if needed */
5a0b0cb9 2525 err = -EAGAIN;
a48353f6
YG		 2526 /*
2527 * in case of an error, after clearing the doorbell,
2528 * we also need to clear the outstanding_request
2529 * field in hba
2530 */
2531 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2532 }
2533
2534 return err;
2535}
2536
2537/**
2538 * ufshcd_get_dev_cmd_tag - Get device management command tag
2539 * @hba: per-adapter instance
2540 * @tag: pointer to variable with available slot value
2541 *
2542 * Get a free slot and lock it until device management command
2543 * completes.
2544 *
2545 * Returns false if free slot is unavailable for locking, else
2546 * return true with tag value in @tag.
2547 */
2548static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2549{
2550 int tag;
2551 bool ret = false;
2552 unsigned long tmp;
2553
2554 if (!tag_out)
2555 goto out;
2556
2557 do {
2558 tmp = ~hba->lrb_in_use;
2559 tag = find_last_bit(&tmp, hba->nutrs);
2560 if (tag >= hba->nutrs)
2561 goto out;
2562 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2563
2564 *tag_out = tag;
2565 ret = true;
2566out:
2567 return ret;
2568}
2569
2570static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2571{
2572 clear_bit_unlock(tag, &hba->lrb_in_use);
2573}
2574
2575/**
2576 * ufshcd_exec_dev_cmd - API for sending device management requests
2577 * @hba - UFS hba
2578 * @cmd_type - specifies the type (NOP, Query...)
2579 * @timeout - time in seconds
2580 *
68078d5c
DR		 2581 * NOTE: Since there is only one available tag for device management commands,
2582 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2583 */
2584static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2585 enum dev_cmd_type cmd_type, int timeout)
2586{
2587 struct ufshcd_lrb *lrbp;
2588 int err;
2589 int tag;
2590 struct completion wait;
2591 unsigned long flags;
2592
a3cd5ec5
SJ		 2593 down_read(&hba->clk_scaling_lock);
2594
5a0b0cb9
SRT		 2595 /*
2596 * Get free slot, sleep if slots are unavailable.
2597 * Even though we use wait_event() which sleeps indefinitely,
2598 * the maximum wait time is bounded by SCSI request timeout.
2599 */
2600 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2601
2602 init_completion(&wait);
2603 lrbp = &hba->lrb[tag];
2604 WARN_ON(lrbp->cmd);
2605 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2606 if (unlikely(err))
2607 goto out_put_tag;
2608
2609 hba->dev_cmd.complete = &wait;
2610
e3dfdc53
YG		 2611 /* Make sure descriptors are ready before ringing the doorbell */
2612 wmb();
5a0b0cb9 2613 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2614 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 2615 ufshcd_send_command(hba, tag);
2616 spin_unlock_irqrestore(hba->host->host_lock, flags);
2617
2618 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2619
2620out_put_tag:
2621 ufshcd_put_dev_cmd_tag(hba, tag);
2622 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2623 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2624 return err;
2625}
2626
d44a5f98
DR		 2627/**
2628 * ufshcd_init_query() - init the query response and request parameters
2629 * @hba: per-adapter instance
2630 * @request: address of the request pointer to be initialized
2631 * @response: address of the response pointer to be initialized
2632 * @opcode: operation to perform
2633 * @idn: flag idn to access
2634 * @index: LU number to access
2635 * @selector: query/flag/descriptor further identification
2636 */
2637static inline void ufshcd_init_query(struct ufs_hba *hba,
2638 struct ufs_query_req **request, struct ufs_query_res **response,
2639 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2640{
2641 *request = &hba->dev_cmd.query.request;
2642 *response = &hba->dev_cmd.query.response;
2643 memset(*request, 0, sizeof(struct ufs_query_req));
2644 memset(*response, 0, sizeof(struct ufs_query_res));
2645 (*request)->upiu_req.opcode = opcode;
2646 (*request)->upiu_req.idn = idn;
2647 (*request)->upiu_req.index = index;
2648 (*request)->upiu_req.selector = selector;
2649}
2650
dc3c8d3a
YG		 2651static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2652 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2653{
2654 int ret;
2655 int retries;
2656
2657 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2658 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2659 if (ret)
2660 dev_dbg(hba->dev,
2661 "%s: failed with error %d, retries %d\n",
2662 __func__, ret, retries);
2663 else
2664 break;
2665 }
2666
2667 if (ret)
2668 dev_err(hba->dev,
2669 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2670 __func__, opcode, idn, ret, retries);
2671 return ret;
2672}
2673
68078d5c
DR		 2674/**
2675 * ufshcd_query_flag() - API function for sending flag query requests
2676 * hba: per-adapter instance
2677 * query_opcode: flag query to perform
2678 * idn: flag idn to access
2679 * flag_res: the flag value after the query request completes
2680 *
2681 * Returns 0 for success, non-zero in case of failure
2682 */
dc3c8d3a 2683int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2684 enum flag_idn idn, bool *flag_res)
2685{
d44a5f98
DR		 2686 struct ufs_query_req *request = NULL;
2687 struct ufs_query_res *response = NULL;
2688 int err, index = 0, selector = 0;
e5ad406c 2689 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2690
2691 BUG_ON(!hba);
2692
1ab27c9c 2693 ufshcd_hold(hba, false);
68078d5c 2694 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2695 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2696 selector);
68078d5c
DR		 2697
2698 switch (opcode) {
2699 case UPIU_QUERY_OPCODE_SET_FLAG:
2700 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2701 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2702 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2703 break;
2704 case UPIU_QUERY_OPCODE_READ_FLAG:
2705 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2706 if (!flag_res) {
2707 /* No dummy reads */
2708 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2709 __func__);
2710 err = -EINVAL;
2711 goto out_unlock;
2712 }
2713 break;
2714 default:
2715 dev_err(hba->dev,
2716 "%s: Expected query flag opcode but got = %d\n",
2717 __func__, opcode);
2718 err = -EINVAL;
2719 goto out_unlock;
2720 }
68078d5c 2721
e5ad406c 2722 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2723
2724 if (err) {
2725 dev_err(hba->dev,
2726 "%s: Sending flag query for idn %d failed, err = %d\n",
2727 __func__, idn, err);
2728 goto out_unlock;
2729 }
2730
2731 if (flag_res)
e8c8e82a 2732 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2733 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2734
2735out_unlock:
2736 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2737 ufshcd_release(hba);
68078d5c
DR		 2738 return err;
2739}
2740
66ec6d59
SRT		 2741/**
2742 * ufshcd_query_attr - API function for sending attribute requests
2743 * hba: per-adapter instance
2744 * opcode: attribute opcode
2745 * idn: attribute idn to access
2746 * index: index field
2747 * selector: selector field
2748 * attr_val: the attribute value after the query request completes
2749 *
2750 * Returns 0 for success, non-zero in case of failure
2751*/
bdbe5d2f 2752static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 2753 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2754{
d44a5f98
DR		 2755 struct ufs_query_req *request = NULL;
2756 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2757 int err;
2758
2759 BUG_ON(!hba);
2760
1ab27c9c 2761 ufshcd_hold(hba, false);
66ec6d59
SRT		 2762 if (!attr_val) {
2763 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2764 __func__, opcode);
2765 err = -EINVAL;
2766 goto out;
2767 }
2768
2769 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2770 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2771 selector);
66ec6d59
SRT		 2772
2773 switch (opcode) {
2774 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2775 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2776 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2777 break;
2778 case UPIU_QUERY_OPCODE_READ_ATTR:
2779 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2780 break;
2781 default:
2782 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2783 __func__, opcode);
2784 err = -EINVAL;
2785 goto out_unlock;
2786 }
2787
d44a5f98 2788 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2789
2790 if (err) {
4b761b58
YG		 2791 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2792 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2793 goto out_unlock;
2794 }
2795
e8c8e82a 2796 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2797
2798out_unlock:
2799 mutex_unlock(&hba->dev_cmd.lock);
2800out:
1ab27c9c 2801 ufshcd_release(hba);
66ec6d59
SRT		 2802 return err;
2803}
2804
5e86ae44
YG		 2805/**
2806 * ufshcd_query_attr_retry() - API function for sending query
2807 * attribute with retries
2808 * @hba: per-adapter instance
2809 * @opcode: attribute opcode
2810 * @idn: attribute idn to access
2811 * @index: index field
2812 * @selector: selector field
2813 * @attr_val: the attribute value after the query request
2814 * completes
2815 *
2816 * Returns 0 for success, non-zero in case of failure
2817*/
2818static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2819 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2820 u32 *attr_val)
2821{
2822 int ret = 0;
2823 u32 retries;
2824
2825 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2826 ret = ufshcd_query_attr(hba, opcode, idn, index,
2827 selector, attr_val);
2828 if (ret)
2829 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2830 __func__, ret, retries);
2831 else
2832 break;
2833 }
2834
2835 if (ret)
2836 dev_err(hba->dev,
2837 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2838 __func__, idn, ret, QUERY_REQ_RETRIES);
2839 return ret;
2840}
2841
a70e91b8 2842static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2843 enum query_opcode opcode, enum desc_idn idn, u8 index,
2844 u8 selector, u8 *desc_buf, int *buf_len)
2845{
2846 struct ufs_query_req *request = NULL;
2847 struct ufs_query_res *response = NULL;
2848 int err;
2849
2850 BUG_ON(!hba);
2851
1ab27c9c 2852 ufshcd_hold(hba, false);
d44a5f98
DR		 2853 if (!desc_buf) {
2854 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2855 __func__, opcode);
2856 err = -EINVAL;
2857 goto out;
2858 }
2859
2860 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
2861 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2862 __func__, *buf_len);
2863 err = -EINVAL;
2864 goto out;
2865 }
2866
2867 mutex_lock(&hba->dev_cmd.lock);
2868 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2869 selector);
2870 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2871 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2872
2873 switch (opcode) {
2874 case UPIU_QUERY_OPCODE_WRITE_DESC:
2875 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2876 break;
2877 case UPIU_QUERY_OPCODE_READ_DESC:
2878 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2879 break;
2880 default:
2881 dev_err(hba->dev,
2882 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2883 __func__, opcode);
2884 err = -EINVAL;
2885 goto out_unlock;
2886 }
2887
2888 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2889
2890 if (err) {
4b761b58
YG		 2891 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2892 __func__, opcode, idn, index, err);
d44a5f98
DR		 2893 goto out_unlock;
2894 }
2895
2896 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2897 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2898
2899out_unlock:
2900 mutex_unlock(&hba->dev_cmd.lock);
2901out:
1ab27c9c 2902 ufshcd_release(hba);
d44a5f98
DR		 2903 return err;
2904}
2905
a70e91b8
YG		 2906/**
2907 * ufshcd_query_descriptor_retry - API function for sending descriptor
2908 * requests
2909 * hba: per-adapter instance
2910 * opcode: attribute opcode
2911 * idn: attribute idn to access
2912 * index: index field
2913 * selector: selector field
2914 * desc_buf: the buffer that contains the descriptor
2915 * buf_len: length parameter passed to the device
2916 *
2917 * Returns 0 for success, non-zero in case of failure.
2918 * The buf_len parameter will contain, on return, the length parameter
2919 * received on the response.
2920 */
26cf9155
TW		 2921static int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2922 enum query_opcode opcode,
2923 enum desc_idn idn, u8 index,
2924 u8 selector,
2925 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 2926{
2927 int err;
2928 int retries;
2929
2930 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2931 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2932 selector, desc_buf, buf_len);
2933 if (!err || err == -EINVAL)
2934 break;
2935 }
2936
2937 return err;
2938}
a70e91b8 2939
da461cec
SJ		 2940/**
2941 * ufshcd_read_desc_param - read the specified descriptor parameter
2942 * @hba: Pointer to adapter instance
2943 * @desc_id: descriptor idn value
2944 * @desc_index: descriptor index
2945 * @param_offset: offset of the parameter to read
2946 * @param_read_buf: pointer to buffer where parameter would be read
2947 * @param_size: sizeof(param_read_buf)
2948 *
2949 * Return 0 in case of success, non-zero otherwise
2950 */
2951static int ufshcd_read_desc_param(struct ufs_hba *hba,
2952 enum desc_idn desc_id,
2953 int desc_index,
2954 u32 param_offset,
2955 u8 *param_read_buf,
2956 u32 param_size)
2957{
2958 int ret;
2959 u8 *desc_buf;
2960 u32 buff_len;
2961 bool is_kmalloc = true;
2962
2963 /* safety checks */
2964 if (desc_id >= QUERY_DESC_IDN_MAX)
2965 return -EINVAL;
2966
2967 buff_len = ufs_query_desc_max_size[desc_id];
2968 if ((param_offset + param_size) > buff_len)
2969 return -EINVAL;
2970
2971 if (!param_offset && (param_size == buff_len)) {
2972 /* memory space already available to hold full descriptor */
2973 desc_buf = param_read_buf;
2974 is_kmalloc = false;
2975 } else {
2976 /* allocate memory to hold full descriptor */
2977 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2978 if (!desc_buf)
2979 return -ENOMEM;
2980 }
2981
a70e91b8
YG		 2982 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2983 desc_id, desc_index, 0, desc_buf,
2984 &buff_len);
da461cec 2985
bde44bb6
SJ		 2986 if (ret) {
2987 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
2988 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 2989
2990 goto out;
2991 }
2992
bde44bb6
SJ		 2993 /* Sanity check */
2994 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
2995 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
2996 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
2997 ret = -EINVAL;
2998 goto out;
2999 }
3000
3001 /*
3002 * While reading variable size descriptors (like string descriptor),
3003 * some UFS devices may report the "LENGTH" (field in "Transaction
3004 * Specific fields" of Query Response UPIU) same as what was requested
3005 * in Query Request UPIU instead of reporting the actual size of the
3006 * variable size descriptor.
3007 * Although it's safe to ignore the "LENGTH" field for variable size
3008 * descriptors as we can always derive the length of the descriptor from
3009 * the descriptor header fields. Hence this change impose the length
3010 * match check only for fixed size descriptors (for which we always
3011 * request the correct size as part of Query Request UPIU).
3012 */
3013 if ((desc_id != QUERY_DESC_IDN_STRING) &&
3014 (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) {
3015 dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d",
3016 __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]);
3017 ret = -EINVAL;
3018 goto out;
3019 }
3020
da461cec
SJ		 3021 if (is_kmalloc)
3022 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3023out:
3024 if (is_kmalloc)
3025 kfree(desc_buf);
3026 return ret;
3027}
3028
3029static inline int ufshcd_read_desc(struct ufs_hba *hba,
3030 enum desc_idn desc_id,
3031 int desc_index,
3032 u8 *buf,
3033 u32 size)
3034{
3035 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3036}
3037
3038static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3039 u8 *buf,
3040 u32 size)
3041{
61e07359
DR		 3042 int err = 0;
3043 int retries;
3044
3045 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3046 /* Read descriptor*/
3047 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
3048 if (!err)
3049 break;
3050 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3051 }
3052
3053 return err;
da461cec
SJ		 3054}
3055
8209b6d5 3056static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3057{
3058 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3059}
b573d484
YG		 3060
3061/**
3062 * ufshcd_read_string_desc - read string descriptor
3063 * @hba: pointer to adapter instance
3064 * @desc_index: descriptor index
3065 * @buf: pointer to buffer where descriptor would be read
3066 * @size: size of buf
3067 * @ascii: if true convert from unicode to ascii characters
3068 *
3069 * Return 0 in case of success, non-zero otherwise
3070 */
8209b6d5
TW		 3071#define ASCII_STD true
3072static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3073 u8 *buf, u32 size, bool ascii)
b573d484
YG		 3074{
3075 int err = 0;
3076
3077 err = ufshcd_read_desc(hba,
3078 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3079
3080 if (err) {
3081 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3082 __func__, QUERY_REQ_RETRIES, err);
3083 goto out;
3084 }
3085
3086 if (ascii) {
3087 int desc_len;
3088 int ascii_len;
3089 int i;
3090 char *buff_ascii;
3091
3092 desc_len = buf[0];
3093 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3094 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3095 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3096 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3097 __func__);
3098 err = -ENOMEM;
3099 goto out;
3100 }
3101
3102 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3103 if (!buff_ascii) {
3104 err = -ENOMEM;
fcbefc3b 3105 goto out;
b573d484
YG		 3106 }
3107
3108 /*
3109 * the descriptor contains string in UTF16 format
3110 * we need to convert to utf-8 so it can be displayed
3111 */
3112 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3113 desc_len - QUERY_DESC_HDR_SIZE,
3114 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3115
3116 /* replace non-printable or non-ASCII characters with spaces */
3117 for (i = 0; i < ascii_len; i++)
3118 ufshcd_remove_non_printable(&buff_ascii[i]);
3119
3120 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3121 size - QUERY_DESC_HDR_SIZE);
3122 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3123 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 3124 kfree(buff_ascii);
3125 }
3126out:
3127 return err;
3128}
b573d484 3129
da461cec
SJ		 3130/**
3131 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3132 * @hba: Pointer to adapter instance
3133 * @lun: lun id
3134 * @param_offset: offset of the parameter to read
3135 * @param_read_buf: pointer to buffer where parameter would be read
3136 * @param_size: sizeof(param_read_buf)
3137 *
3138 * Return 0 in case of success, non-zero otherwise
3139 */
3140static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3141 int lun,
3142 enum unit_desc_param param_offset,
3143 u8 *param_read_buf,
3144 u32 param_size)
3145{
3146 /*
3147 * Unit descriptors are only available for general purpose LUs (LUN id
3148 * from 0 to 7) and RPMB Well known LU.
3149 */
0ce147d4 3150 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 3151 return -EOPNOTSUPP;
3152
3153 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3154 param_offset, param_read_buf, param_size);
3155}
3156
7a3e97b0
SY		 3157/**
3158 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3159 * @hba: per adapter instance
3160 *
3161 * 1. Allocate DMA memory for Command Descriptor array
3162 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3163 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3164 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3165 * (UTMRDL)
3166 * 4. Allocate memory for local reference block(lrb).
3167 *
3168 * Returns 0 for success, non-zero in case of failure
3169 */
3170static int ufshcd_memory_alloc(struct ufs_hba *hba)
3171{
3172 size_t utmrdl_size, utrdl_size, ucdl_size;
3173
3174 /* Allocate memory for UTP command descriptors */
3175 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3176 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3177 ucdl_size,
3178 &hba->ucdl_dma_addr,
3179 GFP_KERNEL);
7a3e97b0
SY		 3180
3181 /*
3182 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3183 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3184 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3185 * be aligned to 128 bytes as well
3186 */
3187 if (!hba->ucdl_base_addr ||
3188 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3189 dev_err(hba->dev,
7a3e97b0
SY		 3190 "Command Descriptor Memory allocation failed\n");
3191 goto out;
3192 }
3193
3194 /*
3195 * Allocate memory for UTP Transfer descriptors
3196 * UFSHCI requires 1024 byte alignment of UTRD
3197 */
3198 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3199 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3200 utrdl_size,
3201 &hba->utrdl_dma_addr,
3202 GFP_KERNEL);
7a3e97b0
SY		 3203 if (!hba->utrdl_base_addr ||
3204 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3205 dev_err(hba->dev,
7a3e97b0
SY		 3206 "Transfer Descriptor Memory allocation failed\n");
3207 goto out;
3208 }
3209
3210 /*
3211 * Allocate memory for UTP Task Management descriptors
3212 * UFSHCI requires 1024 byte alignment of UTMRD
3213 */
3214 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3215 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3216 utmrdl_size,
3217 &hba->utmrdl_dma_addr,
3218 GFP_KERNEL);
7a3e97b0
SY		 3219 if (!hba->utmrdl_base_addr ||
3220 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3221 dev_err(hba->dev,
7a3e97b0
SY		 3222 "Task Management Descriptor Memory allocation failed\n");
3223 goto out;
3224 }
3225
3226 /* Allocate memory for local reference block */
2953f850
SJ		 3227 hba->lrb = devm_kzalloc(hba->dev,
3228 hba->nutrs * sizeof(struct ufshcd_lrb),
3229 GFP_KERNEL);
7a3e97b0 3230 if (!hba->lrb) {
3b1d0580 3231 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3232 goto out;
3233 }
3234 return 0;
3235out:
7a3e97b0
SY		 3236 return -ENOMEM;
3237}
3238
3239/**
3240 * ufshcd_host_memory_configure - configure local reference block with
3241 * memory offsets
3242 * @hba: per adapter instance
3243 *
3244 * Configure Host memory space
3245 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3246 * address.
3247 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3248 * and PRDT offset.
3249 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3250 * into local reference block.
3251 */
3252static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3253{
3254 struct utp_transfer_cmd_desc *cmd_descp;
3255 struct utp_transfer_req_desc *utrdlp;
3256 dma_addr_t cmd_desc_dma_addr;
3257 dma_addr_t cmd_desc_element_addr;
3258 u16 response_offset;
3259 u16 prdt_offset;
3260 int cmd_desc_size;
3261 int i;
3262
3263 utrdlp = hba->utrdl_base_addr;
3264 cmd_descp = hba->ucdl_base_addr;
3265
3266 response_offset =
3267 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3268 prdt_offset =
3269 offsetof(struct utp_transfer_cmd_desc, prd_table);
3270
3271 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3272 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3273
3274 for (i = 0; i < hba->nutrs; i++) {
3275 /* Configure UTRD with command descriptor base address */
3276 cmd_desc_element_addr =
3277 (cmd_desc_dma_addr + (cmd_desc_size * i));
3278 utrdlp[i].command_desc_base_addr_lo =
3279 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3280 utrdlp[i].command_desc_base_addr_hi =
3281 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3282
3283 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3284 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3285 utrdlp[i].response_upiu_offset =
3286 cpu_to_le16(response_offset);
3287 utrdlp[i].prd_table_offset =
3288 cpu_to_le16(prdt_offset);
3289 utrdlp[i].response_upiu_length =
3290 cpu_to_le16(ALIGNED_UPIU_SIZE);
3291 } else {
3292 utrdlp[i].response_upiu_offset =
7a3e97b0 3293 cpu_to_le16((response_offset >> 2));
75b1cc4a 3294 utrdlp[i].prd_table_offset =
7a3e97b0 3295 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3296 utrdlp[i].response_upiu_length =
3ca316c5 3297 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3298 }
7a3e97b0
SY		 3299
3300 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3301 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3302 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3303 hba->lrb[i].ucd_req_ptr =
3304 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3305 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3306 hba->lrb[i].ucd_rsp_ptr =
3307 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3308 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3309 response_offset;
7a3e97b0
SY		 3310 hba->lrb[i].ucd_prdt_ptr =
3311 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3312 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3313 prdt_offset;
7a3e97b0
SY		 3314 }
3315}
3316
3317/**
3318 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3319 * @hba: per adapter instance
3320 *
3321 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3322 * in order to initialize the Unipro link startup procedure.
3323 * Once the Unipro links are up, the device connected to the controller
3324 * is detected.
3325 *
3326 * Returns 0 on success, non-zero value on failure
3327 */
3328static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3329{
6ccf44fe
SJ		 3330 struct uic_command uic_cmd = {0};
3331 int ret;
7a3e97b0 3332
6ccf44fe 3333 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3334
6ccf44fe
SJ		 3335 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3336 if (ret)
ff8e20c6 3337 dev_dbg(hba->dev,
6ccf44fe
SJ		 3338 "dme-link-startup: error code %d\n", ret);
3339 return ret;
7a3e97b0
SY		 3340}
3341
cad2e03d
YG		 3342static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3343{
3344 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3345 unsigned long min_sleep_time_us;
3346
3347 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3348 return;
3349
3350 /*
3351 * last_dme_cmd_tstamp will be 0 only for 1st call to
3352 * this function
3353 */
3354 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3355 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3356 } else {
3357 unsigned long delta =
3358 (unsigned long) ktime_to_us(
3359 ktime_sub(ktime_get(),
3360 hba->last_dme_cmd_tstamp));
3361
3362 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3363 min_sleep_time_us =
3364 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3365 else
3366 return; /* no more delay required */
3367 }
3368
3369 /* allow sleep for extra 50us if needed */
3370 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3371}
3372
12b4fdb4
SJ		 3373/**
3374 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3375 * @hba: per adapter instance
3376 * @attr_sel: uic command argument1
3377 * @attr_set: attribute set type as uic command argument2
3378 * @mib_val: setting value as uic command argument3
3379 * @peer: indicate whether peer or local
3380 *
3381 * Returns 0 on success, non-zero value on failure
3382 */
3383int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3384 u8 attr_set, u32 mib_val, u8 peer)
3385{
3386 struct uic_command uic_cmd = {0};
3387 static const char *const action[] = {
3388 "dme-set",
3389 "dme-peer-set"
3390 };
3391 const char *set = action[!!peer];
3392 int ret;
64238fbd 3393 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3394
3395 uic_cmd.command = peer ?
3396 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3397 uic_cmd.argument1 = attr_sel;
3398 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3399 uic_cmd.argument3 = mib_val;
3400
64238fbd
YG		 3401 do {
3402 /* for peer attributes we retry upon failure */
3403 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3404 if (ret)
3405 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3406 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3407 } while (ret && peer && --retries);
3408
f37e9f8c 3409 if (ret)
64238fbd 3410 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3411 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3412 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3413
3414 return ret;
3415}
3416EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3417
3418/**
3419 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3420 * @hba: per adapter instance
3421 * @attr_sel: uic command argument1
3422 * @mib_val: the value of the attribute as returned by the UIC command
3423 * @peer: indicate whether peer or local
3424 *
3425 * Returns 0 on success, non-zero value on failure
3426 */
3427int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3428 u32 *mib_val, u8 peer)
3429{
3430 struct uic_command uic_cmd = {0};
3431 static const char *const action[] = {
3432 "dme-get",
3433 "dme-peer-get"
3434 };
3435 const char *get = action[!!peer];
3436 int ret;
64238fbd 3437 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3438 struct ufs_pa_layer_attr orig_pwr_info;
3439 struct ufs_pa_layer_attr temp_pwr_info;
3440 bool pwr_mode_change = false;
3441
3442 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3443 orig_pwr_info = hba->pwr_info;
3444 temp_pwr_info = orig_pwr_info;
3445
3446 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3447 orig_pwr_info.pwr_rx == FAST_MODE) {
3448 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3449 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3450 pwr_mode_change = true;
3451 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3452 orig_pwr_info.pwr_rx == SLOW_MODE) {
3453 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3454 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3455 pwr_mode_change = true;
3456 }
3457 if (pwr_mode_change) {
3458 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3459 if (ret)
3460 goto out;
3461 }
3462 }
12b4fdb4
SJ		 3463
3464 uic_cmd.command = peer ?
3465 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3466 uic_cmd.argument1 = attr_sel;
3467
64238fbd
YG		 3468 do {
3469 /* for peer attributes we retry upon failure */
3470 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3471 if (ret)
3472 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3473 get, UIC_GET_ATTR_ID(attr_sel), ret);
3474 } while (ret && peer && --retries);
3475
f37e9f8c 3476 if (ret)
64238fbd 3477 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3478 get, UIC_GET_ATTR_ID(attr_sel),
3479 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3480
64238fbd 3481 if (mib_val && !ret)
12b4fdb4 3482 *mib_val = uic_cmd.argument3;
874237f7
YG		 3483
3484 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3485 && pwr_mode_change)
3486 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3487out:
3488 return ret;
3489}
3490EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3491
53b3d9c3 3492/**
57d104c1
SJ		 3493 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3494 * state) and waits for it to take effect.
3495 *
53b3d9c3 3496 * @hba: per adapter instance
57d104c1
SJ		 3497 * @cmd: UIC command to execute
3498 *
3499 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3500 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3501 * and device UniPro link and hence it's final completion would be indicated by
3502 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3503 * addition to normal UIC command completion Status (UCCS). This function only
3504 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3505 *
3506 * Returns 0 on success, non-zero value on failure
3507 */
57d104c1 3508static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3509{
57d104c1 3510 struct completion uic_async_done;
53b3d9c3
SJ		 3511 unsigned long flags;
3512 u8 status;
3513 int ret;
d75f7fe4 3514 bool reenable_intr = false;
53b3d9c3 3515
53b3d9c3 3516 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3517 init_completion(&uic_async_done);
cad2e03d 3518 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3519
3520 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3521 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3522 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3523 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3524 /*
3525 * Make sure UIC command completion interrupt is disabled before
3526 * issuing UIC command.
3527 */
3528 wmb();
3529 reenable_intr = true;
57d104c1 3530 }
d75f7fe4
YG		 3531 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3532 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3533 if (ret) {
3534 dev_err(hba->dev,
3535 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3536 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3537 goto out;
3538 }
3539
57d104c1 3540 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3541 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3542 dev_err(hba->dev,
57d104c1
SJ		 3543 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3544 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3545 ret = -ETIMEDOUT;
3546 goto out;
3547 }
3548
3549 status = ufshcd_get_upmcrs(hba);
3550 if (status != PWR_LOCAL) {
3551 dev_err(hba->dev,
73615428 3552 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 3553 cmd->command, status);
53b3d9c3
SJ		 3554 ret = (status != PWR_OK) ? status : -1;
3555 }
3556out:
3557 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3558 hba->active_uic_cmd = NULL;
57d104c1 3559 hba->uic_async_done = NULL;
d75f7fe4
YG		 3560 if (reenable_intr)
3561 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3562 spin_unlock_irqrestore(hba->host->host_lock, flags);
3563 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3564
53b3d9c3
SJ		 3565 return ret;
3566}
3567
57d104c1
SJ		 3568/**
3569 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3570 * using DME_SET primitives.
3571 * @hba: per adapter instance
3572 * @mode: powr mode value
3573 *
3574 * Returns 0 on success, non-zero value on failure
3575 */
3576static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3577{
3578 struct uic_command uic_cmd = {0};
1ab27c9c 3579 int ret;
57d104c1 3580
c3a2f9ee
YG		 3581 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3582 ret = ufshcd_dme_set(hba,
3583 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3584 if (ret) {
3585 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3586 __func__, ret);
3587 goto out;
3588 }
3589 }
3590
57d104c1
SJ		 3591 uic_cmd.command = UIC_CMD_DME_SET;
3592 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3593 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3594 ufshcd_hold(hba, false);
3595 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3596 ufshcd_release(hba);
57d104c1 3597
c3a2f9ee 3598out:
1ab27c9c 3599 return ret;
57d104c1
SJ		 3600}
3601
53c12d0e
YG		 3602static int ufshcd_link_recovery(struct ufs_hba *hba)
3603{
3604 int ret;
3605 unsigned long flags;
3606
3607 spin_lock_irqsave(hba->host->host_lock, flags);
3608 hba->ufshcd_state = UFSHCD_STATE_RESET;
3609 ufshcd_set_eh_in_progress(hba);
3610 spin_unlock_irqrestore(hba->host->host_lock, flags);
3611
3612 ret = ufshcd_host_reset_and_restore(hba);
3613
3614 spin_lock_irqsave(hba->host->host_lock, flags);
3615 if (ret)
3616 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3617 ufshcd_clear_eh_in_progress(hba);
3618 spin_unlock_irqrestore(hba->host->host_lock, flags);
3619
3620 if (ret)
3621 dev_err(hba->dev, "%s: link recovery failed, err %d",
3622 __func__, ret);
3623
3624 return ret;
3625}
3626
87d0b4a6 3627static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3628{
87d0b4a6 3629 int ret;
57d104c1 3630 struct uic_command uic_cmd = {0};
911a0771 3631 ktime_t start = ktime_get();
57d104c1 3632
ee32c909
KK		 3633 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3634
57d104c1 3635 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3636 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3637 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3638 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3639
53c12d0e 3640 if (ret) {
87d0b4a6
YG		 3641 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3642 __func__, ret);
3643
53c12d0e
YG		 3644 /*
3645 * If link recovery fails then return error so that caller
3646 * don't retry the hibern8 enter again.
3647 */
3648 if (ufshcd_link_recovery(hba))
3649 ret = -ENOLINK;
ee32c909
KK		 3650 } else
3651 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3652 POST_CHANGE);
53c12d0e 3653
87d0b4a6
YG		 3654 return ret;
3655}
3656
3657static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3658{
3659 int ret = 0, retries;
57d104c1 3660
87d0b4a6
YG		 3661 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3662 ret = __ufshcd_uic_hibern8_enter(hba);
3663 if (!ret || ret == -ENOLINK)
3664 goto out;
3665 }
3666out:
3667 return ret;
57d104c1
SJ		 3668}
3669
3670static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3671{
3672 struct uic_command uic_cmd = {0};
3673 int ret;
911a0771 3674 ktime_t start = ktime_get();
57d104c1 3675
ee32c909
KK		 3676 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3677
57d104c1
SJ		 3678 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3679 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3680 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3681 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3682
57d104c1 3683 if (ret) {
53c12d0e
YG		 3684 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3685 __func__, ret);
3686 ret = ufshcd_link_recovery(hba);
ff8e20c6 3687 } else {
ee32c909
KK		 3688 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3689 POST_CHANGE);
ff8e20c6
DR		 3690 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3691 hba->ufs_stats.hibern8_exit_cnt++;
3692 }
57d104c1
SJ		 3693
3694 return ret;
3695}
3696
5064636c
YG		 3697 /**
3698 * ufshcd_init_pwr_info - setting the POR (power on reset)
3699 * values in hba power info
3700 * @hba: per-adapter instance
3701 */
3702static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3703{
3704 hba->pwr_info.gear_rx = UFS_PWM_G1;
3705 hba->pwr_info.gear_tx = UFS_PWM_G1;
3706 hba->pwr_info.lane_rx = 1;
3707 hba->pwr_info.lane_tx = 1;
3708 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3709 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3710 hba->pwr_info.hs_rate = 0;
3711}
3712
d3e89bac 3713/**
7eb584db
DR		 3714 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3715 * @hba: per-adapter instance
d3e89bac 3716 */
7eb584db 3717static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3718{
7eb584db
DR		 3719 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3720
3721 if (hba->max_pwr_info.is_valid)
3722 return 0;
3723
2349b533
SJ		 3724 pwr_info->pwr_tx = FAST_MODE;
3725 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3726 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3727
3728 /* Get the connected lane count */
7eb584db
DR		 3729 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3730 &pwr_info->lane_rx);
3731 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3732 &pwr_info->lane_tx);
3733
3734 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3735 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3736 __func__,
3737 pwr_info->lane_rx,
3738 pwr_info->lane_tx);
3739 return -EINVAL;
3740 }
d3e89bac
SJ		 3741
3742 /*
3743 * First, get the maximum gears of HS speed.
3744 * If a zero value, it means there is no HSGEAR capability.
3745 * Then, get the maximum gears of PWM speed.
3746 */
7eb584db
DR		 3747 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3748 if (!pwr_info->gear_rx) {
3749 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3750 &pwr_info->gear_rx);
3751 if (!pwr_info->gear_rx) {
3752 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3753 __func__, pwr_info->gear_rx);
3754 return -EINVAL;
3755 }
2349b533 3756 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3757 }
3758
7eb584db
DR		 3759 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3760 &pwr_info->gear_tx);
3761 if (!pwr_info->gear_tx) {
d3e89bac 3762 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3763 &pwr_info->gear_tx);
3764 if (!pwr_info->gear_tx) {
3765 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3766 __func__, pwr_info->gear_tx);
3767 return -EINVAL;
3768 }
2349b533 3769 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3770 }
3771
3772 hba->max_pwr_info.is_valid = true;
3773 return 0;
3774}
3775
3776static int ufshcd_change_power_mode(struct ufs_hba *hba,
3777 struct ufs_pa_layer_attr *pwr_mode)
3778{
3779 int ret;
3780
3781 /* if already configured to the requested pwr_mode */
3782 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3783 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3784 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3785 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
3786 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
3787 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
3788 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
3789 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
3790 return 0;
d3e89bac
SJ		 3791 }
3792
3793 /*
3794 * Configure attributes for power mode change with below.
3795 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
3796 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
3797 * - PA_HSSERIES
3798 */
7eb584db
DR		 3799 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
3800 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
3801 pwr_mode->lane_rx);
3802 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3803 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 3804 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 3805 else
3806 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 3807
7eb584db
DR		 3808 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
3809 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
3810 pwr_mode->lane_tx);
3811 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
3812 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 3813 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 3814 else
3815 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 3816
7eb584db
DR		 3817 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3818 pwr_mode->pwr_tx == FASTAUTO_MODE ||
3819 pwr_mode->pwr_rx == FAST_MODE ||
3820 pwr_mode->pwr_tx == FAST_MODE)
3821 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
3822 pwr_mode->hs_rate);
d3e89bac 3823
7eb584db
DR		 3824 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
3825 | pwr_mode->pwr_tx);
3826
3827 if (ret) {
d3e89bac 3828 dev_err(hba->dev,
7eb584db
DR		 3829 "%s: power mode change failed %d\n", __func__, ret);
3830 } else {
0263bcd0
YG		 3831 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
3832 pwr_mode);
7eb584db
DR		 3833
3834 memcpy(&hba->pwr_info, pwr_mode,
3835 sizeof(struct ufs_pa_layer_attr));
3836 }
3837
3838 return ret;
3839}
3840
3841/**
3842 * ufshcd_config_pwr_mode - configure a new power mode
3843 * @hba: per-adapter instance
3844 * @desired_pwr_mode: desired power configuration
3845 */
3846static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
3847 struct ufs_pa_layer_attr *desired_pwr_mode)
3848{
3849 struct ufs_pa_layer_attr final_params = { 0 };
3850 int ret;
3851
0263bcd0
YG		 3852 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
3853 desired_pwr_mode, &final_params);
3854
3855 if (ret)
7eb584db
DR		 3856 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
3857
3858 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5
SJ		 3859 if (!ret)
3860 ufshcd_print_pwr_info(hba);
d3e89bac
SJ		 3861
3862 return ret;
3863}
3864
68078d5c
DR		 3865/**
3866 * ufshcd_complete_dev_init() - checks device readiness
3867 * hba: per-adapter instance
3868 *
3869 * Set fDeviceInit flag and poll until device toggles it.
3870 */
3871static int ufshcd_complete_dev_init(struct ufs_hba *hba)
3872{
dc3c8d3a
YG		 3873 int i;
3874 int err;
68078d5c
DR		 3875 bool flag_res = 1;
3876
dc3c8d3a
YG		 3877 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3878 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 3879 if (err) {
3880 dev_err(hba->dev,
3881 "%s setting fDeviceInit flag failed with error %d\n",
3882 __func__, err);
3883 goto out;
3884 }
3885
dc3c8d3a
YG		 3886 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
3887 for (i = 0; i < 1000 && !err && flag_res; i++)
3888 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
3889 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
3890
68078d5c
DR		 3891 if (err)
3892 dev_err(hba->dev,
3893 "%s reading fDeviceInit flag failed with error %d\n",
3894 __func__, err);
3895 else if (flag_res)
3896 dev_err(hba->dev,
3897 "%s fDeviceInit was not cleared by the device\n",
3898 __func__);
3899
3900out:
3901 return err;
3902}
3903
7a3e97b0
SY		 3904/**
3905 * ufshcd_make_hba_operational - Make UFS controller operational
3906 * @hba: per adapter instance
3907 *
3908 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 3909 * 1. Enable required interrupts
3910 * 2. Configure interrupt aggregation
897efe62 3911 * 3. Program UTRL and UTMRL base address
5c0c28a8 3912 * 4. Configure run-stop-registers
7a3e97b0
SY		 3913 *
3914 * Returns 0 on success, non-zero value on failure
3915 */
3916static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3917{
3918 int err = 0;
3919 u32 reg;
3920
6ccf44fe
SJ		 3921 /* Enable required interrupts */
3922 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3923
3924 /* Configure interrupt aggregation */
b852190e
YG		 3925 if (ufshcd_is_intr_aggr_allowed(hba))
3926 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3927 else
3928 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 3929
3930 /* Configure UTRL and UTMRL base address registers */
3931 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3932 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3933 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3934 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3935 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3936 REG_UTP_TASK_REQ_LIST_BASE_L);
3937 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3938 REG_UTP_TASK_REQ_LIST_BASE_H);
3939
897efe62
YG		 3940 /*
3941 * Make sure base address and interrupt setup are updated before
3942 * enabling the run/stop registers below.
3943 */
3944 wmb();
3945
7a3e97b0
SY		 3946 /*
3947 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 3948 */
5c0c28a8 3949 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 3950 if (!(ufshcd_get_lists_status(reg))) {
3951 ufshcd_enable_run_stop_reg(hba);
3952 } else {
3b1d0580 3953 dev_err(hba->dev,
7a3e97b0
SY		 3954 "Host controller not ready to process requests");
3955 err = -EIO;
3956 goto out;
3957 }
3958
7a3e97b0
SY		 3959out:
3960 return err;
3961}
3962
596585a2
YG		 3963/**
3964 * ufshcd_hba_stop - Send controller to reset state
3965 * @hba: per adapter instance
3966 * @can_sleep: perform sleep or just spin
3967 */
3968static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3969{
3970 int err;
3971
3972 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3973 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3974 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3975 10, 1, can_sleep);
3976 if (err)
3977 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3978}
3979
7a3e97b0
SY		 3980/**
3981 * ufshcd_hba_enable - initialize the controller
3982 * @hba: per adapter instance
3983 *
3984 * The controller resets itself and controller firmware initialization
3985 * sequence kicks off. When controller is ready it will set
3986 * the Host Controller Enable bit to 1.
3987 *
3988 * Returns 0 on success, non-zero value on failure
3989 */
3990static int ufshcd_hba_enable(struct ufs_hba *hba)
3991{
3992 int retry;
3993
3994 /*
3995 * msleep of 1 and 5 used in this function might result in msleep(20),
3996 * but it was necessary to send the UFS FPGA to reset mode during
3997 * development and testing of this driver. msleep can be changed to
3998 * mdelay and retry count can be reduced based on the controller.
3999 */
596585a2 4000 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4001 /* change controller state to "reset state" */
596585a2 4002 ufshcd_hba_stop(hba, true);
7a3e97b0 4003
57d104c1
SJ		 4004 /* UniPro link is disabled at this point */
4005 ufshcd_set_link_off(hba);
4006
0263bcd0 4007 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4008
7a3e97b0
SY		 4009 /* start controller initialization sequence */
4010 ufshcd_hba_start(hba);
4011
4012 /*
4013 * To initialize a UFS host controller HCE bit must be set to 1.
4014 * During initialization the HCE bit value changes from 1->0->1.
4015 * When the host controller completes initialization sequence
4016 * it sets the value of HCE bit to 1. The same HCE bit is read back
4017 * to check if the controller has completed initialization sequence.
4018 * So without this delay the value HCE = 1, set in the previous
4019 * instruction might be read back.
4020 * This delay can be changed based on the controller.
4021 */
4022 msleep(1);
4023
4024 /* wait for the host controller to complete initialization */
4025 retry = 10;
4026 while (ufshcd_is_hba_active(hba)) {
4027 if (retry) {
4028 retry--;
4029 } else {
3b1d0580 4030 dev_err(hba->dev,
7a3e97b0
SY		 4031 "Controller enable failed\n");
4032 return -EIO;
4033 }
4034 msleep(5);
4035 }
5c0c28a8 4036
1d337ec2 4037 /* enable UIC related interrupts */
57d104c1 4038 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4039
0263bcd0 4040 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4041
7a3e97b0
SY		 4042 return 0;
4043}
4044
7ca38cf3
YG		 4045static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4046{
4047 int tx_lanes, i, err = 0;
4048
4049 if (!peer)
4050 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4051 &tx_lanes);
4052 else
4053 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4054 &tx_lanes);
4055 for (i = 0; i < tx_lanes; i++) {
4056 if (!peer)
4057 err = ufshcd_dme_set(hba,
4058 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4059 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4060 0);
4061 else
4062 err = ufshcd_dme_peer_set(hba,
4063 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4064 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4065 0);
4066 if (err) {
4067 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4068 __func__, peer, i, err);
4069 break;
4070 }
4071 }
4072
4073 return err;
4074}
4075
4076static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4077{
4078 return ufshcd_disable_tx_lcc(hba, true);
4079}
4080
7a3e97b0 4081/**
6ccf44fe 4082 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4083 * @hba: per adapter instance
4084 *
6ccf44fe 4085 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4086 */
6ccf44fe 4087static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4088{
6ccf44fe 4089 int ret;
1d337ec2 4090 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4091 bool link_startup_again = false;
7a3e97b0 4092
7caf489b
SJ		 4093 /*
4094 * If UFS device isn't active then we will have to issue link startup
4095 * 2 times to make sure the device state move to active.
4096 */
4097 if (!ufshcd_is_ufs_dev_active(hba))
4098 link_startup_again = true;
7a3e97b0 4099
7caf489b 4100link_startup:
1d337ec2 4101 do {
0263bcd0 4102 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4103
1d337ec2 4104 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4105
1d337ec2
SRT		 4106 /* check if device is detected by inter-connect layer */
4107 if (!ret && !ufshcd_is_device_present(hba)) {
4108 dev_err(hba->dev, "%s: Device not present\n", __func__);
4109 ret = -ENXIO;
4110 goto out;
4111 }
6ccf44fe 4112
1d337ec2
SRT		 4113 /*
4114 * DME link lost indication is only received when link is up,
4115 * but we can't be sure if the link is up until link startup
4116 * succeeds. So reset the local Uni-Pro and try again.
4117 */
4118 if (ret && ufshcd_hba_enable(hba))
4119 goto out;
4120 } while (ret && retries--);
4121
4122 if (ret)
4123 /* failed to get the link up... retire */
5c0c28a8 4124 goto out;
5c0c28a8 4125
7caf489b
SJ		 4126 if (link_startup_again) {
4127 link_startup_again = false;
4128 retries = DME_LINKSTARTUP_RETRIES;
4129 goto link_startup;
4130 }
4131
d2aebb9b
SJ		 4132 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4133 ufshcd_init_pwr_info(hba);
4134 ufshcd_print_pwr_info(hba);
4135
7ca38cf3
YG		 4136 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4137 ret = ufshcd_disable_device_tx_lcc(hba);
4138 if (ret)
4139 goto out;
4140 }
4141
5c0c28a8 4142 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4143 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4144 if (ret)
4145 goto out;
7a3e97b0 4146
5c0c28a8 4147 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 4148out:
4149 if (ret)
4150 dev_err(hba->dev, "link startup failed %d\n", ret);
4151 return ret;
7a3e97b0
SY		 4152}
4153
5a0b0cb9
SRT		 4154/**
4155 * ufshcd_verify_dev_init() - Verify device initialization
4156 * @hba: per-adapter instance
4157 *
4158 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4159 * device Transport Protocol (UTP) layer is ready after a reset.
4160 * If the UTP layer at the device side is not initialized, it may
4161 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4162 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4163 */
4164static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4165{
4166 int err = 0;
4167 int retries;
4168
1ab27c9c 4169 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4170 mutex_lock(&hba->dev_cmd.lock);
4171 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4172 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4173 NOP_OUT_TIMEOUT);
4174
4175 if (!err || err == -ETIMEDOUT)
4176 break;
4177
4178 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4179 }
4180 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4181 ufshcd_release(hba);
5a0b0cb9
SRT		 4182
4183 if (err)
4184 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4185 return err;
4186}
4187
0ce147d4
SJ		 4188/**
4189 * ufshcd_set_queue_depth - set lun queue depth
4190 * @sdev: pointer to SCSI device
4191 *
4192 * Read bLUQueueDepth value and activate scsi tagged command
4193 * queueing. For WLUN, queue depth is set to 1. For best-effort
4194 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4195 * value that host can queue.
4196 */
4197static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4198{
4199 int ret = 0;
4200 u8 lun_qdepth;
61e07359 4201 int retries;
0ce147d4
SJ		 4202 struct ufs_hba *hba;
4203
4204 hba = shost_priv(sdev->host);
4205
4206 lun_qdepth = hba->nutrs;
61e07359
DR		 4207 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
4208 /* Read descriptor*/
4209 ret = ufshcd_read_unit_desc_param(hba,
4210 ufshcd_scsi_to_upiu_lun(sdev->lun),
4211 UNIT_DESC_PARAM_LU_Q_DEPTH,
4212 &lun_qdepth,
4213 sizeof(lun_qdepth));
4214 if (!ret || ret == -ENOTSUPP)
4215 break;
4216
4217 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, ret);
4218 }
0ce147d4
SJ		 4219
4220 /* Some WLUN doesn't support unit descriptor */
4221 if (ret == -EOPNOTSUPP)
4222 lun_qdepth = 1;
4223 else if (!lun_qdepth)
4224 /* eventually, we can figure out the real queue depth */
4225 lun_qdepth = hba->nutrs;
4226 else
4227 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4228
4229 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4230 __func__, lun_qdepth);
db5ed4df 4231 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4232}
4233
57d104c1
SJ		 4234/*
4235 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4236 * @hba: per-adapter instance
4237 * @lun: UFS device lun id
4238 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4239 *
4240 * Returns 0 in case of success and b_lu_write_protect status would be returned
4241 * @b_lu_write_protect parameter.
4242 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4243 * Returns -EINVAL in case of invalid parameters passed to this function.
4244 */
4245static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4246 u8 lun,
4247 u8 *b_lu_write_protect)
4248{
4249 int ret;
4250
4251 if (!b_lu_write_protect)
4252 ret = -EINVAL;
4253 /*
4254 * According to UFS device spec, RPMB LU can't be write
4255 * protected so skip reading bLUWriteProtect parameter for
4256 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4257 */
4258 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4259 ret = -ENOTSUPP;
4260 else
4261 ret = ufshcd_read_unit_desc_param(hba,
4262 lun,
4263 UNIT_DESC_PARAM_LU_WR_PROTECT,
4264 b_lu_write_protect,
4265 sizeof(*b_lu_write_protect));
4266 return ret;
4267}
4268
4269/**
4270 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4271 * status
4272 * @hba: per-adapter instance
4273 * @sdev: pointer to SCSI device
4274 *
4275 */
4276static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4277 struct scsi_device *sdev)
4278{
4279 if (hba->dev_info.f_power_on_wp_en &&
4280 !hba->dev_info.is_lu_power_on_wp) {
4281 u8 b_lu_write_protect;
4282
4283 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4284 &b_lu_write_protect) &&
4285 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4286 hba->dev_info.is_lu_power_on_wp = true;
4287 }
4288}
4289
7a3e97b0
SY		 4290/**
4291 * ufshcd_slave_alloc - handle initial SCSI device configurations
4292 * @sdev: pointer to SCSI device
4293 *
4294 * Returns success
4295 */
4296static int ufshcd_slave_alloc(struct scsi_device *sdev)
4297{
4298 struct ufs_hba *hba;
4299
4300 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4301
4302 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4303 sdev->use_10_for_ms = 1;
7a3e97b0 4304
e8e7f271
SRT		 4305 /* allow SCSI layer to restart the device in case of errors */
4306 sdev->allow_restart = 1;
4264fd61 4307
b2a6c522
SRT		 4308 /* REPORT SUPPORTED OPERATION CODES is not supported */
4309 sdev->no_report_opcodes = 1;
4310
e8e7f271 4311
0ce147d4 4312 ufshcd_set_queue_depth(sdev);
4264fd61 4313
57d104c1
SJ		 4314 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4315
7a3e97b0
SY		 4316 return 0;
4317}
4318
4264fd61
SRT		 4319/**
4320 * ufshcd_change_queue_depth - change queue depth
4321 * @sdev: pointer to SCSI device
4322 * @depth: required depth to set
4264fd61 4323 *
db5ed4df 4324 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4325 */
db5ed4df 4326static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4327{
4328 struct ufs_hba *hba = shost_priv(sdev->host);
4329
4330 if (depth > hba->nutrs)
4331 depth = hba->nutrs;
db5ed4df 4332 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4333}
4334
eeda4749
AM		 4335/**
4336 * ufshcd_slave_configure - adjust SCSI device configurations
4337 * @sdev: pointer to SCSI device
4338 */
4339static int ufshcd_slave_configure(struct scsi_device *sdev)
4340{
4341 struct request_queue *q = sdev->request_queue;
4342
4343 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4344 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4345
4346 return 0;
4347}
4348
7a3e97b0
SY		 4349/**
4350 * ufshcd_slave_destroy - remove SCSI device configurations
4351 * @sdev: pointer to SCSI device
4352 */
4353static void ufshcd_slave_destroy(struct scsi_device *sdev)
4354{
4355 struct ufs_hba *hba;
4356
4357 hba = shost_priv(sdev->host);
0ce147d4 4358 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4359 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4360 unsigned long flags;
4361
4362 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4363 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4364 spin_unlock_irqrestore(hba->host->host_lock, flags);
4365 }
7a3e97b0
SY		 4366}
4367
4368/**
4369 * ufshcd_task_req_compl - handle task management request completion
4370 * @hba: per adapter instance
4371 * @index: index of the completed request
e2933132 4372 * @resp: task management service response
7a3e97b0 4373 *
e2933132 4374 * Returns non-zero value on error, zero on success
7a3e97b0 4375 */
e2933132 4376static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 4377{
4378 struct utp_task_req_desc *task_req_descp;
4379 struct utp_upiu_task_rsp *task_rsp_upiup;
4380 unsigned long flags;
4381 int ocs_value;
4382 int task_result;
4383
4384 spin_lock_irqsave(hba->host->host_lock, flags);
4385
4386 /* Clear completed tasks from outstanding_tasks */
4387 __clear_bit(index, &hba->outstanding_tasks);
4388
4389 task_req_descp = hba->utmrdl_base_addr;
4390 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
4391
4392 if (ocs_value == OCS_SUCCESS) {
4393 task_rsp_upiup = (struct utp_upiu_task_rsp *)
4394 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 4395 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
4396 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 4397 if (resp)
4398 *resp = (u8)task_result;
7a3e97b0 4399 } else {
e2933132
SRT		 4400 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
4401 __func__, ocs_value);
7a3e97b0
SY		 4402 }
4403 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 4404
4405 return ocs_value;
7a3e97b0
SY		 4406}
4407
7a3e97b0
SY		 4408/**
4409 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
4410 * @lrb: pointer to local reference block of completed command
4411 * @scsi_status: SCSI command status
4412 *
4413 * Returns value base on SCSI command status
4414 */
4415static inline int
4416ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4417{
4418 int result = 0;
4419
4420 switch (scsi_status) {
7a3e97b0 4421 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 4422 ufshcd_copy_sense_data(lrbp);
4423 case SAM_STAT_GOOD:
7a3e97b0
SY		 4424 result |= DID_OK << 16 |
4425 COMMAND_COMPLETE << 8 |
1c2623c5 4426 scsi_status;
7a3e97b0
SY		 4427 break;
4428 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4429 case SAM_STAT_BUSY:
7a3e97b0 4430 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4431 ufshcd_copy_sense_data(lrbp);
4432 result |= scsi_status;
7a3e97b0
SY		 4433 break;
4434 default:
4435 result |= DID_ERROR << 16;
4436 break;
4437 } /* end of switch */
4438
4439 return result;
4440}
4441
4442/**
4443 * ufshcd_transfer_rsp_status - Get overall status of the response
4444 * @hba: per adapter instance
4445 * @lrb: pointer to local reference block of completed command
4446 *
4447 * Returns result of the command to notify SCSI midlayer
4448 */
4449static inline int
4450ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4451{
4452 int result = 0;
4453 int scsi_status;
4454 int ocs;
4455
4456 /* overall command status of utrd */
4457 ocs = ufshcd_get_tr_ocs(lrbp);
4458
4459 switch (ocs) {
4460 case OCS_SUCCESS:
5a0b0cb9 4461 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4462 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4463 switch (result) {
4464 case UPIU_TRANSACTION_RESPONSE:
4465 /*
4466 * get the response UPIU result to extract
4467 * the SCSI command status
4468 */
4469 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4470
4471 /*
4472 * get the result based on SCSI status response
4473 * to notify the SCSI midlayer of the command status
4474 */
4475 scsi_status = result & MASK_SCSI_STATUS;
4476 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4477
f05ac2e5
YG		 4478 /*
4479 * Currently we are only supporting BKOPs exception
4480 * events hence we can ignore BKOPs exception event
4481 * during power management callbacks. BKOPs exception
4482 * event is not expected to be raised in runtime suspend
4483 * callback as it allows the urgent bkops.
4484 * During system suspend, we are anyway forcefully
4485 * disabling the bkops and if urgent bkops is needed
4486 * it will be enabled on system resume. Long term
4487 * solution could be to abort the system suspend if
4488 * UFS device needs urgent BKOPs.
4489 */
4490 if (!hba->pm_op_in_progress &&
4491 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 4492 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 4493 break;
4494 case UPIU_TRANSACTION_REJECT_UPIU:
4495 /* TODO: handle Reject UPIU Response */
4496 result = DID_ERROR << 16;
3b1d0580 4497 dev_err(hba->dev,
5a0b0cb9
SRT		 4498 "Reject UPIU not fully implemented\n");
4499 break;
4500 default:
4501 result = DID_ERROR << 16;
4502 dev_err(hba->dev,
4503 "Unexpected request response code = %x\n",
4504 result);
7a3e97b0
SY		 4505 break;
4506 }
7a3e97b0
SY		 4507 break;
4508 case OCS_ABORTED:
4509 result |= DID_ABORT << 16;
4510 break;
e8e7f271
SRT		 4511 case OCS_INVALID_COMMAND_STATUS:
4512 result |= DID_REQUEUE << 16;
4513 break;
7a3e97b0
SY		 4514 case OCS_INVALID_CMD_TABLE_ATTR:
4515 case OCS_INVALID_PRDT_ATTR:
4516 case OCS_MISMATCH_DATA_BUF_SIZE:
4517 case OCS_MISMATCH_RESP_UPIU_SIZE:
4518 case OCS_PEER_COMM_FAILURE:
4519 case OCS_FATAL_ERROR:
4520 default:
4521 result |= DID_ERROR << 16;
3b1d0580 4522 dev_err(hba->dev,
ff8e20c6
DR		 4523 "OCS error from controller = %x for tag %d\n",
4524 ocs, lrbp->task_tag);
4525 ufshcd_print_host_regs(hba);
6ba65588 4526 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4527 break;
4528 } /* end of switch */
4529
66cc820f
DR		 4530 if (host_byte(result) != DID_OK)
4531 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4532 return result;
4533}
4534
6ccf44fe
SJ		 4535/**
4536 * ufshcd_uic_cmd_compl - handle completion of uic command
4537 * @hba: per adapter instance
53b3d9c3 4538 * @intr_status: interrupt status generated by the controller
6ccf44fe 4539 */
53b3d9c3 4540static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4541{
53b3d9c3 4542 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4543 hba->active_uic_cmd->argument2 |=
4544 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4545 hba->active_uic_cmd->argument3 =
4546 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 4547 complete(&hba->active_uic_cmd->done);
4548 }
53b3d9c3 4549
57d104c1
SJ		 4550 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4551 complete(hba->uic_async_done);
6ccf44fe
SJ		 4552}
4553
7a3e97b0 4554/**
9a47ec7c 4555 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4556 * @hba: per adapter instance
9a47ec7c 4557 * @completed_reqs: requests to complete
7a3e97b0 4558 */
9a47ec7c
YG		 4559static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4560 unsigned long completed_reqs)
7a3e97b0 4561{
5a0b0cb9
SRT		 4562 struct ufshcd_lrb *lrbp;
4563 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4564 int result;
4565 int index;
e9d501b1 4566
e9d501b1
DR		 4567 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4568 lrbp = &hba->lrb[index];
4569 cmd = lrbp->cmd;
4570 if (cmd) {
1a07f2d9 4571 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4572 result = ufshcd_transfer_rsp_status(hba, lrbp);
4573 scsi_dma_unmap(cmd);
4574 cmd->result = result;
4575 /* Mark completed command as NULL in LRB */
4576 lrbp->cmd = NULL;
4577 clear_bit_unlock(index, &hba->lrb_in_use);
4578 /* Do not touch lrbp after scsi done */
4579 cmd->scsi_done(cmd);
1ab27c9c 4580 __ufshcd_release(hba);
300bb13f
JP		 4581 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4582 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 4583 if (hba->dev_cmd.complete) {
4584 ufshcd_add_command_trace(hba, index,
4585 "dev_complete");
e9d501b1 4586 complete(hba->dev_cmd.complete);
1a07f2d9 4587 }
e9d501b1 4588 }
401f1e44
SJ		 4589 if (ufshcd_is_clkscaling_supported(hba))
4590 hba->clk_scaling.active_reqs--;
4591 if (ufshcd_is_clkscaling_supported(hba))
4592 hba->clk_scaling.active_reqs--;
e9d501b1 4593 }
7a3e97b0
SY		 4594
4595 /* clear corresponding bits of completed commands */
4596 hba->outstanding_reqs ^= completed_reqs;
4597
856b3483
ST		 4598 ufshcd_clk_scaling_update_busy(hba);
4599
5a0b0cb9
SRT		 4600 /* we might have free'd some tags above */
4601 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 4602}
4603
9a47ec7c
YG		 4604/**
4605 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4606 * @hba: per adapter instance
4607 */
4608static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4609{
4610 unsigned long completed_reqs;
4611 u32 tr_doorbell;
4612
4613 /* Resetting interrupt aggregation counters first and reading the
4614 * DOOR_BELL afterward allows us to handle all the completed requests.
4615 * In order to prevent other interrupts starvation the DB is read once
4616 * after reset. The down side of this solution is the possibility of
4617 * false interrupt if device completes another request after resetting
4618 * aggregation and before reading the DB.
4619 */
4620 if (ufshcd_is_intr_aggr_allowed(hba))
4621 ufshcd_reset_intr_aggr(hba);
4622
4623 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4624 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4625
4626 __ufshcd_transfer_req_compl(hba, completed_reqs);
4627}
4628
66ec6d59
SRT		 4629/**
4630 * ufshcd_disable_ee - disable exception event
4631 * @hba: per-adapter instance
4632 * @mask: exception event to disable
4633 *
4634 * Disables exception event in the device so that the EVENT_ALERT
4635 * bit is not set.
4636 *
4637 * Returns zero on success, non-zero error value on failure.
4638 */
4639static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4640{
4641 int err = 0;
4642 u32 val;
4643
4644 if (!(hba->ee_ctrl_mask & mask))
4645 goto out;
4646
4647 val = hba->ee_ctrl_mask & ~mask;
4648 val &= 0xFFFF; /* 2 bytes */
5e86ae44 4649 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4650 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4651 if (!err)
4652 hba->ee_ctrl_mask &= ~mask;
4653out:
4654 return err;
4655}
4656
4657/**
4658 * ufshcd_enable_ee - enable exception event
4659 * @hba: per-adapter instance
4660 * @mask: exception event to enable
4661 *
4662 * Enable corresponding exception event in the device to allow
4663 * device to alert host in critical scenarios.
4664 *
4665 * Returns zero on success, non-zero error value on failure.
4666 */
4667static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4668{
4669 int err = 0;
4670 u32 val;
4671
4672 if (hba->ee_ctrl_mask & mask)
4673 goto out;
4674
4675 val = hba->ee_ctrl_mask | mask;
4676 val &= 0xFFFF; /* 2 bytes */
5e86ae44 4677 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4678 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4679 if (!err)
4680 hba->ee_ctrl_mask |= mask;
4681out:
4682 return err;
4683}
4684
4685/**
4686 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4687 * @hba: per-adapter instance
4688 *
4689 * Allow device to manage background operations on its own. Enabling
4690 * this might lead to inconsistent latencies during normal data transfers
4691 * as the device is allowed to manage its own way of handling background
4692 * operations.
4693 *
4694 * Returns zero on success, non-zero on failure.
4695 */
4696static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4697{
4698 int err = 0;
4699
4700 if (hba->auto_bkops_enabled)
4701 goto out;
4702
dc3c8d3a 4703 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4704 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4705 if (err) {
4706 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4707 __func__, err);
4708 goto out;
4709 }
4710
4711 hba->auto_bkops_enabled = true;
7ff5ab47 4712 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4713
4714 /* No need of URGENT_BKOPS exception from the device */
4715 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4716 if (err)
4717 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4718 __func__, err);
4719out:
4720 return err;
4721}
4722
4723/**
4724 * ufshcd_disable_auto_bkops - block device in doing background operations
4725 * @hba: per-adapter instance
4726 *
4727 * Disabling background operations improves command response latency but
4728 * has drawback of device moving into critical state where the device is
4729 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4730 * host is idle so that BKOPS are managed effectively without any negative
4731 * impacts.
4732 *
4733 * Returns zero on success, non-zero on failure.
4734 */
4735static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4736{
4737 int err = 0;
4738
4739 if (!hba->auto_bkops_enabled)
4740 goto out;
4741
4742 /*
4743 * If host assisted BKOPs is to be enabled, make sure
4744 * urgent bkops exception is allowed.
4745 */
4746 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4747 if (err) {
4748 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4749 __func__, err);
4750 goto out;
4751 }
4752
dc3c8d3a 4753 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 4754 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4755 if (err) {
4756 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4757 __func__, err);
4758 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4759 goto out;
4760 }
4761
4762 hba->auto_bkops_enabled = false;
7ff5ab47 4763 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 4764out:
4765 return err;
4766}
4767
4768/**
4e768e76 4769 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 4770 * @hba: per adapter instance
4771 *
4772 * After a device reset the device may toggle the BKOPS_EN flag
4773 * to default value. The s/w tracking variables should be updated
4e768e76
SJ		 4774 * as well. This function would change the auto-bkops state based on
4775 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 4776 */
4e768e76 4777static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 4778{
4e768e76
SJ		 4779 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4780 hba->auto_bkops_enabled = false;
4781 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4782 ufshcd_enable_auto_bkops(hba);
4783 } else {
4784 hba->auto_bkops_enabled = true;
4785 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4786 ufshcd_disable_auto_bkops(hba);
4787 }
66ec6d59
SRT		 4788}
4789
4790static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4791{
5e86ae44 4792 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4793 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
4794}
4795
4796/**
57d104c1 4797 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 4798 * @hba: per-adapter instance
57d104c1 4799 * @status: bkops_status value
66ec6d59 4800 *
57d104c1
SJ		 4801 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
4802 * flag in the device to permit background operations if the device
4803 * bkops_status is greater than or equal to "status" argument passed to
4804 * this function, disable otherwise.
4805 *
4806 * Returns 0 for success, non-zero in case of failure.
4807 *
4808 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
4809 * to know whether auto bkops is enabled or disabled after this function
4810 * returns control to it.
66ec6d59 4811 */
57d104c1
SJ		 4812static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
4813 enum bkops_status status)
66ec6d59
SRT		 4814{
4815 int err;
57d104c1 4816 u32 curr_status = 0;
66ec6d59 4817
57d104c1 4818 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 4819 if (err) {
4820 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4821 __func__, err);
4822 goto out;
57d104c1
SJ		 4823 } else if (curr_status > BKOPS_STATUS_MAX) {
4824 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
4825 __func__, curr_status);
4826 err = -EINVAL;
4827 goto out;
66ec6d59
SRT		 4828 }
4829
57d104c1 4830 if (curr_status >= status)
66ec6d59 4831 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 4832 else
4833 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 4834out:
4835 return err;
4836}
4837
57d104c1
SJ		 4838/**
4839 * ufshcd_urgent_bkops - handle urgent bkops exception event
4840 * @hba: per-adapter instance
4841 *
4842 * Enable fBackgroundOpsEn flag in the device to permit background
4843 * operations.
4844 *
4845 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
4846 * and negative error value for any other failure.
4847 */
4848static int ufshcd_urgent_bkops(struct ufs_hba *hba)
4849{
afdfff59 4850 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 4851}
4852
66ec6d59
SRT		 4853static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
4854{
5e86ae44 4855 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4856 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
4857}
4858
afdfff59
YG		 4859static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
4860{
4861 int err;
4862 u32 curr_status = 0;
4863
4864 if (hba->is_urgent_bkops_lvl_checked)
4865 goto enable_auto_bkops;
4866
4867 err = ufshcd_get_bkops_status(hba, &curr_status);
4868 if (err) {
4869 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4870 __func__, err);
4871 goto out;
4872 }
4873
4874 /*
4875 * We are seeing that some devices are raising the urgent bkops
4876 * exception events even when BKOPS status doesn't indicate performace
4877 * impacted or critical. Handle these device by determining their urgent
4878 * bkops status at runtime.
4879 */
4880 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
4881 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
4882 __func__, curr_status);
4883 /* update the current status as the urgent bkops level */
4884 hba->urgent_bkops_lvl = curr_status;
4885 hba->is_urgent_bkops_lvl_checked = true;
4886 }
4887
4888enable_auto_bkops:
4889 err = ufshcd_enable_auto_bkops(hba);
4890out:
4891 if (err < 0)
4892 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
4893 __func__, err);
4894}
4895
66ec6d59
SRT		 4896/**
4897 * ufshcd_exception_event_handler - handle exceptions raised by device
4898 * @work: pointer to work data
4899 *
4900 * Read bExceptionEventStatus attribute from the device and handle the
4901 * exception event accordingly.
4902 */
4903static void ufshcd_exception_event_handler(struct work_struct *work)
4904{
4905 struct ufs_hba *hba;
4906 int err;
4907 u32 status = 0;
4908 hba = container_of(work, struct ufs_hba, eeh_work);
4909
62694735 4910 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 4911 err = ufshcd_get_ee_status(hba, &status);
4912 if (err) {
4913 dev_err(hba->dev, "%s: failed to get exception status %d\n",
4914 __func__, err);
4915 goto out;
4916 }
4917
4918 status &= hba->ee_ctrl_mask;
afdfff59
YG		 4919
4920 if (status & MASK_EE_URGENT_BKOPS)
4921 ufshcd_bkops_exception_event_handler(hba);
4922
66ec6d59 4923out:
62694735 4924 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 4925 return;
4926}
4927
9a47ec7c
YG		 4928/* Complete requests that have door-bell cleared */
4929static void ufshcd_complete_requests(struct ufs_hba *hba)
4930{
4931 ufshcd_transfer_req_compl(hba);
4932 ufshcd_tmc_handler(hba);
4933}
4934
583fa62d
YG		 4935/**
4936 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
4937 * to recover from the DL NAC errors or not.
4938 * @hba: per-adapter instance
4939 *
4940 * Returns true if error handling is required, false otherwise
4941 */
4942static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
4943{
4944 unsigned long flags;
4945 bool err_handling = true;
4946
4947 spin_lock_irqsave(hba->host->host_lock, flags);
4948 /*
4949 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
4950 * device fatal error and/or DL NAC & REPLAY timeout errors.
4951 */
4952 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
4953 goto out;
4954
4955 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
4956 ((hba->saved_err & UIC_ERROR) &&
4957 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
4958 goto out;
4959
4960 if ((hba->saved_err & UIC_ERROR) &&
4961 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
4962 int err;
4963 /*
4964 * wait for 50ms to see if we can get any other errors or not.
4965 */
4966 spin_unlock_irqrestore(hba->host->host_lock, flags);
4967 msleep(50);
4968 spin_lock_irqsave(hba->host->host_lock, flags);
4969
4970 /*
4971 * now check if we have got any other severe errors other than
4972 * DL NAC error?
4973 */
4974 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4975 ((hba->saved_err & UIC_ERROR) &&
4976 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
4977 goto out;
4978
4979 /*
4980 * As DL NAC is the only error received so far, send out NOP
4981 * command to confirm if link is still active or not.
4982 * - If we don't get any response then do error recovery.
4983 * - If we get response then clear the DL NAC error bit.
4984 */
4985
4986 spin_unlock_irqrestore(hba->host->host_lock, flags);
4987 err = ufshcd_verify_dev_init(hba);
4988 spin_lock_irqsave(hba->host->host_lock, flags);
4989
4990 if (err)
4991 goto out;
4992
4993 /* Link seems to be alive hence ignore the DL NAC errors */
4994 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
4995 hba->saved_err &= ~UIC_ERROR;
4996 /* clear NAC error */
4997 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4998 if (!hba->saved_uic_err) {
4999 err_handling = false;
5000 goto out;
5001 }
5002 }
5003out:
5004 spin_unlock_irqrestore(hba->host->host_lock, flags);
5005 return err_handling;
5006}
5007
7a3e97b0 5008/**
e8e7f271
SRT		 5009 * ufshcd_err_handler - handle UFS errors that require s/w attention
5010 * @work: pointer to work structure
7a3e97b0 5011 */
e8e7f271 5012static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5013{
5014 struct ufs_hba *hba;
e8e7f271
SRT		 5015 unsigned long flags;
5016 u32 err_xfer = 0;
5017 u32 err_tm = 0;
5018 int err = 0;
5019 int tag;
9a47ec7c 5020 bool needs_reset = false;
e8e7f271
SRT		 5021
5022 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5023
62694735 5024 pm_runtime_get_sync(hba->dev);
1ab27c9c 5025 ufshcd_hold(hba, false);
e8e7f271
SRT		 5026
5027 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5028 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5029 goto out;
e8e7f271
SRT		 5030
5031 hba->ufshcd_state = UFSHCD_STATE_RESET;
5032 ufshcd_set_eh_in_progress(hba);
5033
5034 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5035 ufshcd_complete_requests(hba);
583fa62d
YG		 5036
5037 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5038 bool ret;
5039
5040 spin_unlock_irqrestore(hba->host->host_lock, flags);
5041 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5042 ret = ufshcd_quirk_dl_nac_errors(hba);
5043 spin_lock_irqsave(hba->host->host_lock, flags);
5044 if (!ret)
5045 goto skip_err_handling;
5046 }
9a47ec7c
YG		 5047 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5048 ((hba->saved_err & UIC_ERROR) &&
5049 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5050 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5051 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5052 needs_reset = true;
e8e7f271 5053
9a47ec7c
YG		 5054 /*
5055 * if host reset is required then skip clearing the pending
5056 * transfers forcefully because they will automatically get
5057 * cleared after link startup.
5058 */
5059 if (needs_reset)
5060 goto skip_pending_xfer_clear;
5061
5062 /* release lock as clear command might sleep */
5063 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5064 /* Clear pending transfer requests */
9a47ec7c
YG		 5065 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5066 if (ufshcd_clear_cmd(hba, tag)) {
5067 err_xfer = true;
5068 goto lock_skip_pending_xfer_clear;
5069 }
5070 }
e8e7f271
SRT		 5071
5072 /* Clear pending task management requests */
9a47ec7c
YG		 5073 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5074 if (ufshcd_clear_tm_cmd(hba, tag)) {
5075 err_tm = true;
5076 goto lock_skip_pending_xfer_clear;
5077 }
5078 }
e8e7f271 5079
9a47ec7c 5080lock_skip_pending_xfer_clear:
e8e7f271 5081 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5082
9a47ec7c
YG		 5083 /* Complete the requests that are cleared by s/w */
5084 ufshcd_complete_requests(hba);
5085
5086 if (err_xfer || err_tm)
5087 needs_reset = true;
5088
5089skip_pending_xfer_clear:
e8e7f271 5090 /* Fatal errors need reset */
9a47ec7c
YG		 5091 if (needs_reset) {
5092 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5093
5094 /*
5095 * ufshcd_reset_and_restore() does the link reinitialization
5096 * which will need atleast one empty doorbell slot to send the
5097 * device management commands (NOP and query commands).
5098 * If there is no slot empty at this moment then free up last
5099 * slot forcefully.
5100 */
5101 if (hba->outstanding_reqs == max_doorbells)
5102 __ufshcd_transfer_req_compl(hba,
5103 (1UL << (hba->nutrs - 1)));
5104
5105 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5106 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5107 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5108 if (err) {
5109 dev_err(hba->dev, "%s: reset and restore failed\n",
5110 __func__);
5111 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5112 }
5113 /*
5114 * Inform scsi mid-layer that we did reset and allow to handle
5115 * Unit Attention properly.
5116 */
5117 scsi_report_bus_reset(hba->host, 0);
5118 hba->saved_err = 0;
5119 hba->saved_uic_err = 0;
5120 }
9a47ec7c 5121
583fa62d 5122skip_err_handling:
9a47ec7c
YG		 5123 if (!needs_reset) {
5124 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5125 if (hba->saved_err || hba->saved_uic_err)
5126 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5127 __func__, hba->saved_err, hba->saved_uic_err);
5128 }
5129
e8e7f271
SRT		 5130 ufshcd_clear_eh_in_progress(hba);
5131
5132out:
9a47ec7c 5133 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5134 scsi_unblock_requests(hba->host);
1ab27c9c 5135 ufshcd_release(hba);
62694735 5136 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5137}
5138
ff8e20c6
DR		 5139static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5140 u32 reg)
5141{
5142 reg_hist->reg[reg_hist->pos] = reg;
5143 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5144 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5145}
5146
7a3e97b0 5147/**
e8e7f271
SRT		 5148 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5149 * @hba: per-adapter instance
7a3e97b0 5150 */
e8e7f271 5151static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5152{
5153 u32 reg;
5154
fb7b45f0
DR		 5155 /* PHY layer lane error */
5156 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5157 /* Ignore LINERESET indication, as this is not an error */
5158 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5159 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5160 /*
5161 * To know whether this error is fatal or not, DB timeout
5162 * must be checked but this error is handled separately.
5163 */
5164 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR		 5165 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5166 }
fb7b45f0 5167
e8e7f271
SRT		 5168 /* PA_INIT_ERROR is fatal and needs UIC reset */
5169 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR		 5170 if (reg)
5171 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5172
e8e7f271
SRT		 5173 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5174 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 5175 else if (hba->dev_quirks &
5176 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5177 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5178 hba->uic_error |=
5179 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5180 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5181 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5182 }
e8e7f271
SRT		 5183
5184 /* UIC NL/TL/DME errors needs software retry */
5185 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR		 5186 if (reg) {
5187 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5188 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5189 }
e8e7f271
SRT		 5190
5191 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR		 5192 if (reg) {
5193 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5194 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5195 }
e8e7f271
SRT		 5196
5197 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR		 5198 if (reg) {
5199 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5200 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5201 }
e8e7f271
SRT		 5202
5203 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5204 __func__, hba->uic_error);
5205}
5206
5207/**
5208 * ufshcd_check_errors - Check for errors that need s/w attention
5209 * @hba: per-adapter instance
5210 */
5211static void ufshcd_check_errors(struct ufs_hba *hba)
5212{
5213 bool queue_eh_work = false;
5214
7a3e97b0 5215 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5216 queue_eh_work = true;
7a3e97b0
SY		 5217
5218 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 5219 hba->uic_error = 0;
5220 ufshcd_update_uic_error(hba);
5221 if (hba->uic_error)
5222 queue_eh_work = true;
7a3e97b0 5223 }
e8e7f271
SRT		 5224
5225 if (queue_eh_work) {
9a47ec7c
YG		 5226 /*
5227 * update the transfer error masks to sticky bits, let's do this
5228 * irrespective of current ufshcd_state.
5229 */
5230 hba->saved_err |= hba->errors;
5231 hba->saved_uic_err |= hba->uic_error;
5232
e8e7f271
SRT		 5233 /* handle fatal errors only when link is functional */
5234 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5235 /* block commands from scsi mid-layer */
5236 scsi_block_requests(hba->host);
5237
141f8165 5238 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5239
5240 /* dump controller state before resetting */
5241 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5242 bool pr_prdt = !!(hba->saved_err &
5243 SYSTEM_BUS_FATAL_ERROR);
5244
5245 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5246 __func__, hba->saved_err,
5247 hba->saved_uic_err);
5248
5249 ufshcd_print_host_regs(hba);
5250 ufshcd_print_pwr_info(hba);
5251 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5252 ufshcd_print_trs(hba, hba->outstanding_reqs,
5253 pr_prdt);
5254 }
e8e7f271
SRT		 5255 schedule_work(&hba->eh_work);
5256 }
3441da7d 5257 }
e8e7f271
SRT		 5258 /*
5259 * if (!queue_eh_work) -
5260 * Other errors are either non-fatal where host recovers
5261 * itself without s/w intervention or errors that will be
5262 * handled by the SCSI core layer.
5263 */
7a3e97b0
SY		 5264}
5265
5266/**
5267 * ufshcd_tmc_handler - handle task management function completion
5268 * @hba: per adapter instance
5269 */
5270static void ufshcd_tmc_handler(struct ufs_hba *hba)
5271{
5272 u32 tm_doorbell;
5273
b873a275 5274 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5275 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 5276 wake_up(&hba->tm_wq);
7a3e97b0
SY		 5277}
5278
5279/**
5280 * ufshcd_sl_intr - Interrupt service routine
5281 * @hba: per adapter instance
5282 * @intr_status: contains interrupts generated by the controller
5283 */
5284static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5285{
5286 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5287 if (hba->errors)
e8e7f271 5288 ufshcd_check_errors(hba);
7a3e97b0 5289
53b3d9c3
SJ		 5290 if (intr_status & UFSHCD_UIC_MASK)
5291 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5292
5293 if (intr_status & UTP_TASK_REQ_COMPL)
5294 ufshcd_tmc_handler(hba);
5295
5296 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5297 ufshcd_transfer_req_compl(hba);
5298}
5299
5300/**
5301 * ufshcd_intr - Main interrupt service routine
5302 * @irq: irq number
5303 * @__hba: pointer to adapter instance
5304 *
5305 * Returns IRQ_HANDLED - If interrupt is valid
5306 * IRQ_NONE - If invalid interrupt
5307 */
5308static irqreturn_t ufshcd_intr(int irq, void *__hba)
5309{
d75f7fe4 5310 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5311 irqreturn_t retval = IRQ_NONE;
5312 struct ufs_hba *hba = __hba;
5313
5314 spin_lock(hba->host->host_lock);
b873a275 5315 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5316 enabled_intr_status =
5317 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 5318
d75f7fe4 5319 if (intr_status)
261ea452 5320 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5321
5322 if (enabled_intr_status) {
5323 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 5324 retval = IRQ_HANDLED;
5325 }
5326 spin_unlock(hba->host->host_lock);
5327 return retval;
5328}
5329
e2933132
SRT		 5330static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5331{
5332 int err = 0;
5333 u32 mask = 1 << tag;
5334 unsigned long flags;
5335
5336 if (!test_bit(tag, &hba->outstanding_tasks))
5337 goto out;
5338
5339 spin_lock_irqsave(hba->host->host_lock, flags);
5340 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
5341 spin_unlock_irqrestore(hba->host->host_lock, flags);
5342
5343 /* poll for max. 1 sec to clear door bell register by h/w */
5344 err = ufshcd_wait_for_register(hba,
5345 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5346 mask, 0, 1000, 1000, true);
e2933132
SRT		 5347out:
5348 return err;
5349}
5350
7a3e97b0
SY		 5351/**
5352 * ufshcd_issue_tm_cmd - issues task management commands to controller
5353 * @hba: per adapter instance
e2933132
SRT		 5354 * @lun_id: LUN ID to which TM command is sent
5355 * @task_id: task ID to which the TM command is applicable
5356 * @tm_function: task management function opcode
5357 * @tm_response: task management service response return value
7a3e97b0 5358 *
e2933132 5359 * Returns non-zero value on error, zero on success.
7a3e97b0 5360 */
e2933132
SRT		 5361static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5362 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 5363{
5364 struct utp_task_req_desc *task_req_descp;
5365 struct utp_upiu_task_req *task_req_upiup;
5366 struct Scsi_Host *host;
5367 unsigned long flags;
e2933132 5368 int free_slot;
7a3e97b0 5369 int err;
e2933132 5370 int task_tag;
7a3e97b0
SY		 5371
5372 host = hba->host;
5373
e2933132
SRT		 5374 /*
5375 * Get free slot, sleep if slots are unavailable.
5376 * Even though we use wait_event() which sleeps indefinitely,
5377 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5378 */
5379 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5380 ufshcd_hold(hba, false);
7a3e97b0 5381
e2933132 5382 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 5383 task_req_descp = hba->utmrdl_base_addr;
5384 task_req_descp += free_slot;
5385
5386 /* Configure task request descriptor */
5387 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5388 task_req_descp->header.dword_2 =
5389 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5390
5391 /* Configure task request UPIU */
5392 task_req_upiup =
5393 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 5394 task_tag = hba->nutrs + free_slot;
7a3e97b0 5395 task_req_upiup->header.dword_0 =
5a0b0cb9 5396 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 5397 lun_id, task_tag);
7a3e97b0 5398 task_req_upiup->header.dword_1 =
5a0b0cb9 5399 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 5400 /*
5401 * The host shall provide the same value for LUN field in the basic
5402 * header and for Input Parameter.
5403 */
e2933132
SRT		 5404 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
5405 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 5406
d2877be4
KK		 5407 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5408
7a3e97b0
SY		 5409 /* send command to the controller */
5410 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5411
5412 /* Make sure descriptors are ready before ringing the task doorbell */
5413 wmb();
5414
b873a275 5415 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5416 /* Make sure that doorbell is committed immediately */
5417 wmb();
7a3e97b0
SY		 5418
5419 spin_unlock_irqrestore(host->host_lock, flags);
5420
5421 /* wait until the task management command is completed */
e2933132
SRT		 5422 err = wait_event_timeout(hba->tm_wq,
5423 test_bit(free_slot, &hba->tm_condition),
5424 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5425 if (!err) {
e2933132
SRT		 5426 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5427 __func__, tm_function);
5428 if (ufshcd_clear_tm_cmd(hba, free_slot))
5429 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5430 __func__, free_slot);
5431 err = -ETIMEDOUT;
5432 } else {
5433 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 5434 }
e2933132 5435
7a3e97b0 5436 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 5437 ufshcd_put_tm_slot(hba, free_slot);
5438 wake_up(&hba->tm_tag_wq);
5439
1ab27c9c 5440 ufshcd_release(hba);
7a3e97b0
SY		 5441 return err;
5442}
5443
5444/**
3441da7d
SRT		 5445 * ufshcd_eh_device_reset_handler - device reset handler registered to
5446 * scsi layer.
7a3e97b0
SY		 5447 * @cmd: SCSI command pointer
5448 *
5449 * Returns SUCCESS/FAILED
5450 */
3441da7d 5451static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5452{
5453 struct Scsi_Host *host;
5454 struct ufs_hba *hba;
5455 unsigned int tag;
5456 u32 pos;
5457 int err;
e2933132
SRT		 5458 u8 resp = 0xF;
5459 struct ufshcd_lrb *lrbp;
3441da7d 5460 unsigned long flags;
7a3e97b0
SY		 5461
5462 host = cmd->device->host;
5463 hba = shost_priv(host);
5464 tag = cmd->request->tag;
5465
e2933132
SRT		 5466 lrbp = &hba->lrb[tag];
5467 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5468 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 5469 if (!err)
5470 err = resp;
7a3e97b0 5471 goto out;
e2933132 5472 }
7a3e97b0 5473
3441da7d
SRT		 5474 /* clear the commands that were pending for corresponding LUN */
5475 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5476 if (hba->lrb[pos].lun == lrbp->lun) {
5477 err = ufshcd_clear_cmd(hba, pos);
5478 if (err)
5479 break;
7a3e97b0 5480 }
3441da7d
SRT		 5481 }
5482 spin_lock_irqsave(host->host_lock, flags);
5483 ufshcd_transfer_req_compl(hba);
5484 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5485
7a3e97b0 5486out:
7fabb77b 5487 hba->req_abort_count = 0;
3441da7d
SRT		 5488 if (!err) {
5489 err = SUCCESS;
5490 } else {
5491 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5492 err = FAILED;
5493 }
7a3e97b0
SY		 5494 return err;
5495}
5496
e0b299e3
GB		 5497static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5498{
5499 struct ufshcd_lrb *lrbp;
5500 int tag;
5501
5502 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5503 lrbp = &hba->lrb[tag];
5504 lrbp->req_abort_skip = true;
5505 }
5506}
5507
7a3e97b0
SY		 5508/**
5509 * ufshcd_abort - abort a specific command
5510 * @cmd: SCSI command pointer
5511 *
f20810d8
SRT		 5512 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5513 * command, and in host controller by clearing the door-bell register. There can
5514 * be race between controller sending the command to the device while abort is
5515 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5516 * really issued and then try to abort it.
5517 *
7a3e97b0
SY		 5518 * Returns SUCCESS/FAILED
5519 */
5520static int ufshcd_abort(struct scsi_cmnd *cmd)
5521{
5522 struct Scsi_Host *host;
5523 struct ufs_hba *hba;
5524 unsigned long flags;
5525 unsigned int tag;
f20810d8
SRT		 5526 int err = 0;
5527 int poll_cnt;
e2933132
SRT		 5528 u8 resp = 0xF;
5529 struct ufshcd_lrb *lrbp;
e9d501b1 5530 u32 reg;
7a3e97b0
SY		 5531
5532 host = cmd->device->host;
5533 hba = shost_priv(host);
5534 tag = cmd->request->tag;
e7d38257 5535 lrbp = &hba->lrb[tag];
14497328
YG		 5536 if (!ufshcd_valid_tag(hba, tag)) {
5537 dev_err(hba->dev,
5538 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5539 __func__, tag, cmd, cmd->request);
5540 BUG();
5541 }
7a3e97b0 5542
e7d38257
DR		 5543 /*
5544 * Task abort to the device W-LUN is illegal. When this command
5545 * will fail, due to spec violation, scsi err handling next step
5546 * will be to send LU reset which, again, is a spec violation.
5547 * To avoid these unnecessary/illegal step we skip to the last error
5548 * handling stage: reset and restore.
5549 */
5550 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5551 return ufshcd_eh_host_reset_handler(cmd);
5552
1ab27c9c 5553 ufshcd_hold(hba, false);
14497328 5554 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5555 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 5556 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5557 dev_err(hba->dev,
5558 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5559 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 5560 goto out;
14497328 5561 }
7a3e97b0 5562
e9d501b1
DR		 5563 if (!(reg & (1 << tag))) {
5564 dev_err(hba->dev,
5565 "%s: cmd was completed, but without a notifying intr, tag = %d",
5566 __func__, tag);
5567 }
5568
66cc820f
DR		 5569 /* Print Transfer Request of aborted task */
5570 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 5571
7fabb77b
GB		 5572 /*
5573 * Print detailed info about aborted request.
5574 * As more than one request might get aborted at the same time,
5575 * print full information only for the first aborted request in order
5576 * to reduce repeated printouts. For other aborted requests only print
5577 * basic details.
5578 */
5579 scsi_print_command(hba->lrb[tag].cmd);
5580 if (!hba->req_abort_count) {
5581 ufshcd_print_host_regs(hba);
6ba65588 5582 ufshcd_print_host_state(hba);
7fabb77b
GB		 5583 ufshcd_print_pwr_info(hba);
5584 ufshcd_print_trs(hba, 1 << tag, true);
5585 } else {
5586 ufshcd_print_trs(hba, 1 << tag, false);
5587 }
5588 hba->req_abort_count++;
e0b299e3
GB		 5589
5590 /* Skip task abort in case previous aborts failed and report failure */
5591 if (lrbp->req_abort_skip) {
5592 err = -EIO;
5593 goto out;
5594 }
5595
f20810d8
SRT		 5596 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
5597 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5598 UFS_QUERY_TASK, &resp);
5599 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
5600 /* cmd pending in the device */
ff8e20c6
DR		 5601 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
5602 __func__, tag);
f20810d8
SRT		 5603 break;
5604 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 5605 /*
5606 * cmd not pending in the device, check if it is
5607 * in transition.
5608 */
ff8e20c6
DR		 5609 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
5610 __func__, tag);
f20810d8
SRT		 5611 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5612 if (reg & (1 << tag)) {
5613 /* sleep for max. 200us to stabilize */
5614 usleep_range(100, 200);
5615 continue;
5616 }
5617 /* command completed already */
ff8e20c6
DR		 5618 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
5619 __func__, tag);
f20810d8
SRT		 5620 goto out;
5621 } else {
ff8e20c6
DR		 5622 dev_err(hba->dev,
5623 "%s: no response from device. tag = %d, err %d\n",
5624 __func__, tag, err);
f20810d8
SRT		 5625 if (!err)
5626 err = resp; /* service response error */
5627 goto out;
5628 }
5629 }
5630
5631 if (!poll_cnt) {
5632 err = -EBUSY;
7a3e97b0
SY		 5633 goto out;
5634 }
7a3e97b0 5635
e2933132
SRT		 5636 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5637 UFS_ABORT_TASK, &resp);
5638 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 5639 if (!err) {
f20810d8 5640 err = resp; /* service response error */
ff8e20c6
DR		 5641 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
5642 __func__, tag, err);
5643 }
7a3e97b0 5644 goto out;
e2933132 5645 }
7a3e97b0 5646
f20810d8 5647 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 5648 if (err) {
5649 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
5650 __func__, tag, err);
f20810d8 5651 goto out;
ff8e20c6 5652 }
f20810d8 5653
7a3e97b0
SY		 5654 scsi_dma_unmap(cmd);
5655
5656 spin_lock_irqsave(host->host_lock, flags);
a48353f6 5657 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 5658 hba->lrb[tag].cmd = NULL;
5659 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 5660
5661 clear_bit_unlock(tag, &hba->lrb_in_use);
5662 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 5663
7a3e97b0 5664out:
f20810d8
SRT		 5665 if (!err) {
5666 err = SUCCESS;
5667 } else {
5668 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 5669 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 5670 err = FAILED;
5671 }
5672
1ab27c9c
ST		 5673 /*
5674 * This ufshcd_release() corresponds to the original scsi cmd that got
5675 * aborted here (as we won't get any IRQ for it).
5676 */
5677 ufshcd_release(hba);
7a3e97b0
SY		 5678 return err;
5679}
5680
3441da7d
SRT		 5681/**
5682 * ufshcd_host_reset_and_restore - reset and restore host controller
5683 * @hba: per-adapter instance
5684 *
5685 * Note that host controller reset may issue DME_RESET to
5686 * local and remote (device) Uni-Pro stack and the attributes
5687 * are reset to default state.
5688 *
5689 * Returns zero on success, non-zero on failure
5690 */
5691static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
5692{
5693 int err;
3441da7d
SRT		 5694 unsigned long flags;
5695
5696 /* Reset the host controller */
5697 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 5698 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 5699 spin_unlock_irqrestore(hba->host->host_lock, flags);
5700
a3cd5ec5
SJ		 5701 /* scale up clocks to max frequency before full reinitialization */
5702 ufshcd_scale_clks(hba, true);
5703
3441da7d
SRT		 5704 err = ufshcd_hba_enable(hba);
5705 if (err)
5706 goto out;
5707
5708 /* Establish the link again and restore the device */
1d337ec2
SRT		 5709 err = ufshcd_probe_hba(hba);
5710
5711 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 5712 err = -EIO;
5713out:
5714 if (err)
5715 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
5716
5717 return err;
5718}
5719
5720/**
5721 * ufshcd_reset_and_restore - reset and re-initialize host/device
5722 * @hba: per-adapter instance
5723 *
5724 * Reset and recover device, host and re-establish link. This
5725 * is helpful to recover the communication in fatal error conditions.
5726 *
5727 * Returns zero on success, non-zero on failure
5728 */
5729static int ufshcd_reset_and_restore(struct ufs_hba *hba)
5730{
5731 int err = 0;
5732 unsigned long flags;
1d337ec2 5733 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 5734
1d337ec2
SRT		 5735 do {
5736 err = ufshcd_host_reset_and_restore(hba);
5737 } while (err && --retries);
3441da7d
SRT		 5738
5739 /*
5740 * After reset the door-bell might be cleared, complete
5741 * outstanding requests in s/w here.
5742 */
5743 spin_lock_irqsave(hba->host->host_lock, flags);
5744 ufshcd_transfer_req_compl(hba);
5745 ufshcd_tmc_handler(hba);
5746 spin_unlock_irqrestore(hba->host->host_lock, flags);
5747
5748 return err;
5749}
5750
5751/**
5752 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
5753 * @cmd - SCSI command pointer
5754 *
5755 * Returns SUCCESS/FAILED
5756 */
5757static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
5758{
5759 int err;
5760 unsigned long flags;
5761 struct ufs_hba *hba;
5762
5763 hba = shost_priv(cmd->device->host);
5764
1ab27c9c 5765 ufshcd_hold(hba, false);
3441da7d
SRT		 5766 /*
5767 * Check if there is any race with fatal error handling.
5768 * If so, wait for it to complete. Even though fatal error
5769 * handling does reset and restore in some cases, don't assume
5770 * anything out of it. We are just avoiding race here.
5771 */
5772 do {
5773 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5774 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 5775 hba->ufshcd_state == UFSHCD_STATE_RESET))
5776 break;
5777 spin_unlock_irqrestore(hba->host->host_lock, flags);
5778 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 5779 flush_work(&hba->eh_work);
3441da7d
SRT		 5780 } while (1);
5781
5782 hba->ufshcd_state = UFSHCD_STATE_RESET;
5783 ufshcd_set_eh_in_progress(hba);
5784 spin_unlock_irqrestore(hba->host->host_lock, flags);
5785
5786 err = ufshcd_reset_and_restore(hba);
5787
5788 spin_lock_irqsave(hba->host->host_lock, flags);
5789 if (!err) {
5790 err = SUCCESS;
5791 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5792 } else {
5793 err = FAILED;
5794 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5795 }
5796 ufshcd_clear_eh_in_progress(hba);
5797 spin_unlock_irqrestore(hba->host->host_lock, flags);
5798
1ab27c9c 5799 ufshcd_release(hba);
3441da7d
SRT		 5800 return err;
5801}
5802
3a4bf06d
YG		 5803/**
5804 * ufshcd_get_max_icc_level - calculate the ICC level
5805 * @sup_curr_uA: max. current supported by the regulator
5806 * @start_scan: row at the desc table to start scan from
5807 * @buff: power descriptor buffer
5808 *
5809 * Returns calculated max ICC level for specific regulator
5810 */
5811static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
5812{
5813 int i;
5814 int curr_uA;
5815 u16 data;
5816 u16 unit;
5817
5818 for (i = start_scan; i >= 0; i--) {
d79713f9 5819 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 5820 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
5821 ATTR_ICC_LVL_UNIT_OFFSET;
5822 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
5823 switch (unit) {
5824 case UFSHCD_NANO_AMP:
5825 curr_uA = curr_uA / 1000;
5826 break;
5827 case UFSHCD_MILI_AMP:
5828 curr_uA = curr_uA * 1000;
5829 break;
5830 case UFSHCD_AMP:
5831 curr_uA = curr_uA * 1000 * 1000;
5832 break;
5833 case UFSHCD_MICRO_AMP:
5834 default:
5835 break;
5836 }
5837 if (sup_curr_uA >= curr_uA)
5838 break;
5839 }
5840 if (i < 0) {
5841 i = 0;
5842 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
5843 }
5844
5845 return (u32)i;
5846}
5847
5848/**
5849 * ufshcd_calc_icc_level - calculate the max ICC level
5850 * In case regulators are not initialized we'll return 0
5851 * @hba: per-adapter instance
5852 * @desc_buf: power descriptor buffer to extract ICC levels from.
5853 * @len: length of desc_buff
5854 *
5855 * Returns calculated ICC level
5856 */
5857static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
5858 u8 *desc_buf, int len)
5859{
5860 u32 icc_level = 0;
5861
5862 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
5863 !hba->vreg_info.vccq2) {
5864 dev_err(hba->dev,
5865 "%s: Regulator capability was not set, actvIccLevel=%d",
5866 __func__, icc_level);
5867 goto out;
5868 }
5869
5870 if (hba->vreg_info.vcc)
5871 icc_level = ufshcd_get_max_icc_level(
5872 hba->vreg_info.vcc->max_uA,
5873 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
5874 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
5875
5876 if (hba->vreg_info.vccq)
5877 icc_level = ufshcd_get_max_icc_level(
5878 hba->vreg_info.vccq->max_uA,
5879 icc_level,
5880 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
5881
5882 if (hba->vreg_info.vccq2)
5883 icc_level = ufshcd_get_max_icc_level(
5884 hba->vreg_info.vccq2->max_uA,
5885 icc_level,
5886 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
5887out:
5888 return icc_level;
5889}
5890
61e07359
DR		 5891static int ufshcd_set_icc_levels_attr(struct ufs_hba *hba, u32 icc_level)
5892{
5893 int ret = 0;
5894 int retries;
5895
5896 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5897 /* write attribute */
5898 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5899 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
5900 if (!ret)
5901 break;
5902
5903 dev_dbg(hba->dev, "%s: failed with error %d\n", __func__, ret);
5904 }
5905
5906 return ret;
5907}
5908
3a4bf06d
YG		 5909static void ufshcd_init_icc_levels(struct ufs_hba *hba)
5910{
5911 int ret;
5912 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
5913 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
5914
5915 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
5916 if (ret) {
5917 dev_err(hba->dev,
5918 "%s: Failed reading power descriptor.len = %d ret = %d",
5919 __func__, buff_len, ret);
5920 return;
5921 }
5922
5923 hba->init_prefetch_data.icc_level =
5924 ufshcd_find_max_sup_active_icc_level(hba,
5925 desc_buf, buff_len);
5926 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
5927 __func__, hba->init_prefetch_data.icc_level);
5928
61e07359
DR		 5929 ret = ufshcd_set_icc_levels_attr(hba,
5930 hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 5931
5932 if (ret)
5933 dev_err(hba->dev,
5934 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
5935 __func__, hba->init_prefetch_data.icc_level , ret);
5936
5937}
5938
2a8fa600
SJ		 5939/**
5940 * ufshcd_scsi_add_wlus - Adds required W-LUs
5941 * @hba: per-adapter instance
5942 *
5943 * UFS device specification requires the UFS devices to support 4 well known
5944 * logical units:
5945 * "REPORT_LUNS" (address: 01h)
5946 * "UFS Device" (address: 50h)
5947 * "RPMB" (address: 44h)
5948 * "BOOT" (address: 30h)
5949 * UFS device's power management needs to be controlled by "POWER CONDITION"
5950 * field of SSU (START STOP UNIT) command. But this "power condition" field
5951 * will take effect only when its sent to "UFS device" well known logical unit
5952 * hence we require the scsi_device instance to represent this logical unit in
5953 * order for the UFS host driver to send the SSU command for power management.
5954
5955 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
5956 * Block) LU so user space process can control this LU. User space may also
5957 * want to have access to BOOT LU.
5958
5959 * This function adds scsi device instances for each of all well known LUs
5960 * (except "REPORT LUNS" LU).
5961 *
5962 * Returns zero on success (all required W-LUs are added successfully),
5963 * non-zero error value on failure (if failed to add any of the required W-LU).
5964 */
5965static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
5966{
5967 int ret = 0;
7c48bfd0
AM		 5968 struct scsi_device *sdev_rpmb;
5969 struct scsi_device *sdev_boot;
2a8fa600
SJ		 5970
5971 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
5972 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
5973 if (IS_ERR(hba->sdev_ufs_device)) {
5974 ret = PTR_ERR(hba->sdev_ufs_device);
5975 hba->sdev_ufs_device = NULL;
5976 goto out;
5977 }
7c48bfd0 5978 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 5979
7c48bfd0 5980 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 5981 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 5982 if (IS_ERR(sdev_boot)) {
5983 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 5984 goto remove_sdev_ufs_device;
5985 }
7c48bfd0 5986 scsi_device_put(sdev_boot);
2a8fa600 5987
7c48bfd0 5988 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 5989 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 5990 if (IS_ERR(sdev_rpmb)) {
5991 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 5992 goto remove_sdev_boot;
5993 }
7c48bfd0 5994 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 5995 goto out;
5996
5997remove_sdev_boot:
7c48bfd0 5998 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 5999remove_sdev_ufs_device:
6000 scsi_remove_device(hba->sdev_ufs_device);
6001out:
6002 return ret;
6003}
6004
93fdd5ac
TW		 6005static int ufs_get_device_desc(struct ufs_hba *hba,
6006 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6007{
6008 int err;
6009 u8 model_index;
6010 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
6011 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
6012
6013 err = ufshcd_read_device_desc(hba, desc_buf,
6014 QUERY_DESC_DEVICE_MAX_SIZE);
6015 if (err) {
6016 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6017 __func__, err);
6018 goto out;
6019 }
6020
6021 /*
6022 * getting vendor (manufacturerID) and Bank Index in big endian
6023 * format
6024 */
93fdd5ac 6025 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6026 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6027
6028 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6029
6030 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
6031 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
6032 if (err) {
6033 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6034 __func__, err);
6035 goto out;
6036 }
6037
6038 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
93fdd5ac 6039 strlcpy(dev_desc->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
c58ab7aa
YG		 6040 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
6041 MAX_MODEL_LEN));
6042
6043 /* Null terminate the model string */
93fdd5ac 6044 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG		 6045
6046out:
6047 return err;
6048}
6049
93fdd5ac
TW		 6050static void ufs_fixup_device_setup(struct ufs_hba *hba,
6051 struct ufs_dev_desc *dev_desc)
c58ab7aa 6052{
c58ab7aa 6053 struct ufs_dev_fix *f;
c58ab7aa
YG		 6054
6055 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6056 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6057 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6058 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG		 6059 !strcmp(f->card.model, UFS_ANY_MODEL)))
6060 hba->dev_quirks |= f->quirk;
6061 }
6062}
6063
37113106
YG		 6064/**
6065 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6066 * @hba: per-adapter instance
6067 *
6068 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6069 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6070 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6071 * the hibern8 exit latency.
6072 *
6073 * Returns zero on success, non-zero error value on failure.
6074 */
6075static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6076{
6077 int ret = 0;
6078 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6079
6080 ret = ufshcd_dme_peer_get(hba,
6081 UIC_ARG_MIB_SEL(
6082 RX_MIN_ACTIVATETIME_CAPABILITY,
6083 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6084 &peer_rx_min_activatetime);
6085 if (ret)
6086 goto out;
6087
6088 /* make sure proper unit conversion is applied */
6089 tuned_pa_tactivate =
6090 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6091 / PA_TACTIVATE_TIME_UNIT_US);
6092 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6093 tuned_pa_tactivate);
6094
6095out:
6096 return ret;
6097}
6098
6099/**
6100 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6101 * @hba: per-adapter instance
6102 *
6103 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6104 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6105 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6106 * This optimal value can help reduce the hibern8 exit latency.
6107 *
6108 * Returns zero on success, non-zero error value on failure.
6109 */
6110static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6111{
6112 int ret = 0;
6113 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6114 u32 max_hibern8_time, tuned_pa_hibern8time;
6115
6116 ret = ufshcd_dme_get(hba,
6117 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6118 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6119 &local_tx_hibern8_time_cap);
6120 if (ret)
6121 goto out;
6122
6123 ret = ufshcd_dme_peer_get(hba,
6124 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6125 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6126 &peer_rx_hibern8_time_cap);
6127 if (ret)
6128 goto out;
6129
6130 max_hibern8_time = max(local_tx_hibern8_time_cap,
6131 peer_rx_hibern8_time_cap);
6132 /* make sure proper unit conversion is applied */
6133 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6134 / PA_HIBERN8_TIME_UNIT_US);
6135 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6136 tuned_pa_hibern8time);
6137out:
6138 return ret;
6139}
6140
c6a6db43
SJ		 6141/**
6142 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6143 * less than device PA_TACTIVATE time.
6144 * @hba: per-adapter instance
6145 *
6146 * Some UFS devices require host PA_TACTIVATE to be lower than device
6147 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6148 * for such devices.
6149 *
6150 * Returns zero on success, non-zero error value on failure.
6151 */
6152static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6153{
6154 int ret = 0;
6155 u32 granularity, peer_granularity;
6156 u32 pa_tactivate, peer_pa_tactivate;
6157 u32 pa_tactivate_us, peer_pa_tactivate_us;
6158 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6159
6160 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6161 &granularity);
6162 if (ret)
6163 goto out;
6164
6165 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6166 &peer_granularity);
6167 if (ret)
6168 goto out;
6169
6170 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6171 (granularity > PA_GRANULARITY_MAX_VAL)) {
6172 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6173 __func__, granularity);
6174 return -EINVAL;
6175 }
6176
6177 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6178 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6179 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6180 __func__, peer_granularity);
6181 return -EINVAL;
6182 }
6183
6184 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6185 if (ret)
6186 goto out;
6187
6188 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6189 &peer_pa_tactivate);
6190 if (ret)
6191 goto out;
6192
6193 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6194 peer_pa_tactivate_us = peer_pa_tactivate *
6195 gran_to_us_table[peer_granularity - 1];
6196
6197 if (pa_tactivate_us > peer_pa_tactivate_us) {
6198 u32 new_peer_pa_tactivate;
6199
6200 new_peer_pa_tactivate = pa_tactivate_us /
6201 gran_to_us_table[peer_granularity - 1];
6202 new_peer_pa_tactivate++;
6203 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6204 new_peer_pa_tactivate);
6205 }
6206
6207out:
6208 return ret;
6209}
6210
37113106
YG		 6211static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6212{
6213 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6214 ufshcd_tune_pa_tactivate(hba);
6215 ufshcd_tune_pa_hibern8time(hba);
6216 }
6217
6218 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6219 /* set 1ms timeout for PA_TACTIVATE */
6220 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43
SJ		 6221
6222 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6223 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6224
6225 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6226}
6227
ff8e20c6
DR		 6228static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6229{
6230 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6231
6232 hba->ufs_stats.hibern8_exit_cnt = 0;
6233 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6234
6235 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6236 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6237 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6238 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6239 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB		 6240
6241 hba->req_abort_count = 0;
ff8e20c6
DR		 6242}
6243
6ccf44fe 6244/**
1d337ec2
SRT		 6245 * ufshcd_probe_hba - probe hba to detect device and initialize
6246 * @hba: per-adapter instance
6247 *
6248 * Execute link-startup and verify device initialization
6ccf44fe 6249 */
1d337ec2 6250static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6251{
93fdd5ac 6252 struct ufs_dev_desc card = {0};
6ccf44fe 6253 int ret;
7ff5ab47 6254 ktime_t start = ktime_get();
6ccf44fe
SJ		 6255
6256 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6257 if (ret)
6258 goto out;
6259
afdfff59
YG		 6260 /* set the default level for urgent bkops */
6261 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6262 hba->is_urgent_bkops_lvl_checked = false;
6263
ff8e20c6
DR		 6264 /* Debug counters initialization */
6265 ufshcd_clear_dbg_ufs_stats(hba);
6266
57d104c1
SJ		 6267 /* UniPro link is active now */
6268 ufshcd_set_link_active(hba);
d3e89bac 6269
5a0b0cb9
SRT		 6270 ret = ufshcd_verify_dev_init(hba);
6271 if (ret)
6272 goto out;
68078d5c
DR		 6273
6274 ret = ufshcd_complete_dev_init(hba);
6275 if (ret)
6276 goto out;
5a0b0cb9 6277
93fdd5ac
TW		 6278 ret = ufs_get_device_desc(hba, &card);
6279 if (ret) {
6280 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6281 __func__, ret);
6282 goto out;
6283 }
6284
6285 ufs_fixup_device_setup(hba, &card);
37113106 6286 ufshcd_tune_unipro_params(hba);
60f01870
YG		 6287
6288 ret = ufshcd_set_vccq_rail_unused(hba,
6289 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6290 if (ret)
6291 goto out;
6292
57d104c1
SJ		 6293 /* UFS device is also active now */
6294 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6295 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6296 hba->wlun_dev_clr_ua = true;
6297
7eb584db
DR		 6298 if (ufshcd_get_max_pwr_mode(hba)) {
6299 dev_err(hba->dev,
6300 "%s: Failed getting max supported power mode\n",
6301 __func__);
6302 } else {
6303 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6304 if (ret) {
7eb584db
DR		 6305 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6306 __func__, ret);
8643ae66
DL		 6307 goto out;
6308 }
7eb584db 6309 }
57d104c1 6310
53c12d0e
YG		 6311 /* set the state as operational after switching to desired gear */
6312 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 6313 /*
6314 * If we are in error handling context or in power management callbacks
6315 * context, no need to scan the host
6316 */
6317 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6318 bool flag;
6319
6320 /* clear any previous UFS device information */
6321 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 6322 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6323 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6324 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6325
3a4bf06d
YG		 6326 if (!hba->is_init_prefetch)
6327 ufshcd_init_icc_levels(hba);
6328
2a8fa600
SJ		 6329 /* Add required well known logical units to scsi mid layer */
6330 if (ufshcd_scsi_add_wlus(hba))
6331 goto out;
6332
3441da7d
SRT		 6333 scsi_scan_host(hba->host);
6334 pm_runtime_put_sync(hba->dev);
6335 }
3a4bf06d 6336
fcb0c4b0
ST		 6337 /* Resume devfreq after UFS device is detected */
6338 if (ufshcd_is_clkscaling_supported(hba)) {
a3cd5ec5
SJ		 6339 memcpy(&hba->clk_scaling.saved_pwr_info.info, &hba->pwr_info,
6340 sizeof(struct ufs_pa_layer_attr));
6341 hba->clk_scaling.saved_pwr_info.is_valid = true;
fcb0c4b0
ST		 6342 ufshcd_resume_clkscaling(hba);
6343 hba->clk_scaling.is_allowed = true;
6344 }
6345
3a4bf06d
YG		 6346 if (!hba->is_init_prefetch)
6347 hba->is_init_prefetch = true;
6348
5a0b0cb9 6349out:
1d337ec2
SRT		 6350 /*
6351 * If we failed to initialize the device or the device is not
6352 * present, turn off the power/clocks etc.
6353 */
57d104c1
SJ		 6354 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6355 pm_runtime_put_sync(hba->dev);
1d337ec2 6356 ufshcd_hba_exit(hba);
57d104c1 6357 }
1d337ec2 6358
7ff5ab47
SJ		 6359 trace_ufshcd_init(dev_name(hba->dev), ret,
6360 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6361 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 6362 return ret;
6363}
6364
6365/**
6366 * ufshcd_async_scan - asynchronous execution for probing hba
6367 * @data: data pointer to pass to this function
6368 * @cookie: cookie data
6369 */
6370static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6371{
6372 struct ufs_hba *hba = (struct ufs_hba *)data;
6373
6374 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 6375}
6376
f550c65b
YG		 6377static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6378{
6379 unsigned long flags;
6380 struct Scsi_Host *host;
6381 struct ufs_hba *hba;
6382 int index;
6383 bool found = false;
6384
6385 if (!scmd || !scmd->device || !scmd->device->host)
6386 return BLK_EH_NOT_HANDLED;
6387
6388 host = scmd->device->host;
6389 hba = shost_priv(host);
6390 if (!hba)
6391 return BLK_EH_NOT_HANDLED;
6392
6393 spin_lock_irqsave(host->host_lock, flags);
6394
6395 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6396 if (hba->lrb[index].cmd == scmd) {
6397 found = true;
6398 break;
6399 }
6400 }
6401
6402 spin_unlock_irqrestore(host->host_lock, flags);
6403
6404 /*
6405 * Bypass SCSI error handling and reset the block layer timer if this
6406 * SCSI command was not actually dispatched to UFS driver, otherwise
6407 * let SCSI layer handle the error as usual.
6408 */
6409 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
6410}
6411
7a3e97b0
SY		 6412static struct scsi_host_template ufshcd_driver_template = {
6413 .module = THIS_MODULE,
6414 .name = UFSHCD,
6415 .proc_name = UFSHCD,
6416 .queuecommand = ufshcd_queuecommand,
6417 .slave_alloc = ufshcd_slave_alloc,
eeda4749 6418 .slave_configure = ufshcd_slave_configure,
7a3e97b0 6419 .slave_destroy = ufshcd_slave_destroy,
4264fd61 6420 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 6421 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 6422 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6423 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 6424 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 6425 .this_id = -1,
6426 .sg_tablesize = SG_ALL,
6427 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6428 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 6429 .max_host_blocked = 1,
c40ecc12 6430 .track_queue_depth = 1,
7a3e97b0
SY		 6431};
6432
57d104c1
SJ		 6433static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6434 int ua)
6435{
7b16a07c 6436 int ret;
57d104c1 6437
7b16a07c
BA		 6438 if (!vreg)
6439 return 0;
57d104c1 6440
7b16a07c
BA		 6441 ret = regulator_set_load(vreg->reg, ua);
6442 if (ret < 0) {
6443 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6444 __func__, vreg->name, ua, ret);
57d104c1
SJ		 6445 }
6446
6447 return ret;
6448}
6449
6450static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6451 struct ufs_vreg *vreg)
6452{
60f01870
YG		 6453 if (!vreg)
6454 return 0;
6455 else if (vreg->unused)
6456 return 0;
6457 else
6458 return ufshcd_config_vreg_load(hba->dev, vreg,
6459 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 6460}
6461
6462static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6463 struct ufs_vreg *vreg)
6464{
60f01870
YG		 6465 if (!vreg)
6466 return 0;
6467 else if (vreg->unused)
6468 return 0;
6469 else
6470 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 6471}
6472
aa497613
SRT		 6473static int ufshcd_config_vreg(struct device *dev,
6474 struct ufs_vreg *vreg, bool on)
6475{
6476 int ret = 0;
6477 struct regulator *reg = vreg->reg;
6478 const char *name = vreg->name;
6479 int min_uV, uA_load;
6480
6481 BUG_ON(!vreg);
6482
6483 if (regulator_count_voltages(reg) > 0) {
6484 min_uV = on ? vreg->min_uV : 0;
6485 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6486 if (ret) {
6487 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6488 __func__, name, ret);
6489 goto out;
6490 }
6491
6492 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 6493 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6494 if (ret)
aa497613 6495 goto out;
aa497613
SRT		 6496 }
6497out:
6498 return ret;
6499}
6500
6501static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6502{
6503 int ret = 0;
6504
60f01870
YG		 6505 if (!vreg)
6506 goto out;
6507 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 6508 goto out;
6509
6510 ret = ufshcd_config_vreg(dev, vreg, true);
6511 if (!ret)
6512 ret = regulator_enable(vreg->reg);
6513
6514 if (!ret)
6515 vreg->enabled = true;
6516 else
6517 dev_err(dev, "%s: %s enable failed, err=%d\n",
6518 __func__, vreg->name, ret);
6519out:
6520 return ret;
6521}
6522
6523static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
6524{
6525 int ret = 0;
6526
60f01870
YG		 6527 if (!vreg)
6528 goto out;
6529 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 6530 goto out;
6531
6532 ret = regulator_disable(vreg->reg);
6533
6534 if (!ret) {
6535 /* ignore errors on applying disable config */
6536 ufshcd_config_vreg(dev, vreg, false);
6537 vreg->enabled = false;
6538 } else {
6539 dev_err(dev, "%s: %s disable failed, err=%d\n",
6540 __func__, vreg->name, ret);
6541 }
6542out:
6543 return ret;
6544}
6545
6546static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
6547{
6548 int ret = 0;
6549 struct device *dev = hba->dev;
6550 struct ufs_vreg_info *info = &hba->vreg_info;
6551
6552 if (!info)
6553 goto out;
6554
6555 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
6556 if (ret)
6557 goto out;
6558
6559 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
6560 if (ret)
6561 goto out;
6562
6563 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
6564 if (ret)
6565 goto out;
6566
6567out:
6568 if (ret) {
6569 ufshcd_toggle_vreg(dev, info->vccq2, false);
6570 ufshcd_toggle_vreg(dev, info->vccq, false);
6571 ufshcd_toggle_vreg(dev, info->vcc, false);
6572 }
6573 return ret;
6574}
6575
6a771a65
RS		 6576static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
6577{
6578 struct ufs_vreg_info *info = &hba->vreg_info;
6579
6580 if (info)
6581 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6582
6583 return 0;
6584}
6585
aa497613
SRT		 6586static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
6587{
6588 int ret = 0;
6589
6590 if (!vreg)
6591 goto out;
6592
6593 vreg->reg = devm_regulator_get(dev, vreg->name);
6594 if (IS_ERR(vreg->reg)) {
6595 ret = PTR_ERR(vreg->reg);
6596 dev_err(dev, "%s: %s get failed, err=%d\n",
6597 __func__, vreg->name, ret);
6598 }
6599out:
6600 return ret;
6601}
6602
6603static int ufshcd_init_vreg(struct ufs_hba *hba)
6604{
6605 int ret = 0;
6606 struct device *dev = hba->dev;
6607 struct ufs_vreg_info *info = &hba->vreg_info;
6608
6609 if (!info)
6610 goto out;
6611
6612 ret = ufshcd_get_vreg(dev, info->vcc);
6613 if (ret)
6614 goto out;
6615
6616 ret = ufshcd_get_vreg(dev, info->vccq);
6617 if (ret)
6618 goto out;
6619
6620 ret = ufshcd_get_vreg(dev, info->vccq2);
6621out:
6622 return ret;
6623}
6624
6a771a65
RS		 6625static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
6626{
6627 struct ufs_vreg_info *info = &hba->vreg_info;
6628
6629 if (info)
6630 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
6631
6632 return 0;
6633}
6634
60f01870
YG		 6635static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
6636{
6637 int ret = 0;
6638 struct ufs_vreg_info *info = &hba->vreg_info;
6639
6640 if (!info)
6641 goto out;
6642 else if (!info->vccq)
6643 goto out;
6644
6645 if (unused) {
6646 /* shut off the rail here */
6647 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
6648 /*
6649 * Mark this rail as no longer used, so it doesn't get enabled
6650 * later by mistake
6651 */
6652 if (!ret)
6653 info->vccq->unused = true;
6654 } else {
6655 /*
6656 * rail should have been already enabled hence just make sure
6657 * that unused flag is cleared.
6658 */
6659 info->vccq->unused = false;
6660 }
6661out:
6662 return ret;
6663}
6664
57d104c1
SJ		 6665static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
6666 bool skip_ref_clk)
c6e79dac
SRT		 6667{
6668 int ret = 0;
6669 struct ufs_clk_info *clki;
6670 struct list_head *head = &hba->clk_list_head;
1ab27c9c 6671 unsigned long flags;
911a0771
SJ		 6672 ktime_t start = ktime_get();
6673 bool clk_state_changed = false;
c6e79dac
SRT		 6674
6675 if (!head || list_empty(head))
6676 goto out;
6677
1e879e8f
SJ		 6678 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
6679 if (ret)
6680 return ret;
6681
c6e79dac
SRT		 6682 list_for_each_entry(clki, head, list) {
6683 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 6684 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
6685 continue;
6686
911a0771 6687 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 6688 if (on && !clki->enabled) {
6689 ret = clk_prepare_enable(clki->clk);
6690 if (ret) {
6691 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
6692 __func__, clki->name, ret);
6693 goto out;
6694 }
6695 } else if (!on && clki->enabled) {
6696 clk_disable_unprepare(clki->clk);
6697 }
6698 clki->enabled = on;
6699 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
6700 clki->name, on ? "en" : "dis");
6701 }
6702 }
1ab27c9c 6703
1e879e8f
SJ		 6704 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
6705 if (ret)
6706 return ret;
6707
c6e79dac
SRT		 6708out:
6709 if (ret) {
6710 list_for_each_entry(clki, head, list) {
6711 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
6712 clk_disable_unprepare(clki->clk);
6713 }
7ff5ab47 6714 } else if (!ret && on) {
1ab27c9c
ST		 6715 spin_lock_irqsave(hba->host->host_lock, flags);
6716 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 6717 trace_ufshcd_clk_gating(dev_name(hba->dev),
6718 hba->clk_gating.state);
1ab27c9c 6719 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 6720 }
7ff5ab47 6721
911a0771
SJ		 6722 if (clk_state_changed)
6723 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
6724 (on ? "on" : "off"),
6725 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 6726 return ret;
6727}
6728
57d104c1
SJ		 6729static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
6730{
6731 return __ufshcd_setup_clocks(hba, on, false);
6732}
6733
c6e79dac
SRT		 6734static int ufshcd_init_clocks(struct ufs_hba *hba)
6735{
6736 int ret = 0;
6737 struct ufs_clk_info *clki;
6738 struct device *dev = hba->dev;
6739 struct list_head *head = &hba->clk_list_head;
6740
6741 if (!head || list_empty(head))
6742 goto out;
6743
6744 list_for_each_entry(clki, head, list) {
6745 if (!clki->name)
6746 continue;
6747
6748 clki->clk = devm_clk_get(dev, clki->name);
6749 if (IS_ERR(clki->clk)) {
6750 ret = PTR_ERR(clki->clk);
6751 dev_err(dev, "%s: %s clk get failed, %d\n",
6752 __func__, clki->name, ret);
6753 goto out;
6754 }
6755
6756 if (clki->max_freq) {
6757 ret = clk_set_rate(clki->clk, clki->max_freq);
6758 if (ret) {
6759 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6760 __func__, clki->name,
6761 clki->max_freq, ret);
6762 goto out;
6763 }
856b3483 6764 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 6765 }
6766 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
6767 clki->name, clk_get_rate(clki->clk));
6768 }
6769out:
6770 return ret;
6771}
6772
5c0c28a8
SRT		 6773static int ufshcd_variant_hba_init(struct ufs_hba *hba)
6774{
6775 int err = 0;
6776
6777 if (!hba->vops)
6778 goto out;
6779
0263bcd0
YG		 6780 err = ufshcd_vops_init(hba);
6781 if (err)
6782 goto out;
5c0c28a8 6783
0263bcd0
YG		 6784 err = ufshcd_vops_setup_regulators(hba, true);
6785 if (err)
6786 goto out_exit;
5c0c28a8
SRT		 6787
6788 goto out;
6789
5c0c28a8 6790out_exit:
0263bcd0 6791 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 6792out:
6793 if (err)
6794 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 6795 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 6796 return err;
6797}
6798
6799static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
6800{
6801 if (!hba->vops)
6802 return;
6803
0263bcd0 6804 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 6805
0263bcd0 6806 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 6807}
6808
aa497613
SRT		 6809static int ufshcd_hba_init(struct ufs_hba *hba)
6810{
6811 int err;
6812
6a771a65
RS		 6813 /*
6814 * Handle host controller power separately from the UFS device power
6815 * rails as it will help controlling the UFS host controller power
6816 * collapse easily which is different than UFS device power collapse.
6817 * Also, enable the host controller power before we go ahead with rest
6818 * of the initialization here.
6819 */
6820 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 6821 if (err)
6822 goto out;
6823
6a771a65 6824 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 6825 if (err)
6826 goto out;
6827
6a771a65
RS		 6828 err = ufshcd_init_clocks(hba);
6829 if (err)
6830 goto out_disable_hba_vreg;
6831
6832 err = ufshcd_setup_clocks(hba, true);
6833 if (err)
6834 goto out_disable_hba_vreg;
6835
c6e79dac
SRT		 6836 err = ufshcd_init_vreg(hba);
6837 if (err)
6838 goto out_disable_clks;
6839
6840 err = ufshcd_setup_vreg(hba, true);
6841 if (err)
6842 goto out_disable_clks;
6843
aa497613
SRT		 6844 err = ufshcd_variant_hba_init(hba);
6845 if (err)
6846 goto out_disable_vreg;
6847
1d337ec2 6848 hba->is_powered = true;
aa497613
SRT		 6849 goto out;
6850
6851out_disable_vreg:
6852 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 6853out_disable_clks:
6854 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 6855out_disable_hba_vreg:
6856 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 6857out:
6858 return err;
6859}
6860
6861static void ufshcd_hba_exit(struct ufs_hba *hba)
6862{
1d337ec2
SRT		 6863 if (hba->is_powered) {
6864 ufshcd_variant_hba_exit(hba);
6865 ufshcd_setup_vreg(hba, false);
a508253d 6866 ufshcd_suspend_clkscaling(hba);
401f1e44
SJ		 6867 if (ufshcd_is_clkscaling_supported(hba)) {
6868 ufshcd_suspend_clkscaling(hba);
6869 destroy_workqueue(hba->clk_scaling.workq);
6870 }
1d337ec2
SRT		 6871 ufshcd_setup_clocks(hba, false);
6872 ufshcd_setup_hba_vreg(hba, false);
6873 hba->is_powered = false;
6874 }
aa497613
SRT		 6875}
6876
57d104c1
SJ		 6877static int
6878ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
6879{
6880 unsigned char cmd[6] = {REQUEST_SENSE,
6881 0,
6882 0,
6883 0,
dcea0bfb 6884 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 6885 0};
6886 char *buffer;
6887 int ret;
6888
dcea0bfb 6889 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 6890 if (!buffer) {
6891 ret = -ENOMEM;
6892 goto out;
6893 }
6894
6895 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
dcea0bfb 6896 UFSHCD_REQ_SENSE_SIZE, NULL,
e8064021 6897 msecs_to_jiffies(1000), 3, NULL, 0, RQF_PM);
57d104c1
SJ		 6898 if (ret)
6899 pr_err("%s: failed with err %d\n", __func__, ret);
6900
6901 kfree(buffer);
6902out:
6903 return ret;
6904}
6905
6906/**
6907 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
6908 * power mode
6909 * @hba: per adapter instance
6910 * @pwr_mode: device power mode to set
6911 *
6912 * Returns 0 if requested power mode is set successfully
6913 * Returns non-zero if failed to set the requested power mode
6914 */
6915static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
6916 enum ufs_dev_pwr_mode pwr_mode)
6917{
6918 unsigned char cmd[6] = { START_STOP };
6919 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 6920 struct scsi_device *sdp;
6921 unsigned long flags;
57d104c1
SJ		 6922 int ret;
6923
7c48bfd0
AM		 6924 spin_lock_irqsave(hba->host->host_lock, flags);
6925 sdp = hba->sdev_ufs_device;
6926 if (sdp) {
6927 ret = scsi_device_get(sdp);
6928 if (!ret && !scsi_device_online(sdp)) {
6929 ret = -ENODEV;
6930 scsi_device_put(sdp);
6931 }
6932 } else {
6933 ret = -ENODEV;
6934 }
6935 spin_unlock_irqrestore(hba->host->host_lock, flags);
6936
6937 if (ret)
6938 return ret;
57d104c1
SJ		 6939
6940 /*
6941 * If scsi commands fail, the scsi mid-layer schedules scsi error-
6942 * handling, which would wait for host to be resumed. Since we know
6943 * we are functional while we are here, skip host resume in error
6944 * handling context.
6945 */
6946 hba->host->eh_noresume = 1;
6947 if (hba->wlun_dev_clr_ua) {
6948 ret = ufshcd_send_request_sense(hba, sdp);
6949 if (ret)
6950 goto out;
6951 /* Unit attention condition is cleared now */
6952 hba->wlun_dev_clr_ua = false;
6953 }
6954
6955 cmd[4] = pwr_mode << 4;
6956
6957 /*
6958 * Current function would be generally called from the power management
e8064021 6959 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 6960 * already suspended childs.
6961 */
6962 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
e8064021 6963 START_STOP_TIMEOUT, 0, NULL, 0, RQF_PM);
57d104c1
SJ		 6964 if (ret) {
6965 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 6966 "START_STOP failed for power mode: %d, result %x\n",
6967 pwr_mode, ret);
21045519
HR		 6968 if (driver_byte(ret) & DRIVER_SENSE)
6969 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 6970 }
6971
6972 if (!ret)
6973 hba->curr_dev_pwr_mode = pwr_mode;
6974out:
7c48bfd0 6975 scsi_device_put(sdp);
57d104c1
SJ		 6976 hba->host->eh_noresume = 0;
6977 return ret;
6978}
6979
6980static int ufshcd_link_state_transition(struct ufs_hba *hba,
6981 enum uic_link_state req_link_state,
6982 int check_for_bkops)
6983{
6984 int ret = 0;
6985
6986 if (req_link_state == hba->uic_link_state)
6987 return 0;
6988
6989 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
6990 ret = ufshcd_uic_hibern8_enter(hba);
6991 if (!ret)
6992 ufshcd_set_link_hibern8(hba);
6993 else
6994 goto out;
6995 }
6996 /*
6997 * If autobkops is enabled, link can't be turned off because
6998 * turning off the link would also turn off the device.
6999 */
7000 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7001 (!check_for_bkops || (check_for_bkops &&
7002 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 7003 /*
7004 * Let's make sure that link is in low power mode, we are doing
7005 * this currently by putting the link in Hibern8. Otherway to
7006 * put the link in low power mode is to send the DME end point
7007 * to device and then send the DME reset command to local
7008 * unipro. But putting the link in hibern8 is much faster.
7009 */
7010 ret = ufshcd_uic_hibern8_enter(hba);
7011 if (ret)
7012 goto out;
57d104c1
SJ		 7013 /*
7014 * Change controller state to "reset state" which
7015 * should also put the link in off/reset state
7016 */
596585a2 7017 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 7018 /*
7019 * TODO: Check if we need any delay to make sure that
7020 * controller is reset
7021 */
7022 ufshcd_set_link_off(hba);
7023 }
7024
7025out:
7026 return ret;
7027}
7028
7029static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7030{
b799fdf7
YG		 7031 /*
7032 * It seems some UFS devices may keep drawing more than sleep current
7033 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7034 * To avoid this situation, add 2ms delay before putting these UFS
7035 * rails in LPM mode.
7036 */
7037 if (!ufshcd_is_link_active(hba) &&
7038 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7039 usleep_range(2000, 2100);
7040
57d104c1
SJ		 7041 /*
7042 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7043 * power.
7044 *
7045 * If UFS device and link is in OFF state, all power supplies (VCC,
7046 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7047 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7048 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7049 *
7050 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7051 * in low power state which would save some power.
7052 */
7053 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7054 !hba->dev_info.is_lu_power_on_wp) {
7055 ufshcd_setup_vreg(hba, false);
7056 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7057 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7058 if (!ufshcd_is_link_active(hba)) {
7059 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7060 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7061 }
7062 }
7063}
7064
7065static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7066{
7067 int ret = 0;
7068
7069 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7070 !hba->dev_info.is_lu_power_on_wp) {
7071 ret = ufshcd_setup_vreg(hba, true);
7072 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7073 if (!ret && !ufshcd_is_link_active(hba)) {
7074 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7075 if (ret)
7076 goto vcc_disable;
7077 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7078 if (ret)
7079 goto vccq_lpm;
7080 }
69d72ac8 7081 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7082 }
7083 goto out;
7084
7085vccq_lpm:
7086 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7087vcc_disable:
7088 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7089out:
7090 return ret;
7091}
7092
7093static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7094{
7095 if (ufshcd_is_link_off(hba))
7096 ufshcd_setup_hba_vreg(hba, false);
7097}
7098
7099static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7100{
7101 if (ufshcd_is_link_off(hba))
7102 ufshcd_setup_hba_vreg(hba, true);
7103}
7104
7a3e97b0 7105/**
57d104c1 7106 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7107 * @hba: per adapter instance
57d104c1
SJ		 7108 * @pm_op: desired low power operation type
7109 *
7110 * This function will try to put the UFS device and link into low power
7111 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7112 * (System PM level).
7113 *
7114 * If this function is called during shutdown, it will make sure that
7115 * both UFS device and UFS link is powered off.
7a3e97b0 7116 *
57d104c1
SJ		 7117 * NOTE: UFS device & link must be active before we enter in this function.
7118 *
7119 * Returns 0 for success and non-zero for failure
7a3e97b0 7120 */
57d104c1 7121static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7122{
57d104c1
SJ		 7123 int ret = 0;
7124 enum ufs_pm_level pm_lvl;
7125 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7126 enum uic_link_state req_link_state;
7127
7128 hba->pm_op_in_progress = 1;
7129 if (!ufshcd_is_shutdown_pm(pm_op)) {
7130 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7131 hba->rpm_lvl : hba->spm_lvl;
7132 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7133 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7134 } else {
7135 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7136 req_link_state = UIC_LINK_OFF_STATE;
7137 }
7138
7a3e97b0 7139 /*
57d104c1
SJ		 7140 * If we can't transition into any of the low power modes
7141 * just gate the clocks.
7a3e97b0 7142 */
1ab27c9c
ST		 7143 ufshcd_hold(hba, false);
7144 hba->clk_gating.is_suspended = true;
7145
401f1e44
SJ		 7146 if (hba->clk_scaling.is_allowed) {
7147 cancel_work_sync(&hba->clk_scaling.suspend_work);
7148 cancel_work_sync(&hba->clk_scaling.resume_work);
7149 ufshcd_suspend_clkscaling(hba);
7150 }
d6fcf81a 7151
57d104c1
SJ		 7152 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7153 req_link_state == UIC_LINK_ACTIVE_STATE) {
7154 goto disable_clks;
7155 }
7a3e97b0 7156
57d104c1
SJ		 7157 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7158 (req_link_state == hba->uic_link_state))
d6fcf81a 7159 goto enable_gating;
57d104c1
SJ		 7160
7161 /* UFS device & link must be active before we enter in this function */
7162 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7163 ret = -EINVAL;
d6fcf81a 7164 goto enable_gating;
57d104c1
SJ		 7165 }
7166
7167 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7168 if (ufshcd_can_autobkops_during_suspend(hba)) {
7169 /*
7170 * The device is idle with no requests in the queue,
7171 * allow background operations if bkops status shows
7172 * that performance might be impacted.
7173 */
7174 ret = ufshcd_urgent_bkops(hba);
7175 if (ret)
7176 goto enable_gating;
7177 } else {
7178 /* make sure that auto bkops is disabled */
7179 ufshcd_disable_auto_bkops(hba);
7180 }
57d104c1
SJ		 7181 }
7182
7183 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7184 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7185 !ufshcd_is_runtime_pm(pm_op))) {
7186 /* ensure that bkops is disabled */
7187 ufshcd_disable_auto_bkops(hba);
7188 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7189 if (ret)
1ab27c9c 7190 goto enable_gating;
57d104c1
SJ		 7191 }
7192
7193 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7194 if (ret)
7195 goto set_dev_active;
7196
7197 ufshcd_vreg_set_lpm(hba);
7198
7199disable_clks:
7200 /*
7201 * Call vendor specific suspend callback. As these callbacks may access
7202 * vendor specific host controller register space call them before the
7203 * host clocks are ON.
7204 */
0263bcd0
YG		 7205 ret = ufshcd_vops_suspend(hba, pm_op);
7206 if (ret)
7207 goto set_link_active;
57d104c1 7208
57d104c1
SJ		 7209 if (!ufshcd_is_link_active(hba))
7210 ufshcd_setup_clocks(hba, false);
7211 else
7212 /* If link is active, device ref_clk can't be switched off */
7213 __ufshcd_setup_clocks(hba, false, true);
7214
1ab27c9c 7215 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7216 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1
SJ		 7217 /*
7218 * Disable the host irq as host controller as there won't be any
0263bcd0 7219 * host controller transaction expected till resume.
57d104c1
SJ		 7220 */
7221 ufshcd_disable_irq(hba);
7222 /* Put the host controller in low power mode if possible */
7223 ufshcd_hba_vreg_set_lpm(hba);
7224 goto out;
7225
57d104c1 7226set_link_active:
401f1e44
SJ		 7227 if (hba->clk_scaling.is_allowed)
7228 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 7229 ufshcd_vreg_set_hpm(hba);
7230 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7231 ufshcd_set_link_active(hba);
7232 else if (ufshcd_is_link_off(hba))
7233 ufshcd_host_reset_and_restore(hba);
7234set_dev_active:
7235 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7236 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7237enable_gating:
401f1e44
SJ		 7238 if (hba->clk_scaling.is_allowed)
7239 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7240 hba->clk_gating.is_suspended = false;
7241 ufshcd_release(hba);
57d104c1
SJ		 7242out:
7243 hba->pm_op_in_progress = 0;
7244 return ret;
7a3e97b0
SY		 7245}
7246
7247/**
57d104c1 7248 * ufshcd_resume - helper function for resume operations
3b1d0580 7249 * @hba: per adapter instance
57d104c1 7250 * @pm_op: runtime PM or system PM
7a3e97b0 7251 *
57d104c1
SJ		 7252 * This function basically brings the UFS device, UniPro link and controller
7253 * to active state.
7254 *
7255 * Returns 0 for success and non-zero for failure
7a3e97b0 7256 */
57d104c1 7257static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7258{
57d104c1
SJ		 7259 int ret;
7260 enum uic_link_state old_link_state;
7261
7262 hba->pm_op_in_progress = 1;
7263 old_link_state = hba->uic_link_state;
7264
7265 ufshcd_hba_vreg_set_hpm(hba);
7266 /* Make sure clocks are enabled before accessing controller */
7267 ret = ufshcd_setup_clocks(hba, true);
7268 if (ret)
7269 goto out;
7270
57d104c1
SJ		 7271 /* enable the host irq as host controller would be active soon */
7272 ret = ufshcd_enable_irq(hba);
7273 if (ret)
7274 goto disable_irq_and_vops_clks;
7275
7276 ret = ufshcd_vreg_set_hpm(hba);
7277 if (ret)
7278 goto disable_irq_and_vops_clks;
7279
7a3e97b0 7280 /*
57d104c1
SJ		 7281 * Call vendor specific resume callback. As these callbacks may access
7282 * vendor specific host controller register space call them when the
7283 * host clocks are ON.
7a3e97b0 7284 */
0263bcd0
YG		 7285 ret = ufshcd_vops_resume(hba, pm_op);
7286 if (ret)
7287 goto disable_vreg;
57d104c1
SJ		 7288
7289 if (ufshcd_is_link_hibern8(hba)) {
7290 ret = ufshcd_uic_hibern8_exit(hba);
7291 if (!ret)
7292 ufshcd_set_link_active(hba);
7293 else
7294 goto vendor_suspend;
7295 } else if (ufshcd_is_link_off(hba)) {
7296 ret = ufshcd_host_reset_and_restore(hba);
7297 /*
7298 * ufshcd_host_reset_and_restore() should have already
7299 * set the link state as active
7300 */
7301 if (ret || !ufshcd_is_link_active(hba))
7302 goto vendor_suspend;
7303 }
7304
7305 if (!ufshcd_is_ufs_dev_active(hba)) {
7306 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7307 if (ret)
7308 goto set_old_link_state;
7309 }
7310
4e768e76
SJ		 7311 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7312 ufshcd_enable_auto_bkops(hba);
7313 else
7314 /*
7315 * If BKOPs operations are urgently needed at this moment then
7316 * keep auto-bkops enabled or else disable it.
7317 */
7318 ufshcd_urgent_bkops(hba);
7319
1ab27c9c
ST		 7320 hba->clk_gating.is_suspended = false;
7321
fcb0c4b0
ST		 7322 if (hba->clk_scaling.is_allowed)
7323 ufshcd_resume_clkscaling(hba);
856b3483 7324
1ab27c9c
ST		 7325 /* Schedule clock gating in case of no access to UFS device yet */
7326 ufshcd_release(hba);
57d104c1
SJ		 7327 goto out;
7328
7329set_old_link_state:
7330 ufshcd_link_state_transition(hba, old_link_state, 0);
7331vendor_suspend:
0263bcd0 7332 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 7333disable_vreg:
7334 ufshcd_vreg_set_lpm(hba);
7335disable_irq_and_vops_clks:
7336 ufshcd_disable_irq(hba);
401f1e44
SJ		 7337 if (hba->clk_scaling.is_allowed)
7338 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 7339 ufshcd_setup_clocks(hba, false);
7340out:
7341 hba->pm_op_in_progress = 0;
7342 return ret;
7343}
7344
7345/**
7346 * ufshcd_system_suspend - system suspend routine
7347 * @hba: per adapter instance
7348 * @pm_op: runtime PM or system PM
7349 *
7350 * Check the description of ufshcd_suspend() function for more details.
7351 *
7352 * Returns 0 for success and non-zero for failure
7353 */
7354int ufshcd_system_suspend(struct ufs_hba *hba)
7355{
7356 int ret = 0;
7ff5ab47 7357 ktime_t start = ktime_get();
57d104c1
SJ		 7358
7359 if (!hba || !hba->is_powered)
233b594b 7360 return 0;
57d104c1 7361
0b257734
SJ		 7362 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7363 hba->curr_dev_pwr_mode) &&
7364 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7365 hba->uic_link_state))
7366 goto out;
57d104c1 7367
0b257734 7368 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 7369 /*
7370 * UFS device and/or UFS link low power states during runtime
7371 * suspend seems to be different than what is expected during
7372 * system suspend. Hence runtime resume the devic & link and
7373 * let the system suspend low power states to take effect.
7374 * TODO: If resume takes longer time, we might have optimize
7375 * it in future by not resuming everything if possible.
7376 */
7377 ret = ufshcd_runtime_resume(hba);
7378 if (ret)
7379 goto out;
7380 }
7381
7382 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7383out:
7ff5ab47
SJ		 7384 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7385 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7386 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 7387 if (!ret)
7388 hba->is_sys_suspended = true;
57d104c1
SJ		 7389 return ret;
7390}
7391EXPORT_SYMBOL(ufshcd_system_suspend);
7392
7393/**
7394 * ufshcd_system_resume - system resume routine
7395 * @hba: per adapter instance
7396 *
7397 * Returns 0 for success and non-zero for failure
7398 */
7a3e97b0 7399
57d104c1
SJ		 7400int ufshcd_system_resume(struct ufs_hba *hba)
7401{
7ff5ab47
SJ		 7402 int ret = 0;
7403 ktime_t start = ktime_get();
7404
e3ce73d6
YG		 7405 if (!hba)
7406 return -EINVAL;
7407
7408 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 7409 /*
7410 * Let the runtime resume take care of resuming
7411 * if runtime suspended.
7412 */
7ff5ab47
SJ		 7413 goto out;
7414 else
7415 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7416out:
7417 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7418 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7419 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7420 return ret;
7a3e97b0 7421}
57d104c1 7422EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 7423
57d104c1
SJ		 7424/**
7425 * ufshcd_runtime_suspend - runtime suspend routine
7426 * @hba: per adapter instance
7427 *
7428 * Check the description of ufshcd_suspend() function for more details.
7429 *
7430 * Returns 0 for success and non-zero for failure
7431 */
66ec6d59
SRT		 7432int ufshcd_runtime_suspend(struct ufs_hba *hba)
7433{
7ff5ab47
SJ		 7434 int ret = 0;
7435 ktime_t start = ktime_get();
7436
e3ce73d6
YG		 7437 if (!hba)
7438 return -EINVAL;
7439
7440 if (!hba->is_powered)
7ff5ab47
SJ		 7441 goto out;
7442 else
7443 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7444out:
7445 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7446 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7447 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7448 return ret;
66ec6d59
SRT		 7449}
7450EXPORT_SYMBOL(ufshcd_runtime_suspend);
7451
57d104c1
SJ		 7452/**
7453 * ufshcd_runtime_resume - runtime resume routine
7454 * @hba: per adapter instance
7455 *
7456 * This function basically brings the UFS device, UniPro link and controller
7457 * to active state. Following operations are done in this function:
7458 *
7459 * 1. Turn on all the controller related clocks
7460 * 2. Bring the UniPro link out of Hibernate state
7461 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7462 * to active state.
7463 * 4. If auto-bkops is enabled on the device, disable it.
7464 *
7465 * So following would be the possible power state after this function return
7466 * successfully:
7467 * S1: UFS device in Active state with VCC rail ON
7468 * UniPro link in Active state
7469 * All the UFS/UniPro controller clocks are ON
7470 *
7471 * Returns 0 for success and non-zero for failure
7472 */
66ec6d59
SRT		 7473int ufshcd_runtime_resume(struct ufs_hba *hba)
7474{
7ff5ab47
SJ		 7475 int ret = 0;
7476 ktime_t start = ktime_get();
7477
e3ce73d6
YG		 7478 if (!hba)
7479 return -EINVAL;
7480
7481 if (!hba->is_powered)
7ff5ab47
SJ		 7482 goto out;
7483 else
7484 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7485out:
7486 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7487 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7488 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7489 return ret;
66ec6d59
SRT		 7490}
7491EXPORT_SYMBOL(ufshcd_runtime_resume);
7492
7493int ufshcd_runtime_idle(struct ufs_hba *hba)
7494{
7495 return 0;
7496}
7497EXPORT_SYMBOL(ufshcd_runtime_idle);
7498
09690d5a
SJ		 7499static inline ssize_t ufshcd_pm_lvl_store(struct device *dev,
7500 struct device_attribute *attr,
7501 const char *buf, size_t count,
7502 bool rpm)
7503{
7504 struct ufs_hba *hba = dev_get_drvdata(dev);
7505 unsigned long flags, value;
7506
7507 if (kstrtoul(buf, 0, &value))
7508 return -EINVAL;
7509
7510 if ((value < UFS_PM_LVL_0) || (value >= UFS_PM_LVL_MAX))
7511 return -EINVAL;
7512
7513 spin_lock_irqsave(hba->host->host_lock, flags);
7514 if (rpm)
7515 hba->rpm_lvl = value;
7516 else
7517 hba->spm_lvl = value;
7518 spin_unlock_irqrestore(hba->host->host_lock, flags);
7519 return count;
7520}
7521
7522static ssize_t ufshcd_rpm_lvl_show(struct device *dev,
7523 struct device_attribute *attr, char *buf)
7524{
7525 struct ufs_hba *hba = dev_get_drvdata(dev);
7526 int curr_len;
7527 u8 lvl;
7528
7529 curr_len = snprintf(buf, PAGE_SIZE,
7530 "\nCurrent Runtime PM level [%d] => dev_state [%s] link_state [%s]\n",
7531 hba->rpm_lvl,
7532 ufschd_ufs_dev_pwr_mode_to_string(
7533 ufs_pm_lvl_states[hba->rpm_lvl].dev_state),
7534 ufschd_uic_link_state_to_string(
7535 ufs_pm_lvl_states[hba->rpm_lvl].link_state));
7536
7537 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7538 "\nAll available Runtime PM levels info:\n");
7539 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7540 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7541 "\tRuntime PM level [%d] => dev_state [%s] link_state [%s]\n",
7542 lvl,
7543 ufschd_ufs_dev_pwr_mode_to_string(
7544 ufs_pm_lvl_states[lvl].dev_state),
7545 ufschd_uic_link_state_to_string(
7546 ufs_pm_lvl_states[lvl].link_state));
7547
7548 return curr_len;
7549}
7550
7551static ssize_t ufshcd_rpm_lvl_store(struct device *dev,
7552 struct device_attribute *attr, const char *buf, size_t count)
7553{
7554 return ufshcd_pm_lvl_store(dev, attr, buf, count, true);
7555}
7556
7557static void ufshcd_add_rpm_lvl_sysfs_nodes(struct ufs_hba *hba)
7558{
7559 hba->rpm_lvl_attr.show = ufshcd_rpm_lvl_show;
7560 hba->rpm_lvl_attr.store = ufshcd_rpm_lvl_store;
7561 sysfs_attr_init(&hba->rpm_lvl_attr.attr);
7562 hba->rpm_lvl_attr.attr.name = "rpm_lvl";
7563 hba->rpm_lvl_attr.attr.mode = 0644;
7564 if (device_create_file(hba->dev, &hba->rpm_lvl_attr))
7565 dev_err(hba->dev, "Failed to create sysfs for rpm_lvl\n");
7566}
7567
7568static ssize_t ufshcd_spm_lvl_show(struct device *dev,
7569 struct device_attribute *attr, char *buf)
7570{
7571 struct ufs_hba *hba = dev_get_drvdata(dev);
7572 int curr_len;
7573 u8 lvl;
7574
7575 curr_len = snprintf(buf, PAGE_SIZE,
7576 "\nCurrent System PM level [%d] => dev_state [%s] link_state [%s]\n",
7577 hba->spm_lvl,
7578 ufschd_ufs_dev_pwr_mode_to_string(
7579 ufs_pm_lvl_states[hba->spm_lvl].dev_state),
7580 ufschd_uic_link_state_to_string(
7581 ufs_pm_lvl_states[hba->spm_lvl].link_state));
7582
7583 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7584 "\nAll available System PM levels info:\n");
7585 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7586 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7587 "\tSystem PM level [%d] => dev_state [%s] link_state [%s]\n",
7588 lvl,
7589 ufschd_ufs_dev_pwr_mode_to_string(
7590 ufs_pm_lvl_states[lvl].dev_state),
7591 ufschd_uic_link_state_to_string(
7592 ufs_pm_lvl_states[lvl].link_state));
7593
7594 return curr_len;
7595}
7596
7597static ssize_t ufshcd_spm_lvl_store(struct device *dev,
7598 struct device_attribute *attr, const char *buf, size_t count)
7599{
7600 return ufshcd_pm_lvl_store(dev, attr, buf, count, false);
7601}
7602
7603static void ufshcd_add_spm_lvl_sysfs_nodes(struct ufs_hba *hba)
7604{
7605 hba->spm_lvl_attr.show = ufshcd_spm_lvl_show;
7606 hba->spm_lvl_attr.store = ufshcd_spm_lvl_store;
7607 sysfs_attr_init(&hba->spm_lvl_attr.attr);
7608 hba->spm_lvl_attr.attr.name = "spm_lvl";
7609 hba->spm_lvl_attr.attr.mode = 0644;
7610 if (device_create_file(hba->dev, &hba->spm_lvl_attr))
7611 dev_err(hba->dev, "Failed to create sysfs for spm_lvl\n");
7612}
7613
7614static inline void ufshcd_add_sysfs_nodes(struct ufs_hba *hba)
7615{
7616 ufshcd_add_rpm_lvl_sysfs_nodes(hba);
7617 ufshcd_add_spm_lvl_sysfs_nodes(hba);
7618}
7619
57d104c1
SJ		 7620/**
7621 * ufshcd_shutdown - shutdown routine
7622 * @hba: per adapter instance
7623 *
7624 * This function would power off both UFS device and UFS link.
7625 *
7626 * Returns 0 always to allow force shutdown even in case of errors.
7627 */
7628int ufshcd_shutdown(struct ufs_hba *hba)
7629{
7630 int ret = 0;
7631
7632 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
7633 goto out;
7634
7635 if (pm_runtime_suspended(hba->dev)) {
7636 ret = ufshcd_runtime_resume(hba);
7637 if (ret)
7638 goto out;
7639 }
7640
7641 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
7642out:
7643 if (ret)
7644 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
7645 /* allow force shutdown even in case of errors */
7646 return 0;
7647}
7648EXPORT_SYMBOL(ufshcd_shutdown);
7649
7a3e97b0 7650/**
3b1d0580 7651 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 7652 * data structure memory
3b1d0580 7653 * @hba - per adapter instance
7a3e97b0 7654 */
3b1d0580 7655void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 7656{
cfdf9c91 7657 scsi_remove_host(hba->host);
7a3e97b0 7658 /* disable interrupts */
2fbd009b 7659 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 7660 ufshcd_hba_stop(hba, true);
7a3e97b0 7661
1ab27c9c 7662 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 7663 if (ufshcd_is_clkscaling_supported(hba))
7664 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 7665 ufshcd_hba_exit(hba);
3b1d0580
VH		 7666}
7667EXPORT_SYMBOL_GPL(ufshcd_remove);
7668
47555a5c
YG		 7669/**
7670 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
7671 * @hba: pointer to Host Bus Adapter (HBA)
7672 */
7673void ufshcd_dealloc_host(struct ufs_hba *hba)
7674{
7675 scsi_host_put(hba->host);
7676}
7677EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
7678
ca3d7bf9
AM		 7679/**
7680 * ufshcd_set_dma_mask - Set dma mask based on the controller
7681 * addressing capability
7682 * @hba: per adapter instance
7683 *
7684 * Returns 0 for success, non-zero for failure
7685 */
7686static int ufshcd_set_dma_mask(struct ufs_hba *hba)
7687{
7688 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
7689 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
7690 return 0;
7691 }
7692 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
7693}
7694
7a3e97b0 7695/**
5c0c28a8 7696 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 7697 * @dev: pointer to device handle
7698 * @hba_handle: driver private handle
7a3e97b0
SY		 7699 * Returns 0 on success, non-zero value on failure
7700 */
5c0c28a8 7701int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 7702{
7703 struct Scsi_Host *host;
7704 struct ufs_hba *hba;
5c0c28a8 7705 int err = 0;
7a3e97b0 7706
3b1d0580
VH		 7707 if (!dev) {
7708 dev_err(dev,
7709 "Invalid memory reference for dev is NULL\n");
7710 err = -ENODEV;
7a3e97b0
SY		 7711 goto out_error;
7712 }
7713
7a3e97b0
SY		 7714 host = scsi_host_alloc(&ufshcd_driver_template,
7715 sizeof(struct ufs_hba));
7716 if (!host) {
3b1d0580 7717 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 7718 err = -ENOMEM;
3b1d0580 7719 goto out_error;
7a3e97b0
SY		 7720 }
7721 hba = shost_priv(host);
7a3e97b0 7722 hba->host = host;
3b1d0580 7723 hba->dev = dev;
5c0c28a8
SRT		 7724 *hba_handle = hba;
7725
7726out_error:
7727 return err;
7728}
7729EXPORT_SYMBOL(ufshcd_alloc_host);
7730
7731/**
7732 * ufshcd_init - Driver initialization routine
7733 * @hba: per-adapter instance
7734 * @mmio_base: base register address
7735 * @irq: Interrupt line of device
7736 * Returns 0 on success, non-zero value on failure
7737 */
7738int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
7739{
7740 int err;
7741 struct Scsi_Host *host = hba->host;
7742 struct device *dev = hba->dev;
7743
7744 if (!mmio_base) {
7745 dev_err(hba->dev,
7746 "Invalid memory reference for mmio_base is NULL\n");
7747 err = -ENODEV;
7748 goto out_error;
7749 }
7750
3b1d0580
VH		 7751 hba->mmio_base = mmio_base;
7752 hba->irq = irq;
7a3e97b0 7753
aa497613 7754 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 7755 if (err)
7756 goto out_error;
7757
7a3e97b0
SY		 7758 /* Read capabilities registers */
7759 ufshcd_hba_capabilities(hba);
7760
7761 /* Get UFS version supported by the controller */
7762 hba->ufs_version = ufshcd_get_ufs_version(hba);
7763
c01848c6
YG		 7764 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
7765 (hba->ufs_version != UFSHCI_VERSION_11) &&
7766 (hba->ufs_version != UFSHCI_VERSION_20) &&
7767 (hba->ufs_version != UFSHCI_VERSION_21))
7768 dev_err(hba->dev, "invalid UFS version 0x%x\n",
7769 hba->ufs_version);
7770
2fbd009b
SJ		 7771 /* Get Interrupt bit mask per version */
7772 hba->intr_mask = ufshcd_get_intr_mask(hba);
7773
ca3d7bf9
AM		 7774 err = ufshcd_set_dma_mask(hba);
7775 if (err) {
7776 dev_err(hba->dev, "set dma mask failed\n");
7777 goto out_disable;
7778 }
7779
7a3e97b0
SY		 7780 /* Allocate memory for host memory space */
7781 err = ufshcd_memory_alloc(hba);
7782 if (err) {
3b1d0580
VH		 7783 dev_err(hba->dev, "Memory allocation failed\n");
7784 goto out_disable;
7a3e97b0
SY		 7785 }
7786
7787 /* Configure LRB */
7788 ufshcd_host_memory_configure(hba);
7789
7790 host->can_queue = hba->nutrs;
7791 host->cmd_per_lun = hba->nutrs;
7792 host->max_id = UFSHCD_MAX_ID;
0ce147d4 7793 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 7794 host->max_channel = UFSHCD_MAX_CHANNEL;
7795 host->unique_id = host->host_no;
7796 host->max_cmd_len = MAX_CDB_SIZE;
7797
7eb584db
DR		 7798 hba->max_pwr_info.is_valid = false;
7799
7a3e97b0 7800 /* Initailize wait queue for task management */
e2933132
SRT		 7801 init_waitqueue_head(&hba->tm_wq);
7802 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 7803
7804 /* Initialize work queues */
e8e7f271 7805 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 7806 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 7807
6ccf44fe
SJ		 7808 /* Initialize UIC command mutex */
7809 mutex_init(&hba->uic_cmd_mutex);
7810
5a0b0cb9
SRT		 7811 /* Initialize mutex for device management commands */
7812 mutex_init(&hba->dev_cmd.lock);
7813
a3cd5ec5
SJ		 7814 init_rwsem(&hba->clk_scaling_lock);
7815
5a0b0cb9
SRT		 7816 /* Initialize device management tag acquire wait queue */
7817 init_waitqueue_head(&hba->dev_cmd.tag_wq);
7818
1ab27c9c 7819 ufshcd_init_clk_gating(hba);
199ef13c
YG		 7820
7821 /*
7822 * In order to avoid any spurious interrupt immediately after
7823 * registering UFS controller interrupt handler, clear any pending UFS
7824 * interrupt status and disable all the UFS interrupts.
7825 */
7826 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
7827 REG_INTERRUPT_STATUS);
7828 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
7829 /*
7830 * Make sure that UFS interrupts are disabled and any pending interrupt
7831 * status is cleared before registering UFS interrupt handler.
7832 */
7833 mb();
7834
7a3e97b0 7835 /* IRQ registration */
2953f850 7836 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 7837 if (err) {
3b1d0580 7838 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 7839 goto exit_gating;
57d104c1
SJ		 7840 } else {
7841 hba->is_irq_enabled = true;
7a3e97b0
SY		 7842 }
7843
3b1d0580 7844 err = scsi_add_host(host, hba->dev);
7a3e97b0 7845 if (err) {
3b1d0580 7846 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 7847 goto exit_gating;
7a3e97b0
SY		 7848 }
7849
6ccf44fe
SJ		 7850 /* Host controller enable */
7851 err = ufshcd_hba_enable(hba);
7a3e97b0 7852 if (err) {
6ccf44fe 7853 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 7854 ufshcd_print_host_regs(hba);
6ba65588 7855 ufshcd_print_host_state(hba);
3b1d0580 7856 goto out_remove_scsi_host;
7a3e97b0 7857 }
6ccf44fe 7858
fcb0c4b0 7859 if (ufshcd_is_clkscaling_supported(hba)) {
401f1e44
SJ		 7860 char wq_name[sizeof("ufs_clkscaling_00")];
7861
4861ee15 7862 hba->devfreq = devm_devfreq_add_device(dev, &ufs_devfreq_profile,
856b3483
ST		 7863 "simple_ondemand", NULL);
7864 if (IS_ERR(hba->devfreq)) {
7865 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
7866 PTR_ERR(hba->devfreq));
73811c94 7867 err = PTR_ERR(hba->devfreq);
856b3483
ST		 7868 goto out_remove_scsi_host;
7869 }
401f1e44
SJ		 7870 hba->clk_scaling.is_suspended = false;
7871
7872 INIT_WORK(&hba->clk_scaling.suspend_work,
7873 ufshcd_clk_scaling_suspend_work);
7874 INIT_WORK(&hba->clk_scaling.resume_work,
7875 ufshcd_clk_scaling_resume_work);
7876
7877 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clkscaling_%d",
7878 host->host_no);
7879 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
7880
856b3483 7881 /* Suspend devfreq until the UFS device is detected */
a508253d 7882 ufshcd_suspend_clkscaling(hba);
fcb0c4b0 7883 ufshcd_clkscaling_init_sysfs(hba);
856b3483
ST		 7884 }
7885
0c8f7586
SJ		 7886 /*
7887 * Set the default power management level for runtime and system PM.
7888 * Default power saving mode is to keep UFS link in Hibern8 state
7889 * and UFS device in sleep state.
7890 */
7891 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7892 UFS_SLEEP_PWR_MODE,
7893 UIC_LINK_HIBERN8_STATE);
7894 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7895 UFS_SLEEP_PWR_MODE,
7896 UIC_LINK_HIBERN8_STATE);
7897
62694735
SRT		 7898 /* Hold auto suspend until async scan completes */
7899 pm_runtime_get_sync(dev);
7900
57d104c1 7901 /*
7caf489b
SJ		 7902 * We are assuming that device wasn't put in sleep/power-down
7903 * state exclusively during the boot stage before kernel.
7904 * This assumption helps avoid doing link startup twice during
7905 * ufshcd_probe_hba().
57d104c1 7906 */
7caf489b 7907 ufshcd_set_ufs_dev_active(hba);
57d104c1 7908
6ccf44fe 7909 async_schedule(ufshcd_async_scan, hba);
09690d5a 7910 ufshcd_add_sysfs_nodes(hba);
6ccf44fe 7911
7a3e97b0
SY		 7912 return 0;
7913
3b1d0580
VH		 7914out_remove_scsi_host:
7915 scsi_remove_host(hba->host);
1ab27c9c
ST		 7916exit_gating:
7917 ufshcd_exit_clk_gating(hba);
3b1d0580 7918out_disable:
57d104c1 7919 hba->is_irq_enabled = false;
aa497613 7920 ufshcd_hba_exit(hba);
3b1d0580
VH		 7921out_error:
7922 return err;
7923}
7924EXPORT_SYMBOL_GPL(ufshcd_init);
7925
3b1d0580
VH		 7926MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
7927MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 7928MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 7929MODULE_LICENSE("GPL");
7930MODULE_VERSION(UFSHCD_DRIVER_VERSION);
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