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scsi: ufs: fix empty check of error history
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
ad448378 44#include <linux/bitfield.h>
e0eca63e 45#include "ufshcd.h"
c58ab7aa 46#include "ufs_quirks.h"
53b3d9c3 47#include "unipro.h"
cbb6813e 48#include "ufs-sysfs.h"
df032bf2 49#include "ufs_bsg.h"
7a3e97b0 50
7ff5ab47
SJ		 51#define CREATE_TRACE_POINTS
52#include <trace/events/ufs.h>
53
2fbd009b
SJ		 54#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
55 UTP_TASK_REQ_COMPL |\
56 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 57/* UIC command timeout, unit: ms */
58#define UIC_CMD_TIMEOUT 500
2fbd009b 59
5a0b0cb9
SRT		 60/* NOP OUT retries waiting for NOP IN response */
61#define NOP_OUT_RETRIES 10
62/* Timeout after 30 msecs if NOP OUT hangs without response */
63#define NOP_OUT_TIMEOUT 30 /* msecs */
64
68078d5c 65/* Query request retries */
10fe5888 66#define QUERY_REQ_RETRIES 3
68078d5c 67/* Query request timeout */
10fe5888 68#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 69
e2933132
SRT		 70/* Task management command timeout */
71#define TM_CMD_TIMEOUT 100 /* msecs */
72
64238fbd
YG		 73/* maximum number of retries for a general UIC command */
74#define UFS_UIC_COMMAND_RETRIES 3
75
1d337ec2
SRT		 76/* maximum number of link-startup retries */
77#define DME_LINKSTARTUP_RETRIES 3
78
87d0b4a6
YG		 79/* Maximum retries for Hibern8 enter */
80#define UIC_HIBERN8_ENTER_RETRIES 3
81
1d337ec2
SRT		 82/* maximum number of reset retries before giving up */
83#define MAX_HOST_RESET_RETRIES 5
84
68078d5c
DR		 85/* Expose the flag value from utp_upiu_query.value */
86#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
87
7d568652
SJ		 88/* Interrupt aggregation default timeout, unit: 40us */
89#define INT_AGGR_DEF_TO 0x02
90
49615ba1
SC		 91/* default delay of autosuspend: 2000 ms */
92#define RPM_AUTOSUSPEND_DELAY_MS 2000
93
aa497613
SRT		 94#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
95 ({ \
96 int _ret; \
97 if (_on) \
98 _ret = ufshcd_enable_vreg(_dev, _vreg); \
99 else \
100 _ret = ufshcd_disable_vreg(_dev, _vreg); \
101 _ret; \
102 })
103
ba80917d
TW		 104#define ufshcd_hex_dump(prefix_str, buf, len) do { \
105 size_t __len = (len); \
106 print_hex_dump(KERN_ERR, prefix_str, \
107 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
108 16, 4, buf, __len, false); \
109} while (0)
110
111int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
112 const char *prefix)
113{
d6724756
MG		 114 u32 *regs;
115 size_t pos;
116
117 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
118 return -EINVAL;
ba80917d 119
cddaebaf 120 regs = kzalloc(len, GFP_ATOMIC);
ba80917d
TW		 121 if (!regs)
122 return -ENOMEM;
123
d6724756
MG		 124 for (pos = 0; pos < len; pos += 4)
125 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
126
ba80917d
TW		 127 ufshcd_hex_dump(prefix, regs, len);
128 kfree(regs);
129
130 return 0;
131}
132EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 133
7a3e97b0
SY		 134enum {
135 UFSHCD_MAX_CHANNEL = 0,
136 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 137 UFSHCD_CMD_PER_LUN = 32,
138 UFSHCD_CAN_QUEUE = 32,
139};
140
141/* UFSHCD states */
142enum {
7a3e97b0
SY		 143 UFSHCD_STATE_RESET,
144 UFSHCD_STATE_ERROR,
3441da7d 145 UFSHCD_STATE_OPERATIONAL,
141f8165 146 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 147};
148
149/* UFSHCD error handling flags */
150enum {
151 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 152};
153
e8e7f271
SRT		 154/* UFSHCD UIC layer error flags */
155enum {
156 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 157 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
158 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
159 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
160 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
161 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 162};
163
3441da7d 164#define ufshcd_set_eh_in_progress(h) \
9c490d2d 165 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 166#define ufshcd_eh_in_progress(h) \
9c490d2d 167 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 168#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 169 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 170
57d104c1
SJ		 171#define ufshcd_set_ufs_dev_active(h) \
172 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
173#define ufshcd_set_ufs_dev_sleep(h) \
174 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
175#define ufshcd_set_ufs_dev_poweroff(h) \
176 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
177#define ufshcd_is_ufs_dev_active(h) \
178 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
179#define ufshcd_is_ufs_dev_sleep(h) \
180 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
181#define ufshcd_is_ufs_dev_poweroff(h) \
182 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
183
cbb6813e 184struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
57d104c1
SJ		 185 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
186 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
187 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
188 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
189 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
190 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
191};
192
193static inline enum ufs_dev_pwr_mode
194ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
195{
196 return ufs_pm_lvl_states[lvl].dev_state;
197}
198
199static inline enum uic_link_state
200ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
201{
202 return ufs_pm_lvl_states[lvl].link_state;
203}
204
0c8f7586
SJ		 205static inline enum ufs_pm_level
206ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
207 enum uic_link_state link_state)
208{
209 enum ufs_pm_level lvl;
210
211 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
212 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
213 (ufs_pm_lvl_states[lvl].link_state == link_state))
214 return lvl;
215 }
216
217 /* if no match found, return the level 0 */
218 return UFS_PM_LVL_0;
219}
220
56d4a186
SJ		 221static struct ufs_dev_fix ufs_fixups[] = {
222 /* UFS cards deviations table */
223 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
224 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
56d4a186
SJ		 225 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
226 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
56d4a186
SJ		 227 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
228 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
229 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
230 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
231 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
232 UFS_DEVICE_QUIRK_PA_TACTIVATE),
233 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
234 UFS_DEVICE_QUIRK_PA_TACTIVATE),
56d4a186
SJ		 235 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
236 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
8e4829c6
WL		 237 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
238 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
56d4a186
SJ		 239
240 END_FIX
241};
242
9333d775 243static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
3441da7d 244static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 245static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 246static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 247static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 248static void ufshcd_hba_exit(struct ufs_hba *hba);
249static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 250static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
251 bool skip_ref_clk);
252static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
253static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
254static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 255static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 256static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 257static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
258static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 259static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 260static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 261static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 262static int ufshcd_change_power_mode(struct ufs_hba *hba,
263 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 264static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
265{
266 return tag >= 0 && tag < hba->nutrs;
267}
57d104c1 268
5231d38c 269static inline void ufshcd_enable_irq(struct ufs_hba *hba)
57d104c1 270{
57d104c1 271 if (!hba->is_irq_enabled) {
5231d38c 272 enable_irq(hba->irq);
57d104c1
SJ		 273 hba->is_irq_enabled = true;
274 }
57d104c1
SJ		 275}
276
277static inline void ufshcd_disable_irq(struct ufs_hba *hba)
278{
279 if (hba->is_irq_enabled) {
5231d38c 280 disable_irq(hba->irq);
57d104c1
SJ		 281 hba->is_irq_enabled = false;
282 }
283}
3441da7d 284
38135535
SJ		 285static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
286{
287 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
288 scsi_unblock_requests(hba->host);
289}
290
291static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
292{
293 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
294 scsi_block_requests(hba->host);
295}
296
6667e6d9
OS		 297static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
298 const char *str)
299{
300 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
301
302 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
303}
304
305static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
306 const char *str)
307{
308 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
309
310 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
311}
312
313static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
314 const char *str)
315{
6667e6d9 316 int off = (int)tag - hba->nutrs;
391e388f 317 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
6667e6d9 318
391e388f
CH		 319 trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
320 &descp->input_param1);
6667e6d9
OS		 321}
322
1a07f2d9
LS		 323static void ufshcd_add_command_trace(struct ufs_hba *hba,
324 unsigned int tag, const char *str)
325{
326 sector_t lba = -1;
327 u8 opcode = 0;
328 u32 intr, doorbell;
e7c3b379 329 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
e4d2add7 330 struct scsi_cmnd *cmd = lrbp->cmd;
1a07f2d9
LS		 331 int transfer_len = -1;
332
e7c3b379
OS		 333 if (!trace_ufshcd_command_enabled()) {
334 /* trace UPIU W/O tracing command */
e4d2add7 335 if (cmd)
e7c3b379 336 ufshcd_add_cmd_upiu_trace(hba, tag, str);
1a07f2d9 337 return;
e7c3b379 338 }
1a07f2d9 339
e4d2add7 340 if (cmd) { /* data phase exists */
e7c3b379
OS		 341 /* trace UPIU also */
342 ufshcd_add_cmd_upiu_trace(hba, tag, str);
e4d2add7 343 opcode = cmd->cmnd[0];
1a07f2d9
LS		 344 if ((opcode == READ_10) || (opcode == WRITE_10)) {
345 /*
346 * Currently we only fully trace read(10) and write(10)
347 * commands
348 */
e4d2add7
BVA		 349 if (cmd->request && cmd->request->bio)
350 lba = cmd->request->bio->bi_iter.bi_sector;
1a07f2d9
LS		 351 transfer_len = be32_to_cpu(
352 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
353 }
354 }
355
356 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
357 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
358 trace_ufshcd_command(dev_name(hba->dev), str, tag,
359 doorbell, transfer_len, intr, lba, opcode);
360}
361
ff8e20c6
DR		 362static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
363{
364 struct ufs_clk_info *clki;
365 struct list_head *head = &hba->clk_list_head;
366
566ec9ad 367 if (list_empty(head))
ff8e20c6
DR		 368 return;
369
370 list_for_each_entry(clki, head, list) {
371 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
372 clki->max_freq)
373 dev_err(hba->dev, "clk: %s, rate: %u\n",
374 clki->name, clki->curr_freq);
375 }
376}
377
48d5b973
SC		 378static void ufshcd_print_err_hist(struct ufs_hba *hba,
379 struct ufs_err_reg_hist *err_hist,
380 char *err_name)
ff8e20c6
DR		 381{
382 int i;
27752647 383 bool found = false;
ff8e20c6 384
48d5b973
SC		 385 for (i = 0; i < UFS_ERR_REG_HIST_LENGTH; i++) {
386 int p = (i + err_hist->pos) % UFS_ERR_REG_HIST_LENGTH;
ff8e20c6 387
645728a6 388 if (err_hist->tstamp[p] == 0)
ff8e20c6 389 continue;
c5397f13 390 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
ff8e20c6 391 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
27752647 392 found = true;
ff8e20c6 393 }
27752647
SC		 394
395 if (!found)
48d5b973 396 dev_err(hba->dev, "No record of %s errors\n", err_name);
ff8e20c6
DR		 397}
398
66cc820f
DR		 399static void ufshcd_print_host_regs(struct ufs_hba *hba)
400{
ba80917d 401 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
66cc820f
DR		 402 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
403 hba->ufs_version, hba->capabilities);
404 dev_err(hba->dev,
405 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
406 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 407 dev_err(hba->dev,
408 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
409 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
410 hba->ufs_stats.hibern8_exit_cnt);
411
48d5b973
SC		 412 ufshcd_print_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
413 ufshcd_print_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
414 ufshcd_print_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
415 ufshcd_print_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
416 ufshcd_print_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
d3c615bf
SC		 417 ufshcd_print_err_hist(hba, &hba->ufs_stats.auto_hibern8_err,
418 "auto_hibern8_err");
8808b4e9
SC		 419 ufshcd_print_err_hist(hba, &hba->ufs_stats.fatal_err, "fatal_err");
420 ufshcd_print_err_hist(hba, &hba->ufs_stats.link_startup_err,
421 "link_startup_fail");
422 ufshcd_print_err_hist(hba, &hba->ufs_stats.resume_err, "resume_fail");
423 ufshcd_print_err_hist(hba, &hba->ufs_stats.suspend_err,
424 "suspend_fail");
425 ufshcd_print_err_hist(hba, &hba->ufs_stats.dev_reset, "dev_reset");
426 ufshcd_print_err_hist(hba, &hba->ufs_stats.host_reset, "host_reset");
427 ufshcd_print_err_hist(hba, &hba->ufs_stats.task_abort, "task_abort");
ff8e20c6
DR		 428
429 ufshcd_print_clk_freqs(hba);
430
7c486d91 431 ufshcd_vops_dbg_register_dump(hba);
66cc820f
DR		 432}
433
434static
435void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
436{
437 struct ufshcd_lrb *lrbp;
7fabb77b 438 int prdt_length;
66cc820f
DR		 439 int tag;
440
441 for_each_set_bit(tag, &bitmap, hba->nutrs) {
442 lrbp = &hba->lrb[tag];
443
ff8e20c6
DR		 444 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
445 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 446 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
447 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 448 dev_err(hba->dev,
449 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
450 tag, (u64)lrbp->utrd_dma_addr);
451
66cc820f
DR		 452 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
453 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 454 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
455 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 456 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
457 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 458 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
459 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 460 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
461 sizeof(struct utp_upiu_rsp));
66cc820f 462
7fabb77b
GB		 463 prdt_length = le16_to_cpu(
464 lrbp->utr_descriptor_ptr->prd_table_length);
465 dev_err(hba->dev,
466 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
467 tag, prdt_length,
468 (u64)lrbp->ucd_prdt_dma_addr);
469
470 if (pr_prdt)
66cc820f 471 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 472 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 473 }
474}
475
476static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
477{
66cc820f
DR		 478 int tag;
479
480 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 481 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
482
66cc820f 483 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 484 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 485 }
486}
487
6ba65588
GB		 488static void ufshcd_print_host_state(struct ufs_hba *hba)
489{
490 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
7252a360
BVA		 491 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
492 hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 493 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
494 hba->saved_err, hba->saved_uic_err);
495 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
496 hba->curr_dev_pwr_mode, hba->uic_link_state);
497 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
498 hba->pm_op_in_progress, hba->is_sys_suspended);
499 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
500 hba->auto_bkops_enabled, hba->host->host_self_blocked);
501 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
502 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
503 hba->eh_flags, hba->req_abort_count);
504 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
505 hba->capabilities, hba->caps);
506 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
507 hba->dev_quirks);
508}
509
ff8e20c6
DR		 510/**
511 * ufshcd_print_pwr_info - print power params as saved in hba
512 * power info
513 * @hba: per-adapter instance
514 */
515static void ufshcd_print_pwr_info(struct ufs_hba *hba)
516{
517 static const char * const names[] = {
518 "INVALID MODE",
519 "FAST MODE",
520 "SLOW_MODE",
521 "INVALID MODE",
522 "FASTAUTO_MODE",
523 "SLOWAUTO_MODE",
524 "INVALID MODE",
525 };
526
527 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
528 __func__,
529 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
530 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
531 names[hba->pwr_info.pwr_rx],
532 names[hba->pwr_info.pwr_tx],
533 hba->pwr_info.hs_rate);
534}
535
5a0b0cb9
SRT		 536/*
537 * ufshcd_wait_for_register - wait for register value to change
538 * @hba - per-adapter interface
539 * @reg - mmio register offset
540 * @mask - mask to apply to read register value
541 * @val - wait condition
542 * @interval_us - polling interval in microsecs
543 * @timeout_ms - timeout in millisecs
596585a2 544 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 545 *
546 * Returns -ETIMEDOUT on error, zero on success
547 */
596585a2
YG		 548int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
549 u32 val, unsigned long interval_us,
550 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 551{
552 int err = 0;
553 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
554
555 /* ignore bits that we don't intend to wait on */
556 val = val & mask;
557
558 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 559 if (can_sleep)
560 usleep_range(interval_us, interval_us + 50);
561 else
562 udelay(interval_us);
5a0b0cb9
SRT		 563 if (time_after(jiffies, timeout)) {
564 if ((ufshcd_readl(hba, reg) & mask) != val)
565 err = -ETIMEDOUT;
566 break;
567 }
568 }
569
570 return err;
571}
572
2fbd009b
SJ		 573/**
574 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 575 * @hba: Pointer to adapter instance
2fbd009b
SJ		 576 *
577 * Returns interrupt bit mask per version
578 */
579static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
580{
c01848c6
YG		 581 u32 intr_mask = 0;
582
583 switch (hba->ufs_version) {
584 case UFSHCI_VERSION_10:
585 intr_mask = INTERRUPT_MASK_ALL_VER_10;
586 break;
c01848c6
YG		 587 case UFSHCI_VERSION_11:
588 case UFSHCI_VERSION_20:
589 intr_mask = INTERRUPT_MASK_ALL_VER_11;
590 break;
c01848c6
YG		 591 case UFSHCI_VERSION_21:
592 default:
593 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 594 break;
c01848c6
YG		 595 }
596
597 return intr_mask;
2fbd009b
SJ		 598}
599
7a3e97b0
SY		 600/**
601 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 602 * @hba: Pointer to adapter instance
7a3e97b0
SY		 603 *
604 * Returns UFSHCI version supported by the controller
605 */
606static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
607{
0263bcd0
YG		 608 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
609 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 610
b873a275 611 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 612}
613
614/**
615 * ufshcd_is_device_present - Check if any device connected to
616 * the host controller
5c0c28a8 617 * @hba: pointer to adapter instance
7a3e97b0 618 *
c9e6010b 619 * Returns true if device present, false if no device detected
7a3e97b0 620 */
c9e6010b 621static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 622{
5c0c28a8 623 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 624 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 625}
626
627/**
628 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 629 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 630 *
631 * This function is used to get the OCS field from UTRD
632 * Returns the OCS field in the UTRD
633 */
634static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
635{
e8c8e82a 636 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 637}
638
7a3e97b0
SY		 639/**
640 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
641 * @hba: per adapter instance
642 * @pos: position of the bit to be cleared
643 */
644static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
645{
1399c5b0
AA		 646 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
647 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
648 else
649 ufshcd_writel(hba, ~(1 << pos),
650 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
651}
652
653/**
654 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
655 * @hba: per adapter instance
656 * @pos: position of the bit to be cleared
657 */
658static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
659{
660 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
661 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
662 else
663 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 664}
665
a48353f6
YG		 666/**
667 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
668 * @hba: per adapter instance
669 * @tag: position of the bit to be cleared
670 */
671static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
672{
673 __clear_bit(tag, &hba->outstanding_reqs);
674}
675
7a3e97b0
SY		 676/**
677 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
678 * @reg: Register value of host controller status
679 *
680 * Returns integer, 0 on Success and positive value if failed
681 */
682static inline int ufshcd_get_lists_status(u32 reg)
683{
6cf16115 684 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 685}
686
687/**
688 * ufshcd_get_uic_cmd_result - Get the UIC command result
689 * @hba: Pointer to adapter instance
690 *
691 * This function gets the result of UIC command completion
692 * Returns 0 on success, non zero value on error
693 */
694static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
695{
b873a275 696 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 697 MASK_UIC_COMMAND_RESULT;
698}
699
12b4fdb4
SJ		 700/**
701 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
702 * @hba: Pointer to adapter instance
703 *
704 * This function gets UIC command argument3
705 * Returns 0 on success, non zero value on error
706 */
707static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
708{
709 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
710}
711
7a3e97b0 712/**
5a0b0cb9 713 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 714 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 715 */
716static inline int
5a0b0cb9 717ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 718{
5a0b0cb9 719 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 720}
721
722/**
723 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
724 * @ucd_rsp_ptr: pointer to response UPIU
725 *
726 * This function gets the response status and scsi_status from response UPIU
727 * Returns the response result code.
728 */
729static inline int
730ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
731{
732 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
733}
734
1c2623c5
SJ		 735/*
736 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
737 * from response UPIU
738 * @ucd_rsp_ptr: pointer to response UPIU
739 *
740 * Return the data segment length.
741 */
742static inline unsigned int
743ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
744{
745 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
746 MASK_RSP_UPIU_DATA_SEG_LEN;
747}
748
66ec6d59
SRT		 749/**
750 * ufshcd_is_exception_event - Check if the device raised an exception event
751 * @ucd_rsp_ptr: pointer to response UPIU
752 *
753 * The function checks if the device raised an exception event indicated in
754 * the Device Information field of response UPIU.
755 *
756 * Returns true if exception is raised, false otherwise.
757 */
758static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
759{
760 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
761 MASK_RSP_EXCEPTION_EVENT ? true : false;
762}
763
7a3e97b0 764/**
7d568652 765 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 766 * @hba: per adapter instance
7a3e97b0
SY		 767 */
768static inline void
7d568652 769ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 770{
7d568652
SJ		 771 ufshcd_writel(hba, INT_AGGR_ENABLE |
772 INT_AGGR_COUNTER_AND_TIMER_RESET,
773 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
774}
775
776/**
777 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
778 * @hba: per adapter instance
779 * @cnt: Interrupt aggregation counter threshold
780 * @tmout: Interrupt aggregation timeout value
781 */
782static inline void
783ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
784{
785 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
786 INT_AGGR_COUNTER_THLD_VAL(cnt) |
787 INT_AGGR_TIMEOUT_VAL(tmout),
788 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 789}
790
b852190e
YG		 791/**
792 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
793 * @hba: per adapter instance
794 */
795static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
796{
797 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
798}
799
7a3e97b0
SY		 800/**
801 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
802 * When run-stop registers are set to 1, it indicates the
803 * host controller that it can process the requests
804 * @hba: per adapter instance
805 */
806static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
807{
b873a275
SJ		 808 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
809 REG_UTP_TASK_REQ_LIST_RUN_STOP);
810 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
811 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 812}
813
7a3e97b0
SY		 814/**
815 * ufshcd_hba_start - Start controller initialization sequence
816 * @hba: per adapter instance
817 */
818static inline void ufshcd_hba_start(struct ufs_hba *hba)
819{
b873a275 820 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 821}
822
823/**
824 * ufshcd_is_hba_active - Get controller state
825 * @hba: per adapter instance
826 *
c9e6010b 827 * Returns false if controller is active, true otherwise
7a3e97b0 828 */
c9e6010b 829static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 830{
4a8eec2b
TK		 831 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
832 ? false : true;
7a3e97b0
SY		 833}
834
37113106
YG		 835u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
836{
837 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
838 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
839 (hba->ufs_version == UFSHCI_VERSION_11))
840 return UFS_UNIPRO_VER_1_41;
841 else
842 return UFS_UNIPRO_VER_1_6;
843}
844EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
845
846static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
847{
848 /*
849 * If both host and device support UniPro ver1.6 or later, PA layer
850 * parameters tuning happens during link startup itself.
851 *
852 * We can manually tune PA layer parameters if either host or device
853 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
854 * logic simple, we will only do manual tuning if local unipro version
855 * doesn't support ver1.6 or later.
856 */
857 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
858 return true;
859 else
860 return false;
861}
862
a3cd5ec5
SJ		 863static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
864{
865 int ret = 0;
866 struct ufs_clk_info *clki;
867 struct list_head *head = &hba->clk_list_head;
868 ktime_t start = ktime_get();
869 bool clk_state_changed = false;
870
566ec9ad 871 if (list_empty(head))
a3cd5ec5
SJ		 872 goto out;
873
874 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
875 if (ret)
876 return ret;
877
878 list_for_each_entry(clki, head, list) {
879 if (!IS_ERR_OR_NULL(clki->clk)) {
880 if (scale_up && clki->max_freq) {
881 if (clki->curr_freq == clki->max_freq)
882 continue;
883
884 clk_state_changed = true;
885 ret = clk_set_rate(clki->clk, clki->max_freq);
886 if (ret) {
887 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
888 __func__, clki->name,
889 clki->max_freq, ret);
890 break;
891 }
892 trace_ufshcd_clk_scaling(dev_name(hba->dev),
893 "scaled up", clki->name,
894 clki->curr_freq,
895 clki->max_freq);
896
897 clki->curr_freq = clki->max_freq;
898
899 } else if (!scale_up && clki->min_freq) {
900 if (clki->curr_freq == clki->min_freq)
901 continue;
902
903 clk_state_changed = true;
904 ret = clk_set_rate(clki->clk, clki->min_freq);
905 if (ret) {
906 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
907 __func__, clki->name,
908 clki->min_freq, ret);
909 break;
910 }
911 trace_ufshcd_clk_scaling(dev_name(hba->dev),
912 "scaled down", clki->name,
913 clki->curr_freq,
914 clki->min_freq);
915 clki->curr_freq = clki->min_freq;
916 }
917 }
918 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
919 clki->name, clk_get_rate(clki->clk));
920 }
921
922 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
923
924out:
925 if (clk_state_changed)
926 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
927 (scale_up ? "up" : "down"),
928 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
929 return ret;
930}
931
932/**
933 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
934 * @hba: per adapter instance
935 * @scale_up: True if scaling up and false if scaling down
936 *
937 * Returns true if scaling is required, false otherwise.
938 */
939static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
940 bool scale_up)
941{
942 struct ufs_clk_info *clki;
943 struct list_head *head = &hba->clk_list_head;
944
566ec9ad 945 if (list_empty(head))
a3cd5ec5
SJ		 946 return false;
947
948 list_for_each_entry(clki, head, list) {
949 if (!IS_ERR_OR_NULL(clki->clk)) {
950 if (scale_up && clki->max_freq) {
951 if (clki->curr_freq == clki->max_freq)
952 continue;
953 return true;
954 } else if (!scale_up && clki->min_freq) {
955 if (clki->curr_freq == clki->min_freq)
956 continue;
957 return true;
958 }
959 }
960 }
961
962 return false;
963}
964
965static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
966 u64 wait_timeout_us)
967{
968 unsigned long flags;
969 int ret = 0;
970 u32 tm_doorbell;
971 u32 tr_doorbell;
972 bool timeout = false, do_last_check = false;
973 ktime_t start;
974
975 ufshcd_hold(hba, false);
976 spin_lock_irqsave(hba->host->host_lock, flags);
977 /*
978 * Wait for all the outstanding tasks/transfer requests.
979 * Verify by checking the doorbell registers are clear.
980 */
981 start = ktime_get();
982 do {
983 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
984 ret = -EBUSY;
985 goto out;
986 }
987
988 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
989 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
990 if (!tm_doorbell && !tr_doorbell) {
991 timeout = false;
992 break;
993 } else if (do_last_check) {
994 break;
995 }
996
997 spin_unlock_irqrestore(hba->host->host_lock, flags);
998 schedule();
999 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1000 wait_timeout_us) {
1001 timeout = true;
1002 /*
1003 * We might have scheduled out for long time so make
1004 * sure to check if doorbells are cleared by this time
1005 * or not.
1006 */
1007 do_last_check = true;
1008 }
1009 spin_lock_irqsave(hba->host->host_lock, flags);
1010 } while (tm_doorbell || tr_doorbell);
1011
1012 if (timeout) {
1013 dev_err(hba->dev,
1014 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1015 __func__, tm_doorbell, tr_doorbell);
1016 ret = -EBUSY;
1017 }
1018out:
1019 spin_unlock_irqrestore(hba->host->host_lock, flags);
1020 ufshcd_release(hba);
1021 return ret;
1022}
1023
1024/**
1025 * ufshcd_scale_gear - scale up/down UFS gear
1026 * @hba: per adapter instance
1027 * @scale_up: True for scaling up gear and false for scaling down
1028 *
1029 * Returns 0 for success,
1030 * Returns -EBUSY if scaling can't happen at this time
1031 * Returns non-zero for any other errors
1032 */
1033static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1034{
1035 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1036 int ret = 0;
1037 struct ufs_pa_layer_attr new_pwr_info;
1038
1039 if (scale_up) {
1040 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1041 sizeof(struct ufs_pa_layer_attr));
1042 } else {
1043 memcpy(&new_pwr_info, &hba->pwr_info,
1044 sizeof(struct ufs_pa_layer_attr));
1045
1046 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1047 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1048 /* save the current power mode */
1049 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1050 &hba->pwr_info,
1051 sizeof(struct ufs_pa_layer_attr));
1052
1053 /* scale down gear */
1054 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1055 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1056 }
1057 }
1058
1059 /* check if the power mode needs to be changed or not? */
1060 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1061
1062 if (ret)
1063 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1064 __func__, ret,
1065 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1066 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1067
1068 return ret;
1069}
1070
1071static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1072{
1073 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1074 int ret = 0;
1075 /*
1076 * make sure that there are no outstanding requests when
1077 * clock scaling is in progress
1078 */
38135535 1079 ufshcd_scsi_block_requests(hba);
a3cd5ec5
SJ		 1080 down_write(&hba->clk_scaling_lock);
1081 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1082 ret = -EBUSY;
1083 up_write(&hba->clk_scaling_lock);
38135535 1084 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5
SJ		 1085 }
1086
1087 return ret;
1088}
1089
1090static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1091{
1092 up_write(&hba->clk_scaling_lock);
38135535 1093 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5
SJ		 1094}
1095
1096/**
1097 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1098 * @hba: per adapter instance
1099 * @scale_up: True for scaling up and false for scalin down
1100 *
1101 * Returns 0 for success,
1102 * Returns -EBUSY if scaling can't happen at this time
1103 * Returns non-zero for any other errors
1104 */
1105static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1106{
1107 int ret = 0;
1108
401f1e44
SJ		 1109 /* let's not get into low power until clock scaling is completed */
1110 ufshcd_hold(hba, false);
1111
a3cd5ec5
SJ		 1112 ret = ufshcd_clock_scaling_prepare(hba);
1113 if (ret)
1114 return ret;
1115
1116 /* scale down the gear before scaling down clocks */
1117 if (!scale_up) {
1118 ret = ufshcd_scale_gear(hba, false);
1119 if (ret)
1120 goto out;
1121 }
1122
1123 ret = ufshcd_scale_clks(hba, scale_up);
1124 if (ret) {
1125 if (!scale_up)
1126 ufshcd_scale_gear(hba, true);
1127 goto out;
1128 }
1129
1130 /* scale up the gear after scaling up clocks */
1131 if (scale_up) {
1132 ret = ufshcd_scale_gear(hba, true);
1133 if (ret) {
1134 ufshcd_scale_clks(hba, false);
1135 goto out;
1136 }
1137 }
1138
1139 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1140
1141out:
1142 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1143 ufshcd_release(hba);
a3cd5ec5
SJ		 1144 return ret;
1145}
1146
401f1e44
SJ		 1147static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1148{
1149 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1150 clk_scaling.suspend_work);
1151 unsigned long irq_flags;
1152
1153 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1154 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1155 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1156 return;
1157 }
1158 hba->clk_scaling.is_suspended = true;
1159 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1160
1161 __ufshcd_suspend_clkscaling(hba);
1162}
1163
1164static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1165{
1166 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1167 clk_scaling.resume_work);
1168 unsigned long irq_flags;
1169
1170 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1171 if (!hba->clk_scaling.is_suspended) {
1172 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1173 return;
1174 }
1175 hba->clk_scaling.is_suspended = false;
1176 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1177
1178 devfreq_resume_device(hba->devfreq);
1179}
1180
a3cd5ec5
SJ		 1181static int ufshcd_devfreq_target(struct device *dev,
1182 unsigned long *freq, u32 flags)
1183{
1184 int ret = 0;
1185 struct ufs_hba *hba = dev_get_drvdata(dev);
1186 ktime_t start;
401f1e44 1187 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1188 struct list_head *clk_list = &hba->clk_list_head;
1189 struct ufs_clk_info *clki;
a3cd5ec5
SJ		 1190 unsigned long irq_flags;
1191
1192 if (!ufshcd_is_clkscaling_supported(hba))
1193 return -EINVAL;
1194
a3cd5ec5
SJ		 1195 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1196 if (ufshcd_eh_in_progress(hba)) {
1197 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1198 return 0;
1199 }
1200
401f1e44
SJ		 1201 if (!hba->clk_scaling.active_reqs)
1202 sched_clk_scaling_suspend_work = true;
1203
092b4558
BA		 1204 if (list_empty(clk_list)) {
1205 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1206 goto out;
1207 }
1208
1209 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1210 scale_up = (*freq == clki->max_freq) ? true : false;
401f1e44
SJ		 1211 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1212 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1213 ret = 0;
1214 goto out; /* no state change required */
a3cd5ec5
SJ		 1215 }
1216 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1217
1218 start = ktime_get();
a3cd5ec5
SJ		 1219 ret = ufshcd_devfreq_scale(hba, scale_up);
1220
a3cd5ec5
SJ		 1221 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1222 (scale_up ? "up" : "down"),
1223 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1224
401f1e44
SJ		 1225out:
1226 if (sched_clk_scaling_suspend_work)
1227 queue_work(hba->clk_scaling.workq,
1228 &hba->clk_scaling.suspend_work);
1229
a3cd5ec5
SJ		 1230 return ret;
1231}
1232
7252a360
BVA		 1233static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1234{
1235 int *busy = priv;
1236
1237 WARN_ON_ONCE(reserved);
1238 (*busy)++;
1239 return false;
1240}
1241
1242/* Whether or not any tag is in use by a request that is in progress. */
1243static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1244{
1245 struct request_queue *q = hba->cmd_queue;
1246 int busy = 0;
1247
1248 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1249 return busy;
1250}
a3cd5ec5
SJ		 1251
1252static int ufshcd_devfreq_get_dev_status(struct device *dev,
1253 struct devfreq_dev_status *stat)
1254{
1255 struct ufs_hba *hba = dev_get_drvdata(dev);
1256 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1257 unsigned long flags;
1258
1259 if (!ufshcd_is_clkscaling_supported(hba))
1260 return -EINVAL;
1261
1262 memset(stat, 0, sizeof(*stat));
1263
1264 spin_lock_irqsave(hba->host->host_lock, flags);
1265 if (!scaling->window_start_t)
1266 goto start_window;
1267
1268 if (scaling->is_busy_started)
1269 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1270 scaling->busy_start_t));
1271
1272 stat->total_time = jiffies_to_usecs((long)jiffies -
1273 (long)scaling->window_start_t);
1274 stat->busy_time = scaling->tot_busy_t;
1275start_window:
1276 scaling->window_start_t = jiffies;
1277 scaling->tot_busy_t = 0;
1278
1279 if (hba->outstanding_reqs) {
1280 scaling->busy_start_t = ktime_get();
1281 scaling->is_busy_started = true;
1282 } else {
1283 scaling->busy_start_t = 0;
1284 scaling->is_busy_started = false;
1285 }
1286 spin_unlock_irqrestore(hba->host->host_lock, flags);
1287 return 0;
1288}
1289
1290static struct devfreq_dev_profile ufs_devfreq_profile = {
1291 .polling_ms = 100,
1292 .target = ufshcd_devfreq_target,
1293 .get_dev_status = ufshcd_devfreq_get_dev_status,
1294};
1295
deac444f
BA		 1296static int ufshcd_devfreq_init(struct ufs_hba *hba)
1297{
092b4558
BA		 1298 struct list_head *clk_list = &hba->clk_list_head;
1299 struct ufs_clk_info *clki;
deac444f
BA		 1300 struct devfreq *devfreq;
1301 int ret;
1302
092b4558
BA		 1303 /* Skip devfreq if we don't have any clocks in the list */
1304 if (list_empty(clk_list))
1305 return 0;
1306
1307 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1308 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1309 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1310
1311 devfreq = devfreq_add_device(hba->dev,
deac444f
BA		 1312 &ufs_devfreq_profile,
1313 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1314 NULL);
1315 if (IS_ERR(devfreq)) {
1316 ret = PTR_ERR(devfreq);
1317 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1318
1319 dev_pm_opp_remove(hba->dev, clki->min_freq);
1320 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1321 return ret;
1322 }
1323
1324 hba->devfreq = devfreq;
1325
1326 return 0;
1327}
1328
092b4558
BA		 1329static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1330{
1331 struct list_head *clk_list = &hba->clk_list_head;
1332 struct ufs_clk_info *clki;
1333
1334 if (!hba->devfreq)
1335 return;
1336
1337 devfreq_remove_device(hba->devfreq);
1338 hba->devfreq = NULL;
1339
1340 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1341 dev_pm_opp_remove(hba->dev, clki->min_freq);
1342 dev_pm_opp_remove(hba->dev, clki->max_freq);
1343}
1344
401f1e44
SJ		 1345static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1346{
1347 unsigned long flags;
1348
1349 devfreq_suspend_device(hba->devfreq);
1350 spin_lock_irqsave(hba->host->host_lock, flags);
1351 hba->clk_scaling.window_start_t = 0;
1352 spin_unlock_irqrestore(hba->host->host_lock, flags);
1353}
a3cd5ec5 1354
a508253d
GB		 1355static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1356{
401f1e44
SJ		 1357 unsigned long flags;
1358 bool suspend = false;
1359
fcb0c4b0
ST		 1360 if (!ufshcd_is_clkscaling_supported(hba))
1361 return;
1362
401f1e44
SJ		 1363 spin_lock_irqsave(hba->host->host_lock, flags);
1364 if (!hba->clk_scaling.is_suspended) {
1365 suspend = true;
1366 hba->clk_scaling.is_suspended = true;
1367 }
1368 spin_unlock_irqrestore(hba->host->host_lock, flags);
1369
1370 if (suspend)
1371 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1372}
1373
1374static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1375{
401f1e44
SJ		 1376 unsigned long flags;
1377 bool resume = false;
1378
1379 if (!ufshcd_is_clkscaling_supported(hba))
1380 return;
1381
1382 spin_lock_irqsave(hba->host->host_lock, flags);
1383 if (hba->clk_scaling.is_suspended) {
1384 resume = true;
1385 hba->clk_scaling.is_suspended = false;
1386 }
1387 spin_unlock_irqrestore(hba->host->host_lock, flags);
1388
1389 if (resume)
1390 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1391}
1392
1393static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1394 struct device_attribute *attr, char *buf)
1395{
1396 struct ufs_hba *hba = dev_get_drvdata(dev);
1397
1398 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1399}
1400
1401static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1402 struct device_attribute *attr, const char *buf, size_t count)
1403{
1404 struct ufs_hba *hba = dev_get_drvdata(dev);
1405 u32 value;
1406 int err;
1407
1408 if (kstrtou32(buf, 0, &value))
1409 return -EINVAL;
1410
1411 value = !!value;
1412 if (value == hba->clk_scaling.is_allowed)
1413 goto out;
1414
1415 pm_runtime_get_sync(hba->dev);
1416 ufshcd_hold(hba, false);
1417
401f1e44
SJ		 1418 cancel_work_sync(&hba->clk_scaling.suspend_work);
1419 cancel_work_sync(&hba->clk_scaling.resume_work);
1420
1421 hba->clk_scaling.is_allowed = value;
1422
fcb0c4b0
ST		 1423 if (value) {
1424 ufshcd_resume_clkscaling(hba);
1425 } else {
1426 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1427 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1428 if (err)
1429 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1430 __func__, err);
1431 }
fcb0c4b0
ST		 1432
1433 ufshcd_release(hba);
1434 pm_runtime_put_sync(hba->dev);
1435out:
1436 return count;
a508253d
GB		 1437}
1438
a3cd5ec5
SJ		 1439static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1440{
1441 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1442 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1443 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1444 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1445 hba->clk_scaling.enable_attr.attr.mode = 0644;
1446 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1447 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1448}
1449
1ab27c9c
ST		 1450static void ufshcd_ungate_work(struct work_struct *work)
1451{
1452 int ret;
1453 unsigned long flags;
1454 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1455 clk_gating.ungate_work);
1456
1457 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1458
1459 spin_lock_irqsave(hba->host->host_lock, flags);
1460 if (hba->clk_gating.state == CLKS_ON) {
1461 spin_unlock_irqrestore(hba->host->host_lock, flags);
1462 goto unblock_reqs;
1463 }
1464
1465 spin_unlock_irqrestore(hba->host->host_lock, flags);
1466 ufshcd_setup_clocks(hba, true);
1467
8b0bbf00
SC		 1468 ufshcd_enable_irq(hba);
1469
1ab27c9c
ST		 1470 /* Exit from hibern8 */
1471 if (ufshcd_can_hibern8_during_gating(hba)) {
1472 /* Prevent gating in this path */
1473 hba->clk_gating.is_suspended = true;
1474 if (ufshcd_is_link_hibern8(hba)) {
1475 ret = ufshcd_uic_hibern8_exit(hba);
1476 if (ret)
1477 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1478 __func__, ret);
1479 else
1480 ufshcd_set_link_active(hba);
1481 }
1482 hba->clk_gating.is_suspended = false;
1483 }
1484unblock_reqs:
38135535 1485 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1486}
1487
1488/**
1489 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1490 * Also, exit from hibern8 mode and set the link as active.
1491 * @hba: per adapter instance
1492 * @async: This indicates whether caller should ungate clocks asynchronously.
1493 */
1494int ufshcd_hold(struct ufs_hba *hba, bool async)
1495{
1496 int rc = 0;
1497 unsigned long flags;
1498
1499 if (!ufshcd_is_clkgating_allowed(hba))
1500 goto out;
1ab27c9c
ST		 1501 spin_lock_irqsave(hba->host->host_lock, flags);
1502 hba->clk_gating.active_reqs++;
1503
53c12d0e
YG		 1504 if (ufshcd_eh_in_progress(hba)) {
1505 spin_unlock_irqrestore(hba->host->host_lock, flags);
1506 return 0;
1507 }
1508
856b3483 1509start:
1ab27c9c
ST		 1510 switch (hba->clk_gating.state) {
1511 case CLKS_ON:
f2a785ac
VG		 1512 /*
1513 * Wait for the ungate work to complete if in progress.
1514 * Though the clocks may be in ON state, the link could
1515 * still be in hibner8 state if hibern8 is allowed
1516 * during clock gating.
1517 * Make sure we exit hibern8 state also in addition to
1518 * clocks being ON.
1519 */
1520 if (ufshcd_can_hibern8_during_gating(hba) &&
1521 ufshcd_is_link_hibern8(hba)) {
1522 spin_unlock_irqrestore(hba->host->host_lock, flags);
1523 flush_work(&hba->clk_gating.ungate_work);
1524 spin_lock_irqsave(hba->host->host_lock, flags);
1525 goto start;
1526 }
1ab27c9c
ST		 1527 break;
1528 case REQ_CLKS_OFF:
1529 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1530 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1531 trace_ufshcd_clk_gating(dev_name(hba->dev),
1532 hba->clk_gating.state);
1ab27c9c
ST		 1533 break;
1534 }
1535 /*
9c490d2d 1536 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1537 * currently running. Hence, fall through to cancel gating
1538 * work and to enable clocks.
1539 */
30eb2e4c 1540 /* fallthrough */
1ab27c9c 1541 case CLKS_OFF:
38135535 1542 ufshcd_scsi_block_requests(hba);
1ab27c9c 1543 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47
SJ		 1544 trace_ufshcd_clk_gating(dev_name(hba->dev),
1545 hba->clk_gating.state);
10e5e375
VV		 1546 queue_work(hba->clk_gating.clk_gating_workq,
1547 &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1548 /*
1549 * fall through to check if we should wait for this
1550 * work to be done or not.
1551 */
30eb2e4c 1552 /* fallthrough */
1ab27c9c
ST		 1553 case REQ_CLKS_ON:
1554 if (async) {
1555 rc = -EAGAIN;
1556 hba->clk_gating.active_reqs--;
1557 break;
1558 }
1559
1560 spin_unlock_irqrestore(hba->host->host_lock, flags);
1561 flush_work(&hba->clk_gating.ungate_work);
1562 /* Make sure state is CLKS_ON before returning */
856b3483 1563 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1564 goto start;
1565 default:
1566 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1567 __func__, hba->clk_gating.state);
1568 break;
1569 }
1570 spin_unlock_irqrestore(hba->host->host_lock, flags);
1571out:
1572 return rc;
1573}
6e3fd44d 1574EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1575
1576static void ufshcd_gate_work(struct work_struct *work)
1577{
1578 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1579 clk_gating.gate_work.work);
1580 unsigned long flags;
1581
1582 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1583 /*
1584 * In case you are here to cancel this work the gating state
1585 * would be marked as REQ_CLKS_ON. In this case save time by
1586 * skipping the gating work and exit after changing the clock
1587 * state to CLKS_ON.
1588 */
1589 if (hba->clk_gating.is_suspended ||
18f01374 1590 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1ab27c9c 1591 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1592 trace_ufshcd_clk_gating(dev_name(hba->dev),
1593 hba->clk_gating.state);
1ab27c9c
ST		 1594 goto rel_lock;
1595 }
1596
1597 if (hba->clk_gating.active_reqs
1598 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1599 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1ab27c9c
ST		 1600 || hba->active_uic_cmd || hba->uic_async_done)
1601 goto rel_lock;
1602
1603 spin_unlock_irqrestore(hba->host->host_lock, flags);
1604
1605 /* put the link into hibern8 mode before turning off clocks */
1606 if (ufshcd_can_hibern8_during_gating(hba)) {
1607 if (ufshcd_uic_hibern8_enter(hba)) {
1608 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1609 trace_ufshcd_clk_gating(dev_name(hba->dev),
1610 hba->clk_gating.state);
1ab27c9c
ST		 1611 goto out;
1612 }
1613 ufshcd_set_link_hibern8(hba);
1614 }
1615
8b0bbf00
SC		 1616 ufshcd_disable_irq(hba);
1617
1ab27c9c
ST		 1618 if (!ufshcd_is_link_active(hba))
1619 ufshcd_setup_clocks(hba, false);
1620 else
1621 /* If link is active, device ref_clk can't be switched off */
1622 __ufshcd_setup_clocks(hba, false, true);
1623
1624 /*
1625 * In case you are here to cancel this work the gating state
1626 * would be marked as REQ_CLKS_ON. In this case keep the state
1627 * as REQ_CLKS_ON which would anyway imply that clocks are off
1628 * and a request to turn them on is pending. By doing this way,
1629 * we keep the state machine in tact and this would ultimately
1630 * prevent from doing cancel work multiple times when there are
1631 * new requests arriving before the current cancel work is done.
1632 */
1633 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1634 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1635 hba->clk_gating.state = CLKS_OFF;
7ff5ab47
SJ		 1636 trace_ufshcd_clk_gating(dev_name(hba->dev),
1637 hba->clk_gating.state);
1638 }
1ab27c9c
ST		 1639rel_lock:
1640 spin_unlock_irqrestore(hba->host->host_lock, flags);
1641out:
1642 return;
1643}
1644
1645/* host lock must be held before calling this variant */
1646static void __ufshcd_release(struct ufs_hba *hba)
1647{
1648 if (!ufshcd_is_clkgating_allowed(hba))
1649 return;
1650
1651 hba->clk_gating.active_reqs--;
1652
1653 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1654 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1655 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
53c12d0e
YG		 1656 || hba->active_uic_cmd || hba->uic_async_done
1657 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1658 return;
1659
1660 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1661 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1662 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1663 &hba->clk_gating.gate_work,
1664 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1665}
1666
1667void ufshcd_release(struct ufs_hba *hba)
1668{
1669 unsigned long flags;
1670
1671 spin_lock_irqsave(hba->host->host_lock, flags);
1672 __ufshcd_release(hba);
1673 spin_unlock_irqrestore(hba->host->host_lock, flags);
1674}
6e3fd44d 1675EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1676
1677static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1678 struct device_attribute *attr, char *buf)
1679{
1680 struct ufs_hba *hba = dev_get_drvdata(dev);
1681
1682 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1683}
1684
1685static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1686 struct device_attribute *attr, const char *buf, size_t count)
1687{
1688 struct ufs_hba *hba = dev_get_drvdata(dev);
1689 unsigned long flags, value;
1690
1691 if (kstrtoul(buf, 0, &value))
1692 return -EINVAL;
1693
1694 spin_lock_irqsave(hba->host->host_lock, flags);
1695 hba->clk_gating.delay_ms = value;
1696 spin_unlock_irqrestore(hba->host->host_lock, flags);
1697 return count;
1698}
1699
b427411a
ST		 1700static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1701 struct device_attribute *attr, char *buf)
1702{
1703 struct ufs_hba *hba = dev_get_drvdata(dev);
1704
1705 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1706}
1707
1708static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1709 struct device_attribute *attr, const char *buf, size_t count)
1710{
1711 struct ufs_hba *hba = dev_get_drvdata(dev);
1712 unsigned long flags;
1713 u32 value;
1714
1715 if (kstrtou32(buf, 0, &value))
1716 return -EINVAL;
1717
1718 value = !!value;
1719 if (value == hba->clk_gating.is_enabled)
1720 goto out;
1721
1722 if (value) {
1723 ufshcd_release(hba);
1724 } else {
1725 spin_lock_irqsave(hba->host->host_lock, flags);
1726 hba->clk_gating.active_reqs++;
1727 spin_unlock_irqrestore(hba->host->host_lock, flags);
1728 }
1729
1730 hba->clk_gating.is_enabled = value;
1731out:
1732 return count;
1733}
1734
eebcc196
VG		 1735static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1736{
1737 char wq_name[sizeof("ufs_clkscaling_00")];
1738
1739 if (!ufshcd_is_clkscaling_supported(hba))
1740 return;
1741
1742 INIT_WORK(&hba->clk_scaling.suspend_work,
1743 ufshcd_clk_scaling_suspend_work);
1744 INIT_WORK(&hba->clk_scaling.resume_work,
1745 ufshcd_clk_scaling_resume_work);
1746
1747 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1748 hba->host->host_no);
1749 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1750
1751 ufshcd_clkscaling_init_sysfs(hba);
1752}
1753
1754static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1755{
1756 if (!ufshcd_is_clkscaling_supported(hba))
1757 return;
1758
1759 destroy_workqueue(hba->clk_scaling.workq);
1760 ufshcd_devfreq_remove(hba);
1761}
1762
1ab27c9c
ST		 1763static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1764{
10e5e375
VV		 1765 char wq_name[sizeof("ufs_clk_gating_00")];
1766
1ab27c9c
ST		 1767 if (!ufshcd_is_clkgating_allowed(hba))
1768 return;
1769
1770 hba->clk_gating.delay_ms = 150;
1771 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1772 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1773
10e5e375
VV		 1774 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1775 hba->host->host_no);
1776 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1777 WQ_MEM_RECLAIM);
1778
b427411a
ST		 1779 hba->clk_gating.is_enabled = true;
1780
1ab27c9c
ST		 1781 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1782 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1783 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1784 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1785 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1786 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1787 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1788
1789 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1790 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1791 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1792 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1793 hba->clk_gating.enable_attr.attr.mode = 0644;
1794 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1795 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1796}
1797
1798static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1799{
1800 if (!ufshcd_is_clkgating_allowed(hba))
1801 return;
1802 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1803 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1804 cancel_work_sync(&hba->clk_gating.ungate_work);
1805 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
10e5e375 1806 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 1807}
1808
856b3483
ST		 1809/* Must be called with host lock acquired */
1810static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1811{
401f1e44
SJ		 1812 bool queue_resume_work = false;
1813
fcb0c4b0 1814 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1815 return;
1816
401f1e44
SJ		 1817 if (!hba->clk_scaling.active_reqs++)
1818 queue_resume_work = true;
1819
1820 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1821 return;
1822
1823 if (queue_resume_work)
1824 queue_work(hba->clk_scaling.workq,
1825 &hba->clk_scaling.resume_work);
1826
1827 if (!hba->clk_scaling.window_start_t) {
1828 hba->clk_scaling.window_start_t = jiffies;
1829 hba->clk_scaling.tot_busy_t = 0;
1830 hba->clk_scaling.is_busy_started = false;
1831 }
1832
856b3483
ST		 1833 if (!hba->clk_scaling.is_busy_started) {
1834 hba->clk_scaling.busy_start_t = ktime_get();
1835 hba->clk_scaling.is_busy_started = true;
1836 }
1837}
1838
1839static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1840{
1841 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1842
fcb0c4b0 1843 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1844 return;
1845
1846 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1847 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1848 scaling->busy_start_t));
8b0e1953 1849 scaling->busy_start_t = 0;
856b3483
ST		 1850 scaling->is_busy_started = false;
1851 }
1852}
7a3e97b0
SY		 1853/**
1854 * ufshcd_send_command - Send SCSI or device management commands
1855 * @hba: per adapter instance
1856 * @task_tag: Task tag of the command
1857 */
1858static inline
1859void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1860{
ff8e20c6 1861 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1862 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
eacf36f5 1863 ufshcd_add_command_trace(hba, task_tag, "send");
856b3483 1864 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1865 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1866 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1867 /* Make sure that doorbell is committed immediately */
1868 wmb();
7a3e97b0
SY		 1869}
1870
1871/**
1872 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 1873 * @lrbp: pointer to local reference block
7a3e97b0
SY		 1874 */
1875static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1876{
1877 int len;
1c2623c5
SJ		 1878 if (lrbp->sense_buffer &&
1879 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1880 int len_to_copy;
1881
5a0b0cb9 1882 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
09a5a24f 1883 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
e3ce73d6 1884
09a5a24f
AA		 1885 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
1886 len_to_copy);
7a3e97b0
SY		 1887 }
1888}
1889
68078d5c
DR		 1890/**
1891 * ufshcd_copy_query_response() - Copy the Query Response and the data
1892 * descriptor
1893 * @hba: per adapter instance
8aa29f19 1894 * @lrbp: pointer to local reference block
68078d5c
DR		 1895 */
1896static
c6d4a831 1897int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1898{
1899 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1900
68078d5c 1901 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1902
68078d5c 1903 /* Get the descriptor */
1c90836f
AA		 1904 if (hba->dev_cmd.query.descriptor &&
1905 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1906 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1907 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1908 u16 resp_len;
1909 u16 buf_len;
68078d5c
DR		 1910
1911 /* data segment length */
c6d4a831 1912 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1913 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1914 buf_len = be16_to_cpu(
1915 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1916 if (likely(buf_len >= resp_len)) {
1917 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1918 } else {
1919 dev_warn(hba->dev,
3d4881d1
BH		 1920 "%s: rsp size %d is bigger than buffer size %d",
1921 __func__, resp_len, buf_len);
c6d4a831
DR		 1922 return -EINVAL;
1923 }
68078d5c 1924 }
c6d4a831
DR		 1925
1926 return 0;
68078d5c
DR		 1927}
1928
7a3e97b0
SY		 1929/**
1930 * ufshcd_hba_capabilities - Read controller capabilities
1931 * @hba: per adapter instance
1932 */
1933static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1934{
b873a275 1935 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1936
1937 /* nutrs and nutmrs are 0 based values */
1938 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1939 hba->nutmrs =
1940 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1941}
1942
1943/**
6ccf44fe
SJ		 1944 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1945 * to accept UIC commands
7a3e97b0 1946 * @hba: per adapter instance
6ccf44fe
SJ		 1947 * Return true on success, else false
1948 */
1949static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1950{
1951 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1952 return true;
1953 else
1954 return false;
1955}
1956
53b3d9c3
SJ		 1957/**
1958 * ufshcd_get_upmcrs - Get the power mode change request status
1959 * @hba: Pointer to adapter instance
1960 *
1961 * This function gets the UPMCRS field of HCS register
1962 * Returns value of UPMCRS field
1963 */
1964static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1965{
1966 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1967}
1968
6ccf44fe
SJ		 1969/**
1970 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1971 * @hba: per adapter instance
1972 * @uic_cmd: UIC command
1973 *
1974 * Mutex must be held.
7a3e97b0
SY		 1975 */
1976static inline void
6ccf44fe 1977ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1978{
6ccf44fe
SJ		 1979 WARN_ON(hba->active_uic_cmd);
1980
1981 hba->active_uic_cmd = uic_cmd;
1982
7a3e97b0 1983 /* Write Args */
6ccf44fe
SJ		 1984 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1985 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1986 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1987
1988 /* Write UIC Cmd */
6ccf44fe 1989 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1990 REG_UIC_COMMAND);
7a3e97b0
SY		 1991}
1992
6ccf44fe
SJ		 1993/**
1994 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1995 * @hba: per adapter instance
8aa29f19 1996 * @uic_cmd: UIC command
6ccf44fe
SJ		 1997 *
1998 * Must be called with mutex held.
1999 * Returns 0 only if success.
2000 */
2001static int
2002ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2003{
2004 int ret;
2005 unsigned long flags;
2006
2007 if (wait_for_completion_timeout(&uic_cmd->done,
2008 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2009 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2010 else
2011 ret = -ETIMEDOUT;
2012
2013 spin_lock_irqsave(hba->host->host_lock, flags);
2014 hba->active_uic_cmd = NULL;
2015 spin_unlock_irqrestore(hba->host->host_lock, flags);
2016
2017 return ret;
2018}
2019
2020/**
2021 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2022 * @hba: per adapter instance
2023 * @uic_cmd: UIC command
d75f7fe4 2024 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 2025 *
2026 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 2027 * with mutex held and host_lock locked.
6ccf44fe
SJ		 2028 * Returns 0 only if success.
2029 */
2030static int
d75f7fe4
YG		 2031__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2032 bool completion)
6ccf44fe 2033{
6ccf44fe
SJ		 2034 if (!ufshcd_ready_for_uic_cmd(hba)) {
2035 dev_err(hba->dev,
2036 "Controller not ready to accept UIC commands\n");
2037 return -EIO;
2038 }
2039
d75f7fe4
YG		 2040 if (completion)
2041 init_completion(&uic_cmd->done);
6ccf44fe 2042
6ccf44fe 2043 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2044
57d104c1 2045 return 0;
6ccf44fe
SJ		 2046}
2047
2048/**
2049 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2050 * @hba: per adapter instance
2051 * @uic_cmd: UIC command
2052 *
2053 * Returns 0 only if success.
2054 */
e77044c5 2055int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2056{
2057 int ret;
57d104c1 2058 unsigned long flags;
6ccf44fe 2059
1ab27c9c 2060 ufshcd_hold(hba, false);
6ccf44fe 2061 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2062 ufshcd_add_delay_before_dme_cmd(hba);
2063
57d104c1 2064 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2065 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2066 spin_unlock_irqrestore(hba->host->host_lock, flags);
2067 if (!ret)
2068 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2069
6ccf44fe
SJ		 2070 mutex_unlock(&hba->uic_cmd_mutex);
2071
1ab27c9c 2072 ufshcd_release(hba);
6ccf44fe
SJ		 2073 return ret;
2074}
2075
7a3e97b0
SY		 2076/**
2077 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2078 * @hba: per adapter instance
2079 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2080 *
2081 * Returns 0 in case of success, non-zero value in case of failure
2082 */
75b1cc4a 2083static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2084{
2085 struct ufshcd_sg_entry *prd_table;
2086 struct scatterlist *sg;
2087 struct scsi_cmnd *cmd;
2088 int sg_segments;
2089 int i;
2090
2091 cmd = lrbp->cmd;
2092 sg_segments = scsi_dma_map(cmd);
2093 if (sg_segments < 0)
2094 return sg_segments;
2095
2096 if (sg_segments) {
75b1cc4a
KK		 2097 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2098 lrbp->utr_descriptor_ptr->prd_table_length =
2099 cpu_to_le16((u16)(sg_segments *
2100 sizeof(struct ufshcd_sg_entry)));
2101 else
2102 lrbp->utr_descriptor_ptr->prd_table_length =
2103 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2104
2105 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2106
2107 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2108 prd_table[i].size =
2109 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2110 prd_table[i].base_addr =
2111 cpu_to_le32(lower_32_bits(sg->dma_address));
2112 prd_table[i].upper_addr =
2113 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2114 prd_table[i].reserved = 0;
7a3e97b0
SY		 2115 }
2116 } else {
2117 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2118 }
2119
2120 return 0;
2121}
2122
2123/**
2fbd009b 2124 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2125 * @hba: per adapter instance
2fbd009b 2126 * @intrs: interrupt bits
7a3e97b0 2127 */
2fbd009b 2128static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2129{
2fbd009b
SJ		 2130 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2131
2132 if (hba->ufs_version == UFSHCI_VERSION_10) {
2133 u32 rw;
2134 rw = set & INTERRUPT_MASK_RW_VER_10;
2135 set = rw | ((set ^ intrs) & intrs);
2136 } else {
2137 set |= intrs;
2138 }
2139
2140 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2141}
2142
2143/**
2144 * ufshcd_disable_intr - disable interrupts
2145 * @hba: per adapter instance
2146 * @intrs: interrupt bits
2147 */
2148static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2149{
2150 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2151
2152 if (hba->ufs_version == UFSHCI_VERSION_10) {
2153 u32 rw;
2154 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2155 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2156 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2157
2158 } else {
2159 set &= ~intrs;
7a3e97b0 2160 }
2fbd009b
SJ		 2161
2162 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2163}
2164
5a0b0cb9
SRT		 2165/**
2166 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2167 * descriptor according to request
2168 * @lrbp: pointer to local reference block
2169 * @upiu_flags: flags required in the header
2170 * @cmd_dir: requests data direction
2171 */
2172static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2173 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2174{
2175 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2176 u32 data_direction;
2177 u32 dword_0;
2178
2179 if (cmd_dir == DMA_FROM_DEVICE) {
2180 data_direction = UTP_DEVICE_TO_HOST;
2181 *upiu_flags = UPIU_CMD_FLAGS_READ;
2182 } else if (cmd_dir == DMA_TO_DEVICE) {
2183 data_direction = UTP_HOST_TO_DEVICE;
2184 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2185 } else {
2186 data_direction = UTP_NO_DATA_TRANSFER;
2187 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2188 }
2189
2190 dword_0 = data_direction | (lrbp->command_type
2191 << UPIU_COMMAND_TYPE_OFFSET);
2192 if (lrbp->intr_cmd)
2193 dword_0 |= UTP_REQ_DESC_INT_CMD;
2194
2195 /* Transfer request descriptor header fields */
2196 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2197 /* dword_1 is reserved, hence it is set to 0 */
2198 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2199 /*
2200 * assigning invalid value for command status. Controller
2201 * updates OCS on command completion, with the command
2202 * status
2203 */
2204 req_desc->header.dword_2 =
2205 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2206 /* dword_3 is reserved, hence it is set to 0 */
2207 req_desc->header.dword_3 = 0;
51047266
YG		 2208
2209 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2210}
2211
2212/**
2213 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2214 * for scsi commands
8aa29f19
BVA		 2215 * @lrbp: local reference block pointer
2216 * @upiu_flags: flags
5a0b0cb9
SRT		 2217 */
2218static
2219void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2220{
1b21b8f0 2221 struct scsi_cmnd *cmd = lrbp->cmd;
5a0b0cb9 2222 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2223 unsigned short cdb_len;
5a0b0cb9
SRT		 2224
2225 /* command descriptor fields */
2226 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2227 UPIU_TRANSACTION_COMMAND, upiu_flags,
2228 lrbp->lun, lrbp->task_tag);
2229 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2230 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2231
2232 /* Total EHS length and Data segment length will be zero */
2233 ucd_req_ptr->header.dword_2 = 0;
2234
1b21b8f0 2235 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
5a0b0cb9 2236
1b21b8f0 2237 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
a851b2bd 2238 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1b21b8f0 2239 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
52ac95fe
YG		 2240
2241 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2242}
2243
68078d5c
DR		 2244/**
2245 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2246 * for query requsts
2247 * @hba: UFS hba
2248 * @lrbp: local reference block pointer
2249 * @upiu_flags: flags
2250 */
2251static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2252 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2253{
2254 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2255 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2256 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2257
2258 /* Query request header */
2259 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2260 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2261 lrbp->lun, lrbp->task_tag);
2262 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2263 0, query->request.query_func, 0, 0);
2264
6861285c
ZL		 2265 /* Data segment length only need for WRITE_DESC */
2266 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2267 ucd_req_ptr->header.dword_2 =
2268 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2269 else
2270 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2271
2272 /* Copy the Query Request buffer as is */
2273 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2274 QUERY_OSF_SIZE);
68078d5c
DR		 2275
2276 /* Copy the Descriptor */
c6d4a831 2277 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2278 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2279
51047266 2280 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2281}
2282
5a0b0cb9
SRT		 2283static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2284{
2285 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2286
2287 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2288
2289 /* command descriptor fields */
2290 ucd_req_ptr->header.dword_0 =
2291 UPIU_HEADER_DWORD(
2292 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2293 /* clear rest of the fields of basic header */
2294 ucd_req_ptr->header.dword_1 = 0;
2295 ucd_req_ptr->header.dword_2 = 0;
2296
2297 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2298}
2299
7a3e97b0 2300/**
300bb13f
JP		 2301 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2302 * for Device Management Purposes
8aa29f19
BVA		 2303 * @hba: per adapter instance
2304 * @lrbp: pointer to local reference block
7a3e97b0 2305 */
300bb13f 2306static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2307{
7a3e97b0 2308 u32 upiu_flags;
5a0b0cb9 2309 int ret = 0;
7a3e97b0 2310
83dc7e3d 2311 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2312 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2313 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2314 else
2315 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2316
2317 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2318 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2319 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2320 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2321 ufshcd_prepare_utp_nop_upiu(lrbp);
2322 else
2323 ret = -EINVAL;
2324
2325 return ret;
2326}
2327
2328/**
2329 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2330 * for SCSI Purposes
8aa29f19
BVA		 2331 * @hba: per adapter instance
2332 * @lrbp: pointer to local reference block
300bb13f
JP		 2333 */
2334static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2335{
2336 u32 upiu_flags;
2337 int ret = 0;
2338
83dc7e3d 2339 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2340 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2341 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2342 else
2343 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2344
2345 if (likely(lrbp->cmd)) {
2346 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2347 lrbp->cmd->sc_data_direction);
2348 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2349 } else {
2350 ret = -EINVAL;
2351 }
5a0b0cb9
SRT		 2352
2353 return ret;
7a3e97b0
SY		 2354}
2355
2a8fa600
SJ		 2356/**
2357 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2358 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2359 *
2360 * Returns SCSI W-LUN id
2361 */
2362static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2363{
2364 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2365}
2366
7a3e97b0
SY		 2367/**
2368 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2369 * @host: SCSI host pointer
7a3e97b0 2370 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2371 *
2372 * Returns 0 for success, non-zero in case of failure
2373 */
2374static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2375{
2376 struct ufshcd_lrb *lrbp;
2377 struct ufs_hba *hba;
2378 unsigned long flags;
2379 int tag;
2380 int err = 0;
2381
2382 hba = shost_priv(host);
2383
2384 tag = cmd->request->tag;
14497328
YG		 2385 if (!ufshcd_valid_tag(hba, tag)) {
2386 dev_err(hba->dev,
2387 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2388 __func__, tag, cmd, cmd->request);
2389 BUG();
2390 }
7a3e97b0 2391
a3cd5ec5
SJ		 2392 if (!down_read_trylock(&hba->clk_scaling_lock))
2393 return SCSI_MLQUEUE_HOST_BUSY;
2394
3441da7d
SRT		 2395 spin_lock_irqsave(hba->host->host_lock, flags);
2396 switch (hba->ufshcd_state) {
2397 case UFSHCD_STATE_OPERATIONAL:
2398 break;
141f8165 2399 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2400 case UFSHCD_STATE_RESET:
7a3e97b0 2401 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2402 goto out_unlock;
2403 case UFSHCD_STATE_ERROR:
2404 set_host_byte(cmd, DID_ERROR);
2405 cmd->scsi_done(cmd);
2406 goto out_unlock;
2407 default:
2408 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2409 __func__, hba->ufshcd_state);
2410 set_host_byte(cmd, DID_BAD_TARGET);
2411 cmd->scsi_done(cmd);
2412 goto out_unlock;
7a3e97b0 2413 }
53c12d0e
YG		 2414
2415 /* if error handling is in progress, don't issue commands */
2416 if (ufshcd_eh_in_progress(hba)) {
2417 set_host_byte(cmd, DID_ERROR);
2418 cmd->scsi_done(cmd);
2419 goto out_unlock;
2420 }
3441da7d 2421 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2422
7fabb77b
GB		 2423 hba->req_abort_count = 0;
2424
1ab27c9c
ST		 2425 err = ufshcd_hold(hba, true);
2426 if (err) {
2427 err = SCSI_MLQUEUE_HOST_BUSY;
1ab27c9c
ST		 2428 goto out;
2429 }
2430 WARN_ON(hba->clk_gating.state != CLKS_ON);
2431
7a3e97b0
SY		 2432 lrbp = &hba->lrb[tag];
2433
5a0b0cb9 2434 WARN_ON(lrbp->cmd);
7a3e97b0 2435 lrbp->cmd = cmd;
09a5a24f 2436 lrbp->sense_bufflen = UFS_SENSE_SIZE;
7a3e97b0
SY		 2437 lrbp->sense_buffer = cmd->sense_buffer;
2438 lrbp->task_tag = tag;
0ce147d4 2439 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2440 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2441 lrbp->req_abort_skip = false;
7a3e97b0 2442
300bb13f
JP		 2443 ufshcd_comp_scsi_upiu(hba, lrbp);
2444
75b1cc4a 2445 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2446 if (err) {
2447 lrbp->cmd = NULL;
17c7d35f 2448 ufshcd_release(hba);
7a3e97b0 2449 goto out;
5a0b0cb9 2450 }
ad1a1b9c
GB		 2451 /* Make sure descriptors are ready before ringing the doorbell */
2452 wmb();
7a3e97b0
SY		 2453
2454 /* issue command to the controller */
2455 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2456 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 2457 ufshcd_send_command(hba, tag);
3441da7d 2458out_unlock:
7a3e97b0
SY		 2459 spin_unlock_irqrestore(hba->host->host_lock, flags);
2460out:
a3cd5ec5 2461 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2462 return err;
2463}
2464
5a0b0cb9
SRT		 2465static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2466 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2467{
2468 lrbp->cmd = NULL;
2469 lrbp->sense_bufflen = 0;
2470 lrbp->sense_buffer = NULL;
2471 lrbp->task_tag = tag;
2472 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2473 lrbp->intr_cmd = true; /* No interrupt aggregation */
2474 hba->dev_cmd.type = cmd_type;
2475
300bb13f 2476 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2477}
2478
2479static int
2480ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2481{
2482 int err = 0;
2483 unsigned long flags;
2484 u32 mask = 1 << tag;
2485
2486 /* clear outstanding transaction before retry */
2487 spin_lock_irqsave(hba->host->host_lock, flags);
2488 ufshcd_utrl_clear(hba, tag);
2489 spin_unlock_irqrestore(hba->host->host_lock, flags);
2490
2491 /*
2492 * wait for for h/w to clear corresponding bit in door-bell.
2493 * max. wait is 1 sec.
2494 */
2495 err = ufshcd_wait_for_register(hba,
2496 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2497 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2498
2499 return err;
2500}
2501
c6d4a831
DR		 2502static int
2503ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2504{
2505 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2506
2507 /* Get the UPIU response */
2508 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2509 UPIU_RSP_CODE_OFFSET;
2510 return query_res->response;
2511}
2512
5a0b0cb9
SRT		 2513/**
2514 * ufshcd_dev_cmd_completion() - handles device management command responses
2515 * @hba: per adapter instance
2516 * @lrbp: pointer to local reference block
2517 */
2518static int
2519ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2520{
2521 int resp;
2522 int err = 0;
2523
ff8e20c6 2524 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2525 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2526
2527 switch (resp) {
2528 case UPIU_TRANSACTION_NOP_IN:
2529 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2530 err = -EINVAL;
2531 dev_err(hba->dev, "%s: unexpected response %x\n",
2532 __func__, resp);
2533 }
2534 break;
68078d5c 2535 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2536 err = ufshcd_check_query_response(hba, lrbp);
2537 if (!err)
2538 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2539 break;
5a0b0cb9
SRT		 2540 case UPIU_TRANSACTION_REJECT_UPIU:
2541 /* TODO: handle Reject UPIU Response */
2542 err = -EPERM;
2543 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2544 __func__);
2545 break;
2546 default:
2547 err = -EINVAL;
2548 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2549 __func__, resp);
2550 break;
2551 }
2552
2553 return err;
2554}
2555
2556static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2557 struct ufshcd_lrb *lrbp, int max_timeout)
2558{
2559 int err = 0;
2560 unsigned long time_left;
2561 unsigned long flags;
2562
2563 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2564 msecs_to_jiffies(max_timeout));
2565
ad1a1b9c
GB		 2566 /* Make sure descriptors are ready before ringing the doorbell */
2567 wmb();
5a0b0cb9
SRT		 2568 spin_lock_irqsave(hba->host->host_lock, flags);
2569 hba->dev_cmd.complete = NULL;
2570 if (likely(time_left)) {
2571 err = ufshcd_get_tr_ocs(lrbp);
2572 if (!err)
2573 err = ufshcd_dev_cmd_completion(hba, lrbp);
2574 }
2575 spin_unlock_irqrestore(hba->host->host_lock, flags);
2576
2577 if (!time_left) {
2578 err = -ETIMEDOUT;
a48353f6
YG		 2579 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2580 __func__, lrbp->task_tag);
5a0b0cb9 2581 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2582 /* successfully cleared the command, retry if needed */
5a0b0cb9 2583 err = -EAGAIN;
a48353f6
YG		 2584 /*
2585 * in case of an error, after clearing the doorbell,
2586 * we also need to clear the outstanding_request
2587 * field in hba
2588 */
2589 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2590 }
2591
2592 return err;
2593}
2594
5a0b0cb9
SRT		 2595/**
2596 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2597 * @hba: UFS hba
2598 * @cmd_type: specifies the type (NOP, Query...)
2599 * @timeout: time in seconds
5a0b0cb9 2600 *
68078d5c
DR		 2601 * NOTE: Since there is only one available tag for device management commands,
2602 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2603 */
2604static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2605 enum dev_cmd_type cmd_type, int timeout)
2606{
7252a360
BVA		 2607 struct request_queue *q = hba->cmd_queue;
2608 struct request *req;
5a0b0cb9
SRT		 2609 struct ufshcd_lrb *lrbp;
2610 int err;
2611 int tag;
2612 struct completion wait;
2613 unsigned long flags;
2614
a3cd5ec5
SJ		 2615 down_read(&hba->clk_scaling_lock);
2616
5a0b0cb9
SRT		 2617 /*
2618 * Get free slot, sleep if slots are unavailable.
2619 * Even though we use wait_event() which sleeps indefinitely,
2620 * the maximum wait time is bounded by SCSI request timeout.
2621 */
7252a360 2622 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 2623 if (IS_ERR(req)) {
2624 err = PTR_ERR(req);
2625 goto out_unlock;
2626 }
7252a360
BVA		 2627 tag = req->tag;
2628 WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
5a0b0cb9
SRT		 2629
2630 init_completion(&wait);
2631 lrbp = &hba->lrb[tag];
2632 WARN_ON(lrbp->cmd);
2633 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2634 if (unlikely(err))
2635 goto out_put_tag;
2636
2637 hba->dev_cmd.complete = &wait;
2638
6667e6d9 2639 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
e3dfdc53
YG		 2640 /* Make sure descriptors are ready before ringing the doorbell */
2641 wmb();
5a0b0cb9 2642 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2643 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 2644 ufshcd_send_command(hba, tag);
2645 spin_unlock_irqrestore(hba->host->host_lock, flags);
2646
2647 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2648
6667e6d9
OS		 2649 ufshcd_add_query_upiu_trace(hba, tag,
2650 err ? "query_complete_err" : "query_complete");
2651
5a0b0cb9 2652out_put_tag:
7252a360 2653 blk_put_request(req);
bb14dd15 2654out_unlock:
a3cd5ec5 2655 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2656 return err;
2657}
2658
d44a5f98
DR		 2659/**
2660 * ufshcd_init_query() - init the query response and request parameters
2661 * @hba: per-adapter instance
2662 * @request: address of the request pointer to be initialized
2663 * @response: address of the response pointer to be initialized
2664 * @opcode: operation to perform
2665 * @idn: flag idn to access
2666 * @index: LU number to access
2667 * @selector: query/flag/descriptor further identification
2668 */
2669static inline void ufshcd_init_query(struct ufs_hba *hba,
2670 struct ufs_query_req **request, struct ufs_query_res **response,
2671 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2672{
2673 *request = &hba->dev_cmd.query.request;
2674 *response = &hba->dev_cmd.query.response;
2675 memset(*request, 0, sizeof(struct ufs_query_req));
2676 memset(*response, 0, sizeof(struct ufs_query_res));
2677 (*request)->upiu_req.opcode = opcode;
2678 (*request)->upiu_req.idn = idn;
2679 (*request)->upiu_req.index = index;
2680 (*request)->upiu_req.selector = selector;
2681}
2682
dc3c8d3a
YG		 2683static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2684 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2685{
2686 int ret;
2687 int retries;
2688
2689 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2690 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2691 if (ret)
2692 dev_dbg(hba->dev,
2693 "%s: failed with error %d, retries %d\n",
2694 __func__, ret, retries);
2695 else
2696 break;
2697 }
2698
2699 if (ret)
2700 dev_err(hba->dev,
2701 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2702 __func__, opcode, idn, ret, retries);
2703 return ret;
2704}
2705
68078d5c
DR		 2706/**
2707 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 2708 * @hba: per-adapter instance
2709 * @opcode: flag query to perform
2710 * @idn: flag idn to access
2711 * @flag_res: the flag value after the query request completes
68078d5c
DR		 2712 *
2713 * Returns 0 for success, non-zero in case of failure
2714 */
dc3c8d3a 2715int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2716 enum flag_idn idn, bool *flag_res)
2717{
d44a5f98
DR		 2718 struct ufs_query_req *request = NULL;
2719 struct ufs_query_res *response = NULL;
2720 int err, index = 0, selector = 0;
e5ad406c 2721 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2722
2723 BUG_ON(!hba);
2724
1ab27c9c 2725 ufshcd_hold(hba, false);
68078d5c 2726 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2727 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2728 selector);
68078d5c
DR		 2729
2730 switch (opcode) {
2731 case UPIU_QUERY_OPCODE_SET_FLAG:
2732 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2733 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2734 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2735 break;
2736 case UPIU_QUERY_OPCODE_READ_FLAG:
2737 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2738 if (!flag_res) {
2739 /* No dummy reads */
2740 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2741 __func__);
2742 err = -EINVAL;
2743 goto out_unlock;
2744 }
2745 break;
2746 default:
2747 dev_err(hba->dev,
2748 "%s: Expected query flag opcode but got = %d\n",
2749 __func__, opcode);
2750 err = -EINVAL;
2751 goto out_unlock;
2752 }
68078d5c 2753
e5ad406c 2754 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2755
2756 if (err) {
2757 dev_err(hba->dev,
2758 "%s: Sending flag query for idn %d failed, err = %d\n",
2759 __func__, idn, err);
2760 goto out_unlock;
2761 }
2762
2763 if (flag_res)
e8c8e82a 2764 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2765 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2766
2767out_unlock:
2768 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2769 ufshcd_release(hba);
68078d5c
DR		 2770 return err;
2771}
2772
66ec6d59
SRT		 2773/**
2774 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 2775 * @hba: per-adapter instance
2776 * @opcode: attribute opcode
2777 * @idn: attribute idn to access
2778 * @index: index field
2779 * @selector: selector field
2780 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 2781 *
2782 * Returns 0 for success, non-zero in case of failure
2783*/
ec92b59c
SN		 2784int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2785 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 2786{
d44a5f98
DR		 2787 struct ufs_query_req *request = NULL;
2788 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2789 int err;
2790
2791 BUG_ON(!hba);
2792
1ab27c9c 2793 ufshcd_hold(hba, false);
66ec6d59
SRT		 2794 if (!attr_val) {
2795 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2796 __func__, opcode);
2797 err = -EINVAL;
2798 goto out;
2799 }
2800
2801 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2802 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2803 selector);
66ec6d59
SRT		 2804
2805 switch (opcode) {
2806 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2807 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2808 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2809 break;
2810 case UPIU_QUERY_OPCODE_READ_ATTR:
2811 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2812 break;
2813 default:
2814 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2815 __func__, opcode);
2816 err = -EINVAL;
2817 goto out_unlock;
2818 }
2819
d44a5f98 2820 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2821
2822 if (err) {
4b761b58
YG		 2823 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2824 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2825 goto out_unlock;
2826 }
2827
e8c8e82a 2828 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2829
2830out_unlock:
2831 mutex_unlock(&hba->dev_cmd.lock);
2832out:
1ab27c9c 2833 ufshcd_release(hba);
66ec6d59
SRT		 2834 return err;
2835}
2836
5e86ae44
YG		 2837/**
2838 * ufshcd_query_attr_retry() - API function for sending query
2839 * attribute with retries
2840 * @hba: per-adapter instance
2841 * @opcode: attribute opcode
2842 * @idn: attribute idn to access
2843 * @index: index field
2844 * @selector: selector field
2845 * @attr_val: the attribute value after the query request
2846 * completes
2847 *
2848 * Returns 0 for success, non-zero in case of failure
2849*/
2850static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2851 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2852 u32 *attr_val)
2853{
2854 int ret = 0;
2855 u32 retries;
2856
68c9fcfd 2857 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5e86ae44
YG		 2858 ret = ufshcd_query_attr(hba, opcode, idn, index,
2859 selector, attr_val);
2860 if (ret)
2861 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2862 __func__, ret, retries);
2863 else
2864 break;
2865 }
2866
2867 if (ret)
2868 dev_err(hba->dev,
2869 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2870 __func__, idn, ret, QUERY_REQ_RETRIES);
2871 return ret;
2872}
2873
a70e91b8 2874static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2875 enum query_opcode opcode, enum desc_idn idn, u8 index,
2876 u8 selector, u8 *desc_buf, int *buf_len)
2877{
2878 struct ufs_query_req *request = NULL;
2879 struct ufs_query_res *response = NULL;
2880 int err;
2881
2882 BUG_ON(!hba);
2883
1ab27c9c 2884 ufshcd_hold(hba, false);
d44a5f98
DR		 2885 if (!desc_buf) {
2886 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2887 __func__, opcode);
2888 err = -EINVAL;
2889 goto out;
2890 }
2891
a4b0e8a4 2892 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2893 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2894 __func__, *buf_len);
2895 err = -EINVAL;
2896 goto out;
2897 }
2898
2899 mutex_lock(&hba->dev_cmd.lock);
2900 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2901 selector);
2902 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2903 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2904
2905 switch (opcode) {
2906 case UPIU_QUERY_OPCODE_WRITE_DESC:
2907 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2908 break;
2909 case UPIU_QUERY_OPCODE_READ_DESC:
2910 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2911 break;
2912 default:
2913 dev_err(hba->dev,
2914 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2915 __func__, opcode);
2916 err = -EINVAL;
2917 goto out_unlock;
2918 }
2919
2920 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2921
2922 if (err) {
4b761b58
YG		 2923 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2924 __func__, opcode, idn, index, err);
d44a5f98
DR		 2925 goto out_unlock;
2926 }
2927
ea2aab24 2928 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2929
2930out_unlock:
cfcbae38 2931 hba->dev_cmd.query.descriptor = NULL;
d44a5f98
DR		 2932 mutex_unlock(&hba->dev_cmd.lock);
2933out:
1ab27c9c 2934 ufshcd_release(hba);
d44a5f98
DR		 2935 return err;
2936}
2937
a70e91b8 2938/**
8aa29f19
BVA		 2939 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
2940 * @hba: per-adapter instance
2941 * @opcode: attribute opcode
2942 * @idn: attribute idn to access
2943 * @index: index field
2944 * @selector: selector field
2945 * @desc_buf: the buffer that contains the descriptor
2946 * @buf_len: length parameter passed to the device
a70e91b8
YG		 2947 *
2948 * Returns 0 for success, non-zero in case of failure.
2949 * The buf_len parameter will contain, on return, the length parameter
2950 * received on the response.
2951 */
2238d31c
SN		 2952int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2953 enum query_opcode opcode,
2954 enum desc_idn idn, u8 index,
2955 u8 selector,
2956 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 2957{
2958 int err;
2959 int retries;
2960
2961 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2962 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2963 selector, desc_buf, buf_len);
2964 if (!err || err == -EINVAL)
2965 break;
2966 }
2967
2968 return err;
2969}
a70e91b8 2970
a4b0e8a4
PM		 2971/**
2972 * ufshcd_read_desc_length - read the specified descriptor length from header
2973 * @hba: Pointer to adapter instance
2974 * @desc_id: descriptor idn value
2975 * @desc_index: descriptor index
2976 * @desc_length: pointer to variable to read the length of descriptor
2977 *
2978 * Return 0 in case of success, non-zero otherwise
2979 */
2980static int ufshcd_read_desc_length(struct ufs_hba *hba,
2981 enum desc_idn desc_id,
2982 int desc_index,
2983 int *desc_length)
2984{
2985 int ret;
2986 u8 header[QUERY_DESC_HDR_SIZE];
2987 int header_len = QUERY_DESC_HDR_SIZE;
2988
2989 if (desc_id >= QUERY_DESC_IDN_MAX)
2990 return -EINVAL;
2991
2992 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2993 desc_id, desc_index, 0, header,
2994 &header_len);
2995
2996 if (ret) {
2997 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
2998 __func__, desc_id);
2999 return ret;
3000 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3001 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3002 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3003 desc_id);
3004 ret = -EINVAL;
3005 }
3006
3007 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3008 return ret;
3009
3010}
3011
3012/**
3013 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3014 * @hba: Pointer to adapter instance
3015 * @desc_id: descriptor idn value
3016 * @desc_len: mapped desc length (out)
3017 *
3018 * Return 0 in case of success, non-zero otherwise
3019 */
3020int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3021 enum desc_idn desc_id, int *desc_len)
3022{
3023 switch (desc_id) {
3024 case QUERY_DESC_IDN_DEVICE:
3025 *desc_len = hba->desc_size.dev_desc;
3026 break;
3027 case QUERY_DESC_IDN_POWER:
3028 *desc_len = hba->desc_size.pwr_desc;
3029 break;
3030 case QUERY_DESC_IDN_GEOMETRY:
3031 *desc_len = hba->desc_size.geom_desc;
3032 break;
3033 case QUERY_DESC_IDN_CONFIGURATION:
3034 *desc_len = hba->desc_size.conf_desc;
3035 break;
3036 case QUERY_DESC_IDN_UNIT:
3037 *desc_len = hba->desc_size.unit_desc;
3038 break;
3039 case QUERY_DESC_IDN_INTERCONNECT:
3040 *desc_len = hba->desc_size.interc_desc;
3041 break;
3042 case QUERY_DESC_IDN_STRING:
3043 *desc_len = QUERY_DESC_MAX_SIZE;
3044 break;
c648c2d2
SN		 3045 case QUERY_DESC_IDN_HEALTH:
3046 *desc_len = hba->desc_size.hlth_desc;
3047 break;
a4b0e8a4
PM		 3048 case QUERY_DESC_IDN_RFU_0:
3049 case QUERY_DESC_IDN_RFU_1:
3050 *desc_len = 0;
3051 break;
3052 default:
3053 *desc_len = 0;
3054 return -EINVAL;
3055 }
3056 return 0;
3057}
3058EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3059
da461cec
SJ		 3060/**
3061 * ufshcd_read_desc_param - read the specified descriptor parameter
3062 * @hba: Pointer to adapter instance
3063 * @desc_id: descriptor idn value
3064 * @desc_index: descriptor index
3065 * @param_offset: offset of the parameter to read
3066 * @param_read_buf: pointer to buffer where parameter would be read
3067 * @param_size: sizeof(param_read_buf)
3068 *
3069 * Return 0 in case of success, non-zero otherwise
3070 */
45bced87
SN		 3071int ufshcd_read_desc_param(struct ufs_hba *hba,
3072 enum desc_idn desc_id,
3073 int desc_index,
3074 u8 param_offset,
3075 u8 *param_read_buf,
3076 u8 param_size)
da461cec
SJ		 3077{
3078 int ret;
3079 u8 *desc_buf;
a4b0e8a4 3080 int buff_len;
da461cec
SJ		 3081 bool is_kmalloc = true;
3082
a4b0e8a4
PM		 3083 /* Safety check */
3084 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3085 return -EINVAL;
3086
a4b0e8a4
PM		 3087 /* Get the max length of descriptor from structure filled up at probe
3088 * time.
3089 */
3090 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3091
a4b0e8a4
PM		 3092 /* Sanity checks */
3093 if (ret || !buff_len) {
3094 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3095 __func__);
3096 return ret;
3097 }
3098
3099 /* Check whether we need temp memory */
3100 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3101 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3102 if (!desc_buf)
3103 return -ENOMEM;
a4b0e8a4
PM		 3104 } else {
3105 desc_buf = param_read_buf;
3106 is_kmalloc = false;
da461cec
SJ		 3107 }
3108
a4b0e8a4 3109 /* Request for full descriptor */
a70e91b8 3110 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3111 desc_id, desc_index, 0,
3112 desc_buf, &buff_len);
da461cec 3113
bde44bb6
SJ		 3114 if (ret) {
3115 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3116 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3117 goto out;
3118 }
3119
bde44bb6
SJ		 3120 /* Sanity check */
3121 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3122 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3123 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3124 ret = -EINVAL;
3125 goto out;
3126 }
3127
a4b0e8a4
PM		 3128 /* Check wherher we will not copy more data, than available */
3129 if (is_kmalloc && param_size > buff_len)
3130 param_size = buff_len;
bde44bb6 3131
da461cec
SJ		 3132 if (is_kmalloc)
3133 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3134out:
3135 if (is_kmalloc)
3136 kfree(desc_buf);
3137 return ret;
3138}
3139
3140static inline int ufshcd_read_desc(struct ufs_hba *hba,
3141 enum desc_idn desc_id,
3142 int desc_index,
4b828fe1 3143 void *buf,
da461cec
SJ		 3144 u32 size)
3145{
3146 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3147}
3148
3149static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3150 u8 *buf,
3151 u32 size)
3152{
dbd34a61 3153 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
da461cec
SJ		 3154}
3155
8209b6d5 3156static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3157{
3158 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3159}
b573d484 3160
4b828fe1
TW		 3161/**
3162 * struct uc_string_id - unicode string
3163 *
3164 * @len: size of this descriptor inclusive
3165 * @type: descriptor type
3166 * @uc: unicode string character
3167 */
3168struct uc_string_id {
3169 u8 len;
3170 u8 type;
3171 wchar_t uc[0];
3172} __packed;
3173
3174/* replace non-printable or non-ASCII characters with spaces */
3175static inline char ufshcd_remove_non_printable(u8 ch)
3176{
3177 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3178}
3179
b573d484
YG		 3180/**
3181 * ufshcd_read_string_desc - read string descriptor
3182 * @hba: pointer to adapter instance
3183 * @desc_index: descriptor index
4b828fe1
TW		 3184 * @buf: pointer to buffer where descriptor would be read,
3185 * the caller should free the memory.
b573d484 3186 * @ascii: if true convert from unicode to ascii characters
4b828fe1 3187 * null terminated string.
b573d484 3188 *
4b828fe1
TW		 3189 * Return:
3190 * * string size on success.
3191 * * -ENOMEM: on allocation failure
3192 * * -EINVAL: on a wrong parameter
b573d484 3193 */
4b828fe1
TW		 3194int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3195 u8 **buf, bool ascii)
b573d484 3196{
4b828fe1
TW		 3197 struct uc_string_id *uc_str;
3198 u8 *str;
3199 int ret;
b573d484 3200
4b828fe1
TW		 3201 if (!buf)
3202 return -EINVAL;
b573d484 3203
4b828fe1
TW		 3204 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3205 if (!uc_str)
3206 return -ENOMEM;
b573d484 3207
4b828fe1
TW		 3208 ret = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING,
3209 desc_index, uc_str,
3210 QUERY_DESC_MAX_SIZE);
3211 if (ret < 0) {
3212 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3213 QUERY_REQ_RETRIES, ret);
3214 str = NULL;
3215 goto out;
3216 }
3217
3218 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3219 dev_dbg(hba->dev, "String Desc is of zero length\n");
3220 str = NULL;
3221 ret = 0;
b573d484
YG		 3222 goto out;
3223 }
3224
3225 if (ascii) {
4b828fe1 3226 ssize_t ascii_len;
b573d484 3227 int i;
b573d484 3228 /* remove header and divide by 2 to move from UTF16 to UTF8 */
4b828fe1
TW		 3229 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3230 str = kzalloc(ascii_len, GFP_KERNEL);
3231 if (!str) {
3232 ret = -ENOMEM;
fcbefc3b 3233 goto out;
b573d484
YG		 3234 }
3235
3236 /*
3237 * the descriptor contains string in UTF16 format
3238 * we need to convert to utf-8 so it can be displayed
3239 */
4b828fe1
TW		 3240 ret = utf16s_to_utf8s(uc_str->uc,
3241 uc_str->len - QUERY_DESC_HDR_SIZE,
3242 UTF16_BIG_ENDIAN, str, ascii_len);
b573d484
YG		 3243
3244 /* replace non-printable or non-ASCII characters with spaces */
4b828fe1
TW		 3245 for (i = 0; i < ret; i++)
3246 str[i] = ufshcd_remove_non_printable(str[i]);
b573d484 3247
4b828fe1
TW		 3248 str[ret++] = '\0';
3249
3250 } else {
5f57704d 3251 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
4b828fe1
TW		 3252 if (!str) {
3253 ret = -ENOMEM;
3254 goto out;
3255 }
4b828fe1 3256 ret = uc_str->len;
b573d484
YG		 3257 }
3258out:
4b828fe1
TW		 3259 *buf = str;
3260 kfree(uc_str);
3261 return ret;
b573d484 3262}
b573d484 3263
da461cec
SJ		 3264/**
3265 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3266 * @hba: Pointer to adapter instance
3267 * @lun: lun id
3268 * @param_offset: offset of the parameter to read
3269 * @param_read_buf: pointer to buffer where parameter would be read
3270 * @param_size: sizeof(param_read_buf)
3271 *
3272 * Return 0 in case of success, non-zero otherwise
3273 */
3274static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3275 int lun,
3276 enum unit_desc_param param_offset,
3277 u8 *param_read_buf,
3278 u32 param_size)
3279{
3280 /*
3281 * Unit descriptors are only available for general purpose LUs (LUN id
3282 * from 0 to 7) and RPMB Well known LU.
3283 */
d829fc8a 3284 if (!ufs_is_valid_unit_desc_lun(lun))
da461cec
SJ		 3285 return -EOPNOTSUPP;
3286
3287 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3288 param_offset, param_read_buf, param_size);
3289}
3290
7a3e97b0
SY		 3291/**
3292 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3293 * @hba: per adapter instance
3294 *
3295 * 1. Allocate DMA memory for Command Descriptor array
3296 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3297 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3298 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3299 * (UTMRDL)
3300 * 4. Allocate memory for local reference block(lrb).
3301 *
3302 * Returns 0 for success, non-zero in case of failure
3303 */
3304static int ufshcd_memory_alloc(struct ufs_hba *hba)
3305{
3306 size_t utmrdl_size, utrdl_size, ucdl_size;
3307
3308 /* Allocate memory for UTP command descriptors */
3309 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3310 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3311 ucdl_size,
3312 &hba->ucdl_dma_addr,
3313 GFP_KERNEL);
7a3e97b0
SY		 3314
3315 /*
3316 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3317 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3318 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3319 * be aligned to 128 bytes as well
3320 */
3321 if (!hba->ucdl_base_addr ||
3322 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3323 dev_err(hba->dev,
7a3e97b0
SY		 3324 "Command Descriptor Memory allocation failed\n");
3325 goto out;
3326 }
3327
3328 /*
3329 * Allocate memory for UTP Transfer descriptors
3330 * UFSHCI requires 1024 byte alignment of UTRD
3331 */
3332 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3333 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3334 utrdl_size,
3335 &hba->utrdl_dma_addr,
3336 GFP_KERNEL);
7a3e97b0
SY		 3337 if (!hba->utrdl_base_addr ||
3338 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3339 dev_err(hba->dev,
7a3e97b0
SY		 3340 "Transfer Descriptor Memory allocation failed\n");
3341 goto out;
3342 }
3343
3344 /*
3345 * Allocate memory for UTP Task Management descriptors
3346 * UFSHCI requires 1024 byte alignment of UTMRD
3347 */
3348 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3349 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3350 utmrdl_size,
3351 &hba->utmrdl_dma_addr,
3352 GFP_KERNEL);
7a3e97b0
SY		 3353 if (!hba->utmrdl_base_addr ||
3354 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3355 dev_err(hba->dev,
7a3e97b0
SY		 3356 "Task Management Descriptor Memory allocation failed\n");
3357 goto out;
3358 }
3359
3360 /* Allocate memory for local reference block */
a86854d0
KC		 3361 hba->lrb = devm_kcalloc(hba->dev,
3362 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3363 GFP_KERNEL);
7a3e97b0 3364 if (!hba->lrb) {
3b1d0580 3365 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3366 goto out;
3367 }
3368 return 0;
3369out:
7a3e97b0
SY		 3370 return -ENOMEM;
3371}
3372
3373/**
3374 * ufshcd_host_memory_configure - configure local reference block with
3375 * memory offsets
3376 * @hba: per adapter instance
3377 *
3378 * Configure Host memory space
3379 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3380 * address.
3381 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3382 * and PRDT offset.
3383 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3384 * into local reference block.
3385 */
3386static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3387{
3388 struct utp_transfer_cmd_desc *cmd_descp;
3389 struct utp_transfer_req_desc *utrdlp;
3390 dma_addr_t cmd_desc_dma_addr;
3391 dma_addr_t cmd_desc_element_addr;
3392 u16 response_offset;
3393 u16 prdt_offset;
3394 int cmd_desc_size;
3395 int i;
3396
3397 utrdlp = hba->utrdl_base_addr;
3398 cmd_descp = hba->ucdl_base_addr;
3399
3400 response_offset =
3401 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3402 prdt_offset =
3403 offsetof(struct utp_transfer_cmd_desc, prd_table);
3404
3405 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3406 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3407
3408 for (i = 0; i < hba->nutrs; i++) {
3409 /* Configure UTRD with command descriptor base address */
3410 cmd_desc_element_addr =
3411 (cmd_desc_dma_addr + (cmd_desc_size * i));
3412 utrdlp[i].command_desc_base_addr_lo =
3413 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3414 utrdlp[i].command_desc_base_addr_hi =
3415 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3416
3417 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3418 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3419 utrdlp[i].response_upiu_offset =
3420 cpu_to_le16(response_offset);
3421 utrdlp[i].prd_table_offset =
3422 cpu_to_le16(prdt_offset);
3423 utrdlp[i].response_upiu_length =
3424 cpu_to_le16(ALIGNED_UPIU_SIZE);
3425 } else {
3426 utrdlp[i].response_upiu_offset =
7a3e97b0 3427 cpu_to_le16((response_offset >> 2));
75b1cc4a 3428 utrdlp[i].prd_table_offset =
7a3e97b0 3429 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3430 utrdlp[i].response_upiu_length =
3ca316c5 3431 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3432 }
7a3e97b0
SY		 3433
3434 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3435 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3436 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3437 hba->lrb[i].ucd_req_ptr =
3438 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3439 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3440 hba->lrb[i].ucd_rsp_ptr =
3441 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3442 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3443 response_offset;
7a3e97b0
SY		 3444 hba->lrb[i].ucd_prdt_ptr =
3445 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3446 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3447 prdt_offset;
7a3e97b0
SY		 3448 }
3449}
3450
3451/**
3452 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3453 * @hba: per adapter instance
3454 *
3455 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3456 * in order to initialize the Unipro link startup procedure.
3457 * Once the Unipro links are up, the device connected to the controller
3458 * is detected.
3459 *
3460 * Returns 0 on success, non-zero value on failure
3461 */
3462static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3463{
6ccf44fe
SJ		 3464 struct uic_command uic_cmd = {0};
3465 int ret;
7a3e97b0 3466
6ccf44fe 3467 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3468
6ccf44fe
SJ		 3469 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3470 if (ret)
ff8e20c6 3471 dev_dbg(hba->dev,
6ccf44fe
SJ		 3472 "dme-link-startup: error code %d\n", ret);
3473 return ret;
7a3e97b0 3474}
4404c5de
AA		 3475/**
3476 * ufshcd_dme_reset - UIC command for DME_RESET
3477 * @hba: per adapter instance
3478 *
3479 * DME_RESET command is issued in order to reset UniPro stack.
3480 * This function now deal with cold reset.
3481 *
3482 * Returns 0 on success, non-zero value on failure
3483 */
3484static int ufshcd_dme_reset(struct ufs_hba *hba)
3485{
3486 struct uic_command uic_cmd = {0};
3487 int ret;
3488
3489 uic_cmd.command = UIC_CMD_DME_RESET;
3490
3491 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3492 if (ret)
3493 dev_err(hba->dev,
3494 "dme-reset: error code %d\n", ret);
3495
3496 return ret;
3497}
3498
3499/**
3500 * ufshcd_dme_enable - UIC command for DME_ENABLE
3501 * @hba: per adapter instance
3502 *
3503 * DME_ENABLE command is issued in order to enable UniPro stack.
3504 *
3505 * Returns 0 on success, non-zero value on failure
3506 */
3507static int ufshcd_dme_enable(struct ufs_hba *hba)
3508{
3509 struct uic_command uic_cmd = {0};
3510 int ret;
3511
3512 uic_cmd.command = UIC_CMD_DME_ENABLE;
3513
3514 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3515 if (ret)
3516 dev_err(hba->dev,
3517 "dme-reset: error code %d\n", ret);
3518
3519 return ret;
3520}
7a3e97b0 3521
cad2e03d
YG		 3522static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3523{
3524 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3525 unsigned long min_sleep_time_us;
3526
3527 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3528 return;
3529
3530 /*
3531 * last_dme_cmd_tstamp will be 0 only for 1st call to
3532 * this function
3533 */
3534 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3535 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3536 } else {
3537 unsigned long delta =
3538 (unsigned long) ktime_to_us(
3539 ktime_sub(ktime_get(),
3540 hba->last_dme_cmd_tstamp));
3541
3542 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3543 min_sleep_time_us =
3544 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3545 else
3546 return; /* no more delay required */
3547 }
3548
3549 /* allow sleep for extra 50us if needed */
3550 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3551}
3552
12b4fdb4
SJ		 3553/**
3554 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3555 * @hba: per adapter instance
3556 * @attr_sel: uic command argument1
3557 * @attr_set: attribute set type as uic command argument2
3558 * @mib_val: setting value as uic command argument3
3559 * @peer: indicate whether peer or local
3560 *
3561 * Returns 0 on success, non-zero value on failure
3562 */
3563int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3564 u8 attr_set, u32 mib_val, u8 peer)
3565{
3566 struct uic_command uic_cmd = {0};
3567 static const char *const action[] = {
3568 "dme-set",
3569 "dme-peer-set"
3570 };
3571 const char *set = action[!!peer];
3572 int ret;
64238fbd 3573 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3574
3575 uic_cmd.command = peer ?
3576 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3577 uic_cmd.argument1 = attr_sel;
3578 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3579 uic_cmd.argument3 = mib_val;
3580
64238fbd
YG		 3581 do {
3582 /* for peer attributes we retry upon failure */
3583 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3584 if (ret)
3585 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3586 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3587 } while (ret && peer && --retries);
3588
f37e9f8c 3589 if (ret)
64238fbd 3590 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3591 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3592 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3593
3594 return ret;
3595}
3596EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3597
3598/**
3599 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3600 * @hba: per adapter instance
3601 * @attr_sel: uic command argument1
3602 * @mib_val: the value of the attribute as returned by the UIC command
3603 * @peer: indicate whether peer or local
3604 *
3605 * Returns 0 on success, non-zero value on failure
3606 */
3607int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3608 u32 *mib_val, u8 peer)
3609{
3610 struct uic_command uic_cmd = {0};
3611 static const char *const action[] = {
3612 "dme-get",
3613 "dme-peer-get"
3614 };
3615 const char *get = action[!!peer];
3616 int ret;
64238fbd 3617 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3618 struct ufs_pa_layer_attr orig_pwr_info;
3619 struct ufs_pa_layer_attr temp_pwr_info;
3620 bool pwr_mode_change = false;
3621
3622 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3623 orig_pwr_info = hba->pwr_info;
3624 temp_pwr_info = orig_pwr_info;
3625
3626 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3627 orig_pwr_info.pwr_rx == FAST_MODE) {
3628 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3629 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3630 pwr_mode_change = true;
3631 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3632 orig_pwr_info.pwr_rx == SLOW_MODE) {
3633 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3634 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3635 pwr_mode_change = true;
3636 }
3637 if (pwr_mode_change) {
3638 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3639 if (ret)
3640 goto out;
3641 }
3642 }
12b4fdb4
SJ		 3643
3644 uic_cmd.command = peer ?
3645 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3646 uic_cmd.argument1 = attr_sel;
3647
64238fbd
YG		 3648 do {
3649 /* for peer attributes we retry upon failure */
3650 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3651 if (ret)
3652 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3653 get, UIC_GET_ATTR_ID(attr_sel), ret);
3654 } while (ret && peer && --retries);
3655
f37e9f8c 3656 if (ret)
64238fbd 3657 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3658 get, UIC_GET_ATTR_ID(attr_sel),
3659 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3660
64238fbd 3661 if (mib_val && !ret)
12b4fdb4 3662 *mib_val = uic_cmd.argument3;
874237f7
YG		 3663
3664 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3665 && pwr_mode_change)
3666 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3667out:
3668 return ret;
3669}
3670EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3671
53b3d9c3 3672/**
57d104c1
SJ		 3673 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3674 * state) and waits for it to take effect.
3675 *
53b3d9c3 3676 * @hba: per adapter instance
57d104c1
SJ		 3677 * @cmd: UIC command to execute
3678 *
3679 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3680 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3681 * and device UniPro link and hence it's final completion would be indicated by
3682 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3683 * addition to normal UIC command completion Status (UCCS). This function only
3684 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3685 *
3686 * Returns 0 on success, non-zero value on failure
3687 */
57d104c1 3688static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3689{
57d104c1 3690 struct completion uic_async_done;
53b3d9c3
SJ		 3691 unsigned long flags;
3692 u8 status;
3693 int ret;
d75f7fe4 3694 bool reenable_intr = false;
53b3d9c3 3695
53b3d9c3 3696 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3697 init_completion(&uic_async_done);
cad2e03d 3698 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3699
3700 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3701 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3702 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3703 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3704 /*
3705 * Make sure UIC command completion interrupt is disabled before
3706 * issuing UIC command.
3707 */
3708 wmb();
3709 reenable_intr = true;
57d104c1 3710 }
d75f7fe4
YG		 3711 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3712 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3713 if (ret) {
3714 dev_err(hba->dev,
3715 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3716 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3717 goto out;
3718 }
3719
57d104c1 3720 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3721 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3722 dev_err(hba->dev,
57d104c1
SJ		 3723 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3724 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3725 ret = -ETIMEDOUT;
3726 goto out;
3727 }
3728
3729 status = ufshcd_get_upmcrs(hba);
3730 if (status != PWR_LOCAL) {
3731 dev_err(hba->dev,
479da360 3732 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3733 cmd->command, status);
53b3d9c3
SJ		 3734 ret = (status != PWR_OK) ? status : -1;
3735 }
3736out:
7942f7b5
VG		 3737 if (ret) {
3738 ufshcd_print_host_state(hba);
3739 ufshcd_print_pwr_info(hba);
3740 ufshcd_print_host_regs(hba);
3741 }
3742
53b3d9c3 3743 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3744 hba->active_uic_cmd = NULL;
57d104c1 3745 hba->uic_async_done = NULL;
d75f7fe4
YG		 3746 if (reenable_intr)
3747 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3748 spin_unlock_irqrestore(hba->host->host_lock, flags);
3749 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3750
53b3d9c3
SJ		 3751 return ret;
3752}
3753
57d104c1
SJ		 3754/**
3755 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3756 * using DME_SET primitives.
3757 * @hba: per adapter instance
3758 * @mode: powr mode value
3759 *
3760 * Returns 0 on success, non-zero value on failure
3761 */
3762static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3763{
3764 struct uic_command uic_cmd = {0};
1ab27c9c 3765 int ret;
57d104c1 3766
c3a2f9ee
YG		 3767 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3768 ret = ufshcd_dme_set(hba,
3769 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3770 if (ret) {
3771 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3772 __func__, ret);
3773 goto out;
3774 }
3775 }
3776
57d104c1
SJ		 3777 uic_cmd.command = UIC_CMD_DME_SET;
3778 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3779 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3780 ufshcd_hold(hba, false);
3781 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3782 ufshcd_release(hba);
57d104c1 3783
c3a2f9ee 3784out:
1ab27c9c 3785 return ret;
57d104c1
SJ		 3786}
3787
53c12d0e
YG		 3788static int ufshcd_link_recovery(struct ufs_hba *hba)
3789{
3790 int ret;
3791 unsigned long flags;
3792
3793 spin_lock_irqsave(hba->host->host_lock, flags);
3794 hba->ufshcd_state = UFSHCD_STATE_RESET;
3795 ufshcd_set_eh_in_progress(hba);
3796 spin_unlock_irqrestore(hba->host->host_lock, flags);
3797
ebdd1dfd
CG		 3798 /* Reset the attached device */
3799 ufshcd_vops_device_reset(hba);
3800
53c12d0e
YG		 3801 ret = ufshcd_host_reset_and_restore(hba);
3802
3803 spin_lock_irqsave(hba->host->host_lock, flags);
3804 if (ret)
3805 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3806 ufshcd_clear_eh_in_progress(hba);
3807 spin_unlock_irqrestore(hba->host->host_lock, flags);
3808
3809 if (ret)
3810 dev_err(hba->dev, "%s: link recovery failed, err %d",
3811 __func__, ret);
3812
3813 return ret;
3814}
3815
87d0b4a6 3816static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3817{
87d0b4a6 3818 int ret;
57d104c1 3819 struct uic_command uic_cmd = {0};
911a0771 3820 ktime_t start = ktime_get();
57d104c1 3821
ee32c909
KK		 3822 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3823
57d104c1 3824 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3825 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3826 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3827 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3828
53c12d0e 3829 if (ret) {
6d303e4b
SJ		 3830 int err;
3831
87d0b4a6
YG		 3832 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3833 __func__, ret);
3834
53c12d0e 3835 /*
6d303e4b
SJ		 3836 * If link recovery fails then return error code returned from
3837 * ufshcd_link_recovery().
3838 * If link recovery succeeds then return -EAGAIN to attempt
3839 * hibern8 enter retry again.
53c12d0e 3840 */
6d303e4b
SJ		 3841 err = ufshcd_link_recovery(hba);
3842 if (err) {
3843 dev_err(hba->dev, "%s: link recovery failed", __func__);
3844 ret = err;
3845 } else {
3846 ret = -EAGAIN;
3847 }
ee32c909
KK		 3848 } else
3849 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3850 POST_CHANGE);
53c12d0e 3851
87d0b4a6
YG		 3852 return ret;
3853}
3854
3855static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3856{
3857 int ret = 0, retries;
57d104c1 3858
87d0b4a6
YG		 3859 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3860 ret = __ufshcd_uic_hibern8_enter(hba);
6d303e4b 3861 if (!ret)
87d0b4a6
YG		 3862 goto out;
3863 }
3864out:
3865 return ret;
57d104c1
SJ		 3866}
3867
3868static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3869{
3870 struct uic_command uic_cmd = {0};
3871 int ret;
911a0771 3872 ktime_t start = ktime_get();
57d104c1 3873
ee32c909
KK		 3874 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3875
57d104c1
SJ		 3876 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3877 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3878 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3879 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3880
57d104c1 3881 if (ret) {
53c12d0e
YG		 3882 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3883 __func__, ret);
3884 ret = ufshcd_link_recovery(hba);
ff8e20c6 3885 } else {
ee32c909
KK		 3886 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3887 POST_CHANGE);
ff8e20c6
DR		 3888 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3889 hba->ufs_stats.hibern8_exit_cnt++;
3890 }
57d104c1
SJ		 3891
3892 return ret;
3893}
3894
ba7af5ec
SC		 3895void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
3896{
3897 unsigned long flags;
3898
3899 if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT))
3900 return;
3901
3902 spin_lock_irqsave(hba->host->host_lock, flags);
3903 if (hba->ahit == ahit)
3904 goto out_unlock;
3905 hba->ahit = ahit;
3906 if (!pm_runtime_suspended(hba->dev))
3907 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3908out_unlock:
3909 spin_unlock_irqrestore(hba->host->host_lock, flags);
3910}
3911EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
3912
71d848b8 3913void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
ad448378
AH		 3914{
3915 unsigned long flags;
3916
ee5f1042 3917 if (!ufshcd_is_auto_hibern8_supported(hba) || !hba->ahit)
ad448378
AH		 3918 return;
3919
3920 spin_lock_irqsave(hba->host->host_lock, flags);
3921 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3922 spin_unlock_irqrestore(hba->host->host_lock, flags);
3923}
3924
5064636c
YG		 3925 /**
3926 * ufshcd_init_pwr_info - setting the POR (power on reset)
3927 * values in hba power info
3928 * @hba: per-adapter instance
3929 */
3930static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3931{
3932 hba->pwr_info.gear_rx = UFS_PWM_G1;
3933 hba->pwr_info.gear_tx = UFS_PWM_G1;
3934 hba->pwr_info.lane_rx = 1;
3935 hba->pwr_info.lane_tx = 1;
3936 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3937 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3938 hba->pwr_info.hs_rate = 0;
3939}
3940
d3e89bac 3941/**
7eb584db
DR		 3942 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3943 * @hba: per-adapter instance
d3e89bac 3944 */
7eb584db 3945static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3946{
7eb584db
DR		 3947 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3948
3949 if (hba->max_pwr_info.is_valid)
3950 return 0;
3951
2349b533
SJ		 3952 pwr_info->pwr_tx = FAST_MODE;
3953 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3954 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3955
3956 /* Get the connected lane count */
7eb584db
DR		 3957 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3958 &pwr_info->lane_rx);
3959 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3960 &pwr_info->lane_tx);
3961
3962 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3963 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3964 __func__,
3965 pwr_info->lane_rx,
3966 pwr_info->lane_tx);
3967 return -EINVAL;
3968 }
d3e89bac
SJ		 3969
3970 /*
3971 * First, get the maximum gears of HS speed.
3972 * If a zero value, it means there is no HSGEAR capability.
3973 * Then, get the maximum gears of PWM speed.
3974 */
7eb584db
DR		 3975 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3976 if (!pwr_info->gear_rx) {
3977 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3978 &pwr_info->gear_rx);
3979 if (!pwr_info->gear_rx) {
3980 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3981 __func__, pwr_info->gear_rx);
3982 return -EINVAL;
3983 }
2349b533 3984 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3985 }
3986
7eb584db
DR		 3987 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3988 &pwr_info->gear_tx);
3989 if (!pwr_info->gear_tx) {
d3e89bac 3990 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3991 &pwr_info->gear_tx);
3992 if (!pwr_info->gear_tx) {
3993 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3994 __func__, pwr_info->gear_tx);
3995 return -EINVAL;
3996 }
2349b533 3997 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3998 }
3999
4000 hba->max_pwr_info.is_valid = true;
4001 return 0;
4002}
4003
4004static int ufshcd_change_power_mode(struct ufs_hba *hba,
4005 struct ufs_pa_layer_attr *pwr_mode)
4006{
4007 int ret;
4008
4009 /* if already configured to the requested pwr_mode */
4010 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4011 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4012 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4013 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4014 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4015 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4016 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4017 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4018 return 0;
d3e89bac
SJ		 4019 }
4020
4021 /*
4022 * Configure attributes for power mode change with below.
4023 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4024 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4025 * - PA_HSSERIES
4026 */
7eb584db
DR		 4027 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4028 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4029 pwr_mode->lane_rx);
4030 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4031 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4032 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4033 else
4034 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4035
7eb584db
DR		 4036 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4037 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4038 pwr_mode->lane_tx);
4039 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4040 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4041 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4042 else
4043 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4044
7eb584db
DR		 4045 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4046 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4047 pwr_mode->pwr_rx == FAST_MODE ||
4048 pwr_mode->pwr_tx == FAST_MODE)
4049 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4050 pwr_mode->hs_rate);
d3e89bac 4051
08342537
CG		 4052 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4053 DL_FC0ProtectionTimeOutVal_Default);
4054 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4055 DL_TC0ReplayTimeOutVal_Default);
4056 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4057 DL_AFC0ReqTimeOutVal_Default);
4058 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4059 DL_FC1ProtectionTimeOutVal_Default);
4060 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4061 DL_TC1ReplayTimeOutVal_Default);
4062 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4063 DL_AFC1ReqTimeOutVal_Default);
4064
4065 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4066 DL_FC0ProtectionTimeOutVal_Default);
4067 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4068 DL_TC0ReplayTimeOutVal_Default);
4069 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4070 DL_AFC0ReqTimeOutVal_Default);
4071
7eb584db
DR		 4072 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4073 | pwr_mode->pwr_tx);
4074
4075 if (ret) {
d3e89bac 4076 dev_err(hba->dev,
7eb584db
DR		 4077 "%s: power mode change failed %d\n", __func__, ret);
4078 } else {
0263bcd0
YG		 4079 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4080 pwr_mode);
7eb584db
DR		 4081
4082 memcpy(&hba->pwr_info, pwr_mode,
4083 sizeof(struct ufs_pa_layer_attr));
4084 }
4085
4086 return ret;
4087}
4088
4089/**
4090 * ufshcd_config_pwr_mode - configure a new power mode
4091 * @hba: per-adapter instance
4092 * @desired_pwr_mode: desired power configuration
4093 */
0d846e70 4094int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4095 struct ufs_pa_layer_attr *desired_pwr_mode)
4096{
4097 struct ufs_pa_layer_attr final_params = { 0 };
4098 int ret;
4099
0263bcd0
YG		 4100 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4101 desired_pwr_mode, &final_params);
4102
4103 if (ret)
7eb584db
DR		 4104 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4105
4106 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5
SJ		 4107 if (!ret)
4108 ufshcd_print_pwr_info(hba);
d3e89bac
SJ		 4109
4110 return ret;
4111}
0d846e70 4112EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4113
68078d5c
DR		 4114/**
4115 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4116 * @hba: per-adapter instance
68078d5c
DR		 4117 *
4118 * Set fDeviceInit flag and poll until device toggles it.
4119 */
4120static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4121{
dc3c8d3a
YG		 4122 int i;
4123 int err;
68078d5c
DR		 4124 bool flag_res = 1;
4125
dc3c8d3a
YG		 4126 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4127 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 4128 if (err) {
4129 dev_err(hba->dev,
4130 "%s setting fDeviceInit flag failed with error %d\n",
4131 __func__, err);
4132 goto out;
4133 }
4134
dc3c8d3a
YG		 4135 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4136 for (i = 0; i < 1000 && !err && flag_res; i++)
4137 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4138 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4139
68078d5c
DR		 4140 if (err)
4141 dev_err(hba->dev,
4142 "%s reading fDeviceInit flag failed with error %d\n",
4143 __func__, err);
4144 else if (flag_res)
4145 dev_err(hba->dev,
4146 "%s fDeviceInit was not cleared by the device\n",
4147 __func__);
4148
4149out:
4150 return err;
4151}
4152
7a3e97b0
SY		 4153/**
4154 * ufshcd_make_hba_operational - Make UFS controller operational
4155 * @hba: per adapter instance
4156 *
4157 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4158 * 1. Enable required interrupts
4159 * 2. Configure interrupt aggregation
897efe62 4160 * 3. Program UTRL and UTMRL base address
5c0c28a8 4161 * 4. Configure run-stop-registers
7a3e97b0
SY		 4162 *
4163 * Returns 0 on success, non-zero value on failure
4164 */
4165static int ufshcd_make_hba_operational(struct ufs_hba *hba)
4166{
4167 int err = 0;
4168 u32 reg;
4169
6ccf44fe
SJ		 4170 /* Enable required interrupts */
4171 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4172
4173 /* Configure interrupt aggregation */
b852190e
YG		 4174 if (ufshcd_is_intr_aggr_allowed(hba))
4175 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4176 else
4177 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4178
4179 /* Configure UTRL and UTMRL base address registers */
4180 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4181 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4182 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4183 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4184 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4185 REG_UTP_TASK_REQ_LIST_BASE_L);
4186 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4187 REG_UTP_TASK_REQ_LIST_BASE_H);
4188
897efe62
YG		 4189 /*
4190 * Make sure base address and interrupt setup are updated before
4191 * enabling the run/stop registers below.
4192 */
4193 wmb();
4194
7a3e97b0
SY		 4195 /*
4196 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4197 */
5c0c28a8 4198 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4199 if (!(ufshcd_get_lists_status(reg))) {
4200 ufshcd_enable_run_stop_reg(hba);
4201 } else {
3b1d0580 4202 dev_err(hba->dev,
7a3e97b0
SY		 4203 "Host controller not ready to process requests");
4204 err = -EIO;
4205 goto out;
4206 }
4207
7a3e97b0
SY		 4208out:
4209 return err;
4210}
4211
596585a2
YG		 4212/**
4213 * ufshcd_hba_stop - Send controller to reset state
4214 * @hba: per adapter instance
4215 * @can_sleep: perform sleep or just spin
4216 */
4217static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4218{
4219 int err;
4220
4221 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4222 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4223 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4224 10, 1, can_sleep);
4225 if (err)
4226 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4227}
4228
7a3e97b0 4229/**
4404c5de 4230 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4231 * @hba: per adapter instance
4232 *
4233 * The controller resets itself and controller firmware initialization
4234 * sequence kicks off. When controller is ready it will set
4235 * the Host Controller Enable bit to 1.
4236 *
4237 * Returns 0 on success, non-zero value on failure
4238 */
4404c5de 4239static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0
SY		 4240{
4241 int retry;
4242
596585a2 4243 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4244 /* change controller state to "reset state" */
596585a2 4245 ufshcd_hba_stop(hba, true);
7a3e97b0 4246
57d104c1
SJ		 4247 /* UniPro link is disabled at this point */
4248 ufshcd_set_link_off(hba);
4249
0263bcd0 4250 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4251
7a3e97b0
SY		 4252 /* start controller initialization sequence */
4253 ufshcd_hba_start(hba);
4254
4255 /*
4256 * To initialize a UFS host controller HCE bit must be set to 1.
4257 * During initialization the HCE bit value changes from 1->0->1.
4258 * When the host controller completes initialization sequence
4259 * it sets the value of HCE bit to 1. The same HCE bit is read back
4260 * to check if the controller has completed initialization sequence.
4261 * So without this delay the value HCE = 1, set in the previous
4262 * instruction might be read back.
4263 * This delay can be changed based on the controller.
4264 */
838c1efc 4265 usleep_range(1000, 1100);
7a3e97b0
SY		 4266
4267 /* wait for the host controller to complete initialization */
4268 retry = 10;
4269 while (ufshcd_is_hba_active(hba)) {
4270 if (retry) {
4271 retry--;
4272 } else {
3b1d0580 4273 dev_err(hba->dev,
7a3e97b0
SY		 4274 "Controller enable failed\n");
4275 return -EIO;
4276 }
838c1efc 4277 usleep_range(5000, 5100);
7a3e97b0 4278 }
5c0c28a8 4279
1d337ec2 4280 /* enable UIC related interrupts */
57d104c1 4281 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4282
0263bcd0 4283 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4284
7a3e97b0
SY		 4285 return 0;
4286}
4287
4404c5de
AA		 4288static int ufshcd_hba_enable(struct ufs_hba *hba)
4289{
4290 int ret;
4291
4292 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4293 ufshcd_set_link_off(hba);
4294 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4295
4296 /* enable UIC related interrupts */
4297 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4298 ret = ufshcd_dme_reset(hba);
4299 if (!ret) {
4300 ret = ufshcd_dme_enable(hba);
4301 if (!ret)
4302 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4303 if (ret)
4304 dev_err(hba->dev,
4305 "Host controller enable failed with non-hce\n");
4306 }
4307 } else {
4308 ret = ufshcd_hba_execute_hce(hba);
4309 }
4310
4311 return ret;
4312}
7ca38cf3
YG		 4313static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4314{
4315 int tx_lanes, i, err = 0;
4316
4317 if (!peer)
4318 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4319 &tx_lanes);
4320 else
4321 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4322 &tx_lanes);
4323 for (i = 0; i < tx_lanes; i++) {
4324 if (!peer)
4325 err = ufshcd_dme_set(hba,
4326 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4327 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4328 0);
4329 else
4330 err = ufshcd_dme_peer_set(hba,
4331 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4332 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4333 0);
4334 if (err) {
4335 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4336 __func__, peer, i, err);
4337 break;
4338 }
4339 }
4340
4341 return err;
4342}
4343
4344static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4345{
4346 return ufshcd_disable_tx_lcc(hba, true);
4347}
4348
8808b4e9
SC		 4349static void ufshcd_update_reg_hist(struct ufs_err_reg_hist *reg_hist,
4350 u32 reg)
4351{
4352 reg_hist->reg[reg_hist->pos] = reg;
4353 reg_hist->tstamp[reg_hist->pos] = ktime_get();
4354 reg_hist->pos = (reg_hist->pos + 1) % UFS_ERR_REG_HIST_LENGTH;
4355}
4356
7a3e97b0 4357/**
6ccf44fe 4358 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4359 * @hba: per adapter instance
4360 *
6ccf44fe 4361 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4362 */
6ccf44fe 4363static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4364{
6ccf44fe 4365 int ret;
1d337ec2 4366 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4367 bool link_startup_again = false;
7a3e97b0 4368
7caf489b
SJ		 4369 /*
4370 * If UFS device isn't active then we will have to issue link startup
4371 * 2 times to make sure the device state move to active.
4372 */
4373 if (!ufshcd_is_ufs_dev_active(hba))
4374 link_startup_again = true;
7a3e97b0 4375
7caf489b 4376link_startup:
1d337ec2 4377 do {
0263bcd0 4378 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4379
1d337ec2 4380 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4381
1d337ec2
SRT		 4382 /* check if device is detected by inter-connect layer */
4383 if (!ret && !ufshcd_is_device_present(hba)) {
8808b4e9
SC		 4384 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4385 0);
1d337ec2
SRT		 4386 dev_err(hba->dev, "%s: Device not present\n", __func__);
4387 ret = -ENXIO;
4388 goto out;
4389 }
6ccf44fe 4390
1d337ec2
SRT		 4391 /*
4392 * DME link lost indication is only received when link is up,
4393 * but we can't be sure if the link is up until link startup
4394 * succeeds. So reset the local Uni-Pro and try again.
4395 */
8808b4e9
SC		 4396 if (ret && ufshcd_hba_enable(hba)) {
4397 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4398 (u32)ret);
1d337ec2 4399 goto out;
8808b4e9 4400 }
1d337ec2
SRT		 4401 } while (ret && retries--);
4402
8808b4e9 4403 if (ret) {
1d337ec2 4404 /* failed to get the link up... retire */
8808b4e9
SC		 4405 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4406 (u32)ret);
5c0c28a8 4407 goto out;
8808b4e9 4408 }
5c0c28a8 4409
7caf489b
SJ		 4410 if (link_startup_again) {
4411 link_startup_again = false;
4412 retries = DME_LINKSTARTUP_RETRIES;
4413 goto link_startup;
4414 }
4415
d2aebb9b
SJ		 4416 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4417 ufshcd_init_pwr_info(hba);
4418 ufshcd_print_pwr_info(hba);
4419
7ca38cf3
YG		 4420 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4421 ret = ufshcd_disable_device_tx_lcc(hba);
4422 if (ret)
4423 goto out;
4424 }
4425
5c0c28a8 4426 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4427 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4428 if (ret)
4429 goto out;
7a3e97b0 4430
5c0c28a8 4431 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4432out:
7942f7b5 4433 if (ret) {
6ccf44fe 4434 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4435 ufshcd_print_host_state(hba);
4436 ufshcd_print_pwr_info(hba);
4437 ufshcd_print_host_regs(hba);
4438 }
6ccf44fe 4439 return ret;
7a3e97b0
SY		 4440}
4441
5a0b0cb9
SRT		 4442/**
4443 * ufshcd_verify_dev_init() - Verify device initialization
4444 * @hba: per-adapter instance
4445 *
4446 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4447 * device Transport Protocol (UTP) layer is ready after a reset.
4448 * If the UTP layer at the device side is not initialized, it may
4449 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4450 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4451 */
4452static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4453{
4454 int err = 0;
4455 int retries;
4456
1ab27c9c 4457 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4458 mutex_lock(&hba->dev_cmd.lock);
4459 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4460 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4461 NOP_OUT_TIMEOUT);
4462
4463 if (!err || err == -ETIMEDOUT)
4464 break;
4465
4466 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4467 }
4468 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4469 ufshcd_release(hba);
5a0b0cb9
SRT		 4470
4471 if (err)
4472 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4473 return err;
4474}
4475
0ce147d4
SJ		 4476/**
4477 * ufshcd_set_queue_depth - set lun queue depth
4478 * @sdev: pointer to SCSI device
4479 *
4480 * Read bLUQueueDepth value and activate scsi tagged command
4481 * queueing. For WLUN, queue depth is set to 1. For best-effort
4482 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4483 * value that host can queue.
4484 */
4485static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4486{
4487 int ret = 0;
4488 u8 lun_qdepth;
4489 struct ufs_hba *hba;
4490
4491 hba = shost_priv(sdev->host);
4492
4493 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4494 ret = ufshcd_read_unit_desc_param(hba,
4495 ufshcd_scsi_to_upiu_lun(sdev->lun),
4496 UNIT_DESC_PARAM_LU_Q_DEPTH,
4497 &lun_qdepth,
4498 sizeof(lun_qdepth));
0ce147d4
SJ		 4499
4500 /* Some WLUN doesn't support unit descriptor */
4501 if (ret == -EOPNOTSUPP)
4502 lun_qdepth = 1;
4503 else if (!lun_qdepth)
4504 /* eventually, we can figure out the real queue depth */
4505 lun_qdepth = hba->nutrs;
4506 else
4507 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4508
4509 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4510 __func__, lun_qdepth);
db5ed4df 4511 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4512}
4513
57d104c1
SJ		 4514/*
4515 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4516 * @hba: per-adapter instance
4517 * @lun: UFS device lun id
4518 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4519 *
4520 * Returns 0 in case of success and b_lu_write_protect status would be returned
4521 * @b_lu_write_protect parameter.
4522 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4523 * Returns -EINVAL in case of invalid parameters passed to this function.
4524 */
4525static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4526 u8 lun,
4527 u8 *b_lu_write_protect)
4528{
4529 int ret;
4530
4531 if (!b_lu_write_protect)
4532 ret = -EINVAL;
4533 /*
4534 * According to UFS device spec, RPMB LU can't be write
4535 * protected so skip reading bLUWriteProtect parameter for
4536 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4537 */
4538 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4539 ret = -ENOTSUPP;
4540 else
4541 ret = ufshcd_read_unit_desc_param(hba,
4542 lun,
4543 UNIT_DESC_PARAM_LU_WR_PROTECT,
4544 b_lu_write_protect,
4545 sizeof(*b_lu_write_protect));
4546 return ret;
4547}
4548
4549/**
4550 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4551 * status
4552 * @hba: per-adapter instance
4553 * @sdev: pointer to SCSI device
4554 *
4555 */
4556static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4557 struct scsi_device *sdev)
4558{
4559 if (hba->dev_info.f_power_on_wp_en &&
4560 !hba->dev_info.is_lu_power_on_wp) {
4561 u8 b_lu_write_protect;
4562
4563 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4564 &b_lu_write_protect) &&
4565 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4566 hba->dev_info.is_lu_power_on_wp = true;
4567 }
4568}
4569
7a3e97b0
SY		 4570/**
4571 * ufshcd_slave_alloc - handle initial SCSI device configurations
4572 * @sdev: pointer to SCSI device
4573 *
4574 * Returns success
4575 */
4576static int ufshcd_slave_alloc(struct scsi_device *sdev)
4577{
4578 struct ufs_hba *hba;
4579
4580 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4581
4582 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4583 sdev->use_10_for_ms = 1;
a3a76391
CG		 4584
4585 /* DBD field should be set to 1 in mode sense(10) */
4586 sdev->set_dbd_for_ms = 1;
7a3e97b0 4587
e8e7f271
SRT		 4588 /* allow SCSI layer to restart the device in case of errors */
4589 sdev->allow_restart = 1;
4264fd61 4590
b2a6c522
SRT		 4591 /* REPORT SUPPORTED OPERATION CODES is not supported */
4592 sdev->no_report_opcodes = 1;
4593
84af7e8b
SRT		 4594 /* WRITE_SAME command is not supported */
4595 sdev->no_write_same = 1;
e8e7f271 4596
0ce147d4 4597 ufshcd_set_queue_depth(sdev);
4264fd61 4598
57d104c1
SJ		 4599 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4600
7a3e97b0
SY		 4601 return 0;
4602}
4603
4264fd61
SRT		 4604/**
4605 * ufshcd_change_queue_depth - change queue depth
4606 * @sdev: pointer to SCSI device
4607 * @depth: required depth to set
4264fd61 4608 *
db5ed4df 4609 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4610 */
db5ed4df 4611static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4612{
4613 struct ufs_hba *hba = shost_priv(sdev->host);
4614
4615 if (depth > hba->nutrs)
4616 depth = hba->nutrs;
db5ed4df 4617 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4618}
4619
eeda4749
AM		 4620/**
4621 * ufshcd_slave_configure - adjust SCSI device configurations
4622 * @sdev: pointer to SCSI device
4623 */
4624static int ufshcd_slave_configure(struct scsi_device *sdev)
4625{
49615ba1 4626 struct ufs_hba *hba = shost_priv(sdev->host);
eeda4749
AM		 4627 struct request_queue *q = sdev->request_queue;
4628
4629 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
49615ba1
SC		 4630
4631 if (ufshcd_is_rpm_autosuspend_allowed(hba))
4632 sdev->rpm_autosuspend = 1;
4633
eeda4749
AM		 4634 return 0;
4635}
4636
7a3e97b0
SY		 4637/**
4638 * ufshcd_slave_destroy - remove SCSI device configurations
4639 * @sdev: pointer to SCSI device
4640 */
4641static void ufshcd_slave_destroy(struct scsi_device *sdev)
4642{
4643 struct ufs_hba *hba;
4644
4645 hba = shost_priv(sdev->host);
0ce147d4 4646 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4647 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4648 unsigned long flags;
4649
4650 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4651 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4652 spin_unlock_irqrestore(hba->host->host_lock, flags);
4653 }
7a3e97b0
SY		 4654}
4655
7a3e97b0
SY		 4656/**
4657 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 4658 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4659 * @scsi_status: SCSI command status
4660 *
4661 * Returns value base on SCSI command status
4662 */
4663static inline int
4664ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4665{
4666 int result = 0;
4667
4668 switch (scsi_status) {
7a3e97b0 4669 case SAM_STAT_CHECK_CONDITION:
1c2623c5 4670 ufshcd_copy_sense_data(lrbp);
30eb2e4c 4671 /* fallthrough */
1c2623c5 4672 case SAM_STAT_GOOD:
7a3e97b0
SY		 4673 result |= DID_OK << 16 |
4674 COMMAND_COMPLETE << 8 |
1c2623c5 4675 scsi_status;
7a3e97b0
SY		 4676 break;
4677 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4678 case SAM_STAT_BUSY:
7a3e97b0 4679 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4680 ufshcd_copy_sense_data(lrbp);
4681 result |= scsi_status;
7a3e97b0
SY		 4682 break;
4683 default:
4684 result |= DID_ERROR << 16;
4685 break;
4686 } /* end of switch */
4687
4688 return result;
4689}
4690
4691/**
4692 * ufshcd_transfer_rsp_status - Get overall status of the response
4693 * @hba: per adapter instance
8aa29f19 4694 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4695 *
4696 * Returns result of the command to notify SCSI midlayer
4697 */
4698static inline int
4699ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4700{
4701 int result = 0;
4702 int scsi_status;
4703 int ocs;
4704
4705 /* overall command status of utrd */
4706 ocs = ufshcd_get_tr_ocs(lrbp);
4707
4708 switch (ocs) {
4709 case OCS_SUCCESS:
5a0b0cb9 4710 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4711 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4712 switch (result) {
4713 case UPIU_TRANSACTION_RESPONSE:
4714 /*
4715 * get the response UPIU result to extract
4716 * the SCSI command status
4717 */
4718 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4719
4720 /*
4721 * get the result based on SCSI status response
4722 * to notify the SCSI midlayer of the command status
4723 */
4724 scsi_status = result & MASK_SCSI_STATUS;
4725 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4726
f05ac2e5
YG		 4727 /*
4728 * Currently we are only supporting BKOPs exception
4729 * events hence we can ignore BKOPs exception event
4730 * during power management callbacks. BKOPs exception
4731 * event is not expected to be raised in runtime suspend
4732 * callback as it allows the urgent bkops.
4733 * During system suspend, we are anyway forcefully
4734 * disabling the bkops and if urgent bkops is needed
4735 * it will be enabled on system resume. Long term
4736 * solution could be to abort the system suspend if
4737 * UFS device needs urgent BKOPs.
4738 */
4739 if (!hba->pm_op_in_progress &&
4740 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 4741 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 4742 break;
4743 case UPIU_TRANSACTION_REJECT_UPIU:
4744 /* TODO: handle Reject UPIU Response */
4745 result = DID_ERROR << 16;
3b1d0580 4746 dev_err(hba->dev,
5a0b0cb9
SRT		 4747 "Reject UPIU not fully implemented\n");
4748 break;
4749 default:
5a0b0cb9
SRT		 4750 dev_err(hba->dev,
4751 "Unexpected request response code = %x\n",
4752 result);
e0347d89 4753 result = DID_ERROR << 16;
7a3e97b0
SY		 4754 break;
4755 }
7a3e97b0
SY		 4756 break;
4757 case OCS_ABORTED:
4758 result |= DID_ABORT << 16;
4759 break;
e8e7f271
SRT		 4760 case OCS_INVALID_COMMAND_STATUS:
4761 result |= DID_REQUEUE << 16;
4762 break;
7a3e97b0
SY		 4763 case OCS_INVALID_CMD_TABLE_ATTR:
4764 case OCS_INVALID_PRDT_ATTR:
4765 case OCS_MISMATCH_DATA_BUF_SIZE:
4766 case OCS_MISMATCH_RESP_UPIU_SIZE:
4767 case OCS_PEER_COMM_FAILURE:
4768 case OCS_FATAL_ERROR:
4769 default:
4770 result |= DID_ERROR << 16;
3b1d0580 4771 dev_err(hba->dev,
ff8e20c6
DR		 4772 "OCS error from controller = %x for tag %d\n",
4773 ocs, lrbp->task_tag);
4774 ufshcd_print_host_regs(hba);
6ba65588 4775 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4776 break;
4777 } /* end of switch */
4778
2df74b69 4779 if ((host_byte(result) != DID_OK) && !hba->silence_err_logs)
66cc820f 4780 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4781 return result;
4782}
4783
6ccf44fe
SJ		 4784/**
4785 * ufshcd_uic_cmd_compl - handle completion of uic command
4786 * @hba: per adapter instance
53b3d9c3 4787 * @intr_status: interrupt status generated by the controller
9333d775
VG		 4788 *
4789 * Returns
4790 * IRQ_HANDLED - If interrupt is valid
4791 * IRQ_NONE - If invalid interrupt
6ccf44fe 4792 */
9333d775 4793static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4794{
9333d775
VG		 4795 irqreturn_t retval = IRQ_NONE;
4796
53b3d9c3 4797 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4798 hba->active_uic_cmd->argument2 |=
4799 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4800 hba->active_uic_cmd->argument3 =
4801 ufshcd_get_dme_attr_val(hba);
6ccf44fe 4802 complete(&hba->active_uic_cmd->done);
9333d775 4803 retval = IRQ_HANDLED;
6ccf44fe 4804 }
53b3d9c3 4805
9333d775 4806 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
57d104c1 4807 complete(hba->uic_async_done);
9333d775
VG		 4808 retval = IRQ_HANDLED;
4809 }
4810 return retval;
6ccf44fe
SJ		 4811}
4812
7a3e97b0 4813/**
9a47ec7c 4814 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4815 * @hba: per adapter instance
9a47ec7c 4816 * @completed_reqs: requests to complete
7a3e97b0 4817 */
9a47ec7c
YG		 4818static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4819 unsigned long completed_reqs)
7a3e97b0 4820{
5a0b0cb9
SRT		 4821 struct ufshcd_lrb *lrbp;
4822 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4823 int result;
4824 int index;
e9d501b1 4825
e9d501b1
DR		 4826 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4827 lrbp = &hba->lrb[index];
4828 cmd = lrbp->cmd;
4829 if (cmd) {
1a07f2d9 4830 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4831 result = ufshcd_transfer_rsp_status(hba, lrbp);
4832 scsi_dma_unmap(cmd);
4833 cmd->result = result;
4834 /* Mark completed command as NULL in LRB */
4835 lrbp->cmd = NULL;
74a527a2 4836 lrbp->compl_time_stamp = ktime_get();
e9d501b1
DR		 4837 /* Do not touch lrbp after scsi done */
4838 cmd->scsi_done(cmd);
1ab27c9c 4839 __ufshcd_release(hba);
300bb13f
JP		 4840 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4841 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
74a527a2 4842 lrbp->compl_time_stamp = ktime_get();
1a07f2d9
LS		 4843 if (hba->dev_cmd.complete) {
4844 ufshcd_add_command_trace(hba, index,
4845 "dev_complete");
e9d501b1 4846 complete(hba->dev_cmd.complete);
1a07f2d9 4847 }
e9d501b1 4848 }
401f1e44
SJ		 4849 if (ufshcd_is_clkscaling_supported(hba))
4850 hba->clk_scaling.active_reqs--;
e9d501b1 4851 }
7a3e97b0
SY		 4852
4853 /* clear corresponding bits of completed commands */
4854 hba->outstanding_reqs ^= completed_reqs;
4855
856b3483 4856 ufshcd_clk_scaling_update_busy(hba);
7a3e97b0
SY		 4857}
4858
9a47ec7c
YG		 4859/**
4860 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4861 * @hba: per adapter instance
9333d775
VG		 4862 *
4863 * Returns
4864 * IRQ_HANDLED - If interrupt is valid
4865 * IRQ_NONE - If invalid interrupt
9a47ec7c 4866 */
9333d775 4867static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
9a47ec7c
YG		 4868{
4869 unsigned long completed_reqs;
4870 u32 tr_doorbell;
4871
4872 /* Resetting interrupt aggregation counters first and reading the
4873 * DOOR_BELL afterward allows us to handle all the completed requests.
4874 * In order to prevent other interrupts starvation the DB is read once
4875 * after reset. The down side of this solution is the possibility of
4876 * false interrupt if device completes another request after resetting
4877 * aggregation and before reading the DB.
4878 */
5ac6abc9
AA		 4879 if (ufshcd_is_intr_aggr_allowed(hba) &&
4880 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 4881 ufshcd_reset_intr_aggr(hba);
4882
4883 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4884 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4885
9333d775
VG		 4886 if (completed_reqs) {
4887 __ufshcd_transfer_req_compl(hba, completed_reqs);
4888 return IRQ_HANDLED;
4889 } else {
4890 return IRQ_NONE;
4891 }
9a47ec7c
YG		 4892}
4893
66ec6d59
SRT		 4894/**
4895 * ufshcd_disable_ee - disable exception event
4896 * @hba: per-adapter instance
4897 * @mask: exception event to disable
4898 *
4899 * Disables exception event in the device so that the EVENT_ALERT
4900 * bit is not set.
4901 *
4902 * Returns zero on success, non-zero error value on failure.
4903 */
4904static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4905{
4906 int err = 0;
4907 u32 val;
4908
4909 if (!(hba->ee_ctrl_mask & mask))
4910 goto out;
4911
4912 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4913 val &= MASK_EE_STATUS;
5e86ae44 4914 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4915 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4916 if (!err)
4917 hba->ee_ctrl_mask &= ~mask;
4918out:
4919 return err;
4920}
4921
4922/**
4923 * ufshcd_enable_ee - enable exception event
4924 * @hba: per-adapter instance
4925 * @mask: exception event to enable
4926 *
4927 * Enable corresponding exception event in the device to allow
4928 * device to alert host in critical scenarios.
4929 *
4930 * Returns zero on success, non-zero error value on failure.
4931 */
4932static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4933{
4934 int err = 0;
4935 u32 val;
4936
4937 if (hba->ee_ctrl_mask & mask)
4938 goto out;
4939
4940 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4941 val &= MASK_EE_STATUS;
5e86ae44 4942 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4943 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4944 if (!err)
4945 hba->ee_ctrl_mask |= mask;
4946out:
4947 return err;
4948}
4949
4950/**
4951 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4952 * @hba: per-adapter instance
4953 *
4954 * Allow device to manage background operations on its own. Enabling
4955 * this might lead to inconsistent latencies during normal data transfers
4956 * as the device is allowed to manage its own way of handling background
4957 * operations.
4958 *
4959 * Returns zero on success, non-zero on failure.
4960 */
4961static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4962{
4963 int err = 0;
4964
4965 if (hba->auto_bkops_enabled)
4966 goto out;
4967
dc3c8d3a 4968 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4969 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4970 if (err) {
4971 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4972 __func__, err);
4973 goto out;
4974 }
4975
4976 hba->auto_bkops_enabled = true;
7ff5ab47 4977 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4978
4979 /* No need of URGENT_BKOPS exception from the device */
4980 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4981 if (err)
4982 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4983 __func__, err);
4984out:
4985 return err;
4986}
4987
4988/**
4989 * ufshcd_disable_auto_bkops - block device in doing background operations
4990 * @hba: per-adapter instance
4991 *
4992 * Disabling background operations improves command response latency but
4993 * has drawback of device moving into critical state where the device is
4994 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4995 * host is idle so that BKOPS are managed effectively without any negative
4996 * impacts.
4997 *
4998 * Returns zero on success, non-zero on failure.
4999 */
5000static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5001{
5002 int err = 0;
5003
5004 if (!hba->auto_bkops_enabled)
5005 goto out;
5006
5007 /*
5008 * If host assisted BKOPs is to be enabled, make sure
5009 * urgent bkops exception is allowed.
5010 */
5011 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5012 if (err) {
5013 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5014 __func__, err);
5015 goto out;
5016 }
5017
dc3c8d3a 5018 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 5019 QUERY_FLAG_IDN_BKOPS_EN, NULL);
5020 if (err) {
5021 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5022 __func__, err);
5023 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5024 goto out;
5025 }
5026
5027 hba->auto_bkops_enabled = false;
7ff5ab47 5028 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
24366c2a 5029 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5030out:
5031 return err;
5032}
5033
5034/**
4e768e76 5035 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5036 * @hba: per adapter instance
5037 *
5038 * After a device reset the device may toggle the BKOPS_EN flag
5039 * to default value. The s/w tracking variables should be updated
4e768e76
SJ		 5040 * as well. This function would change the auto-bkops state based on
5041 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5042 */
4e768e76 5043static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5044{
4e768e76
SJ		 5045 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5046 hba->auto_bkops_enabled = false;
5047 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5048 ufshcd_enable_auto_bkops(hba);
5049 } else {
5050 hba->auto_bkops_enabled = true;
5051 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5052 ufshcd_disable_auto_bkops(hba);
5053 }
24366c2a 5054 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5055}
5056
5057static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5058{
5e86ae44 5059 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5060 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5061}
5062
5063/**
57d104c1 5064 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5065 * @hba: per-adapter instance
57d104c1 5066 * @status: bkops_status value
66ec6d59 5067 *
57d104c1
SJ		 5068 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5069 * flag in the device to permit background operations if the device
5070 * bkops_status is greater than or equal to "status" argument passed to
5071 * this function, disable otherwise.
5072 *
5073 * Returns 0 for success, non-zero in case of failure.
5074 *
5075 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5076 * to know whether auto bkops is enabled or disabled after this function
5077 * returns control to it.
66ec6d59 5078 */
57d104c1
SJ		 5079static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5080 enum bkops_status status)
66ec6d59
SRT		 5081{
5082 int err;
57d104c1 5083 u32 curr_status = 0;
66ec6d59 5084
57d104c1 5085 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5086 if (err) {
5087 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5088 __func__, err);
5089 goto out;
57d104c1
SJ		 5090 } else if (curr_status > BKOPS_STATUS_MAX) {
5091 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5092 __func__, curr_status);
5093 err = -EINVAL;
5094 goto out;
66ec6d59
SRT		 5095 }
5096
57d104c1 5097 if (curr_status >= status)
66ec6d59 5098 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5099 else
5100 err = ufshcd_disable_auto_bkops(hba);
24366c2a 5101 hba->urgent_bkops_lvl = curr_status;
66ec6d59
SRT		 5102out:
5103 return err;
5104}
5105
57d104c1
SJ		 5106/**
5107 * ufshcd_urgent_bkops - handle urgent bkops exception event
5108 * @hba: per-adapter instance
5109 *
5110 * Enable fBackgroundOpsEn flag in the device to permit background
5111 * operations.
5112 *
5113 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5114 * and negative error value for any other failure.
5115 */
5116static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5117{
afdfff59 5118 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5119}
5120
66ec6d59
SRT		 5121static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5122{
5e86ae44 5123 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5124 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5125}
5126
afdfff59
YG		 5127static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5128{
5129 int err;
5130 u32 curr_status = 0;
5131
5132 if (hba->is_urgent_bkops_lvl_checked)
5133 goto enable_auto_bkops;
5134
5135 err = ufshcd_get_bkops_status(hba, &curr_status);
5136 if (err) {
5137 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5138 __func__, err);
5139 goto out;
5140 }
5141
5142 /*
5143 * We are seeing that some devices are raising the urgent bkops
5144 * exception events even when BKOPS status doesn't indicate performace
5145 * impacted or critical. Handle these device by determining their urgent
5146 * bkops status at runtime.
5147 */
5148 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5149 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5150 __func__, curr_status);
5151 /* update the current status as the urgent bkops level */
5152 hba->urgent_bkops_lvl = curr_status;
5153 hba->is_urgent_bkops_lvl_checked = true;
5154 }
5155
5156enable_auto_bkops:
5157 err = ufshcd_enable_auto_bkops(hba);
5158out:
5159 if (err < 0)
5160 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5161 __func__, err);
5162}
5163
66ec6d59
SRT		 5164/**
5165 * ufshcd_exception_event_handler - handle exceptions raised by device
5166 * @work: pointer to work data
5167 *
5168 * Read bExceptionEventStatus attribute from the device and handle the
5169 * exception event accordingly.
5170 */
5171static void ufshcd_exception_event_handler(struct work_struct *work)
5172{
5173 struct ufs_hba *hba;
5174 int err;
5175 u32 status = 0;
5176 hba = container_of(work, struct ufs_hba, eeh_work);
5177
62694735 5178 pm_runtime_get_sync(hba->dev);
03e1d28e 5179 ufshcd_scsi_block_requests(hba);
66ec6d59
SRT		 5180 err = ufshcd_get_ee_status(hba, &status);
5181 if (err) {
5182 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5183 __func__, err);
5184 goto out;
5185 }
5186
5187 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5188
5189 if (status & MASK_EE_URGENT_BKOPS)
5190 ufshcd_bkops_exception_event_handler(hba);
5191
66ec6d59 5192out:
03e1d28e 5193 ufshcd_scsi_unblock_requests(hba);
62694735 5194 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 5195 return;
5196}
5197
9a47ec7c
YG		 5198/* Complete requests that have door-bell cleared */
5199static void ufshcd_complete_requests(struct ufs_hba *hba)
5200{
5201 ufshcd_transfer_req_compl(hba);
5202 ufshcd_tmc_handler(hba);
5203}
5204
583fa62d
YG		 5205/**
5206 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5207 * to recover from the DL NAC errors or not.
5208 * @hba: per-adapter instance
5209 *
5210 * Returns true if error handling is required, false otherwise
5211 */
5212static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5213{
5214 unsigned long flags;
5215 bool err_handling = true;
5216
5217 spin_lock_irqsave(hba->host->host_lock, flags);
5218 /*
5219 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5220 * device fatal error and/or DL NAC & REPLAY timeout errors.
5221 */
5222 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5223 goto out;
5224
5225 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5226 ((hba->saved_err & UIC_ERROR) &&
5227 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5228 goto out;
5229
5230 if ((hba->saved_err & UIC_ERROR) &&
5231 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5232 int err;
5233 /*
5234 * wait for 50ms to see if we can get any other errors or not.
5235 */
5236 spin_unlock_irqrestore(hba->host->host_lock, flags);
5237 msleep(50);
5238 spin_lock_irqsave(hba->host->host_lock, flags);
5239
5240 /*
5241 * now check if we have got any other severe errors other than
5242 * DL NAC error?
5243 */
5244 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5245 ((hba->saved_err & UIC_ERROR) &&
5246 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5247 goto out;
5248
5249 /*
5250 * As DL NAC is the only error received so far, send out NOP
5251 * command to confirm if link is still active or not.
5252 * - If we don't get any response then do error recovery.
5253 * - If we get response then clear the DL NAC error bit.
5254 */
5255
5256 spin_unlock_irqrestore(hba->host->host_lock, flags);
5257 err = ufshcd_verify_dev_init(hba);
5258 spin_lock_irqsave(hba->host->host_lock, flags);
5259
5260 if (err)
5261 goto out;
5262
5263 /* Link seems to be alive hence ignore the DL NAC errors */
5264 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5265 hba->saved_err &= ~UIC_ERROR;
5266 /* clear NAC error */
5267 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5268 if (!hba->saved_uic_err) {
5269 err_handling = false;
5270 goto out;
5271 }
5272 }
5273out:
5274 spin_unlock_irqrestore(hba->host->host_lock, flags);
5275 return err_handling;
5276}
5277
7a3e97b0 5278/**
e8e7f271
SRT		 5279 * ufshcd_err_handler - handle UFS errors that require s/w attention
5280 * @work: pointer to work structure
7a3e97b0 5281 */
e8e7f271 5282static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5283{
5284 struct ufs_hba *hba;
e8e7f271
SRT		 5285 unsigned long flags;
5286 u32 err_xfer = 0;
5287 u32 err_tm = 0;
5288 int err = 0;
5289 int tag;
9a47ec7c 5290 bool needs_reset = false;
e8e7f271
SRT		 5291
5292 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5293
62694735 5294 pm_runtime_get_sync(hba->dev);
1ab27c9c 5295 ufshcd_hold(hba, false);
e8e7f271
SRT		 5296
5297 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5298 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5299 goto out;
e8e7f271
SRT		 5300
5301 hba->ufshcd_state = UFSHCD_STATE_RESET;
5302 ufshcd_set_eh_in_progress(hba);
5303
5304 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5305 ufshcd_complete_requests(hba);
583fa62d
YG		 5306
5307 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5308 bool ret;
5309
5310 spin_unlock_irqrestore(hba->host->host_lock, flags);
5311 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5312 ret = ufshcd_quirk_dl_nac_errors(hba);
5313 spin_lock_irqsave(hba->host->host_lock, flags);
5314 if (!ret)
5315 goto skip_err_handling;
5316 }
9a47ec7c 5317 if ((hba->saved_err & INT_FATAL_ERRORS) ||
82174440 5318 (hba->saved_err & UFSHCD_UIC_HIBERN8_MASK) ||
9a47ec7c
YG		 5319 ((hba->saved_err & UIC_ERROR) &&
5320 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5321 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5322 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5323 needs_reset = true;
e8e7f271 5324
9a47ec7c
YG		 5325 /*
5326 * if host reset is required then skip clearing the pending
2df74b69
CG		 5327 * transfers forcefully because they will get cleared during
5328 * host reset and restore
9a47ec7c
YG		 5329 */
5330 if (needs_reset)
5331 goto skip_pending_xfer_clear;
5332
5333 /* release lock as clear command might sleep */
5334 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5335 /* Clear pending transfer requests */
9a47ec7c
YG		 5336 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5337 if (ufshcd_clear_cmd(hba, tag)) {
5338 err_xfer = true;
5339 goto lock_skip_pending_xfer_clear;
5340 }
5341 }
e8e7f271
SRT		 5342
5343 /* Clear pending task management requests */
9a47ec7c
YG		 5344 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5345 if (ufshcd_clear_tm_cmd(hba, tag)) {
5346 err_tm = true;
5347 goto lock_skip_pending_xfer_clear;
5348 }
5349 }
e8e7f271 5350
9a47ec7c 5351lock_skip_pending_xfer_clear:
e8e7f271 5352 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5353
9a47ec7c
YG		 5354 /* Complete the requests that are cleared by s/w */
5355 ufshcd_complete_requests(hba);
5356
5357 if (err_xfer || err_tm)
5358 needs_reset = true;
5359
5360skip_pending_xfer_clear:
e8e7f271 5361 /* Fatal errors need reset */
9a47ec7c
YG		 5362 if (needs_reset) {
5363 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5364
5365 /*
5366 * ufshcd_reset_and_restore() does the link reinitialization
5367 * which will need atleast one empty doorbell slot to send the
5368 * device management commands (NOP and query commands).
5369 * If there is no slot empty at this moment then free up last
5370 * slot forcefully.
5371 */
5372 if (hba->outstanding_reqs == max_doorbells)
5373 __ufshcd_transfer_req_compl(hba,
5374 (1UL << (hba->nutrs - 1)));
5375
5376 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5377 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5378 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5379 if (err) {
5380 dev_err(hba->dev, "%s: reset and restore failed\n",
5381 __func__);
5382 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5383 }
5384 /*
5385 * Inform scsi mid-layer that we did reset and allow to handle
5386 * Unit Attention properly.
5387 */
5388 scsi_report_bus_reset(hba->host, 0);
5389 hba->saved_err = 0;
5390 hba->saved_uic_err = 0;
5391 }
9a47ec7c 5392
583fa62d 5393skip_err_handling:
9a47ec7c
YG		 5394 if (!needs_reset) {
5395 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5396 if (hba->saved_err || hba->saved_uic_err)
5397 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5398 __func__, hba->saved_err, hba->saved_uic_err);
5399 }
5400
e8e7f271
SRT		 5401 ufshcd_clear_eh_in_progress(hba);
5402
5403out:
9a47ec7c 5404 spin_unlock_irqrestore(hba->host->host_lock, flags);
38135535 5405 ufshcd_scsi_unblock_requests(hba);
1ab27c9c 5406 ufshcd_release(hba);
62694735 5407 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5408}
5409
5410/**
e8e7f271
SRT		 5411 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5412 * @hba: per-adapter instance
9333d775
VG		 5413 *
5414 * Returns
5415 * IRQ_HANDLED - If interrupt is valid
5416 * IRQ_NONE - If invalid interrupt
7a3e97b0 5417 */
9333d775 5418static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5419{
5420 u32 reg;
9333d775 5421 irqreturn_t retval = IRQ_NONE;
7a3e97b0 5422
fb7b45f0
DR		 5423 /* PHY layer lane error */
5424 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5425 /* Ignore LINERESET indication, as this is not an error */
5426 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
9333d775 5427 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5428 /*
5429 * To know whether this error is fatal or not, DB timeout
5430 * must be checked but this error is handled separately.
5431 */
5432 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
48d5b973 5433 ufshcd_update_reg_hist(&hba->ufs_stats.pa_err, reg);
9333d775 5434 retval |= IRQ_HANDLED;
ff8e20c6 5435 }
fb7b45f0 5436
e8e7f271
SRT		 5437 /* PA_INIT_ERROR is fatal and needs UIC reset */
5438 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
9333d775
VG		 5439 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
5440 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
48d5b973 5441 ufshcd_update_reg_hist(&hba->ufs_stats.dl_err, reg);
ff8e20c6 5442
9333d775
VG		 5443 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5444 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
5445 else if (hba->dev_quirks &
5446 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5447 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5448 hba->uic_error |=
5449 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5450 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5451 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5452 }
5453 retval |= IRQ_HANDLED;
583fa62d 5454 }
e8e7f271
SRT		 5455
5456 /* UIC NL/TL/DME errors needs software retry */
5457 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
9333d775
VG		 5458 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
5459 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
48d5b973 5460 ufshcd_update_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5461 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
9333d775 5462 retval |= IRQ_HANDLED;
ff8e20c6 5463 }
e8e7f271
SRT		 5464
5465 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
9333d775
VG		 5466 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
5467 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
48d5b973 5468 ufshcd_update_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5469 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
9333d775 5470 retval |= IRQ_HANDLED;
ff8e20c6 5471 }
e8e7f271
SRT		 5472
5473 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
9333d775
VG		 5474 if ((reg & UIC_DME_ERROR) &&
5475 (reg & UIC_DME_ERROR_CODE_MASK)) {
48d5b973 5476 ufshcd_update_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5477 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
9333d775 5478 retval |= IRQ_HANDLED;
ff8e20c6 5479 }
e8e7f271
SRT		 5480
5481 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5482 __func__, hba->uic_error);
9333d775 5483 return retval;
e8e7f271
SRT		 5484}
5485
82174440
SC		 5486static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5487 u32 intr_mask)
5488{
5489 if (!ufshcd_is_auto_hibern8_supported(hba))
5490 return false;
5491
5492 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5493 return false;
5494
5495 if (hba->active_uic_cmd &&
5496 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5497 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5498 return false;
5499
5500 return true;
5501}
5502
e8e7f271
SRT		 5503/**
5504 * ufshcd_check_errors - Check for errors that need s/w attention
5505 * @hba: per-adapter instance
9333d775
VG		 5506 *
5507 * Returns
5508 * IRQ_HANDLED - If interrupt is valid
5509 * IRQ_NONE - If invalid interrupt
e8e7f271 5510 */
9333d775 5511static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba)
e8e7f271
SRT		 5512{
5513 bool queue_eh_work = false;
9333d775 5514 irqreturn_t retval = IRQ_NONE;
e8e7f271 5515
d3c615bf
SC		 5516 if (hba->errors & INT_FATAL_ERRORS) {
5517 ufshcd_update_reg_hist(&hba->ufs_stats.fatal_err, hba->errors);
e8e7f271 5518 queue_eh_work = true;
d3c615bf 5519 }
7a3e97b0
SY		 5520
5521 if (hba->errors & UIC_ERROR) {
e8e7f271 5522 hba->uic_error = 0;
9333d775 5523 retval = ufshcd_update_uic_error(hba);
e8e7f271
SRT		 5524 if (hba->uic_error)
5525 queue_eh_work = true;
7a3e97b0 5526 }
e8e7f271 5527
82174440
SC		 5528 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
5529 dev_err(hba->dev,
5530 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
5531 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
5532 "Enter" : "Exit",
5533 hba->errors, ufshcd_get_upmcrs(hba));
d3c615bf
SC		 5534 ufshcd_update_reg_hist(&hba->ufs_stats.auto_hibern8_err,
5535 hba->errors);
82174440
SC		 5536 queue_eh_work = true;
5537 }
5538
e8e7f271 5539 if (queue_eh_work) {
9a47ec7c
YG		 5540 /*
5541 * update the transfer error masks to sticky bits, let's do this
5542 * irrespective of current ufshcd_state.
5543 */
5544 hba->saved_err |= hba->errors;
5545 hba->saved_uic_err |= hba->uic_error;
5546
e8e7f271
SRT		 5547 /* handle fatal errors only when link is functional */
5548 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5549 /* block commands from scsi mid-layer */
38135535 5550 ufshcd_scsi_block_requests(hba);
e8e7f271 5551
141f8165 5552 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5553
5554 /* dump controller state before resetting */
5555 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5556 bool pr_prdt = !!(hba->saved_err &
5557 SYSTEM_BUS_FATAL_ERROR);
5558
5559 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5560 __func__, hba->saved_err,
5561 hba->saved_uic_err);
5562
5563 ufshcd_print_host_regs(hba);
5564 ufshcd_print_pwr_info(hba);
5565 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5566 ufshcd_print_trs(hba, hba->outstanding_reqs,
5567 pr_prdt);
5568 }
e8e7f271
SRT		 5569 schedule_work(&hba->eh_work);
5570 }
9333d775 5571 retval |= IRQ_HANDLED;
3441da7d 5572 }
e8e7f271
SRT		 5573 /*
5574 * if (!queue_eh_work) -
5575 * Other errors are either non-fatal where host recovers
5576 * itself without s/w intervention or errors that will be
5577 * handled by the SCSI core layer.
5578 */
9333d775 5579 return retval;
7a3e97b0
SY		 5580}
5581
69a6c269
BVA		 5582struct ctm_info {
5583 struct ufs_hba *hba;
5584 unsigned long pending;
5585 unsigned int ncpl;
5586};
5587
5588static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
5589{
5590 struct ctm_info *const ci = priv;
5591 struct completion *c;
5592
5593 WARN_ON_ONCE(reserved);
5594 if (test_bit(req->tag, &ci->pending))
5595 return true;
5596 ci->ncpl++;
5597 c = req->end_io_data;
5598 if (c)
5599 complete(c);
5600 return true;
5601}
5602
7a3e97b0
SY		 5603/**
5604 * ufshcd_tmc_handler - handle task management function completion
5605 * @hba: per adapter instance
9333d775
VG		 5606 *
5607 * Returns
5608 * IRQ_HANDLED - If interrupt is valid
5609 * IRQ_NONE - If invalid interrupt
7a3e97b0 5610 */
9333d775 5611static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7a3e97b0 5612{
69a6c269
BVA		 5613 struct request_queue *q = hba->tmf_queue;
5614 struct ctm_info ci = {
5615 .hba = hba,
5616 .pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL),
5617 };
7a3e97b0 5618
69a6c269
BVA		 5619 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
5620 return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
7a3e97b0
SY		 5621}
5622
5623/**
5624 * ufshcd_sl_intr - Interrupt service routine
5625 * @hba: per adapter instance
5626 * @intr_status: contains interrupts generated by the controller
9333d775
VG		 5627 *
5628 * Returns
5629 * IRQ_HANDLED - If interrupt is valid
5630 * IRQ_NONE - If invalid interrupt
7a3e97b0 5631 */
9333d775 5632static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7a3e97b0 5633{
9333d775
VG		 5634 irqreturn_t retval = IRQ_NONE;
5635
7a3e97b0 5636 hba->errors = UFSHCD_ERROR_MASK & intr_status;
82174440
SC		 5637
5638 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5639 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5640
7a3e97b0 5641 if (hba->errors)
9333d775 5642 retval |= ufshcd_check_errors(hba);
7a3e97b0 5643
53b3d9c3 5644 if (intr_status & UFSHCD_UIC_MASK)
9333d775 5645 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5646
5647 if (intr_status & UTP_TASK_REQ_COMPL)
9333d775 5648 retval |= ufshcd_tmc_handler(hba);
7a3e97b0
SY		 5649
5650 if (intr_status & UTP_TRANSFER_REQ_COMPL)
9333d775
VG		 5651 retval |= ufshcd_transfer_req_compl(hba);
5652
5653 return retval;
7a3e97b0
SY		 5654}
5655
5656/**
5657 * ufshcd_intr - Main interrupt service routine
5658 * @irq: irq number
5659 * @__hba: pointer to adapter instance
5660 *
9333d775
VG		 5661 * Returns
5662 * IRQ_HANDLED - If interrupt is valid
5663 * IRQ_NONE - If invalid interrupt
7a3e97b0
SY		 5664 */
5665static irqreturn_t ufshcd_intr(int irq, void *__hba)
5666{
d75f7fe4 5667 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5668 irqreturn_t retval = IRQ_NONE;
5669 struct ufs_hba *hba = __hba;
7f6ba4f1 5670 int retries = hba->nutrs;
7a3e97b0
SY		 5671
5672 spin_lock(hba->host->host_lock);
b873a275 5673 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0 5674
7f6ba4f1
VG		 5675 /*
5676 * There could be max of hba->nutrs reqs in flight and in worst case
5677 * if the reqs get finished 1 by 1 after the interrupt status is
5678 * read, make sure we handle them by checking the interrupt status
5679 * again in a loop until we process all of the reqs before returning.
5680 */
5681 do {
5682 enabled_intr_status =
5683 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5684 if (intr_status)
5685 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
9333d775
VG		 5686 if (enabled_intr_status)
5687 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7f6ba4f1
VG		 5688
5689 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5690 } while (intr_status && --retries);
d75f7fe4 5691
9333d775
VG		 5692 if (retval == IRQ_NONE) {
5693 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n",
5694 __func__, intr_status);
5695 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
5696 }
5697
7a3e97b0
SY		 5698 spin_unlock(hba->host->host_lock);
5699 return retval;
5700}
5701
e2933132
SRT		 5702static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5703{
5704 int err = 0;
5705 u32 mask = 1 << tag;
5706 unsigned long flags;
5707
5708 if (!test_bit(tag, &hba->outstanding_tasks))
5709 goto out;
5710
5711 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 5712 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5713 spin_unlock_irqrestore(hba->host->host_lock, flags);
5714
5715 /* poll for max. 1 sec to clear door bell register by h/w */
5716 err = ufshcd_wait_for_register(hba,
5717 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5718 mask, 0, 1000, 1000, true);
e2933132
SRT		 5719out:
5720 return err;
5721}
5722
c6049cd9
CH		 5723static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
5724 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 5725{
69a6c269 5726 struct request_queue *q = hba->tmf_queue;
c6049cd9 5727 struct Scsi_Host *host = hba->host;
69a6c269
BVA		 5728 DECLARE_COMPLETION_ONSTACK(wait);
5729 struct request *req;
7a3e97b0 5730 unsigned long flags;
c6049cd9 5731 int free_slot, task_tag, err;
7a3e97b0 5732
e2933132
SRT		 5733 /*
5734 * Get free slot, sleep if slots are unavailable.
5735 * Even though we use wait_event() which sleeps indefinitely,
5736 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5737 */
69a6c269
BVA		 5738 req = blk_get_request(q, REQ_OP_DRV_OUT, BLK_MQ_REQ_RESERVED);
5739 req->end_io_data = &wait;
5740 free_slot = req->tag;
5741 WARN_ON_ONCE(free_slot < 0 || free_slot >= hba->nutmrs);
1ab27c9c 5742 ufshcd_hold(hba, false);
7a3e97b0 5743
e2933132 5744 spin_lock_irqsave(host->host_lock, flags);
e2933132 5745 task_tag = hba->nutrs + free_slot;
7a3e97b0 5746
c6049cd9
CH		 5747 treq->req_header.dword_0 |= cpu_to_be32(task_tag);
5748
5749 memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
d2877be4
KK		 5750 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5751
7a3e97b0
SY		 5752 /* send command to the controller */
5753 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5754
5755 /* Make sure descriptors are ready before ringing the task doorbell */
5756 wmb();
5757
b873a275 5758 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5759 /* Make sure that doorbell is committed immediately */
5760 wmb();
7a3e97b0
SY		 5761
5762 spin_unlock_irqrestore(host->host_lock, flags);
5763
6667e6d9
OS		 5764 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5765
7a3e97b0 5766 /* wait until the task management command is completed */
69a6c269 5767 err = wait_for_completion_io_timeout(&wait,
e2933132 5768 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5769 if (!err) {
69a6c269
BVA		 5770 /*
5771 * Make sure that ufshcd_compl_tm() does not trigger a
5772 * use-after-free.
5773 */
5774 req->end_io_data = NULL;
6667e6d9 5775 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
e2933132
SRT		 5776 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5777 __func__, tm_function);
5778 if (ufshcd_clear_tm_cmd(hba, free_slot))
5779 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5780 __func__, free_slot);
5781 err = -ETIMEDOUT;
5782 } else {
c6049cd9
CH		 5783 err = 0;
5784 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
5785
6667e6d9 5786 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
7a3e97b0 5787 }
e2933132 5788
b557217c
SC		 5789 spin_lock_irqsave(hba->host->host_lock, flags);
5790 __clear_bit(free_slot, &hba->outstanding_tasks);
5791 spin_unlock_irqrestore(hba->host->host_lock, flags);
5792
69a6c269 5793 blk_put_request(req);
e2933132 5794
1ab27c9c 5795 ufshcd_release(hba);
7a3e97b0
SY		 5796 return err;
5797}
5798
c6049cd9
CH		 5799/**
5800 * ufshcd_issue_tm_cmd - issues task management commands to controller
5801 * @hba: per adapter instance
5802 * @lun_id: LUN ID to which TM command is sent
5803 * @task_id: task ID to which the TM command is applicable
5804 * @tm_function: task management function opcode
5805 * @tm_response: task management service response return value
5806 *
5807 * Returns non-zero value on error, zero on success.
5808 */
5809static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5810 u8 tm_function, u8 *tm_response)
5811{
5812 struct utp_task_req_desc treq = { { 0 }, };
5813 int ocs_value, err;
5814
5815 /* Configure task request descriptor */
5816 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5817 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5818
5819 /* Configure task request UPIU */
5820 treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
5821 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
5822 treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
5823
5824 /*
5825 * The host shall provide the same value for LUN field in the basic
5826 * header and for Input Parameter.
5827 */
5828 treq.input_param1 = cpu_to_be32(lun_id);
5829 treq.input_param2 = cpu_to_be32(task_id);
5830
5831 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
5832 if (err == -ETIMEDOUT)
5833 return err;
5834
5835 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5836 if (ocs_value != OCS_SUCCESS)
5837 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
5838 __func__, ocs_value);
5839 else if (tm_response)
5840 *tm_response = be32_to_cpu(treq.output_param1) &
5841 MASK_TM_SERVICE_RESP;
5842 return err;
5843}
5844
5e0a86ee
AA		 5845/**
5846 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
5847 * @hba: per-adapter instance
5848 * @req_upiu: upiu request
5849 * @rsp_upiu: upiu reply
5e0a86ee
AA		 5850 * @desc_buff: pointer to descriptor buffer, NULL if NA
5851 * @buff_len: descriptor size, 0 if NA
d0e9760d 5852 * @cmd_type: specifies the type (NOP, Query...)
5e0a86ee
AA		 5853 * @desc_op: descriptor operation
5854 *
5855 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
5856 * Therefore, it "rides" the device management infrastructure: uses its tag and
5857 * tasks work queues.
5858 *
5859 * Since there is only one available tag for device management commands,
5860 * the caller is expected to hold the hba->dev_cmd.lock mutex.
5861 */
5862static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
5863 struct utp_upiu_req *req_upiu,
5864 struct utp_upiu_req *rsp_upiu,
5865 u8 *desc_buff, int *buff_len,
7f674c38 5866 enum dev_cmd_type cmd_type,
5e0a86ee
AA		 5867 enum query_opcode desc_op)
5868{
7252a360
BVA		 5869 struct request_queue *q = hba->cmd_queue;
5870 struct request *req;
5e0a86ee
AA		 5871 struct ufshcd_lrb *lrbp;
5872 int err = 0;
5873 int tag;
5874 struct completion wait;
5875 unsigned long flags;
5876 u32 upiu_flags;
5877
5878 down_read(&hba->clk_scaling_lock);
5879
7252a360 5880 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 5881 if (IS_ERR(req)) {
5882 err = PTR_ERR(req);
5883 goto out_unlock;
5884 }
7252a360
BVA		 5885 tag = req->tag;
5886 WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
5e0a86ee
AA		 5887
5888 init_completion(&wait);
5889 lrbp = &hba->lrb[tag];
5890 WARN_ON(lrbp->cmd);
5891
5892 lrbp->cmd = NULL;
5893 lrbp->sense_bufflen = 0;
5894 lrbp->sense_buffer = NULL;
5895 lrbp->task_tag = tag;
5896 lrbp->lun = 0;
5897 lrbp->intr_cmd = true;
5898 hba->dev_cmd.type = cmd_type;
5899
5900 switch (hba->ufs_version) {
5901 case UFSHCI_VERSION_10:
5902 case UFSHCI_VERSION_11:
5903 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
5904 break;
5905 default:
5906 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5907 break;
5908 }
5909
5910 /* update the task tag in the request upiu */
5911 req_upiu->header.dword_0 |= cpu_to_be32(tag);
5912
5913 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
5914
5915 /* just copy the upiu request as it is */
5916 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
5917 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
5918 /* The Data Segment Area is optional depending upon the query
5919 * function value. for WRITE DESCRIPTOR, the data segment
5920 * follows right after the tsf.
5921 */
5922 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
5923 *buff_len = 0;
5924 }
5925
5926 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5927
5928 hba->dev_cmd.complete = &wait;
5929
5930 /* Make sure descriptors are ready before ringing the doorbell */
5931 wmb();
5932 spin_lock_irqsave(hba->host->host_lock, flags);
5933 ufshcd_send_command(hba, tag);
5934 spin_unlock_irqrestore(hba->host->host_lock, flags);
5935
5936 /*
5937 * ignore the returning value here - ufshcd_check_query_response is
5938 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
5939 * read the response directly ignoring all errors.
5940 */
5941 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
5942
5943 /* just copy the upiu response as it is */
5944 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
4bbbe242
AA		 5945 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
5946 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
5947 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
5948 MASK_QUERY_DATA_SEG_LEN;
5949
5950 if (*buff_len >= resp_len) {
5951 memcpy(desc_buff, descp, resp_len);
5952 *buff_len = resp_len;
5953 } else {
3d4881d1
BH		 5954 dev_warn(hba->dev,
5955 "%s: rsp size %d is bigger than buffer size %d",
5956 __func__, resp_len, *buff_len);
4bbbe242
AA		 5957 *buff_len = 0;
5958 err = -EINVAL;
5959 }
5960 }
5e0a86ee 5961
7252a360 5962 blk_put_request(req);
bb14dd15 5963out_unlock:
5e0a86ee
AA		 5964 up_read(&hba->clk_scaling_lock);
5965 return err;
5966}
5967
5968/**
5969 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
5970 * @hba: per-adapter instance
5971 * @req_upiu: upiu request
5972 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
5973 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
5974 * @desc_buff: pointer to descriptor buffer, NULL if NA
5975 * @buff_len: descriptor size, 0 if NA
5976 * @desc_op: descriptor operation
5977 *
5978 * Supports UTP Transfer requests (nop and query), and UTP Task
5979 * Management requests.
5980 * It is up to the caller to fill the upiu conent properly, as it will
5981 * be copied without any further input validations.
5982 */
5983int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
5984 struct utp_upiu_req *req_upiu,
5985 struct utp_upiu_req *rsp_upiu,
5986 int msgcode,
5987 u8 *desc_buff, int *buff_len,
5988 enum query_opcode desc_op)
5989{
5990 int err;
7f674c38 5991 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
5e0a86ee
AA		 5992 struct utp_task_req_desc treq = { { 0 }, };
5993 int ocs_value;
5994 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
5995
5e0a86ee
AA		 5996 switch (msgcode) {
5997 case UPIU_TRANSACTION_NOP_OUT:
5998 cmd_type = DEV_CMD_TYPE_NOP;
5999 /* fall through */
6000 case UPIU_TRANSACTION_QUERY_REQ:
6001 ufshcd_hold(hba, false);
6002 mutex_lock(&hba->dev_cmd.lock);
6003 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6004 desc_buff, buff_len,
6005 cmd_type, desc_op);
6006 mutex_unlock(&hba->dev_cmd.lock);
6007 ufshcd_release(hba);
6008
6009 break;
6010 case UPIU_TRANSACTION_TASK_REQ:
6011 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6012 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6013
6014 memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
6015
6016 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6017 if (err == -ETIMEDOUT)
6018 break;
6019
6020 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6021 if (ocs_value != OCS_SUCCESS) {
6022 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6023 ocs_value);
6024 break;
6025 }
6026
6027 memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
6028
6029 break;
6030 default:
6031 err = -EINVAL;
6032
6033 break;
6034 }
6035
5e0a86ee
AA		 6036 return err;
6037}
6038
7a3e97b0 6039/**
3441da7d
SRT		 6040 * ufshcd_eh_device_reset_handler - device reset handler registered to
6041 * scsi layer.
7a3e97b0
SY		 6042 * @cmd: SCSI command pointer
6043 *
6044 * Returns SUCCESS/FAILED
6045 */
3441da7d 6046static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 6047{
6048 struct Scsi_Host *host;
6049 struct ufs_hba *hba;
6050 unsigned int tag;
6051 u32 pos;
6052 int err;
e2933132
SRT		 6053 u8 resp = 0xF;
6054 struct ufshcd_lrb *lrbp;
3441da7d 6055 unsigned long flags;
7a3e97b0
SY		 6056
6057 host = cmd->device->host;
6058 hba = shost_priv(host);
6059 tag = cmd->request->tag;
6060
e2933132
SRT		 6061 lrbp = &hba->lrb[tag];
6062 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
6063 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 6064 if (!err)
6065 err = resp;
7a3e97b0 6066 goto out;
e2933132 6067 }
7a3e97b0 6068
3441da7d
SRT		 6069 /* clear the commands that were pending for corresponding LUN */
6070 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6071 if (hba->lrb[pos].lun == lrbp->lun) {
6072 err = ufshcd_clear_cmd(hba, pos);
6073 if (err)
6074 break;
7a3e97b0 6075 }
3441da7d
SRT		 6076 }
6077 spin_lock_irqsave(host->host_lock, flags);
6078 ufshcd_transfer_req_compl(hba);
6079 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 6080
7a3e97b0 6081out:
7fabb77b 6082 hba->req_abort_count = 0;
8808b4e9 6083 ufshcd_update_reg_hist(&hba->ufs_stats.dev_reset, (u32)err);
3441da7d
SRT		 6084 if (!err) {
6085 err = SUCCESS;
6086 } else {
6087 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6088 err = FAILED;
6089 }
7a3e97b0
SY		 6090 return err;
6091}
6092
e0b299e3
GB		 6093static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6094{
6095 struct ufshcd_lrb *lrbp;
6096 int tag;
6097
6098 for_each_set_bit(tag, &bitmap, hba->nutrs) {
6099 lrbp = &hba->lrb[tag];
6100 lrbp->req_abort_skip = true;
6101 }
6102}
6103
7a3e97b0
SY		 6104/**
6105 * ufshcd_abort - abort a specific command
6106 * @cmd: SCSI command pointer
6107 *
f20810d8
SRT		 6108 * Abort the pending command in device by sending UFS_ABORT_TASK task management
6109 * command, and in host controller by clearing the door-bell register. There can
6110 * be race between controller sending the command to the device while abort is
6111 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6112 * really issued and then try to abort it.
6113 *
7a3e97b0
SY		 6114 * Returns SUCCESS/FAILED
6115 */
6116static int ufshcd_abort(struct scsi_cmnd *cmd)
6117{
6118 struct Scsi_Host *host;
6119 struct ufs_hba *hba;
6120 unsigned long flags;
6121 unsigned int tag;
f20810d8
SRT		 6122 int err = 0;
6123 int poll_cnt;
e2933132
SRT		 6124 u8 resp = 0xF;
6125 struct ufshcd_lrb *lrbp;
e9d501b1 6126 u32 reg;
7a3e97b0
SY		 6127
6128 host = cmd->device->host;
6129 hba = shost_priv(host);
6130 tag = cmd->request->tag;
e7d38257 6131 lrbp = &hba->lrb[tag];
14497328
YG		 6132 if (!ufshcd_valid_tag(hba, tag)) {
6133 dev_err(hba->dev,
6134 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
6135 __func__, tag, cmd, cmd->request);
6136 BUG();
6137 }
7a3e97b0 6138
e7d38257
DR		 6139 /*
6140 * Task abort to the device W-LUN is illegal. When this command
6141 * will fail, due to spec violation, scsi err handling next step
6142 * will be to send LU reset which, again, is a spec violation.
6143 * To avoid these unnecessary/illegal step we skip to the last error
6144 * handling stage: reset and restore.
6145 */
6146 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
6147 return ufshcd_eh_host_reset_handler(cmd);
6148
1ab27c9c 6149 ufshcd_hold(hba, false);
14497328 6150 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 6151 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 6152 if (!(test_bit(tag, &hba->outstanding_reqs))) {
6153 dev_err(hba->dev,
6154 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6155 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 6156 goto out;
14497328 6157 }
7a3e97b0 6158
e9d501b1
DR		 6159 if (!(reg & (1 << tag))) {
6160 dev_err(hba->dev,
6161 "%s: cmd was completed, but without a notifying intr, tag = %d",
6162 __func__, tag);
6163 }
6164
66cc820f
DR		 6165 /* Print Transfer Request of aborted task */
6166 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 6167
7fabb77b
GB		 6168 /*
6169 * Print detailed info about aborted request.
6170 * As more than one request might get aborted at the same time,
6171 * print full information only for the first aborted request in order
6172 * to reduce repeated printouts. For other aborted requests only print
6173 * basic details.
6174 */
6175 scsi_print_command(hba->lrb[tag].cmd);
6176 if (!hba->req_abort_count) {
8808b4e9 6177 ufshcd_update_reg_hist(&hba->ufs_stats.task_abort, 0);
7fabb77b 6178 ufshcd_print_host_regs(hba);
6ba65588 6179 ufshcd_print_host_state(hba);
7fabb77b
GB		 6180 ufshcd_print_pwr_info(hba);
6181 ufshcd_print_trs(hba, 1 << tag, true);
6182 } else {
6183 ufshcd_print_trs(hba, 1 << tag, false);
6184 }
6185 hba->req_abort_count++;
e0b299e3
GB		 6186
6187 /* Skip task abort in case previous aborts failed and report failure */
6188 if (lrbp->req_abort_skip) {
6189 err = -EIO;
6190 goto out;
6191 }
6192
f20810d8
SRT		 6193 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6194 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6195 UFS_QUERY_TASK, &resp);
6196 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6197 /* cmd pending in the device */
ff8e20c6
DR		 6198 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6199 __func__, tag);
f20810d8
SRT		 6200 break;
6201 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 6202 /*
6203 * cmd not pending in the device, check if it is
6204 * in transition.
6205 */
ff8e20c6
DR		 6206 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6207 __func__, tag);
f20810d8
SRT		 6208 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6209 if (reg & (1 << tag)) {
6210 /* sleep for max. 200us to stabilize */
6211 usleep_range(100, 200);
6212 continue;
6213 }
6214 /* command completed already */
ff8e20c6
DR		 6215 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6216 __func__, tag);
f20810d8
SRT		 6217 goto out;
6218 } else {
ff8e20c6
DR		 6219 dev_err(hba->dev,
6220 "%s: no response from device. tag = %d, err %d\n",
6221 __func__, tag, err);
f20810d8
SRT		 6222 if (!err)
6223 err = resp; /* service response error */
6224 goto out;
6225 }
6226 }
6227
6228 if (!poll_cnt) {
6229 err = -EBUSY;
7a3e97b0
SY		 6230 goto out;
6231 }
7a3e97b0 6232
e2933132
SRT		 6233 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6234 UFS_ABORT_TASK, &resp);
6235 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 6236 if (!err) {
f20810d8 6237 err = resp; /* service response error */
ff8e20c6
DR		 6238 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6239 __func__, tag, err);
6240 }
7a3e97b0 6241 goto out;
e2933132 6242 }
7a3e97b0 6243
f20810d8 6244 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 6245 if (err) {
6246 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6247 __func__, tag, err);
f20810d8 6248 goto out;
ff8e20c6 6249 }
f20810d8 6250
7a3e97b0
SY		 6251 scsi_dma_unmap(cmd);
6252
6253 spin_lock_irqsave(host->host_lock, flags);
a48353f6 6254 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 6255 hba->lrb[tag].cmd = NULL;
6256 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9 6257
7a3e97b0 6258out:
f20810d8
SRT		 6259 if (!err) {
6260 err = SUCCESS;
6261 } else {
6262 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 6263 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 6264 err = FAILED;
6265 }
6266
1ab27c9c
ST		 6267 /*
6268 * This ufshcd_release() corresponds to the original scsi cmd that got
6269 * aborted here (as we won't get any IRQ for it).
6270 */
6271 ufshcd_release(hba);
7a3e97b0
SY		 6272 return err;
6273}
6274
3441da7d
SRT		 6275/**
6276 * ufshcd_host_reset_and_restore - reset and restore host controller
6277 * @hba: per-adapter instance
6278 *
6279 * Note that host controller reset may issue DME_RESET to
6280 * local and remote (device) Uni-Pro stack and the attributes
6281 * are reset to default state.
6282 *
6283 * Returns zero on success, non-zero on failure
6284 */
6285static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6286{
6287 int err;
3441da7d
SRT		 6288 unsigned long flags;
6289
2df74b69
CG		 6290 /*
6291 * Stop the host controller and complete the requests
6292 * cleared by h/w
6293 */
3441da7d 6294 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 6295 ufshcd_hba_stop(hba, false);
2df74b69
CG		 6296 hba->silence_err_logs = true;
6297 ufshcd_complete_requests(hba);
6298 hba->silence_err_logs = false;
3441da7d
SRT		 6299 spin_unlock_irqrestore(hba->host->host_lock, flags);
6300
a3cd5ec5
SJ		 6301 /* scale up clocks to max frequency before full reinitialization */
6302 ufshcd_scale_clks(hba, true);
6303
3441da7d
SRT		 6304 err = ufshcd_hba_enable(hba);
6305 if (err)
6306 goto out;
6307
6308 /* Establish the link again and restore the device */
1d337ec2
SRT		 6309 err = ufshcd_probe_hba(hba);
6310
6311 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 6312 err = -EIO;
6313out:
6314 if (err)
6315 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
8808b4e9 6316 ufshcd_update_reg_hist(&hba->ufs_stats.host_reset, (u32)err);
3441da7d
SRT		 6317 return err;
6318}
6319
6320/**
6321 * ufshcd_reset_and_restore - reset and re-initialize host/device
6322 * @hba: per-adapter instance
6323 *
6324 * Reset and recover device, host and re-establish link. This
6325 * is helpful to recover the communication in fatal error conditions.
6326 *
6327 * Returns zero on success, non-zero on failure
6328 */
6329static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6330{
6331 int err = 0;
1d337ec2 6332 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 6333
1d337ec2 6334 do {
d8d9f793
BA		 6335 /* Reset the attached device */
6336 ufshcd_vops_device_reset(hba);
6337
1d337ec2
SRT		 6338 err = ufshcd_host_reset_and_restore(hba);
6339 } while (err && --retries);
3441da7d 6340
3441da7d
SRT		 6341 return err;
6342}
6343
6344/**
6345 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 6346 * @cmd: SCSI command pointer
3441da7d
SRT		 6347 *
6348 * Returns SUCCESS/FAILED
6349 */
6350static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6351{
6352 int err;
6353 unsigned long flags;
6354 struct ufs_hba *hba;
6355
6356 hba = shost_priv(cmd->device->host);
6357
1ab27c9c 6358 ufshcd_hold(hba, false);
3441da7d
SRT		 6359 /*
6360 * Check if there is any race with fatal error handling.
6361 * If so, wait for it to complete. Even though fatal error
6362 * handling does reset and restore in some cases, don't assume
6363 * anything out of it. We are just avoiding race here.
6364 */
6365 do {
6366 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6367 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6368 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6369 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6370 break;
6371 spin_unlock_irqrestore(hba->host->host_lock, flags);
6372 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6373 flush_work(&hba->eh_work);
3441da7d
SRT		 6374 } while (1);
6375
6376 hba->ufshcd_state = UFSHCD_STATE_RESET;
6377 ufshcd_set_eh_in_progress(hba);
6378 spin_unlock_irqrestore(hba->host->host_lock, flags);
6379
6380 err = ufshcd_reset_and_restore(hba);
6381
6382 spin_lock_irqsave(hba->host->host_lock, flags);
6383 if (!err) {
6384 err = SUCCESS;
6385 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6386 } else {
6387 err = FAILED;
6388 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6389 }
6390 ufshcd_clear_eh_in_progress(hba);
6391 spin_unlock_irqrestore(hba->host->host_lock, flags);
6392
1ab27c9c 6393 ufshcd_release(hba);
3441da7d
SRT		 6394 return err;
6395}
6396
3a4bf06d
YG		 6397/**
6398 * ufshcd_get_max_icc_level - calculate the ICC level
6399 * @sup_curr_uA: max. current supported by the regulator
6400 * @start_scan: row at the desc table to start scan from
6401 * @buff: power descriptor buffer
6402 *
6403 * Returns calculated max ICC level for specific regulator
6404 */
6405static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6406{
6407 int i;
6408 int curr_uA;
6409 u16 data;
6410 u16 unit;
6411
6412 for (i = start_scan; i >= 0; i--) {
d79713f9 6413 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6414 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6415 ATTR_ICC_LVL_UNIT_OFFSET;
6416 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6417 switch (unit) {
6418 case UFSHCD_NANO_AMP:
6419 curr_uA = curr_uA / 1000;
6420 break;
6421 case UFSHCD_MILI_AMP:
6422 curr_uA = curr_uA * 1000;
6423 break;
6424 case UFSHCD_AMP:
6425 curr_uA = curr_uA * 1000 * 1000;
6426 break;
6427 case UFSHCD_MICRO_AMP:
6428 default:
6429 break;
6430 }
6431 if (sup_curr_uA >= curr_uA)
6432 break;
6433 }
6434 if (i < 0) {
6435 i = 0;
6436 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6437 }
6438
6439 return (u32)i;
6440}
6441
6442/**
6443 * ufshcd_calc_icc_level - calculate the max ICC level
6444 * In case regulators are not initialized we'll return 0
6445 * @hba: per-adapter instance
6446 * @desc_buf: power descriptor buffer to extract ICC levels from.
6447 * @len: length of desc_buff
6448 *
6449 * Returns calculated ICC level
6450 */
6451static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6452 u8 *desc_buf, int len)
6453{
6454 u32 icc_level = 0;
6455
6456 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6457 !hba->vreg_info.vccq2) {
6458 dev_err(hba->dev,
6459 "%s: Regulator capability was not set, actvIccLevel=%d",
6460 __func__, icc_level);
6461 goto out;
6462 }
6463
0487fff7 6464 if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
3a4bf06d
YG		 6465 icc_level = ufshcd_get_max_icc_level(
6466 hba->vreg_info.vcc->max_uA,
6467 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6468 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6469
0487fff7 6470 if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
3a4bf06d
YG		 6471 icc_level = ufshcd_get_max_icc_level(
6472 hba->vreg_info.vccq->max_uA,
6473 icc_level,
6474 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6475
0487fff7 6476 if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
3a4bf06d
YG		 6477 icc_level = ufshcd_get_max_icc_level(
6478 hba->vreg_info.vccq2->max_uA,
6479 icc_level,
6480 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6481out:
6482 return icc_level;
6483}
6484
6485static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6486{
6487 int ret;
a4b0e8a4 6488 int buff_len = hba->desc_size.pwr_desc;
bbe21d7a
KC		 6489 u8 *desc_buf;
6490
6491 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6492 if (!desc_buf)
6493 return;
3a4bf06d
YG		 6494
6495 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
6496 if (ret) {
6497 dev_err(hba->dev,
6498 "%s: Failed reading power descriptor.len = %d ret = %d",
6499 __func__, buff_len, ret);
bbe21d7a 6500 goto out;
3a4bf06d
YG		 6501 }
6502
6503 hba->init_prefetch_data.icc_level =
6504 ufshcd_find_max_sup_active_icc_level(hba,
6505 desc_buf, buff_len);
6506 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6507 __func__, hba->init_prefetch_data.icc_level);
6508
dbd34a61
SM		 6509 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6510 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6511 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 6512
6513 if (ret)
6514 dev_err(hba->dev,
6515 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6516 __func__, hba->init_prefetch_data.icc_level , ret);
6517
bbe21d7a
KC		 6518out:
6519 kfree(desc_buf);
3a4bf06d
YG		 6520}
6521
2a8fa600
SJ		 6522/**
6523 * ufshcd_scsi_add_wlus - Adds required W-LUs
6524 * @hba: per-adapter instance
6525 *
6526 * UFS device specification requires the UFS devices to support 4 well known
6527 * logical units:
6528 * "REPORT_LUNS" (address: 01h)
6529 * "UFS Device" (address: 50h)
6530 * "RPMB" (address: 44h)
6531 * "BOOT" (address: 30h)
6532 * UFS device's power management needs to be controlled by "POWER CONDITION"
6533 * field of SSU (START STOP UNIT) command. But this "power condition" field
6534 * will take effect only when its sent to "UFS device" well known logical unit
6535 * hence we require the scsi_device instance to represent this logical unit in
6536 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 6537 *
2a8fa600
SJ		 6538 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6539 * Block) LU so user space process can control this LU. User space may also
6540 * want to have access to BOOT LU.
8aa29f19 6541 *
2a8fa600
SJ		 6542 * This function adds scsi device instances for each of all well known LUs
6543 * (except "REPORT LUNS" LU).
6544 *
6545 * Returns zero on success (all required W-LUs are added successfully),
6546 * non-zero error value on failure (if failed to add any of the required W-LU).
6547 */
6548static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6549{
6550 int ret = 0;
7c48bfd0
AM		 6551 struct scsi_device *sdev_rpmb;
6552 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6553
6554 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6555 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6556 if (IS_ERR(hba->sdev_ufs_device)) {
6557 ret = PTR_ERR(hba->sdev_ufs_device);
6558 hba->sdev_ufs_device = NULL;
6559 goto out;
6560 }
7c48bfd0 6561 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6562
7c48bfd0 6563 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6564 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6565 if (IS_ERR(sdev_rpmb)) {
6566 ret = PTR_ERR(sdev_rpmb);
3d21fbde 6567 goto remove_sdev_ufs_device;
2a8fa600 6568 }
7c48bfd0 6569 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 6570
6571 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6572 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
6573 if (IS_ERR(sdev_boot))
6574 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
6575 else
6576 scsi_device_put(sdev_boot);
2a8fa600
SJ		 6577 goto out;
6578
2a8fa600
SJ		 6579remove_sdev_ufs_device:
6580 scsi_remove_device(hba->sdev_ufs_device);
6581out:
6582 return ret;
6583}
6584
93fdd5ac
TW		 6585static int ufs_get_device_desc(struct ufs_hba *hba,
6586 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6587{
6588 int err;
bbe21d7a 6589 size_t buff_len;
c58ab7aa 6590 u8 model_index;
bbe21d7a
KC		 6591 u8 *desc_buf;
6592
4b828fe1
TW		 6593 if (!dev_desc)
6594 return -EINVAL;
6595
bbe21d7a
KC		 6596 buff_len = max_t(size_t, hba->desc_size.dev_desc,
6597 QUERY_DESC_MAX_SIZE + 1);
6598 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6599 if (!desc_buf) {
6600 err = -ENOMEM;
6601 goto out;
6602 }
c58ab7aa 6603
a4b0e8a4 6604 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
c58ab7aa
YG		 6605 if (err) {
6606 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6607 __func__, err);
6608 goto out;
6609 }
6610
6611 /*
6612 * getting vendor (manufacturerID) and Bank Index in big endian
6613 * format
6614 */
93fdd5ac 6615 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6616 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6617
6618 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
4b828fe1
TW		 6619 err = ufshcd_read_string_desc(hba, model_index,
6620 &dev_desc->model, SD_ASCII_STD);
6621 if (err < 0) {
c58ab7aa
YG		 6622 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6623 __func__, err);
6624 goto out;
6625 }
6626
4b828fe1
TW		 6627 /*
6628 * ufshcd_read_string_desc returns size of the string
6629 * reset the error value
6630 */
6631 err = 0;
c58ab7aa
YG		 6632
6633out:
bbe21d7a 6634 kfree(desc_buf);
c58ab7aa
YG		 6635 return err;
6636}
6637
4b828fe1
TW		 6638static void ufs_put_device_desc(struct ufs_dev_desc *dev_desc)
6639{
6640 kfree(dev_desc->model);
6641 dev_desc->model = NULL;
6642}
6643
93fdd5ac
TW		 6644static void ufs_fixup_device_setup(struct ufs_hba *hba,
6645 struct ufs_dev_desc *dev_desc)
c58ab7aa 6646{
c58ab7aa 6647 struct ufs_dev_fix *f;
c58ab7aa
YG		 6648
6649 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6650 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6651 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
4b828fe1
TW		 6652 ((dev_desc->model &&
6653 STR_PRFX_EQUAL(f->card.model, dev_desc->model)) ||
6654 !strcmp(f->card.model, UFS_ANY_MODEL)))
c58ab7aa
YG		 6655 hba->dev_quirks |= f->quirk;
6656 }
6657}
6658
37113106
YG		 6659/**
6660 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6661 * @hba: per-adapter instance
6662 *
6663 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6664 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6665 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6666 * the hibern8 exit latency.
6667 *
6668 * Returns zero on success, non-zero error value on failure.
6669 */
6670static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6671{
6672 int ret = 0;
6673 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6674
6675 ret = ufshcd_dme_peer_get(hba,
6676 UIC_ARG_MIB_SEL(
6677 RX_MIN_ACTIVATETIME_CAPABILITY,
6678 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6679 &peer_rx_min_activatetime);
6680 if (ret)
6681 goto out;
6682
6683 /* make sure proper unit conversion is applied */
6684 tuned_pa_tactivate =
6685 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6686 / PA_TACTIVATE_TIME_UNIT_US);
6687 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6688 tuned_pa_tactivate);
6689
6690out:
6691 return ret;
6692}
6693
6694/**
6695 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6696 * @hba: per-adapter instance
6697 *
6698 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6699 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6700 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6701 * This optimal value can help reduce the hibern8 exit latency.
6702 *
6703 * Returns zero on success, non-zero error value on failure.
6704 */
6705static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6706{
6707 int ret = 0;
6708 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6709 u32 max_hibern8_time, tuned_pa_hibern8time;
6710
6711 ret = ufshcd_dme_get(hba,
6712 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6713 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6714 &local_tx_hibern8_time_cap);
6715 if (ret)
6716 goto out;
6717
6718 ret = ufshcd_dme_peer_get(hba,
6719 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6720 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6721 &peer_rx_hibern8_time_cap);
6722 if (ret)
6723 goto out;
6724
6725 max_hibern8_time = max(local_tx_hibern8_time_cap,
6726 peer_rx_hibern8_time_cap);
6727 /* make sure proper unit conversion is applied */
6728 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6729 / PA_HIBERN8_TIME_UNIT_US);
6730 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6731 tuned_pa_hibern8time);
6732out:
6733 return ret;
6734}
6735
c6a6db43
SJ		 6736/**
6737 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6738 * less than device PA_TACTIVATE time.
6739 * @hba: per-adapter instance
6740 *
6741 * Some UFS devices require host PA_TACTIVATE to be lower than device
6742 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6743 * for such devices.
6744 *
6745 * Returns zero on success, non-zero error value on failure.
6746 */
6747static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6748{
6749 int ret = 0;
6750 u32 granularity, peer_granularity;
6751 u32 pa_tactivate, peer_pa_tactivate;
6752 u32 pa_tactivate_us, peer_pa_tactivate_us;
6753 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6754
6755 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6756 &granularity);
6757 if (ret)
6758 goto out;
6759
6760 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6761 &peer_granularity);
6762 if (ret)
6763 goto out;
6764
6765 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6766 (granularity > PA_GRANULARITY_MAX_VAL)) {
6767 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6768 __func__, granularity);
6769 return -EINVAL;
6770 }
6771
6772 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6773 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6774 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6775 __func__, peer_granularity);
6776 return -EINVAL;
6777 }
6778
6779 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6780 if (ret)
6781 goto out;
6782
6783 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6784 &peer_pa_tactivate);
6785 if (ret)
6786 goto out;
6787
6788 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6789 peer_pa_tactivate_us = peer_pa_tactivate *
6790 gran_to_us_table[peer_granularity - 1];
6791
6792 if (pa_tactivate_us > peer_pa_tactivate_us) {
6793 u32 new_peer_pa_tactivate;
6794
6795 new_peer_pa_tactivate = pa_tactivate_us /
6796 gran_to_us_table[peer_granularity - 1];
6797 new_peer_pa_tactivate++;
6798 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6799 new_peer_pa_tactivate);
6800 }
6801
6802out:
6803 return ret;
6804}
6805
37113106
YG		 6806static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6807{
6808 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6809 ufshcd_tune_pa_tactivate(hba);
6810 ufshcd_tune_pa_hibern8time(hba);
6811 }
6812
6813 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6814 /* set 1ms timeout for PA_TACTIVATE */
6815 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43
SJ		 6816
6817 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6818 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6819
6820 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6821}
6822
ff8e20c6
DR		 6823static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6824{
ff8e20c6
DR		 6825 hba->ufs_stats.hibern8_exit_cnt = 0;
6826 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7fabb77b 6827 hba->req_abort_count = 0;
ff8e20c6
DR		 6828}
6829
a4b0e8a4
PM		 6830static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6831{
6832 int err;
6833
6834 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6835 &hba->desc_size.dev_desc);
6836 if (err)
6837 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6838
6839 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6840 &hba->desc_size.pwr_desc);
6841 if (err)
6842 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6843
6844 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6845 &hba->desc_size.interc_desc);
6846 if (err)
6847 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6848
6849 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6850 &hba->desc_size.conf_desc);
6851 if (err)
6852 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6853
6854 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6855 &hba->desc_size.unit_desc);
6856 if (err)
6857 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6858
6859 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6860 &hba->desc_size.geom_desc);
6861 if (err)
6862 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
059efd84 6863
c648c2d2
SN		 6864 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
6865 &hba->desc_size.hlth_desc);
6866 if (err)
6867 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 6868}
6869
9e1e8a75
SJ		 6870static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
6871 {19200000, REF_CLK_FREQ_19_2_MHZ},
6872 {26000000, REF_CLK_FREQ_26_MHZ},
6873 {38400000, REF_CLK_FREQ_38_4_MHZ},
6874 {52000000, REF_CLK_FREQ_52_MHZ},
6875 {0, REF_CLK_FREQ_INVAL},
6876};
6877
6878static enum ufs_ref_clk_freq
6879ufs_get_bref_clk_from_hz(unsigned long freq)
6880{
6881 int i;
6882
6883 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
6884 if (ufs_ref_clk_freqs[i].freq_hz == freq)
6885 return ufs_ref_clk_freqs[i].val;
6886
6887 return REF_CLK_FREQ_INVAL;
6888}
6889
6890void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
6891{
6892 unsigned long freq;
6893
6894 freq = clk_get_rate(refclk);
6895
6896 hba->dev_ref_clk_freq =
6897 ufs_get_bref_clk_from_hz(freq);
6898
6899 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
6900 dev_err(hba->dev,
6901 "invalid ref_clk setting = %ld\n", freq);
6902}
6903
6904static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
6905{
6906 int err;
6907 u32 ref_clk;
6908 u32 freq = hba->dev_ref_clk_freq;
6909
6910 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6911 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
6912
6913 if (err) {
6914 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
6915 err);
6916 goto out;
6917 }
6918
6919 if (ref_clk == freq)
6920 goto out; /* nothing to update */
6921
6922 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6923 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
6924
6925 if (err) {
6926 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
6927 ufs_ref_clk_freqs[freq].freq_hz);
6928 goto out;
6929 }
6930
6931 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
6932 ufs_ref_clk_freqs[freq].freq_hz);
6933
6934out:
6935 return err;
6936}
6937
6ccf44fe 6938/**
1d337ec2
SRT		 6939 * ufshcd_probe_hba - probe hba to detect device and initialize
6940 * @hba: per-adapter instance
6941 *
6942 * Execute link-startup and verify device initialization
6ccf44fe 6943 */
1d337ec2 6944static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6945{
93fdd5ac 6946 struct ufs_dev_desc card = {0};
6ccf44fe 6947 int ret;
7ff5ab47 6948 ktime_t start = ktime_get();
6ccf44fe
SJ		 6949
6950 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6951 if (ret)
6952 goto out;
6953
afdfff59
YG		 6954 /* set the default level for urgent bkops */
6955 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6956 hba->is_urgent_bkops_lvl_checked = false;
6957
ff8e20c6
DR		 6958 /* Debug counters initialization */
6959 ufshcd_clear_dbg_ufs_stats(hba);
6960
57d104c1
SJ		 6961 /* UniPro link is active now */
6962 ufshcd_set_link_active(hba);
d3e89bac 6963
5a0b0cb9
SRT		 6964 ret = ufshcd_verify_dev_init(hba);
6965 if (ret)
6966 goto out;
68078d5c
DR		 6967
6968 ret = ufshcd_complete_dev_init(hba);
6969 if (ret)
6970 goto out;
5a0b0cb9 6971
a4b0e8a4
PM		 6972 /* Init check for device descriptor sizes */
6973 ufshcd_init_desc_sizes(hba);
6974
93fdd5ac
TW		 6975 ret = ufs_get_device_desc(hba, &card);
6976 if (ret) {
6977 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6978 __func__, ret);
6979 goto out;
6980 }
6981
6982 ufs_fixup_device_setup(hba, &card);
4b828fe1
TW		 6983 ufs_put_device_desc(&card);
6984
37113106 6985 ufshcd_tune_unipro_params(hba);
60f01870 6986
57d104c1
SJ		 6987 /* UFS device is also active now */
6988 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6989 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6990 hba->wlun_dev_clr_ua = true;
6991
7eb584db
DR		 6992 if (ufshcd_get_max_pwr_mode(hba)) {
6993 dev_err(hba->dev,
6994 "%s: Failed getting max supported power mode\n",
6995 __func__);
6996 } else {
9e1e8a75
SJ		 6997 /*
6998 * Set the right value to bRefClkFreq before attempting to
6999 * switch to HS gears.
7000 */
7001 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
7002 ufshcd_set_dev_ref_clk(hba);
7eb584db 7003 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 7004 if (ret) {
7eb584db
DR		 7005 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
7006 __func__, ret);
8643ae66
DL		 7007 goto out;
7008 }
7eb584db 7009 }
57d104c1 7010
53c12d0e
YG		 7011 /* set the state as operational after switching to desired gear */
7012 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 7013
71d848b8
CG		 7014 /* Enable Auto-Hibernate if configured */
7015 ufshcd_auto_hibern8_enable(hba);
7016
57d104c1
SJ		 7017 /*
7018 * If we are in error handling context or in power management callbacks
7019 * context, no need to scan the host
7020 */
7021 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
7022 bool flag;
7023
7024 /* clear any previous UFS device information */
7025 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 7026 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
7027 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 7028 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 7029
3a4bf06d
YG		 7030 if (!hba->is_init_prefetch)
7031 ufshcd_init_icc_levels(hba);
7032
2a8fa600
SJ		 7033 /* Add required well known logical units to scsi mid layer */
7034 if (ufshcd_scsi_add_wlus(hba))
7035 goto out;
7036
0701e49d
SJ		 7037 /* Initialize devfreq after UFS device is detected */
7038 if (ufshcd_is_clkscaling_supported(hba)) {
7039 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7040 &hba->pwr_info,
7041 sizeof(struct ufs_pa_layer_attr));
7042 hba->clk_scaling.saved_pwr_info.is_valid = true;
7043 if (!hba->devfreq) {
deac444f
BA		 7044 ret = ufshcd_devfreq_init(hba);
7045 if (ret)
0701e49d 7046 goto out;
0701e49d
SJ		 7047 }
7048 hba->clk_scaling.is_allowed = true;
7049 }
7050
df032bf2
AA		 7051 ufs_bsg_probe(hba);
7052
3441da7d
SRT		 7053 scsi_scan_host(hba->host);
7054 pm_runtime_put_sync(hba->dev);
7055 }
3a4bf06d
YG		 7056
7057 if (!hba->is_init_prefetch)
7058 hba->is_init_prefetch = true;
7059
5a0b0cb9 7060out:
1d337ec2
SRT		 7061 /*
7062 * If we failed to initialize the device or the device is not
7063 * present, turn off the power/clocks etc.
7064 */
57d104c1
SJ		 7065 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
7066 pm_runtime_put_sync(hba->dev);
eebcc196 7067 ufshcd_exit_clk_scaling(hba);
1d337ec2 7068 ufshcd_hba_exit(hba);
57d104c1 7069 }
1d337ec2 7070
7ff5ab47
SJ		 7071 trace_ufshcd_init(dev_name(hba->dev), ret,
7072 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7073 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 7074 return ret;
7075}
7076
7077/**
7078 * ufshcd_async_scan - asynchronous execution for probing hba
7079 * @data: data pointer to pass to this function
7080 * @cookie: cookie data
7081 */
7082static void ufshcd_async_scan(void *data, async_cookie_t cookie)
7083{
7084 struct ufs_hba *hba = (struct ufs_hba *)data;
7085
7086 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 7087}
7088
d829fc8a
SN		 7089static const struct attribute_group *ufshcd_driver_groups[] = {
7090 &ufs_sysfs_unit_descriptor_group,
ec92b59c 7091 &ufs_sysfs_lun_attributes_group,
d829fc8a
SN		 7092 NULL,
7093};
7094
7a3e97b0
SY		 7095static struct scsi_host_template ufshcd_driver_template = {
7096 .module = THIS_MODULE,
7097 .name = UFSHCD,
7098 .proc_name = UFSHCD,
7099 .queuecommand = ufshcd_queuecommand,
7100 .slave_alloc = ufshcd_slave_alloc,
eeda4749 7101 .slave_configure = ufshcd_slave_configure,
7a3e97b0 7102 .slave_destroy = ufshcd_slave_destroy,
4264fd61 7103 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 7104 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 7105 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
7106 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 7107 .this_id = -1,
7108 .sg_tablesize = SG_ALL,
7109 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
7110 .can_queue = UFSHCD_CAN_QUEUE,
552a990c 7111 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
1ab27c9c 7112 .max_host_blocked = 1,
c40ecc12 7113 .track_queue_depth = 1,
d829fc8a 7114 .sdev_groups = ufshcd_driver_groups,
4af14d11 7115 .dma_boundary = PAGE_SIZE - 1,
49615ba1 7116 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
7a3e97b0
SY		 7117};
7118
57d104c1
SJ		 7119static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
7120 int ua)
7121{
7b16a07c 7122 int ret;
57d104c1 7123
7b16a07c
BA		 7124 if (!vreg)
7125 return 0;
57d104c1 7126
0487fff7
SC		 7127 /*
7128 * "set_load" operation shall be required on those regulators
7129 * which specifically configured current limitation. Otherwise
7130 * zero max_uA may cause unexpected behavior when regulator is
7131 * enabled or set as high power mode.
7132 */
7133 if (!vreg->max_uA)
7134 return 0;
7135
7b16a07c
BA		 7136 ret = regulator_set_load(vreg->reg, ua);
7137 if (ret < 0) {
7138 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7139 __func__, vreg->name, ua, ret);
57d104c1
SJ		 7140 }
7141
7142 return ret;
7143}
7144
7145static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
7146 struct ufs_vreg *vreg)
7147{
73067981 7148 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 7149}
7150
7151static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
7152 struct ufs_vreg *vreg)
7153{
7c7cfdcf
AH		 7154 if (!vreg)
7155 return 0;
7156
73067981 7157 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 7158}
7159
aa497613
SRT		 7160static int ufshcd_config_vreg(struct device *dev,
7161 struct ufs_vreg *vreg, bool on)
7162{
7163 int ret = 0;
72753590
GS		 7164 struct regulator *reg;
7165 const char *name;
aa497613
SRT		 7166 int min_uV, uA_load;
7167
7168 BUG_ON(!vreg);
7169
72753590
GS		 7170 reg = vreg->reg;
7171 name = vreg->name;
7172
aa497613 7173 if (regulator_count_voltages(reg) > 0) {
3b141e8c
SC		 7174 if (vreg->min_uV && vreg->max_uV) {
7175 min_uV = on ? vreg->min_uV : 0;
7176 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
7177 if (ret) {
7178 dev_err(dev,
7179 "%s: %s set voltage failed, err=%d\n",
aa497613 7180 __func__, name, ret);
3b141e8c
SC		 7181 goto out;
7182 }
aa497613
SRT		 7183 }
7184
7185 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 7186 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
7187 if (ret)
aa497613 7188 goto out;
aa497613
SRT		 7189 }
7190out:
7191 return ret;
7192}
7193
7194static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
7195{
7196 int ret = 0;
7197
73067981 7198 if (!vreg || vreg->enabled)
aa497613
SRT		 7199 goto out;
7200
7201 ret = ufshcd_config_vreg(dev, vreg, true);
7202 if (!ret)
7203 ret = regulator_enable(vreg->reg);
7204
7205 if (!ret)
7206 vreg->enabled = true;
7207 else
7208 dev_err(dev, "%s: %s enable failed, err=%d\n",
7209 __func__, vreg->name, ret);
7210out:
7211 return ret;
7212}
7213
7214static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7215{
7216 int ret = 0;
7217
73067981 7218 if (!vreg || !vreg->enabled)
aa497613
SRT		 7219 goto out;
7220
7221 ret = regulator_disable(vreg->reg);
7222
7223 if (!ret) {
7224 /* ignore errors on applying disable config */
7225 ufshcd_config_vreg(dev, vreg, false);
7226 vreg->enabled = false;
7227 } else {
7228 dev_err(dev, "%s: %s disable failed, err=%d\n",
7229 __func__, vreg->name, ret);
7230 }
7231out:
7232 return ret;
7233}
7234
7235static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7236{
7237 int ret = 0;
7238 struct device *dev = hba->dev;
7239 struct ufs_vreg_info *info = &hba->vreg_info;
7240
aa497613
SRT		 7241 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7242 if (ret)
7243 goto out;
7244
7245 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7246 if (ret)
7247 goto out;
7248
7249 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7250 if (ret)
7251 goto out;
7252
7253out:
7254 if (ret) {
7255 ufshcd_toggle_vreg(dev, info->vccq2, false);
7256 ufshcd_toggle_vreg(dev, info->vccq, false);
7257 ufshcd_toggle_vreg(dev, info->vcc, false);
7258 }
7259 return ret;
7260}
7261
6a771a65
RS		 7262static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7263{
7264 struct ufs_vreg_info *info = &hba->vreg_info;
7265
60b7b823 7266 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6a771a65
RS		 7267}
7268
aa497613
SRT		 7269static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7270{
7271 int ret = 0;
7272
7273 if (!vreg)
7274 goto out;
7275
7276 vreg->reg = devm_regulator_get(dev, vreg->name);
7277 if (IS_ERR(vreg->reg)) {
7278 ret = PTR_ERR(vreg->reg);
7279 dev_err(dev, "%s: %s get failed, err=%d\n",
7280 __func__, vreg->name, ret);
7281 }
7282out:
7283 return ret;
7284}
7285
7286static int ufshcd_init_vreg(struct ufs_hba *hba)
7287{
7288 int ret = 0;
7289 struct device *dev = hba->dev;
7290 struct ufs_vreg_info *info = &hba->vreg_info;
7291
aa497613
SRT		 7292 ret = ufshcd_get_vreg(dev, info->vcc);
7293 if (ret)
7294 goto out;
7295
7296 ret = ufshcd_get_vreg(dev, info->vccq);
7297 if (ret)
7298 goto out;
7299
7300 ret = ufshcd_get_vreg(dev, info->vccq2);
7301out:
7302 return ret;
7303}
7304
6a771a65
RS		 7305static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7306{
7307 struct ufs_vreg_info *info = &hba->vreg_info;
7308
7309 if (info)
7310 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7311
7312 return 0;
7313}
7314
57d104c1
SJ		 7315static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7316 bool skip_ref_clk)
c6e79dac
SRT		 7317{
7318 int ret = 0;
7319 struct ufs_clk_info *clki;
7320 struct list_head *head = &hba->clk_list_head;
1ab27c9c 7321 unsigned long flags;
911a0771
SJ		 7322 ktime_t start = ktime_get();
7323 bool clk_state_changed = false;
c6e79dac 7324
566ec9ad 7325 if (list_empty(head))
c6e79dac
SRT		 7326 goto out;
7327
b334456e
SJ		 7328 /*
7329 * vendor specific setup_clocks ops may depend on clocks managed by
7330 * this standard driver hence call the vendor specific setup_clocks
7331 * before disabling the clocks managed here.
7332 */
7333 if (!on) {
7334 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7335 if (ret)
7336 return ret;
7337 }
1e879e8f 7338
c6e79dac
SRT		 7339 list_for_each_entry(clki, head, list) {
7340 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 7341 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7342 continue;
7343
911a0771 7344 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7345 if (on && !clki->enabled) {
7346 ret = clk_prepare_enable(clki->clk);
7347 if (ret) {
7348 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7349 __func__, clki->name, ret);
7350 goto out;
7351 }
7352 } else if (!on && clki->enabled) {
7353 clk_disable_unprepare(clki->clk);
7354 }
7355 clki->enabled = on;
7356 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7357 clki->name, on ? "en" : "dis");
7358 }
7359 }
1ab27c9c 7360
b334456e
SJ		 7361 /*
7362 * vendor specific setup_clocks ops may depend on clocks managed by
7363 * this standard driver hence call the vendor specific setup_clocks
7364 * after enabling the clocks managed here.
7365 */
7366 if (on) {
7367 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7368 if (ret)
7369 return ret;
7370 }
1e879e8f 7371
c6e79dac
SRT		 7372out:
7373 if (ret) {
7374 list_for_each_entry(clki, head, list) {
7375 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7376 clk_disable_unprepare(clki->clk);
7377 }
7ff5ab47 7378 } else if (!ret && on) {
1ab27c9c
ST		 7379 spin_lock_irqsave(hba->host->host_lock, flags);
7380 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 7381 trace_ufshcd_clk_gating(dev_name(hba->dev),
7382 hba->clk_gating.state);
1ab27c9c 7383 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7384 }
7ff5ab47 7385
911a0771
SJ		 7386 if (clk_state_changed)
7387 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7388 (on ? "on" : "off"),
7389 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7390 return ret;
7391}
7392
57d104c1
SJ		 7393static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7394{
7395 return __ufshcd_setup_clocks(hba, on, false);
7396}
7397
c6e79dac
SRT		 7398static int ufshcd_init_clocks(struct ufs_hba *hba)
7399{
7400 int ret = 0;
7401 struct ufs_clk_info *clki;
7402 struct device *dev = hba->dev;
7403 struct list_head *head = &hba->clk_list_head;
7404
566ec9ad 7405 if (list_empty(head))
c6e79dac
SRT		 7406 goto out;
7407
7408 list_for_each_entry(clki, head, list) {
7409 if (!clki->name)
7410 continue;
7411
7412 clki->clk = devm_clk_get(dev, clki->name);
7413 if (IS_ERR(clki->clk)) {
7414 ret = PTR_ERR(clki->clk);
7415 dev_err(dev, "%s: %s clk get failed, %d\n",
7416 __func__, clki->name, ret);
7417 goto out;
7418 }
7419
9e1e8a75
SJ		 7420 /*
7421 * Parse device ref clk freq as per device tree "ref_clk".
7422 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
7423 * in ufshcd_alloc_host().
7424 */
7425 if (!strcmp(clki->name, "ref_clk"))
7426 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
7427
c6e79dac
SRT		 7428 if (clki->max_freq) {
7429 ret = clk_set_rate(clki->clk, clki->max_freq);
7430 if (ret) {
7431 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7432 __func__, clki->name,
7433 clki->max_freq, ret);
7434 goto out;
7435 }
856b3483 7436 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 7437 }
7438 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7439 clki->name, clk_get_rate(clki->clk));
7440 }
7441out:
7442 return ret;
7443}
7444
5c0c28a8
SRT		 7445static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7446{
7447 int err = 0;
7448
7449 if (!hba->vops)
7450 goto out;
7451
0263bcd0
YG		 7452 err = ufshcd_vops_init(hba);
7453 if (err)
7454 goto out;
5c0c28a8 7455
0263bcd0
YG		 7456 err = ufshcd_vops_setup_regulators(hba, true);
7457 if (err)
7458 goto out_exit;
5c0c28a8
SRT		 7459
7460 goto out;
7461
5c0c28a8 7462out_exit:
0263bcd0 7463 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7464out:
7465 if (err)
7466 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7467 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7468 return err;
7469}
7470
7471static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7472{
7473 if (!hba->vops)
7474 return;
7475
0263bcd0 7476 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7477
0263bcd0 7478 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7479}
7480
aa497613
SRT		 7481static int ufshcd_hba_init(struct ufs_hba *hba)
7482{
7483 int err;
7484
6a771a65
RS		 7485 /*
7486 * Handle host controller power separately from the UFS device power
7487 * rails as it will help controlling the UFS host controller power
7488 * collapse easily which is different than UFS device power collapse.
7489 * Also, enable the host controller power before we go ahead with rest
7490 * of the initialization here.
7491 */
7492 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7493 if (err)
7494 goto out;
7495
6a771a65 7496 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7497 if (err)
7498 goto out;
7499
6a771a65
RS		 7500 err = ufshcd_init_clocks(hba);
7501 if (err)
7502 goto out_disable_hba_vreg;
7503
7504 err = ufshcd_setup_clocks(hba, true);
7505 if (err)
7506 goto out_disable_hba_vreg;
7507
c6e79dac
SRT		 7508 err = ufshcd_init_vreg(hba);
7509 if (err)
7510 goto out_disable_clks;
7511
7512 err = ufshcd_setup_vreg(hba, true);
7513 if (err)
7514 goto out_disable_clks;
7515
aa497613
SRT		 7516 err = ufshcd_variant_hba_init(hba);
7517 if (err)
7518 goto out_disable_vreg;
7519
1d337ec2 7520 hba->is_powered = true;
aa497613
SRT		 7521 goto out;
7522
7523out_disable_vreg:
7524 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7525out_disable_clks:
7526 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7527out_disable_hba_vreg:
7528 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7529out:
7530 return err;
7531}
7532
7533static void ufshcd_hba_exit(struct ufs_hba *hba)
7534{
1d337ec2
SRT		 7535 if (hba->is_powered) {
7536 ufshcd_variant_hba_exit(hba);
7537 ufshcd_setup_vreg(hba, false);
a508253d 7538 ufshcd_suspend_clkscaling(hba);
eebcc196 7539 if (ufshcd_is_clkscaling_supported(hba))
0701e49d
SJ		 7540 if (hba->devfreq)
7541 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 7542 ufshcd_setup_clocks(hba, false);
7543 ufshcd_setup_hba_vreg(hba, false);
7544 hba->is_powered = false;
7545 }
aa497613
SRT		 7546}
7547
57d104c1
SJ		 7548static int
7549ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7550{
7551 unsigned char cmd[6] = {REQUEST_SENSE,
7552 0,
7553 0,
7554 0,
09a5a24f 7555 UFS_SENSE_SIZE,
57d104c1
SJ		 7556 0};
7557 char *buffer;
7558 int ret;
7559
09a5a24f 7560 buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7561 if (!buffer) {
7562 ret = -ENOMEM;
7563 goto out;
7564 }
7565
fcbfffe2 7566 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
09a5a24f 7567 UFS_SENSE_SIZE, NULL, NULL,
fcbfffe2 7568 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7569 if (ret)
7570 pr_err("%s: failed with err %d\n", __func__, ret);
7571
7572 kfree(buffer);
7573out:
7574 return ret;
7575}
7576
7577/**
7578 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7579 * power mode
7580 * @hba: per adapter instance
7581 * @pwr_mode: device power mode to set
7582 *
7583 * Returns 0 if requested power mode is set successfully
7584 * Returns non-zero if failed to set the requested power mode
7585 */
7586static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7587 enum ufs_dev_pwr_mode pwr_mode)
7588{
7589 unsigned char cmd[6] = { START_STOP };
7590 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7591 struct scsi_device *sdp;
7592 unsigned long flags;
57d104c1
SJ		 7593 int ret;
7594
7c48bfd0
AM		 7595 spin_lock_irqsave(hba->host->host_lock, flags);
7596 sdp = hba->sdev_ufs_device;
7597 if (sdp) {
7598 ret = scsi_device_get(sdp);
7599 if (!ret && !scsi_device_online(sdp)) {
7600 ret = -ENODEV;
7601 scsi_device_put(sdp);
7602 }
7603 } else {
7604 ret = -ENODEV;
7605 }
7606 spin_unlock_irqrestore(hba->host->host_lock, flags);
7607
7608 if (ret)
7609 return ret;
57d104c1
SJ		 7610
7611 /*
7612 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7613 * handling, which would wait for host to be resumed. Since we know
7614 * we are functional while we are here, skip host resume in error
7615 * handling context.
7616 */
7617 hba->host->eh_noresume = 1;
7618 if (hba->wlun_dev_clr_ua) {
7619 ret = ufshcd_send_request_sense(hba, sdp);
7620 if (ret)
7621 goto out;
7622 /* Unit attention condition is cleared now */
7623 hba->wlun_dev_clr_ua = false;
7624 }
7625
7626 cmd[4] = pwr_mode << 4;
7627
7628 /*
7629 * Current function would be generally called from the power management
e8064021 7630 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7631 * already suspended childs.
7632 */
fcbfffe2
CH		 7633 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7634 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7635 if (ret) {
7636 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7637 "START_STOP failed for power mode: %d, result %x\n",
7638 pwr_mode, ret);
c65be1a6 7639 if (driver_byte(ret) == DRIVER_SENSE)
21045519 7640 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7641 }
7642
7643 if (!ret)
7644 hba->curr_dev_pwr_mode = pwr_mode;
7645out:
7c48bfd0 7646 scsi_device_put(sdp);
57d104c1
SJ		 7647 hba->host->eh_noresume = 0;
7648 return ret;
7649}
7650
7651static int ufshcd_link_state_transition(struct ufs_hba *hba,
7652 enum uic_link_state req_link_state,
7653 int check_for_bkops)
7654{
7655 int ret = 0;
7656
7657 if (req_link_state == hba->uic_link_state)
7658 return 0;
7659
7660 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7661 ret = ufshcd_uic_hibern8_enter(hba);
7662 if (!ret)
7663 ufshcd_set_link_hibern8(hba);
7664 else
7665 goto out;
7666 }
7667 /*
7668 * If autobkops is enabled, link can't be turned off because
7669 * turning off the link would also turn off the device.
7670 */
7671 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
dc30c9e6 7672 (!check_for_bkops || !hba->auto_bkops_enabled)) {
f3099fbd
YG		 7673 /*
7674 * Let's make sure that link is in low power mode, we are doing
7675 * this currently by putting the link in Hibern8. Otherway to
7676 * put the link in low power mode is to send the DME end point
7677 * to device and then send the DME reset command to local
7678 * unipro. But putting the link in hibern8 is much faster.
7679 */
7680 ret = ufshcd_uic_hibern8_enter(hba);
7681 if (ret)
7682 goto out;
57d104c1
SJ		 7683 /*
7684 * Change controller state to "reset state" which
7685 * should also put the link in off/reset state
7686 */
596585a2 7687 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 7688 /*
7689 * TODO: Check if we need any delay to make sure that
7690 * controller is reset
7691 */
7692 ufshcd_set_link_off(hba);
7693 }
7694
7695out:
7696 return ret;
7697}
7698
7699static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7700{
b799fdf7
YG		 7701 /*
7702 * It seems some UFS devices may keep drawing more than sleep current
7703 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7704 * To avoid this situation, add 2ms delay before putting these UFS
7705 * rails in LPM mode.
7706 */
7707 if (!ufshcd_is_link_active(hba) &&
7708 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7709 usleep_range(2000, 2100);
7710
57d104c1
SJ		 7711 /*
7712 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7713 * power.
7714 *
7715 * If UFS device and link is in OFF state, all power supplies (VCC,
7716 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7717 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7718 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7719 *
7720 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7721 * in low power state which would save some power.
7722 */
7723 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7724 !hba->dev_info.is_lu_power_on_wp) {
7725 ufshcd_setup_vreg(hba, false);
7726 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7727 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7728 if (!ufshcd_is_link_active(hba)) {
7729 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7730 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7731 }
7732 }
7733}
7734
7735static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7736{
7737 int ret = 0;
7738
7739 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7740 !hba->dev_info.is_lu_power_on_wp) {
7741 ret = ufshcd_setup_vreg(hba, true);
7742 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7743 if (!ret && !ufshcd_is_link_active(hba)) {
7744 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7745 if (ret)
7746 goto vcc_disable;
7747 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7748 if (ret)
7749 goto vccq_lpm;
7750 }
69d72ac8 7751 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7752 }
7753 goto out;
7754
7755vccq_lpm:
7756 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7757vcc_disable:
7758 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7759out:
7760 return ret;
7761}
7762
7763static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7764{
7765 if (ufshcd_is_link_off(hba))
7766 ufshcd_setup_hba_vreg(hba, false);
7767}
7768
7769static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7770{
7771 if (ufshcd_is_link_off(hba))
7772 ufshcd_setup_hba_vreg(hba, true);
7773}
7774
7a3e97b0 7775/**
57d104c1 7776 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7777 * @hba: per adapter instance
57d104c1
SJ		 7778 * @pm_op: desired low power operation type
7779 *
7780 * This function will try to put the UFS device and link into low power
7781 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7782 * (System PM level).
7783 *
7784 * If this function is called during shutdown, it will make sure that
7785 * both UFS device and UFS link is powered off.
7a3e97b0 7786 *
57d104c1
SJ		 7787 * NOTE: UFS device & link must be active before we enter in this function.
7788 *
7789 * Returns 0 for success and non-zero for failure
7a3e97b0 7790 */
57d104c1 7791static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7792{
57d104c1
SJ		 7793 int ret = 0;
7794 enum ufs_pm_level pm_lvl;
7795 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7796 enum uic_link_state req_link_state;
7797
7798 hba->pm_op_in_progress = 1;
7799 if (!ufshcd_is_shutdown_pm(pm_op)) {
7800 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7801 hba->rpm_lvl : hba->spm_lvl;
7802 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7803 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7804 } else {
7805 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7806 req_link_state = UIC_LINK_OFF_STATE;
7807 }
7808
7a3e97b0 7809 /*
57d104c1
SJ		 7810 * If we can't transition into any of the low power modes
7811 * just gate the clocks.
7a3e97b0 7812 */
1ab27c9c
ST		 7813 ufshcd_hold(hba, false);
7814 hba->clk_gating.is_suspended = true;
7815
401f1e44
SJ		 7816 if (hba->clk_scaling.is_allowed) {
7817 cancel_work_sync(&hba->clk_scaling.suspend_work);
7818 cancel_work_sync(&hba->clk_scaling.resume_work);
7819 ufshcd_suspend_clkscaling(hba);
7820 }
d6fcf81a 7821
57d104c1
SJ		 7822 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7823 req_link_state == UIC_LINK_ACTIVE_STATE) {
7824 goto disable_clks;
7825 }
7a3e97b0 7826
57d104c1
SJ		 7827 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7828 (req_link_state == hba->uic_link_state))
d6fcf81a 7829 goto enable_gating;
57d104c1
SJ		 7830
7831 /* UFS device & link must be active before we enter in this function */
7832 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7833 ret = -EINVAL;
d6fcf81a 7834 goto enable_gating;
57d104c1
SJ		 7835 }
7836
7837 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7838 if (ufshcd_can_autobkops_during_suspend(hba)) {
7839 /*
7840 * The device is idle with no requests in the queue,
7841 * allow background operations if bkops status shows
7842 * that performance might be impacted.
7843 */
7844 ret = ufshcd_urgent_bkops(hba);
7845 if (ret)
7846 goto enable_gating;
7847 } else {
7848 /* make sure that auto bkops is disabled */
7849 ufshcd_disable_auto_bkops(hba);
7850 }
57d104c1
SJ		 7851 }
7852
7853 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7854 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7855 !ufshcd_is_runtime_pm(pm_op))) {
7856 /* ensure that bkops is disabled */
7857 ufshcd_disable_auto_bkops(hba);
7858 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7859 if (ret)
1ab27c9c 7860 goto enable_gating;
57d104c1
SJ		 7861 }
7862
7863 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7864 if (ret)
7865 goto set_dev_active;
7866
7867 ufshcd_vreg_set_lpm(hba);
7868
7869disable_clks:
7870 /*
7871 * Call vendor specific suspend callback. As these callbacks may access
7872 * vendor specific host controller register space call them before the
7873 * host clocks are ON.
7874 */
0263bcd0
YG		 7875 ret = ufshcd_vops_suspend(hba, pm_op);
7876 if (ret)
7877 goto set_link_active;
dcb6cec5
SC		 7878 /*
7879 * Disable the host irq as host controller as there won't be any
7880 * host controller transaction expected till resume.
7881 */
7882 ufshcd_disable_irq(hba);
57d104c1 7883
57d104c1
SJ		 7884 if (!ufshcd_is_link_active(hba))
7885 ufshcd_setup_clocks(hba, false);
7886 else
7887 /* If link is active, device ref_clk can't be switched off */
7888 __ufshcd_setup_clocks(hba, false, true);
7889
1ab27c9c 7890 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7891 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
dcb6cec5 7892
57d104c1
SJ		 7893 /* Put the host controller in low power mode if possible */
7894 ufshcd_hba_vreg_set_lpm(hba);
7895 goto out;
7896
57d104c1 7897set_link_active:
401f1e44
SJ		 7898 if (hba->clk_scaling.is_allowed)
7899 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 7900 ufshcd_vreg_set_hpm(hba);
7901 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7902 ufshcd_set_link_active(hba);
7903 else if (ufshcd_is_link_off(hba))
7904 ufshcd_host_reset_and_restore(hba);
7905set_dev_active:
7906 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7907 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7908enable_gating:
401f1e44
SJ		 7909 if (hba->clk_scaling.is_allowed)
7910 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7911 hba->clk_gating.is_suspended = false;
7912 ufshcd_release(hba);
57d104c1
SJ		 7913out:
7914 hba->pm_op_in_progress = 0;
8808b4e9
SC		 7915 if (ret)
7916 ufshcd_update_reg_hist(&hba->ufs_stats.suspend_err, (u32)ret);
57d104c1 7917 return ret;
7a3e97b0
SY		 7918}
7919
7920/**
57d104c1 7921 * ufshcd_resume - helper function for resume operations
3b1d0580 7922 * @hba: per adapter instance
57d104c1 7923 * @pm_op: runtime PM or system PM
7a3e97b0 7924 *
57d104c1
SJ		 7925 * This function basically brings the UFS device, UniPro link and controller
7926 * to active state.
7927 *
7928 * Returns 0 for success and non-zero for failure
7a3e97b0 7929 */
57d104c1 7930static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7931{
57d104c1
SJ		 7932 int ret;
7933 enum uic_link_state old_link_state;
7934
7935 hba->pm_op_in_progress = 1;
7936 old_link_state = hba->uic_link_state;
7937
7938 ufshcd_hba_vreg_set_hpm(hba);
7939 /* Make sure clocks are enabled before accessing controller */
7940 ret = ufshcd_setup_clocks(hba, true);
7941 if (ret)
7942 goto out;
7943
57d104c1 7944 /* enable the host irq as host controller would be active soon */
5231d38c 7945 ufshcd_enable_irq(hba);
57d104c1
SJ		 7946
7947 ret = ufshcd_vreg_set_hpm(hba);
7948 if (ret)
7949 goto disable_irq_and_vops_clks;
7950
7a3e97b0 7951 /*
57d104c1
SJ		 7952 * Call vendor specific resume callback. As these callbacks may access
7953 * vendor specific host controller register space call them when the
7954 * host clocks are ON.
7a3e97b0 7955 */
0263bcd0
YG		 7956 ret = ufshcd_vops_resume(hba, pm_op);
7957 if (ret)
7958 goto disable_vreg;
57d104c1
SJ		 7959
7960 if (ufshcd_is_link_hibern8(hba)) {
7961 ret = ufshcd_uic_hibern8_exit(hba);
7962 if (!ret)
7963 ufshcd_set_link_active(hba);
7964 else
7965 goto vendor_suspend;
7966 } else if (ufshcd_is_link_off(hba)) {
7967 ret = ufshcd_host_reset_and_restore(hba);
7968 /*
7969 * ufshcd_host_reset_and_restore() should have already
7970 * set the link state as active
7971 */
7972 if (ret || !ufshcd_is_link_active(hba))
7973 goto vendor_suspend;
7974 }
7975
7976 if (!ufshcd_is_ufs_dev_active(hba)) {
7977 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7978 if (ret)
7979 goto set_old_link_state;
7980 }
7981
4e768e76
SJ		 7982 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7983 ufshcd_enable_auto_bkops(hba);
7984 else
7985 /*
7986 * If BKOPs operations are urgently needed at this moment then
7987 * keep auto-bkops enabled or else disable it.
7988 */
7989 ufshcd_urgent_bkops(hba);
7990
1ab27c9c
ST		 7991 hba->clk_gating.is_suspended = false;
7992
fcb0c4b0
ST		 7993 if (hba->clk_scaling.is_allowed)
7994 ufshcd_resume_clkscaling(hba);
856b3483 7995
ad448378
AH		 7996 /* Enable Auto-Hibernate if configured */
7997 ufshcd_auto_hibern8_enable(hba);
7998
71d848b8
CG		 7999 /* Schedule clock gating in case of no access to UFS device yet */
8000 ufshcd_release(hba);
8001
57d104c1
SJ		 8002 goto out;
8003
8004set_old_link_state:
8005 ufshcd_link_state_transition(hba, old_link_state, 0);
8006vendor_suspend:
0263bcd0 8007 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 8008disable_vreg:
8009 ufshcd_vreg_set_lpm(hba);
8010disable_irq_and_vops_clks:
8011 ufshcd_disable_irq(hba);
401f1e44
SJ		 8012 if (hba->clk_scaling.is_allowed)
8013 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 8014 ufshcd_setup_clocks(hba, false);
8015out:
8016 hba->pm_op_in_progress = 0;
8808b4e9
SC		 8017 if (ret)
8018 ufshcd_update_reg_hist(&hba->ufs_stats.resume_err, (u32)ret);
57d104c1
SJ		 8019 return ret;
8020}
8021
8022/**
8023 * ufshcd_system_suspend - system suspend routine
8024 * @hba: per adapter instance
57d104c1
SJ		 8025 *
8026 * Check the description of ufshcd_suspend() function for more details.
8027 *
8028 * Returns 0 for success and non-zero for failure
8029 */
8030int ufshcd_system_suspend(struct ufs_hba *hba)
8031{
8032 int ret = 0;
7ff5ab47 8033 ktime_t start = ktime_get();
57d104c1
SJ		 8034
8035 if (!hba || !hba->is_powered)
233b594b 8036 return 0;
57d104c1 8037
0b257734
SJ		 8038 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
8039 hba->curr_dev_pwr_mode) &&
8040 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
8041 hba->uic_link_state))
8042 goto out;
57d104c1 8043
0b257734 8044 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 8045 /*
8046 * UFS device and/or UFS link low power states during runtime
8047 * suspend seems to be different than what is expected during
8048 * system suspend. Hence runtime resume the devic & link and
8049 * let the system suspend low power states to take effect.
8050 * TODO: If resume takes longer time, we might have optimize
8051 * it in future by not resuming everything if possible.
8052 */
8053 ret = ufshcd_runtime_resume(hba);
8054 if (ret)
8055 goto out;
8056 }
8057
8058 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
8059out:
7ff5ab47
SJ		 8060 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
8061 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8062 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 8063 if (!ret)
8064 hba->is_sys_suspended = true;
57d104c1
SJ		 8065 return ret;
8066}
8067EXPORT_SYMBOL(ufshcd_system_suspend);
8068
8069/**
8070 * ufshcd_system_resume - system resume routine
8071 * @hba: per adapter instance
8072 *
8073 * Returns 0 for success and non-zero for failure
8074 */
7a3e97b0 8075
57d104c1
SJ		 8076int ufshcd_system_resume(struct ufs_hba *hba)
8077{
7ff5ab47
SJ		 8078 int ret = 0;
8079 ktime_t start = ktime_get();
8080
e3ce73d6
YG		 8081 if (!hba)
8082 return -EINVAL;
8083
8084 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 8085 /*
8086 * Let the runtime resume take care of resuming
8087 * if runtime suspended.
8088 */
7ff5ab47
SJ		 8089 goto out;
8090 else
8091 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
8092out:
8093 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
8094 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8095 hba->curr_dev_pwr_mode, hba->uic_link_state);
ce9e7bce
SC		 8096 if (!ret)
8097 hba->is_sys_suspended = false;
7ff5ab47 8098 return ret;
7a3e97b0 8099}
57d104c1 8100EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 8101
57d104c1
SJ		 8102/**
8103 * ufshcd_runtime_suspend - runtime suspend routine
8104 * @hba: per adapter instance
8105 *
8106 * Check the description of ufshcd_suspend() function for more details.
8107 *
8108 * Returns 0 for success and non-zero for failure
8109 */
66ec6d59
SRT		 8110int ufshcd_runtime_suspend(struct ufs_hba *hba)
8111{
7ff5ab47
SJ		 8112 int ret = 0;
8113 ktime_t start = ktime_get();
8114
e3ce73d6
YG		 8115 if (!hba)
8116 return -EINVAL;
8117
8118 if (!hba->is_powered)
7ff5ab47
SJ		 8119 goto out;
8120 else
8121 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
8122out:
8123 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
8124 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8125 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8126 return ret;
66ec6d59
SRT		 8127}
8128EXPORT_SYMBOL(ufshcd_runtime_suspend);
8129
57d104c1
SJ		 8130/**
8131 * ufshcd_runtime_resume - runtime resume routine
8132 * @hba: per adapter instance
8133 *
8134 * This function basically brings the UFS device, UniPro link and controller
8135 * to active state. Following operations are done in this function:
8136 *
8137 * 1. Turn on all the controller related clocks
8138 * 2. Bring the UniPro link out of Hibernate state
8139 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
8140 * to active state.
8141 * 4. If auto-bkops is enabled on the device, disable it.
8142 *
8143 * So following would be the possible power state after this function return
8144 * successfully:
8145 * S1: UFS device in Active state with VCC rail ON
8146 * UniPro link in Active state
8147 * All the UFS/UniPro controller clocks are ON
8148 *
8149 * Returns 0 for success and non-zero for failure
8150 */
66ec6d59
SRT		 8151int ufshcd_runtime_resume(struct ufs_hba *hba)
8152{
7ff5ab47
SJ		 8153 int ret = 0;
8154 ktime_t start = ktime_get();
8155
e3ce73d6
YG		 8156 if (!hba)
8157 return -EINVAL;
8158
8159 if (!hba->is_powered)
7ff5ab47
SJ		 8160 goto out;
8161 else
8162 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
8163out:
8164 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
8165 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8166 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8167 return ret;
66ec6d59
SRT		 8168}
8169EXPORT_SYMBOL(ufshcd_runtime_resume);
8170
8171int ufshcd_runtime_idle(struct ufs_hba *hba)
8172{
8173 return 0;
8174}
8175EXPORT_SYMBOL(ufshcd_runtime_idle);
8176
57d104c1
SJ		 8177/**
8178 * ufshcd_shutdown - shutdown routine
8179 * @hba: per adapter instance
8180 *
8181 * This function would power off both UFS device and UFS link.
8182 *
8183 * Returns 0 always to allow force shutdown even in case of errors.
8184 */
8185int ufshcd_shutdown(struct ufs_hba *hba)
8186{
8187 int ret = 0;
8188
f51913ee
SC		 8189 if (!hba->is_powered)
8190 goto out;
8191
57d104c1
SJ		 8192 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8193 goto out;
8194
8195 if (pm_runtime_suspended(hba->dev)) {
8196 ret = ufshcd_runtime_resume(hba);
8197 if (ret)
8198 goto out;
8199 }
8200
8201 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8202out:
8203 if (ret)
8204 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8205 /* allow force shutdown even in case of errors */
8206 return 0;
8207}
8208EXPORT_SYMBOL(ufshcd_shutdown);
8209
7a3e97b0 8210/**
3b1d0580 8211 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 8212 * data structure memory
8aa29f19 8213 * @hba: per adapter instance
7a3e97b0 8214 */
3b1d0580 8215void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 8216{
df032bf2 8217 ufs_bsg_remove(hba);
cbb6813e 8218 ufs_sysfs_remove_nodes(hba->dev);
69a6c269
BVA		 8219 blk_cleanup_queue(hba->tmf_queue);
8220 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360 8221 blk_cleanup_queue(hba->cmd_queue);
cfdf9c91 8222 scsi_remove_host(hba->host);
7a3e97b0 8223 /* disable interrupts */
2fbd009b 8224 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 8225 ufshcd_hba_stop(hba, true);
7a3e97b0 8226
eebcc196 8227 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8228 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 8229 if (ufshcd_is_clkscaling_supported(hba))
8230 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 8231 ufshcd_hba_exit(hba);
3b1d0580
VH		 8232}
8233EXPORT_SYMBOL_GPL(ufshcd_remove);
8234
47555a5c
YG		 8235/**
8236 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
8237 * @hba: pointer to Host Bus Adapter (HBA)
8238 */
8239void ufshcd_dealloc_host(struct ufs_hba *hba)
8240{
8241 scsi_host_put(hba->host);
8242}
8243EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8244
ca3d7bf9
AM		 8245/**
8246 * ufshcd_set_dma_mask - Set dma mask based on the controller
8247 * addressing capability
8248 * @hba: per adapter instance
8249 *
8250 * Returns 0 for success, non-zero for failure
8251 */
8252static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8253{
8254 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8255 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8256 return 0;
8257 }
8258 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8259}
8260
7a3e97b0 8261/**
5c0c28a8 8262 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 8263 * @dev: pointer to device handle
8264 * @hba_handle: driver private handle
7a3e97b0
SY		 8265 * Returns 0 on success, non-zero value on failure
8266 */
5c0c28a8 8267int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 8268{
8269 struct Scsi_Host *host;
8270 struct ufs_hba *hba;
5c0c28a8 8271 int err = 0;
7a3e97b0 8272
3b1d0580
VH		 8273 if (!dev) {
8274 dev_err(dev,
8275 "Invalid memory reference for dev is NULL\n");
8276 err = -ENODEV;
7a3e97b0
SY		 8277 goto out_error;
8278 }
8279
7a3e97b0
SY		 8280 host = scsi_host_alloc(&ufshcd_driver_template,
8281 sizeof(struct ufs_hba));
8282 if (!host) {
3b1d0580 8283 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 8284 err = -ENOMEM;
3b1d0580 8285 goto out_error;
7a3e97b0
SY		 8286 }
8287 hba = shost_priv(host);
7a3e97b0 8288 hba->host = host;
3b1d0580 8289 hba->dev = dev;
5c0c28a8 8290 *hba_handle = hba;
9e1e8a75 8291 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
5c0c28a8 8292
566ec9ad
SM		 8293 INIT_LIST_HEAD(&hba->clk_list_head);
8294
5c0c28a8
SRT		 8295out_error:
8296 return err;
8297}
8298EXPORT_SYMBOL(ufshcd_alloc_host);
8299
69a6c269
BVA		 8300/* This function exists because blk_mq_alloc_tag_set() requires this. */
8301static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
8302 const struct blk_mq_queue_data *qd)
8303{
8304 WARN_ON_ONCE(true);
8305 return BLK_STS_NOTSUPP;
8306}
8307
8308static const struct blk_mq_ops ufshcd_tmf_ops = {
8309 .queue_rq = ufshcd_queue_tmf,
8310};
8311
5c0c28a8
SRT		 8312/**
8313 * ufshcd_init - Driver initialization routine
8314 * @hba: per-adapter instance
8315 * @mmio_base: base register address
8316 * @irq: Interrupt line of device
8317 * Returns 0 on success, non-zero value on failure
8318 */
8319int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8320{
8321 int err;
8322 struct Scsi_Host *host = hba->host;
8323 struct device *dev = hba->dev;
8324
8325 if (!mmio_base) {
8326 dev_err(hba->dev,
8327 "Invalid memory reference for mmio_base is NULL\n");
8328 err = -ENODEV;
8329 goto out_error;
8330 }
8331
3b1d0580
VH		 8332 hba->mmio_base = mmio_base;
8333 hba->irq = irq;
7a3e97b0 8334
aa497613 8335 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 8336 if (err)
8337 goto out_error;
8338
7a3e97b0
SY		 8339 /* Read capabilities registers */
8340 ufshcd_hba_capabilities(hba);
8341
8342 /* Get UFS version supported by the controller */
8343 hba->ufs_version = ufshcd_get_ufs_version(hba);
8344
c01848c6
YG		 8345 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8346 (hba->ufs_version != UFSHCI_VERSION_11) &&
8347 (hba->ufs_version != UFSHCI_VERSION_20) &&
8348 (hba->ufs_version != UFSHCI_VERSION_21))
8349 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8350 hba->ufs_version);
8351
2fbd009b
SJ		 8352 /* Get Interrupt bit mask per version */
8353 hba->intr_mask = ufshcd_get_intr_mask(hba);
8354
ca3d7bf9
AM		 8355 err = ufshcd_set_dma_mask(hba);
8356 if (err) {
8357 dev_err(hba->dev, "set dma mask failed\n");
8358 goto out_disable;
8359 }
8360
7a3e97b0
SY		 8361 /* Allocate memory for host memory space */
8362 err = ufshcd_memory_alloc(hba);
8363 if (err) {
3b1d0580
VH		 8364 dev_err(hba->dev, "Memory allocation failed\n");
8365 goto out_disable;
7a3e97b0
SY		 8366 }
8367
8368 /* Configure LRB */
8369 ufshcd_host_memory_configure(hba);
8370
8371 host->can_queue = hba->nutrs;
8372 host->cmd_per_lun = hba->nutrs;
8373 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8374 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8375 host->max_channel = UFSHCD_MAX_CHANNEL;
8376 host->unique_id = host->host_no;
a851b2bd 8377 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 8378
7eb584db
DR		 8379 hba->max_pwr_info.is_valid = false;
8380
7a3e97b0 8381 /* Initialize work queues */
e8e7f271 8382 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8383 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8384
6ccf44fe
SJ		 8385 /* Initialize UIC command mutex */
8386 mutex_init(&hba->uic_cmd_mutex);
8387
5a0b0cb9
SRT		 8388 /* Initialize mutex for device management commands */
8389 mutex_init(&hba->dev_cmd.lock);
8390
a3cd5ec5
SJ		 8391 init_rwsem(&hba->clk_scaling_lock);
8392
1ab27c9c 8393 ufshcd_init_clk_gating(hba);
199ef13c 8394
eebcc196
VG		 8395 ufshcd_init_clk_scaling(hba);
8396
199ef13c
YG		 8397 /*
8398 * In order to avoid any spurious interrupt immediately after
8399 * registering UFS controller interrupt handler, clear any pending UFS
8400 * interrupt status and disable all the UFS interrupts.
8401 */
8402 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8403 REG_INTERRUPT_STATUS);
8404 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8405 /*
8406 * Make sure that UFS interrupts are disabled and any pending interrupt
8407 * status is cleared before registering UFS interrupt handler.
8408 */
8409 mb();
8410
7a3e97b0 8411 /* IRQ registration */
2953f850 8412 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8413 if (err) {
3b1d0580 8414 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8415 goto exit_gating;
57d104c1
SJ		 8416 } else {
8417 hba->is_irq_enabled = true;
7a3e97b0
SY		 8418 }
8419
3b1d0580 8420 err = scsi_add_host(host, hba->dev);
7a3e97b0 8421 if (err) {
3b1d0580 8422 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8423 goto exit_gating;
7a3e97b0
SY		 8424 }
8425
7252a360
BVA		 8426 hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
8427 if (IS_ERR(hba->cmd_queue)) {
8428 err = PTR_ERR(hba->cmd_queue);
8429 goto out_remove_scsi_host;
8430 }
8431
69a6c269
BVA		 8432 hba->tmf_tag_set = (struct blk_mq_tag_set) {
8433 .nr_hw_queues = 1,
8434 .queue_depth = hba->nutmrs,
8435 .ops = &ufshcd_tmf_ops,
8436 .flags = BLK_MQ_F_NO_SCHED,
8437 };
8438 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
8439 if (err < 0)
8440 goto free_cmd_queue;
8441 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
8442 if (IS_ERR(hba->tmf_queue)) {
8443 err = PTR_ERR(hba->tmf_queue);
8444 goto free_tmf_tag_set;
8445 }
8446
d8d9f793
BA		 8447 /* Reset the attached device */
8448 ufshcd_vops_device_reset(hba);
8449
6ccf44fe
SJ		 8450 /* Host controller enable */
8451 err = ufshcd_hba_enable(hba);
7a3e97b0 8452 if (err) {
6ccf44fe 8453 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 8454 ufshcd_print_host_regs(hba);
6ba65588 8455 ufshcd_print_host_state(hba);
69a6c269 8456 goto free_tmf_queue;
7a3e97b0 8457 }
6ccf44fe 8458
0c8f7586
SJ		 8459 /*
8460 * Set the default power management level for runtime and system PM.
8461 * Default power saving mode is to keep UFS link in Hibern8 state
8462 * and UFS device in sleep state.
8463 */
8464 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8465 UFS_SLEEP_PWR_MODE,
8466 UIC_LINK_HIBERN8_STATE);
8467 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8468 UFS_SLEEP_PWR_MODE,
8469 UIC_LINK_HIBERN8_STATE);
8470
ad448378 8471 /* Set the default auto-hiberate idle timer value to 150 ms */
f571b377 8472 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
ad448378
AH		 8473 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8474 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8475 }
8476
62694735
SRT		 8477 /* Hold auto suspend until async scan completes */
8478 pm_runtime_get_sync(dev);
38135535 8479 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 8480 /*
7caf489b
SJ		 8481 * We are assuming that device wasn't put in sleep/power-down
8482 * state exclusively during the boot stage before kernel.
8483 * This assumption helps avoid doing link startup twice during
8484 * ufshcd_probe_hba().
57d104c1 8485 */
7caf489b 8486 ufshcd_set_ufs_dev_active(hba);
57d104c1 8487
6ccf44fe 8488 async_schedule(ufshcd_async_scan, hba);
cbb6813e 8489 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 8490
7a3e97b0
SY		 8491 return 0;
8492
69a6c269
BVA		 8493free_tmf_queue:
8494 blk_cleanup_queue(hba->tmf_queue);
8495free_tmf_tag_set:
8496 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360
BVA		 8497free_cmd_queue:
8498 blk_cleanup_queue(hba->cmd_queue);
3b1d0580
VH		 8499out_remove_scsi_host:
8500 scsi_remove_host(hba->host);
1ab27c9c 8501exit_gating:
eebcc196 8502 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8503 ufshcd_exit_clk_gating(hba);
3b1d0580 8504out_disable:
57d104c1 8505 hba->is_irq_enabled = false;
aa497613 8506 ufshcd_hba_exit(hba);
3b1d0580
VH		 8507out_error:
8508 return err;
8509}
8510EXPORT_SYMBOL_GPL(ufshcd_init);
8511
3b1d0580
VH		 8512MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8513MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8514MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8515MODULE_LICENSE("GPL");
8516MODULE_VERSION(UFSHCD_DRIVER_VERSION);
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