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be2iscsi: Fix memory leak in mgmt_set_ip()
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / ufs / ufshcd.c
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7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
7a3e97b0 6 *
3b1d0580
VH		 7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
3b1d0580
VH		 15 * See the COPYING file in the top-level directory or visit
16 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
3b1d0580
VH		 23 * This program is provided "AS IS" and "WITH ALL FAULTS" and
24 * without warranty of any kind. You are solely responsible for
25 * determining the appropriateness of using and distributing
26 * the program and assume all risks associated with your exercise
27 * of rights with respect to the program, including but not limited
28 * to infringement of third party rights, the risks and costs of
29 * program errors, damage to or loss of data, programs or equipment,
30 * and unavailability or interruption of operations. Under no
31 * circumstances will the contributor of this Program be liable for
32 * any damages of any kind arising from your use or distribution of
33 * this program.
7a3e97b0
SY		 34 */
35
6ccf44fe
SJ		 36#include <linux/async.h>
37
e0eca63e 38#include "ufshcd.h"
53b3d9c3 39#include "unipro.h"
7a3e97b0 40
2fbd009b
SJ		 41#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
42 UTP_TASK_REQ_COMPL |\
53b3d9c3 43 UIC_POWER_MODE |\
2fbd009b 44 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 45/* UIC command timeout, unit: ms */
46#define UIC_CMD_TIMEOUT 500
2fbd009b 47
5a0b0cb9
SRT		 48/* NOP OUT retries waiting for NOP IN response */
49#define NOP_OUT_RETRIES 10
50/* Timeout after 30 msecs if NOP OUT hangs without response */
51#define NOP_OUT_TIMEOUT 30 /* msecs */
52
68078d5c
DR		 53/* Query request retries */
54#define QUERY_REQ_RETRIES 10
55/* Query request timeout */
56#define QUERY_REQ_TIMEOUT 30 /* msec */
57
e2933132
SRT		 58/* Task management command timeout */
59#define TM_CMD_TIMEOUT 100 /* msecs */
60
68078d5c
DR		 61/* Expose the flag value from utp_upiu_query.value */
62#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
63
7d568652
SJ		 64/* Interrupt aggregation default timeout, unit: 40us */
65#define INT_AGGR_DEF_TO 0x02
66
7a3e97b0
SY		 67enum {
68 UFSHCD_MAX_CHANNEL = 0,
69 UFSHCD_MAX_ID = 1,
70 UFSHCD_MAX_LUNS = 8,
71 UFSHCD_CMD_PER_LUN = 32,
72 UFSHCD_CAN_QUEUE = 32,
73};
74
75/* UFSHCD states */
76enum {
7a3e97b0
SY		 77 UFSHCD_STATE_RESET,
78 UFSHCD_STATE_ERROR,
3441da7d
SRT		 79 UFSHCD_STATE_OPERATIONAL,
80};
81
82/* UFSHCD error handling flags */
83enum {
84 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 85};
86
e8e7f271
SRT		 87/* UFSHCD UIC layer error flags */
88enum {
89 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
90 UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
91 UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
92 UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
93};
94
7a3e97b0
SY		 95/* Interrupt configuration options */
96enum {
97 UFSHCD_INT_DISABLE,
98 UFSHCD_INT_ENABLE,
99 UFSHCD_INT_CLEAR,
100};
101
3441da7d
SRT		 102#define ufshcd_set_eh_in_progress(h) \
103 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
104#define ufshcd_eh_in_progress(h) \
105 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
106#define ufshcd_clear_eh_in_progress(h) \
107 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
108
109static void ufshcd_tmc_handler(struct ufs_hba *hba);
110static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 111static int ufshcd_reset_and_restore(struct ufs_hba *hba);
112static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
3441da7d 113
5a0b0cb9
SRT		 114/*
115 * ufshcd_wait_for_register - wait for register value to change
116 * @hba - per-adapter interface
117 * @reg - mmio register offset
118 * @mask - mask to apply to read register value
119 * @val - wait condition
120 * @interval_us - polling interval in microsecs
121 * @timeout_ms - timeout in millisecs
122 *
123 * Returns -ETIMEDOUT on error, zero on success
124 */
125static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
126 u32 val, unsigned long interval_us, unsigned long timeout_ms)
127{
128 int err = 0;
129 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
130
131 /* ignore bits that we don't intend to wait on */
132 val = val & mask;
133
134 while ((ufshcd_readl(hba, reg) & mask) != val) {
135 /* wakeup within 50us of expiry */
136 usleep_range(interval_us, interval_us + 50);
137
138 if (time_after(jiffies, timeout)) {
139 if ((ufshcd_readl(hba, reg) & mask) != val)
140 err = -ETIMEDOUT;
141 break;
142 }
143 }
144
145 return err;
146}
147
2fbd009b
SJ		 148/**
149 * ufshcd_get_intr_mask - Get the interrupt bit mask
150 * @hba - Pointer to adapter instance
151 *
152 * Returns interrupt bit mask per version
153 */
154static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
155{
156 if (hba->ufs_version == UFSHCI_VERSION_10)
157 return INTERRUPT_MASK_ALL_VER_10;
158 else
159 return INTERRUPT_MASK_ALL_VER_11;
160}
161
7a3e97b0
SY		 162/**
163 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
164 * @hba - Pointer to adapter instance
165 *
166 * Returns UFSHCI version supported by the controller
167 */
168static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
169{
b873a275 170 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 171}
172
173/**
174 * ufshcd_is_device_present - Check if any device connected to
175 * the host controller
176 * @reg_hcs - host controller status register value
177 *
73ec513a 178 * Returns 1 if device present, 0 if no device detected
7a3e97b0
SY		 179 */
180static inline int ufshcd_is_device_present(u32 reg_hcs)
181{
73ec513a 182 return (DEVICE_PRESENT & reg_hcs) ? 1 : 0;
7a3e97b0
SY		 183}
184
185/**
186 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
187 * @lrb: pointer to local command reference block
188 *
189 * This function is used to get the OCS field from UTRD
190 * Returns the OCS field in the UTRD
191 */
192static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
193{
e8c8e82a 194 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 195}
196
197/**
198 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
199 * @task_req_descp: pointer to utp_task_req_desc structure
200 *
201 * This function is used to get the OCS field from UTMRD
202 * Returns the OCS field in the UTMRD
203 */
204static inline int
205ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
206{
e8c8e82a 207 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 208}
209
210/**
211 * ufshcd_get_tm_free_slot - get a free slot for task management request
212 * @hba: per adapter instance
e2933132 213 * @free_slot: pointer to variable with available slot value
7a3e97b0 214 *
e2933132
SRT		 215 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
216 * Returns 0 if free slot is not available, else return 1 with tag value
217 * in @free_slot.
7a3e97b0 218 */
e2933132 219static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 220{
e2933132
SRT		 221 int tag;
222 bool ret = false;
223
224 if (!free_slot)
225 goto out;
226
227 do {
228 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
229 if (tag >= hba->nutmrs)
230 goto out;
231 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
232
233 *free_slot = tag;
234 ret = true;
235out:
236 return ret;
237}
238
239static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
240{
241 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 242}
243
244/**
245 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
246 * @hba: per adapter instance
247 * @pos: position of the bit to be cleared
248 */
249static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
250{
b873a275 251 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 252}
253
254/**
255 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
256 * @reg: Register value of host controller status
257 *
258 * Returns integer, 0 on Success and positive value if failed
259 */
260static inline int ufshcd_get_lists_status(u32 reg)
261{
262 /*
263 * The mask 0xFF is for the following HCS register bits
264 * Bit Description
265 * 0 Device Present
266 * 1 UTRLRDY
267 * 2 UTMRLRDY
268 * 3 UCRDY
269 * 4 HEI
270 * 5 DEI
271 * 6-7 reserved
272 */
273 return (((reg) & (0xFF)) >> 1) ^ (0x07);
274}
275
276/**
277 * ufshcd_get_uic_cmd_result - Get the UIC command result
278 * @hba: Pointer to adapter instance
279 *
280 * This function gets the result of UIC command completion
281 * Returns 0 on success, non zero value on error
282 */
283static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
284{
b873a275 285 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 286 MASK_UIC_COMMAND_RESULT;
287}
288
12b4fdb4
SJ		 289/**
290 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
291 * @hba: Pointer to adapter instance
292 *
293 * This function gets UIC command argument3
294 * Returns 0 on success, non zero value on error
295 */
296static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
297{
298 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
299}
300
7a3e97b0 301/**
5a0b0cb9 302 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 303 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 304 */
305static inline int
5a0b0cb9 306ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 307{
5a0b0cb9 308 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 309}
310
311/**
312 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
313 * @ucd_rsp_ptr: pointer to response UPIU
314 *
315 * This function gets the response status and scsi_status from response UPIU
316 * Returns the response result code.
317 */
318static inline int
319ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
320{
321 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
322}
323
1c2623c5
SJ		 324/*
325 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
326 * from response UPIU
327 * @ucd_rsp_ptr: pointer to response UPIU
328 *
329 * Return the data segment length.
330 */
331static inline unsigned int
332ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
333{
334 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
335 MASK_RSP_UPIU_DATA_SEG_LEN;
336}
337
66ec6d59
SRT		 338/**
339 * ufshcd_is_exception_event - Check if the device raised an exception event
340 * @ucd_rsp_ptr: pointer to response UPIU
341 *
342 * The function checks if the device raised an exception event indicated in
343 * the Device Information field of response UPIU.
344 *
345 * Returns true if exception is raised, false otherwise.
346 */
347static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
348{
349 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
350 MASK_RSP_EXCEPTION_EVENT ? true : false;
351}
352
7a3e97b0 353/**
7d568652 354 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 355 * @hba: per adapter instance
7a3e97b0
SY		 356 */
357static inline void
7d568652 358ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 359{
7d568652
SJ		 360 ufshcd_writel(hba, INT_AGGR_ENABLE |
361 INT_AGGR_COUNTER_AND_TIMER_RESET,
362 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
363}
364
365/**
366 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
367 * @hba: per adapter instance
368 * @cnt: Interrupt aggregation counter threshold
369 * @tmout: Interrupt aggregation timeout value
370 */
371static inline void
372ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
373{
374 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
375 INT_AGGR_COUNTER_THLD_VAL(cnt) |
376 INT_AGGR_TIMEOUT_VAL(tmout),
377 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 378}
379
380/**
381 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
382 * When run-stop registers are set to 1, it indicates the
383 * host controller that it can process the requests
384 * @hba: per adapter instance
385 */
386static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
387{
b873a275
SJ		 388 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
389 REG_UTP_TASK_REQ_LIST_RUN_STOP);
390 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
391 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 392}
393
7a3e97b0
SY		 394/**
395 * ufshcd_hba_start - Start controller initialization sequence
396 * @hba: per adapter instance
397 */
398static inline void ufshcd_hba_start(struct ufs_hba *hba)
399{
b873a275 400 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 401}
402
403/**
404 * ufshcd_is_hba_active - Get controller state
405 * @hba: per adapter instance
406 *
407 * Returns zero if controller is active, 1 otherwise
408 */
409static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
410{
b873a275 411 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 412}
413
414/**
415 * ufshcd_send_command - Send SCSI or device management commands
416 * @hba: per adapter instance
417 * @task_tag: Task tag of the command
418 */
419static inline
420void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
421{
422 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 423 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 424}
425
426/**
427 * ufshcd_copy_sense_data - Copy sense data in case of check condition
428 * @lrb - pointer to local reference block
429 */
430static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
431{
432 int len;
1c2623c5
SJ		 433 if (lrbp->sense_buffer &&
434 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
5a0b0cb9 435 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
7a3e97b0 436 memcpy(lrbp->sense_buffer,
5a0b0cb9 437 lrbp->ucd_rsp_ptr->sr.sense_data,
7a3e97b0
SY		 438 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
439 }
440}
441
68078d5c
DR		 442/**
443 * ufshcd_copy_query_response() - Copy the Query Response and the data
444 * descriptor
445 * @hba: per adapter instance
446 * @lrb - pointer to local reference block
447 */
448static
449void ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
450{
451 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
452
453 /* Get the UPIU response */
454 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
455 UPIU_RSP_CODE_OFFSET;
456
457 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c
DR		 458
459
460 /* Get the descriptor */
461 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
462 u8 *descp = (u8 *)&lrbp->ucd_rsp_ptr +
463 GENERAL_UPIU_REQUEST_SIZE;
464 u16 len;
465
466 /* data segment length */
467 len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
468 MASK_QUERY_DATA_SEG_LEN;
469
470 memcpy(hba->dev_cmd.query.descriptor, descp,
471 min_t(u16, len, QUERY_DESC_MAX_SIZE));
472 }
473}
474
7a3e97b0
SY		 475/**
476 * ufshcd_hba_capabilities - Read controller capabilities
477 * @hba: per adapter instance
478 */
479static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
480{
b873a275 481 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 482
483 /* nutrs and nutmrs are 0 based values */
484 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
485 hba->nutmrs =
486 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
487}
488
489/**
6ccf44fe
SJ		 490 * ufshcd_ready_for_uic_cmd - Check if controller is ready
491 * to accept UIC commands
7a3e97b0 492 * @hba: per adapter instance
6ccf44fe
SJ		 493 * Return true on success, else false
494 */
495static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
496{
497 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
498 return true;
499 else
500 return false;
501}
502
53b3d9c3
SJ		 503/**
504 * ufshcd_get_upmcrs - Get the power mode change request status
505 * @hba: Pointer to adapter instance
506 *
507 * This function gets the UPMCRS field of HCS register
508 * Returns value of UPMCRS field
509 */
510static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
511{
512 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
513}
514
6ccf44fe
SJ		 515/**
516 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
517 * @hba: per adapter instance
518 * @uic_cmd: UIC command
519 *
520 * Mutex must be held.
7a3e97b0
SY		 521 */
522static inline void
6ccf44fe 523ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 524{
6ccf44fe
SJ		 525 WARN_ON(hba->active_uic_cmd);
526
527 hba->active_uic_cmd = uic_cmd;
528
7a3e97b0 529 /* Write Args */
6ccf44fe
SJ		 530 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
531 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
532 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 533
534 /* Write UIC Cmd */
6ccf44fe 535 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 536 REG_UIC_COMMAND);
7a3e97b0
SY		 537}
538
6ccf44fe
SJ		 539/**
540 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
541 * @hba: per adapter instance
542 * @uic_command: UIC command
543 *
544 * Must be called with mutex held.
545 * Returns 0 only if success.
546 */
547static int
548ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
549{
550 int ret;
551 unsigned long flags;
552
553 if (wait_for_completion_timeout(&uic_cmd->done,
554 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
555 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
556 else
557 ret = -ETIMEDOUT;
558
559 spin_lock_irqsave(hba->host->host_lock, flags);
560 hba->active_uic_cmd = NULL;
561 spin_unlock_irqrestore(hba->host->host_lock, flags);
562
563 return ret;
564}
565
566/**
567 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
568 * @hba: per adapter instance
569 * @uic_cmd: UIC command
570 *
571 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
572 * with mutex held.
573 * Returns 0 only if success.
574 */
575static int
576__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
577{
578 int ret;
579 unsigned long flags;
580
581 if (!ufshcd_ready_for_uic_cmd(hba)) {
582 dev_err(hba->dev,
583 "Controller not ready to accept UIC commands\n");
584 return -EIO;
585 }
586
587 init_completion(&uic_cmd->done);
588
589 spin_lock_irqsave(hba->host->host_lock, flags);
590 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
591 spin_unlock_irqrestore(hba->host->host_lock, flags);
592
593 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
594
595 return ret;
596}
597
598/**
599 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
600 * @hba: per adapter instance
601 * @uic_cmd: UIC command
602 *
603 * Returns 0 only if success.
604 */
605static int
606ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
607{
608 int ret;
609
610 mutex_lock(&hba->uic_cmd_mutex);
611 ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
612 mutex_unlock(&hba->uic_cmd_mutex);
613
614 return ret;
615}
616
7a3e97b0
SY		 617/**
618 * ufshcd_map_sg - Map scatter-gather list to prdt
619 * @lrbp - pointer to local reference block
620 *
621 * Returns 0 in case of success, non-zero value in case of failure
622 */
623static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
624{
625 struct ufshcd_sg_entry *prd_table;
626 struct scatterlist *sg;
627 struct scsi_cmnd *cmd;
628 int sg_segments;
629 int i;
630
631 cmd = lrbp->cmd;
632 sg_segments = scsi_dma_map(cmd);
633 if (sg_segments < 0)
634 return sg_segments;
635
636 if (sg_segments) {
637 lrbp->utr_descriptor_ptr->prd_table_length =
638 cpu_to_le16((u16) (sg_segments));
639
640 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
641
642 scsi_for_each_sg(cmd, sg, sg_segments, i) {
643 prd_table[i].size =
644 cpu_to_le32(((u32) sg_dma_len(sg))-1);
645 prd_table[i].base_addr =
646 cpu_to_le32(lower_32_bits(sg->dma_address));
647 prd_table[i].upper_addr =
648 cpu_to_le32(upper_32_bits(sg->dma_address));
649 }
650 } else {
651 lrbp->utr_descriptor_ptr->prd_table_length = 0;
652 }
653
654 return 0;
655}
656
657/**
2fbd009b 658 * ufshcd_enable_intr - enable interrupts
7a3e97b0 659 * @hba: per adapter instance
2fbd009b 660 * @intrs: interrupt bits
7a3e97b0 661 */
2fbd009b 662static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 663{
2fbd009b
SJ		 664 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
665
666 if (hba->ufs_version == UFSHCI_VERSION_10) {
667 u32 rw;
668 rw = set & INTERRUPT_MASK_RW_VER_10;
669 set = rw | ((set ^ intrs) & intrs);
670 } else {
671 set |= intrs;
672 }
673
674 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
675}
676
677/**
678 * ufshcd_disable_intr - disable interrupts
679 * @hba: per adapter instance
680 * @intrs: interrupt bits
681 */
682static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
683{
684 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
685
686 if (hba->ufs_version == UFSHCI_VERSION_10) {
687 u32 rw;
688 rw = (set & INTERRUPT_MASK_RW_VER_10) &
689 ~(intrs & INTERRUPT_MASK_RW_VER_10);
690 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
691
692 } else {
693 set &= ~intrs;
7a3e97b0 694 }
2fbd009b
SJ		 695
696 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 697}
698
5a0b0cb9
SRT		 699/**
700 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
701 * descriptor according to request
702 * @lrbp: pointer to local reference block
703 * @upiu_flags: flags required in the header
704 * @cmd_dir: requests data direction
705 */
706static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
707 u32 *upiu_flags, enum dma_data_direction cmd_dir)
708{
709 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
710 u32 data_direction;
711 u32 dword_0;
712
713 if (cmd_dir == DMA_FROM_DEVICE) {
714 data_direction = UTP_DEVICE_TO_HOST;
715 *upiu_flags = UPIU_CMD_FLAGS_READ;
716 } else if (cmd_dir == DMA_TO_DEVICE) {
717 data_direction = UTP_HOST_TO_DEVICE;
718 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
719 } else {
720 data_direction = UTP_NO_DATA_TRANSFER;
721 *upiu_flags = UPIU_CMD_FLAGS_NONE;
722 }
723
724 dword_0 = data_direction | (lrbp->command_type
725 << UPIU_COMMAND_TYPE_OFFSET);
726 if (lrbp->intr_cmd)
727 dword_0 |= UTP_REQ_DESC_INT_CMD;
728
729 /* Transfer request descriptor header fields */
730 req_desc->header.dword_0 = cpu_to_le32(dword_0);
731
732 /*
733 * assigning invalid value for command status. Controller
734 * updates OCS on command completion, with the command
735 * status
736 */
737 req_desc->header.dword_2 =
738 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
739}
740
741/**
742 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
743 * for scsi commands
744 * @lrbp - local reference block pointer
745 * @upiu_flags - flags
746 */
747static
748void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
749{
750 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
751
752 /* command descriptor fields */
753 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
754 UPIU_TRANSACTION_COMMAND, upiu_flags,
755 lrbp->lun, lrbp->task_tag);
756 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
757 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
758
759 /* Total EHS length and Data segment length will be zero */
760 ucd_req_ptr->header.dword_2 = 0;
761
762 ucd_req_ptr->sc.exp_data_transfer_len =
763 cpu_to_be32(lrbp->cmd->sdb.length);
764
765 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
766 (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
767}
768
68078d5c
DR		 769/**
770 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
771 * for query requsts
772 * @hba: UFS hba
773 * @lrbp: local reference block pointer
774 * @upiu_flags: flags
775 */
776static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
777 struct ufshcd_lrb *lrbp, u32 upiu_flags)
778{
779 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
780 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 781 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 782 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
783
784 /* Query request header */
785 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
786 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
787 lrbp->lun, lrbp->task_tag);
788 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
789 0, query->request.query_func, 0, 0);
790
791 /* Data segment length */
792 ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
793 0, 0, len >> 8, (u8)len);
794
795 /* Copy the Query Request buffer as is */
796 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
797 QUERY_OSF_SIZE);
68078d5c
DR		 798
799 /* Copy the Descriptor */
800 if ((len > 0) && (query->request.upiu_req.opcode ==
801 UPIU_QUERY_OPCODE_WRITE_DESC)) {
802 memcpy(descp, query->descriptor,
803 min_t(u16, len, QUERY_DESC_MAX_SIZE));
804 }
805}
806
5a0b0cb9
SRT		 807static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
808{
809 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
810
811 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
812
813 /* command descriptor fields */
814 ucd_req_ptr->header.dword_0 =
815 UPIU_HEADER_DWORD(
816 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
817}
818
7a3e97b0
SY		 819/**
820 * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
5a0b0cb9 821 * @hba - per adapter instance
7a3e97b0
SY		 822 * @lrb - pointer to local reference block
823 */
5a0b0cb9 824static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 825{
7a3e97b0 826 u32 upiu_flags;
5a0b0cb9 827 int ret = 0;
7a3e97b0
SY		 828
829 switch (lrbp->command_type) {
830 case UTP_CMD_TYPE_SCSI:
5a0b0cb9
SRT		 831 if (likely(lrbp->cmd)) {
832 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
833 lrbp->cmd->sc_data_direction);
834 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
7a3e97b0 835 } else {
5a0b0cb9 836 ret = -EINVAL;
7a3e97b0 837 }
7a3e97b0
SY		 838 break;
839 case UTP_CMD_TYPE_DEV_MANAGE:
5a0b0cb9 840 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
68078d5c
DR		 841 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
842 ufshcd_prepare_utp_query_req_upiu(
843 hba, lrbp, upiu_flags);
844 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
5a0b0cb9
SRT		 845 ufshcd_prepare_utp_nop_upiu(lrbp);
846 else
847 ret = -EINVAL;
7a3e97b0
SY		 848 break;
849 case UTP_CMD_TYPE_UFS:
850 /* For UFS native command implementation */
5a0b0cb9
SRT		 851 ret = -ENOTSUPP;
852 dev_err(hba->dev, "%s: UFS native command are not supported\n",
853 __func__);
854 break;
855 default:
856 ret = -ENOTSUPP;
857 dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
858 __func__, lrbp->command_type);
7a3e97b0
SY		 859 break;
860 } /* end of switch */
5a0b0cb9
SRT		 861
862 return ret;
7a3e97b0
SY		 863}
864
865/**
866 * ufshcd_queuecommand - main entry point for SCSI requests
867 * @cmd: command from SCSI Midlayer
868 * @done: call back function
869 *
870 * Returns 0 for success, non-zero in case of failure
871 */
872static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
873{
874 struct ufshcd_lrb *lrbp;
875 struct ufs_hba *hba;
876 unsigned long flags;
877 int tag;
878 int err = 0;
879
880 hba = shost_priv(host);
881
882 tag = cmd->request->tag;
883
3441da7d
SRT		 884 spin_lock_irqsave(hba->host->host_lock, flags);
885 switch (hba->ufshcd_state) {
886 case UFSHCD_STATE_OPERATIONAL:
887 break;
888 case UFSHCD_STATE_RESET:
7a3e97b0 889 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 890 goto out_unlock;
891 case UFSHCD_STATE_ERROR:
892 set_host_byte(cmd, DID_ERROR);
893 cmd->scsi_done(cmd);
894 goto out_unlock;
895 default:
896 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
897 __func__, hba->ufshcd_state);
898 set_host_byte(cmd, DID_BAD_TARGET);
899 cmd->scsi_done(cmd);
900 goto out_unlock;
7a3e97b0 901 }
3441da7d 902 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 903
5a0b0cb9
SRT		 904 /* acquire the tag to make sure device cmds don't use it */
905 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
906 /*
907 * Dev manage command in progress, requeue the command.
908 * Requeuing the command helps in cases where the request *may*
909 * find different tag instead of waiting for dev manage command
910 * completion.
911 */
912 err = SCSI_MLQUEUE_HOST_BUSY;
913 goto out;
914 }
915
7a3e97b0
SY		 916 lrbp = &hba->lrb[tag];
917
5a0b0cb9 918 WARN_ON(lrbp->cmd);
7a3e97b0
SY		 919 lrbp->cmd = cmd;
920 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
921 lrbp->sense_buffer = cmd->sense_buffer;
922 lrbp->task_tag = tag;
923 lrbp->lun = cmd->device->lun;
5a0b0cb9 924 lrbp->intr_cmd = false;
7a3e97b0
SY		 925 lrbp->command_type = UTP_CMD_TYPE_SCSI;
926
927 /* form UPIU before issuing the command */
5a0b0cb9 928 ufshcd_compose_upiu(hba, lrbp);
7a3e97b0 929 err = ufshcd_map_sg(lrbp);
5a0b0cb9
SRT		 930 if (err) {
931 lrbp->cmd = NULL;
932 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 933 goto out;
5a0b0cb9 934 }
7a3e97b0
SY		 935
936 /* issue command to the controller */
937 spin_lock_irqsave(hba->host->host_lock, flags);
938 ufshcd_send_command(hba, tag);
3441da7d 939out_unlock:
7a3e97b0
SY		 940 spin_unlock_irqrestore(hba->host->host_lock, flags);
941out:
942 return err;
943}
944
5a0b0cb9
SRT		 945static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
946 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
947{
948 lrbp->cmd = NULL;
949 lrbp->sense_bufflen = 0;
950 lrbp->sense_buffer = NULL;
951 lrbp->task_tag = tag;
952 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
953 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
954 lrbp->intr_cmd = true; /* No interrupt aggregation */
955 hba->dev_cmd.type = cmd_type;
956
957 return ufshcd_compose_upiu(hba, lrbp);
958}
959
960static int
961ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
962{
963 int err = 0;
964 unsigned long flags;
965 u32 mask = 1 << tag;
966
967 /* clear outstanding transaction before retry */
968 spin_lock_irqsave(hba->host->host_lock, flags);
969 ufshcd_utrl_clear(hba, tag);
970 spin_unlock_irqrestore(hba->host->host_lock, flags);
971
972 /*
973 * wait for for h/w to clear corresponding bit in door-bell.
974 * max. wait is 1 sec.
975 */
976 err = ufshcd_wait_for_register(hba,
977 REG_UTP_TRANSFER_REQ_DOOR_BELL,
978 mask, ~mask, 1000, 1000);
979
980 return err;
981}
982
983/**
984 * ufshcd_dev_cmd_completion() - handles device management command responses
985 * @hba: per adapter instance
986 * @lrbp: pointer to local reference block
987 */
988static int
989ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
990{
991 int resp;
992 int err = 0;
993
994 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
995
996 switch (resp) {
997 case UPIU_TRANSACTION_NOP_IN:
998 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
999 err = -EINVAL;
1000 dev_err(hba->dev, "%s: unexpected response %x\n",
1001 __func__, resp);
1002 }
1003 break;
68078d5c
DR		 1004 case UPIU_TRANSACTION_QUERY_RSP:
1005 ufshcd_copy_query_response(hba, lrbp);
1006 break;
5a0b0cb9
SRT		 1007 case UPIU_TRANSACTION_REJECT_UPIU:
1008 /* TODO: handle Reject UPIU Response */
1009 err = -EPERM;
1010 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1011 __func__);
1012 break;
1013 default:
1014 err = -EINVAL;
1015 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1016 __func__, resp);
1017 break;
1018 }
1019
1020 return err;
1021}
1022
1023static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1024 struct ufshcd_lrb *lrbp, int max_timeout)
1025{
1026 int err = 0;
1027 unsigned long time_left;
1028 unsigned long flags;
1029
1030 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1031 msecs_to_jiffies(max_timeout));
1032
1033 spin_lock_irqsave(hba->host->host_lock, flags);
1034 hba->dev_cmd.complete = NULL;
1035 if (likely(time_left)) {
1036 err = ufshcd_get_tr_ocs(lrbp);
1037 if (!err)
1038 err = ufshcd_dev_cmd_completion(hba, lrbp);
1039 }
1040 spin_unlock_irqrestore(hba->host->host_lock, flags);
1041
1042 if (!time_left) {
1043 err = -ETIMEDOUT;
1044 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
1045 /* sucessfully cleared the command, retry if needed */
1046 err = -EAGAIN;
1047 }
1048
1049 return err;
1050}
1051
1052/**
1053 * ufshcd_get_dev_cmd_tag - Get device management command tag
1054 * @hba: per-adapter instance
1055 * @tag: pointer to variable with available slot value
1056 *
1057 * Get a free slot and lock it until device management command
1058 * completes.
1059 *
1060 * Returns false if free slot is unavailable for locking, else
1061 * return true with tag value in @tag.
1062 */
1063static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1064{
1065 int tag;
1066 bool ret = false;
1067 unsigned long tmp;
1068
1069 if (!tag_out)
1070 goto out;
1071
1072 do {
1073 tmp = ~hba->lrb_in_use;
1074 tag = find_last_bit(&tmp, hba->nutrs);
1075 if (tag >= hba->nutrs)
1076 goto out;
1077 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1078
1079 *tag_out = tag;
1080 ret = true;
1081out:
1082 return ret;
1083}
1084
1085static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1086{
1087 clear_bit_unlock(tag, &hba->lrb_in_use);
1088}
1089
1090/**
1091 * ufshcd_exec_dev_cmd - API for sending device management requests
1092 * @hba - UFS hba
1093 * @cmd_type - specifies the type (NOP, Query...)
1094 * @timeout - time in seconds
1095 *
68078d5c
DR		 1096 * NOTE: Since there is only one available tag for device management commands,
1097 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1098 */
1099static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1100 enum dev_cmd_type cmd_type, int timeout)
1101{
1102 struct ufshcd_lrb *lrbp;
1103 int err;
1104 int tag;
1105 struct completion wait;
1106 unsigned long flags;
1107
1108 /*
1109 * Get free slot, sleep if slots are unavailable.
1110 * Even though we use wait_event() which sleeps indefinitely,
1111 * the maximum wait time is bounded by SCSI request timeout.
1112 */
1113 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1114
1115 init_completion(&wait);
1116 lrbp = &hba->lrb[tag];
1117 WARN_ON(lrbp->cmd);
1118 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1119 if (unlikely(err))
1120 goto out_put_tag;
1121
1122 hba->dev_cmd.complete = &wait;
1123
1124 spin_lock_irqsave(hba->host->host_lock, flags);
1125 ufshcd_send_command(hba, tag);
1126 spin_unlock_irqrestore(hba->host->host_lock, flags);
1127
1128 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1129
1130out_put_tag:
1131 ufshcd_put_dev_cmd_tag(hba, tag);
1132 wake_up(&hba->dev_cmd.tag_wq);
1133 return err;
1134}
1135
68078d5c
DR		 1136/**
1137 * ufshcd_query_flag() - API function for sending flag query requests
1138 * hba: per-adapter instance
1139 * query_opcode: flag query to perform
1140 * idn: flag idn to access
1141 * flag_res: the flag value after the query request completes
1142 *
1143 * Returns 0 for success, non-zero in case of failure
1144 */
1145static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1146 enum flag_idn idn, bool *flag_res)
1147{
1148 struct ufs_query_req *request;
1149 struct ufs_query_res *response;
1150 int err;
1151
1152 BUG_ON(!hba);
1153
1154 mutex_lock(&hba->dev_cmd.lock);
1155 request = &hba->dev_cmd.query.request;
1156 response = &hba->dev_cmd.query.response;
1157 memset(request, 0, sizeof(struct ufs_query_req));
1158 memset(response, 0, sizeof(struct ufs_query_res));
1159
1160 switch (opcode) {
1161 case UPIU_QUERY_OPCODE_SET_FLAG:
1162 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1163 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1164 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1165 break;
1166 case UPIU_QUERY_OPCODE_READ_FLAG:
1167 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1168 if (!flag_res) {
1169 /* No dummy reads */
1170 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1171 __func__);
1172 err = -EINVAL;
1173 goto out_unlock;
1174 }
1175 break;
1176 default:
1177 dev_err(hba->dev,
1178 "%s: Expected query flag opcode but got = %d\n",
1179 __func__, opcode);
1180 err = -EINVAL;
1181 goto out_unlock;
1182 }
1183 request->upiu_req.opcode = opcode;
1184 request->upiu_req.idn = idn;
1185
1186 /* Send query request */
1187 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY,
1188 QUERY_REQ_TIMEOUT);
1189
1190 if (err) {
1191 dev_err(hba->dev,
1192 "%s: Sending flag query for idn %d failed, err = %d\n",
1193 __func__, idn, err);
1194 goto out_unlock;
1195 }
1196
1197 if (flag_res)
e8c8e82a 1198 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1199 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1200
1201out_unlock:
1202 mutex_unlock(&hba->dev_cmd.lock);
1203 return err;
1204}
1205
66ec6d59
SRT		 1206/**
1207 * ufshcd_query_attr - API function for sending attribute requests
1208 * hba: per-adapter instance
1209 * opcode: attribute opcode
1210 * idn: attribute idn to access
1211 * index: index field
1212 * selector: selector field
1213 * attr_val: the attribute value after the query request completes
1214 *
1215 * Returns 0 for success, non-zero in case of failure
1216*/
bdbe5d2f 1217static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1218 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1219{
1220 struct ufs_query_req *request;
1221 struct ufs_query_res *response;
1222 int err;
1223
1224 BUG_ON(!hba);
1225
1226 if (!attr_val) {
1227 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1228 __func__, opcode);
1229 err = -EINVAL;
1230 goto out;
1231 }
1232
1233 mutex_lock(&hba->dev_cmd.lock);
1234 request = &hba->dev_cmd.query.request;
1235 response = &hba->dev_cmd.query.response;
1236 memset(request, 0, sizeof(struct ufs_query_req));
1237 memset(response, 0, sizeof(struct ufs_query_res));
1238
1239 switch (opcode) {
1240 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1241 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1242 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1243 break;
1244 case UPIU_QUERY_OPCODE_READ_ATTR:
1245 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1246 break;
1247 default:
1248 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1249 __func__, opcode);
1250 err = -EINVAL;
1251 goto out_unlock;
1252 }
1253
1254 request->upiu_req.opcode = opcode;
1255 request->upiu_req.idn = idn;
1256 request->upiu_req.index = index;
1257 request->upiu_req.selector = selector;
1258
1259 /* Send query request */
1260 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY,
1261 QUERY_REQ_TIMEOUT);
1262
1263 if (err) {
1264 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1265 __func__, opcode, idn, err);
1266 goto out_unlock;
1267 }
1268
e8c8e82a 1269 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1270
1271out_unlock:
1272 mutex_unlock(&hba->dev_cmd.lock);
1273out:
1274 return err;
1275}
1276
7a3e97b0
SY		 1277/**
1278 * ufshcd_memory_alloc - allocate memory for host memory space data structures
1279 * @hba: per adapter instance
1280 *
1281 * 1. Allocate DMA memory for Command Descriptor array
1282 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
1283 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
1284 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
1285 * (UTMRDL)
1286 * 4. Allocate memory for local reference block(lrb).
1287 *
1288 * Returns 0 for success, non-zero in case of failure
1289 */
1290static int ufshcd_memory_alloc(struct ufs_hba *hba)
1291{
1292 size_t utmrdl_size, utrdl_size, ucdl_size;
1293
1294 /* Allocate memory for UTP command descriptors */
1295 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 1296 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
1297 ucdl_size,
1298 &hba->ucdl_dma_addr,
1299 GFP_KERNEL);
7a3e97b0
SY		 1300
1301 /*
1302 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
1303 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
1304 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
1305 * be aligned to 128 bytes as well
1306 */
1307 if (!hba->ucdl_base_addr ||
1308 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1309 dev_err(hba->dev,
7a3e97b0
SY		 1310 "Command Descriptor Memory allocation failed\n");
1311 goto out;
1312 }
1313
1314 /*
1315 * Allocate memory for UTP Transfer descriptors
1316 * UFSHCI requires 1024 byte alignment of UTRD
1317 */
1318 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 1319 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
1320 utrdl_size,
1321 &hba->utrdl_dma_addr,
1322 GFP_KERNEL);
7a3e97b0
SY		 1323 if (!hba->utrdl_base_addr ||
1324 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1325 dev_err(hba->dev,
7a3e97b0
SY		 1326 "Transfer Descriptor Memory allocation failed\n");
1327 goto out;
1328 }
1329
1330 /*
1331 * Allocate memory for UTP Task Management descriptors
1332 * UFSHCI requires 1024 byte alignment of UTMRD
1333 */
1334 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 1335 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
1336 utmrdl_size,
1337 &hba->utmrdl_dma_addr,
1338 GFP_KERNEL);
7a3e97b0
SY		 1339 if (!hba->utmrdl_base_addr ||
1340 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1341 dev_err(hba->dev,
7a3e97b0
SY		 1342 "Task Management Descriptor Memory allocation failed\n");
1343 goto out;
1344 }
1345
1346 /* Allocate memory for local reference block */
2953f850
SJ		 1347 hba->lrb = devm_kzalloc(hba->dev,
1348 hba->nutrs * sizeof(struct ufshcd_lrb),
1349 GFP_KERNEL);
7a3e97b0 1350 if (!hba->lrb) {
3b1d0580 1351 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 1352 goto out;
1353 }
1354 return 0;
1355out:
7a3e97b0
SY		 1356 return -ENOMEM;
1357}
1358
1359/**
1360 * ufshcd_host_memory_configure - configure local reference block with
1361 * memory offsets
1362 * @hba: per adapter instance
1363 *
1364 * Configure Host memory space
1365 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
1366 * address.
1367 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
1368 * and PRDT offset.
1369 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
1370 * into local reference block.
1371 */
1372static void ufshcd_host_memory_configure(struct ufs_hba *hba)
1373{
1374 struct utp_transfer_cmd_desc *cmd_descp;
1375 struct utp_transfer_req_desc *utrdlp;
1376 dma_addr_t cmd_desc_dma_addr;
1377 dma_addr_t cmd_desc_element_addr;
1378 u16 response_offset;
1379 u16 prdt_offset;
1380 int cmd_desc_size;
1381 int i;
1382
1383 utrdlp = hba->utrdl_base_addr;
1384 cmd_descp = hba->ucdl_base_addr;
1385
1386 response_offset =
1387 offsetof(struct utp_transfer_cmd_desc, response_upiu);
1388 prdt_offset =
1389 offsetof(struct utp_transfer_cmd_desc, prd_table);
1390
1391 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
1392 cmd_desc_dma_addr = hba->ucdl_dma_addr;
1393
1394 for (i = 0; i < hba->nutrs; i++) {
1395 /* Configure UTRD with command descriptor base address */
1396 cmd_desc_element_addr =
1397 (cmd_desc_dma_addr + (cmd_desc_size * i));
1398 utrdlp[i].command_desc_base_addr_lo =
1399 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
1400 utrdlp[i].command_desc_base_addr_hi =
1401 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
1402
1403 /* Response upiu and prdt offset should be in double words */
1404 utrdlp[i].response_upiu_offset =
1405 cpu_to_le16((response_offset >> 2));
1406 utrdlp[i].prd_table_offset =
1407 cpu_to_le16((prdt_offset >> 2));
1408 utrdlp[i].response_upiu_length =
3ca316c5 1409 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0
SY		 1410
1411 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 1412 hba->lrb[i].ucd_req_ptr =
1413 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 1414 hba->lrb[i].ucd_rsp_ptr =
1415 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
1416 hba->lrb[i].ucd_prdt_ptr =
1417 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
1418 }
1419}
1420
1421/**
1422 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
1423 * @hba: per adapter instance
1424 *
1425 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
1426 * in order to initialize the Unipro link startup procedure.
1427 * Once the Unipro links are up, the device connected to the controller
1428 * is detected.
1429 *
1430 * Returns 0 on success, non-zero value on failure
1431 */
1432static int ufshcd_dme_link_startup(struct ufs_hba *hba)
1433{
6ccf44fe
SJ		 1434 struct uic_command uic_cmd = {0};
1435 int ret;
7a3e97b0 1436
6ccf44fe 1437 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 1438
6ccf44fe
SJ		 1439 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
1440 if (ret)
1441 dev_err(hba->dev,
1442 "dme-link-startup: error code %d\n", ret);
1443 return ret;
7a3e97b0
SY		 1444}
1445
12b4fdb4
SJ		 1446/**
1447 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
1448 * @hba: per adapter instance
1449 * @attr_sel: uic command argument1
1450 * @attr_set: attribute set type as uic command argument2
1451 * @mib_val: setting value as uic command argument3
1452 * @peer: indicate whether peer or local
1453 *
1454 * Returns 0 on success, non-zero value on failure
1455 */
1456int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1457 u8 attr_set, u32 mib_val, u8 peer)
1458{
1459 struct uic_command uic_cmd = {0};
1460 static const char *const action[] = {
1461 "dme-set",
1462 "dme-peer-set"
1463 };
1464 const char *set = action[!!peer];
1465 int ret;
1466
1467 uic_cmd.command = peer ?
1468 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
1469 uic_cmd.argument1 = attr_sel;
1470 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
1471 uic_cmd.argument3 = mib_val;
1472
1473 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
1474 if (ret)
1475 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
1476 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
1477
1478 return ret;
1479}
1480EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
1481
1482/**
1483 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
1484 * @hba: per adapter instance
1485 * @attr_sel: uic command argument1
1486 * @mib_val: the value of the attribute as returned by the UIC command
1487 * @peer: indicate whether peer or local
1488 *
1489 * Returns 0 on success, non-zero value on failure
1490 */
1491int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1492 u32 *mib_val, u8 peer)
1493{
1494 struct uic_command uic_cmd = {0};
1495 static const char *const action[] = {
1496 "dme-get",
1497 "dme-peer-get"
1498 };
1499 const char *get = action[!!peer];
1500 int ret;
1501
1502 uic_cmd.command = peer ?
1503 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
1504 uic_cmd.argument1 = attr_sel;
1505
1506 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
1507 if (ret) {
1508 dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
1509 get, UIC_GET_ATTR_ID(attr_sel), ret);
1510 goto out;
1511 }
1512
1513 if (mib_val)
1514 *mib_val = uic_cmd.argument3;
1515out:
1516 return ret;
1517}
1518EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
1519
53b3d9c3
SJ		 1520/**
1521 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
1522 * using DME_SET primitives.
1523 * @hba: per adapter instance
1524 * @mode: powr mode value
1525 *
1526 * Returns 0 on success, non-zero value on failure
1527 */
bdbe5d2f 1528static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
53b3d9c3
SJ		 1529{
1530 struct uic_command uic_cmd = {0};
1531 struct completion pwr_done;
1532 unsigned long flags;
1533 u8 status;
1534 int ret;
1535
1536 uic_cmd.command = UIC_CMD_DME_SET;
1537 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
1538 uic_cmd.argument3 = mode;
1539 init_completion(&pwr_done);
1540
1541 mutex_lock(&hba->uic_cmd_mutex);
1542
1543 spin_lock_irqsave(hba->host->host_lock, flags);
1544 hba->pwr_done = &pwr_done;
1545 spin_unlock_irqrestore(hba->host->host_lock, flags);
1546 ret = __ufshcd_send_uic_cmd(hba, &uic_cmd);
1547 if (ret) {
1548 dev_err(hba->dev,
1549 "pwr mode change with mode 0x%x uic error %d\n",
1550 mode, ret);
1551 goto out;
1552 }
1553
1554 if (!wait_for_completion_timeout(hba->pwr_done,
1555 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
1556 dev_err(hba->dev,
1557 "pwr mode change with mode 0x%x completion timeout\n",
1558 mode);
1559 ret = -ETIMEDOUT;
1560 goto out;
1561 }
1562
1563 status = ufshcd_get_upmcrs(hba);
1564 if (status != PWR_LOCAL) {
1565 dev_err(hba->dev,
1566 "pwr mode change failed, host umpcrs:0x%x\n",
1567 status);
1568 ret = (status != PWR_OK) ? status : -1;
1569 }
1570out:
1571 spin_lock_irqsave(hba->host->host_lock, flags);
1572 hba->pwr_done = NULL;
1573 spin_unlock_irqrestore(hba->host->host_lock, flags);
1574 mutex_unlock(&hba->uic_cmd_mutex);
1575 return ret;
1576}
1577
d3e89bac
SJ		 1578/**
1579 * ufshcd_config_max_pwr_mode - Set & Change power mode with
1580 * maximum capability attribute information.
1581 * @hba: per adapter instance
1582 *
1583 * Returns 0 on success, non-zero value on failure
1584 */
1585static int ufshcd_config_max_pwr_mode(struct ufs_hba *hba)
1586{
1587 enum {RX = 0, TX = 1};
1588 u32 lanes[] = {1, 1};
1589 u32 gear[] = {1, 1};
1590 u8 pwr[] = {FASTAUTO_MODE, FASTAUTO_MODE};
1591 int ret;
1592
1593 /* Get the connected lane count */
1594 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), &lanes[RX]);
1595 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), &lanes[TX]);
1596
1597 /*
1598 * First, get the maximum gears of HS speed.
1599 * If a zero value, it means there is no HSGEAR capability.
1600 * Then, get the maximum gears of PWM speed.
1601 */
1602 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &gear[RX]);
1603 if (!gear[RX]) {
1604 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), &gear[RX]);
1605 pwr[RX] = SLOWAUTO_MODE;
1606 }
1607
1608 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &gear[TX]);
1609 if (!gear[TX]) {
1610 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
1611 &gear[TX]);
1612 pwr[TX] = SLOWAUTO_MODE;
1613 }
1614
1615 /*
1616 * Configure attributes for power mode change with below.
1617 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
1618 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
1619 * - PA_HSSERIES
1620 */
1621 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), gear[RX]);
1622 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), lanes[RX]);
1623 if (pwr[RX] == FASTAUTO_MODE)
1624 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
1625
1626 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), gear[TX]);
1627 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), lanes[TX]);
1628 if (pwr[TX] == FASTAUTO_MODE)
1629 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
1630
1631 if (pwr[RX] == FASTAUTO_MODE || pwr[TX] == FASTAUTO_MODE)
1632 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), PA_HS_MODE_B);
1633
1634 ret = ufshcd_uic_change_pwr_mode(hba, pwr[RX] << 4 | pwr[TX]);
1635 if (ret)
1636 dev_err(hba->dev,
1637 "pwr_mode: power mode change failed %d\n", ret);
1638
1639 return ret;
1640}
1641
68078d5c
DR		 1642/**
1643 * ufshcd_complete_dev_init() - checks device readiness
1644 * hba: per-adapter instance
1645 *
1646 * Set fDeviceInit flag and poll until device toggles it.
1647 */
1648static int ufshcd_complete_dev_init(struct ufs_hba *hba)
1649{
1650 int i, retries, err = 0;
1651 bool flag_res = 1;
1652
1653 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1654 /* Set the fDeviceInit flag */
1655 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1656 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
1657 if (!err || err == -ETIMEDOUT)
1658 break;
1659 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
1660 }
1661 if (err) {
1662 dev_err(hba->dev,
1663 "%s setting fDeviceInit flag failed with error %d\n",
1664 __func__, err);
1665 goto out;
1666 }
1667
1668 /* poll for max. 100 iterations for fDeviceInit flag to clear */
1669 for (i = 0; i < 100 && !err && flag_res; i++) {
1670 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1671 err = ufshcd_query_flag(hba,
1672 UPIU_QUERY_OPCODE_READ_FLAG,
1673 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
1674 if (!err || err == -ETIMEDOUT)
1675 break;
1676 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
1677 err);
1678 }
1679 }
1680 if (err)
1681 dev_err(hba->dev,
1682 "%s reading fDeviceInit flag failed with error %d\n",
1683 __func__, err);
1684 else if (flag_res)
1685 dev_err(hba->dev,
1686 "%s fDeviceInit was not cleared by the device\n",
1687 __func__);
1688
1689out:
1690 return err;
1691}
1692
7a3e97b0
SY		 1693/**
1694 * ufshcd_make_hba_operational - Make UFS controller operational
1695 * @hba: per adapter instance
1696 *
1697 * To bring UFS host controller to operational state,
1698 * 1. Check if device is present
6ccf44fe
SJ		 1699 * 2. Enable required interrupts
1700 * 3. Configure interrupt aggregation
1701 * 4. Program UTRL and UTMRL base addres
1702 * 5. Configure run-stop-registers
7a3e97b0
SY		 1703 *
1704 * Returns 0 on success, non-zero value on failure
1705 */
1706static int ufshcd_make_hba_operational(struct ufs_hba *hba)
1707{
1708 int err = 0;
1709 u32 reg;
1710
1711 /* check if device present */
b873a275 1712 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
73ec513a 1713 if (!ufshcd_is_device_present(reg)) {
3b1d0580 1714 dev_err(hba->dev, "cc: Device not present\n");
7a3e97b0
SY		 1715 err = -ENXIO;
1716 goto out;
1717 }
1718
6ccf44fe
SJ		 1719 /* Enable required interrupts */
1720 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
1721
1722 /* Configure interrupt aggregation */
7d568652 1723 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
6ccf44fe
SJ		 1724
1725 /* Configure UTRL and UTMRL base address registers */
1726 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
1727 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
1728 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
1729 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
1730 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
1731 REG_UTP_TASK_REQ_LIST_BASE_L);
1732 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
1733 REG_UTP_TASK_REQ_LIST_BASE_H);
1734
7a3e97b0
SY		 1735 /*
1736 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
1737 * DEI, HEI bits must be 0
1738 */
1739 if (!(ufshcd_get_lists_status(reg))) {
1740 ufshcd_enable_run_stop_reg(hba);
1741 } else {
3b1d0580 1742 dev_err(hba->dev,
7a3e97b0
SY		 1743 "Host controller not ready to process requests");
1744 err = -EIO;
1745 goto out;
1746 }
1747
7a3e97b0
SY		 1748out:
1749 return err;
1750}
1751
1752/**
1753 * ufshcd_hba_enable - initialize the controller
1754 * @hba: per adapter instance
1755 *
1756 * The controller resets itself and controller firmware initialization
1757 * sequence kicks off. When controller is ready it will set
1758 * the Host Controller Enable bit to 1.
1759 *
1760 * Returns 0 on success, non-zero value on failure
1761 */
1762static int ufshcd_hba_enable(struct ufs_hba *hba)
1763{
1764 int retry;
1765
1766 /*
1767 * msleep of 1 and 5 used in this function might result in msleep(20),
1768 * but it was necessary to send the UFS FPGA to reset mode during
1769 * development and testing of this driver. msleep can be changed to
1770 * mdelay and retry count can be reduced based on the controller.
1771 */
1772 if (!ufshcd_is_hba_active(hba)) {
1773
1774 /* change controller state to "reset state" */
1775 ufshcd_hba_stop(hba);
1776
1777 /*
1778 * This delay is based on the testing done with UFS host
1779 * controller FPGA. The delay can be changed based on the
1780 * host controller used.
1781 */
1782 msleep(5);
1783 }
1784
1785 /* start controller initialization sequence */
1786 ufshcd_hba_start(hba);
1787
1788 /*
1789 * To initialize a UFS host controller HCE bit must be set to 1.
1790 * During initialization the HCE bit value changes from 1->0->1.
1791 * When the host controller completes initialization sequence
1792 * it sets the value of HCE bit to 1. The same HCE bit is read back
1793 * to check if the controller has completed initialization sequence.
1794 * So without this delay the value HCE = 1, set in the previous
1795 * instruction might be read back.
1796 * This delay can be changed based on the controller.
1797 */
1798 msleep(1);
1799
1800 /* wait for the host controller to complete initialization */
1801 retry = 10;
1802 while (ufshcd_is_hba_active(hba)) {
1803 if (retry) {
1804 retry--;
1805 } else {
3b1d0580 1806 dev_err(hba->dev,
7a3e97b0
SY		 1807 "Controller enable failed\n");
1808 return -EIO;
1809 }
1810 msleep(5);
1811 }
1812 return 0;
1813}
1814
1815/**
6ccf44fe 1816 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 1817 * @hba: per adapter instance
1818 *
6ccf44fe 1819 * Returns 0 for success, non-zero in case of failure
7a3e97b0 1820 */
6ccf44fe 1821static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 1822{
6ccf44fe 1823 int ret;
7a3e97b0 1824
6ccf44fe
SJ		 1825 /* enable UIC related interrupts */
1826 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
1827
1828 ret = ufshcd_dme_link_startup(hba);
1829 if (ret)
1830 goto out;
1831
1832 ret = ufshcd_make_hba_operational(hba);
7a3e97b0 1833
6ccf44fe
SJ		 1834out:
1835 if (ret)
1836 dev_err(hba->dev, "link startup failed %d\n", ret);
1837 return ret;
7a3e97b0
SY		 1838}
1839
5a0b0cb9
SRT		 1840/**
1841 * ufshcd_verify_dev_init() - Verify device initialization
1842 * @hba: per-adapter instance
1843 *
1844 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
1845 * device Transport Protocol (UTP) layer is ready after a reset.
1846 * If the UTP layer at the device side is not initialized, it may
1847 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
1848 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
1849 */
1850static int ufshcd_verify_dev_init(struct ufs_hba *hba)
1851{
1852 int err = 0;
1853 int retries;
1854
1855 mutex_lock(&hba->dev_cmd.lock);
1856 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
1857 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
1858 NOP_OUT_TIMEOUT);
1859
1860 if (!err || err == -ETIMEDOUT)
1861 break;
1862
1863 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
1864 }
1865 mutex_unlock(&hba->dev_cmd.lock);
1866
1867 if (err)
1868 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
1869 return err;
1870}
1871
7a3e97b0
SY		 1872/**
1873 * ufshcd_slave_alloc - handle initial SCSI device configurations
1874 * @sdev: pointer to SCSI device
1875 *
1876 * Returns success
1877 */
1878static int ufshcd_slave_alloc(struct scsi_device *sdev)
1879{
1880 struct ufs_hba *hba;
1881
1882 hba = shost_priv(sdev->host);
1883 sdev->tagged_supported = 1;
1884
1885 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
1886 sdev->use_10_for_ms = 1;
1887 scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
1888
e8e7f271
SRT		 1889 /* allow SCSI layer to restart the device in case of errors */
1890 sdev->allow_restart = 1;
1891
7a3e97b0
SY		 1892 /*
1893 * Inform SCSI Midlayer that the LUN queue depth is same as the
1894 * controller queue depth. If a LUN queue depth is less than the
1895 * controller queue depth and if the LUN reports
1896 * SAM_STAT_TASK_SET_FULL, the LUN queue depth will be adjusted
1897 * with scsi_adjust_queue_depth.
1898 */
1899 scsi_activate_tcq(sdev, hba->nutrs);
1900 return 0;
1901}
1902
1903/**
1904 * ufshcd_slave_destroy - remove SCSI device configurations
1905 * @sdev: pointer to SCSI device
1906 */
1907static void ufshcd_slave_destroy(struct scsi_device *sdev)
1908{
1909 struct ufs_hba *hba;
1910
1911 hba = shost_priv(sdev->host);
1912 scsi_deactivate_tcq(sdev, hba->nutrs);
1913}
1914
1915/**
1916 * ufshcd_task_req_compl - handle task management request completion
1917 * @hba: per adapter instance
1918 * @index: index of the completed request
e2933132 1919 * @resp: task management service response
7a3e97b0 1920 *
e2933132 1921 * Returns non-zero value on error, zero on success
7a3e97b0 1922 */
e2933132 1923static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 1924{
1925 struct utp_task_req_desc *task_req_descp;
1926 struct utp_upiu_task_rsp *task_rsp_upiup;
1927 unsigned long flags;
1928 int ocs_value;
1929 int task_result;
1930
1931 spin_lock_irqsave(hba->host->host_lock, flags);
1932
1933 /* Clear completed tasks from outstanding_tasks */
1934 __clear_bit(index, &hba->outstanding_tasks);
1935
1936 task_req_descp = hba->utmrdl_base_addr;
1937 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
1938
1939 if (ocs_value == OCS_SUCCESS) {
1940 task_rsp_upiup = (struct utp_upiu_task_rsp *)
1941 task_req_descp[index].task_rsp_upiu;
1942 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
1943 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
e2933132
SRT		 1944 if (resp)
1945 *resp = (u8)task_result;
7a3e97b0 1946 } else {
e2933132
SRT		 1947 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
1948 __func__, ocs_value);
7a3e97b0
SY		 1949 }
1950 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 1951
1952 return ocs_value;
7a3e97b0
SY		 1953}
1954
1955/**
1956 * ufshcd_adjust_lun_qdepth - Update LUN queue depth if device responds with
1957 * SAM_STAT_TASK_SET_FULL SCSI command status.
1958 * @cmd: pointer to SCSI command
1959 */
1960static void ufshcd_adjust_lun_qdepth(struct scsi_cmnd *cmd)
1961{
1962 struct ufs_hba *hba;
1963 int i;
1964 int lun_qdepth = 0;
1965
1966 hba = shost_priv(cmd->device->host);
1967
1968 /*
1969 * LUN queue depth can be obtained by counting outstanding commands
1970 * on the LUN.
1971 */
1972 for (i = 0; i < hba->nutrs; i++) {
1973 if (test_bit(i, &hba->outstanding_reqs)) {
1974
1975 /*
1976 * Check if the outstanding command belongs
1977 * to the LUN which reported SAM_STAT_TASK_SET_FULL.
1978 */
1979 if (cmd->device->lun == hba->lrb[i].lun)
1980 lun_qdepth++;
1981 }
1982 }
1983
1984 /*
1985 * LUN queue depth will be total outstanding commands, except the
1986 * command for which the LUN reported SAM_STAT_TASK_SET_FULL.
1987 */
1988 scsi_adjust_queue_depth(cmd->device, MSG_SIMPLE_TAG, lun_qdepth - 1);
1989}
1990
1991/**
1992 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
1993 * @lrb: pointer to local reference block of completed command
1994 * @scsi_status: SCSI command status
1995 *
1996 * Returns value base on SCSI command status
1997 */
1998static inline int
1999ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
2000{
2001 int result = 0;
2002
2003 switch (scsi_status) {
7a3e97b0 2004 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 2005 ufshcd_copy_sense_data(lrbp);
2006 case SAM_STAT_GOOD:
7a3e97b0
SY		 2007 result |= DID_OK << 16 |
2008 COMMAND_COMPLETE << 8 |
1c2623c5 2009 scsi_status;
7a3e97b0
SY		 2010 break;
2011 case SAM_STAT_TASK_SET_FULL:
7a3e97b0
SY		 2012 /*
2013 * If a LUN reports SAM_STAT_TASK_SET_FULL, then the LUN queue
2014 * depth needs to be adjusted to the exact number of
2015 * outstanding commands the LUN can handle at any given time.
2016 */
2017 ufshcd_adjust_lun_qdepth(lrbp->cmd);
1c2623c5 2018 case SAM_STAT_BUSY:
7a3e97b0 2019 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 2020 ufshcd_copy_sense_data(lrbp);
2021 result |= scsi_status;
7a3e97b0
SY		 2022 break;
2023 default:
2024 result |= DID_ERROR << 16;
2025 break;
2026 } /* end of switch */
2027
2028 return result;
2029}
2030
2031/**
2032 * ufshcd_transfer_rsp_status - Get overall status of the response
2033 * @hba: per adapter instance
2034 * @lrb: pointer to local reference block of completed command
2035 *
2036 * Returns result of the command to notify SCSI midlayer
2037 */
2038static inline int
2039ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2040{
2041 int result = 0;
2042 int scsi_status;
2043 int ocs;
2044
2045 /* overall command status of utrd */
2046 ocs = ufshcd_get_tr_ocs(lrbp);
2047
2048 switch (ocs) {
2049 case OCS_SUCCESS:
5a0b0cb9 2050 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 2051
5a0b0cb9
SRT		 2052 switch (result) {
2053 case UPIU_TRANSACTION_RESPONSE:
2054 /*
2055 * get the response UPIU result to extract
2056 * the SCSI command status
2057 */
2058 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
2059
2060 /*
2061 * get the result based on SCSI status response
2062 * to notify the SCSI midlayer of the command status
2063 */
2064 scsi_status = result & MASK_SCSI_STATUS;
2065 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59
SRT		 2066
2067 if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
2068 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 2069 break;
2070 case UPIU_TRANSACTION_REJECT_UPIU:
2071 /* TODO: handle Reject UPIU Response */
2072 result = DID_ERROR << 16;
3b1d0580 2073 dev_err(hba->dev,
5a0b0cb9
SRT		 2074 "Reject UPIU not fully implemented\n");
2075 break;
2076 default:
2077 result = DID_ERROR << 16;
2078 dev_err(hba->dev,
2079 "Unexpected request response code = %x\n",
2080 result);
7a3e97b0
SY		 2081 break;
2082 }
7a3e97b0
SY		 2083 break;
2084 case OCS_ABORTED:
2085 result |= DID_ABORT << 16;
2086 break;
e8e7f271
SRT		 2087 case OCS_INVALID_COMMAND_STATUS:
2088 result |= DID_REQUEUE << 16;
2089 break;
7a3e97b0
SY		 2090 case OCS_INVALID_CMD_TABLE_ATTR:
2091 case OCS_INVALID_PRDT_ATTR:
2092 case OCS_MISMATCH_DATA_BUF_SIZE:
2093 case OCS_MISMATCH_RESP_UPIU_SIZE:
2094 case OCS_PEER_COMM_FAILURE:
2095 case OCS_FATAL_ERROR:
2096 default:
2097 result |= DID_ERROR << 16;
3b1d0580 2098 dev_err(hba->dev,
7a3e97b0
SY		 2099 "OCS error from controller = %x\n", ocs);
2100 break;
2101 } /* end of switch */
2102
2103 return result;
2104}
2105
6ccf44fe
SJ		 2106/**
2107 * ufshcd_uic_cmd_compl - handle completion of uic command
2108 * @hba: per adapter instance
53b3d9c3 2109 * @intr_status: interrupt status generated by the controller
6ccf44fe 2110 */
53b3d9c3 2111static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 2112{
53b3d9c3 2113 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 2114 hba->active_uic_cmd->argument2 |=
2115 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 2116 hba->active_uic_cmd->argument3 =
2117 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 2118 complete(&hba->active_uic_cmd->done);
2119 }
53b3d9c3
SJ		 2120
2121 if ((intr_status & UIC_POWER_MODE) && hba->pwr_done)
2122 complete(hba->pwr_done);
6ccf44fe
SJ		 2123}
2124
7a3e97b0
SY		 2125/**
2126 * ufshcd_transfer_req_compl - handle SCSI and query command completion
2127 * @hba: per adapter instance
2128 */
2129static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
2130{
5a0b0cb9
SRT		 2131 struct ufshcd_lrb *lrbp;
2132 struct scsi_cmnd *cmd;
7a3e97b0
SY		 2133 unsigned long completed_reqs;
2134 u32 tr_doorbell;
2135 int result;
2136 int index;
5a0b0cb9 2137 bool int_aggr_reset = false;
7a3e97b0 2138
b873a275 2139 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 2140 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
2141
2142 for (index = 0; index < hba->nutrs; index++) {
2143 if (test_bit(index, &completed_reqs)) {
5a0b0cb9
SRT		 2144 lrbp = &hba->lrb[index];
2145 cmd = lrbp->cmd;
2146 /*
2147 * Don't skip resetting interrupt aggregation counters
2148 * if a regular command is present.
2149 */
2150 int_aggr_reset |= !lrbp->intr_cmd;
7a3e97b0 2151
5a0b0cb9
SRT		 2152 if (cmd) {
2153 result = ufshcd_transfer_rsp_status(hba, lrbp);
2154 scsi_dma_unmap(cmd);
2155 cmd->result = result;
7a3e97b0 2156 /* Mark completed command as NULL in LRB */
5a0b0cb9
SRT		 2157 lrbp->cmd = NULL;
2158 clear_bit_unlock(index, &hba->lrb_in_use);
2159 /* Do not touch lrbp after scsi done */
2160 cmd->scsi_done(cmd);
2161 } else if (lrbp->command_type ==
2162 UTP_CMD_TYPE_DEV_MANAGE) {
2163 if (hba->dev_cmd.complete)
2164 complete(hba->dev_cmd.complete);
7a3e97b0
SY		 2165 }
2166 } /* end of if */
2167 } /* end of for */
2168
2169 /* clear corresponding bits of completed commands */
2170 hba->outstanding_reqs ^= completed_reqs;
2171
5a0b0cb9
SRT		 2172 /* we might have free'd some tags above */
2173 wake_up(&hba->dev_cmd.tag_wq);
2174
7a3e97b0 2175 /* Reset interrupt aggregation counters */
5a0b0cb9 2176 if (int_aggr_reset)
7d568652 2177 ufshcd_reset_intr_aggr(hba);
7a3e97b0
SY		 2178}
2179
66ec6d59
SRT		 2180/**
2181 * ufshcd_disable_ee - disable exception event
2182 * @hba: per-adapter instance
2183 * @mask: exception event to disable
2184 *
2185 * Disables exception event in the device so that the EVENT_ALERT
2186 * bit is not set.
2187 *
2188 * Returns zero on success, non-zero error value on failure.
2189 */
2190static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
2191{
2192 int err = 0;
2193 u32 val;
2194
2195 if (!(hba->ee_ctrl_mask & mask))
2196 goto out;
2197
2198 val = hba->ee_ctrl_mask & ~mask;
2199 val &= 0xFFFF; /* 2 bytes */
2200 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
2201 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
2202 if (!err)
2203 hba->ee_ctrl_mask &= ~mask;
2204out:
2205 return err;
2206}
2207
2208/**
2209 * ufshcd_enable_ee - enable exception event
2210 * @hba: per-adapter instance
2211 * @mask: exception event to enable
2212 *
2213 * Enable corresponding exception event in the device to allow
2214 * device to alert host in critical scenarios.
2215 *
2216 * Returns zero on success, non-zero error value on failure.
2217 */
2218static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
2219{
2220 int err = 0;
2221 u32 val;
2222
2223 if (hba->ee_ctrl_mask & mask)
2224 goto out;
2225
2226 val = hba->ee_ctrl_mask | mask;
2227 val &= 0xFFFF; /* 2 bytes */
2228 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
2229 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
2230 if (!err)
2231 hba->ee_ctrl_mask |= mask;
2232out:
2233 return err;
2234}
2235
2236/**
2237 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
2238 * @hba: per-adapter instance
2239 *
2240 * Allow device to manage background operations on its own. Enabling
2241 * this might lead to inconsistent latencies during normal data transfers
2242 * as the device is allowed to manage its own way of handling background
2243 * operations.
2244 *
2245 * Returns zero on success, non-zero on failure.
2246 */
2247static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
2248{
2249 int err = 0;
2250
2251 if (hba->auto_bkops_enabled)
2252 goto out;
2253
2254 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2255 QUERY_FLAG_IDN_BKOPS_EN, NULL);
2256 if (err) {
2257 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
2258 __func__, err);
2259 goto out;
2260 }
2261
2262 hba->auto_bkops_enabled = true;
2263
2264 /* No need of URGENT_BKOPS exception from the device */
2265 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
2266 if (err)
2267 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
2268 __func__, err);
2269out:
2270 return err;
2271}
2272
2273/**
2274 * ufshcd_disable_auto_bkops - block device in doing background operations
2275 * @hba: per-adapter instance
2276 *
2277 * Disabling background operations improves command response latency but
2278 * has drawback of device moving into critical state where the device is
2279 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
2280 * host is idle so that BKOPS are managed effectively without any negative
2281 * impacts.
2282 *
2283 * Returns zero on success, non-zero on failure.
2284 */
2285static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
2286{
2287 int err = 0;
2288
2289 if (!hba->auto_bkops_enabled)
2290 goto out;
2291
2292 /*
2293 * If host assisted BKOPs is to be enabled, make sure
2294 * urgent bkops exception is allowed.
2295 */
2296 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
2297 if (err) {
2298 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
2299 __func__, err);
2300 goto out;
2301 }
2302
2303 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
2304 QUERY_FLAG_IDN_BKOPS_EN, NULL);
2305 if (err) {
2306 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
2307 __func__, err);
2308 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
2309 goto out;
2310 }
2311
2312 hba->auto_bkops_enabled = false;
2313out:
2314 return err;
2315}
2316
2317/**
2318 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
2319 * @hba: per adapter instance
2320 *
2321 * After a device reset the device may toggle the BKOPS_EN flag
2322 * to default value. The s/w tracking variables should be updated
2323 * as well. Do this by forcing enable of auto bkops.
2324 */
2325static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
2326{
2327 hba->auto_bkops_enabled = false;
2328 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
2329 ufshcd_enable_auto_bkops(hba);
2330}
2331
2332static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
2333{
2334 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
2335 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
2336}
2337
2338/**
2339 * ufshcd_urgent_bkops - handle urgent bkops exception event
2340 * @hba: per-adapter instance
2341 *
2342 * Enable fBackgroundOpsEn flag in the device to permit background
2343 * operations.
2344 */
2345static int ufshcd_urgent_bkops(struct ufs_hba *hba)
2346{
2347 int err;
2348 u32 status = 0;
2349
2350 err = ufshcd_get_bkops_status(hba, &status);
2351 if (err) {
2352 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
2353 __func__, err);
2354 goto out;
2355 }
2356
2357 status = status & 0xF;
2358
2359 /* handle only if status indicates performance impact or critical */
2360 if (status >= BKOPS_STATUS_PERF_IMPACT)
2361 err = ufshcd_enable_auto_bkops(hba);
2362out:
2363 return err;
2364}
2365
2366static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
2367{
2368 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
2369 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
2370}
2371
2372/**
2373 * ufshcd_exception_event_handler - handle exceptions raised by device
2374 * @work: pointer to work data
2375 *
2376 * Read bExceptionEventStatus attribute from the device and handle the
2377 * exception event accordingly.
2378 */
2379static void ufshcd_exception_event_handler(struct work_struct *work)
2380{
2381 struct ufs_hba *hba;
2382 int err;
2383 u32 status = 0;
2384 hba = container_of(work, struct ufs_hba, eeh_work);
2385
62694735 2386 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 2387 err = ufshcd_get_ee_status(hba, &status);
2388 if (err) {
2389 dev_err(hba->dev, "%s: failed to get exception status %d\n",
2390 __func__, err);
2391 goto out;
2392 }
2393
2394 status &= hba->ee_ctrl_mask;
2395 if (status & MASK_EE_URGENT_BKOPS) {
2396 err = ufshcd_urgent_bkops(hba);
2397 if (err)
2398 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
2399 __func__, err);
2400 }
2401out:
62694735 2402 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 2403 return;
2404}
2405
7a3e97b0 2406/**
e8e7f271
SRT		 2407 * ufshcd_err_handler - handle UFS errors that require s/w attention
2408 * @work: pointer to work structure
7a3e97b0 2409 */
e8e7f271 2410static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 2411{
2412 struct ufs_hba *hba;
e8e7f271
SRT		 2413 unsigned long flags;
2414 u32 err_xfer = 0;
2415 u32 err_tm = 0;
2416 int err = 0;
2417 int tag;
2418
2419 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 2420
62694735 2421 pm_runtime_get_sync(hba->dev);
e8e7f271
SRT		 2422
2423 spin_lock_irqsave(hba->host->host_lock, flags);
2424 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
2425 spin_unlock_irqrestore(hba->host->host_lock, flags);
2426 goto out;
2427 }
2428
2429 hba->ufshcd_state = UFSHCD_STATE_RESET;
2430 ufshcd_set_eh_in_progress(hba);
2431
2432 /* Complete requests that have door-bell cleared by h/w */
2433 ufshcd_transfer_req_compl(hba);
2434 ufshcd_tmc_handler(hba);
2435 spin_unlock_irqrestore(hba->host->host_lock, flags);
2436
2437 /* Clear pending transfer requests */
2438 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
2439 if (ufshcd_clear_cmd(hba, tag))
2440 err_xfer |= 1 << tag;
2441
2442 /* Clear pending task management requests */
2443 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
2444 if (ufshcd_clear_tm_cmd(hba, tag))
2445 err_tm |= 1 << tag;
2446
2447 /* Complete the requests that are cleared by s/w */
2448 spin_lock_irqsave(hba->host->host_lock, flags);
2449 ufshcd_transfer_req_compl(hba);
2450 ufshcd_tmc_handler(hba);
2451 spin_unlock_irqrestore(hba->host->host_lock, flags);
2452
2453 /* Fatal errors need reset */
2454 if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
2455 ((hba->saved_err & UIC_ERROR) &&
2456 (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
2457 err = ufshcd_reset_and_restore(hba);
2458 if (err) {
2459 dev_err(hba->dev, "%s: reset and restore failed\n",
2460 __func__);
2461 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2462 }
2463 /*
2464 * Inform scsi mid-layer that we did reset and allow to handle
2465 * Unit Attention properly.
2466 */
2467 scsi_report_bus_reset(hba->host, 0);
2468 hba->saved_err = 0;
2469 hba->saved_uic_err = 0;
2470 }
2471 ufshcd_clear_eh_in_progress(hba);
2472
2473out:
2474 scsi_unblock_requests(hba->host);
62694735 2475 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 2476}
2477
2478/**
e8e7f271
SRT		 2479 * ufshcd_update_uic_error - check and set fatal UIC error flags.
2480 * @hba: per-adapter instance
7a3e97b0 2481 */
e8e7f271 2482static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 2483{
2484 u32 reg;
2485
e8e7f271
SRT		 2486 /* PA_INIT_ERROR is fatal and needs UIC reset */
2487 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
2488 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
2489 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
2490
2491 /* UIC NL/TL/DME errors needs software retry */
2492 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
2493 if (reg)
2494 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
2495
2496 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
2497 if (reg)
2498 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
2499
2500 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
2501 if (reg)
2502 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
2503
2504 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
2505 __func__, hba->uic_error);
2506}
2507
2508/**
2509 * ufshcd_check_errors - Check for errors that need s/w attention
2510 * @hba: per-adapter instance
2511 */
2512static void ufshcd_check_errors(struct ufs_hba *hba)
2513{
2514 bool queue_eh_work = false;
2515
7a3e97b0 2516 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 2517 queue_eh_work = true;
7a3e97b0
SY		 2518
2519 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 2520 hba->uic_error = 0;
2521 ufshcd_update_uic_error(hba);
2522 if (hba->uic_error)
2523 queue_eh_work = true;
7a3e97b0 2524 }
e8e7f271
SRT		 2525
2526 if (queue_eh_work) {
2527 /* handle fatal errors only when link is functional */
2528 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
2529 /* block commands from scsi mid-layer */
2530 scsi_block_requests(hba->host);
2531
2532 /* transfer error masks to sticky bits */
2533 hba->saved_err |= hba->errors;
2534 hba->saved_uic_err |= hba->uic_error;
2535
2536 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2537 schedule_work(&hba->eh_work);
2538 }
3441da7d 2539 }
e8e7f271
SRT		 2540 /*
2541 * if (!queue_eh_work) -
2542 * Other errors are either non-fatal where host recovers
2543 * itself without s/w intervention or errors that will be
2544 * handled by the SCSI core layer.
2545 */
7a3e97b0
SY		 2546}
2547
2548/**
2549 * ufshcd_tmc_handler - handle task management function completion
2550 * @hba: per adapter instance
2551 */
2552static void ufshcd_tmc_handler(struct ufs_hba *hba)
2553{
2554 u32 tm_doorbell;
2555
b873a275 2556 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 2557 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 2558 wake_up(&hba->tm_wq);
7a3e97b0
SY		 2559}
2560
2561/**
2562 * ufshcd_sl_intr - Interrupt service routine
2563 * @hba: per adapter instance
2564 * @intr_status: contains interrupts generated by the controller
2565 */
2566static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
2567{
2568 hba->errors = UFSHCD_ERROR_MASK & intr_status;
2569 if (hba->errors)
e8e7f271 2570 ufshcd_check_errors(hba);
7a3e97b0 2571
53b3d9c3
SJ		 2572 if (intr_status & UFSHCD_UIC_MASK)
2573 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 2574
2575 if (intr_status & UTP_TASK_REQ_COMPL)
2576 ufshcd_tmc_handler(hba);
2577
2578 if (intr_status & UTP_TRANSFER_REQ_COMPL)
2579 ufshcd_transfer_req_compl(hba);
2580}
2581
2582/**
2583 * ufshcd_intr - Main interrupt service routine
2584 * @irq: irq number
2585 * @__hba: pointer to adapter instance
2586 *
2587 * Returns IRQ_HANDLED - If interrupt is valid
2588 * IRQ_NONE - If invalid interrupt
2589 */
2590static irqreturn_t ufshcd_intr(int irq, void *__hba)
2591{
2592 u32 intr_status;
2593 irqreturn_t retval = IRQ_NONE;
2594 struct ufs_hba *hba = __hba;
2595
2596 spin_lock(hba->host->host_lock);
b873a275 2597 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0
SY		 2598
2599 if (intr_status) {
261ea452 2600 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7a3e97b0 2601 ufshcd_sl_intr(hba, intr_status);
7a3e97b0
SY		 2602 retval = IRQ_HANDLED;
2603 }
2604 spin_unlock(hba->host->host_lock);
2605 return retval;
2606}
2607
e2933132
SRT		 2608static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
2609{
2610 int err = 0;
2611 u32 mask = 1 << tag;
2612 unsigned long flags;
2613
2614 if (!test_bit(tag, &hba->outstanding_tasks))
2615 goto out;
2616
2617 spin_lock_irqsave(hba->host->host_lock, flags);
2618 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
2619 spin_unlock_irqrestore(hba->host->host_lock, flags);
2620
2621 /* poll for max. 1 sec to clear door bell register by h/w */
2622 err = ufshcd_wait_for_register(hba,
2623 REG_UTP_TASK_REQ_DOOR_BELL,
2624 mask, 0, 1000, 1000);
2625out:
2626 return err;
2627}
2628
7a3e97b0
SY		 2629/**
2630 * ufshcd_issue_tm_cmd - issues task management commands to controller
2631 * @hba: per adapter instance
e2933132
SRT		 2632 * @lun_id: LUN ID to which TM command is sent
2633 * @task_id: task ID to which the TM command is applicable
2634 * @tm_function: task management function opcode
2635 * @tm_response: task management service response return value
7a3e97b0 2636 *
e2933132 2637 * Returns non-zero value on error, zero on success.
7a3e97b0 2638 */
e2933132
SRT		 2639static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
2640 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 2641{
2642 struct utp_task_req_desc *task_req_descp;
2643 struct utp_upiu_task_req *task_req_upiup;
2644 struct Scsi_Host *host;
2645 unsigned long flags;
e2933132 2646 int free_slot;
7a3e97b0 2647 int err;
e2933132 2648 int task_tag;
7a3e97b0
SY		 2649
2650 host = hba->host;
2651
e2933132
SRT		 2652 /*
2653 * Get free slot, sleep if slots are unavailable.
2654 * Even though we use wait_event() which sleeps indefinitely,
2655 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
2656 */
2657 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
7a3e97b0 2658
e2933132 2659 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 2660 task_req_descp = hba->utmrdl_base_addr;
2661 task_req_descp += free_slot;
2662
2663 /* Configure task request descriptor */
2664 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
2665 task_req_descp->header.dword_2 =
2666 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2667
2668 /* Configure task request UPIU */
2669 task_req_upiup =
2670 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 2671 task_tag = hba->nutrs + free_slot;
7a3e97b0 2672 task_req_upiup->header.dword_0 =
5a0b0cb9 2673 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 2674 lun_id, task_tag);
7a3e97b0 2675 task_req_upiup->header.dword_1 =
5a0b0cb9 2676 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
7a3e97b0 2677
e2933132
SRT		 2678 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
2679 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0
SY		 2680
2681 /* send command to the controller */
2682 __set_bit(free_slot, &hba->outstanding_tasks);
b873a275 2683 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0
SY		 2684
2685 spin_unlock_irqrestore(host->host_lock, flags);
2686
2687 /* wait until the task management command is completed */
e2933132
SRT		 2688 err = wait_event_timeout(hba->tm_wq,
2689 test_bit(free_slot, &hba->tm_condition),
2690 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 2691 if (!err) {
e2933132
SRT		 2692 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
2693 __func__, tm_function);
2694 if (ufshcd_clear_tm_cmd(hba, free_slot))
2695 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
2696 __func__, free_slot);
2697 err = -ETIMEDOUT;
2698 } else {
2699 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 2700 }
e2933132 2701
7a3e97b0 2702 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 2703 ufshcd_put_tm_slot(hba, free_slot);
2704 wake_up(&hba->tm_tag_wq);
2705
7a3e97b0
SY		 2706 return err;
2707}
2708
2709/**
3441da7d
SRT		 2710 * ufshcd_eh_device_reset_handler - device reset handler registered to
2711 * scsi layer.
7a3e97b0
SY		 2712 * @cmd: SCSI command pointer
2713 *
2714 * Returns SUCCESS/FAILED
2715 */
3441da7d 2716static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 2717{
2718 struct Scsi_Host *host;
2719 struct ufs_hba *hba;
2720 unsigned int tag;
2721 u32 pos;
2722 int err;
e2933132
SRT		 2723 u8 resp = 0xF;
2724 struct ufshcd_lrb *lrbp;
3441da7d 2725 unsigned long flags;
7a3e97b0
SY		 2726
2727 host = cmd->device->host;
2728 hba = shost_priv(host);
2729 tag = cmd->request->tag;
2730
e2933132
SRT		 2731 lrbp = &hba->lrb[tag];
2732 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
2733 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 2734 if (!err)
2735 err = resp;
7a3e97b0 2736 goto out;
e2933132 2737 }
7a3e97b0 2738
3441da7d
SRT		 2739 /* clear the commands that were pending for corresponding LUN */
2740 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
2741 if (hba->lrb[pos].lun == lrbp->lun) {
2742 err = ufshcd_clear_cmd(hba, pos);
2743 if (err)
2744 break;
7a3e97b0 2745 }
3441da7d
SRT		 2746 }
2747 spin_lock_irqsave(host->host_lock, flags);
2748 ufshcd_transfer_req_compl(hba);
2749 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 2750out:
3441da7d
SRT		 2751 if (!err) {
2752 err = SUCCESS;
2753 } else {
2754 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
2755 err = FAILED;
2756 }
7a3e97b0
SY		 2757 return err;
2758}
2759
7a3e97b0
SY		 2760/**
2761 * ufshcd_abort - abort a specific command
2762 * @cmd: SCSI command pointer
2763 *
f20810d8
SRT		 2764 * Abort the pending command in device by sending UFS_ABORT_TASK task management
2765 * command, and in host controller by clearing the door-bell register. There can
2766 * be race between controller sending the command to the device while abort is
2767 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
2768 * really issued and then try to abort it.
2769 *
7a3e97b0
SY		 2770 * Returns SUCCESS/FAILED
2771 */
2772static int ufshcd_abort(struct scsi_cmnd *cmd)
2773{
2774 struct Scsi_Host *host;
2775 struct ufs_hba *hba;
2776 unsigned long flags;
2777 unsigned int tag;
f20810d8
SRT		 2778 int err = 0;
2779 int poll_cnt;
e2933132
SRT		 2780 u8 resp = 0xF;
2781 struct ufshcd_lrb *lrbp;
7a3e97b0
SY		 2782
2783 host = cmd->device->host;
2784 hba = shost_priv(host);
2785 tag = cmd->request->tag;
2786
f20810d8
SRT		 2787 /* If command is already aborted/completed, return SUCCESS */
2788 if (!(test_bit(tag, &hba->outstanding_reqs)))
2789 goto out;
7a3e97b0 2790
f20810d8
SRT		 2791 lrbp = &hba->lrb[tag];
2792 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
2793 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
2794 UFS_QUERY_TASK, &resp);
2795 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
2796 /* cmd pending in the device */
2797 break;
2798 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
2799 u32 reg;
2800
2801 /*
2802 * cmd not pending in the device, check if it is
2803 * in transition.
2804 */
2805 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
2806 if (reg & (1 << tag)) {
2807 /* sleep for max. 200us to stabilize */
2808 usleep_range(100, 200);
2809 continue;
2810 }
2811 /* command completed already */
2812 goto out;
2813 } else {
2814 if (!err)
2815 err = resp; /* service response error */
2816 goto out;
2817 }
2818 }
2819
2820 if (!poll_cnt) {
2821 err = -EBUSY;
7a3e97b0
SY		 2822 goto out;
2823 }
7a3e97b0 2824
e2933132
SRT		 2825 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
2826 UFS_ABORT_TASK, &resp);
2827 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 2828 if (!err)
2829 err = resp; /* service response error */
7a3e97b0 2830 goto out;
e2933132 2831 }
7a3e97b0 2832
f20810d8
SRT		 2833 err = ufshcd_clear_cmd(hba, tag);
2834 if (err)
2835 goto out;
2836
7a3e97b0
SY		 2837 scsi_dma_unmap(cmd);
2838
2839 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 2840 __clear_bit(tag, &hba->outstanding_reqs);
2841 hba->lrb[tag].cmd = NULL;
2842 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 2843
2844 clear_bit_unlock(tag, &hba->lrb_in_use);
2845 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0 2846out:
f20810d8
SRT		 2847 if (!err) {
2848 err = SUCCESS;
2849 } else {
2850 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
2851 err = FAILED;
2852 }
2853
7a3e97b0
SY		 2854 return err;
2855}
2856
3441da7d
SRT		 2857/**
2858 * ufshcd_host_reset_and_restore - reset and restore host controller
2859 * @hba: per-adapter instance
2860 *
2861 * Note that host controller reset may issue DME_RESET to
2862 * local and remote (device) Uni-Pro stack and the attributes
2863 * are reset to default state.
2864 *
2865 * Returns zero on success, non-zero on failure
2866 */
2867static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
2868{
2869 int err;
2870 async_cookie_t cookie;
2871 unsigned long flags;
2872
2873 /* Reset the host controller */
2874 spin_lock_irqsave(hba->host->host_lock, flags);
2875 ufshcd_hba_stop(hba);
2876 spin_unlock_irqrestore(hba->host->host_lock, flags);
2877
2878 err = ufshcd_hba_enable(hba);
2879 if (err)
2880 goto out;
2881
2882 /* Establish the link again and restore the device */
2883 cookie = async_schedule(ufshcd_async_scan, hba);
2884 /* wait for async scan to be completed */
2885 async_synchronize_cookie(++cookie);
2886 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
2887 err = -EIO;
2888out:
2889 if (err)
2890 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
2891
2892 return err;
2893}
2894
2895/**
2896 * ufshcd_reset_and_restore - reset and re-initialize host/device
2897 * @hba: per-adapter instance
2898 *
2899 * Reset and recover device, host and re-establish link. This
2900 * is helpful to recover the communication in fatal error conditions.
2901 *
2902 * Returns zero on success, non-zero on failure
2903 */
2904static int ufshcd_reset_and_restore(struct ufs_hba *hba)
2905{
2906 int err = 0;
2907 unsigned long flags;
2908
2909 err = ufshcd_host_reset_and_restore(hba);
2910
2911 /*
2912 * After reset the door-bell might be cleared, complete
2913 * outstanding requests in s/w here.
2914 */
2915 spin_lock_irqsave(hba->host->host_lock, flags);
2916 ufshcd_transfer_req_compl(hba);
2917 ufshcd_tmc_handler(hba);
2918 spin_unlock_irqrestore(hba->host->host_lock, flags);
2919
2920 return err;
2921}
2922
2923/**
2924 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
2925 * @cmd - SCSI command pointer
2926 *
2927 * Returns SUCCESS/FAILED
2928 */
2929static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
2930{
2931 int err;
2932 unsigned long flags;
2933 struct ufs_hba *hba;
2934
2935 hba = shost_priv(cmd->device->host);
2936
2937 /*
2938 * Check if there is any race with fatal error handling.
2939 * If so, wait for it to complete. Even though fatal error
2940 * handling does reset and restore in some cases, don't assume
2941 * anything out of it. We are just avoiding race here.
2942 */
2943 do {
2944 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 2945 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 2946 hba->ufshcd_state == UFSHCD_STATE_RESET))
2947 break;
2948 spin_unlock_irqrestore(hba->host->host_lock, flags);
2949 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 2950 flush_work(&hba->eh_work);
3441da7d
SRT		 2951 } while (1);
2952
2953 hba->ufshcd_state = UFSHCD_STATE_RESET;
2954 ufshcd_set_eh_in_progress(hba);
2955 spin_unlock_irqrestore(hba->host->host_lock, flags);
2956
2957 err = ufshcd_reset_and_restore(hba);
2958
2959 spin_lock_irqsave(hba->host->host_lock, flags);
2960 if (!err) {
2961 err = SUCCESS;
2962 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
2963 } else {
2964 err = FAILED;
2965 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2966 }
2967 ufshcd_clear_eh_in_progress(hba);
2968 spin_unlock_irqrestore(hba->host->host_lock, flags);
2969
2970 return err;
2971}
2972
6ccf44fe
SJ		 2973/**
2974 * ufshcd_async_scan - asynchronous execution for link startup
2975 * @data: data pointer to pass to this function
2976 * @cookie: cookie data
2977 */
2978static void ufshcd_async_scan(void *data, async_cookie_t cookie)
2979{
2980 struct ufs_hba *hba = (struct ufs_hba *)data;
2981 int ret;
2982
2983 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 2984 if (ret)
2985 goto out;
2986
d3e89bac
SJ		 2987 ufshcd_config_max_pwr_mode(hba);
2988
5a0b0cb9
SRT		 2989 ret = ufshcd_verify_dev_init(hba);
2990 if (ret)
2991 goto out;
68078d5c
DR		 2992
2993 ret = ufshcd_complete_dev_init(hba);
2994 if (ret)
2995 goto out;
5a0b0cb9 2996
66ec6d59 2997 ufshcd_force_reset_auto_bkops(hba);
3441da7d
SRT		 2998 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
2999
3000 /* If we are in error handling context no need to scan the host */
3001 if (!ufshcd_eh_in_progress(hba)) {
3002 scsi_scan_host(hba->host);
3003 pm_runtime_put_sync(hba->dev);
3004 }
5a0b0cb9
SRT		 3005out:
3006 return;
6ccf44fe
SJ		 3007}
3008
7a3e97b0
SY		 3009static struct scsi_host_template ufshcd_driver_template = {
3010 .module = THIS_MODULE,
3011 .name = UFSHCD,
3012 .proc_name = UFSHCD,
3013 .queuecommand = ufshcd_queuecommand,
3014 .slave_alloc = ufshcd_slave_alloc,
3015 .slave_destroy = ufshcd_slave_destroy,
3016 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 3017 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
3018 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 3019 .this_id = -1,
3020 .sg_tablesize = SG_ALL,
3021 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
3022 .can_queue = UFSHCD_CAN_QUEUE,
3023};
3024
7a3e97b0
SY		 3025/**
3026 * ufshcd_suspend - suspend power management function
3b1d0580 3027 * @hba: per adapter instance
7a3e97b0
SY		 3028 * @state: power state
3029 *
3030 * Returns -ENOSYS
3031 */
3b1d0580 3032int ufshcd_suspend(struct ufs_hba *hba, pm_message_t state)
7a3e97b0
SY		 3033{
3034 /*
3035 * TODO:
3036 * 1. Block SCSI requests from SCSI midlayer
3037 * 2. Change the internal driver state to non operational
3038 * 3. Set UTRLRSR and UTMRLRSR bits to zero
3039 * 4. Wait until outstanding commands are completed
3040 * 5. Set HCE to zero to send the UFS host controller to reset state
3041 */
3042
3043 return -ENOSYS;
3044}
3b1d0580 3045EXPORT_SYMBOL_GPL(ufshcd_suspend);
7a3e97b0
SY		 3046
3047/**
3048 * ufshcd_resume - resume power management function
3b1d0580 3049 * @hba: per adapter instance
7a3e97b0
SY		 3050 *
3051 * Returns -ENOSYS
3052 */
3b1d0580 3053int ufshcd_resume(struct ufs_hba *hba)
7a3e97b0
SY		 3054{
3055 /*
3056 * TODO:
3057 * 1. Set HCE to 1, to start the UFS host controller
3058 * initialization process
3059 * 2. Set UTRLRSR and UTMRLRSR bits to 1
3060 * 3. Change the internal driver state to operational
3061 * 4. Unblock SCSI requests from SCSI midlayer
3062 */
3063
3064 return -ENOSYS;
3065}
3b1d0580
VH		 3066EXPORT_SYMBOL_GPL(ufshcd_resume);
3067
66ec6d59
SRT		 3068int ufshcd_runtime_suspend(struct ufs_hba *hba)
3069{
3070 if (!hba)
3071 return 0;
3072
3073 /*
3074 * The device is idle with no requests in the queue,
3075 * allow background operations.
3076 */
3077 return ufshcd_enable_auto_bkops(hba);
3078}
3079EXPORT_SYMBOL(ufshcd_runtime_suspend);
3080
3081int ufshcd_runtime_resume(struct ufs_hba *hba)
3082{
3083 if (!hba)
3084 return 0;
3085
3086 return ufshcd_disable_auto_bkops(hba);
3087}
3088EXPORT_SYMBOL(ufshcd_runtime_resume);
3089
3090int ufshcd_runtime_idle(struct ufs_hba *hba)
3091{
3092 return 0;
3093}
3094EXPORT_SYMBOL(ufshcd_runtime_idle);
3095
7a3e97b0 3096/**
3b1d0580 3097 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 3098 * data structure memory
3b1d0580 3099 * @hba - per adapter instance
7a3e97b0 3100 */
3b1d0580 3101void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 3102{
cfdf9c91 3103 scsi_remove_host(hba->host);
7a3e97b0 3104 /* disable interrupts */
2fbd009b 3105 ufshcd_disable_intr(hba, hba->intr_mask);
7a3e97b0 3106 ufshcd_hba_stop(hba);
7a3e97b0 3107
7a3e97b0 3108 scsi_host_put(hba->host);
3b1d0580
VH		 3109}
3110EXPORT_SYMBOL_GPL(ufshcd_remove);
3111
7a3e97b0 3112/**
3b1d0580
VH		 3113 * ufshcd_init - Driver initialization routine
3114 * @dev: pointer to device handle
3115 * @hba_handle: driver private handle
3116 * @mmio_base: base register address
3117 * @irq: Interrupt line of device
7a3e97b0
SY		 3118 * Returns 0 on success, non-zero value on failure
3119 */
3b1d0580
VH		 3120int ufshcd_init(struct device *dev, struct ufs_hba **hba_handle,
3121 void __iomem *mmio_base, unsigned int irq)
7a3e97b0
SY		 3122{
3123 struct Scsi_Host *host;
3124 struct ufs_hba *hba;
3125 int err;
3126
3b1d0580
VH		 3127 if (!dev) {
3128 dev_err(dev,
3129 "Invalid memory reference for dev is NULL\n");
3130 err = -ENODEV;
7a3e97b0
SY		 3131 goto out_error;
3132 }
3133
3b1d0580
VH		 3134 if (!mmio_base) {
3135 dev_err(dev,
3136 "Invalid memory reference for mmio_base is NULL\n");
3137 err = -ENODEV;
3138 goto out_error;
3139 }
7a3e97b0
SY		 3140
3141 host = scsi_host_alloc(&ufshcd_driver_template,
3142 sizeof(struct ufs_hba));
3143 if (!host) {
3b1d0580 3144 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 3145 err = -ENOMEM;
3b1d0580 3146 goto out_error;
7a3e97b0
SY		 3147 }
3148 hba = shost_priv(host);
7a3e97b0 3149 hba->host = host;
3b1d0580
VH		 3150 hba->dev = dev;
3151 hba->mmio_base = mmio_base;
3152 hba->irq = irq;
7a3e97b0
SY		 3153
3154 /* Read capabilities registers */
3155 ufshcd_hba_capabilities(hba);
3156
3157 /* Get UFS version supported by the controller */
3158 hba->ufs_version = ufshcd_get_ufs_version(hba);
3159
2fbd009b
SJ		 3160 /* Get Interrupt bit mask per version */
3161 hba->intr_mask = ufshcd_get_intr_mask(hba);
3162
7a3e97b0
SY		 3163 /* Allocate memory for host memory space */
3164 err = ufshcd_memory_alloc(hba);
3165 if (err) {
3b1d0580
VH		 3166 dev_err(hba->dev, "Memory allocation failed\n");
3167 goto out_disable;
7a3e97b0
SY		 3168 }
3169
3170 /* Configure LRB */
3171 ufshcd_host_memory_configure(hba);
3172
3173 host->can_queue = hba->nutrs;
3174 host->cmd_per_lun = hba->nutrs;
3175 host->max_id = UFSHCD_MAX_ID;
3176 host->max_lun = UFSHCD_MAX_LUNS;
3177 host->max_channel = UFSHCD_MAX_CHANNEL;
3178 host->unique_id = host->host_no;
3179 host->max_cmd_len = MAX_CDB_SIZE;
3180
3181 /* Initailize wait queue for task management */
e2933132
SRT		 3182 init_waitqueue_head(&hba->tm_wq);
3183 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 3184
3185 /* Initialize work queues */
e8e7f271 3186 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 3187 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 3188
6ccf44fe
SJ		 3189 /* Initialize UIC command mutex */
3190 mutex_init(&hba->uic_cmd_mutex);
3191
5a0b0cb9
SRT		 3192 /* Initialize mutex for device management commands */
3193 mutex_init(&hba->dev_cmd.lock);
3194
3195 /* Initialize device management tag acquire wait queue */
3196 init_waitqueue_head(&hba->dev_cmd.tag_wq);
3197
7a3e97b0 3198 /* IRQ registration */
2953f850 3199 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 3200 if (err) {
3b1d0580 3201 dev_err(hba->dev, "request irq failed\n");
2953f850 3202 goto out_disable;
7a3e97b0
SY		 3203 }
3204
3205 /* Enable SCSI tag mapping */
3206 err = scsi_init_shared_tag_map(host, host->can_queue);
3207 if (err) {
3b1d0580 3208 dev_err(hba->dev, "init shared queue failed\n");
2953f850 3209 goto out_disable;
7a3e97b0
SY		 3210 }
3211
3b1d0580 3212 err = scsi_add_host(host, hba->dev);
7a3e97b0 3213 if (err) {
3b1d0580 3214 dev_err(hba->dev, "scsi_add_host failed\n");
2953f850 3215 goto out_disable;
7a3e97b0
SY		 3216 }
3217
6ccf44fe
SJ		 3218 /* Host controller enable */
3219 err = ufshcd_hba_enable(hba);
7a3e97b0 3220 if (err) {
6ccf44fe 3221 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 3222 goto out_remove_scsi_host;
7a3e97b0 3223 }
6ccf44fe 3224
3b1d0580 3225 *hba_handle = hba;
7a3e97b0 3226
62694735
SRT		 3227 /* Hold auto suspend until async scan completes */
3228 pm_runtime_get_sync(dev);
3229
6ccf44fe
SJ		 3230 async_schedule(ufshcd_async_scan, hba);
3231
7a3e97b0
SY		 3232 return 0;
3233
3b1d0580
VH		 3234out_remove_scsi_host:
3235 scsi_remove_host(hba->host);
3b1d0580
VH		 3236out_disable:
3237 scsi_host_put(host);
3238out_error:
3239 return err;
3240}
3241EXPORT_SYMBOL_GPL(ufshcd_init);
3242
3b1d0580
VH		 3243MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
3244MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 3245MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 3246MODULE_LICENSE("GPL");
3247MODULE_VERSION(UFSHCD_DRIVER_VERSION);
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