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7a3e97b0 | 1 | /* |
e0eca63e | 2 | * Universal Flash Storage Host controller driver Core |
7a3e97b0 SY |
3 | * |
4 | * This code is based on drivers/scsi/ufs/ufshcd.c | |
3b1d0580 | 5 | * Copyright (C) 2011-2013 Samsung India Software Operations |
7a3e97b0 | 6 | * |
3b1d0580 VH |
7 | * Authors: |
8 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
9 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
7a3e97b0 SY |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version 2 | |
14 | * of the License, or (at your option) any later version. | |
3b1d0580 VH |
15 | * See the COPYING file in the top-level directory or visit |
16 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
7a3e97b0 SY |
17 | * |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
3b1d0580 VH |
23 | * This program is provided "AS IS" and "WITH ALL FAULTS" and |
24 | * without warranty of any kind. You are solely responsible for | |
25 | * determining the appropriateness of using and distributing | |
26 | * the program and assume all risks associated with your exercise | |
27 | * of rights with respect to the program, including but not limited | |
28 | * to infringement of third party rights, the risks and costs of | |
29 | * program errors, damage to or loss of data, programs or equipment, | |
30 | * and unavailability or interruption of operations. Under no | |
31 | * circumstances will the contributor of this Program be liable for | |
32 | * any damages of any kind arising from your use or distribution of | |
33 | * this program. | |
7a3e97b0 SY |
34 | */ |
35 | ||
6ccf44fe SJ |
36 | #include <linux/async.h> |
37 | ||
e0eca63e | 38 | #include "ufshcd.h" |
7a3e97b0 | 39 | |
2fbd009b SJ |
40 | #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ |
41 | UTP_TASK_REQ_COMPL |\ | |
42 | UFSHCD_ERROR_MASK) | |
6ccf44fe SJ |
43 | /* UIC command timeout, unit: ms */ |
44 | #define UIC_CMD_TIMEOUT 500 | |
2fbd009b | 45 | |
5a0b0cb9 SRT |
46 | /* NOP OUT retries waiting for NOP IN response */ |
47 | #define NOP_OUT_RETRIES 10 | |
48 | /* Timeout after 30 msecs if NOP OUT hangs without response */ | |
49 | #define NOP_OUT_TIMEOUT 30 /* msecs */ | |
50 | ||
68078d5c DR |
51 | /* Query request retries */ |
52 | #define QUERY_REQ_RETRIES 10 | |
53 | /* Query request timeout */ | |
54 | #define QUERY_REQ_TIMEOUT 30 /* msec */ | |
55 | ||
56 | /* Expose the flag value from utp_upiu_query.value */ | |
57 | #define MASK_QUERY_UPIU_FLAG_LOC 0xFF | |
58 | ||
7d568652 SJ |
59 | /* Interrupt aggregation default timeout, unit: 40us */ |
60 | #define INT_AGGR_DEF_TO 0x02 | |
61 | ||
7a3e97b0 SY |
62 | enum { |
63 | UFSHCD_MAX_CHANNEL = 0, | |
64 | UFSHCD_MAX_ID = 1, | |
65 | UFSHCD_MAX_LUNS = 8, | |
66 | UFSHCD_CMD_PER_LUN = 32, | |
67 | UFSHCD_CAN_QUEUE = 32, | |
68 | }; | |
69 | ||
70 | /* UFSHCD states */ | |
71 | enum { | |
72 | UFSHCD_STATE_OPERATIONAL, | |
73 | UFSHCD_STATE_RESET, | |
74 | UFSHCD_STATE_ERROR, | |
75 | }; | |
76 | ||
77 | /* Interrupt configuration options */ | |
78 | enum { | |
79 | UFSHCD_INT_DISABLE, | |
80 | UFSHCD_INT_ENABLE, | |
81 | UFSHCD_INT_CLEAR, | |
82 | }; | |
83 | ||
5a0b0cb9 SRT |
84 | /* |
85 | * ufshcd_wait_for_register - wait for register value to change | |
86 | * @hba - per-adapter interface | |
87 | * @reg - mmio register offset | |
88 | * @mask - mask to apply to read register value | |
89 | * @val - wait condition | |
90 | * @interval_us - polling interval in microsecs | |
91 | * @timeout_ms - timeout in millisecs | |
92 | * | |
93 | * Returns -ETIMEDOUT on error, zero on success | |
94 | */ | |
95 | static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, | |
96 | u32 val, unsigned long interval_us, unsigned long timeout_ms) | |
97 | { | |
98 | int err = 0; | |
99 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); | |
100 | ||
101 | /* ignore bits that we don't intend to wait on */ | |
102 | val = val & mask; | |
103 | ||
104 | while ((ufshcd_readl(hba, reg) & mask) != val) { | |
105 | /* wakeup within 50us of expiry */ | |
106 | usleep_range(interval_us, interval_us + 50); | |
107 | ||
108 | if (time_after(jiffies, timeout)) { | |
109 | if ((ufshcd_readl(hba, reg) & mask) != val) | |
110 | err = -ETIMEDOUT; | |
111 | break; | |
112 | } | |
113 | } | |
114 | ||
115 | return err; | |
116 | } | |
117 | ||
2fbd009b SJ |
118 | /** |
119 | * ufshcd_get_intr_mask - Get the interrupt bit mask | |
120 | * @hba - Pointer to adapter instance | |
121 | * | |
122 | * Returns interrupt bit mask per version | |
123 | */ | |
124 | static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) | |
125 | { | |
126 | if (hba->ufs_version == UFSHCI_VERSION_10) | |
127 | return INTERRUPT_MASK_ALL_VER_10; | |
128 | else | |
129 | return INTERRUPT_MASK_ALL_VER_11; | |
130 | } | |
131 | ||
7a3e97b0 SY |
132 | /** |
133 | * ufshcd_get_ufs_version - Get the UFS version supported by the HBA | |
134 | * @hba - Pointer to adapter instance | |
135 | * | |
136 | * Returns UFSHCI version supported by the controller | |
137 | */ | |
138 | static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) | |
139 | { | |
b873a275 | 140 | return ufshcd_readl(hba, REG_UFS_VERSION); |
7a3e97b0 SY |
141 | } |
142 | ||
143 | /** | |
144 | * ufshcd_is_device_present - Check if any device connected to | |
145 | * the host controller | |
146 | * @reg_hcs - host controller status register value | |
147 | * | |
73ec513a | 148 | * Returns 1 if device present, 0 if no device detected |
7a3e97b0 SY |
149 | */ |
150 | static inline int ufshcd_is_device_present(u32 reg_hcs) | |
151 | { | |
73ec513a | 152 | return (DEVICE_PRESENT & reg_hcs) ? 1 : 0; |
7a3e97b0 SY |
153 | } |
154 | ||
155 | /** | |
156 | * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status | |
157 | * @lrb: pointer to local command reference block | |
158 | * | |
159 | * This function is used to get the OCS field from UTRD | |
160 | * Returns the OCS field in the UTRD | |
161 | */ | |
162 | static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp) | |
163 | { | |
164 | return lrbp->utr_descriptor_ptr->header.dword_2 & MASK_OCS; | |
165 | } | |
166 | ||
167 | /** | |
168 | * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status | |
169 | * @task_req_descp: pointer to utp_task_req_desc structure | |
170 | * | |
171 | * This function is used to get the OCS field from UTMRD | |
172 | * Returns the OCS field in the UTMRD | |
173 | */ | |
174 | static inline int | |
175 | ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp) | |
176 | { | |
177 | return task_req_descp->header.dword_2 & MASK_OCS; | |
178 | } | |
179 | ||
180 | /** | |
181 | * ufshcd_get_tm_free_slot - get a free slot for task management request | |
182 | * @hba: per adapter instance | |
183 | * | |
184 | * Returns maximum number of task management request slots in case of | |
185 | * task management queue full or returns the free slot number | |
186 | */ | |
187 | static inline int ufshcd_get_tm_free_slot(struct ufs_hba *hba) | |
188 | { | |
189 | return find_first_zero_bit(&hba->outstanding_tasks, hba->nutmrs); | |
190 | } | |
191 | ||
192 | /** | |
193 | * ufshcd_utrl_clear - Clear a bit in UTRLCLR register | |
194 | * @hba: per adapter instance | |
195 | * @pos: position of the bit to be cleared | |
196 | */ | |
197 | static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos) | |
198 | { | |
b873a275 | 199 | ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR); |
7a3e97b0 SY |
200 | } |
201 | ||
202 | /** | |
203 | * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY | |
204 | * @reg: Register value of host controller status | |
205 | * | |
206 | * Returns integer, 0 on Success and positive value if failed | |
207 | */ | |
208 | static inline int ufshcd_get_lists_status(u32 reg) | |
209 | { | |
210 | /* | |
211 | * The mask 0xFF is for the following HCS register bits | |
212 | * Bit Description | |
213 | * 0 Device Present | |
214 | * 1 UTRLRDY | |
215 | * 2 UTMRLRDY | |
216 | * 3 UCRDY | |
217 | * 4 HEI | |
218 | * 5 DEI | |
219 | * 6-7 reserved | |
220 | */ | |
221 | return (((reg) & (0xFF)) >> 1) ^ (0x07); | |
222 | } | |
223 | ||
224 | /** | |
225 | * ufshcd_get_uic_cmd_result - Get the UIC command result | |
226 | * @hba: Pointer to adapter instance | |
227 | * | |
228 | * This function gets the result of UIC command completion | |
229 | * Returns 0 on success, non zero value on error | |
230 | */ | |
231 | static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) | |
232 | { | |
b873a275 | 233 | return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & |
7a3e97b0 SY |
234 | MASK_UIC_COMMAND_RESULT; |
235 | } | |
236 | ||
7a3e97b0 | 237 | /** |
5a0b0cb9 | 238 | * ufshcd_get_req_rsp - returns the TR response transaction type |
7a3e97b0 | 239 | * @ucd_rsp_ptr: pointer to response UPIU |
7a3e97b0 SY |
240 | */ |
241 | static inline int | |
5a0b0cb9 | 242 | ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) |
7a3e97b0 | 243 | { |
5a0b0cb9 | 244 | return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; |
7a3e97b0 SY |
245 | } |
246 | ||
247 | /** | |
248 | * ufshcd_get_rsp_upiu_result - Get the result from response UPIU | |
249 | * @ucd_rsp_ptr: pointer to response UPIU | |
250 | * | |
251 | * This function gets the response status and scsi_status from response UPIU | |
252 | * Returns the response result code. | |
253 | */ | |
254 | static inline int | |
255 | ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) | |
256 | { | |
257 | return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; | |
258 | } | |
259 | ||
1c2623c5 SJ |
260 | /* |
261 | * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length | |
262 | * from response UPIU | |
263 | * @ucd_rsp_ptr: pointer to response UPIU | |
264 | * | |
265 | * Return the data segment length. | |
266 | */ | |
267 | static inline unsigned int | |
268 | ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr) | |
269 | { | |
270 | return be32_to_cpu(ucd_rsp_ptr->header.dword_2) & | |
271 | MASK_RSP_UPIU_DATA_SEG_LEN; | |
272 | } | |
273 | ||
66ec6d59 SRT |
274 | /** |
275 | * ufshcd_is_exception_event - Check if the device raised an exception event | |
276 | * @ucd_rsp_ptr: pointer to response UPIU | |
277 | * | |
278 | * The function checks if the device raised an exception event indicated in | |
279 | * the Device Information field of response UPIU. | |
280 | * | |
281 | * Returns true if exception is raised, false otherwise. | |
282 | */ | |
283 | static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) | |
284 | { | |
285 | return be32_to_cpu(ucd_rsp_ptr->header.dword_2) & | |
286 | MASK_RSP_EXCEPTION_EVENT ? true : false; | |
287 | } | |
288 | ||
7a3e97b0 | 289 | /** |
7d568652 | 290 | * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. |
7a3e97b0 | 291 | * @hba: per adapter instance |
7a3e97b0 SY |
292 | */ |
293 | static inline void | |
7d568652 | 294 | ufshcd_reset_intr_aggr(struct ufs_hba *hba) |
7a3e97b0 | 295 | { |
7d568652 SJ |
296 | ufshcd_writel(hba, INT_AGGR_ENABLE | |
297 | INT_AGGR_COUNTER_AND_TIMER_RESET, | |
298 | REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); | |
299 | } | |
300 | ||
301 | /** | |
302 | * ufshcd_config_intr_aggr - Configure interrupt aggregation values. | |
303 | * @hba: per adapter instance | |
304 | * @cnt: Interrupt aggregation counter threshold | |
305 | * @tmout: Interrupt aggregation timeout value | |
306 | */ | |
307 | static inline void | |
308 | ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) | |
309 | { | |
310 | ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | | |
311 | INT_AGGR_COUNTER_THLD_VAL(cnt) | | |
312 | INT_AGGR_TIMEOUT_VAL(tmout), | |
313 | REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); | |
7a3e97b0 SY |
314 | } |
315 | ||
316 | /** | |
317 | * ufshcd_enable_run_stop_reg - Enable run-stop registers, | |
318 | * When run-stop registers are set to 1, it indicates the | |
319 | * host controller that it can process the requests | |
320 | * @hba: per adapter instance | |
321 | */ | |
322 | static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) | |
323 | { | |
b873a275 SJ |
324 | ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, |
325 | REG_UTP_TASK_REQ_LIST_RUN_STOP); | |
326 | ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, | |
327 | REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); | |
7a3e97b0 SY |
328 | } |
329 | ||
7a3e97b0 SY |
330 | /** |
331 | * ufshcd_hba_start - Start controller initialization sequence | |
332 | * @hba: per adapter instance | |
333 | */ | |
334 | static inline void ufshcd_hba_start(struct ufs_hba *hba) | |
335 | { | |
b873a275 | 336 | ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); |
7a3e97b0 SY |
337 | } |
338 | ||
339 | /** | |
340 | * ufshcd_is_hba_active - Get controller state | |
341 | * @hba: per adapter instance | |
342 | * | |
343 | * Returns zero if controller is active, 1 otherwise | |
344 | */ | |
345 | static inline int ufshcd_is_hba_active(struct ufs_hba *hba) | |
346 | { | |
b873a275 | 347 | return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1; |
7a3e97b0 SY |
348 | } |
349 | ||
350 | /** | |
351 | * ufshcd_send_command - Send SCSI or device management commands | |
352 | * @hba: per adapter instance | |
353 | * @task_tag: Task tag of the command | |
354 | */ | |
355 | static inline | |
356 | void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) | |
357 | { | |
358 | __set_bit(task_tag, &hba->outstanding_reqs); | |
b873a275 | 359 | ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); |
7a3e97b0 SY |
360 | } |
361 | ||
362 | /** | |
363 | * ufshcd_copy_sense_data - Copy sense data in case of check condition | |
364 | * @lrb - pointer to local reference block | |
365 | */ | |
366 | static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) | |
367 | { | |
368 | int len; | |
1c2623c5 SJ |
369 | if (lrbp->sense_buffer && |
370 | ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) { | |
5a0b0cb9 | 371 | len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); |
7a3e97b0 | 372 | memcpy(lrbp->sense_buffer, |
5a0b0cb9 | 373 | lrbp->ucd_rsp_ptr->sr.sense_data, |
7a3e97b0 SY |
374 | min_t(int, len, SCSI_SENSE_BUFFERSIZE)); |
375 | } | |
376 | } | |
377 | ||
68078d5c DR |
378 | /** |
379 | * ufshcd_query_to_cpu() - formats the buffer to native cpu endian | |
380 | * @response: upiu query response to convert | |
381 | */ | |
382 | static inline void ufshcd_query_to_cpu(struct utp_upiu_query *response) | |
383 | { | |
384 | response->length = be16_to_cpu(response->length); | |
385 | response->value = be32_to_cpu(response->value); | |
386 | } | |
387 | ||
388 | /** | |
389 | * ufshcd_query_to_be() - formats the buffer to big endian | |
390 | * @request: upiu query request to convert | |
391 | */ | |
392 | static inline void ufshcd_query_to_be(struct utp_upiu_query *request) | |
393 | { | |
394 | request->length = cpu_to_be16(request->length); | |
395 | request->value = cpu_to_be32(request->value); | |
396 | } | |
397 | ||
398 | /** | |
399 | * ufshcd_copy_query_response() - Copy the Query Response and the data | |
400 | * descriptor | |
401 | * @hba: per adapter instance | |
402 | * @lrb - pointer to local reference block | |
403 | */ | |
404 | static | |
405 | void ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
406 | { | |
407 | struct ufs_query_res *query_res = &hba->dev_cmd.query.response; | |
408 | ||
409 | /* Get the UPIU response */ | |
410 | query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >> | |
411 | UPIU_RSP_CODE_OFFSET; | |
412 | ||
413 | memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); | |
414 | ufshcd_query_to_cpu(&query_res->upiu_res); | |
415 | ||
416 | ||
417 | /* Get the descriptor */ | |
418 | if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { | |
419 | u8 *descp = (u8 *)&lrbp->ucd_rsp_ptr + | |
420 | GENERAL_UPIU_REQUEST_SIZE; | |
421 | u16 len; | |
422 | ||
423 | /* data segment length */ | |
424 | len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) & | |
425 | MASK_QUERY_DATA_SEG_LEN; | |
426 | ||
427 | memcpy(hba->dev_cmd.query.descriptor, descp, | |
428 | min_t(u16, len, QUERY_DESC_MAX_SIZE)); | |
429 | } | |
430 | } | |
431 | ||
7a3e97b0 SY |
432 | /** |
433 | * ufshcd_hba_capabilities - Read controller capabilities | |
434 | * @hba: per adapter instance | |
435 | */ | |
436 | static inline void ufshcd_hba_capabilities(struct ufs_hba *hba) | |
437 | { | |
b873a275 | 438 | hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); |
7a3e97b0 SY |
439 | |
440 | /* nutrs and nutmrs are 0 based values */ | |
441 | hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; | |
442 | hba->nutmrs = | |
443 | ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; | |
444 | } | |
445 | ||
446 | /** | |
6ccf44fe SJ |
447 | * ufshcd_ready_for_uic_cmd - Check if controller is ready |
448 | * to accept UIC commands | |
7a3e97b0 | 449 | * @hba: per adapter instance |
6ccf44fe SJ |
450 | * Return true on success, else false |
451 | */ | |
452 | static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) | |
453 | { | |
454 | if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) | |
455 | return true; | |
456 | else | |
457 | return false; | |
458 | } | |
459 | ||
460 | /** | |
461 | * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers | |
462 | * @hba: per adapter instance | |
463 | * @uic_cmd: UIC command | |
464 | * | |
465 | * Mutex must be held. | |
7a3e97b0 SY |
466 | */ |
467 | static inline void | |
6ccf44fe | 468 | ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) |
7a3e97b0 | 469 | { |
6ccf44fe SJ |
470 | WARN_ON(hba->active_uic_cmd); |
471 | ||
472 | hba->active_uic_cmd = uic_cmd; | |
473 | ||
7a3e97b0 | 474 | /* Write Args */ |
6ccf44fe SJ |
475 | ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); |
476 | ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); | |
477 | ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); | |
7a3e97b0 SY |
478 | |
479 | /* Write UIC Cmd */ | |
6ccf44fe | 480 | ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, |
b873a275 | 481 | REG_UIC_COMMAND); |
7a3e97b0 SY |
482 | } |
483 | ||
6ccf44fe SJ |
484 | /** |
485 | * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command | |
486 | * @hba: per adapter instance | |
487 | * @uic_command: UIC command | |
488 | * | |
489 | * Must be called with mutex held. | |
490 | * Returns 0 only if success. | |
491 | */ | |
492 | static int | |
493 | ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
494 | { | |
495 | int ret; | |
496 | unsigned long flags; | |
497 | ||
498 | if (wait_for_completion_timeout(&uic_cmd->done, | |
499 | msecs_to_jiffies(UIC_CMD_TIMEOUT))) | |
500 | ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; | |
501 | else | |
502 | ret = -ETIMEDOUT; | |
503 | ||
504 | spin_lock_irqsave(hba->host->host_lock, flags); | |
505 | hba->active_uic_cmd = NULL; | |
506 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
507 | ||
508 | return ret; | |
509 | } | |
510 | ||
511 | /** | |
512 | * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result | |
513 | * @hba: per adapter instance | |
514 | * @uic_cmd: UIC command | |
515 | * | |
516 | * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called | |
517 | * with mutex held. | |
518 | * Returns 0 only if success. | |
519 | */ | |
520 | static int | |
521 | __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
522 | { | |
523 | int ret; | |
524 | unsigned long flags; | |
525 | ||
526 | if (!ufshcd_ready_for_uic_cmd(hba)) { | |
527 | dev_err(hba->dev, | |
528 | "Controller not ready to accept UIC commands\n"); | |
529 | return -EIO; | |
530 | } | |
531 | ||
532 | init_completion(&uic_cmd->done); | |
533 | ||
534 | spin_lock_irqsave(hba->host->host_lock, flags); | |
535 | ufshcd_dispatch_uic_cmd(hba, uic_cmd); | |
536 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
537 | ||
538 | ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); | |
539 | ||
540 | return ret; | |
541 | } | |
542 | ||
543 | /** | |
544 | * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result | |
545 | * @hba: per adapter instance | |
546 | * @uic_cmd: UIC command | |
547 | * | |
548 | * Returns 0 only if success. | |
549 | */ | |
550 | static int | |
551 | ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
552 | { | |
553 | int ret; | |
554 | ||
555 | mutex_lock(&hba->uic_cmd_mutex); | |
556 | ret = __ufshcd_send_uic_cmd(hba, uic_cmd); | |
557 | mutex_unlock(&hba->uic_cmd_mutex); | |
558 | ||
559 | return ret; | |
560 | } | |
561 | ||
7a3e97b0 SY |
562 | /** |
563 | * ufshcd_map_sg - Map scatter-gather list to prdt | |
564 | * @lrbp - pointer to local reference block | |
565 | * | |
566 | * Returns 0 in case of success, non-zero value in case of failure | |
567 | */ | |
568 | static int ufshcd_map_sg(struct ufshcd_lrb *lrbp) | |
569 | { | |
570 | struct ufshcd_sg_entry *prd_table; | |
571 | struct scatterlist *sg; | |
572 | struct scsi_cmnd *cmd; | |
573 | int sg_segments; | |
574 | int i; | |
575 | ||
576 | cmd = lrbp->cmd; | |
577 | sg_segments = scsi_dma_map(cmd); | |
578 | if (sg_segments < 0) | |
579 | return sg_segments; | |
580 | ||
581 | if (sg_segments) { | |
582 | lrbp->utr_descriptor_ptr->prd_table_length = | |
583 | cpu_to_le16((u16) (sg_segments)); | |
584 | ||
585 | prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr; | |
586 | ||
587 | scsi_for_each_sg(cmd, sg, sg_segments, i) { | |
588 | prd_table[i].size = | |
589 | cpu_to_le32(((u32) sg_dma_len(sg))-1); | |
590 | prd_table[i].base_addr = | |
591 | cpu_to_le32(lower_32_bits(sg->dma_address)); | |
592 | prd_table[i].upper_addr = | |
593 | cpu_to_le32(upper_32_bits(sg->dma_address)); | |
594 | } | |
595 | } else { | |
596 | lrbp->utr_descriptor_ptr->prd_table_length = 0; | |
597 | } | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | /** | |
2fbd009b | 603 | * ufshcd_enable_intr - enable interrupts |
7a3e97b0 | 604 | * @hba: per adapter instance |
2fbd009b | 605 | * @intrs: interrupt bits |
7a3e97b0 | 606 | */ |
2fbd009b | 607 | static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) |
7a3e97b0 | 608 | { |
2fbd009b SJ |
609 | u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); |
610 | ||
611 | if (hba->ufs_version == UFSHCI_VERSION_10) { | |
612 | u32 rw; | |
613 | rw = set & INTERRUPT_MASK_RW_VER_10; | |
614 | set = rw | ((set ^ intrs) & intrs); | |
615 | } else { | |
616 | set |= intrs; | |
617 | } | |
618 | ||
619 | ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); | |
620 | } | |
621 | ||
622 | /** | |
623 | * ufshcd_disable_intr - disable interrupts | |
624 | * @hba: per adapter instance | |
625 | * @intrs: interrupt bits | |
626 | */ | |
627 | static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) | |
628 | { | |
629 | u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); | |
630 | ||
631 | if (hba->ufs_version == UFSHCI_VERSION_10) { | |
632 | u32 rw; | |
633 | rw = (set & INTERRUPT_MASK_RW_VER_10) & | |
634 | ~(intrs & INTERRUPT_MASK_RW_VER_10); | |
635 | set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10); | |
636 | ||
637 | } else { | |
638 | set &= ~intrs; | |
7a3e97b0 | 639 | } |
2fbd009b SJ |
640 | |
641 | ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); | |
7a3e97b0 SY |
642 | } |
643 | ||
5a0b0cb9 SRT |
644 | /** |
645 | * ufshcd_prepare_req_desc_hdr() - Fills the requests header | |
646 | * descriptor according to request | |
647 | * @lrbp: pointer to local reference block | |
648 | * @upiu_flags: flags required in the header | |
649 | * @cmd_dir: requests data direction | |
650 | */ | |
651 | static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, | |
652 | u32 *upiu_flags, enum dma_data_direction cmd_dir) | |
653 | { | |
654 | struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; | |
655 | u32 data_direction; | |
656 | u32 dword_0; | |
657 | ||
658 | if (cmd_dir == DMA_FROM_DEVICE) { | |
659 | data_direction = UTP_DEVICE_TO_HOST; | |
660 | *upiu_flags = UPIU_CMD_FLAGS_READ; | |
661 | } else if (cmd_dir == DMA_TO_DEVICE) { | |
662 | data_direction = UTP_HOST_TO_DEVICE; | |
663 | *upiu_flags = UPIU_CMD_FLAGS_WRITE; | |
664 | } else { | |
665 | data_direction = UTP_NO_DATA_TRANSFER; | |
666 | *upiu_flags = UPIU_CMD_FLAGS_NONE; | |
667 | } | |
668 | ||
669 | dword_0 = data_direction | (lrbp->command_type | |
670 | << UPIU_COMMAND_TYPE_OFFSET); | |
671 | if (lrbp->intr_cmd) | |
672 | dword_0 |= UTP_REQ_DESC_INT_CMD; | |
673 | ||
674 | /* Transfer request descriptor header fields */ | |
675 | req_desc->header.dword_0 = cpu_to_le32(dword_0); | |
676 | ||
677 | /* | |
678 | * assigning invalid value for command status. Controller | |
679 | * updates OCS on command completion, with the command | |
680 | * status | |
681 | */ | |
682 | req_desc->header.dword_2 = | |
683 | cpu_to_le32(OCS_INVALID_COMMAND_STATUS); | |
684 | } | |
685 | ||
686 | /** | |
687 | * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, | |
688 | * for scsi commands | |
689 | * @lrbp - local reference block pointer | |
690 | * @upiu_flags - flags | |
691 | */ | |
692 | static | |
693 | void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags) | |
694 | { | |
695 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
696 | ||
697 | /* command descriptor fields */ | |
698 | ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( | |
699 | UPIU_TRANSACTION_COMMAND, upiu_flags, | |
700 | lrbp->lun, lrbp->task_tag); | |
701 | ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD( | |
702 | UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); | |
703 | ||
704 | /* Total EHS length and Data segment length will be zero */ | |
705 | ucd_req_ptr->header.dword_2 = 0; | |
706 | ||
707 | ucd_req_ptr->sc.exp_data_transfer_len = | |
708 | cpu_to_be32(lrbp->cmd->sdb.length); | |
709 | ||
710 | memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, | |
711 | (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE))); | |
712 | } | |
713 | ||
68078d5c DR |
714 | /** |
715 | * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc, | |
716 | * for query requsts | |
717 | * @hba: UFS hba | |
718 | * @lrbp: local reference block pointer | |
719 | * @upiu_flags: flags | |
720 | */ | |
721 | static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, | |
722 | struct ufshcd_lrb *lrbp, u32 upiu_flags) | |
723 | { | |
724 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
725 | struct ufs_query *query = &hba->dev_cmd.query; | |
726 | u16 len = query->request.upiu_req.length; | |
727 | u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE; | |
728 | ||
729 | /* Query request header */ | |
730 | ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( | |
731 | UPIU_TRANSACTION_QUERY_REQ, upiu_flags, | |
732 | lrbp->lun, lrbp->task_tag); | |
733 | ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD( | |
734 | 0, query->request.query_func, 0, 0); | |
735 | ||
736 | /* Data segment length */ | |
737 | ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD( | |
738 | 0, 0, len >> 8, (u8)len); | |
739 | ||
740 | /* Copy the Query Request buffer as is */ | |
741 | memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, | |
742 | QUERY_OSF_SIZE); | |
743 | ufshcd_query_to_be(&ucd_req_ptr->qr); | |
744 | ||
745 | /* Copy the Descriptor */ | |
746 | if ((len > 0) && (query->request.upiu_req.opcode == | |
747 | UPIU_QUERY_OPCODE_WRITE_DESC)) { | |
748 | memcpy(descp, query->descriptor, | |
749 | min_t(u16, len, QUERY_DESC_MAX_SIZE)); | |
750 | } | |
751 | } | |
752 | ||
5a0b0cb9 SRT |
753 | static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) |
754 | { | |
755 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
756 | ||
757 | memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); | |
758 | ||
759 | /* command descriptor fields */ | |
760 | ucd_req_ptr->header.dword_0 = | |
761 | UPIU_HEADER_DWORD( | |
762 | UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag); | |
763 | } | |
764 | ||
7a3e97b0 SY |
765 | /** |
766 | * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU) | |
5a0b0cb9 | 767 | * @hba - per adapter instance |
7a3e97b0 SY |
768 | * @lrb - pointer to local reference block |
769 | */ | |
5a0b0cb9 | 770 | static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) |
7a3e97b0 | 771 | { |
7a3e97b0 | 772 | u32 upiu_flags; |
5a0b0cb9 | 773 | int ret = 0; |
7a3e97b0 SY |
774 | |
775 | switch (lrbp->command_type) { | |
776 | case UTP_CMD_TYPE_SCSI: | |
5a0b0cb9 SRT |
777 | if (likely(lrbp->cmd)) { |
778 | ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, | |
779 | lrbp->cmd->sc_data_direction); | |
780 | ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); | |
7a3e97b0 | 781 | } else { |
5a0b0cb9 | 782 | ret = -EINVAL; |
7a3e97b0 | 783 | } |
7a3e97b0 SY |
784 | break; |
785 | case UTP_CMD_TYPE_DEV_MANAGE: | |
5a0b0cb9 | 786 | ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE); |
68078d5c DR |
787 | if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) |
788 | ufshcd_prepare_utp_query_req_upiu( | |
789 | hba, lrbp, upiu_flags); | |
790 | else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) | |
5a0b0cb9 SRT |
791 | ufshcd_prepare_utp_nop_upiu(lrbp); |
792 | else | |
793 | ret = -EINVAL; | |
7a3e97b0 SY |
794 | break; |
795 | case UTP_CMD_TYPE_UFS: | |
796 | /* For UFS native command implementation */ | |
5a0b0cb9 SRT |
797 | ret = -ENOTSUPP; |
798 | dev_err(hba->dev, "%s: UFS native command are not supported\n", | |
799 | __func__); | |
800 | break; | |
801 | default: | |
802 | ret = -ENOTSUPP; | |
803 | dev_err(hba->dev, "%s: unknown command type: 0x%x\n", | |
804 | __func__, lrbp->command_type); | |
7a3e97b0 SY |
805 | break; |
806 | } /* end of switch */ | |
5a0b0cb9 SRT |
807 | |
808 | return ret; | |
7a3e97b0 SY |
809 | } |
810 | ||
811 | /** | |
812 | * ufshcd_queuecommand - main entry point for SCSI requests | |
813 | * @cmd: command from SCSI Midlayer | |
814 | * @done: call back function | |
815 | * | |
816 | * Returns 0 for success, non-zero in case of failure | |
817 | */ | |
818 | static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) | |
819 | { | |
820 | struct ufshcd_lrb *lrbp; | |
821 | struct ufs_hba *hba; | |
822 | unsigned long flags; | |
823 | int tag; | |
824 | int err = 0; | |
825 | ||
826 | hba = shost_priv(host); | |
827 | ||
828 | tag = cmd->request->tag; | |
829 | ||
830 | if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { | |
831 | err = SCSI_MLQUEUE_HOST_BUSY; | |
832 | goto out; | |
833 | } | |
834 | ||
5a0b0cb9 SRT |
835 | /* acquire the tag to make sure device cmds don't use it */ |
836 | if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) { | |
837 | /* | |
838 | * Dev manage command in progress, requeue the command. | |
839 | * Requeuing the command helps in cases where the request *may* | |
840 | * find different tag instead of waiting for dev manage command | |
841 | * completion. | |
842 | */ | |
843 | err = SCSI_MLQUEUE_HOST_BUSY; | |
844 | goto out; | |
845 | } | |
846 | ||
7a3e97b0 SY |
847 | lrbp = &hba->lrb[tag]; |
848 | ||
5a0b0cb9 | 849 | WARN_ON(lrbp->cmd); |
7a3e97b0 SY |
850 | lrbp->cmd = cmd; |
851 | lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE; | |
852 | lrbp->sense_buffer = cmd->sense_buffer; | |
853 | lrbp->task_tag = tag; | |
854 | lrbp->lun = cmd->device->lun; | |
5a0b0cb9 | 855 | lrbp->intr_cmd = false; |
7a3e97b0 SY |
856 | lrbp->command_type = UTP_CMD_TYPE_SCSI; |
857 | ||
858 | /* form UPIU before issuing the command */ | |
5a0b0cb9 | 859 | ufshcd_compose_upiu(hba, lrbp); |
7a3e97b0 | 860 | err = ufshcd_map_sg(lrbp); |
5a0b0cb9 SRT |
861 | if (err) { |
862 | lrbp->cmd = NULL; | |
863 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
7a3e97b0 | 864 | goto out; |
5a0b0cb9 | 865 | } |
7a3e97b0 SY |
866 | |
867 | /* issue command to the controller */ | |
868 | spin_lock_irqsave(hba->host->host_lock, flags); | |
869 | ufshcd_send_command(hba, tag); | |
870 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
871 | out: | |
872 | return err; | |
873 | } | |
874 | ||
5a0b0cb9 SRT |
875 | static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, |
876 | struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) | |
877 | { | |
878 | lrbp->cmd = NULL; | |
879 | lrbp->sense_bufflen = 0; | |
880 | lrbp->sense_buffer = NULL; | |
881 | lrbp->task_tag = tag; | |
882 | lrbp->lun = 0; /* device management cmd is not specific to any LUN */ | |
883 | lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; | |
884 | lrbp->intr_cmd = true; /* No interrupt aggregation */ | |
885 | hba->dev_cmd.type = cmd_type; | |
886 | ||
887 | return ufshcd_compose_upiu(hba, lrbp); | |
888 | } | |
889 | ||
890 | static int | |
891 | ufshcd_clear_cmd(struct ufs_hba *hba, int tag) | |
892 | { | |
893 | int err = 0; | |
894 | unsigned long flags; | |
895 | u32 mask = 1 << tag; | |
896 | ||
897 | /* clear outstanding transaction before retry */ | |
898 | spin_lock_irqsave(hba->host->host_lock, flags); | |
899 | ufshcd_utrl_clear(hba, tag); | |
900 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
901 | ||
902 | /* | |
903 | * wait for for h/w to clear corresponding bit in door-bell. | |
904 | * max. wait is 1 sec. | |
905 | */ | |
906 | err = ufshcd_wait_for_register(hba, | |
907 | REG_UTP_TRANSFER_REQ_DOOR_BELL, | |
908 | mask, ~mask, 1000, 1000); | |
909 | ||
910 | return err; | |
911 | } | |
912 | ||
913 | /** | |
914 | * ufshcd_dev_cmd_completion() - handles device management command responses | |
915 | * @hba: per adapter instance | |
916 | * @lrbp: pointer to local reference block | |
917 | */ | |
918 | static int | |
919 | ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
920 | { | |
921 | int resp; | |
922 | int err = 0; | |
923 | ||
924 | resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); | |
925 | ||
926 | switch (resp) { | |
927 | case UPIU_TRANSACTION_NOP_IN: | |
928 | if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { | |
929 | err = -EINVAL; | |
930 | dev_err(hba->dev, "%s: unexpected response %x\n", | |
931 | __func__, resp); | |
932 | } | |
933 | break; | |
68078d5c DR |
934 | case UPIU_TRANSACTION_QUERY_RSP: |
935 | ufshcd_copy_query_response(hba, lrbp); | |
936 | break; | |
5a0b0cb9 SRT |
937 | case UPIU_TRANSACTION_REJECT_UPIU: |
938 | /* TODO: handle Reject UPIU Response */ | |
939 | err = -EPERM; | |
940 | dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", | |
941 | __func__); | |
942 | break; | |
943 | default: | |
944 | err = -EINVAL; | |
945 | dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", | |
946 | __func__, resp); | |
947 | break; | |
948 | } | |
949 | ||
950 | return err; | |
951 | } | |
952 | ||
953 | static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, | |
954 | struct ufshcd_lrb *lrbp, int max_timeout) | |
955 | { | |
956 | int err = 0; | |
957 | unsigned long time_left; | |
958 | unsigned long flags; | |
959 | ||
960 | time_left = wait_for_completion_timeout(hba->dev_cmd.complete, | |
961 | msecs_to_jiffies(max_timeout)); | |
962 | ||
963 | spin_lock_irqsave(hba->host->host_lock, flags); | |
964 | hba->dev_cmd.complete = NULL; | |
965 | if (likely(time_left)) { | |
966 | err = ufshcd_get_tr_ocs(lrbp); | |
967 | if (!err) | |
968 | err = ufshcd_dev_cmd_completion(hba, lrbp); | |
969 | } | |
970 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
971 | ||
972 | if (!time_left) { | |
973 | err = -ETIMEDOUT; | |
974 | if (!ufshcd_clear_cmd(hba, lrbp->task_tag)) | |
975 | /* sucessfully cleared the command, retry if needed */ | |
976 | err = -EAGAIN; | |
977 | } | |
978 | ||
979 | return err; | |
980 | } | |
981 | ||
982 | /** | |
983 | * ufshcd_get_dev_cmd_tag - Get device management command tag | |
984 | * @hba: per-adapter instance | |
985 | * @tag: pointer to variable with available slot value | |
986 | * | |
987 | * Get a free slot and lock it until device management command | |
988 | * completes. | |
989 | * | |
990 | * Returns false if free slot is unavailable for locking, else | |
991 | * return true with tag value in @tag. | |
992 | */ | |
993 | static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out) | |
994 | { | |
995 | int tag; | |
996 | bool ret = false; | |
997 | unsigned long tmp; | |
998 | ||
999 | if (!tag_out) | |
1000 | goto out; | |
1001 | ||
1002 | do { | |
1003 | tmp = ~hba->lrb_in_use; | |
1004 | tag = find_last_bit(&tmp, hba->nutrs); | |
1005 | if (tag >= hba->nutrs) | |
1006 | goto out; | |
1007 | } while (test_and_set_bit_lock(tag, &hba->lrb_in_use)); | |
1008 | ||
1009 | *tag_out = tag; | |
1010 | ret = true; | |
1011 | out: | |
1012 | return ret; | |
1013 | } | |
1014 | ||
1015 | static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag) | |
1016 | { | |
1017 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
1018 | } | |
1019 | ||
1020 | /** | |
1021 | * ufshcd_exec_dev_cmd - API for sending device management requests | |
1022 | * @hba - UFS hba | |
1023 | * @cmd_type - specifies the type (NOP, Query...) | |
1024 | * @timeout - time in seconds | |
1025 | * | |
68078d5c DR |
1026 | * NOTE: Since there is only one available tag for device management commands, |
1027 | * it is expected you hold the hba->dev_cmd.lock mutex. | |
5a0b0cb9 SRT |
1028 | */ |
1029 | static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, | |
1030 | enum dev_cmd_type cmd_type, int timeout) | |
1031 | { | |
1032 | struct ufshcd_lrb *lrbp; | |
1033 | int err; | |
1034 | int tag; | |
1035 | struct completion wait; | |
1036 | unsigned long flags; | |
1037 | ||
1038 | /* | |
1039 | * Get free slot, sleep if slots are unavailable. | |
1040 | * Even though we use wait_event() which sleeps indefinitely, | |
1041 | * the maximum wait time is bounded by SCSI request timeout. | |
1042 | */ | |
1043 | wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag)); | |
1044 | ||
1045 | init_completion(&wait); | |
1046 | lrbp = &hba->lrb[tag]; | |
1047 | WARN_ON(lrbp->cmd); | |
1048 | err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); | |
1049 | if (unlikely(err)) | |
1050 | goto out_put_tag; | |
1051 | ||
1052 | hba->dev_cmd.complete = &wait; | |
1053 | ||
1054 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1055 | ufshcd_send_command(hba, tag); | |
1056 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1057 | ||
1058 | err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); | |
1059 | ||
1060 | out_put_tag: | |
1061 | ufshcd_put_dev_cmd_tag(hba, tag); | |
1062 | wake_up(&hba->dev_cmd.tag_wq); | |
1063 | return err; | |
1064 | } | |
1065 | ||
68078d5c DR |
1066 | /** |
1067 | * ufshcd_query_flag() - API function for sending flag query requests | |
1068 | * hba: per-adapter instance | |
1069 | * query_opcode: flag query to perform | |
1070 | * idn: flag idn to access | |
1071 | * flag_res: the flag value after the query request completes | |
1072 | * | |
1073 | * Returns 0 for success, non-zero in case of failure | |
1074 | */ | |
1075 | static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, | |
1076 | enum flag_idn idn, bool *flag_res) | |
1077 | { | |
1078 | struct ufs_query_req *request; | |
1079 | struct ufs_query_res *response; | |
1080 | int err; | |
1081 | ||
1082 | BUG_ON(!hba); | |
1083 | ||
1084 | mutex_lock(&hba->dev_cmd.lock); | |
1085 | request = &hba->dev_cmd.query.request; | |
1086 | response = &hba->dev_cmd.query.response; | |
1087 | memset(request, 0, sizeof(struct ufs_query_req)); | |
1088 | memset(response, 0, sizeof(struct ufs_query_res)); | |
1089 | ||
1090 | switch (opcode) { | |
1091 | case UPIU_QUERY_OPCODE_SET_FLAG: | |
1092 | case UPIU_QUERY_OPCODE_CLEAR_FLAG: | |
1093 | case UPIU_QUERY_OPCODE_TOGGLE_FLAG: | |
1094 | request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; | |
1095 | break; | |
1096 | case UPIU_QUERY_OPCODE_READ_FLAG: | |
1097 | request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; | |
1098 | if (!flag_res) { | |
1099 | /* No dummy reads */ | |
1100 | dev_err(hba->dev, "%s: Invalid argument for read request\n", | |
1101 | __func__); | |
1102 | err = -EINVAL; | |
1103 | goto out_unlock; | |
1104 | } | |
1105 | break; | |
1106 | default: | |
1107 | dev_err(hba->dev, | |
1108 | "%s: Expected query flag opcode but got = %d\n", | |
1109 | __func__, opcode); | |
1110 | err = -EINVAL; | |
1111 | goto out_unlock; | |
1112 | } | |
1113 | request->upiu_req.opcode = opcode; | |
1114 | request->upiu_req.idn = idn; | |
1115 | ||
1116 | /* Send query request */ | |
1117 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, | |
1118 | QUERY_REQ_TIMEOUT); | |
1119 | ||
1120 | if (err) { | |
1121 | dev_err(hba->dev, | |
1122 | "%s: Sending flag query for idn %d failed, err = %d\n", | |
1123 | __func__, idn, err); | |
1124 | goto out_unlock; | |
1125 | } | |
1126 | ||
1127 | if (flag_res) | |
1128 | *flag_res = (response->upiu_res.value & | |
1129 | MASK_QUERY_UPIU_FLAG_LOC) & 0x1; | |
1130 | ||
1131 | out_unlock: | |
1132 | mutex_unlock(&hba->dev_cmd.lock); | |
1133 | return err; | |
1134 | } | |
1135 | ||
66ec6d59 SRT |
1136 | /** |
1137 | * ufshcd_query_attr - API function for sending attribute requests | |
1138 | * hba: per-adapter instance | |
1139 | * opcode: attribute opcode | |
1140 | * idn: attribute idn to access | |
1141 | * index: index field | |
1142 | * selector: selector field | |
1143 | * attr_val: the attribute value after the query request completes | |
1144 | * | |
1145 | * Returns 0 for success, non-zero in case of failure | |
1146 | */ | |
1147 | int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, | |
1148 | enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) | |
1149 | { | |
1150 | struct ufs_query_req *request; | |
1151 | struct ufs_query_res *response; | |
1152 | int err; | |
1153 | ||
1154 | BUG_ON(!hba); | |
1155 | ||
1156 | if (!attr_val) { | |
1157 | dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", | |
1158 | __func__, opcode); | |
1159 | err = -EINVAL; | |
1160 | goto out; | |
1161 | } | |
1162 | ||
1163 | mutex_lock(&hba->dev_cmd.lock); | |
1164 | request = &hba->dev_cmd.query.request; | |
1165 | response = &hba->dev_cmd.query.response; | |
1166 | memset(request, 0, sizeof(struct ufs_query_req)); | |
1167 | memset(response, 0, sizeof(struct ufs_query_res)); | |
1168 | ||
1169 | switch (opcode) { | |
1170 | case UPIU_QUERY_OPCODE_WRITE_ATTR: | |
1171 | request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; | |
1172 | request->upiu_req.value = *attr_val; | |
1173 | break; | |
1174 | case UPIU_QUERY_OPCODE_READ_ATTR: | |
1175 | request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; | |
1176 | break; | |
1177 | default: | |
1178 | dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", | |
1179 | __func__, opcode); | |
1180 | err = -EINVAL; | |
1181 | goto out_unlock; | |
1182 | } | |
1183 | ||
1184 | request->upiu_req.opcode = opcode; | |
1185 | request->upiu_req.idn = idn; | |
1186 | request->upiu_req.index = index; | |
1187 | request->upiu_req.selector = selector; | |
1188 | ||
1189 | /* Send query request */ | |
1190 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, | |
1191 | QUERY_REQ_TIMEOUT); | |
1192 | ||
1193 | if (err) { | |
1194 | dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n", | |
1195 | __func__, opcode, idn, err); | |
1196 | goto out_unlock; | |
1197 | } | |
1198 | ||
1199 | *attr_val = response->upiu_res.value; | |
1200 | ||
1201 | out_unlock: | |
1202 | mutex_unlock(&hba->dev_cmd.lock); | |
1203 | out: | |
1204 | return err; | |
1205 | } | |
1206 | ||
7a3e97b0 SY |
1207 | /** |
1208 | * ufshcd_memory_alloc - allocate memory for host memory space data structures | |
1209 | * @hba: per adapter instance | |
1210 | * | |
1211 | * 1. Allocate DMA memory for Command Descriptor array | |
1212 | * Each command descriptor consist of Command UPIU, Response UPIU and PRDT | |
1213 | * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). | |
1214 | * 3. Allocate DMA memory for UTP Task Management Request Descriptor List | |
1215 | * (UTMRDL) | |
1216 | * 4. Allocate memory for local reference block(lrb). | |
1217 | * | |
1218 | * Returns 0 for success, non-zero in case of failure | |
1219 | */ | |
1220 | static int ufshcd_memory_alloc(struct ufs_hba *hba) | |
1221 | { | |
1222 | size_t utmrdl_size, utrdl_size, ucdl_size; | |
1223 | ||
1224 | /* Allocate memory for UTP command descriptors */ | |
1225 | ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs); | |
2953f850 SJ |
1226 | hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, |
1227 | ucdl_size, | |
1228 | &hba->ucdl_dma_addr, | |
1229 | GFP_KERNEL); | |
7a3e97b0 SY |
1230 | |
1231 | /* | |
1232 | * UFSHCI requires UTP command descriptor to be 128 byte aligned. | |
1233 | * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE | |
1234 | * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will | |
1235 | * be aligned to 128 bytes as well | |
1236 | */ | |
1237 | if (!hba->ucdl_base_addr || | |
1238 | WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1239 | dev_err(hba->dev, |
7a3e97b0 SY |
1240 | "Command Descriptor Memory allocation failed\n"); |
1241 | goto out; | |
1242 | } | |
1243 | ||
1244 | /* | |
1245 | * Allocate memory for UTP Transfer descriptors | |
1246 | * UFSHCI requires 1024 byte alignment of UTRD | |
1247 | */ | |
1248 | utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); | |
2953f850 SJ |
1249 | hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, |
1250 | utrdl_size, | |
1251 | &hba->utrdl_dma_addr, | |
1252 | GFP_KERNEL); | |
7a3e97b0 SY |
1253 | if (!hba->utrdl_base_addr || |
1254 | WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1255 | dev_err(hba->dev, |
7a3e97b0 SY |
1256 | "Transfer Descriptor Memory allocation failed\n"); |
1257 | goto out; | |
1258 | } | |
1259 | ||
1260 | /* | |
1261 | * Allocate memory for UTP Task Management descriptors | |
1262 | * UFSHCI requires 1024 byte alignment of UTMRD | |
1263 | */ | |
1264 | utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; | |
2953f850 SJ |
1265 | hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, |
1266 | utmrdl_size, | |
1267 | &hba->utmrdl_dma_addr, | |
1268 | GFP_KERNEL); | |
7a3e97b0 SY |
1269 | if (!hba->utmrdl_base_addr || |
1270 | WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1271 | dev_err(hba->dev, |
7a3e97b0 SY |
1272 | "Task Management Descriptor Memory allocation failed\n"); |
1273 | goto out; | |
1274 | } | |
1275 | ||
1276 | /* Allocate memory for local reference block */ | |
2953f850 SJ |
1277 | hba->lrb = devm_kzalloc(hba->dev, |
1278 | hba->nutrs * sizeof(struct ufshcd_lrb), | |
1279 | GFP_KERNEL); | |
7a3e97b0 | 1280 | if (!hba->lrb) { |
3b1d0580 | 1281 | dev_err(hba->dev, "LRB Memory allocation failed\n"); |
7a3e97b0 SY |
1282 | goto out; |
1283 | } | |
1284 | return 0; | |
1285 | out: | |
7a3e97b0 SY |
1286 | return -ENOMEM; |
1287 | } | |
1288 | ||
1289 | /** | |
1290 | * ufshcd_host_memory_configure - configure local reference block with | |
1291 | * memory offsets | |
1292 | * @hba: per adapter instance | |
1293 | * | |
1294 | * Configure Host memory space | |
1295 | * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA | |
1296 | * address. | |
1297 | * 2. Update each UTRD with Response UPIU offset, Response UPIU length | |
1298 | * and PRDT offset. | |
1299 | * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT | |
1300 | * into local reference block. | |
1301 | */ | |
1302 | static void ufshcd_host_memory_configure(struct ufs_hba *hba) | |
1303 | { | |
1304 | struct utp_transfer_cmd_desc *cmd_descp; | |
1305 | struct utp_transfer_req_desc *utrdlp; | |
1306 | dma_addr_t cmd_desc_dma_addr; | |
1307 | dma_addr_t cmd_desc_element_addr; | |
1308 | u16 response_offset; | |
1309 | u16 prdt_offset; | |
1310 | int cmd_desc_size; | |
1311 | int i; | |
1312 | ||
1313 | utrdlp = hba->utrdl_base_addr; | |
1314 | cmd_descp = hba->ucdl_base_addr; | |
1315 | ||
1316 | response_offset = | |
1317 | offsetof(struct utp_transfer_cmd_desc, response_upiu); | |
1318 | prdt_offset = | |
1319 | offsetof(struct utp_transfer_cmd_desc, prd_table); | |
1320 | ||
1321 | cmd_desc_size = sizeof(struct utp_transfer_cmd_desc); | |
1322 | cmd_desc_dma_addr = hba->ucdl_dma_addr; | |
1323 | ||
1324 | for (i = 0; i < hba->nutrs; i++) { | |
1325 | /* Configure UTRD with command descriptor base address */ | |
1326 | cmd_desc_element_addr = | |
1327 | (cmd_desc_dma_addr + (cmd_desc_size * i)); | |
1328 | utrdlp[i].command_desc_base_addr_lo = | |
1329 | cpu_to_le32(lower_32_bits(cmd_desc_element_addr)); | |
1330 | utrdlp[i].command_desc_base_addr_hi = | |
1331 | cpu_to_le32(upper_32_bits(cmd_desc_element_addr)); | |
1332 | ||
1333 | /* Response upiu and prdt offset should be in double words */ | |
1334 | utrdlp[i].response_upiu_offset = | |
1335 | cpu_to_le16((response_offset >> 2)); | |
1336 | utrdlp[i].prd_table_offset = | |
1337 | cpu_to_le16((prdt_offset >> 2)); | |
1338 | utrdlp[i].response_upiu_length = | |
3ca316c5 | 1339 | cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); |
7a3e97b0 SY |
1340 | |
1341 | hba->lrb[i].utr_descriptor_ptr = (utrdlp + i); | |
5a0b0cb9 SRT |
1342 | hba->lrb[i].ucd_req_ptr = |
1343 | (struct utp_upiu_req *)(cmd_descp + i); | |
7a3e97b0 SY |
1344 | hba->lrb[i].ucd_rsp_ptr = |
1345 | (struct utp_upiu_rsp *)cmd_descp[i].response_upiu; | |
1346 | hba->lrb[i].ucd_prdt_ptr = | |
1347 | (struct ufshcd_sg_entry *)cmd_descp[i].prd_table; | |
1348 | } | |
1349 | } | |
1350 | ||
1351 | /** | |
1352 | * ufshcd_dme_link_startup - Notify Unipro to perform link startup | |
1353 | * @hba: per adapter instance | |
1354 | * | |
1355 | * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, | |
1356 | * in order to initialize the Unipro link startup procedure. | |
1357 | * Once the Unipro links are up, the device connected to the controller | |
1358 | * is detected. | |
1359 | * | |
1360 | * Returns 0 on success, non-zero value on failure | |
1361 | */ | |
1362 | static int ufshcd_dme_link_startup(struct ufs_hba *hba) | |
1363 | { | |
6ccf44fe SJ |
1364 | struct uic_command uic_cmd = {0}; |
1365 | int ret; | |
7a3e97b0 | 1366 | |
6ccf44fe | 1367 | uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; |
7a3e97b0 | 1368 | |
6ccf44fe SJ |
1369 | ret = ufshcd_send_uic_cmd(hba, &uic_cmd); |
1370 | if (ret) | |
1371 | dev_err(hba->dev, | |
1372 | "dme-link-startup: error code %d\n", ret); | |
1373 | return ret; | |
7a3e97b0 SY |
1374 | } |
1375 | ||
68078d5c DR |
1376 | /** |
1377 | * ufshcd_complete_dev_init() - checks device readiness | |
1378 | * hba: per-adapter instance | |
1379 | * | |
1380 | * Set fDeviceInit flag and poll until device toggles it. | |
1381 | */ | |
1382 | static int ufshcd_complete_dev_init(struct ufs_hba *hba) | |
1383 | { | |
1384 | int i, retries, err = 0; | |
1385 | bool flag_res = 1; | |
1386 | ||
1387 | for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { | |
1388 | /* Set the fDeviceInit flag */ | |
1389 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG, | |
1390 | QUERY_FLAG_IDN_FDEVICEINIT, NULL); | |
1391 | if (!err || err == -ETIMEDOUT) | |
1392 | break; | |
1393 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); | |
1394 | } | |
1395 | if (err) { | |
1396 | dev_err(hba->dev, | |
1397 | "%s setting fDeviceInit flag failed with error %d\n", | |
1398 | __func__, err); | |
1399 | goto out; | |
1400 | } | |
1401 | ||
1402 | /* poll for max. 100 iterations for fDeviceInit flag to clear */ | |
1403 | for (i = 0; i < 100 && !err && flag_res; i++) { | |
1404 | for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { | |
1405 | err = ufshcd_query_flag(hba, | |
1406 | UPIU_QUERY_OPCODE_READ_FLAG, | |
1407 | QUERY_FLAG_IDN_FDEVICEINIT, &flag_res); | |
1408 | if (!err || err == -ETIMEDOUT) | |
1409 | break; | |
1410 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, | |
1411 | err); | |
1412 | } | |
1413 | } | |
1414 | if (err) | |
1415 | dev_err(hba->dev, | |
1416 | "%s reading fDeviceInit flag failed with error %d\n", | |
1417 | __func__, err); | |
1418 | else if (flag_res) | |
1419 | dev_err(hba->dev, | |
1420 | "%s fDeviceInit was not cleared by the device\n", | |
1421 | __func__); | |
1422 | ||
1423 | out: | |
1424 | return err; | |
1425 | } | |
1426 | ||
7a3e97b0 SY |
1427 | /** |
1428 | * ufshcd_make_hba_operational - Make UFS controller operational | |
1429 | * @hba: per adapter instance | |
1430 | * | |
1431 | * To bring UFS host controller to operational state, | |
1432 | * 1. Check if device is present | |
6ccf44fe SJ |
1433 | * 2. Enable required interrupts |
1434 | * 3. Configure interrupt aggregation | |
1435 | * 4. Program UTRL and UTMRL base addres | |
1436 | * 5. Configure run-stop-registers | |
7a3e97b0 SY |
1437 | * |
1438 | * Returns 0 on success, non-zero value on failure | |
1439 | */ | |
1440 | static int ufshcd_make_hba_operational(struct ufs_hba *hba) | |
1441 | { | |
1442 | int err = 0; | |
1443 | u32 reg; | |
1444 | ||
1445 | /* check if device present */ | |
b873a275 | 1446 | reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); |
73ec513a | 1447 | if (!ufshcd_is_device_present(reg)) { |
3b1d0580 | 1448 | dev_err(hba->dev, "cc: Device not present\n"); |
7a3e97b0 SY |
1449 | err = -ENXIO; |
1450 | goto out; | |
1451 | } | |
1452 | ||
6ccf44fe SJ |
1453 | /* Enable required interrupts */ |
1454 | ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); | |
1455 | ||
1456 | /* Configure interrupt aggregation */ | |
7d568652 | 1457 | ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); |
6ccf44fe SJ |
1458 | |
1459 | /* Configure UTRL and UTMRL base address registers */ | |
1460 | ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), | |
1461 | REG_UTP_TRANSFER_REQ_LIST_BASE_L); | |
1462 | ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), | |
1463 | REG_UTP_TRANSFER_REQ_LIST_BASE_H); | |
1464 | ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), | |
1465 | REG_UTP_TASK_REQ_LIST_BASE_L); | |
1466 | ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), | |
1467 | REG_UTP_TASK_REQ_LIST_BASE_H); | |
1468 | ||
7a3e97b0 SY |
1469 | /* |
1470 | * UCRDY, UTMRLDY and UTRLRDY bits must be 1 | |
1471 | * DEI, HEI bits must be 0 | |
1472 | */ | |
1473 | if (!(ufshcd_get_lists_status(reg))) { | |
1474 | ufshcd_enable_run_stop_reg(hba); | |
1475 | } else { | |
3b1d0580 | 1476 | dev_err(hba->dev, |
7a3e97b0 SY |
1477 | "Host controller not ready to process requests"); |
1478 | err = -EIO; | |
1479 | goto out; | |
1480 | } | |
1481 | ||
7a3e97b0 SY |
1482 | if (hba->ufshcd_state == UFSHCD_STATE_RESET) |
1483 | scsi_unblock_requests(hba->host); | |
1484 | ||
1485 | hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; | |
6ccf44fe | 1486 | |
7a3e97b0 SY |
1487 | out: |
1488 | return err; | |
1489 | } | |
1490 | ||
1491 | /** | |
1492 | * ufshcd_hba_enable - initialize the controller | |
1493 | * @hba: per adapter instance | |
1494 | * | |
1495 | * The controller resets itself and controller firmware initialization | |
1496 | * sequence kicks off. When controller is ready it will set | |
1497 | * the Host Controller Enable bit to 1. | |
1498 | * | |
1499 | * Returns 0 on success, non-zero value on failure | |
1500 | */ | |
1501 | static int ufshcd_hba_enable(struct ufs_hba *hba) | |
1502 | { | |
1503 | int retry; | |
1504 | ||
1505 | /* | |
1506 | * msleep of 1 and 5 used in this function might result in msleep(20), | |
1507 | * but it was necessary to send the UFS FPGA to reset mode during | |
1508 | * development and testing of this driver. msleep can be changed to | |
1509 | * mdelay and retry count can be reduced based on the controller. | |
1510 | */ | |
1511 | if (!ufshcd_is_hba_active(hba)) { | |
1512 | ||
1513 | /* change controller state to "reset state" */ | |
1514 | ufshcd_hba_stop(hba); | |
1515 | ||
1516 | /* | |
1517 | * This delay is based on the testing done with UFS host | |
1518 | * controller FPGA. The delay can be changed based on the | |
1519 | * host controller used. | |
1520 | */ | |
1521 | msleep(5); | |
1522 | } | |
1523 | ||
1524 | /* start controller initialization sequence */ | |
1525 | ufshcd_hba_start(hba); | |
1526 | ||
1527 | /* | |
1528 | * To initialize a UFS host controller HCE bit must be set to 1. | |
1529 | * During initialization the HCE bit value changes from 1->0->1. | |
1530 | * When the host controller completes initialization sequence | |
1531 | * it sets the value of HCE bit to 1. The same HCE bit is read back | |
1532 | * to check if the controller has completed initialization sequence. | |
1533 | * So without this delay the value HCE = 1, set in the previous | |
1534 | * instruction might be read back. | |
1535 | * This delay can be changed based on the controller. | |
1536 | */ | |
1537 | msleep(1); | |
1538 | ||
1539 | /* wait for the host controller to complete initialization */ | |
1540 | retry = 10; | |
1541 | while (ufshcd_is_hba_active(hba)) { | |
1542 | if (retry) { | |
1543 | retry--; | |
1544 | } else { | |
3b1d0580 | 1545 | dev_err(hba->dev, |
7a3e97b0 SY |
1546 | "Controller enable failed\n"); |
1547 | return -EIO; | |
1548 | } | |
1549 | msleep(5); | |
1550 | } | |
1551 | return 0; | |
1552 | } | |
1553 | ||
1554 | /** | |
6ccf44fe | 1555 | * ufshcd_link_startup - Initialize unipro link startup |
7a3e97b0 SY |
1556 | * @hba: per adapter instance |
1557 | * | |
6ccf44fe | 1558 | * Returns 0 for success, non-zero in case of failure |
7a3e97b0 | 1559 | */ |
6ccf44fe | 1560 | static int ufshcd_link_startup(struct ufs_hba *hba) |
7a3e97b0 | 1561 | { |
6ccf44fe | 1562 | int ret; |
7a3e97b0 | 1563 | |
6ccf44fe SJ |
1564 | /* enable UIC related interrupts */ |
1565 | ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); | |
1566 | ||
1567 | ret = ufshcd_dme_link_startup(hba); | |
1568 | if (ret) | |
1569 | goto out; | |
1570 | ||
1571 | ret = ufshcd_make_hba_operational(hba); | |
7a3e97b0 | 1572 | |
6ccf44fe SJ |
1573 | out: |
1574 | if (ret) | |
1575 | dev_err(hba->dev, "link startup failed %d\n", ret); | |
1576 | return ret; | |
7a3e97b0 SY |
1577 | } |
1578 | ||
5a0b0cb9 SRT |
1579 | /** |
1580 | * ufshcd_verify_dev_init() - Verify device initialization | |
1581 | * @hba: per-adapter instance | |
1582 | * | |
1583 | * Send NOP OUT UPIU and wait for NOP IN response to check whether the | |
1584 | * device Transport Protocol (UTP) layer is ready after a reset. | |
1585 | * If the UTP layer at the device side is not initialized, it may | |
1586 | * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT | |
1587 | * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. | |
1588 | */ | |
1589 | static int ufshcd_verify_dev_init(struct ufs_hba *hba) | |
1590 | { | |
1591 | int err = 0; | |
1592 | int retries; | |
1593 | ||
1594 | mutex_lock(&hba->dev_cmd.lock); | |
1595 | for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { | |
1596 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, | |
1597 | NOP_OUT_TIMEOUT); | |
1598 | ||
1599 | if (!err || err == -ETIMEDOUT) | |
1600 | break; | |
1601 | ||
1602 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); | |
1603 | } | |
1604 | mutex_unlock(&hba->dev_cmd.lock); | |
1605 | ||
1606 | if (err) | |
1607 | dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); | |
1608 | return err; | |
1609 | } | |
1610 | ||
7a3e97b0 SY |
1611 | /** |
1612 | * ufshcd_do_reset - reset the host controller | |
1613 | * @hba: per adapter instance | |
1614 | * | |
1615 | * Returns SUCCESS/FAILED | |
1616 | */ | |
1617 | static int ufshcd_do_reset(struct ufs_hba *hba) | |
1618 | { | |
1619 | struct ufshcd_lrb *lrbp; | |
1620 | unsigned long flags; | |
1621 | int tag; | |
1622 | ||
1623 | /* block commands from midlayer */ | |
1624 | scsi_block_requests(hba->host); | |
1625 | ||
1626 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1627 | hba->ufshcd_state = UFSHCD_STATE_RESET; | |
1628 | ||
1629 | /* send controller to reset state */ | |
1630 | ufshcd_hba_stop(hba); | |
1631 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1632 | ||
1633 | /* abort outstanding commands */ | |
1634 | for (tag = 0; tag < hba->nutrs; tag++) { | |
1635 | if (test_bit(tag, &hba->outstanding_reqs)) { | |
1636 | lrbp = &hba->lrb[tag]; | |
5a0b0cb9 SRT |
1637 | if (lrbp->cmd) { |
1638 | scsi_dma_unmap(lrbp->cmd); | |
1639 | lrbp->cmd->result = DID_RESET << 16; | |
1640 | lrbp->cmd->scsi_done(lrbp->cmd); | |
1641 | lrbp->cmd = NULL; | |
1642 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
1643 | } | |
7a3e97b0 SY |
1644 | } |
1645 | } | |
1646 | ||
5a0b0cb9 SRT |
1647 | /* complete device management command */ |
1648 | if (hba->dev_cmd.complete) | |
1649 | complete(hba->dev_cmd.complete); | |
1650 | ||
7a3e97b0 SY |
1651 | /* clear outstanding request/task bit maps */ |
1652 | hba->outstanding_reqs = 0; | |
1653 | hba->outstanding_tasks = 0; | |
1654 | ||
6ccf44fe SJ |
1655 | /* Host controller enable */ |
1656 | if (ufshcd_hba_enable(hba)) { | |
3b1d0580 | 1657 | dev_err(hba->dev, |
7a3e97b0 SY |
1658 | "Reset: Controller initialization failed\n"); |
1659 | return FAILED; | |
1660 | } | |
6ccf44fe SJ |
1661 | |
1662 | if (ufshcd_link_startup(hba)) { | |
1663 | dev_err(hba->dev, | |
1664 | "Reset: Link start-up failed\n"); | |
1665 | return FAILED; | |
1666 | } | |
1667 | ||
7a3e97b0 SY |
1668 | return SUCCESS; |
1669 | } | |
1670 | ||
1671 | /** | |
1672 | * ufshcd_slave_alloc - handle initial SCSI device configurations | |
1673 | * @sdev: pointer to SCSI device | |
1674 | * | |
1675 | * Returns success | |
1676 | */ | |
1677 | static int ufshcd_slave_alloc(struct scsi_device *sdev) | |
1678 | { | |
1679 | struct ufs_hba *hba; | |
1680 | ||
1681 | hba = shost_priv(sdev->host); | |
1682 | sdev->tagged_supported = 1; | |
1683 | ||
1684 | /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ | |
1685 | sdev->use_10_for_ms = 1; | |
1686 | scsi_set_tag_type(sdev, MSG_SIMPLE_TAG); | |
1687 | ||
1688 | /* | |
1689 | * Inform SCSI Midlayer that the LUN queue depth is same as the | |
1690 | * controller queue depth. If a LUN queue depth is less than the | |
1691 | * controller queue depth and if the LUN reports | |
1692 | * SAM_STAT_TASK_SET_FULL, the LUN queue depth will be adjusted | |
1693 | * with scsi_adjust_queue_depth. | |
1694 | */ | |
1695 | scsi_activate_tcq(sdev, hba->nutrs); | |
1696 | return 0; | |
1697 | } | |
1698 | ||
1699 | /** | |
1700 | * ufshcd_slave_destroy - remove SCSI device configurations | |
1701 | * @sdev: pointer to SCSI device | |
1702 | */ | |
1703 | static void ufshcd_slave_destroy(struct scsi_device *sdev) | |
1704 | { | |
1705 | struct ufs_hba *hba; | |
1706 | ||
1707 | hba = shost_priv(sdev->host); | |
1708 | scsi_deactivate_tcq(sdev, hba->nutrs); | |
1709 | } | |
1710 | ||
1711 | /** | |
1712 | * ufshcd_task_req_compl - handle task management request completion | |
1713 | * @hba: per adapter instance | |
1714 | * @index: index of the completed request | |
1715 | * | |
1716 | * Returns SUCCESS/FAILED | |
1717 | */ | |
1718 | static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index) | |
1719 | { | |
1720 | struct utp_task_req_desc *task_req_descp; | |
1721 | struct utp_upiu_task_rsp *task_rsp_upiup; | |
1722 | unsigned long flags; | |
1723 | int ocs_value; | |
1724 | int task_result; | |
1725 | ||
1726 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1727 | ||
1728 | /* Clear completed tasks from outstanding_tasks */ | |
1729 | __clear_bit(index, &hba->outstanding_tasks); | |
1730 | ||
1731 | task_req_descp = hba->utmrdl_base_addr; | |
1732 | ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]); | |
1733 | ||
1734 | if (ocs_value == OCS_SUCCESS) { | |
1735 | task_rsp_upiup = (struct utp_upiu_task_rsp *) | |
1736 | task_req_descp[index].task_rsp_upiu; | |
1737 | task_result = be32_to_cpu(task_rsp_upiup->header.dword_1); | |
1738 | task_result = ((task_result & MASK_TASK_RESPONSE) >> 8); | |
1739 | ||
fd0f8370 | 1740 | if (task_result != UPIU_TASK_MANAGEMENT_FUNC_COMPL && |
7a3e97b0 SY |
1741 | task_result != UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) |
1742 | task_result = FAILED; | |
94c122ab NJ |
1743 | else |
1744 | task_result = SUCCESS; | |
7a3e97b0 SY |
1745 | } else { |
1746 | task_result = FAILED; | |
3b1d0580 | 1747 | dev_err(hba->dev, |
7a3e97b0 SY |
1748 | "trc: Invalid ocs = %x\n", ocs_value); |
1749 | } | |
1750 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1751 | return task_result; | |
1752 | } | |
1753 | ||
1754 | /** | |
1755 | * ufshcd_adjust_lun_qdepth - Update LUN queue depth if device responds with | |
1756 | * SAM_STAT_TASK_SET_FULL SCSI command status. | |
1757 | * @cmd: pointer to SCSI command | |
1758 | */ | |
1759 | static void ufshcd_adjust_lun_qdepth(struct scsi_cmnd *cmd) | |
1760 | { | |
1761 | struct ufs_hba *hba; | |
1762 | int i; | |
1763 | int lun_qdepth = 0; | |
1764 | ||
1765 | hba = shost_priv(cmd->device->host); | |
1766 | ||
1767 | /* | |
1768 | * LUN queue depth can be obtained by counting outstanding commands | |
1769 | * on the LUN. | |
1770 | */ | |
1771 | for (i = 0; i < hba->nutrs; i++) { | |
1772 | if (test_bit(i, &hba->outstanding_reqs)) { | |
1773 | ||
1774 | /* | |
1775 | * Check if the outstanding command belongs | |
1776 | * to the LUN which reported SAM_STAT_TASK_SET_FULL. | |
1777 | */ | |
1778 | if (cmd->device->lun == hba->lrb[i].lun) | |
1779 | lun_qdepth++; | |
1780 | } | |
1781 | } | |
1782 | ||
1783 | /* | |
1784 | * LUN queue depth will be total outstanding commands, except the | |
1785 | * command for which the LUN reported SAM_STAT_TASK_SET_FULL. | |
1786 | */ | |
1787 | scsi_adjust_queue_depth(cmd->device, MSG_SIMPLE_TAG, lun_qdepth - 1); | |
1788 | } | |
1789 | ||
1790 | /** | |
1791 | * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status | |
1792 | * @lrb: pointer to local reference block of completed command | |
1793 | * @scsi_status: SCSI command status | |
1794 | * | |
1795 | * Returns value base on SCSI command status | |
1796 | */ | |
1797 | static inline int | |
1798 | ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) | |
1799 | { | |
1800 | int result = 0; | |
1801 | ||
1802 | switch (scsi_status) { | |
7a3e97b0 | 1803 | case SAM_STAT_CHECK_CONDITION: |
1c2623c5 SJ |
1804 | ufshcd_copy_sense_data(lrbp); |
1805 | case SAM_STAT_GOOD: | |
7a3e97b0 SY |
1806 | result |= DID_OK << 16 | |
1807 | COMMAND_COMPLETE << 8 | | |
1c2623c5 | 1808 | scsi_status; |
7a3e97b0 SY |
1809 | break; |
1810 | case SAM_STAT_TASK_SET_FULL: | |
7a3e97b0 SY |
1811 | /* |
1812 | * If a LUN reports SAM_STAT_TASK_SET_FULL, then the LUN queue | |
1813 | * depth needs to be adjusted to the exact number of | |
1814 | * outstanding commands the LUN can handle at any given time. | |
1815 | */ | |
1816 | ufshcd_adjust_lun_qdepth(lrbp->cmd); | |
1c2623c5 | 1817 | case SAM_STAT_BUSY: |
7a3e97b0 | 1818 | case SAM_STAT_TASK_ABORTED: |
1c2623c5 SJ |
1819 | ufshcd_copy_sense_data(lrbp); |
1820 | result |= scsi_status; | |
7a3e97b0 SY |
1821 | break; |
1822 | default: | |
1823 | result |= DID_ERROR << 16; | |
1824 | break; | |
1825 | } /* end of switch */ | |
1826 | ||
1827 | return result; | |
1828 | } | |
1829 | ||
1830 | /** | |
1831 | * ufshcd_transfer_rsp_status - Get overall status of the response | |
1832 | * @hba: per adapter instance | |
1833 | * @lrb: pointer to local reference block of completed command | |
1834 | * | |
1835 | * Returns result of the command to notify SCSI midlayer | |
1836 | */ | |
1837 | static inline int | |
1838 | ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
1839 | { | |
1840 | int result = 0; | |
1841 | int scsi_status; | |
1842 | int ocs; | |
1843 | ||
1844 | /* overall command status of utrd */ | |
1845 | ocs = ufshcd_get_tr_ocs(lrbp); | |
1846 | ||
1847 | switch (ocs) { | |
1848 | case OCS_SUCCESS: | |
5a0b0cb9 | 1849 | result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); |
7a3e97b0 | 1850 | |
5a0b0cb9 SRT |
1851 | switch (result) { |
1852 | case UPIU_TRANSACTION_RESPONSE: | |
1853 | /* | |
1854 | * get the response UPIU result to extract | |
1855 | * the SCSI command status | |
1856 | */ | |
1857 | result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr); | |
1858 | ||
1859 | /* | |
1860 | * get the result based on SCSI status response | |
1861 | * to notify the SCSI midlayer of the command status | |
1862 | */ | |
1863 | scsi_status = result & MASK_SCSI_STATUS; | |
1864 | result = ufshcd_scsi_cmd_status(lrbp, scsi_status); | |
66ec6d59 SRT |
1865 | |
1866 | if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) | |
1867 | schedule_work(&hba->eeh_work); | |
5a0b0cb9 SRT |
1868 | break; |
1869 | case UPIU_TRANSACTION_REJECT_UPIU: | |
1870 | /* TODO: handle Reject UPIU Response */ | |
1871 | result = DID_ERROR << 16; | |
3b1d0580 | 1872 | dev_err(hba->dev, |
5a0b0cb9 SRT |
1873 | "Reject UPIU not fully implemented\n"); |
1874 | break; | |
1875 | default: | |
1876 | result = DID_ERROR << 16; | |
1877 | dev_err(hba->dev, | |
1878 | "Unexpected request response code = %x\n", | |
1879 | result); | |
7a3e97b0 SY |
1880 | break; |
1881 | } | |
7a3e97b0 SY |
1882 | break; |
1883 | case OCS_ABORTED: | |
1884 | result |= DID_ABORT << 16; | |
1885 | break; | |
1886 | case OCS_INVALID_CMD_TABLE_ATTR: | |
1887 | case OCS_INVALID_PRDT_ATTR: | |
1888 | case OCS_MISMATCH_DATA_BUF_SIZE: | |
1889 | case OCS_MISMATCH_RESP_UPIU_SIZE: | |
1890 | case OCS_PEER_COMM_FAILURE: | |
1891 | case OCS_FATAL_ERROR: | |
1892 | default: | |
1893 | result |= DID_ERROR << 16; | |
3b1d0580 | 1894 | dev_err(hba->dev, |
7a3e97b0 SY |
1895 | "OCS error from controller = %x\n", ocs); |
1896 | break; | |
1897 | } /* end of switch */ | |
1898 | ||
1899 | return result; | |
1900 | } | |
1901 | ||
6ccf44fe SJ |
1902 | /** |
1903 | * ufshcd_uic_cmd_compl - handle completion of uic command | |
1904 | * @hba: per adapter instance | |
1905 | */ | |
1906 | static void ufshcd_uic_cmd_compl(struct ufs_hba *hba) | |
1907 | { | |
1908 | if (hba->active_uic_cmd) { | |
1909 | hba->active_uic_cmd->argument2 |= | |
1910 | ufshcd_get_uic_cmd_result(hba); | |
1911 | complete(&hba->active_uic_cmd->done); | |
1912 | } | |
1913 | } | |
1914 | ||
7a3e97b0 SY |
1915 | /** |
1916 | * ufshcd_transfer_req_compl - handle SCSI and query command completion | |
1917 | * @hba: per adapter instance | |
1918 | */ | |
1919 | static void ufshcd_transfer_req_compl(struct ufs_hba *hba) | |
1920 | { | |
5a0b0cb9 SRT |
1921 | struct ufshcd_lrb *lrbp; |
1922 | struct scsi_cmnd *cmd; | |
7a3e97b0 SY |
1923 | unsigned long completed_reqs; |
1924 | u32 tr_doorbell; | |
1925 | int result; | |
1926 | int index; | |
5a0b0cb9 | 1927 | bool int_aggr_reset = false; |
7a3e97b0 | 1928 | |
b873a275 | 1929 | tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); |
7a3e97b0 SY |
1930 | completed_reqs = tr_doorbell ^ hba->outstanding_reqs; |
1931 | ||
1932 | for (index = 0; index < hba->nutrs; index++) { | |
1933 | if (test_bit(index, &completed_reqs)) { | |
5a0b0cb9 SRT |
1934 | lrbp = &hba->lrb[index]; |
1935 | cmd = lrbp->cmd; | |
1936 | /* | |
1937 | * Don't skip resetting interrupt aggregation counters | |
1938 | * if a regular command is present. | |
1939 | */ | |
1940 | int_aggr_reset |= !lrbp->intr_cmd; | |
7a3e97b0 | 1941 | |
5a0b0cb9 SRT |
1942 | if (cmd) { |
1943 | result = ufshcd_transfer_rsp_status(hba, lrbp); | |
1944 | scsi_dma_unmap(cmd); | |
1945 | cmd->result = result; | |
7a3e97b0 | 1946 | /* Mark completed command as NULL in LRB */ |
5a0b0cb9 SRT |
1947 | lrbp->cmd = NULL; |
1948 | clear_bit_unlock(index, &hba->lrb_in_use); | |
1949 | /* Do not touch lrbp after scsi done */ | |
1950 | cmd->scsi_done(cmd); | |
1951 | } else if (lrbp->command_type == | |
1952 | UTP_CMD_TYPE_DEV_MANAGE) { | |
1953 | if (hba->dev_cmd.complete) | |
1954 | complete(hba->dev_cmd.complete); | |
7a3e97b0 SY |
1955 | } |
1956 | } /* end of if */ | |
1957 | } /* end of for */ | |
1958 | ||
1959 | /* clear corresponding bits of completed commands */ | |
1960 | hba->outstanding_reqs ^= completed_reqs; | |
1961 | ||
5a0b0cb9 SRT |
1962 | /* we might have free'd some tags above */ |
1963 | wake_up(&hba->dev_cmd.tag_wq); | |
1964 | ||
7a3e97b0 | 1965 | /* Reset interrupt aggregation counters */ |
5a0b0cb9 | 1966 | if (int_aggr_reset) |
7d568652 | 1967 | ufshcd_reset_intr_aggr(hba); |
7a3e97b0 SY |
1968 | } |
1969 | ||
66ec6d59 SRT |
1970 | /** |
1971 | * ufshcd_disable_ee - disable exception event | |
1972 | * @hba: per-adapter instance | |
1973 | * @mask: exception event to disable | |
1974 | * | |
1975 | * Disables exception event in the device so that the EVENT_ALERT | |
1976 | * bit is not set. | |
1977 | * | |
1978 | * Returns zero on success, non-zero error value on failure. | |
1979 | */ | |
1980 | static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) | |
1981 | { | |
1982 | int err = 0; | |
1983 | u32 val; | |
1984 | ||
1985 | if (!(hba->ee_ctrl_mask & mask)) | |
1986 | goto out; | |
1987 | ||
1988 | val = hba->ee_ctrl_mask & ~mask; | |
1989 | val &= 0xFFFF; /* 2 bytes */ | |
1990 | err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, | |
1991 | QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); | |
1992 | if (!err) | |
1993 | hba->ee_ctrl_mask &= ~mask; | |
1994 | out: | |
1995 | return err; | |
1996 | } | |
1997 | ||
1998 | /** | |
1999 | * ufshcd_enable_ee - enable exception event | |
2000 | * @hba: per-adapter instance | |
2001 | * @mask: exception event to enable | |
2002 | * | |
2003 | * Enable corresponding exception event in the device to allow | |
2004 | * device to alert host in critical scenarios. | |
2005 | * | |
2006 | * Returns zero on success, non-zero error value on failure. | |
2007 | */ | |
2008 | static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) | |
2009 | { | |
2010 | int err = 0; | |
2011 | u32 val; | |
2012 | ||
2013 | if (hba->ee_ctrl_mask & mask) | |
2014 | goto out; | |
2015 | ||
2016 | val = hba->ee_ctrl_mask | mask; | |
2017 | val &= 0xFFFF; /* 2 bytes */ | |
2018 | err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, | |
2019 | QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); | |
2020 | if (!err) | |
2021 | hba->ee_ctrl_mask |= mask; | |
2022 | out: | |
2023 | return err; | |
2024 | } | |
2025 | ||
2026 | /** | |
2027 | * ufshcd_enable_auto_bkops - Allow device managed BKOPS | |
2028 | * @hba: per-adapter instance | |
2029 | * | |
2030 | * Allow device to manage background operations on its own. Enabling | |
2031 | * this might lead to inconsistent latencies during normal data transfers | |
2032 | * as the device is allowed to manage its own way of handling background | |
2033 | * operations. | |
2034 | * | |
2035 | * Returns zero on success, non-zero on failure. | |
2036 | */ | |
2037 | static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) | |
2038 | { | |
2039 | int err = 0; | |
2040 | ||
2041 | if (hba->auto_bkops_enabled) | |
2042 | goto out; | |
2043 | ||
2044 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG, | |
2045 | QUERY_FLAG_IDN_BKOPS_EN, NULL); | |
2046 | if (err) { | |
2047 | dev_err(hba->dev, "%s: failed to enable bkops %d\n", | |
2048 | __func__, err); | |
2049 | goto out; | |
2050 | } | |
2051 | ||
2052 | hba->auto_bkops_enabled = true; | |
2053 | ||
2054 | /* No need of URGENT_BKOPS exception from the device */ | |
2055 | err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); | |
2056 | if (err) | |
2057 | dev_err(hba->dev, "%s: failed to disable exception event %d\n", | |
2058 | __func__, err); | |
2059 | out: | |
2060 | return err; | |
2061 | } | |
2062 | ||
2063 | /** | |
2064 | * ufshcd_disable_auto_bkops - block device in doing background operations | |
2065 | * @hba: per-adapter instance | |
2066 | * | |
2067 | * Disabling background operations improves command response latency but | |
2068 | * has drawback of device moving into critical state where the device is | |
2069 | * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the | |
2070 | * host is idle so that BKOPS are managed effectively without any negative | |
2071 | * impacts. | |
2072 | * | |
2073 | * Returns zero on success, non-zero on failure. | |
2074 | */ | |
2075 | static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) | |
2076 | { | |
2077 | int err = 0; | |
2078 | ||
2079 | if (!hba->auto_bkops_enabled) | |
2080 | goto out; | |
2081 | ||
2082 | /* | |
2083 | * If host assisted BKOPs is to be enabled, make sure | |
2084 | * urgent bkops exception is allowed. | |
2085 | */ | |
2086 | err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); | |
2087 | if (err) { | |
2088 | dev_err(hba->dev, "%s: failed to enable exception event %d\n", | |
2089 | __func__, err); | |
2090 | goto out; | |
2091 | } | |
2092 | ||
2093 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, | |
2094 | QUERY_FLAG_IDN_BKOPS_EN, NULL); | |
2095 | if (err) { | |
2096 | dev_err(hba->dev, "%s: failed to disable bkops %d\n", | |
2097 | __func__, err); | |
2098 | ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); | |
2099 | goto out; | |
2100 | } | |
2101 | ||
2102 | hba->auto_bkops_enabled = false; | |
2103 | out: | |
2104 | return err; | |
2105 | } | |
2106 | ||
2107 | /** | |
2108 | * ufshcd_force_reset_auto_bkops - force enable of auto bkops | |
2109 | * @hba: per adapter instance | |
2110 | * | |
2111 | * After a device reset the device may toggle the BKOPS_EN flag | |
2112 | * to default value. The s/w tracking variables should be updated | |
2113 | * as well. Do this by forcing enable of auto bkops. | |
2114 | */ | |
2115 | static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) | |
2116 | { | |
2117 | hba->auto_bkops_enabled = false; | |
2118 | hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; | |
2119 | ufshcd_enable_auto_bkops(hba); | |
2120 | } | |
2121 | ||
2122 | static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) | |
2123 | { | |
2124 | return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR, | |
2125 | QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); | |
2126 | } | |
2127 | ||
2128 | /** | |
2129 | * ufshcd_urgent_bkops - handle urgent bkops exception event | |
2130 | * @hba: per-adapter instance | |
2131 | * | |
2132 | * Enable fBackgroundOpsEn flag in the device to permit background | |
2133 | * operations. | |
2134 | */ | |
2135 | static int ufshcd_urgent_bkops(struct ufs_hba *hba) | |
2136 | { | |
2137 | int err; | |
2138 | u32 status = 0; | |
2139 | ||
2140 | err = ufshcd_get_bkops_status(hba, &status); | |
2141 | if (err) { | |
2142 | dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", | |
2143 | __func__, err); | |
2144 | goto out; | |
2145 | } | |
2146 | ||
2147 | status = status & 0xF; | |
2148 | ||
2149 | /* handle only if status indicates performance impact or critical */ | |
2150 | if (status >= BKOPS_STATUS_PERF_IMPACT) | |
2151 | err = ufshcd_enable_auto_bkops(hba); | |
2152 | out: | |
2153 | return err; | |
2154 | } | |
2155 | ||
2156 | static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) | |
2157 | { | |
2158 | return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR, | |
2159 | QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); | |
2160 | } | |
2161 | ||
2162 | /** | |
2163 | * ufshcd_exception_event_handler - handle exceptions raised by device | |
2164 | * @work: pointer to work data | |
2165 | * | |
2166 | * Read bExceptionEventStatus attribute from the device and handle the | |
2167 | * exception event accordingly. | |
2168 | */ | |
2169 | static void ufshcd_exception_event_handler(struct work_struct *work) | |
2170 | { | |
2171 | struct ufs_hba *hba; | |
2172 | int err; | |
2173 | u32 status = 0; | |
2174 | hba = container_of(work, struct ufs_hba, eeh_work); | |
2175 | ||
62694735 | 2176 | pm_runtime_get_sync(hba->dev); |
66ec6d59 SRT |
2177 | err = ufshcd_get_ee_status(hba, &status); |
2178 | if (err) { | |
2179 | dev_err(hba->dev, "%s: failed to get exception status %d\n", | |
2180 | __func__, err); | |
2181 | goto out; | |
2182 | } | |
2183 | ||
2184 | status &= hba->ee_ctrl_mask; | |
2185 | if (status & MASK_EE_URGENT_BKOPS) { | |
2186 | err = ufshcd_urgent_bkops(hba); | |
2187 | if (err) | |
2188 | dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", | |
2189 | __func__, err); | |
2190 | } | |
2191 | out: | |
62694735 | 2192 | pm_runtime_put_sync(hba->dev); |
66ec6d59 SRT |
2193 | return; |
2194 | } | |
2195 | ||
7a3e97b0 SY |
2196 | /** |
2197 | * ufshcd_fatal_err_handler - handle fatal errors | |
2198 | * @hba: per adapter instance | |
2199 | */ | |
2200 | static void ufshcd_fatal_err_handler(struct work_struct *work) | |
2201 | { | |
2202 | struct ufs_hba *hba; | |
2203 | hba = container_of(work, struct ufs_hba, feh_workq); | |
2204 | ||
62694735 | 2205 | pm_runtime_get_sync(hba->dev); |
7a3e97b0 SY |
2206 | /* check if reset is already in progress */ |
2207 | if (hba->ufshcd_state != UFSHCD_STATE_RESET) | |
2208 | ufshcd_do_reset(hba); | |
62694735 | 2209 | pm_runtime_put_sync(hba->dev); |
7a3e97b0 SY |
2210 | } |
2211 | ||
2212 | /** | |
2213 | * ufshcd_err_handler - Check for fatal errors | |
2214 | * @work: pointer to a work queue structure | |
2215 | */ | |
2216 | static void ufshcd_err_handler(struct ufs_hba *hba) | |
2217 | { | |
2218 | u32 reg; | |
2219 | ||
2220 | if (hba->errors & INT_FATAL_ERRORS) | |
2221 | goto fatal_eh; | |
2222 | ||
2223 | if (hba->errors & UIC_ERROR) { | |
cf9f4b59 | 2224 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); |
7a3e97b0 SY |
2225 | if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) |
2226 | goto fatal_eh; | |
2227 | } | |
2228 | return; | |
2229 | fatal_eh: | |
2230 | hba->ufshcd_state = UFSHCD_STATE_ERROR; | |
2231 | schedule_work(&hba->feh_workq); | |
2232 | } | |
2233 | ||
2234 | /** | |
2235 | * ufshcd_tmc_handler - handle task management function completion | |
2236 | * @hba: per adapter instance | |
2237 | */ | |
2238 | static void ufshcd_tmc_handler(struct ufs_hba *hba) | |
2239 | { | |
2240 | u32 tm_doorbell; | |
2241 | ||
b873a275 | 2242 | tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); |
7a3e97b0 SY |
2243 | hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks; |
2244 | wake_up_interruptible(&hba->ufshcd_tm_wait_queue); | |
2245 | } | |
2246 | ||
2247 | /** | |
2248 | * ufshcd_sl_intr - Interrupt service routine | |
2249 | * @hba: per adapter instance | |
2250 | * @intr_status: contains interrupts generated by the controller | |
2251 | */ | |
2252 | static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) | |
2253 | { | |
2254 | hba->errors = UFSHCD_ERROR_MASK & intr_status; | |
2255 | if (hba->errors) | |
2256 | ufshcd_err_handler(hba); | |
2257 | ||
2258 | if (intr_status & UIC_COMMAND_COMPL) | |
6ccf44fe | 2259 | ufshcd_uic_cmd_compl(hba); |
7a3e97b0 SY |
2260 | |
2261 | if (intr_status & UTP_TASK_REQ_COMPL) | |
2262 | ufshcd_tmc_handler(hba); | |
2263 | ||
2264 | if (intr_status & UTP_TRANSFER_REQ_COMPL) | |
2265 | ufshcd_transfer_req_compl(hba); | |
2266 | } | |
2267 | ||
2268 | /** | |
2269 | * ufshcd_intr - Main interrupt service routine | |
2270 | * @irq: irq number | |
2271 | * @__hba: pointer to adapter instance | |
2272 | * | |
2273 | * Returns IRQ_HANDLED - If interrupt is valid | |
2274 | * IRQ_NONE - If invalid interrupt | |
2275 | */ | |
2276 | static irqreturn_t ufshcd_intr(int irq, void *__hba) | |
2277 | { | |
2278 | u32 intr_status; | |
2279 | irqreturn_t retval = IRQ_NONE; | |
2280 | struct ufs_hba *hba = __hba; | |
2281 | ||
2282 | spin_lock(hba->host->host_lock); | |
b873a275 | 2283 | intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); |
7a3e97b0 SY |
2284 | |
2285 | if (intr_status) { | |
261ea452 | 2286 | ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); |
7a3e97b0 | 2287 | ufshcd_sl_intr(hba, intr_status); |
7a3e97b0 SY |
2288 | retval = IRQ_HANDLED; |
2289 | } | |
2290 | spin_unlock(hba->host->host_lock); | |
2291 | return retval; | |
2292 | } | |
2293 | ||
2294 | /** | |
2295 | * ufshcd_issue_tm_cmd - issues task management commands to controller | |
2296 | * @hba: per adapter instance | |
2297 | * @lrbp: pointer to local reference block | |
2298 | * | |
2299 | * Returns SUCCESS/FAILED | |
2300 | */ | |
2301 | static int | |
2302 | ufshcd_issue_tm_cmd(struct ufs_hba *hba, | |
2303 | struct ufshcd_lrb *lrbp, | |
2304 | u8 tm_function) | |
2305 | { | |
2306 | struct utp_task_req_desc *task_req_descp; | |
2307 | struct utp_upiu_task_req *task_req_upiup; | |
2308 | struct Scsi_Host *host; | |
2309 | unsigned long flags; | |
2310 | int free_slot = 0; | |
2311 | int err; | |
2312 | ||
2313 | host = hba->host; | |
2314 | ||
2315 | spin_lock_irqsave(host->host_lock, flags); | |
2316 | ||
2317 | /* If task management queue is full */ | |
2318 | free_slot = ufshcd_get_tm_free_slot(hba); | |
2319 | if (free_slot >= hba->nutmrs) { | |
2320 | spin_unlock_irqrestore(host->host_lock, flags); | |
3b1d0580 | 2321 | dev_err(hba->dev, "Task management queue full\n"); |
7a3e97b0 SY |
2322 | err = FAILED; |
2323 | goto out; | |
2324 | } | |
2325 | ||
2326 | task_req_descp = hba->utmrdl_base_addr; | |
2327 | task_req_descp += free_slot; | |
2328 | ||
2329 | /* Configure task request descriptor */ | |
2330 | task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD); | |
2331 | task_req_descp->header.dword_2 = | |
2332 | cpu_to_le32(OCS_INVALID_COMMAND_STATUS); | |
2333 | ||
2334 | /* Configure task request UPIU */ | |
2335 | task_req_upiup = | |
2336 | (struct utp_upiu_task_req *) task_req_descp->task_req_upiu; | |
2337 | task_req_upiup->header.dword_0 = | |
5a0b0cb9 SRT |
2338 | UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0, |
2339 | lrbp->lun, lrbp->task_tag); | |
7a3e97b0 | 2340 | task_req_upiup->header.dword_1 = |
5a0b0cb9 | 2341 | UPIU_HEADER_DWORD(0, tm_function, 0, 0); |
7a3e97b0 SY |
2342 | |
2343 | task_req_upiup->input_param1 = lrbp->lun; | |
2344 | task_req_upiup->input_param1 = | |
2345 | cpu_to_be32(task_req_upiup->input_param1); | |
2346 | task_req_upiup->input_param2 = lrbp->task_tag; | |
2347 | task_req_upiup->input_param2 = | |
2348 | cpu_to_be32(task_req_upiup->input_param2); | |
2349 | ||
2350 | /* send command to the controller */ | |
2351 | __set_bit(free_slot, &hba->outstanding_tasks); | |
b873a275 | 2352 | ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL); |
7a3e97b0 SY |
2353 | |
2354 | spin_unlock_irqrestore(host->host_lock, flags); | |
2355 | ||
2356 | /* wait until the task management command is completed */ | |
2357 | err = | |
2358 | wait_event_interruptible_timeout(hba->ufshcd_tm_wait_queue, | |
2359 | (test_bit(free_slot, | |
2360 | &hba->tm_condition) != 0), | |
2361 | 60 * HZ); | |
2362 | if (!err) { | |
3b1d0580 | 2363 | dev_err(hba->dev, |
7a3e97b0 SY |
2364 | "Task management command timed-out\n"); |
2365 | err = FAILED; | |
2366 | goto out; | |
2367 | } | |
2368 | clear_bit(free_slot, &hba->tm_condition); | |
94c122ab | 2369 | err = ufshcd_task_req_compl(hba, free_slot); |
7a3e97b0 SY |
2370 | out: |
2371 | return err; | |
2372 | } | |
2373 | ||
2374 | /** | |
2375 | * ufshcd_device_reset - reset device and abort all the pending commands | |
2376 | * @cmd: SCSI command pointer | |
2377 | * | |
2378 | * Returns SUCCESS/FAILED | |
2379 | */ | |
2380 | static int ufshcd_device_reset(struct scsi_cmnd *cmd) | |
2381 | { | |
2382 | struct Scsi_Host *host; | |
2383 | struct ufs_hba *hba; | |
2384 | unsigned int tag; | |
2385 | u32 pos; | |
2386 | int err; | |
2387 | ||
2388 | host = cmd->device->host; | |
2389 | hba = shost_priv(host); | |
2390 | tag = cmd->request->tag; | |
2391 | ||
2392 | err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_LOGICAL_RESET); | |
94c122ab | 2393 | if (err == FAILED) |
7a3e97b0 SY |
2394 | goto out; |
2395 | ||
2396 | for (pos = 0; pos < hba->nutrs; pos++) { | |
2397 | if (test_bit(pos, &hba->outstanding_reqs) && | |
2398 | (hba->lrb[tag].lun == hba->lrb[pos].lun)) { | |
2399 | ||
2400 | /* clear the respective UTRLCLR register bit */ | |
2401 | ufshcd_utrl_clear(hba, pos); | |
2402 | ||
2403 | clear_bit(pos, &hba->outstanding_reqs); | |
2404 | ||
2405 | if (hba->lrb[pos].cmd) { | |
2406 | scsi_dma_unmap(hba->lrb[pos].cmd); | |
2407 | hba->lrb[pos].cmd->result = | |
5a0b0cb9 | 2408 | DID_ABORT << 16; |
7a3e97b0 SY |
2409 | hba->lrb[pos].cmd->scsi_done(cmd); |
2410 | hba->lrb[pos].cmd = NULL; | |
5a0b0cb9 SRT |
2411 | clear_bit_unlock(pos, &hba->lrb_in_use); |
2412 | wake_up(&hba->dev_cmd.tag_wq); | |
7a3e97b0 SY |
2413 | } |
2414 | } | |
2415 | } /* end of for */ | |
2416 | out: | |
2417 | return err; | |
2418 | } | |
2419 | ||
2420 | /** | |
2421 | * ufshcd_host_reset - Main reset function registered with scsi layer | |
2422 | * @cmd: SCSI command pointer | |
2423 | * | |
2424 | * Returns SUCCESS/FAILED | |
2425 | */ | |
2426 | static int ufshcd_host_reset(struct scsi_cmnd *cmd) | |
2427 | { | |
2428 | struct ufs_hba *hba; | |
2429 | ||
2430 | hba = shost_priv(cmd->device->host); | |
2431 | ||
2432 | if (hba->ufshcd_state == UFSHCD_STATE_RESET) | |
2433 | return SUCCESS; | |
2434 | ||
94c122ab | 2435 | return ufshcd_do_reset(hba); |
7a3e97b0 SY |
2436 | } |
2437 | ||
2438 | /** | |
2439 | * ufshcd_abort - abort a specific command | |
2440 | * @cmd: SCSI command pointer | |
2441 | * | |
2442 | * Returns SUCCESS/FAILED | |
2443 | */ | |
2444 | static int ufshcd_abort(struct scsi_cmnd *cmd) | |
2445 | { | |
2446 | struct Scsi_Host *host; | |
2447 | struct ufs_hba *hba; | |
2448 | unsigned long flags; | |
2449 | unsigned int tag; | |
2450 | int err; | |
2451 | ||
2452 | host = cmd->device->host; | |
2453 | hba = shost_priv(host); | |
2454 | tag = cmd->request->tag; | |
2455 | ||
2456 | spin_lock_irqsave(host->host_lock, flags); | |
2457 | ||
2458 | /* check if command is still pending */ | |
2459 | if (!(test_bit(tag, &hba->outstanding_reqs))) { | |
2460 | err = FAILED; | |
2461 | spin_unlock_irqrestore(host->host_lock, flags); | |
2462 | goto out; | |
2463 | } | |
2464 | spin_unlock_irqrestore(host->host_lock, flags); | |
2465 | ||
2466 | err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_ABORT_TASK); | |
94c122ab | 2467 | if (err == FAILED) |
7a3e97b0 SY |
2468 | goto out; |
2469 | ||
2470 | scsi_dma_unmap(cmd); | |
2471 | ||
2472 | spin_lock_irqsave(host->host_lock, flags); | |
2473 | ||
2474 | /* clear the respective UTRLCLR register bit */ | |
2475 | ufshcd_utrl_clear(hba, tag); | |
2476 | ||
2477 | __clear_bit(tag, &hba->outstanding_reqs); | |
2478 | hba->lrb[tag].cmd = NULL; | |
2479 | spin_unlock_irqrestore(host->host_lock, flags); | |
5a0b0cb9 SRT |
2480 | |
2481 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
2482 | wake_up(&hba->dev_cmd.tag_wq); | |
7a3e97b0 SY |
2483 | out: |
2484 | return err; | |
2485 | } | |
2486 | ||
6ccf44fe SJ |
2487 | /** |
2488 | * ufshcd_async_scan - asynchronous execution for link startup | |
2489 | * @data: data pointer to pass to this function | |
2490 | * @cookie: cookie data | |
2491 | */ | |
2492 | static void ufshcd_async_scan(void *data, async_cookie_t cookie) | |
2493 | { | |
2494 | struct ufs_hba *hba = (struct ufs_hba *)data; | |
2495 | int ret; | |
2496 | ||
2497 | ret = ufshcd_link_startup(hba); | |
5a0b0cb9 SRT |
2498 | if (ret) |
2499 | goto out; | |
2500 | ||
2501 | ret = ufshcd_verify_dev_init(hba); | |
2502 | if (ret) | |
2503 | goto out; | |
68078d5c DR |
2504 | |
2505 | ret = ufshcd_complete_dev_init(hba); | |
2506 | if (ret) | |
2507 | goto out; | |
5a0b0cb9 | 2508 | |
66ec6d59 | 2509 | ufshcd_force_reset_auto_bkops(hba); |
5a0b0cb9 | 2510 | scsi_scan_host(hba->host); |
62694735 | 2511 | pm_runtime_put_sync(hba->dev); |
5a0b0cb9 SRT |
2512 | out: |
2513 | return; | |
6ccf44fe SJ |
2514 | } |
2515 | ||
7a3e97b0 SY |
2516 | static struct scsi_host_template ufshcd_driver_template = { |
2517 | .module = THIS_MODULE, | |
2518 | .name = UFSHCD, | |
2519 | .proc_name = UFSHCD, | |
2520 | .queuecommand = ufshcd_queuecommand, | |
2521 | .slave_alloc = ufshcd_slave_alloc, | |
2522 | .slave_destroy = ufshcd_slave_destroy, | |
2523 | .eh_abort_handler = ufshcd_abort, | |
2524 | .eh_device_reset_handler = ufshcd_device_reset, | |
2525 | .eh_host_reset_handler = ufshcd_host_reset, | |
2526 | .this_id = -1, | |
2527 | .sg_tablesize = SG_ALL, | |
2528 | .cmd_per_lun = UFSHCD_CMD_PER_LUN, | |
2529 | .can_queue = UFSHCD_CAN_QUEUE, | |
2530 | }; | |
2531 | ||
7a3e97b0 SY |
2532 | /** |
2533 | * ufshcd_suspend - suspend power management function | |
3b1d0580 | 2534 | * @hba: per adapter instance |
7a3e97b0 SY |
2535 | * @state: power state |
2536 | * | |
2537 | * Returns -ENOSYS | |
2538 | */ | |
3b1d0580 | 2539 | int ufshcd_suspend(struct ufs_hba *hba, pm_message_t state) |
7a3e97b0 SY |
2540 | { |
2541 | /* | |
2542 | * TODO: | |
2543 | * 1. Block SCSI requests from SCSI midlayer | |
2544 | * 2. Change the internal driver state to non operational | |
2545 | * 3. Set UTRLRSR and UTMRLRSR bits to zero | |
2546 | * 4. Wait until outstanding commands are completed | |
2547 | * 5. Set HCE to zero to send the UFS host controller to reset state | |
2548 | */ | |
2549 | ||
2550 | return -ENOSYS; | |
2551 | } | |
3b1d0580 | 2552 | EXPORT_SYMBOL_GPL(ufshcd_suspend); |
7a3e97b0 SY |
2553 | |
2554 | /** | |
2555 | * ufshcd_resume - resume power management function | |
3b1d0580 | 2556 | * @hba: per adapter instance |
7a3e97b0 SY |
2557 | * |
2558 | * Returns -ENOSYS | |
2559 | */ | |
3b1d0580 | 2560 | int ufshcd_resume(struct ufs_hba *hba) |
7a3e97b0 SY |
2561 | { |
2562 | /* | |
2563 | * TODO: | |
2564 | * 1. Set HCE to 1, to start the UFS host controller | |
2565 | * initialization process | |
2566 | * 2. Set UTRLRSR and UTMRLRSR bits to 1 | |
2567 | * 3. Change the internal driver state to operational | |
2568 | * 4. Unblock SCSI requests from SCSI midlayer | |
2569 | */ | |
2570 | ||
2571 | return -ENOSYS; | |
2572 | } | |
3b1d0580 VH |
2573 | EXPORT_SYMBOL_GPL(ufshcd_resume); |
2574 | ||
66ec6d59 SRT |
2575 | int ufshcd_runtime_suspend(struct ufs_hba *hba) |
2576 | { | |
2577 | if (!hba) | |
2578 | return 0; | |
2579 | ||
2580 | /* | |
2581 | * The device is idle with no requests in the queue, | |
2582 | * allow background operations. | |
2583 | */ | |
2584 | return ufshcd_enable_auto_bkops(hba); | |
2585 | } | |
2586 | EXPORT_SYMBOL(ufshcd_runtime_suspend); | |
2587 | ||
2588 | int ufshcd_runtime_resume(struct ufs_hba *hba) | |
2589 | { | |
2590 | if (!hba) | |
2591 | return 0; | |
2592 | ||
2593 | return ufshcd_disable_auto_bkops(hba); | |
2594 | } | |
2595 | EXPORT_SYMBOL(ufshcd_runtime_resume); | |
2596 | ||
2597 | int ufshcd_runtime_idle(struct ufs_hba *hba) | |
2598 | { | |
2599 | return 0; | |
2600 | } | |
2601 | EXPORT_SYMBOL(ufshcd_runtime_idle); | |
2602 | ||
7a3e97b0 | 2603 | /** |
3b1d0580 | 2604 | * ufshcd_remove - de-allocate SCSI host and host memory space |
7a3e97b0 | 2605 | * data structure memory |
3b1d0580 | 2606 | * @hba - per adapter instance |
7a3e97b0 | 2607 | */ |
3b1d0580 | 2608 | void ufshcd_remove(struct ufs_hba *hba) |
7a3e97b0 | 2609 | { |
cfdf9c91 | 2610 | scsi_remove_host(hba->host); |
7a3e97b0 | 2611 | /* disable interrupts */ |
2fbd009b | 2612 | ufshcd_disable_intr(hba, hba->intr_mask); |
7a3e97b0 | 2613 | ufshcd_hba_stop(hba); |
7a3e97b0 | 2614 | |
7a3e97b0 | 2615 | scsi_host_put(hba->host); |
3b1d0580 VH |
2616 | } |
2617 | EXPORT_SYMBOL_GPL(ufshcd_remove); | |
2618 | ||
7a3e97b0 | 2619 | /** |
3b1d0580 VH |
2620 | * ufshcd_init - Driver initialization routine |
2621 | * @dev: pointer to device handle | |
2622 | * @hba_handle: driver private handle | |
2623 | * @mmio_base: base register address | |
2624 | * @irq: Interrupt line of device | |
7a3e97b0 SY |
2625 | * Returns 0 on success, non-zero value on failure |
2626 | */ | |
3b1d0580 VH |
2627 | int ufshcd_init(struct device *dev, struct ufs_hba **hba_handle, |
2628 | void __iomem *mmio_base, unsigned int irq) | |
7a3e97b0 SY |
2629 | { |
2630 | struct Scsi_Host *host; | |
2631 | struct ufs_hba *hba; | |
2632 | int err; | |
2633 | ||
3b1d0580 VH |
2634 | if (!dev) { |
2635 | dev_err(dev, | |
2636 | "Invalid memory reference for dev is NULL\n"); | |
2637 | err = -ENODEV; | |
7a3e97b0 SY |
2638 | goto out_error; |
2639 | } | |
2640 | ||
3b1d0580 VH |
2641 | if (!mmio_base) { |
2642 | dev_err(dev, | |
2643 | "Invalid memory reference for mmio_base is NULL\n"); | |
2644 | err = -ENODEV; | |
2645 | goto out_error; | |
2646 | } | |
7a3e97b0 SY |
2647 | |
2648 | host = scsi_host_alloc(&ufshcd_driver_template, | |
2649 | sizeof(struct ufs_hba)); | |
2650 | if (!host) { | |
3b1d0580 | 2651 | dev_err(dev, "scsi_host_alloc failed\n"); |
7a3e97b0 | 2652 | err = -ENOMEM; |
3b1d0580 | 2653 | goto out_error; |
7a3e97b0 SY |
2654 | } |
2655 | hba = shost_priv(host); | |
7a3e97b0 | 2656 | hba->host = host; |
3b1d0580 VH |
2657 | hba->dev = dev; |
2658 | hba->mmio_base = mmio_base; | |
2659 | hba->irq = irq; | |
7a3e97b0 SY |
2660 | |
2661 | /* Read capabilities registers */ | |
2662 | ufshcd_hba_capabilities(hba); | |
2663 | ||
2664 | /* Get UFS version supported by the controller */ | |
2665 | hba->ufs_version = ufshcd_get_ufs_version(hba); | |
2666 | ||
2fbd009b SJ |
2667 | /* Get Interrupt bit mask per version */ |
2668 | hba->intr_mask = ufshcd_get_intr_mask(hba); | |
2669 | ||
7a3e97b0 SY |
2670 | /* Allocate memory for host memory space */ |
2671 | err = ufshcd_memory_alloc(hba); | |
2672 | if (err) { | |
3b1d0580 VH |
2673 | dev_err(hba->dev, "Memory allocation failed\n"); |
2674 | goto out_disable; | |
7a3e97b0 SY |
2675 | } |
2676 | ||
2677 | /* Configure LRB */ | |
2678 | ufshcd_host_memory_configure(hba); | |
2679 | ||
2680 | host->can_queue = hba->nutrs; | |
2681 | host->cmd_per_lun = hba->nutrs; | |
2682 | host->max_id = UFSHCD_MAX_ID; | |
2683 | host->max_lun = UFSHCD_MAX_LUNS; | |
2684 | host->max_channel = UFSHCD_MAX_CHANNEL; | |
2685 | host->unique_id = host->host_no; | |
2686 | host->max_cmd_len = MAX_CDB_SIZE; | |
2687 | ||
2688 | /* Initailize wait queue for task management */ | |
2689 | init_waitqueue_head(&hba->ufshcd_tm_wait_queue); | |
2690 | ||
2691 | /* Initialize work queues */ | |
7a3e97b0 | 2692 | INIT_WORK(&hba->feh_workq, ufshcd_fatal_err_handler); |
66ec6d59 | 2693 | INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); |
7a3e97b0 | 2694 | |
6ccf44fe SJ |
2695 | /* Initialize UIC command mutex */ |
2696 | mutex_init(&hba->uic_cmd_mutex); | |
2697 | ||
5a0b0cb9 SRT |
2698 | /* Initialize mutex for device management commands */ |
2699 | mutex_init(&hba->dev_cmd.lock); | |
2700 | ||
2701 | /* Initialize device management tag acquire wait queue */ | |
2702 | init_waitqueue_head(&hba->dev_cmd.tag_wq); | |
2703 | ||
7a3e97b0 | 2704 | /* IRQ registration */ |
2953f850 | 2705 | err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); |
7a3e97b0 | 2706 | if (err) { |
3b1d0580 | 2707 | dev_err(hba->dev, "request irq failed\n"); |
2953f850 | 2708 | goto out_disable; |
7a3e97b0 SY |
2709 | } |
2710 | ||
2711 | /* Enable SCSI tag mapping */ | |
2712 | err = scsi_init_shared_tag_map(host, host->can_queue); | |
2713 | if (err) { | |
3b1d0580 | 2714 | dev_err(hba->dev, "init shared queue failed\n"); |
2953f850 | 2715 | goto out_disable; |
7a3e97b0 SY |
2716 | } |
2717 | ||
3b1d0580 | 2718 | err = scsi_add_host(host, hba->dev); |
7a3e97b0 | 2719 | if (err) { |
3b1d0580 | 2720 | dev_err(hba->dev, "scsi_add_host failed\n"); |
2953f850 | 2721 | goto out_disable; |
7a3e97b0 SY |
2722 | } |
2723 | ||
6ccf44fe SJ |
2724 | /* Host controller enable */ |
2725 | err = ufshcd_hba_enable(hba); | |
7a3e97b0 | 2726 | if (err) { |
6ccf44fe | 2727 | dev_err(hba->dev, "Host controller enable failed\n"); |
3b1d0580 | 2728 | goto out_remove_scsi_host; |
7a3e97b0 | 2729 | } |
6ccf44fe | 2730 | |
3b1d0580 | 2731 | *hba_handle = hba; |
7a3e97b0 | 2732 | |
62694735 SRT |
2733 | /* Hold auto suspend until async scan completes */ |
2734 | pm_runtime_get_sync(dev); | |
2735 | ||
6ccf44fe SJ |
2736 | async_schedule(ufshcd_async_scan, hba); |
2737 | ||
7a3e97b0 SY |
2738 | return 0; |
2739 | ||
3b1d0580 VH |
2740 | out_remove_scsi_host: |
2741 | scsi_remove_host(hba->host); | |
3b1d0580 VH |
2742 | out_disable: |
2743 | scsi_host_put(host); | |
2744 | out_error: | |
2745 | return err; | |
2746 | } | |
2747 | EXPORT_SYMBOL_GPL(ufshcd_init); | |
2748 | ||
3b1d0580 VH |
2749 | MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); |
2750 | MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); | |
e0eca63e | 2751 | MODULE_DESCRIPTION("Generic UFS host controller driver Core"); |
7a3e97b0 SY |
2752 | MODULE_LICENSE("GPL"); |
2753 | MODULE_VERSION(UFSHCD_DRIVER_VERSION); |