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lpfc: remove queue_depth events
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
5c0c28a8 6 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
6ccf44fe 42
e0eca63e 43#include "ufshcd.h"
53b3d9c3 44#include "unipro.h"
7a3e97b0 45
2fbd009b
SJ		 46#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
47 UTP_TASK_REQ_COMPL |\
48 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 49/* UIC command timeout, unit: ms */
50#define UIC_CMD_TIMEOUT 500
2fbd009b 51
5a0b0cb9
SRT		 52/* NOP OUT retries waiting for NOP IN response */
53#define NOP_OUT_RETRIES 10
54/* Timeout after 30 msecs if NOP OUT hangs without response */
55#define NOP_OUT_TIMEOUT 30 /* msecs */
56
68078d5c
DR		 57/* Query request retries */
58#define QUERY_REQ_RETRIES 10
59/* Query request timeout */
60#define QUERY_REQ_TIMEOUT 30 /* msec */
61
e2933132
SRT		 62/* Task management command timeout */
63#define TM_CMD_TIMEOUT 100 /* msecs */
64
1d337ec2
SRT		 65/* maximum number of link-startup retries */
66#define DME_LINKSTARTUP_RETRIES 3
67
68/* maximum number of reset retries before giving up */
69#define MAX_HOST_RESET_RETRIES 5
70
68078d5c
DR		 71/* Expose the flag value from utp_upiu_query.value */
72#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
73
7d568652
SJ		 74/* Interrupt aggregation default timeout, unit: 40us */
75#define INT_AGGR_DEF_TO 0x02
76
aa497613
SRT		 77#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
78 ({ \
79 int _ret; \
80 if (_on) \
81 _ret = ufshcd_enable_vreg(_dev, _vreg); \
82 else \
83 _ret = ufshcd_disable_vreg(_dev, _vreg); \
84 _ret; \
85 })
86
da461cec
SJ		 87static u32 ufs_query_desc_max_size[] = {
88 QUERY_DESC_DEVICE_MAX_SIZE,
89 QUERY_DESC_CONFIGURAION_MAX_SIZE,
90 QUERY_DESC_UNIT_MAX_SIZE,
91 QUERY_DESC_RFU_MAX_SIZE,
92 QUERY_DESC_INTERCONNECT_MAX_SIZE,
93 QUERY_DESC_STRING_MAX_SIZE,
94 QUERY_DESC_RFU_MAX_SIZE,
95 QUERY_DESC_GEOMETRY_MAZ_SIZE,
96 QUERY_DESC_POWER_MAX_SIZE,
97 QUERY_DESC_RFU_MAX_SIZE,
98};
99
7a3e97b0
SY		 100enum {
101 UFSHCD_MAX_CHANNEL = 0,
102 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 103 UFSHCD_CMD_PER_LUN = 32,
104 UFSHCD_CAN_QUEUE = 32,
105};
106
107/* UFSHCD states */
108enum {
7a3e97b0
SY		 109 UFSHCD_STATE_RESET,
110 UFSHCD_STATE_ERROR,
3441da7d
SRT		 111 UFSHCD_STATE_OPERATIONAL,
112};
113
114/* UFSHCD error handling flags */
115enum {
116 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 117};
118
e8e7f271
SRT		 119/* UFSHCD UIC layer error flags */
120enum {
121 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
122 UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
123 UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
124 UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
125};
126
7a3e97b0
SY		 127/* Interrupt configuration options */
128enum {
129 UFSHCD_INT_DISABLE,
130 UFSHCD_INT_ENABLE,
131 UFSHCD_INT_CLEAR,
132};
133
3441da7d
SRT		 134#define ufshcd_set_eh_in_progress(h) \
135 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
136#define ufshcd_eh_in_progress(h) \
137 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
138#define ufshcd_clear_eh_in_progress(h) \
139 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
140
57d104c1
SJ		 141#define ufshcd_set_ufs_dev_active(h) \
142 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
143#define ufshcd_set_ufs_dev_sleep(h) \
144 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
145#define ufshcd_set_ufs_dev_poweroff(h) \
146 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
147#define ufshcd_is_ufs_dev_active(h) \
148 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
149#define ufshcd_is_ufs_dev_sleep(h) \
150 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
151#define ufshcd_is_ufs_dev_poweroff(h) \
152 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
153
154static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
155 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
156 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
157 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
158 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
159 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
160 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
161};
162
163static inline enum ufs_dev_pwr_mode
164ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
165{
166 return ufs_pm_lvl_states[lvl].dev_state;
167}
168
169static inline enum uic_link_state
170ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
171{
172 return ufs_pm_lvl_states[lvl].link_state;
173}
174
3441da7d
SRT		 175static void ufshcd_tmc_handler(struct ufs_hba *hba);
176static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 177static int ufshcd_reset_and_restore(struct ufs_hba *hba);
178static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 179static void ufshcd_hba_exit(struct ufs_hba *hba);
180static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 181static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
182 bool skip_ref_clk);
183static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
184static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
185static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
57d104c1
SJ		 186static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
187static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 188static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
189 struct ufs_pa_layer_attr *desired_pwr_mode);
57d104c1
SJ		 190
191static inline int ufshcd_enable_irq(struct ufs_hba *hba)
192{
193 int ret = 0;
194
195 if (!hba->is_irq_enabled) {
196 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
197 hba);
198 if (ret)
199 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
200 __func__, ret);
201 hba->is_irq_enabled = true;
202 }
203
204 return ret;
205}
206
207static inline void ufshcd_disable_irq(struct ufs_hba *hba)
208{
209 if (hba->is_irq_enabled) {
210 free_irq(hba->irq, hba);
211 hba->is_irq_enabled = false;
212 }
213}
3441da7d 214
5a0b0cb9
SRT		 215/*
216 * ufshcd_wait_for_register - wait for register value to change
217 * @hba - per-adapter interface
218 * @reg - mmio register offset
219 * @mask - mask to apply to read register value
220 * @val - wait condition
221 * @interval_us - polling interval in microsecs
222 * @timeout_ms - timeout in millisecs
223 *
224 * Returns -ETIMEDOUT on error, zero on success
225 */
226static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
227 u32 val, unsigned long interval_us, unsigned long timeout_ms)
228{
229 int err = 0;
230 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
231
232 /* ignore bits that we don't intend to wait on */
233 val = val & mask;
234
235 while ((ufshcd_readl(hba, reg) & mask) != val) {
236 /* wakeup within 50us of expiry */
237 usleep_range(interval_us, interval_us + 50);
238
239 if (time_after(jiffies, timeout)) {
240 if ((ufshcd_readl(hba, reg) & mask) != val)
241 err = -ETIMEDOUT;
242 break;
243 }
244 }
245
246 return err;
247}
248
2fbd009b
SJ		 249/**
250 * ufshcd_get_intr_mask - Get the interrupt bit mask
251 * @hba - Pointer to adapter instance
252 *
253 * Returns interrupt bit mask per version
254 */
255static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
256{
257 if (hba->ufs_version == UFSHCI_VERSION_10)
258 return INTERRUPT_MASK_ALL_VER_10;
259 else
260 return INTERRUPT_MASK_ALL_VER_11;
261}
262
7a3e97b0
SY		 263/**
264 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
265 * @hba - Pointer to adapter instance
266 *
267 * Returns UFSHCI version supported by the controller
268 */
269static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
270{
b873a275 271 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 272}
273
274/**
275 * ufshcd_is_device_present - Check if any device connected to
276 * the host controller
5c0c28a8 277 * @hba: pointer to adapter instance
7a3e97b0 278 *
73ec513a 279 * Returns 1 if device present, 0 if no device detected
7a3e97b0 280 */
5c0c28a8 281static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 282{
5c0c28a8
SRT		 283 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
284 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 285}
286
287/**
288 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
289 * @lrb: pointer to local command reference block
290 *
291 * This function is used to get the OCS field from UTRD
292 * Returns the OCS field in the UTRD
293 */
294static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
295{
e8c8e82a 296 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 297}
298
299/**
300 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
301 * @task_req_descp: pointer to utp_task_req_desc structure
302 *
303 * This function is used to get the OCS field from UTMRD
304 * Returns the OCS field in the UTMRD
305 */
306static inline int
307ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
308{
e8c8e82a 309 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 310}
311
312/**
313 * ufshcd_get_tm_free_slot - get a free slot for task management request
314 * @hba: per adapter instance
e2933132 315 * @free_slot: pointer to variable with available slot value
7a3e97b0 316 *
e2933132
SRT		 317 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
318 * Returns 0 if free slot is not available, else return 1 with tag value
319 * in @free_slot.
7a3e97b0 320 */
e2933132 321static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 322{
e2933132
SRT		 323 int tag;
324 bool ret = false;
325
326 if (!free_slot)
327 goto out;
328
329 do {
330 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
331 if (tag >= hba->nutmrs)
332 goto out;
333 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
334
335 *free_slot = tag;
336 ret = true;
337out:
338 return ret;
339}
340
341static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
342{
343 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 344}
345
346/**
347 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
348 * @hba: per adapter instance
349 * @pos: position of the bit to be cleared
350 */
351static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
352{
b873a275 353 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 354}
355
356/**
357 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
358 * @reg: Register value of host controller status
359 *
360 * Returns integer, 0 on Success and positive value if failed
361 */
362static inline int ufshcd_get_lists_status(u32 reg)
363{
364 /*
365 * The mask 0xFF is for the following HCS register bits
366 * Bit Description
367 * 0 Device Present
368 * 1 UTRLRDY
369 * 2 UTMRLRDY
370 * 3 UCRDY
371 * 4 HEI
372 * 5 DEI
373 * 6-7 reserved
374 */
375 return (((reg) & (0xFF)) >> 1) ^ (0x07);
376}
377
378/**
379 * ufshcd_get_uic_cmd_result - Get the UIC command result
380 * @hba: Pointer to adapter instance
381 *
382 * This function gets the result of UIC command completion
383 * Returns 0 on success, non zero value on error
384 */
385static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
386{
b873a275 387 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 388 MASK_UIC_COMMAND_RESULT;
389}
390
12b4fdb4
SJ		 391/**
392 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
393 * @hba: Pointer to adapter instance
394 *
395 * This function gets UIC command argument3
396 * Returns 0 on success, non zero value on error
397 */
398static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
399{
400 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
401}
402
7a3e97b0 403/**
5a0b0cb9 404 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 405 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 406 */
407static inline int
5a0b0cb9 408ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 409{
5a0b0cb9 410 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 411}
412
413/**
414 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
415 * @ucd_rsp_ptr: pointer to response UPIU
416 *
417 * This function gets the response status and scsi_status from response UPIU
418 * Returns the response result code.
419 */
420static inline int
421ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
422{
423 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
424}
425
1c2623c5
SJ		 426/*
427 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
428 * from response UPIU
429 * @ucd_rsp_ptr: pointer to response UPIU
430 *
431 * Return the data segment length.
432 */
433static inline unsigned int
434ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
435{
436 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
437 MASK_RSP_UPIU_DATA_SEG_LEN;
438}
439
66ec6d59
SRT		 440/**
441 * ufshcd_is_exception_event - Check if the device raised an exception event
442 * @ucd_rsp_ptr: pointer to response UPIU
443 *
444 * The function checks if the device raised an exception event indicated in
445 * the Device Information field of response UPIU.
446 *
447 * Returns true if exception is raised, false otherwise.
448 */
449static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
450{
451 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
452 MASK_RSP_EXCEPTION_EVENT ? true : false;
453}
454
7a3e97b0 455/**
7d568652 456 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 457 * @hba: per adapter instance
7a3e97b0
SY		 458 */
459static inline void
7d568652 460ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 461{
7d568652
SJ		 462 ufshcd_writel(hba, INT_AGGR_ENABLE |
463 INT_AGGR_COUNTER_AND_TIMER_RESET,
464 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
465}
466
467/**
468 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
469 * @hba: per adapter instance
470 * @cnt: Interrupt aggregation counter threshold
471 * @tmout: Interrupt aggregation timeout value
472 */
473static inline void
474ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
475{
476 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
477 INT_AGGR_COUNTER_THLD_VAL(cnt) |
478 INT_AGGR_TIMEOUT_VAL(tmout),
479 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 480}
481
482/**
483 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
484 * When run-stop registers are set to 1, it indicates the
485 * host controller that it can process the requests
486 * @hba: per adapter instance
487 */
488static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
489{
b873a275
SJ		 490 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
491 REG_UTP_TASK_REQ_LIST_RUN_STOP);
492 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
493 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 494}
495
7a3e97b0
SY		 496/**
497 * ufshcd_hba_start - Start controller initialization sequence
498 * @hba: per adapter instance
499 */
500static inline void ufshcd_hba_start(struct ufs_hba *hba)
501{
b873a275 502 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 503}
504
505/**
506 * ufshcd_is_hba_active - Get controller state
507 * @hba: per adapter instance
508 *
509 * Returns zero if controller is active, 1 otherwise
510 */
511static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
512{
b873a275 513 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 514}
515
1ab27c9c
ST		 516static void ufshcd_ungate_work(struct work_struct *work)
517{
518 int ret;
519 unsigned long flags;
520 struct ufs_hba *hba = container_of(work, struct ufs_hba,
521 clk_gating.ungate_work);
522
523 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
524
525 spin_lock_irqsave(hba->host->host_lock, flags);
526 if (hba->clk_gating.state == CLKS_ON) {
527 spin_unlock_irqrestore(hba->host->host_lock, flags);
528 goto unblock_reqs;
529 }
530
531 spin_unlock_irqrestore(hba->host->host_lock, flags);
532 ufshcd_setup_clocks(hba, true);
533
534 /* Exit from hibern8 */
535 if (ufshcd_can_hibern8_during_gating(hba)) {
536 /* Prevent gating in this path */
537 hba->clk_gating.is_suspended = true;
538 if (ufshcd_is_link_hibern8(hba)) {
539 ret = ufshcd_uic_hibern8_exit(hba);
540 if (ret)
541 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
542 __func__, ret);
543 else
544 ufshcd_set_link_active(hba);
545 }
546 hba->clk_gating.is_suspended = false;
547 }
548unblock_reqs:
856b3483
ST		 549 if (ufshcd_is_clkscaling_enabled(hba))
550 devfreq_resume_device(hba->devfreq);
1ab27c9c
ST		 551 scsi_unblock_requests(hba->host);
552}
553
554/**
555 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
556 * Also, exit from hibern8 mode and set the link as active.
557 * @hba: per adapter instance
558 * @async: This indicates whether caller should ungate clocks asynchronously.
559 */
560int ufshcd_hold(struct ufs_hba *hba, bool async)
561{
562 int rc = 0;
563 unsigned long flags;
564
565 if (!ufshcd_is_clkgating_allowed(hba))
566 goto out;
1ab27c9c
ST		 567 spin_lock_irqsave(hba->host->host_lock, flags);
568 hba->clk_gating.active_reqs++;
569
856b3483 570start:
1ab27c9c
ST		 571 switch (hba->clk_gating.state) {
572 case CLKS_ON:
573 break;
574 case REQ_CLKS_OFF:
575 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
576 hba->clk_gating.state = CLKS_ON;
577 break;
578 }
579 /*
580 * If we here, it means gating work is either done or
581 * currently running. Hence, fall through to cancel gating
582 * work and to enable clocks.
583 */
584 case CLKS_OFF:
585 scsi_block_requests(hba->host);
586 hba->clk_gating.state = REQ_CLKS_ON;
587 schedule_work(&hba->clk_gating.ungate_work);
588 /*
589 * fall through to check if we should wait for this
590 * work to be done or not.
591 */
592 case REQ_CLKS_ON:
593 if (async) {
594 rc = -EAGAIN;
595 hba->clk_gating.active_reqs--;
596 break;
597 }
598
599 spin_unlock_irqrestore(hba->host->host_lock, flags);
600 flush_work(&hba->clk_gating.ungate_work);
601 /* Make sure state is CLKS_ON before returning */
856b3483 602 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 603 goto start;
604 default:
605 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
606 __func__, hba->clk_gating.state);
607 break;
608 }
609 spin_unlock_irqrestore(hba->host->host_lock, flags);
610out:
611 return rc;
612}
613
614static void ufshcd_gate_work(struct work_struct *work)
615{
616 struct ufs_hba *hba = container_of(work, struct ufs_hba,
617 clk_gating.gate_work.work);
618 unsigned long flags;
619
620 spin_lock_irqsave(hba->host->host_lock, flags);
621 if (hba->clk_gating.is_suspended) {
622 hba->clk_gating.state = CLKS_ON;
623 goto rel_lock;
624 }
625
626 if (hba->clk_gating.active_reqs
627 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
628 || hba->lrb_in_use || hba->outstanding_tasks
629 || hba->active_uic_cmd || hba->uic_async_done)
630 goto rel_lock;
631
632 spin_unlock_irqrestore(hba->host->host_lock, flags);
633
634 /* put the link into hibern8 mode before turning off clocks */
635 if (ufshcd_can_hibern8_during_gating(hba)) {
636 if (ufshcd_uic_hibern8_enter(hba)) {
637 hba->clk_gating.state = CLKS_ON;
638 goto out;
639 }
640 ufshcd_set_link_hibern8(hba);
641 }
642
856b3483
ST		 643 if (ufshcd_is_clkscaling_enabled(hba)) {
644 devfreq_suspend_device(hba->devfreq);
645 hba->clk_scaling.window_start_t = 0;
646 }
647
1ab27c9c
ST		 648 if (!ufshcd_is_link_active(hba))
649 ufshcd_setup_clocks(hba, false);
650 else
651 /* If link is active, device ref_clk can't be switched off */
652 __ufshcd_setup_clocks(hba, false, true);
653
654 /*
655 * In case you are here to cancel this work the gating state
656 * would be marked as REQ_CLKS_ON. In this case keep the state
657 * as REQ_CLKS_ON which would anyway imply that clocks are off
658 * and a request to turn them on is pending. By doing this way,
659 * we keep the state machine in tact and this would ultimately
660 * prevent from doing cancel work multiple times when there are
661 * new requests arriving before the current cancel work is done.
662 */
663 spin_lock_irqsave(hba->host->host_lock, flags);
664 if (hba->clk_gating.state == REQ_CLKS_OFF)
665 hba->clk_gating.state = CLKS_OFF;
666
667rel_lock:
668 spin_unlock_irqrestore(hba->host->host_lock, flags);
669out:
670 return;
671}
672
673/* host lock must be held before calling this variant */
674static void __ufshcd_release(struct ufs_hba *hba)
675{
676 if (!ufshcd_is_clkgating_allowed(hba))
677 return;
678
679 hba->clk_gating.active_reqs--;
680
681 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
682 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
683 || hba->lrb_in_use || hba->outstanding_tasks
684 || hba->active_uic_cmd || hba->uic_async_done)
685 return;
686
687 hba->clk_gating.state = REQ_CLKS_OFF;
688 schedule_delayed_work(&hba->clk_gating.gate_work,
689 msecs_to_jiffies(hba->clk_gating.delay_ms));
690}
691
692void ufshcd_release(struct ufs_hba *hba)
693{
694 unsigned long flags;
695
696 spin_lock_irqsave(hba->host->host_lock, flags);
697 __ufshcd_release(hba);
698 spin_unlock_irqrestore(hba->host->host_lock, flags);
699}
700
701static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
702 struct device_attribute *attr, char *buf)
703{
704 struct ufs_hba *hba = dev_get_drvdata(dev);
705
706 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
707}
708
709static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
710 struct device_attribute *attr, const char *buf, size_t count)
711{
712 struct ufs_hba *hba = dev_get_drvdata(dev);
713 unsigned long flags, value;
714
715 if (kstrtoul(buf, 0, &value))
716 return -EINVAL;
717
718 spin_lock_irqsave(hba->host->host_lock, flags);
719 hba->clk_gating.delay_ms = value;
720 spin_unlock_irqrestore(hba->host->host_lock, flags);
721 return count;
722}
723
724static void ufshcd_init_clk_gating(struct ufs_hba *hba)
725{
726 if (!ufshcd_is_clkgating_allowed(hba))
727 return;
728
729 hba->clk_gating.delay_ms = 150;
730 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
731 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
732
733 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
734 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
735 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
736 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
737 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
738 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
739 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
740}
741
742static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
743{
744 if (!ufshcd_is_clkgating_allowed(hba))
745 return;
746 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
747}
748
856b3483
ST		 749/* Must be called with host lock acquired */
750static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
751{
752 if (!ufshcd_is_clkscaling_enabled(hba))
753 return;
754
755 if (!hba->clk_scaling.is_busy_started) {
756 hba->clk_scaling.busy_start_t = ktime_get();
757 hba->clk_scaling.is_busy_started = true;
758 }
759}
760
761static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
762{
763 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
764
765 if (!ufshcd_is_clkscaling_enabled(hba))
766 return;
767
768 if (!hba->outstanding_reqs && scaling->is_busy_started) {
769 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
770 scaling->busy_start_t));
771 scaling->busy_start_t = ktime_set(0, 0);
772 scaling->is_busy_started = false;
773 }
774}
7a3e97b0
SY		 775/**
776 * ufshcd_send_command - Send SCSI or device management commands
777 * @hba: per adapter instance
778 * @task_tag: Task tag of the command
779 */
780static inline
781void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
782{
856b3483 783 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 784 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 785 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 786}
787
788/**
789 * ufshcd_copy_sense_data - Copy sense data in case of check condition
790 * @lrb - pointer to local reference block
791 */
792static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
793{
794 int len;
1c2623c5
SJ		 795 if (lrbp->sense_buffer &&
796 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
5a0b0cb9 797 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
7a3e97b0 798 memcpy(lrbp->sense_buffer,
5a0b0cb9 799 lrbp->ucd_rsp_ptr->sr.sense_data,
7a3e97b0
SY		 800 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
801 }
802}
803
68078d5c
DR		 804/**
805 * ufshcd_copy_query_response() - Copy the Query Response and the data
806 * descriptor
807 * @hba: per adapter instance
808 * @lrb - pointer to local reference block
809 */
810static
c6d4a831 811int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 812{
813 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
814
68078d5c 815 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 816
68078d5c
DR		 817 /* Get the descriptor */
818 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 819 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 820 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 821 u16 resp_len;
822 u16 buf_len;
68078d5c
DR		 823
824 /* data segment length */
c6d4a831 825 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 826 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 827 buf_len = be16_to_cpu(
828 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 829 if (likely(buf_len >= resp_len)) {
830 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
831 } else {
832 dev_warn(hba->dev,
833 "%s: Response size is bigger than buffer",
834 __func__);
835 return -EINVAL;
836 }
68078d5c 837 }
c6d4a831
DR		 838
839 return 0;
68078d5c
DR		 840}
841
7a3e97b0
SY		 842/**
843 * ufshcd_hba_capabilities - Read controller capabilities
844 * @hba: per adapter instance
845 */
846static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
847{
b873a275 848 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 849
850 /* nutrs and nutmrs are 0 based values */
851 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
852 hba->nutmrs =
853 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
854}
855
856/**
6ccf44fe
SJ		 857 * ufshcd_ready_for_uic_cmd - Check if controller is ready
858 * to accept UIC commands
7a3e97b0 859 * @hba: per adapter instance
6ccf44fe
SJ		 860 * Return true on success, else false
861 */
862static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
863{
864 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
865 return true;
866 else
867 return false;
868}
869
53b3d9c3
SJ		 870/**
871 * ufshcd_get_upmcrs - Get the power mode change request status
872 * @hba: Pointer to adapter instance
873 *
874 * This function gets the UPMCRS field of HCS register
875 * Returns value of UPMCRS field
876 */
877static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
878{
879 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
880}
881
6ccf44fe
SJ		 882/**
883 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
884 * @hba: per adapter instance
885 * @uic_cmd: UIC command
886 *
887 * Mutex must be held.
7a3e97b0
SY		 888 */
889static inline void
6ccf44fe 890ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 891{
6ccf44fe
SJ		 892 WARN_ON(hba->active_uic_cmd);
893
894 hba->active_uic_cmd = uic_cmd;
895
7a3e97b0 896 /* Write Args */
6ccf44fe
SJ		 897 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
898 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
899 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 900
901 /* Write UIC Cmd */
6ccf44fe 902 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 903 REG_UIC_COMMAND);
7a3e97b0
SY		 904}
905
6ccf44fe
SJ		 906/**
907 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
908 * @hba: per adapter instance
909 * @uic_command: UIC command
910 *
911 * Must be called with mutex held.
912 * Returns 0 only if success.
913 */
914static int
915ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
916{
917 int ret;
918 unsigned long flags;
919
920 if (wait_for_completion_timeout(&uic_cmd->done,
921 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
922 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
923 else
924 ret = -ETIMEDOUT;
925
926 spin_lock_irqsave(hba->host->host_lock, flags);
927 hba->active_uic_cmd = NULL;
928 spin_unlock_irqrestore(hba->host->host_lock, flags);
929
930 return ret;
931}
932
933/**
934 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
935 * @hba: per adapter instance
936 * @uic_cmd: UIC command
937 *
938 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 939 * with mutex held and host_lock locked.
6ccf44fe
SJ		 940 * Returns 0 only if success.
941 */
942static int
943__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
944{
6ccf44fe
SJ		 945 if (!ufshcd_ready_for_uic_cmd(hba)) {
946 dev_err(hba->dev,
947 "Controller not ready to accept UIC commands\n");
948 return -EIO;
949 }
950
951 init_completion(&uic_cmd->done);
952
6ccf44fe 953 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 954
57d104c1 955 return 0;
6ccf44fe
SJ		 956}
957
958/**
959 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
960 * @hba: per adapter instance
961 * @uic_cmd: UIC command
962 *
963 * Returns 0 only if success.
964 */
965static int
966ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
967{
968 int ret;
57d104c1 969 unsigned long flags;
6ccf44fe 970
1ab27c9c 971 ufshcd_hold(hba, false);
6ccf44fe 972 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 973 spin_lock_irqsave(hba->host->host_lock, flags);
6ccf44fe 974 ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
57d104c1
SJ		 975 spin_unlock_irqrestore(hba->host->host_lock, flags);
976 if (!ret)
977 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
978
6ccf44fe
SJ		 979 mutex_unlock(&hba->uic_cmd_mutex);
980
1ab27c9c 981 ufshcd_release(hba);
6ccf44fe
SJ		 982 return ret;
983}
984
7a3e97b0
SY		 985/**
986 * ufshcd_map_sg - Map scatter-gather list to prdt
987 * @lrbp - pointer to local reference block
988 *
989 * Returns 0 in case of success, non-zero value in case of failure
990 */
991static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
992{
993 struct ufshcd_sg_entry *prd_table;
994 struct scatterlist *sg;
995 struct scsi_cmnd *cmd;
996 int sg_segments;
997 int i;
998
999 cmd = lrbp->cmd;
1000 sg_segments = scsi_dma_map(cmd);
1001 if (sg_segments < 0)
1002 return sg_segments;
1003
1004 if (sg_segments) {
1005 lrbp->utr_descriptor_ptr->prd_table_length =
1006 cpu_to_le16((u16) (sg_segments));
1007
1008 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1009
1010 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1011 prd_table[i].size =
1012 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1013 prd_table[i].base_addr =
1014 cpu_to_le32(lower_32_bits(sg->dma_address));
1015 prd_table[i].upper_addr =
1016 cpu_to_le32(upper_32_bits(sg->dma_address));
1017 }
1018 } else {
1019 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1020 }
1021
1022 return 0;
1023}
1024
1025/**
2fbd009b 1026 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1027 * @hba: per adapter instance
2fbd009b 1028 * @intrs: interrupt bits
7a3e97b0 1029 */
2fbd009b 1030static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1031{
2fbd009b
SJ		 1032 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1033
1034 if (hba->ufs_version == UFSHCI_VERSION_10) {
1035 u32 rw;
1036 rw = set & INTERRUPT_MASK_RW_VER_10;
1037 set = rw | ((set ^ intrs) & intrs);
1038 } else {
1039 set |= intrs;
1040 }
1041
1042 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1043}
1044
1045/**
1046 * ufshcd_disable_intr - disable interrupts
1047 * @hba: per adapter instance
1048 * @intrs: interrupt bits
1049 */
1050static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1051{
1052 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1053
1054 if (hba->ufs_version == UFSHCI_VERSION_10) {
1055 u32 rw;
1056 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1057 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1058 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1059
1060 } else {
1061 set &= ~intrs;
7a3e97b0 1062 }
2fbd009b
SJ		 1063
1064 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1065}
1066
5a0b0cb9
SRT		 1067/**
1068 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1069 * descriptor according to request
1070 * @lrbp: pointer to local reference block
1071 * @upiu_flags: flags required in the header
1072 * @cmd_dir: requests data direction
1073 */
1074static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
1075 u32 *upiu_flags, enum dma_data_direction cmd_dir)
1076{
1077 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1078 u32 data_direction;
1079 u32 dword_0;
1080
1081 if (cmd_dir == DMA_FROM_DEVICE) {
1082 data_direction = UTP_DEVICE_TO_HOST;
1083 *upiu_flags = UPIU_CMD_FLAGS_READ;
1084 } else if (cmd_dir == DMA_TO_DEVICE) {
1085 data_direction = UTP_HOST_TO_DEVICE;
1086 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1087 } else {
1088 data_direction = UTP_NO_DATA_TRANSFER;
1089 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1090 }
1091
1092 dword_0 = data_direction | (lrbp->command_type
1093 << UPIU_COMMAND_TYPE_OFFSET);
1094 if (lrbp->intr_cmd)
1095 dword_0 |= UTP_REQ_DESC_INT_CMD;
1096
1097 /* Transfer request descriptor header fields */
1098 req_desc->header.dword_0 = cpu_to_le32(dword_0);
1099
1100 /*
1101 * assigning invalid value for command status. Controller
1102 * updates OCS on command completion, with the command
1103 * status
1104 */
1105 req_desc->header.dword_2 =
1106 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
1107}
1108
1109/**
1110 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1111 * for scsi commands
1112 * @lrbp - local reference block pointer
1113 * @upiu_flags - flags
1114 */
1115static
1116void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1117{
1118 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1119
1120 /* command descriptor fields */
1121 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1122 UPIU_TRANSACTION_COMMAND, upiu_flags,
1123 lrbp->lun, lrbp->task_tag);
1124 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1125 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1126
1127 /* Total EHS length and Data segment length will be zero */
1128 ucd_req_ptr->header.dword_2 = 0;
1129
1130 ucd_req_ptr->sc.exp_data_transfer_len =
1131 cpu_to_be32(lrbp->cmd->sdb.length);
1132
1133 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
1134 (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
1135}
1136
68078d5c
DR		 1137/**
1138 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1139 * for query requsts
1140 * @hba: UFS hba
1141 * @lrbp: local reference block pointer
1142 * @upiu_flags: flags
1143 */
1144static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1145 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1146{
1147 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1148 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1149 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1150 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1151
1152 /* Query request header */
1153 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1154 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1155 lrbp->lun, lrbp->task_tag);
1156 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1157 0, query->request.query_func, 0, 0);
1158
1159 /* Data segment length */
1160 ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
1161 0, 0, len >> 8, (u8)len);
1162
1163 /* Copy the Query Request buffer as is */
1164 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1165 QUERY_OSF_SIZE);
68078d5c
DR		 1166
1167 /* Copy the Descriptor */
c6d4a831
DR		 1168 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1169 memcpy(descp, query->descriptor, len);
1170
68078d5c
DR		 1171}
1172
5a0b0cb9
SRT		 1173static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1174{
1175 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1176
1177 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1178
1179 /* command descriptor fields */
1180 ucd_req_ptr->header.dword_0 =
1181 UPIU_HEADER_DWORD(
1182 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
1183}
1184
7a3e97b0
SY		 1185/**
1186 * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
5a0b0cb9 1187 * @hba - per adapter instance
7a3e97b0
SY		 1188 * @lrb - pointer to local reference block
1189 */
5a0b0cb9 1190static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1191{
7a3e97b0 1192 u32 upiu_flags;
5a0b0cb9 1193 int ret = 0;
7a3e97b0
SY		 1194
1195 switch (lrbp->command_type) {
1196 case UTP_CMD_TYPE_SCSI:
5a0b0cb9
SRT		 1197 if (likely(lrbp->cmd)) {
1198 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1199 lrbp->cmd->sc_data_direction);
1200 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
7a3e97b0 1201 } else {
5a0b0cb9 1202 ret = -EINVAL;
7a3e97b0 1203 }
7a3e97b0
SY		 1204 break;
1205 case UTP_CMD_TYPE_DEV_MANAGE:
5a0b0cb9 1206 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
68078d5c
DR		 1207 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1208 ufshcd_prepare_utp_query_req_upiu(
1209 hba, lrbp, upiu_flags);
1210 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
5a0b0cb9
SRT		 1211 ufshcd_prepare_utp_nop_upiu(lrbp);
1212 else
1213 ret = -EINVAL;
7a3e97b0
SY		 1214 break;
1215 case UTP_CMD_TYPE_UFS:
1216 /* For UFS native command implementation */
5a0b0cb9
SRT		 1217 ret = -ENOTSUPP;
1218 dev_err(hba->dev, "%s: UFS native command are not supported\n",
1219 __func__);
1220 break;
1221 default:
1222 ret = -ENOTSUPP;
1223 dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
1224 __func__, lrbp->command_type);
7a3e97b0
SY		 1225 break;
1226 } /* end of switch */
5a0b0cb9
SRT		 1227
1228 return ret;
7a3e97b0
SY		 1229}
1230
0ce147d4
SJ		 1231/*
1232 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1233 * @scsi_lun: scsi LUN id
1234 *
1235 * Returns UPIU LUN id
1236 */
1237static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1238{
1239 if (scsi_is_wlun(scsi_lun))
1240 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1241 | UFS_UPIU_WLUN_ID;
1242 else
1243 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1244}
1245
2a8fa600
SJ		 1246/**
1247 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1248 * @scsi_lun: UPIU W-LUN id
1249 *
1250 * Returns SCSI W-LUN id
1251 */
1252static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1253{
1254 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1255}
1256
7a3e97b0
SY		 1257/**
1258 * ufshcd_queuecommand - main entry point for SCSI requests
1259 * @cmd: command from SCSI Midlayer
1260 * @done: call back function
1261 *
1262 * Returns 0 for success, non-zero in case of failure
1263 */
1264static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1265{
1266 struct ufshcd_lrb *lrbp;
1267 struct ufs_hba *hba;
1268 unsigned long flags;
1269 int tag;
1270 int err = 0;
1271
1272 hba = shost_priv(host);
1273
1274 tag = cmd->request->tag;
1275
3441da7d
SRT		 1276 spin_lock_irqsave(hba->host->host_lock, flags);
1277 switch (hba->ufshcd_state) {
1278 case UFSHCD_STATE_OPERATIONAL:
1279 break;
1280 case UFSHCD_STATE_RESET:
7a3e97b0 1281 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1282 goto out_unlock;
1283 case UFSHCD_STATE_ERROR:
1284 set_host_byte(cmd, DID_ERROR);
1285 cmd->scsi_done(cmd);
1286 goto out_unlock;
1287 default:
1288 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1289 __func__, hba->ufshcd_state);
1290 set_host_byte(cmd, DID_BAD_TARGET);
1291 cmd->scsi_done(cmd);
1292 goto out_unlock;
7a3e97b0 1293 }
3441da7d 1294 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1295
5a0b0cb9
SRT		 1296 /* acquire the tag to make sure device cmds don't use it */
1297 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1298 /*
1299 * Dev manage command in progress, requeue the command.
1300 * Requeuing the command helps in cases where the request *may*
1301 * find different tag instead of waiting for dev manage command
1302 * completion.
1303 */
1304 err = SCSI_MLQUEUE_HOST_BUSY;
1305 goto out;
1306 }
1307
1ab27c9c
ST		 1308 err = ufshcd_hold(hba, true);
1309 if (err) {
1310 err = SCSI_MLQUEUE_HOST_BUSY;
1311 clear_bit_unlock(tag, &hba->lrb_in_use);
1312 goto out;
1313 }
1314 WARN_ON(hba->clk_gating.state != CLKS_ON);
1315
7a3e97b0
SY		 1316 lrbp = &hba->lrb[tag];
1317
5a0b0cb9 1318 WARN_ON(lrbp->cmd);
7a3e97b0
SY		 1319 lrbp->cmd = cmd;
1320 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
1321 lrbp->sense_buffer = cmd->sense_buffer;
1322 lrbp->task_tag = tag;
0ce147d4 1323 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
5a0b0cb9 1324 lrbp->intr_cmd = false;
7a3e97b0
SY		 1325 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1326
1327 /* form UPIU before issuing the command */
5a0b0cb9 1328 ufshcd_compose_upiu(hba, lrbp);
7a3e97b0 1329 err = ufshcd_map_sg(lrbp);
5a0b0cb9
SRT		 1330 if (err) {
1331 lrbp->cmd = NULL;
1332 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1333 goto out;
5a0b0cb9 1334 }
7a3e97b0
SY		 1335
1336 /* issue command to the controller */
1337 spin_lock_irqsave(hba->host->host_lock, flags);
1338 ufshcd_send_command(hba, tag);
3441da7d 1339out_unlock:
7a3e97b0
SY		 1340 spin_unlock_irqrestore(hba->host->host_lock, flags);
1341out:
1342 return err;
1343}
1344
5a0b0cb9
SRT		 1345static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1346 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1347{
1348 lrbp->cmd = NULL;
1349 lrbp->sense_bufflen = 0;
1350 lrbp->sense_buffer = NULL;
1351 lrbp->task_tag = tag;
1352 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
1353 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1354 lrbp->intr_cmd = true; /* No interrupt aggregation */
1355 hba->dev_cmd.type = cmd_type;
1356
1357 return ufshcd_compose_upiu(hba, lrbp);
1358}
1359
1360static int
1361ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1362{
1363 int err = 0;
1364 unsigned long flags;
1365 u32 mask = 1 << tag;
1366
1367 /* clear outstanding transaction before retry */
1368 spin_lock_irqsave(hba->host->host_lock, flags);
1369 ufshcd_utrl_clear(hba, tag);
1370 spin_unlock_irqrestore(hba->host->host_lock, flags);
1371
1372 /*
1373 * wait for for h/w to clear corresponding bit in door-bell.
1374 * max. wait is 1 sec.
1375 */
1376 err = ufshcd_wait_for_register(hba,
1377 REG_UTP_TRANSFER_REQ_DOOR_BELL,
1378 mask, ~mask, 1000, 1000);
1379
1380 return err;
1381}
1382
c6d4a831
DR		 1383static int
1384ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1385{
1386 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1387
1388 /* Get the UPIU response */
1389 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1390 UPIU_RSP_CODE_OFFSET;
1391 return query_res->response;
1392}
1393
5a0b0cb9
SRT		 1394/**
1395 * ufshcd_dev_cmd_completion() - handles device management command responses
1396 * @hba: per adapter instance
1397 * @lrbp: pointer to local reference block
1398 */
1399static int
1400ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1401{
1402 int resp;
1403 int err = 0;
1404
1405 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1406
1407 switch (resp) {
1408 case UPIU_TRANSACTION_NOP_IN:
1409 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1410 err = -EINVAL;
1411 dev_err(hba->dev, "%s: unexpected response %x\n",
1412 __func__, resp);
1413 }
1414 break;
68078d5c 1415 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1416 err = ufshcd_check_query_response(hba, lrbp);
1417 if (!err)
1418 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1419 break;
5a0b0cb9
SRT		 1420 case UPIU_TRANSACTION_REJECT_UPIU:
1421 /* TODO: handle Reject UPIU Response */
1422 err = -EPERM;
1423 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1424 __func__);
1425 break;
1426 default:
1427 err = -EINVAL;
1428 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1429 __func__, resp);
1430 break;
1431 }
1432
1433 return err;
1434}
1435
1436static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1437 struct ufshcd_lrb *lrbp, int max_timeout)
1438{
1439 int err = 0;
1440 unsigned long time_left;
1441 unsigned long flags;
1442
1443 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1444 msecs_to_jiffies(max_timeout));
1445
1446 spin_lock_irqsave(hba->host->host_lock, flags);
1447 hba->dev_cmd.complete = NULL;
1448 if (likely(time_left)) {
1449 err = ufshcd_get_tr_ocs(lrbp);
1450 if (!err)
1451 err = ufshcd_dev_cmd_completion(hba, lrbp);
1452 }
1453 spin_unlock_irqrestore(hba->host->host_lock, flags);
1454
1455 if (!time_left) {
1456 err = -ETIMEDOUT;
1457 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
1458 /* sucessfully cleared the command, retry if needed */
1459 err = -EAGAIN;
1460 }
1461
1462 return err;
1463}
1464
1465/**
1466 * ufshcd_get_dev_cmd_tag - Get device management command tag
1467 * @hba: per-adapter instance
1468 * @tag: pointer to variable with available slot value
1469 *
1470 * Get a free slot and lock it until device management command
1471 * completes.
1472 *
1473 * Returns false if free slot is unavailable for locking, else
1474 * return true with tag value in @tag.
1475 */
1476static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1477{
1478 int tag;
1479 bool ret = false;
1480 unsigned long tmp;
1481
1482 if (!tag_out)
1483 goto out;
1484
1485 do {
1486 tmp = ~hba->lrb_in_use;
1487 tag = find_last_bit(&tmp, hba->nutrs);
1488 if (tag >= hba->nutrs)
1489 goto out;
1490 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1491
1492 *tag_out = tag;
1493 ret = true;
1494out:
1495 return ret;
1496}
1497
1498static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1499{
1500 clear_bit_unlock(tag, &hba->lrb_in_use);
1501}
1502
1503/**
1504 * ufshcd_exec_dev_cmd - API for sending device management requests
1505 * @hba - UFS hba
1506 * @cmd_type - specifies the type (NOP, Query...)
1507 * @timeout - time in seconds
1508 *
68078d5c
DR		 1509 * NOTE: Since there is only one available tag for device management commands,
1510 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1511 */
1512static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1513 enum dev_cmd_type cmd_type, int timeout)
1514{
1515 struct ufshcd_lrb *lrbp;
1516 int err;
1517 int tag;
1518 struct completion wait;
1519 unsigned long flags;
1520
1521 /*
1522 * Get free slot, sleep if slots are unavailable.
1523 * Even though we use wait_event() which sleeps indefinitely,
1524 * the maximum wait time is bounded by SCSI request timeout.
1525 */
1526 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1527
1528 init_completion(&wait);
1529 lrbp = &hba->lrb[tag];
1530 WARN_ON(lrbp->cmd);
1531 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1532 if (unlikely(err))
1533 goto out_put_tag;
1534
1535 hba->dev_cmd.complete = &wait;
1536
1537 spin_lock_irqsave(hba->host->host_lock, flags);
1538 ufshcd_send_command(hba, tag);
1539 spin_unlock_irqrestore(hba->host->host_lock, flags);
1540
1541 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1542
1543out_put_tag:
1544 ufshcd_put_dev_cmd_tag(hba, tag);
1545 wake_up(&hba->dev_cmd.tag_wq);
1546 return err;
1547}
1548
d44a5f98
DR		 1549/**
1550 * ufshcd_init_query() - init the query response and request parameters
1551 * @hba: per-adapter instance
1552 * @request: address of the request pointer to be initialized
1553 * @response: address of the response pointer to be initialized
1554 * @opcode: operation to perform
1555 * @idn: flag idn to access
1556 * @index: LU number to access
1557 * @selector: query/flag/descriptor further identification
1558 */
1559static inline void ufshcd_init_query(struct ufs_hba *hba,
1560 struct ufs_query_req **request, struct ufs_query_res **response,
1561 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1562{
1563 *request = &hba->dev_cmd.query.request;
1564 *response = &hba->dev_cmd.query.response;
1565 memset(*request, 0, sizeof(struct ufs_query_req));
1566 memset(*response, 0, sizeof(struct ufs_query_res));
1567 (*request)->upiu_req.opcode = opcode;
1568 (*request)->upiu_req.idn = idn;
1569 (*request)->upiu_req.index = index;
1570 (*request)->upiu_req.selector = selector;
1571}
1572
68078d5c
DR		 1573/**
1574 * ufshcd_query_flag() - API function for sending flag query requests
1575 * hba: per-adapter instance
1576 * query_opcode: flag query to perform
1577 * idn: flag idn to access
1578 * flag_res: the flag value after the query request completes
1579 *
1580 * Returns 0 for success, non-zero in case of failure
1581 */
1582static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1583 enum flag_idn idn, bool *flag_res)
1584{
d44a5f98
DR		 1585 struct ufs_query_req *request = NULL;
1586 struct ufs_query_res *response = NULL;
1587 int err, index = 0, selector = 0;
68078d5c
DR		 1588
1589 BUG_ON(!hba);
1590
1ab27c9c 1591 ufshcd_hold(hba, false);
68078d5c 1592 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1593 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1594 selector);
68078d5c
DR		 1595
1596 switch (opcode) {
1597 case UPIU_QUERY_OPCODE_SET_FLAG:
1598 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1599 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1600 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1601 break;
1602 case UPIU_QUERY_OPCODE_READ_FLAG:
1603 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1604 if (!flag_res) {
1605 /* No dummy reads */
1606 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1607 __func__);
1608 err = -EINVAL;
1609 goto out_unlock;
1610 }
1611 break;
1612 default:
1613 dev_err(hba->dev,
1614 "%s: Expected query flag opcode but got = %d\n",
1615 __func__, opcode);
1616 err = -EINVAL;
1617 goto out_unlock;
1618 }
68078d5c 1619
d44a5f98 1620 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
68078d5c
DR		 1621
1622 if (err) {
1623 dev_err(hba->dev,
1624 "%s: Sending flag query for idn %d failed, err = %d\n",
1625 __func__, idn, err);
1626 goto out_unlock;
1627 }
1628
1629 if (flag_res)
e8c8e82a 1630 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1631 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1632
1633out_unlock:
1634 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1635 ufshcd_release(hba);
68078d5c
DR		 1636 return err;
1637}
1638
66ec6d59
SRT		 1639/**
1640 * ufshcd_query_attr - API function for sending attribute requests
1641 * hba: per-adapter instance
1642 * opcode: attribute opcode
1643 * idn: attribute idn to access
1644 * index: index field
1645 * selector: selector field
1646 * attr_val: the attribute value after the query request completes
1647 *
1648 * Returns 0 for success, non-zero in case of failure
1649*/
bdbe5d2f 1650static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1651 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1652{
d44a5f98
DR		 1653 struct ufs_query_req *request = NULL;
1654 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1655 int err;
1656
1657 BUG_ON(!hba);
1658
1ab27c9c 1659 ufshcd_hold(hba, false);
66ec6d59
SRT		 1660 if (!attr_val) {
1661 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1662 __func__, opcode);
1663 err = -EINVAL;
1664 goto out;
1665 }
1666
1667 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1668 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1669 selector);
66ec6d59
SRT		 1670
1671 switch (opcode) {
1672 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1673 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1674 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1675 break;
1676 case UPIU_QUERY_OPCODE_READ_ATTR:
1677 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1678 break;
1679 default:
1680 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1681 __func__, opcode);
1682 err = -EINVAL;
1683 goto out_unlock;
1684 }
1685
d44a5f98 1686 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1687
1688 if (err) {
1689 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1690 __func__, opcode, idn, err);
1691 goto out_unlock;
1692 }
1693
e8c8e82a 1694 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1695
1696out_unlock:
1697 mutex_unlock(&hba->dev_cmd.lock);
1698out:
1ab27c9c 1699 ufshcd_release(hba);
66ec6d59
SRT		 1700 return err;
1701}
1702
d44a5f98
DR		 1703/**
1704 * ufshcd_query_descriptor - API function for sending descriptor requests
1705 * hba: per-adapter instance
1706 * opcode: attribute opcode
1707 * idn: attribute idn to access
1708 * index: index field
1709 * selector: selector field
1710 * desc_buf: the buffer that contains the descriptor
1711 * buf_len: length parameter passed to the device
1712 *
1713 * Returns 0 for success, non-zero in case of failure.
1714 * The buf_len parameter will contain, on return, the length parameter
1715 * received on the response.
1716 */
7289f983 1717static int ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1718 enum query_opcode opcode, enum desc_idn idn, u8 index,
1719 u8 selector, u8 *desc_buf, int *buf_len)
1720{
1721 struct ufs_query_req *request = NULL;
1722 struct ufs_query_res *response = NULL;
1723 int err;
1724
1725 BUG_ON(!hba);
1726
1ab27c9c 1727 ufshcd_hold(hba, false);
d44a5f98
DR		 1728 if (!desc_buf) {
1729 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1730 __func__, opcode);
1731 err = -EINVAL;
1732 goto out;
1733 }
1734
1735 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1736 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1737 __func__, *buf_len);
1738 err = -EINVAL;
1739 goto out;
1740 }
1741
1742 mutex_lock(&hba->dev_cmd.lock);
1743 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1744 selector);
1745 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1746 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1747
1748 switch (opcode) {
1749 case UPIU_QUERY_OPCODE_WRITE_DESC:
1750 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1751 break;
1752 case UPIU_QUERY_OPCODE_READ_DESC:
1753 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1754 break;
1755 default:
1756 dev_err(hba->dev,
1757 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1758 __func__, opcode);
1759 err = -EINVAL;
1760 goto out_unlock;
1761 }
1762
1763 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1764
1765 if (err) {
1766 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1767 __func__, opcode, idn, err);
1768 goto out_unlock;
1769 }
1770
1771 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 1772 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 1773
1774out_unlock:
1775 mutex_unlock(&hba->dev_cmd.lock);
1776out:
1ab27c9c 1777 ufshcd_release(hba);
d44a5f98
DR		 1778 return err;
1779}
1780
da461cec
SJ		 1781/**
1782 * ufshcd_read_desc_param - read the specified descriptor parameter
1783 * @hba: Pointer to adapter instance
1784 * @desc_id: descriptor idn value
1785 * @desc_index: descriptor index
1786 * @param_offset: offset of the parameter to read
1787 * @param_read_buf: pointer to buffer where parameter would be read
1788 * @param_size: sizeof(param_read_buf)
1789 *
1790 * Return 0 in case of success, non-zero otherwise
1791 */
1792static int ufshcd_read_desc_param(struct ufs_hba *hba,
1793 enum desc_idn desc_id,
1794 int desc_index,
1795 u32 param_offset,
1796 u8 *param_read_buf,
1797 u32 param_size)
1798{
1799 int ret;
1800 u8 *desc_buf;
1801 u32 buff_len;
1802 bool is_kmalloc = true;
1803
1804 /* safety checks */
1805 if (desc_id >= QUERY_DESC_IDN_MAX)
1806 return -EINVAL;
1807
1808 buff_len = ufs_query_desc_max_size[desc_id];
1809 if ((param_offset + param_size) > buff_len)
1810 return -EINVAL;
1811
1812 if (!param_offset && (param_size == buff_len)) {
1813 /* memory space already available to hold full descriptor */
1814 desc_buf = param_read_buf;
1815 is_kmalloc = false;
1816 } else {
1817 /* allocate memory to hold full descriptor */
1818 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1819 if (!desc_buf)
1820 return -ENOMEM;
1821 }
1822
1823 ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC,
1824 desc_id, desc_index, 0, desc_buf,
1825 &buff_len);
1826
1827 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
1828 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
1829 ufs_query_desc_max_size[desc_id])
1830 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
1831 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
1832 __func__, desc_id, param_offset, buff_len, ret);
1833 if (!ret)
1834 ret = -EINVAL;
1835
1836 goto out;
1837 }
1838
1839 if (is_kmalloc)
1840 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1841out:
1842 if (is_kmalloc)
1843 kfree(desc_buf);
1844 return ret;
1845}
1846
1847static inline int ufshcd_read_desc(struct ufs_hba *hba,
1848 enum desc_idn desc_id,
1849 int desc_index,
1850 u8 *buf,
1851 u32 size)
1852{
1853 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1854}
1855
1856static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
1857 u8 *buf,
1858 u32 size)
1859{
1860 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
1861}
1862
1863/**
1864 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
1865 * @hba: Pointer to adapter instance
1866 * @lun: lun id
1867 * @param_offset: offset of the parameter to read
1868 * @param_read_buf: pointer to buffer where parameter would be read
1869 * @param_size: sizeof(param_read_buf)
1870 *
1871 * Return 0 in case of success, non-zero otherwise
1872 */
1873static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
1874 int lun,
1875 enum unit_desc_param param_offset,
1876 u8 *param_read_buf,
1877 u32 param_size)
1878{
1879 /*
1880 * Unit descriptors are only available for general purpose LUs (LUN id
1881 * from 0 to 7) and RPMB Well known LU.
1882 */
0ce147d4 1883 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 1884 return -EOPNOTSUPP;
1885
1886 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
1887 param_offset, param_read_buf, param_size);
1888}
1889
7a3e97b0
SY		 1890/**
1891 * ufshcd_memory_alloc - allocate memory for host memory space data structures
1892 * @hba: per adapter instance
1893 *
1894 * 1. Allocate DMA memory for Command Descriptor array
1895 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
1896 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
1897 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
1898 * (UTMRDL)
1899 * 4. Allocate memory for local reference block(lrb).
1900 *
1901 * Returns 0 for success, non-zero in case of failure
1902 */
1903static int ufshcd_memory_alloc(struct ufs_hba *hba)
1904{
1905 size_t utmrdl_size, utrdl_size, ucdl_size;
1906
1907 /* Allocate memory for UTP command descriptors */
1908 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 1909 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
1910 ucdl_size,
1911 &hba->ucdl_dma_addr,
1912 GFP_KERNEL);
7a3e97b0
SY		 1913
1914 /*
1915 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
1916 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
1917 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
1918 * be aligned to 128 bytes as well
1919 */
1920 if (!hba->ucdl_base_addr ||
1921 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1922 dev_err(hba->dev,
7a3e97b0
SY		 1923 "Command Descriptor Memory allocation failed\n");
1924 goto out;
1925 }
1926
1927 /*
1928 * Allocate memory for UTP Transfer descriptors
1929 * UFSHCI requires 1024 byte alignment of UTRD
1930 */
1931 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 1932 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
1933 utrdl_size,
1934 &hba->utrdl_dma_addr,
1935 GFP_KERNEL);
7a3e97b0
SY		 1936 if (!hba->utrdl_base_addr ||
1937 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1938 dev_err(hba->dev,
7a3e97b0
SY		 1939 "Transfer Descriptor Memory allocation failed\n");
1940 goto out;
1941 }
1942
1943 /*
1944 * Allocate memory for UTP Task Management descriptors
1945 * UFSHCI requires 1024 byte alignment of UTMRD
1946 */
1947 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 1948 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
1949 utmrdl_size,
1950 &hba->utmrdl_dma_addr,
1951 GFP_KERNEL);
7a3e97b0
SY		 1952 if (!hba->utmrdl_base_addr ||
1953 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1954 dev_err(hba->dev,
7a3e97b0
SY		 1955 "Task Management Descriptor Memory allocation failed\n");
1956 goto out;
1957 }
1958
1959 /* Allocate memory for local reference block */
2953f850
SJ		 1960 hba->lrb = devm_kzalloc(hba->dev,
1961 hba->nutrs * sizeof(struct ufshcd_lrb),
1962 GFP_KERNEL);
7a3e97b0 1963 if (!hba->lrb) {
3b1d0580 1964 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 1965 goto out;
1966 }
1967 return 0;
1968out:
7a3e97b0
SY		 1969 return -ENOMEM;
1970}
1971
1972/**
1973 * ufshcd_host_memory_configure - configure local reference block with
1974 * memory offsets
1975 * @hba: per adapter instance
1976 *
1977 * Configure Host memory space
1978 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
1979 * address.
1980 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
1981 * and PRDT offset.
1982 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
1983 * into local reference block.
1984 */
1985static void ufshcd_host_memory_configure(struct ufs_hba *hba)
1986{
1987 struct utp_transfer_cmd_desc *cmd_descp;
1988 struct utp_transfer_req_desc *utrdlp;
1989 dma_addr_t cmd_desc_dma_addr;
1990 dma_addr_t cmd_desc_element_addr;
1991 u16 response_offset;
1992 u16 prdt_offset;
1993 int cmd_desc_size;
1994 int i;
1995
1996 utrdlp = hba->utrdl_base_addr;
1997 cmd_descp = hba->ucdl_base_addr;
1998
1999 response_offset =
2000 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2001 prdt_offset =
2002 offsetof(struct utp_transfer_cmd_desc, prd_table);
2003
2004 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2005 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2006
2007 for (i = 0; i < hba->nutrs; i++) {
2008 /* Configure UTRD with command descriptor base address */
2009 cmd_desc_element_addr =
2010 (cmd_desc_dma_addr + (cmd_desc_size * i));
2011 utrdlp[i].command_desc_base_addr_lo =
2012 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2013 utrdlp[i].command_desc_base_addr_hi =
2014 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2015
2016 /* Response upiu and prdt offset should be in double words */
2017 utrdlp[i].response_upiu_offset =
2018 cpu_to_le16((response_offset >> 2));
2019 utrdlp[i].prd_table_offset =
2020 cpu_to_le16((prdt_offset >> 2));
2021 utrdlp[i].response_upiu_length =
3ca316c5 2022 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0
SY		 2023
2024 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2025 hba->lrb[i].ucd_req_ptr =
2026 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2027 hba->lrb[i].ucd_rsp_ptr =
2028 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2029 hba->lrb[i].ucd_prdt_ptr =
2030 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2031 }
2032}
2033
2034/**
2035 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2036 * @hba: per adapter instance
2037 *
2038 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2039 * in order to initialize the Unipro link startup procedure.
2040 * Once the Unipro links are up, the device connected to the controller
2041 * is detected.
2042 *
2043 * Returns 0 on success, non-zero value on failure
2044 */
2045static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2046{
6ccf44fe
SJ		 2047 struct uic_command uic_cmd = {0};
2048 int ret;
7a3e97b0 2049
6ccf44fe 2050 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2051
6ccf44fe
SJ		 2052 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2053 if (ret)
2054 dev_err(hba->dev,
2055 "dme-link-startup: error code %d\n", ret);
2056 return ret;
7a3e97b0
SY		 2057}
2058
12b4fdb4
SJ		 2059/**
2060 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2061 * @hba: per adapter instance
2062 * @attr_sel: uic command argument1
2063 * @attr_set: attribute set type as uic command argument2
2064 * @mib_val: setting value as uic command argument3
2065 * @peer: indicate whether peer or local
2066 *
2067 * Returns 0 on success, non-zero value on failure
2068 */
2069int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2070 u8 attr_set, u32 mib_val, u8 peer)
2071{
2072 struct uic_command uic_cmd = {0};
2073 static const char *const action[] = {
2074 "dme-set",
2075 "dme-peer-set"
2076 };
2077 const char *set = action[!!peer];
2078 int ret;
2079
2080 uic_cmd.command = peer ?
2081 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2082 uic_cmd.argument1 = attr_sel;
2083 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2084 uic_cmd.argument3 = mib_val;
2085
2086 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2087 if (ret)
2088 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2089 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2090
2091 return ret;
2092}
2093EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2094
2095/**
2096 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2097 * @hba: per adapter instance
2098 * @attr_sel: uic command argument1
2099 * @mib_val: the value of the attribute as returned by the UIC command
2100 * @peer: indicate whether peer or local
2101 *
2102 * Returns 0 on success, non-zero value on failure
2103 */
2104int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2105 u32 *mib_val, u8 peer)
2106{
2107 struct uic_command uic_cmd = {0};
2108 static const char *const action[] = {
2109 "dme-get",
2110 "dme-peer-get"
2111 };
2112 const char *get = action[!!peer];
2113 int ret;
2114
2115 uic_cmd.command = peer ?
2116 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2117 uic_cmd.argument1 = attr_sel;
2118
2119 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2120 if (ret) {
2121 dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
2122 get, UIC_GET_ATTR_ID(attr_sel), ret);
2123 goto out;
2124 }
2125
2126 if (mib_val)
2127 *mib_val = uic_cmd.argument3;
2128out:
2129 return ret;
2130}
2131EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2132
53b3d9c3 2133/**
57d104c1
SJ		 2134 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2135 * state) and waits for it to take effect.
2136 *
53b3d9c3 2137 * @hba: per adapter instance
57d104c1
SJ		 2138 * @cmd: UIC command to execute
2139 *
2140 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2141 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2142 * and device UniPro link and hence it's final completion would be indicated by
2143 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2144 * addition to normal UIC command completion Status (UCCS). This function only
2145 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2146 *
2147 * Returns 0 on success, non-zero value on failure
2148 */
57d104c1 2149static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2150{
57d104c1 2151 struct completion uic_async_done;
53b3d9c3
SJ		 2152 unsigned long flags;
2153 u8 status;
2154 int ret;
2155
53b3d9c3 2156 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2157 init_completion(&uic_async_done);
53b3d9c3
SJ		 2158
2159 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1
SJ		 2160 hba->uic_async_done = &uic_async_done;
2161 ret = __ufshcd_send_uic_cmd(hba, cmd);
53b3d9c3 2162 spin_unlock_irqrestore(hba->host->host_lock, flags);
53b3d9c3
SJ		 2163 if (ret) {
2164 dev_err(hba->dev,
57d104c1
SJ		 2165 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2166 cmd->command, cmd->argument3, ret);
2167 goto out;
2168 }
2169 ret = ufshcd_wait_for_uic_cmd(hba, cmd);
2170 if (ret) {
2171 dev_err(hba->dev,
2172 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2173 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2174 goto out;
2175 }
2176
57d104c1 2177 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2178 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2179 dev_err(hba->dev,
57d104c1
SJ		 2180 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2181 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2182 ret = -ETIMEDOUT;
2183 goto out;
2184 }
2185
2186 status = ufshcd_get_upmcrs(hba);
2187 if (status != PWR_LOCAL) {
2188 dev_err(hba->dev,
57d104c1
SJ		 2189 "pwr ctrl cmd 0x%0x failed, host umpcrs:0x%x\n",
2190 cmd->command, status);
53b3d9c3
SJ		 2191 ret = (status != PWR_OK) ? status : -1;
2192 }
2193out:
2194 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2195 hba->uic_async_done = NULL;
53b3d9c3
SJ		 2196 spin_unlock_irqrestore(hba->host->host_lock, flags);
2197 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2198
53b3d9c3
SJ		 2199 return ret;
2200}
2201
57d104c1
SJ		 2202/**
2203 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2204 * using DME_SET primitives.
2205 * @hba: per adapter instance
2206 * @mode: powr mode value
2207 *
2208 * Returns 0 on success, non-zero value on failure
2209 */
2210static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2211{
2212 struct uic_command uic_cmd = {0};
1ab27c9c 2213 int ret;
57d104c1
SJ		 2214
2215 uic_cmd.command = UIC_CMD_DME_SET;
2216 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2217 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2218 ufshcd_hold(hba, false);
2219 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2220 ufshcd_release(hba);
57d104c1 2221
1ab27c9c 2222 return ret;
57d104c1
SJ		 2223}
2224
2225static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2226{
2227 struct uic_command uic_cmd = {0};
2228
2229 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
2230
2231 return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2232}
2233
2234static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2235{
2236 struct uic_command uic_cmd = {0};
2237 int ret;
2238
2239 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2240 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2241 if (ret) {
2242 ufshcd_set_link_off(hba);
2243 ret = ufshcd_host_reset_and_restore(hba);
2244 }
2245
2246 return ret;
2247}
2248
d3e89bac 2249/**
7eb584db
DR		 2250 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2251 * @hba: per-adapter instance
d3e89bac 2252 */
7eb584db 2253static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2254{
7eb584db
DR		 2255 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2256
2257 if (hba->max_pwr_info.is_valid)
2258 return 0;
2259
2260 pwr_info->pwr_tx = FASTAUTO_MODE;
2261 pwr_info->pwr_rx = FASTAUTO_MODE;
2262 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 2263
2264 /* Get the connected lane count */
7eb584db
DR		 2265 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2266 &pwr_info->lane_rx);
2267 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2268 &pwr_info->lane_tx);
2269
2270 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2271 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2272 __func__,
2273 pwr_info->lane_rx,
2274 pwr_info->lane_tx);
2275 return -EINVAL;
2276 }
d3e89bac
SJ		 2277
2278 /*
2279 * First, get the maximum gears of HS speed.
2280 * If a zero value, it means there is no HSGEAR capability.
2281 * Then, get the maximum gears of PWM speed.
2282 */
7eb584db
DR		 2283 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2284 if (!pwr_info->gear_rx) {
2285 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2286 &pwr_info->gear_rx);
2287 if (!pwr_info->gear_rx) {
2288 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2289 __func__, pwr_info->gear_rx);
2290 return -EINVAL;
2291 }
2292 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ		 2293 }
2294
7eb584db
DR		 2295 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2296 &pwr_info->gear_tx);
2297 if (!pwr_info->gear_tx) {
d3e89bac 2298 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 2299 &pwr_info->gear_tx);
2300 if (!pwr_info->gear_tx) {
2301 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2302 __func__, pwr_info->gear_tx);
2303 return -EINVAL;
2304 }
2305 pwr_info->pwr_tx = SLOWAUTO_MODE;
2306 }
2307
2308 hba->max_pwr_info.is_valid = true;
2309 return 0;
2310}
2311
2312static int ufshcd_change_power_mode(struct ufs_hba *hba,
2313 struct ufs_pa_layer_attr *pwr_mode)
2314{
2315 int ret;
2316
2317 /* if already configured to the requested pwr_mode */
2318 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2319 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2320 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2321 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2322 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2323 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2324 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2325 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2326 return 0;
d3e89bac
SJ		 2327 }
2328
2329 /*
2330 * Configure attributes for power mode change with below.
2331 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2332 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2333 * - PA_HSSERIES
2334 */
7eb584db
DR		 2335 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2336 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2337 pwr_mode->lane_rx);
2338 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2339 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2340 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 2341 else
2342 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2343
7eb584db
DR		 2344 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2345 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2346 pwr_mode->lane_tx);
2347 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2348 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2349 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 2350 else
2351 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2352
7eb584db
DR		 2353 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2354 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2355 pwr_mode->pwr_rx == FAST_MODE ||
2356 pwr_mode->pwr_tx == FAST_MODE)
2357 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2358 pwr_mode->hs_rate);
d3e89bac 2359
7eb584db
DR		 2360 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2361 | pwr_mode->pwr_tx);
2362
2363 if (ret) {
d3e89bac 2364 dev_err(hba->dev,
7eb584db
DR		 2365 "%s: power mode change failed %d\n", __func__, ret);
2366 } else {
2367 if (hba->vops && hba->vops->pwr_change_notify)
2368 hba->vops->pwr_change_notify(hba,
2369 POST_CHANGE, NULL, pwr_mode);
2370
2371 memcpy(&hba->pwr_info, pwr_mode,
2372 sizeof(struct ufs_pa_layer_attr));
2373 }
2374
2375 return ret;
2376}
2377
2378/**
2379 * ufshcd_config_pwr_mode - configure a new power mode
2380 * @hba: per-adapter instance
2381 * @desired_pwr_mode: desired power configuration
2382 */
2383static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2384 struct ufs_pa_layer_attr *desired_pwr_mode)
2385{
2386 struct ufs_pa_layer_attr final_params = { 0 };
2387 int ret;
2388
2389 if (hba->vops && hba->vops->pwr_change_notify)
2390 hba->vops->pwr_change_notify(hba,
2391 PRE_CHANGE, desired_pwr_mode, &final_params);
2392 else
2393 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2394
2395 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 2396
2397 return ret;
2398}
2399
68078d5c
DR		 2400/**
2401 * ufshcd_complete_dev_init() - checks device readiness
2402 * hba: per-adapter instance
2403 *
2404 * Set fDeviceInit flag and poll until device toggles it.
2405 */
2406static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2407{
2408 int i, retries, err = 0;
2409 bool flag_res = 1;
2410
2411 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2412 /* Set the fDeviceInit flag */
2413 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2414 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
2415 if (!err || err == -ETIMEDOUT)
2416 break;
2417 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2418 }
2419 if (err) {
2420 dev_err(hba->dev,
2421 "%s setting fDeviceInit flag failed with error %d\n",
2422 __func__, err);
2423 goto out;
2424 }
2425
2426 /* poll for max. 100 iterations for fDeviceInit flag to clear */
2427 for (i = 0; i < 100 && !err && flag_res; i++) {
2428 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2429 err = ufshcd_query_flag(hba,
2430 UPIU_QUERY_OPCODE_READ_FLAG,
2431 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2432 if (!err || err == -ETIMEDOUT)
2433 break;
2434 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
2435 err);
2436 }
2437 }
2438 if (err)
2439 dev_err(hba->dev,
2440 "%s reading fDeviceInit flag failed with error %d\n",
2441 __func__, err);
2442 else if (flag_res)
2443 dev_err(hba->dev,
2444 "%s fDeviceInit was not cleared by the device\n",
2445 __func__);
2446
2447out:
2448 return err;
2449}
2450
7a3e97b0
SY		 2451/**
2452 * ufshcd_make_hba_operational - Make UFS controller operational
2453 * @hba: per adapter instance
2454 *
2455 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 2456 * 1. Enable required interrupts
2457 * 2. Configure interrupt aggregation
2458 * 3. Program UTRL and UTMRL base addres
2459 * 4. Configure run-stop-registers
7a3e97b0
SY		 2460 *
2461 * Returns 0 on success, non-zero value on failure
2462 */
2463static int ufshcd_make_hba_operational(struct ufs_hba *hba)
2464{
2465 int err = 0;
2466 u32 reg;
2467
6ccf44fe
SJ		 2468 /* Enable required interrupts */
2469 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
2470
2471 /* Configure interrupt aggregation */
7d568652 2472 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
6ccf44fe
SJ		 2473
2474 /* Configure UTRL and UTMRL base address registers */
2475 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
2476 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
2477 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
2478 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
2479 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
2480 REG_UTP_TASK_REQ_LIST_BASE_L);
2481 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
2482 REG_UTP_TASK_REQ_LIST_BASE_H);
2483
7a3e97b0
SY		 2484 /*
2485 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
2486 * DEI, HEI bits must be 0
2487 */
5c0c28a8 2488 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 2489 if (!(ufshcd_get_lists_status(reg))) {
2490 ufshcd_enable_run_stop_reg(hba);
2491 } else {
3b1d0580 2492 dev_err(hba->dev,
7a3e97b0
SY		 2493 "Host controller not ready to process requests");
2494 err = -EIO;
2495 goto out;
2496 }
2497
7a3e97b0
SY		 2498out:
2499 return err;
2500}
2501
2502/**
2503 * ufshcd_hba_enable - initialize the controller
2504 * @hba: per adapter instance
2505 *
2506 * The controller resets itself and controller firmware initialization
2507 * sequence kicks off. When controller is ready it will set
2508 * the Host Controller Enable bit to 1.
2509 *
2510 * Returns 0 on success, non-zero value on failure
2511 */
2512static int ufshcd_hba_enable(struct ufs_hba *hba)
2513{
2514 int retry;
2515
2516 /*
2517 * msleep of 1 and 5 used in this function might result in msleep(20),
2518 * but it was necessary to send the UFS FPGA to reset mode during
2519 * development and testing of this driver. msleep can be changed to
2520 * mdelay and retry count can be reduced based on the controller.
2521 */
2522 if (!ufshcd_is_hba_active(hba)) {
2523
2524 /* change controller state to "reset state" */
2525 ufshcd_hba_stop(hba);
2526
2527 /*
2528 * This delay is based on the testing done with UFS host
2529 * controller FPGA. The delay can be changed based on the
2530 * host controller used.
2531 */
2532 msleep(5);
2533 }
2534
57d104c1
SJ		 2535 /* UniPro link is disabled at this point */
2536 ufshcd_set_link_off(hba);
2537
5c0c28a8
SRT		 2538 if (hba->vops && hba->vops->hce_enable_notify)
2539 hba->vops->hce_enable_notify(hba, PRE_CHANGE);
2540
7a3e97b0
SY		 2541 /* start controller initialization sequence */
2542 ufshcd_hba_start(hba);
2543
2544 /*
2545 * To initialize a UFS host controller HCE bit must be set to 1.
2546 * During initialization the HCE bit value changes from 1->0->1.
2547 * When the host controller completes initialization sequence
2548 * it sets the value of HCE bit to 1. The same HCE bit is read back
2549 * to check if the controller has completed initialization sequence.
2550 * So without this delay the value HCE = 1, set in the previous
2551 * instruction might be read back.
2552 * This delay can be changed based on the controller.
2553 */
2554 msleep(1);
2555
2556 /* wait for the host controller to complete initialization */
2557 retry = 10;
2558 while (ufshcd_is_hba_active(hba)) {
2559 if (retry) {
2560 retry--;
2561 } else {
3b1d0580 2562 dev_err(hba->dev,
7a3e97b0
SY		 2563 "Controller enable failed\n");
2564 return -EIO;
2565 }
2566 msleep(5);
2567 }
5c0c28a8 2568
1d337ec2 2569 /* enable UIC related interrupts */
57d104c1 2570 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 2571
5c0c28a8
SRT		 2572 if (hba->vops && hba->vops->hce_enable_notify)
2573 hba->vops->hce_enable_notify(hba, POST_CHANGE);
2574
7a3e97b0
SY		 2575 return 0;
2576}
2577
2578/**
6ccf44fe 2579 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 2580 * @hba: per adapter instance
2581 *
6ccf44fe 2582 * Returns 0 for success, non-zero in case of failure
7a3e97b0 2583 */
6ccf44fe 2584static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 2585{
6ccf44fe 2586 int ret;
1d337ec2 2587 int retries = DME_LINKSTARTUP_RETRIES;
7a3e97b0 2588
1d337ec2
SRT		 2589 do {
2590 if (hba->vops && hba->vops->link_startup_notify)
2591 hba->vops->link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 2592
1d337ec2 2593 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 2594
1d337ec2
SRT		 2595 /* check if device is detected by inter-connect layer */
2596 if (!ret && !ufshcd_is_device_present(hba)) {
2597 dev_err(hba->dev, "%s: Device not present\n", __func__);
2598 ret = -ENXIO;
2599 goto out;
2600 }
6ccf44fe 2601
1d337ec2
SRT		 2602 /*
2603 * DME link lost indication is only received when link is up,
2604 * but we can't be sure if the link is up until link startup
2605 * succeeds. So reset the local Uni-Pro and try again.
2606 */
2607 if (ret && ufshcd_hba_enable(hba))
2608 goto out;
2609 } while (ret && retries--);
2610
2611 if (ret)
2612 /* failed to get the link up... retire */
5c0c28a8 2613 goto out;
5c0c28a8
SRT		 2614
2615 /* Include any host controller configuration via UIC commands */
2616 if (hba->vops && hba->vops->link_startup_notify) {
2617 ret = hba->vops->link_startup_notify(hba, POST_CHANGE);
2618 if (ret)
2619 goto out;
2620 }
7a3e97b0 2621
5c0c28a8 2622 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 2623out:
2624 if (ret)
2625 dev_err(hba->dev, "link startup failed %d\n", ret);
2626 return ret;
7a3e97b0
SY		 2627}
2628
5a0b0cb9
SRT		 2629/**
2630 * ufshcd_verify_dev_init() - Verify device initialization
2631 * @hba: per-adapter instance
2632 *
2633 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
2634 * device Transport Protocol (UTP) layer is ready after a reset.
2635 * If the UTP layer at the device side is not initialized, it may
2636 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
2637 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
2638 */
2639static int ufshcd_verify_dev_init(struct ufs_hba *hba)
2640{
2641 int err = 0;
2642 int retries;
2643
1ab27c9c 2644 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 2645 mutex_lock(&hba->dev_cmd.lock);
2646 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
2647 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
2648 NOP_OUT_TIMEOUT);
2649
2650 if (!err || err == -ETIMEDOUT)
2651 break;
2652
2653 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2654 }
2655 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2656 ufshcd_release(hba);
5a0b0cb9
SRT		 2657
2658 if (err)
2659 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
2660 return err;
2661}
2662
0ce147d4
SJ		 2663/**
2664 * ufshcd_set_queue_depth - set lun queue depth
2665 * @sdev: pointer to SCSI device
2666 *
2667 * Read bLUQueueDepth value and activate scsi tagged command
2668 * queueing. For WLUN, queue depth is set to 1. For best-effort
2669 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
2670 * value that host can queue.
2671 */
2672static void ufshcd_set_queue_depth(struct scsi_device *sdev)
2673{
2674 int ret = 0;
2675 u8 lun_qdepth;
2676 struct ufs_hba *hba;
2677
2678 hba = shost_priv(sdev->host);
2679
2680 lun_qdepth = hba->nutrs;
2681 ret = ufshcd_read_unit_desc_param(hba,
2682 ufshcd_scsi_to_upiu_lun(sdev->lun),
2683 UNIT_DESC_PARAM_LU_Q_DEPTH,
2684 &lun_qdepth,
2685 sizeof(lun_qdepth));
2686
2687 /* Some WLUN doesn't support unit descriptor */
2688 if (ret == -EOPNOTSUPP)
2689 lun_qdepth = 1;
2690 else if (!lun_qdepth)
2691 /* eventually, we can figure out the real queue depth */
2692 lun_qdepth = hba->nutrs;
2693 else
2694 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
2695
2696 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
2697 __func__, lun_qdepth);
ee11560f 2698 scsi_adjust_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 2699}
2700
57d104c1
SJ		 2701/*
2702 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
2703 * @hba: per-adapter instance
2704 * @lun: UFS device lun id
2705 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
2706 *
2707 * Returns 0 in case of success and b_lu_write_protect status would be returned
2708 * @b_lu_write_protect parameter.
2709 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
2710 * Returns -EINVAL in case of invalid parameters passed to this function.
2711 */
2712static int ufshcd_get_lu_wp(struct ufs_hba *hba,
2713 u8 lun,
2714 u8 *b_lu_write_protect)
2715{
2716 int ret;
2717
2718 if (!b_lu_write_protect)
2719 ret = -EINVAL;
2720 /*
2721 * According to UFS device spec, RPMB LU can't be write
2722 * protected so skip reading bLUWriteProtect parameter for
2723 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
2724 */
2725 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
2726 ret = -ENOTSUPP;
2727 else
2728 ret = ufshcd_read_unit_desc_param(hba,
2729 lun,
2730 UNIT_DESC_PARAM_LU_WR_PROTECT,
2731 b_lu_write_protect,
2732 sizeof(*b_lu_write_protect));
2733 return ret;
2734}
2735
2736/**
2737 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
2738 * status
2739 * @hba: per-adapter instance
2740 * @sdev: pointer to SCSI device
2741 *
2742 */
2743static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
2744 struct scsi_device *sdev)
2745{
2746 if (hba->dev_info.f_power_on_wp_en &&
2747 !hba->dev_info.is_lu_power_on_wp) {
2748 u8 b_lu_write_protect;
2749
2750 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
2751 &b_lu_write_protect) &&
2752 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
2753 hba->dev_info.is_lu_power_on_wp = true;
2754 }
2755}
2756
7a3e97b0
SY		 2757/**
2758 * ufshcd_slave_alloc - handle initial SCSI device configurations
2759 * @sdev: pointer to SCSI device
2760 *
2761 * Returns success
2762 */
2763static int ufshcd_slave_alloc(struct scsi_device *sdev)
2764{
2765 struct ufs_hba *hba;
2766
2767 hba = shost_priv(sdev->host);
7a3e97b0
SY		 2768
2769 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
2770 sdev->use_10_for_ms = 1;
7a3e97b0 2771
e8e7f271
SRT		 2772 /* allow SCSI layer to restart the device in case of errors */
2773 sdev->allow_restart = 1;
4264fd61 2774
b2a6c522
SRT		 2775 /* REPORT SUPPORTED OPERATION CODES is not supported */
2776 sdev->no_report_opcodes = 1;
2777
e8e7f271 2778
0ce147d4 2779 ufshcd_set_queue_depth(sdev);
4264fd61 2780
57d104c1
SJ		 2781 ufshcd_get_lu_power_on_wp_status(hba, sdev);
2782
7a3e97b0
SY		 2783 return 0;
2784}
2785
4264fd61
SRT		 2786/**
2787 * ufshcd_change_queue_depth - change queue depth
2788 * @sdev: pointer to SCSI device
2789 * @depth: required depth to set
2790 * @reason: reason for changing the depth
2791 *
2792 * Change queue depth according to the reason and make sure
2793 * the max. limits are not crossed.
2794 */
7289f983
SRT		 2795static int ufshcd_change_queue_depth(struct scsi_device *sdev,
2796 int depth, int reason)
4264fd61
SRT		 2797{
2798 struct ufs_hba *hba = shost_priv(sdev->host);
2799
2800 if (depth > hba->nutrs)
2801 depth = hba->nutrs;
2802
2803 switch (reason) {
2804 case SCSI_QDEPTH_DEFAULT:
2805 case SCSI_QDEPTH_RAMP_UP:
c8b09f6f 2806 scsi_adjust_queue_depth(sdev, depth);
4264fd61
SRT		 2807 break;
2808 case SCSI_QDEPTH_QFULL:
2809 scsi_track_queue_full(sdev, depth);
2810 break;
2811 default:
2812 return -EOPNOTSUPP;
2813 }
2814
2815 return depth;
2816}
2817
eeda4749
AM		 2818/**
2819 * ufshcd_slave_configure - adjust SCSI device configurations
2820 * @sdev: pointer to SCSI device
2821 */
2822static int ufshcd_slave_configure(struct scsi_device *sdev)
2823{
2824 struct request_queue *q = sdev->request_queue;
2825
2826 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2827 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
2828
2829 return 0;
2830}
2831
7a3e97b0
SY		 2832/**
2833 * ufshcd_slave_destroy - remove SCSI device configurations
2834 * @sdev: pointer to SCSI device
2835 */
2836static void ufshcd_slave_destroy(struct scsi_device *sdev)
2837{
2838 struct ufs_hba *hba;
2839
2840 hba = shost_priv(sdev->host);
0ce147d4
SJ		 2841 /* Drop the reference as it won't be needed anymore */
2842 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN)
2843 hba->sdev_ufs_device = NULL;
7a3e97b0
SY		 2844}
2845
2846/**
2847 * ufshcd_task_req_compl - handle task management request completion
2848 * @hba: per adapter instance
2849 * @index: index of the completed request
e2933132 2850 * @resp: task management service response
7a3e97b0 2851 *
e2933132 2852 * Returns non-zero value on error, zero on success
7a3e97b0 2853 */
e2933132 2854static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 2855{
2856 struct utp_task_req_desc *task_req_descp;
2857 struct utp_upiu_task_rsp *task_rsp_upiup;
2858 unsigned long flags;
2859 int ocs_value;
2860 int task_result;
2861
2862 spin_lock_irqsave(hba->host->host_lock, flags);
2863
2864 /* Clear completed tasks from outstanding_tasks */
2865 __clear_bit(index, &hba->outstanding_tasks);
2866
2867 task_req_descp = hba->utmrdl_base_addr;
2868 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
2869
2870 if (ocs_value == OCS_SUCCESS) {
2871 task_rsp_upiup = (struct utp_upiu_task_rsp *)
2872 task_req_descp[index].task_rsp_upiu;
2873 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
2874 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
e2933132
SRT		 2875 if (resp)
2876 *resp = (u8)task_result;
7a3e97b0 2877 } else {
e2933132
SRT		 2878 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
2879 __func__, ocs_value);
7a3e97b0
SY		 2880 }
2881 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 2882
2883 return ocs_value;
7a3e97b0
SY		 2884}
2885
7a3e97b0
SY		 2886/**
2887 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
2888 * @lrb: pointer to local reference block of completed command
2889 * @scsi_status: SCSI command status
2890 *
2891 * Returns value base on SCSI command status
2892 */
2893static inline int
2894ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
2895{
2896 int result = 0;
2897
2898 switch (scsi_status) {
7a3e97b0 2899 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 2900 ufshcd_copy_sense_data(lrbp);
2901 case SAM_STAT_GOOD:
7a3e97b0
SY		 2902 result |= DID_OK << 16 |
2903 COMMAND_COMPLETE << 8 |
1c2623c5 2904 scsi_status;
7a3e97b0
SY		 2905 break;
2906 case SAM_STAT_TASK_SET_FULL:
1c2623c5 2907 case SAM_STAT_BUSY:
7a3e97b0 2908 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 2909 ufshcd_copy_sense_data(lrbp);
2910 result |= scsi_status;
7a3e97b0
SY		 2911 break;
2912 default:
2913 result |= DID_ERROR << 16;
2914 break;
2915 } /* end of switch */
2916
2917 return result;
2918}
2919
2920/**
2921 * ufshcd_transfer_rsp_status - Get overall status of the response
2922 * @hba: per adapter instance
2923 * @lrb: pointer to local reference block of completed command
2924 *
2925 * Returns result of the command to notify SCSI midlayer
2926 */
2927static inline int
2928ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2929{
2930 int result = 0;
2931 int scsi_status;
2932 int ocs;
2933
2934 /* overall command status of utrd */
2935 ocs = ufshcd_get_tr_ocs(lrbp);
2936
2937 switch (ocs) {
2938 case OCS_SUCCESS:
5a0b0cb9 2939 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 2940
5a0b0cb9
SRT		 2941 switch (result) {
2942 case UPIU_TRANSACTION_RESPONSE:
2943 /*
2944 * get the response UPIU result to extract
2945 * the SCSI command status
2946 */
2947 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
2948
2949 /*
2950 * get the result based on SCSI status response
2951 * to notify the SCSI midlayer of the command status
2952 */
2953 scsi_status = result & MASK_SCSI_STATUS;
2954 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59
SRT		 2955
2956 if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
2957 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 2958 break;
2959 case UPIU_TRANSACTION_REJECT_UPIU:
2960 /* TODO: handle Reject UPIU Response */
2961 result = DID_ERROR << 16;
3b1d0580 2962 dev_err(hba->dev,
5a0b0cb9
SRT		 2963 "Reject UPIU not fully implemented\n");
2964 break;
2965 default:
2966 result = DID_ERROR << 16;
2967 dev_err(hba->dev,
2968 "Unexpected request response code = %x\n",
2969 result);
7a3e97b0
SY		 2970 break;
2971 }
7a3e97b0
SY		 2972 break;
2973 case OCS_ABORTED:
2974 result |= DID_ABORT << 16;
2975 break;
e8e7f271
SRT		 2976 case OCS_INVALID_COMMAND_STATUS:
2977 result |= DID_REQUEUE << 16;
2978 break;
7a3e97b0
SY		 2979 case OCS_INVALID_CMD_TABLE_ATTR:
2980 case OCS_INVALID_PRDT_ATTR:
2981 case OCS_MISMATCH_DATA_BUF_SIZE:
2982 case OCS_MISMATCH_RESP_UPIU_SIZE:
2983 case OCS_PEER_COMM_FAILURE:
2984 case OCS_FATAL_ERROR:
2985 default:
2986 result |= DID_ERROR << 16;
3b1d0580 2987 dev_err(hba->dev,
7a3e97b0
SY		 2988 "OCS error from controller = %x\n", ocs);
2989 break;
2990 } /* end of switch */
2991
2992 return result;
2993}
2994
6ccf44fe
SJ		 2995/**
2996 * ufshcd_uic_cmd_compl - handle completion of uic command
2997 * @hba: per adapter instance
53b3d9c3 2998 * @intr_status: interrupt status generated by the controller
6ccf44fe 2999 */
53b3d9c3 3000static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3001{
53b3d9c3 3002 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3003 hba->active_uic_cmd->argument2 |=
3004 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3005 hba->active_uic_cmd->argument3 =
3006 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3007 complete(&hba->active_uic_cmd->done);
3008 }
53b3d9c3 3009
57d104c1
SJ		 3010 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3011 complete(hba->uic_async_done);
6ccf44fe
SJ		 3012}
3013
7a3e97b0
SY		 3014/**
3015 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3016 * @hba: per adapter instance
3017 */
3018static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3019{
5a0b0cb9
SRT		 3020 struct ufshcd_lrb *lrbp;
3021 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3022 unsigned long completed_reqs;
3023 u32 tr_doorbell;
3024 int result;
3025 int index;
e9d501b1
DR		 3026
3027 /* Resetting interrupt aggregation counters first and reading the
3028 * DOOR_BELL afterward allows us to handle all the completed requests.
3029 * In order to prevent other interrupts starvation the DB is read once
3030 * after reset. The down side of this solution is the possibility of
3031 * false interrupt if device completes another request after resetting
3032 * aggregation and before reading the DB.
3033 */
3034 ufshcd_reset_intr_aggr(hba);
7a3e97b0 3035
b873a275 3036 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 3037 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3038
e9d501b1
DR		 3039 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3040 lrbp = &hba->lrb[index];
3041 cmd = lrbp->cmd;
3042 if (cmd) {
3043 result = ufshcd_transfer_rsp_status(hba, lrbp);
3044 scsi_dma_unmap(cmd);
3045 cmd->result = result;
3046 /* Mark completed command as NULL in LRB */
3047 lrbp->cmd = NULL;
3048 clear_bit_unlock(index, &hba->lrb_in_use);
3049 /* Do not touch lrbp after scsi done */
3050 cmd->scsi_done(cmd);
1ab27c9c 3051 __ufshcd_release(hba);
e9d501b1
DR		 3052 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) {
3053 if (hba->dev_cmd.complete)
3054 complete(hba->dev_cmd.complete);
3055 }
3056 }
7a3e97b0
SY		 3057
3058 /* clear corresponding bits of completed commands */
3059 hba->outstanding_reqs ^= completed_reqs;
3060
856b3483
ST		 3061 ufshcd_clk_scaling_update_busy(hba);
3062
5a0b0cb9
SRT		 3063 /* we might have free'd some tags above */
3064 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3065}
3066
66ec6d59
SRT		 3067/**
3068 * ufshcd_disable_ee - disable exception event
3069 * @hba: per-adapter instance
3070 * @mask: exception event to disable
3071 *
3072 * Disables exception event in the device so that the EVENT_ALERT
3073 * bit is not set.
3074 *
3075 * Returns zero on success, non-zero error value on failure.
3076 */
3077static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3078{
3079 int err = 0;
3080 u32 val;
3081
3082 if (!(hba->ee_ctrl_mask & mask))
3083 goto out;
3084
3085 val = hba->ee_ctrl_mask & ~mask;
3086 val &= 0xFFFF; /* 2 bytes */
3087 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3088 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3089 if (!err)
3090 hba->ee_ctrl_mask &= ~mask;
3091out:
3092 return err;
3093}
3094
3095/**
3096 * ufshcd_enable_ee - enable exception event
3097 * @hba: per-adapter instance
3098 * @mask: exception event to enable
3099 *
3100 * Enable corresponding exception event in the device to allow
3101 * device to alert host in critical scenarios.
3102 *
3103 * Returns zero on success, non-zero error value on failure.
3104 */
3105static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3106{
3107 int err = 0;
3108 u32 val;
3109
3110 if (hba->ee_ctrl_mask & mask)
3111 goto out;
3112
3113 val = hba->ee_ctrl_mask | mask;
3114 val &= 0xFFFF; /* 2 bytes */
3115 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3116 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3117 if (!err)
3118 hba->ee_ctrl_mask |= mask;
3119out:
3120 return err;
3121}
3122
3123/**
3124 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3125 * @hba: per-adapter instance
3126 *
3127 * Allow device to manage background operations on its own. Enabling
3128 * this might lead to inconsistent latencies during normal data transfers
3129 * as the device is allowed to manage its own way of handling background
3130 * operations.
3131 *
3132 * Returns zero on success, non-zero on failure.
3133 */
3134static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3135{
3136 int err = 0;
3137
3138 if (hba->auto_bkops_enabled)
3139 goto out;
3140
3141 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3142 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3143 if (err) {
3144 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3145 __func__, err);
3146 goto out;
3147 }
3148
3149 hba->auto_bkops_enabled = true;
3150
3151 /* No need of URGENT_BKOPS exception from the device */
3152 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3153 if (err)
3154 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3155 __func__, err);
3156out:
3157 return err;
3158}
3159
3160/**
3161 * ufshcd_disable_auto_bkops - block device in doing background operations
3162 * @hba: per-adapter instance
3163 *
3164 * Disabling background operations improves command response latency but
3165 * has drawback of device moving into critical state where the device is
3166 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3167 * host is idle so that BKOPS are managed effectively without any negative
3168 * impacts.
3169 *
3170 * Returns zero on success, non-zero on failure.
3171 */
3172static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3173{
3174 int err = 0;
3175
3176 if (!hba->auto_bkops_enabled)
3177 goto out;
3178
3179 /*
3180 * If host assisted BKOPs is to be enabled, make sure
3181 * urgent bkops exception is allowed.
3182 */
3183 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3184 if (err) {
3185 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3186 __func__, err);
3187 goto out;
3188 }
3189
3190 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
3191 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3192 if (err) {
3193 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3194 __func__, err);
3195 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3196 goto out;
3197 }
3198
3199 hba->auto_bkops_enabled = false;
3200out:
3201 return err;
3202}
3203
3204/**
3205 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3206 * @hba: per adapter instance
3207 *
3208 * After a device reset the device may toggle the BKOPS_EN flag
3209 * to default value. The s/w tracking variables should be updated
3210 * as well. Do this by forcing enable of auto bkops.
3211 */
3212static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3213{
3214 hba->auto_bkops_enabled = false;
3215 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3216 ufshcd_enable_auto_bkops(hba);
3217}
3218
3219static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3220{
3221 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3222 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3223}
3224
3225/**
57d104c1 3226 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3227 * @hba: per-adapter instance
57d104c1 3228 * @status: bkops_status value
66ec6d59 3229 *
57d104c1
SJ		 3230 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3231 * flag in the device to permit background operations if the device
3232 * bkops_status is greater than or equal to "status" argument passed to
3233 * this function, disable otherwise.
3234 *
3235 * Returns 0 for success, non-zero in case of failure.
3236 *
3237 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3238 * to know whether auto bkops is enabled or disabled after this function
3239 * returns control to it.
66ec6d59 3240 */
57d104c1
SJ		 3241static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3242 enum bkops_status status)
66ec6d59
SRT		 3243{
3244 int err;
57d104c1 3245 u32 curr_status = 0;
66ec6d59 3246
57d104c1 3247 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 3248 if (err) {
3249 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3250 __func__, err);
3251 goto out;
57d104c1
SJ		 3252 } else if (curr_status > BKOPS_STATUS_MAX) {
3253 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3254 __func__, curr_status);
3255 err = -EINVAL;
3256 goto out;
66ec6d59
SRT		 3257 }
3258
57d104c1 3259 if (curr_status >= status)
66ec6d59 3260 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 3261 else
3262 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 3263out:
3264 return err;
3265}
3266
57d104c1
SJ		 3267/**
3268 * ufshcd_urgent_bkops - handle urgent bkops exception event
3269 * @hba: per-adapter instance
3270 *
3271 * Enable fBackgroundOpsEn flag in the device to permit background
3272 * operations.
3273 *
3274 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3275 * and negative error value for any other failure.
3276 */
3277static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3278{
3279 return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT);
3280}
3281
66ec6d59
SRT		 3282static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3283{
3284 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3285 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3286}
3287
3288/**
3289 * ufshcd_exception_event_handler - handle exceptions raised by device
3290 * @work: pointer to work data
3291 *
3292 * Read bExceptionEventStatus attribute from the device and handle the
3293 * exception event accordingly.
3294 */
3295static void ufshcd_exception_event_handler(struct work_struct *work)
3296{
3297 struct ufs_hba *hba;
3298 int err;
3299 u32 status = 0;
3300 hba = container_of(work, struct ufs_hba, eeh_work);
3301
62694735 3302 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 3303 err = ufshcd_get_ee_status(hba, &status);
3304 if (err) {
3305 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3306 __func__, err);
3307 goto out;
3308 }
3309
3310 status &= hba->ee_ctrl_mask;
3311 if (status & MASK_EE_URGENT_BKOPS) {
3312 err = ufshcd_urgent_bkops(hba);
57d104c1 3313 if (err < 0)
66ec6d59
SRT		 3314 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3315 __func__, err);
3316 }
3317out:
62694735 3318 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 3319 return;
3320}
3321
7a3e97b0 3322/**
e8e7f271
SRT		 3323 * ufshcd_err_handler - handle UFS errors that require s/w attention
3324 * @work: pointer to work structure
7a3e97b0 3325 */
e8e7f271 3326static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 3327{
3328 struct ufs_hba *hba;
e8e7f271
SRT		 3329 unsigned long flags;
3330 u32 err_xfer = 0;
3331 u32 err_tm = 0;
3332 int err = 0;
3333 int tag;
3334
3335 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 3336
62694735 3337 pm_runtime_get_sync(hba->dev);
1ab27c9c 3338 ufshcd_hold(hba, false);
e8e7f271
SRT		 3339
3340 spin_lock_irqsave(hba->host->host_lock, flags);
3341 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
3342 spin_unlock_irqrestore(hba->host->host_lock, flags);
3343 goto out;
3344 }
3345
3346 hba->ufshcd_state = UFSHCD_STATE_RESET;
3347 ufshcd_set_eh_in_progress(hba);
3348
3349 /* Complete requests that have door-bell cleared by h/w */
3350 ufshcd_transfer_req_compl(hba);
3351 ufshcd_tmc_handler(hba);
3352 spin_unlock_irqrestore(hba->host->host_lock, flags);
3353
3354 /* Clear pending transfer requests */
3355 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
3356 if (ufshcd_clear_cmd(hba, tag))
3357 err_xfer |= 1 << tag;
3358
3359 /* Clear pending task management requests */
3360 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
3361 if (ufshcd_clear_tm_cmd(hba, tag))
3362 err_tm |= 1 << tag;
3363
3364 /* Complete the requests that are cleared by s/w */
3365 spin_lock_irqsave(hba->host->host_lock, flags);
3366 ufshcd_transfer_req_compl(hba);
3367 ufshcd_tmc_handler(hba);
3368 spin_unlock_irqrestore(hba->host->host_lock, flags);
3369
3370 /* Fatal errors need reset */
3371 if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
3372 ((hba->saved_err & UIC_ERROR) &&
3373 (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
3374 err = ufshcd_reset_and_restore(hba);
3375 if (err) {
3376 dev_err(hba->dev, "%s: reset and restore failed\n",
3377 __func__);
3378 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3379 }
3380 /*
3381 * Inform scsi mid-layer that we did reset and allow to handle
3382 * Unit Attention properly.
3383 */
3384 scsi_report_bus_reset(hba->host, 0);
3385 hba->saved_err = 0;
3386 hba->saved_uic_err = 0;
3387 }
3388 ufshcd_clear_eh_in_progress(hba);
3389
3390out:
3391 scsi_unblock_requests(hba->host);
1ab27c9c 3392 ufshcd_release(hba);
62694735 3393 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 3394}
3395
3396/**
e8e7f271
SRT		 3397 * ufshcd_update_uic_error - check and set fatal UIC error flags.
3398 * @hba: per-adapter instance
7a3e97b0 3399 */
e8e7f271 3400static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 3401{
3402 u32 reg;
3403
e8e7f271
SRT		 3404 /* PA_INIT_ERROR is fatal and needs UIC reset */
3405 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
3406 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
3407 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
3408
3409 /* UIC NL/TL/DME errors needs software retry */
3410 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
3411 if (reg)
3412 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
3413
3414 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
3415 if (reg)
3416 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
3417
3418 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
3419 if (reg)
3420 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
3421
3422 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
3423 __func__, hba->uic_error);
3424}
3425
3426/**
3427 * ufshcd_check_errors - Check for errors that need s/w attention
3428 * @hba: per-adapter instance
3429 */
3430static void ufshcd_check_errors(struct ufs_hba *hba)
3431{
3432 bool queue_eh_work = false;
3433
7a3e97b0 3434 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 3435 queue_eh_work = true;
7a3e97b0
SY		 3436
3437 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 3438 hba->uic_error = 0;
3439 ufshcd_update_uic_error(hba);
3440 if (hba->uic_error)
3441 queue_eh_work = true;
7a3e97b0 3442 }
e8e7f271
SRT		 3443
3444 if (queue_eh_work) {
3445 /* handle fatal errors only when link is functional */
3446 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
3447 /* block commands from scsi mid-layer */
3448 scsi_block_requests(hba->host);
3449
3450 /* transfer error masks to sticky bits */
3451 hba->saved_err |= hba->errors;
3452 hba->saved_uic_err |= hba->uic_error;
3453
3454 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3455 schedule_work(&hba->eh_work);
3456 }
3441da7d 3457 }
e8e7f271
SRT		 3458 /*
3459 * if (!queue_eh_work) -
3460 * Other errors are either non-fatal where host recovers
3461 * itself without s/w intervention or errors that will be
3462 * handled by the SCSI core layer.
3463 */
7a3e97b0
SY		 3464}
3465
3466/**
3467 * ufshcd_tmc_handler - handle task management function completion
3468 * @hba: per adapter instance
3469 */
3470static void ufshcd_tmc_handler(struct ufs_hba *hba)
3471{
3472 u32 tm_doorbell;
3473
b873a275 3474 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 3475 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 3476 wake_up(&hba->tm_wq);
7a3e97b0
SY		 3477}
3478
3479/**
3480 * ufshcd_sl_intr - Interrupt service routine
3481 * @hba: per adapter instance
3482 * @intr_status: contains interrupts generated by the controller
3483 */
3484static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
3485{
3486 hba->errors = UFSHCD_ERROR_MASK & intr_status;
3487 if (hba->errors)
e8e7f271 3488 ufshcd_check_errors(hba);
7a3e97b0 3489
53b3d9c3
SJ		 3490 if (intr_status & UFSHCD_UIC_MASK)
3491 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 3492
3493 if (intr_status & UTP_TASK_REQ_COMPL)
3494 ufshcd_tmc_handler(hba);
3495
3496 if (intr_status & UTP_TRANSFER_REQ_COMPL)
3497 ufshcd_transfer_req_compl(hba);
3498}
3499
3500/**
3501 * ufshcd_intr - Main interrupt service routine
3502 * @irq: irq number
3503 * @__hba: pointer to adapter instance
3504 *
3505 * Returns IRQ_HANDLED - If interrupt is valid
3506 * IRQ_NONE - If invalid interrupt
3507 */
3508static irqreturn_t ufshcd_intr(int irq, void *__hba)
3509{
3510 u32 intr_status;
3511 irqreturn_t retval = IRQ_NONE;
3512 struct ufs_hba *hba = __hba;
3513
3514 spin_lock(hba->host->host_lock);
b873a275 3515 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0
SY		 3516
3517 if (intr_status) {
261ea452 3518 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7a3e97b0 3519 ufshcd_sl_intr(hba, intr_status);
7a3e97b0
SY		 3520 retval = IRQ_HANDLED;
3521 }
3522 spin_unlock(hba->host->host_lock);
3523 return retval;
3524}
3525
e2933132
SRT		 3526static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
3527{
3528 int err = 0;
3529 u32 mask = 1 << tag;
3530 unsigned long flags;
3531
3532 if (!test_bit(tag, &hba->outstanding_tasks))
3533 goto out;
3534
3535 spin_lock_irqsave(hba->host->host_lock, flags);
3536 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
3537 spin_unlock_irqrestore(hba->host->host_lock, flags);
3538
3539 /* poll for max. 1 sec to clear door bell register by h/w */
3540 err = ufshcd_wait_for_register(hba,
3541 REG_UTP_TASK_REQ_DOOR_BELL,
3542 mask, 0, 1000, 1000);
3543out:
3544 return err;
3545}
3546
7a3e97b0
SY		 3547/**
3548 * ufshcd_issue_tm_cmd - issues task management commands to controller
3549 * @hba: per adapter instance
e2933132
SRT		 3550 * @lun_id: LUN ID to which TM command is sent
3551 * @task_id: task ID to which the TM command is applicable
3552 * @tm_function: task management function opcode
3553 * @tm_response: task management service response return value
7a3e97b0 3554 *
e2933132 3555 * Returns non-zero value on error, zero on success.
7a3e97b0 3556 */
e2933132
SRT		 3557static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
3558 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 3559{
3560 struct utp_task_req_desc *task_req_descp;
3561 struct utp_upiu_task_req *task_req_upiup;
3562 struct Scsi_Host *host;
3563 unsigned long flags;
e2933132 3564 int free_slot;
7a3e97b0 3565 int err;
e2933132 3566 int task_tag;
7a3e97b0
SY		 3567
3568 host = hba->host;
3569
e2933132
SRT		 3570 /*
3571 * Get free slot, sleep if slots are unavailable.
3572 * Even though we use wait_event() which sleeps indefinitely,
3573 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
3574 */
3575 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 3576 ufshcd_hold(hba, false);
7a3e97b0 3577
e2933132 3578 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 3579 task_req_descp = hba->utmrdl_base_addr;
3580 task_req_descp += free_slot;
3581
3582 /* Configure task request descriptor */
3583 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
3584 task_req_descp->header.dword_2 =
3585 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
3586
3587 /* Configure task request UPIU */
3588 task_req_upiup =
3589 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 3590 task_tag = hba->nutrs + free_slot;
7a3e97b0 3591 task_req_upiup->header.dword_0 =
5a0b0cb9 3592 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 3593 lun_id, task_tag);
7a3e97b0 3594 task_req_upiup->header.dword_1 =
5a0b0cb9 3595 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 3596 /*
3597 * The host shall provide the same value for LUN field in the basic
3598 * header and for Input Parameter.
3599 */
e2933132
SRT		 3600 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
3601 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0
SY		 3602
3603 /* send command to the controller */
3604 __set_bit(free_slot, &hba->outstanding_tasks);
b873a275 3605 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0
SY		 3606
3607 spin_unlock_irqrestore(host->host_lock, flags);
3608
3609 /* wait until the task management command is completed */
e2933132
SRT		 3610 err = wait_event_timeout(hba->tm_wq,
3611 test_bit(free_slot, &hba->tm_condition),
3612 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 3613 if (!err) {
e2933132
SRT		 3614 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
3615 __func__, tm_function);
3616 if (ufshcd_clear_tm_cmd(hba, free_slot))
3617 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
3618 __func__, free_slot);
3619 err = -ETIMEDOUT;
3620 } else {
3621 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 3622 }
e2933132 3623
7a3e97b0 3624 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 3625 ufshcd_put_tm_slot(hba, free_slot);
3626 wake_up(&hba->tm_tag_wq);
3627
1ab27c9c 3628 ufshcd_release(hba);
7a3e97b0
SY		 3629 return err;
3630}
3631
3632/**
3441da7d
SRT		 3633 * ufshcd_eh_device_reset_handler - device reset handler registered to
3634 * scsi layer.
7a3e97b0
SY		 3635 * @cmd: SCSI command pointer
3636 *
3637 * Returns SUCCESS/FAILED
3638 */
3441da7d 3639static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 3640{
3641 struct Scsi_Host *host;
3642 struct ufs_hba *hba;
3643 unsigned int tag;
3644 u32 pos;
3645 int err;
e2933132
SRT		 3646 u8 resp = 0xF;
3647 struct ufshcd_lrb *lrbp;
3441da7d 3648 unsigned long flags;
7a3e97b0
SY		 3649
3650 host = cmd->device->host;
3651 hba = shost_priv(host);
3652 tag = cmd->request->tag;
3653
e2933132
SRT		 3654 lrbp = &hba->lrb[tag];
3655 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
3656 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 3657 if (!err)
3658 err = resp;
7a3e97b0 3659 goto out;
e2933132 3660 }
7a3e97b0 3661
3441da7d
SRT		 3662 /* clear the commands that were pending for corresponding LUN */
3663 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
3664 if (hba->lrb[pos].lun == lrbp->lun) {
3665 err = ufshcd_clear_cmd(hba, pos);
3666 if (err)
3667 break;
7a3e97b0 3668 }
3441da7d
SRT		 3669 }
3670 spin_lock_irqsave(host->host_lock, flags);
3671 ufshcd_transfer_req_compl(hba);
3672 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 3673out:
3441da7d
SRT		 3674 if (!err) {
3675 err = SUCCESS;
3676 } else {
3677 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3678 err = FAILED;
3679 }
7a3e97b0
SY		 3680 return err;
3681}
3682
7a3e97b0
SY		 3683/**
3684 * ufshcd_abort - abort a specific command
3685 * @cmd: SCSI command pointer
3686 *
f20810d8
SRT		 3687 * Abort the pending command in device by sending UFS_ABORT_TASK task management
3688 * command, and in host controller by clearing the door-bell register. There can
3689 * be race between controller sending the command to the device while abort is
3690 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
3691 * really issued and then try to abort it.
3692 *
7a3e97b0
SY		 3693 * Returns SUCCESS/FAILED
3694 */
3695static int ufshcd_abort(struct scsi_cmnd *cmd)
3696{
3697 struct Scsi_Host *host;
3698 struct ufs_hba *hba;
3699 unsigned long flags;
3700 unsigned int tag;
f20810d8
SRT		 3701 int err = 0;
3702 int poll_cnt;
e2933132
SRT		 3703 u8 resp = 0xF;
3704 struct ufshcd_lrb *lrbp;
e9d501b1 3705 u32 reg;
7a3e97b0
SY		 3706
3707 host = cmd->device->host;
3708 hba = shost_priv(host);
3709 tag = cmd->request->tag;
3710
1ab27c9c 3711 ufshcd_hold(hba, false);
f20810d8
SRT		 3712 /* If command is already aborted/completed, return SUCCESS */
3713 if (!(test_bit(tag, &hba->outstanding_reqs)))
3714 goto out;
7a3e97b0 3715
e9d501b1
DR		 3716 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3717 if (!(reg & (1 << tag))) {
3718 dev_err(hba->dev,
3719 "%s: cmd was completed, but without a notifying intr, tag = %d",
3720 __func__, tag);
3721 }
3722
f20810d8
SRT		 3723 lrbp = &hba->lrb[tag];
3724 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
3725 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3726 UFS_QUERY_TASK, &resp);
3727 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
3728 /* cmd pending in the device */
3729 break;
3730 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3731 /*
3732 * cmd not pending in the device, check if it is
3733 * in transition.
3734 */
3735 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3736 if (reg & (1 << tag)) {
3737 /* sleep for max. 200us to stabilize */
3738 usleep_range(100, 200);
3739 continue;
3740 }
3741 /* command completed already */
3742 goto out;
3743 } else {
3744 if (!err)
3745 err = resp; /* service response error */
3746 goto out;
3747 }
3748 }
3749
3750 if (!poll_cnt) {
3751 err = -EBUSY;
7a3e97b0
SY		 3752 goto out;
3753 }
7a3e97b0 3754
e2933132
SRT		 3755 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3756 UFS_ABORT_TASK, &resp);
3757 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3758 if (!err)
3759 err = resp; /* service response error */
7a3e97b0 3760 goto out;
e2933132 3761 }
7a3e97b0 3762
f20810d8
SRT		 3763 err = ufshcd_clear_cmd(hba, tag);
3764 if (err)
3765 goto out;
3766
7a3e97b0
SY		 3767 scsi_dma_unmap(cmd);
3768
3769 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 3770 __clear_bit(tag, &hba->outstanding_reqs);
3771 hba->lrb[tag].cmd = NULL;
3772 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 3773
3774 clear_bit_unlock(tag, &hba->lrb_in_use);
3775 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 3776
7a3e97b0 3777out:
f20810d8
SRT		 3778 if (!err) {
3779 err = SUCCESS;
3780 } else {
3781 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3782 err = FAILED;
3783 }
3784
1ab27c9c
ST		 3785 /*
3786 * This ufshcd_release() corresponds to the original scsi cmd that got
3787 * aborted here (as we won't get any IRQ for it).
3788 */
3789 ufshcd_release(hba);
7a3e97b0
SY		 3790 return err;
3791}
3792
3441da7d
SRT		 3793/**
3794 * ufshcd_host_reset_and_restore - reset and restore host controller
3795 * @hba: per-adapter instance
3796 *
3797 * Note that host controller reset may issue DME_RESET to
3798 * local and remote (device) Uni-Pro stack and the attributes
3799 * are reset to default state.
3800 *
3801 * Returns zero on success, non-zero on failure
3802 */
3803static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
3804{
3805 int err;
3441da7d
SRT		 3806 unsigned long flags;
3807
3808 /* Reset the host controller */
3809 spin_lock_irqsave(hba->host->host_lock, flags);
3810 ufshcd_hba_stop(hba);
3811 spin_unlock_irqrestore(hba->host->host_lock, flags);
3812
3813 err = ufshcd_hba_enable(hba);
3814 if (err)
3815 goto out;
3816
3817 /* Establish the link again and restore the device */
1d337ec2
SRT		 3818 err = ufshcd_probe_hba(hba);
3819
3820 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 3821 err = -EIO;
3822out:
3823 if (err)
3824 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
3825
3826 return err;
3827}
3828
3829/**
3830 * ufshcd_reset_and_restore - reset and re-initialize host/device
3831 * @hba: per-adapter instance
3832 *
3833 * Reset and recover device, host and re-establish link. This
3834 * is helpful to recover the communication in fatal error conditions.
3835 *
3836 * Returns zero on success, non-zero on failure
3837 */
3838static int ufshcd_reset_and_restore(struct ufs_hba *hba)
3839{
3840 int err = 0;
3841 unsigned long flags;
1d337ec2 3842 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 3843
1d337ec2
SRT		 3844 do {
3845 err = ufshcd_host_reset_and_restore(hba);
3846 } while (err && --retries);
3441da7d
SRT		 3847
3848 /*
3849 * After reset the door-bell might be cleared, complete
3850 * outstanding requests in s/w here.
3851 */
3852 spin_lock_irqsave(hba->host->host_lock, flags);
3853 ufshcd_transfer_req_compl(hba);
3854 ufshcd_tmc_handler(hba);
3855 spin_unlock_irqrestore(hba->host->host_lock, flags);
3856
3857 return err;
3858}
3859
3860/**
3861 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
3862 * @cmd - SCSI command pointer
3863 *
3864 * Returns SUCCESS/FAILED
3865 */
3866static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
3867{
3868 int err;
3869 unsigned long flags;
3870 struct ufs_hba *hba;
3871
3872 hba = shost_priv(cmd->device->host);
3873
1ab27c9c 3874 ufshcd_hold(hba, false);
3441da7d
SRT		 3875 /*
3876 * Check if there is any race with fatal error handling.
3877 * If so, wait for it to complete. Even though fatal error
3878 * handling does reset and restore in some cases, don't assume
3879 * anything out of it. We are just avoiding race here.
3880 */
3881 do {
3882 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 3883 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 3884 hba->ufshcd_state == UFSHCD_STATE_RESET))
3885 break;
3886 spin_unlock_irqrestore(hba->host->host_lock, flags);
3887 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 3888 flush_work(&hba->eh_work);
3441da7d
SRT		 3889 } while (1);
3890
3891 hba->ufshcd_state = UFSHCD_STATE_RESET;
3892 ufshcd_set_eh_in_progress(hba);
3893 spin_unlock_irqrestore(hba->host->host_lock, flags);
3894
3895 err = ufshcd_reset_and_restore(hba);
3896
3897 spin_lock_irqsave(hba->host->host_lock, flags);
3898 if (!err) {
3899 err = SUCCESS;
3900 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
3901 } else {
3902 err = FAILED;
3903 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3904 }
3905 ufshcd_clear_eh_in_progress(hba);
3906 spin_unlock_irqrestore(hba->host->host_lock, flags);
3907
1ab27c9c 3908 ufshcd_release(hba);
3441da7d
SRT		 3909 return err;
3910}
3911
3a4bf06d
YG		 3912/**
3913 * ufshcd_get_max_icc_level - calculate the ICC level
3914 * @sup_curr_uA: max. current supported by the regulator
3915 * @start_scan: row at the desc table to start scan from
3916 * @buff: power descriptor buffer
3917 *
3918 * Returns calculated max ICC level for specific regulator
3919 */
3920static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
3921{
3922 int i;
3923 int curr_uA;
3924 u16 data;
3925 u16 unit;
3926
3927 for (i = start_scan; i >= 0; i--) {
3928 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
3929 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
3930 ATTR_ICC_LVL_UNIT_OFFSET;
3931 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
3932 switch (unit) {
3933 case UFSHCD_NANO_AMP:
3934 curr_uA = curr_uA / 1000;
3935 break;
3936 case UFSHCD_MILI_AMP:
3937 curr_uA = curr_uA * 1000;
3938 break;
3939 case UFSHCD_AMP:
3940 curr_uA = curr_uA * 1000 * 1000;
3941 break;
3942 case UFSHCD_MICRO_AMP:
3943 default:
3944 break;
3945 }
3946 if (sup_curr_uA >= curr_uA)
3947 break;
3948 }
3949 if (i < 0) {
3950 i = 0;
3951 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
3952 }
3953
3954 return (u32)i;
3955}
3956
3957/**
3958 * ufshcd_calc_icc_level - calculate the max ICC level
3959 * In case regulators are not initialized we'll return 0
3960 * @hba: per-adapter instance
3961 * @desc_buf: power descriptor buffer to extract ICC levels from.
3962 * @len: length of desc_buff
3963 *
3964 * Returns calculated ICC level
3965 */
3966static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
3967 u8 *desc_buf, int len)
3968{
3969 u32 icc_level = 0;
3970
3971 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
3972 !hba->vreg_info.vccq2) {
3973 dev_err(hba->dev,
3974 "%s: Regulator capability was not set, actvIccLevel=%d",
3975 __func__, icc_level);
3976 goto out;
3977 }
3978
3979 if (hba->vreg_info.vcc)
3980 icc_level = ufshcd_get_max_icc_level(
3981 hba->vreg_info.vcc->max_uA,
3982 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
3983 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
3984
3985 if (hba->vreg_info.vccq)
3986 icc_level = ufshcd_get_max_icc_level(
3987 hba->vreg_info.vccq->max_uA,
3988 icc_level,
3989 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
3990
3991 if (hba->vreg_info.vccq2)
3992 icc_level = ufshcd_get_max_icc_level(
3993 hba->vreg_info.vccq2->max_uA,
3994 icc_level,
3995 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
3996out:
3997 return icc_level;
3998}
3999
4000static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4001{
4002 int ret;
4003 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4004 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4005
4006 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4007 if (ret) {
4008 dev_err(hba->dev,
4009 "%s: Failed reading power descriptor.len = %d ret = %d",
4010 __func__, buff_len, ret);
4011 return;
4012 }
4013
4014 hba->init_prefetch_data.icc_level =
4015 ufshcd_find_max_sup_active_icc_level(hba,
4016 desc_buf, buff_len);
4017 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4018 __func__, hba->init_prefetch_data.icc_level);
4019
4020 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4021 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
4022 &hba->init_prefetch_data.icc_level);
4023
4024 if (ret)
4025 dev_err(hba->dev,
4026 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4027 __func__, hba->init_prefetch_data.icc_level , ret);
4028
4029}
4030
2a8fa600
SJ		 4031/**
4032 * ufshcd_scsi_add_wlus - Adds required W-LUs
4033 * @hba: per-adapter instance
4034 *
4035 * UFS device specification requires the UFS devices to support 4 well known
4036 * logical units:
4037 * "REPORT_LUNS" (address: 01h)
4038 * "UFS Device" (address: 50h)
4039 * "RPMB" (address: 44h)
4040 * "BOOT" (address: 30h)
4041 * UFS device's power management needs to be controlled by "POWER CONDITION"
4042 * field of SSU (START STOP UNIT) command. But this "power condition" field
4043 * will take effect only when its sent to "UFS device" well known logical unit
4044 * hence we require the scsi_device instance to represent this logical unit in
4045 * order for the UFS host driver to send the SSU command for power management.
4046
4047 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4048 * Block) LU so user space process can control this LU. User space may also
4049 * want to have access to BOOT LU.
4050
4051 * This function adds scsi device instances for each of all well known LUs
4052 * (except "REPORT LUNS" LU).
4053 *
4054 * Returns zero on success (all required W-LUs are added successfully),
4055 * non-zero error value on failure (if failed to add any of the required W-LU).
4056 */
4057static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4058{
4059 int ret = 0;
4060
4061 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4062 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4063 if (IS_ERR(hba->sdev_ufs_device)) {
4064 ret = PTR_ERR(hba->sdev_ufs_device);
4065 hba->sdev_ufs_device = NULL;
4066 goto out;
4067 }
4068
4069 hba->sdev_boot = __scsi_add_device(hba->host, 0, 0,
4070 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
4071 if (IS_ERR(hba->sdev_boot)) {
4072 ret = PTR_ERR(hba->sdev_boot);
4073 hba->sdev_boot = NULL;
4074 goto remove_sdev_ufs_device;
4075 }
4076
4077 hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
4078 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
4079 if (IS_ERR(hba->sdev_rpmb)) {
4080 ret = PTR_ERR(hba->sdev_rpmb);
4081 hba->sdev_rpmb = NULL;
4082 goto remove_sdev_boot;
4083 }
4084 goto out;
4085
4086remove_sdev_boot:
4087 scsi_remove_device(hba->sdev_boot);
4088remove_sdev_ufs_device:
4089 scsi_remove_device(hba->sdev_ufs_device);
4090out:
4091 return ret;
4092}
4093
4094/**
4095 * ufshcd_scsi_remove_wlus - Removes the W-LUs which were added by
4096 * ufshcd_scsi_add_wlus()
4097 * @hba: per-adapter instance
4098 *
4099 */
4100static void ufshcd_scsi_remove_wlus(struct ufs_hba *hba)
4101{
4102 if (hba->sdev_ufs_device) {
4103 scsi_remove_device(hba->sdev_ufs_device);
4104 hba->sdev_ufs_device = NULL;
4105 }
4106
4107 if (hba->sdev_boot) {
4108 scsi_remove_device(hba->sdev_boot);
4109 hba->sdev_boot = NULL;
4110 }
4111
4112 if (hba->sdev_rpmb) {
4113 scsi_remove_device(hba->sdev_rpmb);
4114 hba->sdev_rpmb = NULL;
4115 }
4116}
4117
6ccf44fe 4118/**
1d337ec2
SRT		 4119 * ufshcd_probe_hba - probe hba to detect device and initialize
4120 * @hba: per-adapter instance
4121 *
4122 * Execute link-startup and verify device initialization
6ccf44fe 4123 */
1d337ec2 4124static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 4125{
6ccf44fe
SJ		 4126 int ret;
4127
4128 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 4129 if (ret)
4130 goto out;
4131
57d104c1
SJ		 4132 /* UniPro link is active now */
4133 ufshcd_set_link_active(hba);
d3e89bac 4134
5a0b0cb9
SRT		 4135 ret = ufshcd_verify_dev_init(hba);
4136 if (ret)
4137 goto out;
68078d5c
DR		 4138
4139 ret = ufshcd_complete_dev_init(hba);
4140 if (ret)
4141 goto out;
5a0b0cb9 4142
57d104c1
SJ		 4143 /* UFS device is also active now */
4144 ufshcd_set_ufs_dev_active(hba);
66ec6d59 4145 ufshcd_force_reset_auto_bkops(hba);
3441da7d 4146 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 4147 hba->wlun_dev_clr_ua = true;
4148
7eb584db
DR		 4149 if (ufshcd_get_max_pwr_mode(hba)) {
4150 dev_err(hba->dev,
4151 "%s: Failed getting max supported power mode\n",
4152 __func__);
4153 } else {
4154 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
4155 if (ret)
4156 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
4157 __func__, ret);
4158 }
57d104c1
SJ		 4159
4160 /*
4161 * If we are in error handling context or in power management callbacks
4162 * context, no need to scan the host
4163 */
4164 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4165 bool flag;
4166
4167 /* clear any previous UFS device information */
4168 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
4169 if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4170 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
4171 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 4172
3a4bf06d
YG		 4173 if (!hba->is_init_prefetch)
4174 ufshcd_init_icc_levels(hba);
4175
2a8fa600
SJ		 4176 /* Add required well known logical units to scsi mid layer */
4177 if (ufshcd_scsi_add_wlus(hba))
4178 goto out;
4179
3441da7d
SRT		 4180 scsi_scan_host(hba->host);
4181 pm_runtime_put_sync(hba->dev);
4182 }
3a4bf06d
YG		 4183
4184 if (!hba->is_init_prefetch)
4185 hba->is_init_prefetch = true;
4186
856b3483
ST		 4187 /* Resume devfreq after UFS device is detected */
4188 if (ufshcd_is_clkscaling_enabled(hba))
4189 devfreq_resume_device(hba->devfreq);
4190
5a0b0cb9 4191out:
1d337ec2
SRT		 4192 /*
4193 * If we failed to initialize the device or the device is not
4194 * present, turn off the power/clocks etc.
4195 */
57d104c1
SJ		 4196 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4197 pm_runtime_put_sync(hba->dev);
1d337ec2 4198 ufshcd_hba_exit(hba);
57d104c1 4199 }
1d337ec2
SRT		 4200
4201 return ret;
4202}
4203
4204/**
4205 * ufshcd_async_scan - asynchronous execution for probing hba
4206 * @data: data pointer to pass to this function
4207 * @cookie: cookie data
4208 */
4209static void ufshcd_async_scan(void *data, async_cookie_t cookie)
4210{
4211 struct ufs_hba *hba = (struct ufs_hba *)data;
4212
4213 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 4214}
4215
7a3e97b0
SY		 4216static struct scsi_host_template ufshcd_driver_template = {
4217 .module = THIS_MODULE,
4218 .name = UFSHCD,
4219 .proc_name = UFSHCD,
4220 .queuecommand = ufshcd_queuecommand,
4221 .slave_alloc = ufshcd_slave_alloc,
eeda4749 4222 .slave_configure = ufshcd_slave_configure,
7a3e97b0 4223 .slave_destroy = ufshcd_slave_destroy,
4264fd61 4224 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 4225 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 4226 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
4227 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 4228 .this_id = -1,
4229 .sg_tablesize = SG_ALL,
4230 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
4231 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 4232 .max_host_blocked = 1,
2ecb204d 4233 .use_blk_tags = 1,
7a3e97b0
SY		 4234};
4235
57d104c1
SJ		 4236static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
4237 int ua)
4238{
4239 int ret = 0;
4240 struct regulator *reg = vreg->reg;
4241 const char *name = vreg->name;
4242
4243 BUG_ON(!vreg);
4244
4245 ret = regulator_set_optimum_mode(reg, ua);
4246 if (ret >= 0) {
4247 /*
4248 * regulator_set_optimum_mode() returns new regulator
4249 * mode upon success.
4250 */
4251 ret = 0;
4252 } else {
4253 dev_err(dev, "%s: %s set optimum mode(ua=%d) failed, err=%d\n",
4254 __func__, name, ua, ret);
4255 }
4256
4257 return ret;
4258}
4259
4260static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
4261 struct ufs_vreg *vreg)
4262{
4263 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
4264}
4265
4266static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
4267 struct ufs_vreg *vreg)
4268{
4269 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
4270}
4271
aa497613
SRT		 4272static int ufshcd_config_vreg(struct device *dev,
4273 struct ufs_vreg *vreg, bool on)
4274{
4275 int ret = 0;
4276 struct regulator *reg = vreg->reg;
4277 const char *name = vreg->name;
4278 int min_uV, uA_load;
4279
4280 BUG_ON(!vreg);
4281
4282 if (regulator_count_voltages(reg) > 0) {
4283 min_uV = on ? vreg->min_uV : 0;
4284 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
4285 if (ret) {
4286 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
4287 __func__, name, ret);
4288 goto out;
4289 }
4290
4291 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 4292 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
4293 if (ret)
aa497613 4294 goto out;
aa497613
SRT		 4295 }
4296out:
4297 return ret;
4298}
4299
4300static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
4301{
4302 int ret = 0;
4303
4304 if (!vreg || vreg->enabled)
4305 goto out;
4306
4307 ret = ufshcd_config_vreg(dev, vreg, true);
4308 if (!ret)
4309 ret = regulator_enable(vreg->reg);
4310
4311 if (!ret)
4312 vreg->enabled = true;
4313 else
4314 dev_err(dev, "%s: %s enable failed, err=%d\n",
4315 __func__, vreg->name, ret);
4316out:
4317 return ret;
4318}
4319
4320static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
4321{
4322 int ret = 0;
4323
4324 if (!vreg || !vreg->enabled)
4325 goto out;
4326
4327 ret = regulator_disable(vreg->reg);
4328
4329 if (!ret) {
4330 /* ignore errors on applying disable config */
4331 ufshcd_config_vreg(dev, vreg, false);
4332 vreg->enabled = false;
4333 } else {
4334 dev_err(dev, "%s: %s disable failed, err=%d\n",
4335 __func__, vreg->name, ret);
4336 }
4337out:
4338 return ret;
4339}
4340
4341static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
4342{
4343 int ret = 0;
4344 struct device *dev = hba->dev;
4345 struct ufs_vreg_info *info = &hba->vreg_info;
4346
4347 if (!info)
4348 goto out;
4349
4350 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
4351 if (ret)
4352 goto out;
4353
4354 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
4355 if (ret)
4356 goto out;
4357
4358 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
4359 if (ret)
4360 goto out;
4361
4362out:
4363 if (ret) {
4364 ufshcd_toggle_vreg(dev, info->vccq2, false);
4365 ufshcd_toggle_vreg(dev, info->vccq, false);
4366 ufshcd_toggle_vreg(dev, info->vcc, false);
4367 }
4368 return ret;
4369}
4370
6a771a65
RS		 4371static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
4372{
4373 struct ufs_vreg_info *info = &hba->vreg_info;
4374
4375 if (info)
4376 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
4377
4378 return 0;
4379}
4380
aa497613
SRT		 4381static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
4382{
4383 int ret = 0;
4384
4385 if (!vreg)
4386 goto out;
4387
4388 vreg->reg = devm_regulator_get(dev, vreg->name);
4389 if (IS_ERR(vreg->reg)) {
4390 ret = PTR_ERR(vreg->reg);
4391 dev_err(dev, "%s: %s get failed, err=%d\n",
4392 __func__, vreg->name, ret);
4393 }
4394out:
4395 return ret;
4396}
4397
4398static int ufshcd_init_vreg(struct ufs_hba *hba)
4399{
4400 int ret = 0;
4401 struct device *dev = hba->dev;
4402 struct ufs_vreg_info *info = &hba->vreg_info;
4403
4404 if (!info)
4405 goto out;
4406
4407 ret = ufshcd_get_vreg(dev, info->vcc);
4408 if (ret)
4409 goto out;
4410
4411 ret = ufshcd_get_vreg(dev, info->vccq);
4412 if (ret)
4413 goto out;
4414
4415 ret = ufshcd_get_vreg(dev, info->vccq2);
4416out:
4417 return ret;
4418}
4419
6a771a65
RS		 4420static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
4421{
4422 struct ufs_vreg_info *info = &hba->vreg_info;
4423
4424 if (info)
4425 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
4426
4427 return 0;
4428}
4429
57d104c1
SJ		 4430static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
4431 bool skip_ref_clk)
c6e79dac
SRT		 4432{
4433 int ret = 0;
4434 struct ufs_clk_info *clki;
4435 struct list_head *head = &hba->clk_list_head;
1ab27c9c 4436 unsigned long flags;
c6e79dac
SRT		 4437
4438 if (!head || list_empty(head))
4439 goto out;
4440
4441 list_for_each_entry(clki, head, list) {
4442 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 4443 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
4444 continue;
4445
c6e79dac
SRT		 4446 if (on && !clki->enabled) {
4447 ret = clk_prepare_enable(clki->clk);
4448 if (ret) {
4449 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
4450 __func__, clki->name, ret);
4451 goto out;
4452 }
4453 } else if (!on && clki->enabled) {
4454 clk_disable_unprepare(clki->clk);
4455 }
4456 clki->enabled = on;
4457 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
4458 clki->name, on ? "en" : "dis");
4459 }
4460 }
1ab27c9c
ST		 4461
4462 if (hba->vops && hba->vops->setup_clocks)
4463 ret = hba->vops->setup_clocks(hba, on);
c6e79dac
SRT		 4464out:
4465 if (ret) {
4466 list_for_each_entry(clki, head, list) {
4467 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
4468 clk_disable_unprepare(clki->clk);
4469 }
1ab27c9c
ST		 4470 } else if (!ret && on) {
4471 spin_lock_irqsave(hba->host->host_lock, flags);
4472 hba->clk_gating.state = CLKS_ON;
4473 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT		 4474 }
4475 return ret;
4476}
4477
57d104c1
SJ		 4478static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
4479{
4480 return __ufshcd_setup_clocks(hba, on, false);
4481}
4482
c6e79dac
SRT		 4483static int ufshcd_init_clocks(struct ufs_hba *hba)
4484{
4485 int ret = 0;
4486 struct ufs_clk_info *clki;
4487 struct device *dev = hba->dev;
4488 struct list_head *head = &hba->clk_list_head;
4489
4490 if (!head || list_empty(head))
4491 goto out;
4492
4493 list_for_each_entry(clki, head, list) {
4494 if (!clki->name)
4495 continue;
4496
4497 clki->clk = devm_clk_get(dev, clki->name);
4498 if (IS_ERR(clki->clk)) {
4499 ret = PTR_ERR(clki->clk);
4500 dev_err(dev, "%s: %s clk get failed, %d\n",
4501 __func__, clki->name, ret);
4502 goto out;
4503 }
4504
4505 if (clki->max_freq) {
4506 ret = clk_set_rate(clki->clk, clki->max_freq);
4507 if (ret) {
4508 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
4509 __func__, clki->name,
4510 clki->max_freq, ret);
4511 goto out;
4512 }
856b3483 4513 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 4514 }
4515 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
4516 clki->name, clk_get_rate(clki->clk));
4517 }
4518out:
4519 return ret;
4520}
4521
5c0c28a8
SRT		 4522static int ufshcd_variant_hba_init(struct ufs_hba *hba)
4523{
4524 int err = 0;
4525
4526 if (!hba->vops)
4527 goto out;
4528
4529 if (hba->vops->init) {
4530 err = hba->vops->init(hba);
4531 if (err)
4532 goto out;
4533 }
4534
5c0c28a8
SRT		 4535 if (hba->vops->setup_regulators) {
4536 err = hba->vops->setup_regulators(hba, true);
4537 if (err)
1ab27c9c 4538 goto out_exit;
5c0c28a8
SRT		 4539 }
4540
4541 goto out;
4542
5c0c28a8
SRT		 4543out_exit:
4544 if (hba->vops->exit)
4545 hba->vops->exit(hba);
4546out:
4547 if (err)
4548 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
4549 __func__, hba->vops ? hba->vops->name : "", err);
4550 return err;
4551}
4552
4553static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
4554{
4555 if (!hba->vops)
4556 return;
4557
4558 if (hba->vops->setup_clocks)
4559 hba->vops->setup_clocks(hba, false);
4560
4561 if (hba->vops->setup_regulators)
4562 hba->vops->setup_regulators(hba, false);
4563
4564 if (hba->vops->exit)
4565 hba->vops->exit(hba);
4566}
4567
aa497613
SRT		 4568static int ufshcd_hba_init(struct ufs_hba *hba)
4569{
4570 int err;
4571
6a771a65
RS		 4572 /*
4573 * Handle host controller power separately from the UFS device power
4574 * rails as it will help controlling the UFS host controller power
4575 * collapse easily which is different than UFS device power collapse.
4576 * Also, enable the host controller power before we go ahead with rest
4577 * of the initialization here.
4578 */
4579 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 4580 if (err)
4581 goto out;
4582
6a771a65 4583 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 4584 if (err)
4585 goto out;
4586
6a771a65
RS		 4587 err = ufshcd_init_clocks(hba);
4588 if (err)
4589 goto out_disable_hba_vreg;
4590
4591 err = ufshcd_setup_clocks(hba, true);
4592 if (err)
4593 goto out_disable_hba_vreg;
4594
c6e79dac
SRT		 4595 err = ufshcd_init_vreg(hba);
4596 if (err)
4597 goto out_disable_clks;
4598
4599 err = ufshcd_setup_vreg(hba, true);
4600 if (err)
4601 goto out_disable_clks;
4602
aa497613
SRT		 4603 err = ufshcd_variant_hba_init(hba);
4604 if (err)
4605 goto out_disable_vreg;
4606
1d337ec2 4607 hba->is_powered = true;
aa497613
SRT		 4608 goto out;
4609
4610out_disable_vreg:
4611 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 4612out_disable_clks:
4613 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 4614out_disable_hba_vreg:
4615 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 4616out:
4617 return err;
4618}
4619
4620static void ufshcd_hba_exit(struct ufs_hba *hba)
4621{
1d337ec2
SRT		 4622 if (hba->is_powered) {
4623 ufshcd_variant_hba_exit(hba);
4624 ufshcd_setup_vreg(hba, false);
4625 ufshcd_setup_clocks(hba, false);
4626 ufshcd_setup_hba_vreg(hba, false);
4627 hba->is_powered = false;
4628 }
aa497613
SRT		 4629}
4630
57d104c1
SJ		 4631static int
4632ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
4633{
4634 unsigned char cmd[6] = {REQUEST_SENSE,
4635 0,
4636 0,
4637 0,
4638 SCSI_SENSE_BUFFERSIZE,
4639 0};
4640 char *buffer;
4641 int ret;
4642
4643 buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4644 if (!buffer) {
4645 ret = -ENOMEM;
4646 goto out;
4647 }
4648
4649 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
4650 SCSI_SENSE_BUFFERSIZE, NULL,
4651 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
4652 if (ret)
4653 pr_err("%s: failed with err %d\n", __func__, ret);
4654
4655 kfree(buffer);
4656out:
4657 return ret;
4658}
4659
4660/**
4661 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
4662 * power mode
4663 * @hba: per adapter instance
4664 * @pwr_mode: device power mode to set
4665 *
4666 * Returns 0 if requested power mode is set successfully
4667 * Returns non-zero if failed to set the requested power mode
4668 */
4669static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
4670 enum ufs_dev_pwr_mode pwr_mode)
4671{
4672 unsigned char cmd[6] = { START_STOP };
4673 struct scsi_sense_hdr sshdr;
4674 struct scsi_device *sdp = hba->sdev_ufs_device;
4675 int ret;
4676
4677 if (!sdp || !scsi_device_online(sdp))
4678 return -ENODEV;
4679
4680 /*
4681 * If scsi commands fail, the scsi mid-layer schedules scsi error-
4682 * handling, which would wait for host to be resumed. Since we know
4683 * we are functional while we are here, skip host resume in error
4684 * handling context.
4685 */
4686 hba->host->eh_noresume = 1;
4687 if (hba->wlun_dev_clr_ua) {
4688 ret = ufshcd_send_request_sense(hba, sdp);
4689 if (ret)
4690 goto out;
4691 /* Unit attention condition is cleared now */
4692 hba->wlun_dev_clr_ua = false;
4693 }
4694
4695 cmd[4] = pwr_mode << 4;
4696
4697 /*
4698 * Current function would be generally called from the power management
4699 * callbacks hence set the REQ_PM flag so that it doesn't resume the
4700 * already suspended childs.
4701 */
4702 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
4703 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
4704 if (ret) {
4705 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 4706 "START_STOP failed for power mode: %d, result %x\n",
4707 pwr_mode, ret);
57d104c1 4708 if (driver_byte(ret) & DRIVER_SENSE) {
d811b848
HR		 4709 scsi_show_sense_hdr(sdp, NULL, &sshdr);
4710 scsi_show_extd_sense(sdp, NULL, sshdr.asc, sshdr.ascq);
57d104c1
SJ		 4711 }
4712 }
4713
4714 if (!ret)
4715 hba->curr_dev_pwr_mode = pwr_mode;
4716out:
4717 hba->host->eh_noresume = 0;
4718 return ret;
4719}
4720
4721static int ufshcd_link_state_transition(struct ufs_hba *hba,
4722 enum uic_link_state req_link_state,
4723 int check_for_bkops)
4724{
4725 int ret = 0;
4726
4727 if (req_link_state == hba->uic_link_state)
4728 return 0;
4729
4730 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
4731 ret = ufshcd_uic_hibern8_enter(hba);
4732 if (!ret)
4733 ufshcd_set_link_hibern8(hba);
4734 else
4735 goto out;
4736 }
4737 /*
4738 * If autobkops is enabled, link can't be turned off because
4739 * turning off the link would also turn off the device.
4740 */
4741 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
4742 (!check_for_bkops || (check_for_bkops &&
4743 !hba->auto_bkops_enabled))) {
4744 /*
4745 * Change controller state to "reset state" which
4746 * should also put the link in off/reset state
4747 */
4748 ufshcd_hba_stop(hba);
4749 /*
4750 * TODO: Check if we need any delay to make sure that
4751 * controller is reset
4752 */
4753 ufshcd_set_link_off(hba);
4754 }
4755
4756out:
4757 return ret;
4758}
4759
4760static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
4761{
4762 /*
4763 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
4764 * power.
4765 *
4766 * If UFS device and link is in OFF state, all power supplies (VCC,
4767 * VCCQ, VCCQ2) can be turned off if power on write protect is not
4768 * required. If UFS link is inactive (Hibern8 or OFF state) and device
4769 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
4770 *
4771 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
4772 * in low power state which would save some power.
4773 */
4774 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4775 !hba->dev_info.is_lu_power_on_wp) {
4776 ufshcd_setup_vreg(hba, false);
4777 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4778 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4779 if (!ufshcd_is_link_active(hba)) {
4780 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4781 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
4782 }
4783 }
4784}
4785
4786static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
4787{
4788 int ret = 0;
4789
4790 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4791 !hba->dev_info.is_lu_power_on_wp) {
4792 ret = ufshcd_setup_vreg(hba, true);
4793 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4794 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
4795 if (!ret && !ufshcd_is_link_active(hba)) {
4796 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
4797 if (ret)
4798 goto vcc_disable;
4799 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
4800 if (ret)
4801 goto vccq_lpm;
4802 }
4803 }
4804 goto out;
4805
4806vccq_lpm:
4807 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4808vcc_disable:
4809 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4810out:
4811 return ret;
4812}
4813
4814static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
4815{
4816 if (ufshcd_is_link_off(hba))
4817 ufshcd_setup_hba_vreg(hba, false);
4818}
4819
4820static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
4821{
4822 if (ufshcd_is_link_off(hba))
4823 ufshcd_setup_hba_vreg(hba, true);
4824}
4825
7a3e97b0 4826/**
57d104c1 4827 * ufshcd_suspend - helper function for suspend operations
3b1d0580 4828 * @hba: per adapter instance
57d104c1
SJ		 4829 * @pm_op: desired low power operation type
4830 *
4831 * This function will try to put the UFS device and link into low power
4832 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
4833 * (System PM level).
4834 *
4835 * If this function is called during shutdown, it will make sure that
4836 * both UFS device and UFS link is powered off.
7a3e97b0 4837 *
57d104c1
SJ		 4838 * NOTE: UFS device & link must be active before we enter in this function.
4839 *
4840 * Returns 0 for success and non-zero for failure
7a3e97b0 4841 */
57d104c1 4842static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 4843{
57d104c1
SJ		 4844 int ret = 0;
4845 enum ufs_pm_level pm_lvl;
4846 enum ufs_dev_pwr_mode req_dev_pwr_mode;
4847 enum uic_link_state req_link_state;
4848
4849 hba->pm_op_in_progress = 1;
4850 if (!ufshcd_is_shutdown_pm(pm_op)) {
4851 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
4852 hba->rpm_lvl : hba->spm_lvl;
4853 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
4854 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
4855 } else {
4856 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
4857 req_link_state = UIC_LINK_OFF_STATE;
4858 }
4859
7a3e97b0 4860 /*
57d104c1
SJ		 4861 * If we can't transition into any of the low power modes
4862 * just gate the clocks.
7a3e97b0 4863 */
1ab27c9c
ST		 4864 ufshcd_hold(hba, false);
4865 hba->clk_gating.is_suspended = true;
4866
57d104c1
SJ		 4867 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
4868 req_link_state == UIC_LINK_ACTIVE_STATE) {
4869 goto disable_clks;
4870 }
7a3e97b0 4871
57d104c1
SJ		 4872 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
4873 (req_link_state == hba->uic_link_state))
4874 goto out;
4875
4876 /* UFS device & link must be active before we enter in this function */
4877 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
4878 ret = -EINVAL;
4879 goto out;
4880 }
4881
4882 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 4883 if (ufshcd_can_autobkops_during_suspend(hba)) {
4884 /*
4885 * The device is idle with no requests in the queue,
4886 * allow background operations if bkops status shows
4887 * that performance might be impacted.
4888 */
4889 ret = ufshcd_urgent_bkops(hba);
4890 if (ret)
4891 goto enable_gating;
4892 } else {
4893 /* make sure that auto bkops is disabled */
4894 ufshcd_disable_auto_bkops(hba);
4895 }
57d104c1
SJ		 4896 }
4897
4898 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
4899 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
4900 !ufshcd_is_runtime_pm(pm_op))) {
4901 /* ensure that bkops is disabled */
4902 ufshcd_disable_auto_bkops(hba);
4903 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
4904 if (ret)
1ab27c9c 4905 goto enable_gating;
57d104c1
SJ		 4906 }
4907
4908 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
4909 if (ret)
4910 goto set_dev_active;
4911
4912 ufshcd_vreg_set_lpm(hba);
4913
4914disable_clks:
856b3483
ST		 4915 /*
4916 * The clock scaling needs access to controller registers. Hence, Wait
4917 * for pending clock scaling work to be done before clocks are
4918 * turned off.
4919 */
4920 if (ufshcd_is_clkscaling_enabled(hba)) {
4921 devfreq_suspend_device(hba->devfreq);
4922 hba->clk_scaling.window_start_t = 0;
4923 }
57d104c1
SJ		 4924 /*
4925 * Call vendor specific suspend callback. As these callbacks may access
4926 * vendor specific host controller register space call them before the
4927 * host clocks are ON.
4928 */
4929 if (hba->vops && hba->vops->suspend) {
4930 ret = hba->vops->suspend(hba, pm_op);
4931 if (ret)
4932 goto set_link_active;
4933 }
4934
4935 if (hba->vops && hba->vops->setup_clocks) {
4936 ret = hba->vops->setup_clocks(hba, false);
4937 if (ret)
4938 goto vops_resume;
4939 }
4940
4941 if (!ufshcd_is_link_active(hba))
4942 ufshcd_setup_clocks(hba, false);
4943 else
4944 /* If link is active, device ref_clk can't be switched off */
4945 __ufshcd_setup_clocks(hba, false, true);
4946
1ab27c9c 4947 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ		 4948 /*
4949 * Disable the host irq as host controller as there won't be any
4950 * host controller trasanction expected till resume.
4951 */
4952 ufshcd_disable_irq(hba);
4953 /* Put the host controller in low power mode if possible */
4954 ufshcd_hba_vreg_set_lpm(hba);
4955 goto out;
4956
4957vops_resume:
4958 if (hba->vops && hba->vops->resume)
4959 hba->vops->resume(hba, pm_op);
4960set_link_active:
4961 ufshcd_vreg_set_hpm(hba);
4962 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
4963 ufshcd_set_link_active(hba);
4964 else if (ufshcd_is_link_off(hba))
4965 ufshcd_host_reset_and_restore(hba);
4966set_dev_active:
4967 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
4968 ufshcd_disable_auto_bkops(hba);
1ab27c9c
ST		 4969enable_gating:
4970 hba->clk_gating.is_suspended = false;
4971 ufshcd_release(hba);
57d104c1
SJ		 4972out:
4973 hba->pm_op_in_progress = 0;
4974 return ret;
7a3e97b0
SY		 4975}
4976
4977/**
57d104c1 4978 * ufshcd_resume - helper function for resume operations
3b1d0580 4979 * @hba: per adapter instance
57d104c1 4980 * @pm_op: runtime PM or system PM
7a3e97b0 4981 *
57d104c1
SJ		 4982 * This function basically brings the UFS device, UniPro link and controller
4983 * to active state.
4984 *
4985 * Returns 0 for success and non-zero for failure
7a3e97b0 4986 */
57d104c1 4987static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 4988{
57d104c1
SJ		 4989 int ret;
4990 enum uic_link_state old_link_state;
4991
4992 hba->pm_op_in_progress = 1;
4993 old_link_state = hba->uic_link_state;
4994
4995 ufshcd_hba_vreg_set_hpm(hba);
4996 /* Make sure clocks are enabled before accessing controller */
4997 ret = ufshcd_setup_clocks(hba, true);
4998 if (ret)
4999 goto out;
5000
57d104c1
SJ		 5001 /* enable the host irq as host controller would be active soon */
5002 ret = ufshcd_enable_irq(hba);
5003 if (ret)
5004 goto disable_irq_and_vops_clks;
5005
5006 ret = ufshcd_vreg_set_hpm(hba);
5007 if (ret)
5008 goto disable_irq_and_vops_clks;
5009
7a3e97b0 5010 /*
57d104c1
SJ		 5011 * Call vendor specific resume callback. As these callbacks may access
5012 * vendor specific host controller register space call them when the
5013 * host clocks are ON.
7a3e97b0 5014 */
57d104c1
SJ		 5015 if (hba->vops && hba->vops->resume) {
5016 ret = hba->vops->resume(hba, pm_op);
5017 if (ret)
5018 goto disable_vreg;
5019 }
5020
5021 if (ufshcd_is_link_hibern8(hba)) {
5022 ret = ufshcd_uic_hibern8_exit(hba);
5023 if (!ret)
5024 ufshcd_set_link_active(hba);
5025 else
5026 goto vendor_suspend;
5027 } else if (ufshcd_is_link_off(hba)) {
5028 ret = ufshcd_host_reset_and_restore(hba);
5029 /*
5030 * ufshcd_host_reset_and_restore() should have already
5031 * set the link state as active
5032 */
5033 if (ret || !ufshcd_is_link_active(hba))
5034 goto vendor_suspend;
5035 }
5036
5037 if (!ufshcd_is_ufs_dev_active(hba)) {
5038 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
5039 if (ret)
5040 goto set_old_link_state;
5041 }
5042
374a246e
SJ		 5043 /*
5044 * If BKOPs operations are urgently needed at this moment then
5045 * keep auto-bkops enabled or else disable it.
5046 */
5047 ufshcd_urgent_bkops(hba);
1ab27c9c
ST		 5048 hba->clk_gating.is_suspended = false;
5049
856b3483
ST		 5050 if (ufshcd_is_clkscaling_enabled(hba))
5051 devfreq_resume_device(hba->devfreq);
5052
1ab27c9c
ST		 5053 /* Schedule clock gating in case of no access to UFS device yet */
5054 ufshcd_release(hba);
57d104c1
SJ		 5055 goto out;
5056
5057set_old_link_state:
5058 ufshcd_link_state_transition(hba, old_link_state, 0);
5059vendor_suspend:
5060 if (hba->vops && hba->vops->suspend)
5061 hba->vops->suspend(hba, pm_op);
5062disable_vreg:
5063 ufshcd_vreg_set_lpm(hba);
5064disable_irq_and_vops_clks:
5065 ufshcd_disable_irq(hba);
57d104c1
SJ		 5066 ufshcd_setup_clocks(hba, false);
5067out:
5068 hba->pm_op_in_progress = 0;
5069 return ret;
5070}
5071
5072/**
5073 * ufshcd_system_suspend - system suspend routine
5074 * @hba: per adapter instance
5075 * @pm_op: runtime PM or system PM
5076 *
5077 * Check the description of ufshcd_suspend() function for more details.
5078 *
5079 * Returns 0 for success and non-zero for failure
5080 */
5081int ufshcd_system_suspend(struct ufs_hba *hba)
5082{
5083 int ret = 0;
5084
5085 if (!hba || !hba->is_powered)
5086 goto out;
5087
5088 if (pm_runtime_suspended(hba->dev)) {
5089 if (hba->rpm_lvl == hba->spm_lvl)
5090 /*
5091 * There is possibility that device may still be in
5092 * active state during the runtime suspend.
5093 */
5094 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
5095 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
5096 goto out;
5097
5098 /*
5099 * UFS device and/or UFS link low power states during runtime
5100 * suspend seems to be different than what is expected during
5101 * system suspend. Hence runtime resume the devic & link and
5102 * let the system suspend low power states to take effect.
5103 * TODO: If resume takes longer time, we might have optimize
5104 * it in future by not resuming everything if possible.
5105 */
5106 ret = ufshcd_runtime_resume(hba);
5107 if (ret)
5108 goto out;
5109 }
5110
5111 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
5112out:
e785060e
DR		 5113 if (!ret)
5114 hba->is_sys_suspended = true;
57d104c1
SJ		 5115 return ret;
5116}
5117EXPORT_SYMBOL(ufshcd_system_suspend);
5118
5119/**
5120 * ufshcd_system_resume - system resume routine
5121 * @hba: per adapter instance
5122 *
5123 * Returns 0 for success and non-zero for failure
5124 */
7a3e97b0 5125
57d104c1
SJ		 5126int ufshcd_system_resume(struct ufs_hba *hba)
5127{
5128 if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
5129 /*
5130 * Let the runtime resume take care of resuming
5131 * if runtime suspended.
5132 */
5133 return 0;
5134
5135 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 5136}
57d104c1 5137EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 5138
57d104c1
SJ		 5139/**
5140 * ufshcd_runtime_suspend - runtime suspend routine
5141 * @hba: per adapter instance
5142 *
5143 * Check the description of ufshcd_suspend() function for more details.
5144 *
5145 * Returns 0 for success and non-zero for failure
5146 */
66ec6d59
SRT		 5147int ufshcd_runtime_suspend(struct ufs_hba *hba)
5148{
57d104c1 5149 if (!hba || !hba->is_powered)
66ec6d59
SRT		 5150 return 0;
5151
57d104c1 5152 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 5153}
5154EXPORT_SYMBOL(ufshcd_runtime_suspend);
5155
57d104c1
SJ		 5156/**
5157 * ufshcd_runtime_resume - runtime resume routine
5158 * @hba: per adapter instance
5159 *
5160 * This function basically brings the UFS device, UniPro link and controller
5161 * to active state. Following operations are done in this function:
5162 *
5163 * 1. Turn on all the controller related clocks
5164 * 2. Bring the UniPro link out of Hibernate state
5165 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
5166 * to active state.
5167 * 4. If auto-bkops is enabled on the device, disable it.
5168 *
5169 * So following would be the possible power state after this function return
5170 * successfully:
5171 * S1: UFS device in Active state with VCC rail ON
5172 * UniPro link in Active state
5173 * All the UFS/UniPro controller clocks are ON
5174 *
5175 * Returns 0 for success and non-zero for failure
5176 */
66ec6d59
SRT		 5177int ufshcd_runtime_resume(struct ufs_hba *hba)
5178{
57d104c1 5179 if (!hba || !hba->is_powered)
66ec6d59 5180 return 0;
57d104c1
SJ		 5181 else
5182 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 5183}
5184EXPORT_SYMBOL(ufshcd_runtime_resume);
5185
5186int ufshcd_runtime_idle(struct ufs_hba *hba)
5187{
5188 return 0;
5189}
5190EXPORT_SYMBOL(ufshcd_runtime_idle);
5191
57d104c1
SJ		 5192/**
5193 * ufshcd_shutdown - shutdown routine
5194 * @hba: per adapter instance
5195 *
5196 * This function would power off both UFS device and UFS link.
5197 *
5198 * Returns 0 always to allow force shutdown even in case of errors.
5199 */
5200int ufshcd_shutdown(struct ufs_hba *hba)
5201{
5202 int ret = 0;
5203
5204 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
5205 goto out;
5206
5207 if (pm_runtime_suspended(hba->dev)) {
5208 ret = ufshcd_runtime_resume(hba);
5209 if (ret)
5210 goto out;
5211 }
5212
5213 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
5214out:
5215 if (ret)
5216 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
5217 /* allow force shutdown even in case of errors */
5218 return 0;
5219}
5220EXPORT_SYMBOL(ufshcd_shutdown);
5221
7a3e97b0 5222/**
3b1d0580 5223 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 5224 * data structure memory
3b1d0580 5225 * @hba - per adapter instance
7a3e97b0 5226 */
3b1d0580 5227void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 5228{
cfdf9c91 5229 scsi_remove_host(hba->host);
2a8fa600 5230 ufshcd_scsi_remove_wlus(hba);
7a3e97b0 5231 /* disable interrupts */
2fbd009b 5232 ufshcd_disable_intr(hba, hba->intr_mask);
7a3e97b0 5233 ufshcd_hba_stop(hba);
7a3e97b0 5234
7a3e97b0 5235 scsi_host_put(hba->host);
5c0c28a8 5236
1ab27c9c 5237 ufshcd_exit_clk_gating(hba);
856b3483
ST		 5238 if (ufshcd_is_clkscaling_enabled(hba))
5239 devfreq_remove_device(hba->devfreq);
aa497613 5240 ufshcd_hba_exit(hba);
3b1d0580
VH		 5241}
5242EXPORT_SYMBOL_GPL(ufshcd_remove);
5243
ca3d7bf9
AM		 5244/**
5245 * ufshcd_set_dma_mask - Set dma mask based on the controller
5246 * addressing capability
5247 * @hba: per adapter instance
5248 *
5249 * Returns 0 for success, non-zero for failure
5250 */
5251static int ufshcd_set_dma_mask(struct ufs_hba *hba)
5252{
5253 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
5254 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
5255 return 0;
5256 }
5257 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
5258}
5259
7a3e97b0 5260/**
5c0c28a8 5261 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 5262 * @dev: pointer to device handle
5263 * @hba_handle: driver private handle
7a3e97b0
SY		 5264 * Returns 0 on success, non-zero value on failure
5265 */
5c0c28a8 5266int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 5267{
5268 struct Scsi_Host *host;
5269 struct ufs_hba *hba;
5c0c28a8 5270 int err = 0;
7a3e97b0 5271
3b1d0580
VH		 5272 if (!dev) {
5273 dev_err(dev,
5274 "Invalid memory reference for dev is NULL\n");
5275 err = -ENODEV;
7a3e97b0
SY		 5276 goto out_error;
5277 }
5278
7a3e97b0
SY		 5279 host = scsi_host_alloc(&ufshcd_driver_template,
5280 sizeof(struct ufs_hba));
5281 if (!host) {
3b1d0580 5282 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 5283 err = -ENOMEM;
3b1d0580 5284 goto out_error;
7a3e97b0
SY		 5285 }
5286 hba = shost_priv(host);
7a3e97b0 5287 hba->host = host;
3b1d0580 5288 hba->dev = dev;
5c0c28a8
SRT		 5289 *hba_handle = hba;
5290
5291out_error:
5292 return err;
5293}
5294EXPORT_SYMBOL(ufshcd_alloc_host);
5295
856b3483
ST		 5296static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
5297{
5298 int ret = 0;
5299 struct ufs_clk_info *clki;
5300 struct list_head *head = &hba->clk_list_head;
5301
5302 if (!head || list_empty(head))
5303 goto out;
5304
5305 list_for_each_entry(clki, head, list) {
5306 if (!IS_ERR_OR_NULL(clki->clk)) {
5307 if (scale_up && clki->max_freq) {
5308 if (clki->curr_freq == clki->max_freq)
5309 continue;
5310 ret = clk_set_rate(clki->clk, clki->max_freq);
5311 if (ret) {
5312 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5313 __func__, clki->name,
5314 clki->max_freq, ret);
5315 break;
5316 }
5317 clki->curr_freq = clki->max_freq;
5318
5319 } else if (!scale_up && clki->min_freq) {
5320 if (clki->curr_freq == clki->min_freq)
5321 continue;
5322 ret = clk_set_rate(clki->clk, clki->min_freq);
5323 if (ret) {
5324 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5325 __func__, clki->name,
5326 clki->min_freq, ret);
5327 break;
5328 }
5329 clki->curr_freq = clki->min_freq;
5330 }
5331 }
5332 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
5333 clki->name, clk_get_rate(clki->clk));
5334 }
5335 if (hba->vops->clk_scale_notify)
5336 hba->vops->clk_scale_notify(hba);
5337out:
5338 return ret;
5339}
5340
5341static int ufshcd_devfreq_target(struct device *dev,
5342 unsigned long *freq, u32 flags)
5343{
5344 int err = 0;
5345 struct ufs_hba *hba = dev_get_drvdata(dev);
5346
5347 if (!ufshcd_is_clkscaling_enabled(hba))
5348 return -EINVAL;
5349
5350 if (*freq == UINT_MAX)
5351 err = ufshcd_scale_clks(hba, true);
5352 else if (*freq == 0)
5353 err = ufshcd_scale_clks(hba, false);
5354
5355 return err;
5356}
5357
5358static int ufshcd_devfreq_get_dev_status(struct device *dev,
5359 struct devfreq_dev_status *stat)
5360{
5361 struct ufs_hba *hba = dev_get_drvdata(dev);
5362 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
5363 unsigned long flags;
5364
5365 if (!ufshcd_is_clkscaling_enabled(hba))
5366 return -EINVAL;
5367
5368 memset(stat, 0, sizeof(*stat));
5369
5370 spin_lock_irqsave(hba->host->host_lock, flags);
5371 if (!scaling->window_start_t)
5372 goto start_window;
5373
5374 if (scaling->is_busy_started)
5375 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
5376 scaling->busy_start_t));
5377
5378 stat->total_time = jiffies_to_usecs((long)jiffies -
5379 (long)scaling->window_start_t);
5380 stat->busy_time = scaling->tot_busy_t;
5381start_window:
5382 scaling->window_start_t = jiffies;
5383 scaling->tot_busy_t = 0;
5384
5385 if (hba->outstanding_reqs) {
5386 scaling->busy_start_t = ktime_get();
5387 scaling->is_busy_started = true;
5388 } else {
5389 scaling->busy_start_t = ktime_set(0, 0);
5390 scaling->is_busy_started = false;
5391 }
5392 spin_unlock_irqrestore(hba->host->host_lock, flags);
5393 return 0;
5394}
5395
5396static struct devfreq_dev_profile ufs_devfreq_profile = {
5397 .polling_ms = 100,
5398 .target = ufshcd_devfreq_target,
5399 .get_dev_status = ufshcd_devfreq_get_dev_status,
5400};
5401
5c0c28a8
SRT		 5402/**
5403 * ufshcd_init - Driver initialization routine
5404 * @hba: per-adapter instance
5405 * @mmio_base: base register address
5406 * @irq: Interrupt line of device
5407 * Returns 0 on success, non-zero value on failure
5408 */
5409int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
5410{
5411 int err;
5412 struct Scsi_Host *host = hba->host;
5413 struct device *dev = hba->dev;
5414
5415 if (!mmio_base) {
5416 dev_err(hba->dev,
5417 "Invalid memory reference for mmio_base is NULL\n");
5418 err = -ENODEV;
5419 goto out_error;
5420 }
5421
3b1d0580
VH		 5422 hba->mmio_base = mmio_base;
5423 hba->irq = irq;
7a3e97b0 5424
aa497613 5425 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 5426 if (err)
5427 goto out_error;
5428
7a3e97b0
SY		 5429 /* Read capabilities registers */
5430 ufshcd_hba_capabilities(hba);
5431
5432 /* Get UFS version supported by the controller */
5433 hba->ufs_version = ufshcd_get_ufs_version(hba);
5434
2fbd009b
SJ		 5435 /* Get Interrupt bit mask per version */
5436 hba->intr_mask = ufshcd_get_intr_mask(hba);
5437
ca3d7bf9
AM		 5438 err = ufshcd_set_dma_mask(hba);
5439 if (err) {
5440 dev_err(hba->dev, "set dma mask failed\n");
5441 goto out_disable;
5442 }
5443
7a3e97b0
SY		 5444 /* Allocate memory for host memory space */
5445 err = ufshcd_memory_alloc(hba);
5446 if (err) {
3b1d0580
VH		 5447 dev_err(hba->dev, "Memory allocation failed\n");
5448 goto out_disable;
7a3e97b0
SY		 5449 }
5450
5451 /* Configure LRB */
5452 ufshcd_host_memory_configure(hba);
5453
5454 host->can_queue = hba->nutrs;
5455 host->cmd_per_lun = hba->nutrs;
5456 host->max_id = UFSHCD_MAX_ID;
0ce147d4 5457 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 5458 host->max_channel = UFSHCD_MAX_CHANNEL;
5459 host->unique_id = host->host_no;
5460 host->max_cmd_len = MAX_CDB_SIZE;
5461
7eb584db
DR		 5462 hba->max_pwr_info.is_valid = false;
5463
7a3e97b0 5464 /* Initailize wait queue for task management */
e2933132
SRT		 5465 init_waitqueue_head(&hba->tm_wq);
5466 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 5467
5468 /* Initialize work queues */
e8e7f271 5469 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 5470 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 5471
6ccf44fe
SJ		 5472 /* Initialize UIC command mutex */
5473 mutex_init(&hba->uic_cmd_mutex);
5474
5a0b0cb9
SRT		 5475 /* Initialize mutex for device management commands */
5476 mutex_init(&hba->dev_cmd.lock);
5477
5478 /* Initialize device management tag acquire wait queue */
5479 init_waitqueue_head(&hba->dev_cmd.tag_wq);
5480
1ab27c9c 5481 ufshcd_init_clk_gating(hba);
7a3e97b0 5482 /* IRQ registration */
2953f850 5483 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 5484 if (err) {
3b1d0580 5485 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 5486 goto exit_gating;
57d104c1
SJ		 5487 } else {
5488 hba->is_irq_enabled = true;
7a3e97b0
SY		 5489 }
5490
5491 /* Enable SCSI tag mapping */
5492 err = scsi_init_shared_tag_map(host, host->can_queue);
5493 if (err) {
3b1d0580 5494 dev_err(hba->dev, "init shared queue failed\n");
1ab27c9c 5495 goto exit_gating;
7a3e97b0
SY		 5496 }
5497
3b1d0580 5498 err = scsi_add_host(host, hba->dev);
7a3e97b0 5499 if (err) {
3b1d0580 5500 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 5501 goto exit_gating;
7a3e97b0
SY		 5502 }
5503
6ccf44fe
SJ		 5504 /* Host controller enable */
5505 err = ufshcd_hba_enable(hba);
7a3e97b0 5506 if (err) {
6ccf44fe 5507 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 5508 goto out_remove_scsi_host;
7a3e97b0 5509 }
6ccf44fe 5510
856b3483
ST		 5511 if (ufshcd_is_clkscaling_enabled(hba)) {
5512 hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
5513 "simple_ondemand", NULL);
5514 if (IS_ERR(hba->devfreq)) {
5515 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
5516 PTR_ERR(hba->devfreq));
5517 goto out_remove_scsi_host;
5518 }
5519 /* Suspend devfreq until the UFS device is detected */
5520 devfreq_suspend_device(hba->devfreq);
5521 hba->clk_scaling.window_start_t = 0;
5522 }
5523
62694735
SRT		 5524 /* Hold auto suspend until async scan completes */
5525 pm_runtime_get_sync(dev);
5526
57d104c1
SJ		 5527 /*
5528 * The device-initialize-sequence hasn't been invoked yet.
5529 * Set the device to power-off state
5530 */
5531 ufshcd_set_ufs_dev_poweroff(hba);
5532
6ccf44fe
SJ		 5533 async_schedule(ufshcd_async_scan, hba);
5534
7a3e97b0
SY		 5535 return 0;
5536
3b1d0580
VH		 5537out_remove_scsi_host:
5538 scsi_remove_host(hba->host);
1ab27c9c
ST		 5539exit_gating:
5540 ufshcd_exit_clk_gating(hba);
3b1d0580 5541out_disable:
57d104c1 5542 hba->is_irq_enabled = false;
3b1d0580 5543 scsi_host_put(host);
aa497613 5544 ufshcd_hba_exit(hba);
3b1d0580
VH		 5545out_error:
5546 return err;
5547}
5548EXPORT_SYMBOL_GPL(ufshcd_init);
5549
3b1d0580
VH		 5550MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
5551MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 5552MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 5553MODULE_LICENSE("GPL");
5554MODULE_VERSION(UFSHCD_DRIVER_VERSION);
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