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scsi: ufs: use an enum for host capabilities
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
ad448378 44#include <linux/bitfield.h>
e0eca63e 45#include "ufshcd.h"
c58ab7aa 46#include "ufs_quirks.h"
53b3d9c3 47#include "unipro.h"
cbb6813e 48#include "ufs-sysfs.h"
df032bf2 49#include "ufs_bsg.h"
7a3e97b0 50
7ff5ab47
SJ		 51#define CREATE_TRACE_POINTS
52#include <trace/events/ufs.h>
53
2fbd009b
SJ		 54#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
55 UTP_TASK_REQ_COMPL |\
56 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 57/* UIC command timeout, unit: ms */
58#define UIC_CMD_TIMEOUT 500
2fbd009b 59
5a0b0cb9
SRT		 60/* NOP OUT retries waiting for NOP IN response */
61#define NOP_OUT_RETRIES 10
62/* Timeout after 30 msecs if NOP OUT hangs without response */
63#define NOP_OUT_TIMEOUT 30 /* msecs */
64
68078d5c 65/* Query request retries */
10fe5888 66#define QUERY_REQ_RETRIES 3
68078d5c 67/* Query request timeout */
10fe5888 68#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 69
e2933132
SRT		 70/* Task management command timeout */
71#define TM_CMD_TIMEOUT 100 /* msecs */
72
64238fbd
YG		 73/* maximum number of retries for a general UIC command */
74#define UFS_UIC_COMMAND_RETRIES 3
75
1d337ec2
SRT		 76/* maximum number of link-startup retries */
77#define DME_LINKSTARTUP_RETRIES 3
78
87d0b4a6
YG		 79/* Maximum retries for Hibern8 enter */
80#define UIC_HIBERN8_ENTER_RETRIES 3
81
1d337ec2
SRT		 82/* maximum number of reset retries before giving up */
83#define MAX_HOST_RESET_RETRIES 5
84
68078d5c
DR		 85/* Expose the flag value from utp_upiu_query.value */
86#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
87
7d568652
SJ		 88/* Interrupt aggregation default timeout, unit: 40us */
89#define INT_AGGR_DEF_TO 0x02
90
49615ba1
SC		 91/* default delay of autosuspend: 2000 ms */
92#define RPM_AUTOSUSPEND_DELAY_MS 2000
93
09f17791
CG		 94/* Default value of wait time before gating device ref clock */
95#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
96
aa497613
SRT		 97#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
98 ({ \
99 int _ret; \
100 if (_on) \
101 _ret = ufshcd_enable_vreg(_dev, _vreg); \
102 else \
103 _ret = ufshcd_disable_vreg(_dev, _vreg); \
104 _ret; \
105 })
106
ba80917d
TW		 107#define ufshcd_hex_dump(prefix_str, buf, len) do { \
108 size_t __len = (len); \
109 print_hex_dump(KERN_ERR, prefix_str, \
110 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
111 16, 4, buf, __len, false); \
112} while (0)
113
114int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
115 const char *prefix)
116{
d6724756
MG		 117 u32 *regs;
118 size_t pos;
119
120 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
121 return -EINVAL;
ba80917d 122
cddaebaf 123 regs = kzalloc(len, GFP_ATOMIC);
ba80917d
TW		 124 if (!regs)
125 return -ENOMEM;
126
d6724756
MG		 127 for (pos = 0; pos < len; pos += 4)
128 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
129
ba80917d
TW		 130 ufshcd_hex_dump(prefix, regs, len);
131 kfree(regs);
132
133 return 0;
134}
135EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 136
7a3e97b0
SY		 137enum {
138 UFSHCD_MAX_CHANNEL = 0,
139 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 140 UFSHCD_CMD_PER_LUN = 32,
141 UFSHCD_CAN_QUEUE = 32,
142};
143
144/* UFSHCD states */
145enum {
7a3e97b0
SY		 146 UFSHCD_STATE_RESET,
147 UFSHCD_STATE_ERROR,
3441da7d 148 UFSHCD_STATE_OPERATIONAL,
141f8165 149 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 150};
151
152/* UFSHCD error handling flags */
153enum {
154 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 155};
156
e8e7f271
SRT		 157/* UFSHCD UIC layer error flags */
158enum {
159 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 160 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
161 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
162 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
163 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
164 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 165};
166
3441da7d 167#define ufshcd_set_eh_in_progress(h) \
9c490d2d 168 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 169#define ufshcd_eh_in_progress(h) \
9c490d2d 170 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 171#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 172 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 173
57d104c1
SJ		 174#define ufshcd_set_ufs_dev_active(h) \
175 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
176#define ufshcd_set_ufs_dev_sleep(h) \
177 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
178#define ufshcd_set_ufs_dev_poweroff(h) \
179 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
180#define ufshcd_is_ufs_dev_active(h) \
181 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
182#define ufshcd_is_ufs_dev_sleep(h) \
183 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
184#define ufshcd_is_ufs_dev_poweroff(h) \
185 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
186
cbb6813e 187struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
57d104c1
SJ		 188 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
189 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
190 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
191 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
192 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
193 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
194};
195
196static inline enum ufs_dev_pwr_mode
197ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
198{
199 return ufs_pm_lvl_states[lvl].dev_state;
200}
201
202static inline enum uic_link_state
203ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
204{
205 return ufs_pm_lvl_states[lvl].link_state;
206}
207
0c8f7586
SJ		 208static inline enum ufs_pm_level
209ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
210 enum uic_link_state link_state)
211{
212 enum ufs_pm_level lvl;
213
214 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
215 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
216 (ufs_pm_lvl_states[lvl].link_state == link_state))
217 return lvl;
218 }
219
220 /* if no match found, return the level 0 */
221 return UFS_PM_LVL_0;
222}
223
56d4a186
SJ		 224static struct ufs_dev_fix ufs_fixups[] = {
225 /* UFS cards deviations table */
226 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
227 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
56d4a186
SJ		 228 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
229 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
56d4a186
SJ		 230 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
231 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
232 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
233 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
234 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
235 UFS_DEVICE_QUIRK_PA_TACTIVATE),
236 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
237 UFS_DEVICE_QUIRK_PA_TACTIVATE),
56d4a186
SJ		 238 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
239 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
8e4829c6
WL		 240 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
241 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
56d4a186
SJ		 242
243 END_FIX
244};
245
9333d775 246static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
3441da7d 247static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 248static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 249static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 250static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2 251static void ufshcd_hba_exit(struct ufs_hba *hba);
1b9e2141 252static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
1ab27c9c
ST		 253static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
254 bool skip_ref_clk);
255static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
1ab27c9c 256static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 257static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 258static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 259static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
260static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 261static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 262static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 263static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 264static int ufshcd_change_power_mode(struct ufs_hba *hba,
265 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 266static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
267{
268 return tag >= 0 && tag < hba->nutrs;
269}
57d104c1 270
5231d38c 271static inline void ufshcd_enable_irq(struct ufs_hba *hba)
57d104c1 272{
57d104c1 273 if (!hba->is_irq_enabled) {
5231d38c 274 enable_irq(hba->irq);
57d104c1
SJ		 275 hba->is_irq_enabled = true;
276 }
57d104c1
SJ		 277}
278
279static inline void ufshcd_disable_irq(struct ufs_hba *hba)
280{
281 if (hba->is_irq_enabled) {
5231d38c 282 disable_irq(hba->irq);
57d104c1
SJ		 283 hba->is_irq_enabled = false;
284 }
285}
3441da7d 286
38135535
SJ		 287static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
288{
289 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
290 scsi_unblock_requests(hba->host);
291}
292
293static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
294{
295 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
296 scsi_block_requests(hba->host);
297}
298
6667e6d9
OS		 299static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
300 const char *str)
301{
302 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
303
304 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
305}
306
307static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
308 const char *str)
309{
310 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
311
312 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
313}
314
315static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
316 const char *str)
317{
6667e6d9 318 int off = (int)tag - hba->nutrs;
391e388f 319 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
6667e6d9 320
391e388f
CH		 321 trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
322 &descp->input_param1);
6667e6d9
OS		 323}
324
1a07f2d9
LS		 325static void ufshcd_add_command_trace(struct ufs_hba *hba,
326 unsigned int tag, const char *str)
327{
328 sector_t lba = -1;
329 u8 opcode = 0;
330 u32 intr, doorbell;
e7c3b379 331 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
e4d2add7 332 struct scsi_cmnd *cmd = lrbp->cmd;
1a07f2d9
LS		 333 int transfer_len = -1;
334
e7c3b379
OS		 335 if (!trace_ufshcd_command_enabled()) {
336 /* trace UPIU W/O tracing command */
e4d2add7 337 if (cmd)
e7c3b379 338 ufshcd_add_cmd_upiu_trace(hba, tag, str);
1a07f2d9 339 return;
e7c3b379 340 }
1a07f2d9 341
e4d2add7 342 if (cmd) { /* data phase exists */
e7c3b379
OS		 343 /* trace UPIU also */
344 ufshcd_add_cmd_upiu_trace(hba, tag, str);
e4d2add7 345 opcode = cmd->cmnd[0];
1a07f2d9
LS		 346 if ((opcode == READ_10) || (opcode == WRITE_10)) {
347 /*
348 * Currently we only fully trace read(10) and write(10)
349 * commands
350 */
e4d2add7
BVA		 351 if (cmd->request && cmd->request->bio)
352 lba = cmd->request->bio->bi_iter.bi_sector;
1a07f2d9
LS		 353 transfer_len = be32_to_cpu(
354 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
355 }
356 }
357
358 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
359 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
360 trace_ufshcd_command(dev_name(hba->dev), str, tag,
361 doorbell, transfer_len, intr, lba, opcode);
362}
363
ff8e20c6
DR		 364static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
365{
366 struct ufs_clk_info *clki;
367 struct list_head *head = &hba->clk_list_head;
368
566ec9ad 369 if (list_empty(head))
ff8e20c6
DR		 370 return;
371
372 list_for_each_entry(clki, head, list) {
373 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
374 clki->max_freq)
375 dev_err(hba->dev, "clk: %s, rate: %u\n",
376 clki->name, clki->curr_freq);
377 }
378}
379
48d5b973
SC		 380static void ufshcd_print_err_hist(struct ufs_hba *hba,
381 struct ufs_err_reg_hist *err_hist,
382 char *err_name)
ff8e20c6
DR		 383{
384 int i;
27752647 385 bool found = false;
ff8e20c6 386
48d5b973
SC		 387 for (i = 0; i < UFS_ERR_REG_HIST_LENGTH; i++) {
388 int p = (i + err_hist->pos) % UFS_ERR_REG_HIST_LENGTH;
ff8e20c6 389
645728a6 390 if (err_hist->tstamp[p] == 0)
ff8e20c6 391 continue;
c5397f13 392 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
ff8e20c6 393 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
27752647 394 found = true;
ff8e20c6 395 }
27752647
SC		 396
397 if (!found)
fd1fb4d5 398 dev_err(hba->dev, "No record of %s\n", err_name);
ff8e20c6
DR		 399}
400
66cc820f
DR		 401static void ufshcd_print_host_regs(struct ufs_hba *hba)
402{
ba80917d 403 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
66cc820f
DR		 404 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
405 hba->ufs_version, hba->capabilities);
406 dev_err(hba->dev,
407 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
408 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 409 dev_err(hba->dev,
410 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
411 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
412 hba->ufs_stats.hibern8_exit_cnt);
413
48d5b973
SC		 414 ufshcd_print_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
415 ufshcd_print_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
416 ufshcd_print_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
417 ufshcd_print_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
418 ufshcd_print_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
d3c615bf
SC		 419 ufshcd_print_err_hist(hba, &hba->ufs_stats.auto_hibern8_err,
420 "auto_hibern8_err");
8808b4e9
SC		 421 ufshcd_print_err_hist(hba, &hba->ufs_stats.fatal_err, "fatal_err");
422 ufshcd_print_err_hist(hba, &hba->ufs_stats.link_startup_err,
423 "link_startup_fail");
424 ufshcd_print_err_hist(hba, &hba->ufs_stats.resume_err, "resume_fail");
425 ufshcd_print_err_hist(hba, &hba->ufs_stats.suspend_err,
426 "suspend_fail");
427 ufshcd_print_err_hist(hba, &hba->ufs_stats.dev_reset, "dev_reset");
428 ufshcd_print_err_hist(hba, &hba->ufs_stats.host_reset, "host_reset");
429 ufshcd_print_err_hist(hba, &hba->ufs_stats.task_abort, "task_abort");
ff8e20c6
DR		 430
431 ufshcd_print_clk_freqs(hba);
432
7c486d91 433 ufshcd_vops_dbg_register_dump(hba);
66cc820f
DR		 434}
435
436static
437void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
438{
439 struct ufshcd_lrb *lrbp;
7fabb77b 440 int prdt_length;
66cc820f
DR		 441 int tag;
442
443 for_each_set_bit(tag, &bitmap, hba->nutrs) {
444 lrbp = &hba->lrb[tag];
445
ff8e20c6
DR		 446 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
447 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 448 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
449 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 450 dev_err(hba->dev,
451 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
452 tag, (u64)lrbp->utrd_dma_addr);
453
66cc820f
DR		 454 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
455 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 456 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
457 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 458 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
459 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 460 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
461 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 462 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
463 sizeof(struct utp_upiu_rsp));
66cc820f 464
7fabb77b
GB		 465 prdt_length = le16_to_cpu(
466 lrbp->utr_descriptor_ptr->prd_table_length);
467 dev_err(hba->dev,
468 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
469 tag, prdt_length,
470 (u64)lrbp->ucd_prdt_dma_addr);
471
472 if (pr_prdt)
66cc820f 473 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 474 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 475 }
476}
477
478static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
479{
66cc820f
DR		 480 int tag;
481
482 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 483 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
484
66cc820f 485 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 486 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 487 }
488}
489
6ba65588
GB		 490static void ufshcd_print_host_state(struct ufs_hba *hba)
491{
492 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
7252a360
BVA		 493 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
494 hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 495 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
496 hba->saved_err, hba->saved_uic_err);
497 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
498 hba->curr_dev_pwr_mode, hba->uic_link_state);
499 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
500 hba->pm_op_in_progress, hba->is_sys_suspended);
501 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
502 hba->auto_bkops_enabled, hba->host->host_self_blocked);
503 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
504 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
505 hba->eh_flags, hba->req_abort_count);
506 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
507 hba->capabilities, hba->caps);
508 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
509 hba->dev_quirks);
510}
511
ff8e20c6
DR		 512/**
513 * ufshcd_print_pwr_info - print power params as saved in hba
514 * power info
515 * @hba: per-adapter instance
516 */
517static void ufshcd_print_pwr_info(struct ufs_hba *hba)
518{
519 static const char * const names[] = {
520 "INVALID MODE",
521 "FAST MODE",
522 "SLOW_MODE",
523 "INVALID MODE",
524 "FASTAUTO_MODE",
525 "SLOWAUTO_MODE",
526 "INVALID MODE",
527 };
528
529 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
530 __func__,
531 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
532 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
533 names[hba->pwr_info.pwr_rx],
534 names[hba->pwr_info.pwr_tx],
535 hba->pwr_info.hs_rate);
536}
537
5a0b0cb9
SRT		 538/*
539 * ufshcd_wait_for_register - wait for register value to change
540 * @hba - per-adapter interface
541 * @reg - mmio register offset
542 * @mask - mask to apply to read register value
543 * @val - wait condition
544 * @interval_us - polling interval in microsecs
545 * @timeout_ms - timeout in millisecs
596585a2 546 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 547 *
548 * Returns -ETIMEDOUT on error, zero on success
549 */
596585a2
YG		 550int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
551 u32 val, unsigned long interval_us,
552 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 553{
554 int err = 0;
555 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
556
557 /* ignore bits that we don't intend to wait on */
558 val = val & mask;
559
560 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 561 if (can_sleep)
562 usleep_range(interval_us, interval_us + 50);
563 else
564 udelay(interval_us);
5a0b0cb9
SRT		 565 if (time_after(jiffies, timeout)) {
566 if ((ufshcd_readl(hba, reg) & mask) != val)
567 err = -ETIMEDOUT;
568 break;
569 }
570 }
571
572 return err;
573}
574
2fbd009b
SJ		 575/**
576 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 577 * @hba: Pointer to adapter instance
2fbd009b
SJ		 578 *
579 * Returns interrupt bit mask per version
580 */
581static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
582{
c01848c6
YG		 583 u32 intr_mask = 0;
584
585 switch (hba->ufs_version) {
586 case UFSHCI_VERSION_10:
587 intr_mask = INTERRUPT_MASK_ALL_VER_10;
588 break;
c01848c6
YG		 589 case UFSHCI_VERSION_11:
590 case UFSHCI_VERSION_20:
591 intr_mask = INTERRUPT_MASK_ALL_VER_11;
592 break;
c01848c6
YG		 593 case UFSHCI_VERSION_21:
594 default:
595 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 596 break;
c01848c6
YG		 597 }
598
599 return intr_mask;
2fbd009b
SJ		 600}
601
7a3e97b0
SY		 602/**
603 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 604 * @hba: Pointer to adapter instance
7a3e97b0
SY		 605 *
606 * Returns UFSHCI version supported by the controller
607 */
608static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
609{
0263bcd0
YG		 610 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
611 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 612
b873a275 613 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 614}
615
616/**
617 * ufshcd_is_device_present - Check if any device connected to
618 * the host controller
5c0c28a8 619 * @hba: pointer to adapter instance
7a3e97b0 620 *
c9e6010b 621 * Returns true if device present, false if no device detected
7a3e97b0 622 */
c9e6010b 623static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 624{
5c0c28a8 625 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 626 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 627}
628
629/**
630 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 631 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 632 *
633 * This function is used to get the OCS field from UTRD
634 * Returns the OCS field in the UTRD
635 */
636static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
637{
e8c8e82a 638 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 639}
640
7a3e97b0
SY		 641/**
642 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
643 * @hba: per adapter instance
644 * @pos: position of the bit to be cleared
645 */
646static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
647{
49200199 648 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
1399c5b0
AA		 649}
650
651/**
652 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
653 * @hba: per adapter instance
654 * @pos: position of the bit to be cleared
655 */
656static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
657{
49200199 658 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 659}
660
a48353f6
YG		 661/**
662 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
663 * @hba: per adapter instance
664 * @tag: position of the bit to be cleared
665 */
666static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
667{
668 __clear_bit(tag, &hba->outstanding_reqs);
669}
670
7a3e97b0
SY		 671/**
672 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
673 * @reg: Register value of host controller status
674 *
675 * Returns integer, 0 on Success and positive value if failed
676 */
677static inline int ufshcd_get_lists_status(u32 reg)
678{
6cf16115 679 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 680}
681
682/**
683 * ufshcd_get_uic_cmd_result - Get the UIC command result
684 * @hba: Pointer to adapter instance
685 *
686 * This function gets the result of UIC command completion
687 * Returns 0 on success, non zero value on error
688 */
689static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
690{
b873a275 691 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 692 MASK_UIC_COMMAND_RESULT;
693}
694
12b4fdb4
SJ		 695/**
696 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
697 * @hba: Pointer to adapter instance
698 *
699 * This function gets UIC command argument3
700 * Returns 0 on success, non zero value on error
701 */
702static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
703{
704 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
705}
706
7a3e97b0 707/**
5a0b0cb9 708 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 709 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 710 */
711static inline int
5a0b0cb9 712ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 713{
5a0b0cb9 714 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 715}
716
717/**
718 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
719 * @ucd_rsp_ptr: pointer to response UPIU
720 *
721 * This function gets the response status and scsi_status from response UPIU
722 * Returns the response result code.
723 */
724static inline int
725ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
726{
727 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
728}
729
1c2623c5
SJ		 730/*
731 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
732 * from response UPIU
733 * @ucd_rsp_ptr: pointer to response UPIU
734 *
735 * Return the data segment length.
736 */
737static inline unsigned int
738ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
739{
740 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
741 MASK_RSP_UPIU_DATA_SEG_LEN;
742}
743
66ec6d59
SRT		 744/**
745 * ufshcd_is_exception_event - Check if the device raised an exception event
746 * @ucd_rsp_ptr: pointer to response UPIU
747 *
748 * The function checks if the device raised an exception event indicated in
749 * the Device Information field of response UPIU.
750 *
751 * Returns true if exception is raised, false otherwise.
752 */
753static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
754{
755 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
756 MASK_RSP_EXCEPTION_EVENT ? true : false;
757}
758
7a3e97b0 759/**
7d568652 760 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 761 * @hba: per adapter instance
7a3e97b0
SY		 762 */
763static inline void
7d568652 764ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 765{
7d568652
SJ		 766 ufshcd_writel(hba, INT_AGGR_ENABLE |
767 INT_AGGR_COUNTER_AND_TIMER_RESET,
768 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
769}
770
771/**
772 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
773 * @hba: per adapter instance
774 * @cnt: Interrupt aggregation counter threshold
775 * @tmout: Interrupt aggregation timeout value
776 */
777static inline void
778ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
779{
780 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
781 INT_AGGR_COUNTER_THLD_VAL(cnt) |
782 INT_AGGR_TIMEOUT_VAL(tmout),
783 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 784}
785
b852190e
YG		 786/**
787 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
788 * @hba: per adapter instance
789 */
790static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
791{
792 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
793}
794
7a3e97b0
SY		 795/**
796 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
797 * When run-stop registers are set to 1, it indicates the
798 * host controller that it can process the requests
799 * @hba: per adapter instance
800 */
801static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
802{
b873a275
SJ		 803 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
804 REG_UTP_TASK_REQ_LIST_RUN_STOP);
805 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
806 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 807}
808
7a3e97b0
SY		 809/**
810 * ufshcd_hba_start - Start controller initialization sequence
811 * @hba: per adapter instance
812 */
813static inline void ufshcd_hba_start(struct ufs_hba *hba)
814{
b873a275 815 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 816}
817
818/**
819 * ufshcd_is_hba_active - Get controller state
820 * @hba: per adapter instance
821 *
c9e6010b 822 * Returns false if controller is active, true otherwise
7a3e97b0 823 */
c9e6010b 824static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 825{
4a8eec2b
TK		 826 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
827 ? false : true;
7a3e97b0
SY		 828}
829
37113106
YG		 830u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
831{
832 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
833 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
834 (hba->ufs_version == UFSHCI_VERSION_11))
835 return UFS_UNIPRO_VER_1_41;
836 else
837 return UFS_UNIPRO_VER_1_6;
838}
839EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
840
841static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
842{
843 /*
844 * If both host and device support UniPro ver1.6 or later, PA layer
845 * parameters tuning happens during link startup itself.
846 *
847 * We can manually tune PA layer parameters if either host or device
848 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
849 * logic simple, we will only do manual tuning if local unipro version
850 * doesn't support ver1.6 or later.
851 */
852 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
853 return true;
854 else
855 return false;
856}
857
a3cd5ec5
SJ		 858static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
859{
860 int ret = 0;
861 struct ufs_clk_info *clki;
862 struct list_head *head = &hba->clk_list_head;
863 ktime_t start = ktime_get();
864 bool clk_state_changed = false;
865
566ec9ad 866 if (list_empty(head))
a3cd5ec5
SJ		 867 goto out;
868
869 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
870 if (ret)
871 return ret;
872
873 list_for_each_entry(clki, head, list) {
874 if (!IS_ERR_OR_NULL(clki->clk)) {
875 if (scale_up && clki->max_freq) {
876 if (clki->curr_freq == clki->max_freq)
877 continue;
878
879 clk_state_changed = true;
880 ret = clk_set_rate(clki->clk, clki->max_freq);
881 if (ret) {
882 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
883 __func__, clki->name,
884 clki->max_freq, ret);
885 break;
886 }
887 trace_ufshcd_clk_scaling(dev_name(hba->dev),
888 "scaled up", clki->name,
889 clki->curr_freq,
890 clki->max_freq);
891
892 clki->curr_freq = clki->max_freq;
893
894 } else if (!scale_up && clki->min_freq) {
895 if (clki->curr_freq == clki->min_freq)
896 continue;
897
898 clk_state_changed = true;
899 ret = clk_set_rate(clki->clk, clki->min_freq);
900 if (ret) {
901 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
902 __func__, clki->name,
903 clki->min_freq, ret);
904 break;
905 }
906 trace_ufshcd_clk_scaling(dev_name(hba->dev),
907 "scaled down", clki->name,
908 clki->curr_freq,
909 clki->min_freq);
910 clki->curr_freq = clki->min_freq;
911 }
912 }
913 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
914 clki->name, clk_get_rate(clki->clk));
915 }
916
917 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
918
919out:
920 if (clk_state_changed)
921 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
922 (scale_up ? "up" : "down"),
923 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
924 return ret;
925}
926
927/**
928 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
929 * @hba: per adapter instance
930 * @scale_up: True if scaling up and false if scaling down
931 *
932 * Returns true if scaling is required, false otherwise.
933 */
934static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
935 bool scale_up)
936{
937 struct ufs_clk_info *clki;
938 struct list_head *head = &hba->clk_list_head;
939
566ec9ad 940 if (list_empty(head))
a3cd5ec5
SJ		 941 return false;
942
943 list_for_each_entry(clki, head, list) {
944 if (!IS_ERR_OR_NULL(clki->clk)) {
945 if (scale_up && clki->max_freq) {
946 if (clki->curr_freq == clki->max_freq)
947 continue;
948 return true;
949 } else if (!scale_up && clki->min_freq) {
950 if (clki->curr_freq == clki->min_freq)
951 continue;
952 return true;
953 }
954 }
955 }
956
957 return false;
958}
959
960static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
961 u64 wait_timeout_us)
962{
963 unsigned long flags;
964 int ret = 0;
965 u32 tm_doorbell;
966 u32 tr_doorbell;
967 bool timeout = false, do_last_check = false;
968 ktime_t start;
969
970 ufshcd_hold(hba, false);
971 spin_lock_irqsave(hba->host->host_lock, flags);
972 /*
973 * Wait for all the outstanding tasks/transfer requests.
974 * Verify by checking the doorbell registers are clear.
975 */
976 start = ktime_get();
977 do {
978 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
979 ret = -EBUSY;
980 goto out;
981 }
982
983 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
984 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
985 if (!tm_doorbell && !tr_doorbell) {
986 timeout = false;
987 break;
988 } else if (do_last_check) {
989 break;
990 }
991
992 spin_unlock_irqrestore(hba->host->host_lock, flags);
993 schedule();
994 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
995 wait_timeout_us) {
996 timeout = true;
997 /*
998 * We might have scheduled out for long time so make
999 * sure to check if doorbells are cleared by this time
1000 * or not.
1001 */
1002 do_last_check = true;
1003 }
1004 spin_lock_irqsave(hba->host->host_lock, flags);
1005 } while (tm_doorbell || tr_doorbell);
1006
1007 if (timeout) {
1008 dev_err(hba->dev,
1009 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1010 __func__, tm_doorbell, tr_doorbell);
1011 ret = -EBUSY;
1012 }
1013out:
1014 spin_unlock_irqrestore(hba->host->host_lock, flags);
1015 ufshcd_release(hba);
1016 return ret;
1017}
1018
1019/**
1020 * ufshcd_scale_gear - scale up/down UFS gear
1021 * @hba: per adapter instance
1022 * @scale_up: True for scaling up gear and false for scaling down
1023 *
1024 * Returns 0 for success,
1025 * Returns -EBUSY if scaling can't happen at this time
1026 * Returns non-zero for any other errors
1027 */
1028static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1029{
1030 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1031 int ret = 0;
1032 struct ufs_pa_layer_attr new_pwr_info;
1033
1034 if (scale_up) {
1035 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1036 sizeof(struct ufs_pa_layer_attr));
1037 } else {
1038 memcpy(&new_pwr_info, &hba->pwr_info,
1039 sizeof(struct ufs_pa_layer_attr));
1040
1041 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1042 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1043 /* save the current power mode */
1044 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1045 &hba->pwr_info,
1046 sizeof(struct ufs_pa_layer_attr));
1047
1048 /* scale down gear */
1049 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1050 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1051 }
1052 }
1053
1054 /* check if the power mode needs to be changed or not? */
1055 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1056
1057 if (ret)
1058 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1059 __func__, ret,
1060 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1061 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1062
1063 return ret;
1064}
1065
1066static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1067{
1068 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1069 int ret = 0;
1070 /*
1071 * make sure that there are no outstanding requests when
1072 * clock scaling is in progress
1073 */
38135535 1074 ufshcd_scsi_block_requests(hba);
a3cd5ec5
SJ		 1075 down_write(&hba->clk_scaling_lock);
1076 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1077 ret = -EBUSY;
1078 up_write(&hba->clk_scaling_lock);
38135535 1079 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5
SJ		 1080 }
1081
1082 return ret;
1083}
1084
1085static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1086{
1087 up_write(&hba->clk_scaling_lock);
38135535 1088 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5
SJ		 1089}
1090
1091/**
1092 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1093 * @hba: per adapter instance
1094 * @scale_up: True for scaling up and false for scalin down
1095 *
1096 * Returns 0 for success,
1097 * Returns -EBUSY if scaling can't happen at this time
1098 * Returns non-zero for any other errors
1099 */
1100static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1101{
1102 int ret = 0;
1103
401f1e44
SJ		 1104 /* let's not get into low power until clock scaling is completed */
1105 ufshcd_hold(hba, false);
1106
a3cd5ec5
SJ		 1107 ret = ufshcd_clock_scaling_prepare(hba);
1108 if (ret)
1109 return ret;
1110
1111 /* scale down the gear before scaling down clocks */
1112 if (!scale_up) {
1113 ret = ufshcd_scale_gear(hba, false);
1114 if (ret)
1115 goto out;
1116 }
1117
1118 ret = ufshcd_scale_clks(hba, scale_up);
1119 if (ret) {
1120 if (!scale_up)
1121 ufshcd_scale_gear(hba, true);
1122 goto out;
1123 }
1124
1125 /* scale up the gear after scaling up clocks */
1126 if (scale_up) {
1127 ret = ufshcd_scale_gear(hba, true);
1128 if (ret) {
1129 ufshcd_scale_clks(hba, false);
1130 goto out;
1131 }
1132 }
1133
1134 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1135
1136out:
1137 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1138 ufshcd_release(hba);
a3cd5ec5
SJ		 1139 return ret;
1140}
1141
401f1e44
SJ		 1142static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1143{
1144 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1145 clk_scaling.suspend_work);
1146 unsigned long irq_flags;
1147
1148 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1149 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1150 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1151 return;
1152 }
1153 hba->clk_scaling.is_suspended = true;
1154 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1155
1156 __ufshcd_suspend_clkscaling(hba);
1157}
1158
1159static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1160{
1161 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1162 clk_scaling.resume_work);
1163 unsigned long irq_flags;
1164
1165 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1166 if (!hba->clk_scaling.is_suspended) {
1167 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1168 return;
1169 }
1170 hba->clk_scaling.is_suspended = false;
1171 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1172
1173 devfreq_resume_device(hba->devfreq);
1174}
1175
a3cd5ec5
SJ		 1176static int ufshcd_devfreq_target(struct device *dev,
1177 unsigned long *freq, u32 flags)
1178{
1179 int ret = 0;
1180 struct ufs_hba *hba = dev_get_drvdata(dev);
1181 ktime_t start;
401f1e44 1182 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1183 struct list_head *clk_list = &hba->clk_list_head;
1184 struct ufs_clk_info *clki;
a3cd5ec5
SJ		 1185 unsigned long irq_flags;
1186
1187 if (!ufshcd_is_clkscaling_supported(hba))
1188 return -EINVAL;
1189
a3cd5ec5
SJ		 1190 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1191 if (ufshcd_eh_in_progress(hba)) {
1192 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1193 return 0;
1194 }
1195
401f1e44
SJ		 1196 if (!hba->clk_scaling.active_reqs)
1197 sched_clk_scaling_suspend_work = true;
1198
092b4558
BA		 1199 if (list_empty(clk_list)) {
1200 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1201 goto out;
1202 }
1203
1204 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1205 scale_up = (*freq == clki->max_freq) ? true : false;
401f1e44
SJ		 1206 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1207 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1208 ret = 0;
1209 goto out; /* no state change required */
a3cd5ec5
SJ		 1210 }
1211 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1212
1213 start = ktime_get();
a3cd5ec5
SJ		 1214 ret = ufshcd_devfreq_scale(hba, scale_up);
1215
a3cd5ec5
SJ		 1216 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1217 (scale_up ? "up" : "down"),
1218 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1219
401f1e44
SJ		 1220out:
1221 if (sched_clk_scaling_suspend_work)
1222 queue_work(hba->clk_scaling.workq,
1223 &hba->clk_scaling.suspend_work);
1224
a3cd5ec5
SJ		 1225 return ret;
1226}
1227
7252a360
BVA		 1228static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1229{
1230 int *busy = priv;
1231
1232 WARN_ON_ONCE(reserved);
1233 (*busy)++;
1234 return false;
1235}
1236
1237/* Whether or not any tag is in use by a request that is in progress. */
1238static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1239{
1240 struct request_queue *q = hba->cmd_queue;
1241 int busy = 0;
1242
1243 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1244 return busy;
1245}
a3cd5ec5
SJ		 1246
1247static int ufshcd_devfreq_get_dev_status(struct device *dev,
1248 struct devfreq_dev_status *stat)
1249{
1250 struct ufs_hba *hba = dev_get_drvdata(dev);
1251 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1252 unsigned long flags;
1253
1254 if (!ufshcd_is_clkscaling_supported(hba))
1255 return -EINVAL;
1256
1257 memset(stat, 0, sizeof(*stat));
1258
1259 spin_lock_irqsave(hba->host->host_lock, flags);
1260 if (!scaling->window_start_t)
1261 goto start_window;
1262
1263 if (scaling->is_busy_started)
1264 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1265 scaling->busy_start_t));
1266
1267 stat->total_time = jiffies_to_usecs((long)jiffies -
1268 (long)scaling->window_start_t);
1269 stat->busy_time = scaling->tot_busy_t;
1270start_window:
1271 scaling->window_start_t = jiffies;
1272 scaling->tot_busy_t = 0;
1273
1274 if (hba->outstanding_reqs) {
1275 scaling->busy_start_t = ktime_get();
1276 scaling->is_busy_started = true;
1277 } else {
1278 scaling->busy_start_t = 0;
1279 scaling->is_busy_started = false;
1280 }
1281 spin_unlock_irqrestore(hba->host->host_lock, flags);
1282 return 0;
1283}
1284
1285static struct devfreq_dev_profile ufs_devfreq_profile = {
1286 .polling_ms = 100,
1287 .target = ufshcd_devfreq_target,
1288 .get_dev_status = ufshcd_devfreq_get_dev_status,
1289};
1290
deac444f
BA		 1291static int ufshcd_devfreq_init(struct ufs_hba *hba)
1292{
092b4558
BA		 1293 struct list_head *clk_list = &hba->clk_list_head;
1294 struct ufs_clk_info *clki;
deac444f
BA		 1295 struct devfreq *devfreq;
1296 int ret;
1297
092b4558
BA		 1298 /* Skip devfreq if we don't have any clocks in the list */
1299 if (list_empty(clk_list))
1300 return 0;
1301
1302 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1303 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1304 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1305
1306 devfreq = devfreq_add_device(hba->dev,
deac444f
BA		 1307 &ufs_devfreq_profile,
1308 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1309 NULL);
1310 if (IS_ERR(devfreq)) {
1311 ret = PTR_ERR(devfreq);
1312 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1313
1314 dev_pm_opp_remove(hba->dev, clki->min_freq);
1315 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1316 return ret;
1317 }
1318
1319 hba->devfreq = devfreq;
1320
1321 return 0;
1322}
1323
092b4558
BA		 1324static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1325{
1326 struct list_head *clk_list = &hba->clk_list_head;
1327 struct ufs_clk_info *clki;
1328
1329 if (!hba->devfreq)
1330 return;
1331
1332 devfreq_remove_device(hba->devfreq);
1333 hba->devfreq = NULL;
1334
1335 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1336 dev_pm_opp_remove(hba->dev, clki->min_freq);
1337 dev_pm_opp_remove(hba->dev, clki->max_freq);
1338}
1339
401f1e44
SJ		 1340static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1341{
1342 unsigned long flags;
1343
1344 devfreq_suspend_device(hba->devfreq);
1345 spin_lock_irqsave(hba->host->host_lock, flags);
1346 hba->clk_scaling.window_start_t = 0;
1347 spin_unlock_irqrestore(hba->host->host_lock, flags);
1348}
a3cd5ec5 1349
a508253d
GB		 1350static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1351{
401f1e44
SJ		 1352 unsigned long flags;
1353 bool suspend = false;
1354
fcb0c4b0
ST		 1355 if (!ufshcd_is_clkscaling_supported(hba))
1356 return;
1357
401f1e44
SJ		 1358 spin_lock_irqsave(hba->host->host_lock, flags);
1359 if (!hba->clk_scaling.is_suspended) {
1360 suspend = true;
1361 hba->clk_scaling.is_suspended = true;
1362 }
1363 spin_unlock_irqrestore(hba->host->host_lock, flags);
1364
1365 if (suspend)
1366 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1367}
1368
1369static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1370{
401f1e44
SJ		 1371 unsigned long flags;
1372 bool resume = false;
1373
1374 if (!ufshcd_is_clkscaling_supported(hba))
1375 return;
1376
1377 spin_lock_irqsave(hba->host->host_lock, flags);
1378 if (hba->clk_scaling.is_suspended) {
1379 resume = true;
1380 hba->clk_scaling.is_suspended = false;
1381 }
1382 spin_unlock_irqrestore(hba->host->host_lock, flags);
1383
1384 if (resume)
1385 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1386}
1387
1388static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1389 struct device_attribute *attr, char *buf)
1390{
1391 struct ufs_hba *hba = dev_get_drvdata(dev);
1392
1393 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1394}
1395
1396static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1397 struct device_attribute *attr, const char *buf, size_t count)
1398{
1399 struct ufs_hba *hba = dev_get_drvdata(dev);
1400 u32 value;
1401 int err;
1402
1403 if (kstrtou32(buf, 0, &value))
1404 return -EINVAL;
1405
1406 value = !!value;
1407 if (value == hba->clk_scaling.is_allowed)
1408 goto out;
1409
1410 pm_runtime_get_sync(hba->dev);
1411 ufshcd_hold(hba, false);
1412
401f1e44
SJ		 1413 cancel_work_sync(&hba->clk_scaling.suspend_work);
1414 cancel_work_sync(&hba->clk_scaling.resume_work);
1415
1416 hba->clk_scaling.is_allowed = value;
1417
fcb0c4b0
ST		 1418 if (value) {
1419 ufshcd_resume_clkscaling(hba);
1420 } else {
1421 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1422 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1423 if (err)
1424 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1425 __func__, err);
1426 }
fcb0c4b0
ST		 1427
1428 ufshcd_release(hba);
1429 pm_runtime_put_sync(hba->dev);
1430out:
1431 return count;
a508253d
GB		 1432}
1433
a3cd5ec5
SJ		 1434static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1435{
1436 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1437 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1438 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1439 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1440 hba->clk_scaling.enable_attr.attr.mode = 0644;
1441 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1442 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1443}
1444
1ab27c9c
ST		 1445static void ufshcd_ungate_work(struct work_struct *work)
1446{
1447 int ret;
1448 unsigned long flags;
1449 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1450 clk_gating.ungate_work);
1451
1452 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1453
1454 spin_lock_irqsave(hba->host->host_lock, flags);
1455 if (hba->clk_gating.state == CLKS_ON) {
1456 spin_unlock_irqrestore(hba->host->host_lock, flags);
1457 goto unblock_reqs;
1458 }
1459
1460 spin_unlock_irqrestore(hba->host->host_lock, flags);
1461 ufshcd_setup_clocks(hba, true);
1462
8b0bbf00
SC		 1463 ufshcd_enable_irq(hba);
1464
1ab27c9c
ST		 1465 /* Exit from hibern8 */
1466 if (ufshcd_can_hibern8_during_gating(hba)) {
1467 /* Prevent gating in this path */
1468 hba->clk_gating.is_suspended = true;
1469 if (ufshcd_is_link_hibern8(hba)) {
1470 ret = ufshcd_uic_hibern8_exit(hba);
1471 if (ret)
1472 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1473 __func__, ret);
1474 else
1475 ufshcd_set_link_active(hba);
1476 }
1477 hba->clk_gating.is_suspended = false;
1478 }
1479unblock_reqs:
38135535 1480 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1481}
1482
1483/**
1484 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1485 * Also, exit from hibern8 mode and set the link as active.
1486 * @hba: per adapter instance
1487 * @async: This indicates whether caller should ungate clocks asynchronously.
1488 */
1489int ufshcd_hold(struct ufs_hba *hba, bool async)
1490{
1491 int rc = 0;
1492 unsigned long flags;
1493
1494 if (!ufshcd_is_clkgating_allowed(hba))
1495 goto out;
1ab27c9c
ST		 1496 spin_lock_irqsave(hba->host->host_lock, flags);
1497 hba->clk_gating.active_reqs++;
1498
53c12d0e
YG		 1499 if (ufshcd_eh_in_progress(hba)) {
1500 spin_unlock_irqrestore(hba->host->host_lock, flags);
1501 return 0;
1502 }
1503
856b3483 1504start:
1ab27c9c
ST		 1505 switch (hba->clk_gating.state) {
1506 case CLKS_ON:
f2a785ac
VG		 1507 /*
1508 * Wait for the ungate work to complete if in progress.
1509 * Though the clocks may be in ON state, the link could
1510 * still be in hibner8 state if hibern8 is allowed
1511 * during clock gating.
1512 * Make sure we exit hibern8 state also in addition to
1513 * clocks being ON.
1514 */
1515 if (ufshcd_can_hibern8_during_gating(hba) &&
1516 ufshcd_is_link_hibern8(hba)) {
c63d6099
CG		 1517 if (async) {
1518 rc = -EAGAIN;
1519 hba->clk_gating.active_reqs--;
1520 break;
1521 }
f2a785ac
VG		 1522 spin_unlock_irqrestore(hba->host->host_lock, flags);
1523 flush_work(&hba->clk_gating.ungate_work);
1524 spin_lock_irqsave(hba->host->host_lock, flags);
1525 goto start;
1526 }
1ab27c9c
ST		 1527 break;
1528 case REQ_CLKS_OFF:
1529 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1530 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1531 trace_ufshcd_clk_gating(dev_name(hba->dev),
1532 hba->clk_gating.state);
1ab27c9c
ST		 1533 break;
1534 }
1535 /*
9c490d2d 1536 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1537 * currently running. Hence, fall through to cancel gating
1538 * work and to enable clocks.
1539 */
30eb2e4c 1540 /* fallthrough */
1ab27c9c 1541 case CLKS_OFF:
38135535 1542 ufshcd_scsi_block_requests(hba);
1ab27c9c 1543 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47
SJ		 1544 trace_ufshcd_clk_gating(dev_name(hba->dev),
1545 hba->clk_gating.state);
10e5e375
VV		 1546 queue_work(hba->clk_gating.clk_gating_workq,
1547 &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1548 /*
1549 * fall through to check if we should wait for this
1550 * work to be done or not.
1551 */
30eb2e4c 1552 /* fallthrough */
1ab27c9c
ST		 1553 case REQ_CLKS_ON:
1554 if (async) {
1555 rc = -EAGAIN;
1556 hba->clk_gating.active_reqs--;
1557 break;
1558 }
1559
1560 spin_unlock_irqrestore(hba->host->host_lock, flags);
1561 flush_work(&hba->clk_gating.ungate_work);
1562 /* Make sure state is CLKS_ON before returning */
856b3483 1563 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1564 goto start;
1565 default:
1566 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1567 __func__, hba->clk_gating.state);
1568 break;
1569 }
1570 spin_unlock_irqrestore(hba->host->host_lock, flags);
1571out:
1572 return rc;
1573}
6e3fd44d 1574EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1575
1576static void ufshcd_gate_work(struct work_struct *work)
1577{
1578 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1579 clk_gating.gate_work.work);
1580 unsigned long flags;
1581
1582 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1583 /*
1584 * In case you are here to cancel this work the gating state
1585 * would be marked as REQ_CLKS_ON. In this case save time by
1586 * skipping the gating work and exit after changing the clock
1587 * state to CLKS_ON.
1588 */
1589 if (hba->clk_gating.is_suspended ||
18f01374 1590 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1ab27c9c 1591 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1592 trace_ufshcd_clk_gating(dev_name(hba->dev),
1593 hba->clk_gating.state);
1ab27c9c
ST		 1594 goto rel_lock;
1595 }
1596
1597 if (hba->clk_gating.active_reqs
1598 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1599 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1ab27c9c
ST		 1600 || hba->active_uic_cmd || hba->uic_async_done)
1601 goto rel_lock;
1602
1603 spin_unlock_irqrestore(hba->host->host_lock, flags);
1604
1605 /* put the link into hibern8 mode before turning off clocks */
1606 if (ufshcd_can_hibern8_during_gating(hba)) {
1607 if (ufshcd_uic_hibern8_enter(hba)) {
1608 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1609 trace_ufshcd_clk_gating(dev_name(hba->dev),
1610 hba->clk_gating.state);
1ab27c9c
ST		 1611 goto out;
1612 }
1613 ufshcd_set_link_hibern8(hba);
1614 }
1615
8b0bbf00
SC		 1616 ufshcd_disable_irq(hba);
1617
1ab27c9c
ST		 1618 if (!ufshcd_is_link_active(hba))
1619 ufshcd_setup_clocks(hba, false);
1620 else
1621 /* If link is active, device ref_clk can't be switched off */
1622 __ufshcd_setup_clocks(hba, false, true);
1623
1624 /*
1625 * In case you are here to cancel this work the gating state
1626 * would be marked as REQ_CLKS_ON. In this case keep the state
1627 * as REQ_CLKS_ON which would anyway imply that clocks are off
1628 * and a request to turn them on is pending. By doing this way,
1629 * we keep the state machine in tact and this would ultimately
1630 * prevent from doing cancel work multiple times when there are
1631 * new requests arriving before the current cancel work is done.
1632 */
1633 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1634 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1635 hba->clk_gating.state = CLKS_OFF;
7ff5ab47
SJ		 1636 trace_ufshcd_clk_gating(dev_name(hba->dev),
1637 hba->clk_gating.state);
1638 }
1ab27c9c
ST		 1639rel_lock:
1640 spin_unlock_irqrestore(hba->host->host_lock, flags);
1641out:
1642 return;
1643}
1644
1645/* host lock must be held before calling this variant */
1646static void __ufshcd_release(struct ufs_hba *hba)
1647{
1648 if (!ufshcd_is_clkgating_allowed(hba))
1649 return;
1650
1651 hba->clk_gating.active_reqs--;
1652
1653 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1654 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
7252a360 1655 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
53c12d0e
YG		 1656 || hba->active_uic_cmd || hba->uic_async_done
1657 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1658 return;
1659
1660 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1661 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1662 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1663 &hba->clk_gating.gate_work,
1664 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1665}
1666
1667void ufshcd_release(struct ufs_hba *hba)
1668{
1669 unsigned long flags;
1670
1671 spin_lock_irqsave(hba->host->host_lock, flags);
1672 __ufshcd_release(hba);
1673 spin_unlock_irqrestore(hba->host->host_lock, flags);
1674}
6e3fd44d 1675EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1676
1677static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1678 struct device_attribute *attr, char *buf)
1679{
1680 struct ufs_hba *hba = dev_get_drvdata(dev);
1681
1682 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1683}
1684
1685static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1686 struct device_attribute *attr, const char *buf, size_t count)
1687{
1688 struct ufs_hba *hba = dev_get_drvdata(dev);
1689 unsigned long flags, value;
1690
1691 if (kstrtoul(buf, 0, &value))
1692 return -EINVAL;
1693
1694 spin_lock_irqsave(hba->host->host_lock, flags);
1695 hba->clk_gating.delay_ms = value;
1696 spin_unlock_irqrestore(hba->host->host_lock, flags);
1697 return count;
1698}
1699
b427411a
ST		 1700static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1701 struct device_attribute *attr, char *buf)
1702{
1703 struct ufs_hba *hba = dev_get_drvdata(dev);
1704
1705 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1706}
1707
1708static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1709 struct device_attribute *attr, const char *buf, size_t count)
1710{
1711 struct ufs_hba *hba = dev_get_drvdata(dev);
1712 unsigned long flags;
1713 u32 value;
1714
1715 if (kstrtou32(buf, 0, &value))
1716 return -EINVAL;
1717
1718 value = !!value;
1719 if (value == hba->clk_gating.is_enabled)
1720 goto out;
1721
1722 if (value) {
1723 ufshcd_release(hba);
1724 } else {
1725 spin_lock_irqsave(hba->host->host_lock, flags);
1726 hba->clk_gating.active_reqs++;
1727 spin_unlock_irqrestore(hba->host->host_lock, flags);
1728 }
1729
1730 hba->clk_gating.is_enabled = value;
1731out:
1732 return count;
1733}
1734
eebcc196
VG		 1735static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1736{
1737 char wq_name[sizeof("ufs_clkscaling_00")];
1738
1739 if (!ufshcd_is_clkscaling_supported(hba))
1740 return;
1741
1742 INIT_WORK(&hba->clk_scaling.suspend_work,
1743 ufshcd_clk_scaling_suspend_work);
1744 INIT_WORK(&hba->clk_scaling.resume_work,
1745 ufshcd_clk_scaling_resume_work);
1746
1747 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1748 hba->host->host_no);
1749 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1750
1751 ufshcd_clkscaling_init_sysfs(hba);
1752}
1753
1754static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1755{
1756 if (!ufshcd_is_clkscaling_supported(hba))
1757 return;
1758
1759 destroy_workqueue(hba->clk_scaling.workq);
1760 ufshcd_devfreq_remove(hba);
1761}
1762
1ab27c9c
ST		 1763static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1764{
10e5e375
VV		 1765 char wq_name[sizeof("ufs_clk_gating_00")];
1766
1ab27c9c
ST		 1767 if (!ufshcd_is_clkgating_allowed(hba))
1768 return;
1769
1770 hba->clk_gating.delay_ms = 150;
1771 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1772 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1773
10e5e375
VV		 1774 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1775 hba->host->host_no);
1776 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1777 WQ_MEM_RECLAIM);
1778
b427411a
ST		 1779 hba->clk_gating.is_enabled = true;
1780
1ab27c9c
ST		 1781 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1782 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1783 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1784 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1785 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1786 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1787 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1788
1789 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1790 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1791 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1792 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1793 hba->clk_gating.enable_attr.attr.mode = 0644;
1794 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1795 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1796}
1797
1798static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1799{
1800 if (!ufshcd_is_clkgating_allowed(hba))
1801 return;
1802 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1803 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1804 cancel_work_sync(&hba->clk_gating.ungate_work);
1805 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
10e5e375 1806 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 1807}
1808
856b3483
ST		 1809/* Must be called with host lock acquired */
1810static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1811{
401f1e44
SJ		 1812 bool queue_resume_work = false;
1813
fcb0c4b0 1814 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1815 return;
1816
401f1e44
SJ		 1817 if (!hba->clk_scaling.active_reqs++)
1818 queue_resume_work = true;
1819
1820 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1821 return;
1822
1823 if (queue_resume_work)
1824 queue_work(hba->clk_scaling.workq,
1825 &hba->clk_scaling.resume_work);
1826
1827 if (!hba->clk_scaling.window_start_t) {
1828 hba->clk_scaling.window_start_t = jiffies;
1829 hba->clk_scaling.tot_busy_t = 0;
1830 hba->clk_scaling.is_busy_started = false;
1831 }
1832
856b3483
ST		 1833 if (!hba->clk_scaling.is_busy_started) {
1834 hba->clk_scaling.busy_start_t = ktime_get();
1835 hba->clk_scaling.is_busy_started = true;
1836 }
1837}
1838
1839static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1840{
1841 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1842
fcb0c4b0 1843 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1844 return;
1845
1846 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1847 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1848 scaling->busy_start_t));
8b0e1953 1849 scaling->busy_start_t = 0;
856b3483
ST		 1850 scaling->is_busy_started = false;
1851 }
1852}
7a3e97b0
SY		 1853/**
1854 * ufshcd_send_command - Send SCSI or device management commands
1855 * @hba: per adapter instance
1856 * @task_tag: Task tag of the command
1857 */
1858static inline
1859void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1860{
ff8e20c6 1861 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1862 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
eacf36f5 1863 ufshcd_add_command_trace(hba, task_tag, "send");
856b3483 1864 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1865 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1866 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1867 /* Make sure that doorbell is committed immediately */
1868 wmb();
7a3e97b0
SY		 1869}
1870
1871/**
1872 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 1873 * @lrbp: pointer to local reference block
7a3e97b0
SY		 1874 */
1875static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1876{
1877 int len;
1c2623c5
SJ		 1878 if (lrbp->sense_buffer &&
1879 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1880 int len_to_copy;
1881
5a0b0cb9 1882 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
09a5a24f 1883 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
e3ce73d6 1884
09a5a24f
AA		 1885 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
1886 len_to_copy);
7a3e97b0
SY		 1887 }
1888}
1889
68078d5c
DR		 1890/**
1891 * ufshcd_copy_query_response() - Copy the Query Response and the data
1892 * descriptor
1893 * @hba: per adapter instance
8aa29f19 1894 * @lrbp: pointer to local reference block
68078d5c
DR		 1895 */
1896static
c6d4a831 1897int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1898{
1899 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1900
68078d5c 1901 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1902
68078d5c 1903 /* Get the descriptor */
1c90836f
AA		 1904 if (hba->dev_cmd.query.descriptor &&
1905 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1906 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1907 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1908 u16 resp_len;
1909 u16 buf_len;
68078d5c
DR		 1910
1911 /* data segment length */
c6d4a831 1912 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1913 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1914 buf_len = be16_to_cpu(
1915 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1916 if (likely(buf_len >= resp_len)) {
1917 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1918 } else {
1919 dev_warn(hba->dev,
3d4881d1
BH		 1920 "%s: rsp size %d is bigger than buffer size %d",
1921 __func__, resp_len, buf_len);
c6d4a831
DR		 1922 return -EINVAL;
1923 }
68078d5c 1924 }
c6d4a831
DR		 1925
1926 return 0;
68078d5c
DR		 1927}
1928
7a3e97b0
SY		 1929/**
1930 * ufshcd_hba_capabilities - Read controller capabilities
1931 * @hba: per adapter instance
1932 */
1933static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1934{
b873a275 1935 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1936
1937 /* nutrs and nutmrs are 0 based values */
1938 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1939 hba->nutmrs =
1940 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1941}
1942
1943/**
6ccf44fe
SJ		 1944 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1945 * to accept UIC commands
7a3e97b0 1946 * @hba: per adapter instance
6ccf44fe
SJ		 1947 * Return true on success, else false
1948 */
1949static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1950{
1951 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1952 return true;
1953 else
1954 return false;
1955}
1956
53b3d9c3
SJ		 1957/**
1958 * ufshcd_get_upmcrs - Get the power mode change request status
1959 * @hba: Pointer to adapter instance
1960 *
1961 * This function gets the UPMCRS field of HCS register
1962 * Returns value of UPMCRS field
1963 */
1964static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1965{
1966 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1967}
1968
6ccf44fe
SJ		 1969/**
1970 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1971 * @hba: per adapter instance
1972 * @uic_cmd: UIC command
1973 *
1974 * Mutex must be held.
7a3e97b0
SY		 1975 */
1976static inline void
6ccf44fe 1977ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1978{
6ccf44fe
SJ		 1979 WARN_ON(hba->active_uic_cmd);
1980
1981 hba->active_uic_cmd = uic_cmd;
1982
7a3e97b0 1983 /* Write Args */
6ccf44fe
SJ		 1984 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1985 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1986 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1987
1988 /* Write UIC Cmd */
6ccf44fe 1989 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1990 REG_UIC_COMMAND);
7a3e97b0
SY		 1991}
1992
6ccf44fe
SJ		 1993/**
1994 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1995 * @hba: per adapter instance
8aa29f19 1996 * @uic_cmd: UIC command
6ccf44fe
SJ		 1997 *
1998 * Must be called with mutex held.
1999 * Returns 0 only if success.
2000 */
2001static int
2002ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2003{
2004 int ret;
2005 unsigned long flags;
2006
2007 if (wait_for_completion_timeout(&uic_cmd->done,
2008 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2009 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2010 else
2011 ret = -ETIMEDOUT;
2012
2013 spin_lock_irqsave(hba->host->host_lock, flags);
2014 hba->active_uic_cmd = NULL;
2015 spin_unlock_irqrestore(hba->host->host_lock, flags);
2016
2017 return ret;
2018}
2019
2020/**
2021 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2022 * @hba: per adapter instance
2023 * @uic_cmd: UIC command
d75f7fe4 2024 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 2025 *
2026 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 2027 * with mutex held and host_lock locked.
6ccf44fe
SJ		 2028 * Returns 0 only if success.
2029 */
2030static int
d75f7fe4
YG		 2031__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2032 bool completion)
6ccf44fe 2033{
6ccf44fe
SJ		 2034 if (!ufshcd_ready_for_uic_cmd(hba)) {
2035 dev_err(hba->dev,
2036 "Controller not ready to accept UIC commands\n");
2037 return -EIO;
2038 }
2039
d75f7fe4
YG		 2040 if (completion)
2041 init_completion(&uic_cmd->done);
6ccf44fe 2042
6ccf44fe 2043 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2044
57d104c1 2045 return 0;
6ccf44fe
SJ		 2046}
2047
2048/**
2049 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2050 * @hba: per adapter instance
2051 * @uic_cmd: UIC command
2052 *
2053 * Returns 0 only if success.
2054 */
e77044c5 2055int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2056{
2057 int ret;
57d104c1 2058 unsigned long flags;
6ccf44fe 2059
1ab27c9c 2060 ufshcd_hold(hba, false);
6ccf44fe 2061 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2062 ufshcd_add_delay_before_dme_cmd(hba);
2063
57d104c1 2064 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2065 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2066 spin_unlock_irqrestore(hba->host->host_lock, flags);
2067 if (!ret)
2068 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2069
6ccf44fe
SJ		 2070 mutex_unlock(&hba->uic_cmd_mutex);
2071
1ab27c9c 2072 ufshcd_release(hba);
6ccf44fe
SJ		 2073 return ret;
2074}
2075
7a3e97b0
SY		 2076/**
2077 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2078 * @hba: per adapter instance
2079 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2080 *
2081 * Returns 0 in case of success, non-zero value in case of failure
2082 */
75b1cc4a 2083static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2084{
2085 struct ufshcd_sg_entry *prd_table;
2086 struct scatterlist *sg;
2087 struct scsi_cmnd *cmd;
2088 int sg_segments;
2089 int i;
2090
2091 cmd = lrbp->cmd;
2092 sg_segments = scsi_dma_map(cmd);
2093 if (sg_segments < 0)
2094 return sg_segments;
2095
2096 if (sg_segments) {
49200199
CH		 2097 lrbp->utr_descriptor_ptr->prd_table_length =
2098 cpu_to_le16((u16)sg_segments);
7a3e97b0
SY		 2099
2100 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2101
2102 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2103 prd_table[i].size =
2104 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2105 prd_table[i].base_addr =
2106 cpu_to_le32(lower_32_bits(sg->dma_address));
2107 prd_table[i].upper_addr =
2108 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2109 prd_table[i].reserved = 0;
7a3e97b0
SY		 2110 }
2111 } else {
2112 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2113 }
2114
2115 return 0;
2116}
2117
2118/**
2fbd009b 2119 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2120 * @hba: per adapter instance
2fbd009b 2121 * @intrs: interrupt bits
7a3e97b0 2122 */
2fbd009b 2123static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2124{
2fbd009b
SJ		 2125 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2126
2127 if (hba->ufs_version == UFSHCI_VERSION_10) {
2128 u32 rw;
2129 rw = set & INTERRUPT_MASK_RW_VER_10;
2130 set = rw | ((set ^ intrs) & intrs);
2131 } else {
2132 set |= intrs;
2133 }
2134
2135 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2136}
2137
2138/**
2139 * ufshcd_disable_intr - disable interrupts
2140 * @hba: per adapter instance
2141 * @intrs: interrupt bits
2142 */
2143static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2144{
2145 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2146
2147 if (hba->ufs_version == UFSHCI_VERSION_10) {
2148 u32 rw;
2149 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2150 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2151 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2152
2153 } else {
2154 set &= ~intrs;
7a3e97b0 2155 }
2fbd009b
SJ		 2156
2157 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2158}
2159
5a0b0cb9
SRT		 2160/**
2161 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2162 * descriptor according to request
2163 * @lrbp: pointer to local reference block
2164 * @upiu_flags: flags required in the header
2165 * @cmd_dir: requests data direction
2166 */
2167static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2168 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2169{
2170 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2171 u32 data_direction;
2172 u32 dword_0;
2173
2174 if (cmd_dir == DMA_FROM_DEVICE) {
2175 data_direction = UTP_DEVICE_TO_HOST;
2176 *upiu_flags = UPIU_CMD_FLAGS_READ;
2177 } else if (cmd_dir == DMA_TO_DEVICE) {
2178 data_direction = UTP_HOST_TO_DEVICE;
2179 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2180 } else {
2181 data_direction = UTP_NO_DATA_TRANSFER;
2182 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2183 }
2184
2185 dword_0 = data_direction | (lrbp->command_type
2186 << UPIU_COMMAND_TYPE_OFFSET);
2187 if (lrbp->intr_cmd)
2188 dword_0 |= UTP_REQ_DESC_INT_CMD;
2189
2190 /* Transfer request descriptor header fields */
2191 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2192 /* dword_1 is reserved, hence it is set to 0 */
2193 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2194 /*
2195 * assigning invalid value for command status. Controller
2196 * updates OCS on command completion, with the command
2197 * status
2198 */
2199 req_desc->header.dword_2 =
2200 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2201 /* dword_3 is reserved, hence it is set to 0 */
2202 req_desc->header.dword_3 = 0;
51047266
YG		 2203
2204 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2205}
2206
2207/**
2208 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2209 * for scsi commands
8aa29f19
BVA		 2210 * @lrbp: local reference block pointer
2211 * @upiu_flags: flags
5a0b0cb9
SRT		 2212 */
2213static
2214void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2215{
1b21b8f0 2216 struct scsi_cmnd *cmd = lrbp->cmd;
5a0b0cb9 2217 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2218 unsigned short cdb_len;
5a0b0cb9
SRT		 2219
2220 /* command descriptor fields */
2221 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2222 UPIU_TRANSACTION_COMMAND, upiu_flags,
2223 lrbp->lun, lrbp->task_tag);
2224 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2225 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2226
2227 /* Total EHS length and Data segment length will be zero */
2228 ucd_req_ptr->header.dword_2 = 0;
2229
1b21b8f0 2230 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
5a0b0cb9 2231
1b21b8f0 2232 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
a851b2bd 2233 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1b21b8f0 2234 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
52ac95fe
YG		 2235
2236 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2237}
2238
68078d5c
DR		 2239/**
2240 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2241 * for query requsts
2242 * @hba: UFS hba
2243 * @lrbp: local reference block pointer
2244 * @upiu_flags: flags
2245 */
2246static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2247 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2248{
2249 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2250 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2251 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2252
2253 /* Query request header */
2254 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2255 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2256 lrbp->lun, lrbp->task_tag);
2257 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2258 0, query->request.query_func, 0, 0);
2259
6861285c
ZL		 2260 /* Data segment length only need for WRITE_DESC */
2261 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2262 ucd_req_ptr->header.dword_2 =
2263 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2264 else
2265 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2266
2267 /* Copy the Query Request buffer as is */
2268 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2269 QUERY_OSF_SIZE);
68078d5c
DR		 2270
2271 /* Copy the Descriptor */
c6d4a831 2272 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2273 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2274
51047266 2275 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2276}
2277
5a0b0cb9
SRT		 2278static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2279{
2280 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2281
2282 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2283
2284 /* command descriptor fields */
2285 ucd_req_ptr->header.dword_0 =
2286 UPIU_HEADER_DWORD(
2287 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2288 /* clear rest of the fields of basic header */
2289 ucd_req_ptr->header.dword_1 = 0;
2290 ucd_req_ptr->header.dword_2 = 0;
2291
2292 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2293}
2294
7a3e97b0 2295/**
300bb13f
JP		 2296 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2297 * for Device Management Purposes
8aa29f19
BVA		 2298 * @hba: per adapter instance
2299 * @lrbp: pointer to local reference block
7a3e97b0 2300 */
300bb13f 2301static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2302{
7a3e97b0 2303 u32 upiu_flags;
5a0b0cb9 2304 int ret = 0;
7a3e97b0 2305
83dc7e3d 2306 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2307 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2308 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2309 else
2310 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2311
2312 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2313 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2314 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2315 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2316 ufshcd_prepare_utp_nop_upiu(lrbp);
2317 else
2318 ret = -EINVAL;
2319
2320 return ret;
2321}
2322
2323/**
2324 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2325 * for SCSI Purposes
8aa29f19
BVA		 2326 * @hba: per adapter instance
2327 * @lrbp: pointer to local reference block
300bb13f
JP		 2328 */
2329static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2330{
2331 u32 upiu_flags;
2332 int ret = 0;
2333
83dc7e3d 2334 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2335 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2336 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2337 else
2338 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2339
2340 if (likely(lrbp->cmd)) {
2341 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2342 lrbp->cmd->sc_data_direction);
2343 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2344 } else {
2345 ret = -EINVAL;
2346 }
5a0b0cb9
SRT		 2347
2348 return ret;
7a3e97b0
SY		 2349}
2350
2a8fa600
SJ		 2351/**
2352 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2353 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2354 *
2355 * Returns SCSI W-LUN id
2356 */
2357static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2358{
2359 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2360}
2361
4d2b8d40
BVA		 2362static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2363{
2364 struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2365 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2366 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2367 i * sizeof(struct utp_transfer_cmd_desc);
2368 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2369 response_upiu);
2370 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2371
2372 lrb->utr_descriptor_ptr = utrdlp + i;
2373 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2374 i * sizeof(struct utp_transfer_req_desc);
2375 lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2376 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2377 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2378 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2379 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2380 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2381}
2382
7a3e97b0
SY		 2383/**
2384 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2385 * @host: SCSI host pointer
7a3e97b0 2386 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2387 *
2388 * Returns 0 for success, non-zero in case of failure
2389 */
2390static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2391{
2392 struct ufshcd_lrb *lrbp;
2393 struct ufs_hba *hba;
2394 unsigned long flags;
2395 int tag;
2396 int err = 0;
2397
2398 hba = shost_priv(host);
2399
2400 tag = cmd->request->tag;
14497328
YG		 2401 if (!ufshcd_valid_tag(hba, tag)) {
2402 dev_err(hba->dev,
2403 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2404 __func__, tag, cmd, cmd->request);
2405 BUG();
2406 }
7a3e97b0 2407
a3cd5ec5
SJ		 2408 if (!down_read_trylock(&hba->clk_scaling_lock))
2409 return SCSI_MLQUEUE_HOST_BUSY;
2410
3441da7d
SRT		 2411 spin_lock_irqsave(hba->host->host_lock, flags);
2412 switch (hba->ufshcd_state) {
2413 case UFSHCD_STATE_OPERATIONAL:
2414 break;
141f8165 2415 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2416 case UFSHCD_STATE_RESET:
7a3e97b0 2417 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2418 goto out_unlock;
2419 case UFSHCD_STATE_ERROR:
2420 set_host_byte(cmd, DID_ERROR);
2421 cmd->scsi_done(cmd);
2422 goto out_unlock;
2423 default:
2424 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2425 __func__, hba->ufshcd_state);
2426 set_host_byte(cmd, DID_BAD_TARGET);
2427 cmd->scsi_done(cmd);
2428 goto out_unlock;
7a3e97b0 2429 }
53c12d0e
YG		 2430
2431 /* if error handling is in progress, don't issue commands */
2432 if (ufshcd_eh_in_progress(hba)) {
2433 set_host_byte(cmd, DID_ERROR);
2434 cmd->scsi_done(cmd);
2435 goto out_unlock;
2436 }
3441da7d 2437 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2438
7fabb77b
GB		 2439 hba->req_abort_count = 0;
2440
1ab27c9c
ST		 2441 err = ufshcd_hold(hba, true);
2442 if (err) {
2443 err = SCSI_MLQUEUE_HOST_BUSY;
1ab27c9c
ST		 2444 goto out;
2445 }
2446 WARN_ON(hba->clk_gating.state != CLKS_ON);
2447
7a3e97b0
SY		 2448 lrbp = &hba->lrb[tag];
2449
5a0b0cb9 2450 WARN_ON(lrbp->cmd);
7a3e97b0 2451 lrbp->cmd = cmd;
09a5a24f 2452 lrbp->sense_bufflen = UFS_SENSE_SIZE;
7a3e97b0
SY		 2453 lrbp->sense_buffer = cmd->sense_buffer;
2454 lrbp->task_tag = tag;
0ce147d4 2455 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2456 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2457 lrbp->req_abort_skip = false;
7a3e97b0 2458
300bb13f
JP		 2459 ufshcd_comp_scsi_upiu(hba, lrbp);
2460
75b1cc4a 2461 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2462 if (err) {
2463 lrbp->cmd = NULL;
17c7d35f 2464 ufshcd_release(hba);
7a3e97b0 2465 goto out;
5a0b0cb9 2466 }
ad1a1b9c
GB		 2467 /* Make sure descriptors are ready before ringing the doorbell */
2468 wmb();
7a3e97b0
SY		 2469
2470 /* issue command to the controller */
2471 spin_lock_irqsave(hba->host->host_lock, flags);
5905d464 2472 ufshcd_vops_setup_xfer_req(hba, tag, true);
7a3e97b0 2473 ufshcd_send_command(hba, tag);
3441da7d 2474out_unlock:
7a3e97b0
SY		 2475 spin_unlock_irqrestore(hba->host->host_lock, flags);
2476out:
a3cd5ec5 2477 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2478 return err;
2479}
2480
5a0b0cb9
SRT		 2481static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2482 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2483{
2484 lrbp->cmd = NULL;
2485 lrbp->sense_bufflen = 0;
2486 lrbp->sense_buffer = NULL;
2487 lrbp->task_tag = tag;
2488 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2489 lrbp->intr_cmd = true; /* No interrupt aggregation */
2490 hba->dev_cmd.type = cmd_type;
2491
300bb13f 2492 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2493}
2494
2495static int
2496ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2497{
2498 int err = 0;
2499 unsigned long flags;
2500 u32 mask = 1 << tag;
2501
2502 /* clear outstanding transaction before retry */
2503 spin_lock_irqsave(hba->host->host_lock, flags);
2504 ufshcd_utrl_clear(hba, tag);
2505 spin_unlock_irqrestore(hba->host->host_lock, flags);
2506
2507 /*
2508 * wait for for h/w to clear corresponding bit in door-bell.
2509 * max. wait is 1 sec.
2510 */
2511 err = ufshcd_wait_for_register(hba,
2512 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2513 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2514
2515 return err;
2516}
2517
c6d4a831
DR		 2518static int
2519ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2520{
2521 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2522
2523 /* Get the UPIU response */
2524 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2525 UPIU_RSP_CODE_OFFSET;
2526 return query_res->response;
2527}
2528
5a0b0cb9
SRT		 2529/**
2530 * ufshcd_dev_cmd_completion() - handles device management command responses
2531 * @hba: per adapter instance
2532 * @lrbp: pointer to local reference block
2533 */
2534static int
2535ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2536{
2537 int resp;
2538 int err = 0;
2539
ff8e20c6 2540 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2541 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2542
2543 switch (resp) {
2544 case UPIU_TRANSACTION_NOP_IN:
2545 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2546 err = -EINVAL;
2547 dev_err(hba->dev, "%s: unexpected response %x\n",
2548 __func__, resp);
2549 }
2550 break;
68078d5c 2551 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2552 err = ufshcd_check_query_response(hba, lrbp);
2553 if (!err)
2554 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2555 break;
5a0b0cb9
SRT		 2556 case UPIU_TRANSACTION_REJECT_UPIU:
2557 /* TODO: handle Reject UPIU Response */
2558 err = -EPERM;
2559 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2560 __func__);
2561 break;
2562 default:
2563 err = -EINVAL;
2564 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2565 __func__, resp);
2566 break;
2567 }
2568
2569 return err;
2570}
2571
2572static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2573 struct ufshcd_lrb *lrbp, int max_timeout)
2574{
2575 int err = 0;
2576 unsigned long time_left;
2577 unsigned long flags;
2578
2579 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2580 msecs_to_jiffies(max_timeout));
2581
ad1a1b9c
GB		 2582 /* Make sure descriptors are ready before ringing the doorbell */
2583 wmb();
5a0b0cb9
SRT		 2584 spin_lock_irqsave(hba->host->host_lock, flags);
2585 hba->dev_cmd.complete = NULL;
2586 if (likely(time_left)) {
2587 err = ufshcd_get_tr_ocs(lrbp);
2588 if (!err)
2589 err = ufshcd_dev_cmd_completion(hba, lrbp);
2590 }
2591 spin_unlock_irqrestore(hba->host->host_lock, flags);
2592
2593 if (!time_left) {
2594 err = -ETIMEDOUT;
a48353f6
YG		 2595 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2596 __func__, lrbp->task_tag);
5a0b0cb9 2597 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2598 /* successfully cleared the command, retry if needed */
5a0b0cb9 2599 err = -EAGAIN;
a48353f6
YG		 2600 /*
2601 * in case of an error, after clearing the doorbell,
2602 * we also need to clear the outstanding_request
2603 * field in hba
2604 */
2605 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2606 }
2607
2608 return err;
2609}
2610
5a0b0cb9
SRT		 2611/**
2612 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2613 * @hba: UFS hba
2614 * @cmd_type: specifies the type (NOP, Query...)
2615 * @timeout: time in seconds
5a0b0cb9 2616 *
68078d5c
DR		 2617 * NOTE: Since there is only one available tag for device management commands,
2618 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2619 */
2620static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2621 enum dev_cmd_type cmd_type, int timeout)
2622{
7252a360
BVA		 2623 struct request_queue *q = hba->cmd_queue;
2624 struct request *req;
5a0b0cb9
SRT		 2625 struct ufshcd_lrb *lrbp;
2626 int err;
2627 int tag;
2628 struct completion wait;
2629 unsigned long flags;
2630
a3cd5ec5
SJ		 2631 down_read(&hba->clk_scaling_lock);
2632
5a0b0cb9
SRT		 2633 /*
2634 * Get free slot, sleep if slots are unavailable.
2635 * Even though we use wait_event() which sleeps indefinitely,
2636 * the maximum wait time is bounded by SCSI request timeout.
2637 */
7252a360 2638 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 2639 if (IS_ERR(req)) {
2640 err = PTR_ERR(req);
2641 goto out_unlock;
2642 }
7252a360
BVA		 2643 tag = req->tag;
2644 WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
5a0b0cb9
SRT		 2645
2646 init_completion(&wait);
2647 lrbp = &hba->lrb[tag];
2648 WARN_ON(lrbp->cmd);
2649 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2650 if (unlikely(err))
2651 goto out_put_tag;
2652
2653 hba->dev_cmd.complete = &wait;
2654
6667e6d9 2655 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
e3dfdc53
YG		 2656 /* Make sure descriptors are ready before ringing the doorbell */
2657 wmb();
5a0b0cb9 2658 spin_lock_irqsave(hba->host->host_lock, flags);
5905d464 2659 ufshcd_vops_setup_xfer_req(hba, tag, false);
5a0b0cb9
SRT		 2660 ufshcd_send_command(hba, tag);
2661 spin_unlock_irqrestore(hba->host->host_lock, flags);
2662
2663 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2664
6667e6d9
OS		 2665 ufshcd_add_query_upiu_trace(hba, tag,
2666 err ? "query_complete_err" : "query_complete");
2667
5a0b0cb9 2668out_put_tag:
7252a360 2669 blk_put_request(req);
bb14dd15 2670out_unlock:
a3cd5ec5 2671 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2672 return err;
2673}
2674
d44a5f98
DR		 2675/**
2676 * ufshcd_init_query() - init the query response and request parameters
2677 * @hba: per-adapter instance
2678 * @request: address of the request pointer to be initialized
2679 * @response: address of the response pointer to be initialized
2680 * @opcode: operation to perform
2681 * @idn: flag idn to access
2682 * @index: LU number to access
2683 * @selector: query/flag/descriptor further identification
2684 */
2685static inline void ufshcd_init_query(struct ufs_hba *hba,
2686 struct ufs_query_req **request, struct ufs_query_res **response,
2687 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2688{
2689 *request = &hba->dev_cmd.query.request;
2690 *response = &hba->dev_cmd.query.response;
2691 memset(*request, 0, sizeof(struct ufs_query_req));
2692 memset(*response, 0, sizeof(struct ufs_query_res));
2693 (*request)->upiu_req.opcode = opcode;
2694 (*request)->upiu_req.idn = idn;
2695 (*request)->upiu_req.index = index;
2696 (*request)->upiu_req.selector = selector;
2697}
2698
dc3c8d3a
YG		 2699static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2700 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2701{
2702 int ret;
2703 int retries;
2704
2705 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2706 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2707 if (ret)
2708 dev_dbg(hba->dev,
2709 "%s: failed with error %d, retries %d\n",
2710 __func__, ret, retries);
2711 else
2712 break;
2713 }
2714
2715 if (ret)
2716 dev_err(hba->dev,
2717 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2718 __func__, opcode, idn, ret, retries);
2719 return ret;
2720}
2721
68078d5c
DR		 2722/**
2723 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 2724 * @hba: per-adapter instance
2725 * @opcode: flag query to perform
2726 * @idn: flag idn to access
2727 * @flag_res: the flag value after the query request completes
68078d5c
DR		 2728 *
2729 * Returns 0 for success, non-zero in case of failure
2730 */
dc3c8d3a 2731int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2732 enum flag_idn idn, bool *flag_res)
2733{
d44a5f98
DR		 2734 struct ufs_query_req *request = NULL;
2735 struct ufs_query_res *response = NULL;
2736 int err, index = 0, selector = 0;
e5ad406c 2737 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2738
2739 BUG_ON(!hba);
2740
1ab27c9c 2741 ufshcd_hold(hba, false);
68078d5c 2742 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2743 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2744 selector);
68078d5c
DR		 2745
2746 switch (opcode) {
2747 case UPIU_QUERY_OPCODE_SET_FLAG:
2748 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2749 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2750 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2751 break;
2752 case UPIU_QUERY_OPCODE_READ_FLAG:
2753 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2754 if (!flag_res) {
2755 /* No dummy reads */
2756 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2757 __func__);
2758 err = -EINVAL;
2759 goto out_unlock;
2760 }
2761 break;
2762 default:
2763 dev_err(hba->dev,
2764 "%s: Expected query flag opcode but got = %d\n",
2765 __func__, opcode);
2766 err = -EINVAL;
2767 goto out_unlock;
2768 }
68078d5c 2769
e5ad406c 2770 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2771
2772 if (err) {
2773 dev_err(hba->dev,
2774 "%s: Sending flag query for idn %d failed, err = %d\n",
2775 __func__, idn, err);
2776 goto out_unlock;
2777 }
2778
2779 if (flag_res)
e8c8e82a 2780 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2781 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2782
2783out_unlock:
2784 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2785 ufshcd_release(hba);
68078d5c
DR		 2786 return err;
2787}
2788
66ec6d59
SRT		 2789/**
2790 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 2791 * @hba: per-adapter instance
2792 * @opcode: attribute opcode
2793 * @idn: attribute idn to access
2794 * @index: index field
2795 * @selector: selector field
2796 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 2797 *
2798 * Returns 0 for success, non-zero in case of failure
2799*/
ec92b59c
SN		 2800int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2801 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 2802{
d44a5f98
DR		 2803 struct ufs_query_req *request = NULL;
2804 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2805 int err;
2806
2807 BUG_ON(!hba);
2808
1ab27c9c 2809 ufshcd_hold(hba, false);
66ec6d59
SRT		 2810 if (!attr_val) {
2811 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2812 __func__, opcode);
2813 err = -EINVAL;
2814 goto out;
2815 }
2816
2817 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2818 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2819 selector);
66ec6d59
SRT		 2820
2821 switch (opcode) {
2822 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2823 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2824 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2825 break;
2826 case UPIU_QUERY_OPCODE_READ_ATTR:
2827 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2828 break;
2829 default:
2830 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2831 __func__, opcode);
2832 err = -EINVAL;
2833 goto out_unlock;
2834 }
2835
d44a5f98 2836 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2837
2838 if (err) {
4b761b58
YG		 2839 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2840 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2841 goto out_unlock;
2842 }
2843
e8c8e82a 2844 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2845
2846out_unlock:
2847 mutex_unlock(&hba->dev_cmd.lock);
2848out:
1ab27c9c 2849 ufshcd_release(hba);
66ec6d59
SRT		 2850 return err;
2851}
2852
5e86ae44
YG		 2853/**
2854 * ufshcd_query_attr_retry() - API function for sending query
2855 * attribute with retries
2856 * @hba: per-adapter instance
2857 * @opcode: attribute opcode
2858 * @idn: attribute idn to access
2859 * @index: index field
2860 * @selector: selector field
2861 * @attr_val: the attribute value after the query request
2862 * completes
2863 *
2864 * Returns 0 for success, non-zero in case of failure
2865*/
2866static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2867 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2868 u32 *attr_val)
2869{
2870 int ret = 0;
2871 u32 retries;
2872
68c9fcfd 2873 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5e86ae44
YG		 2874 ret = ufshcd_query_attr(hba, opcode, idn, index,
2875 selector, attr_val);
2876 if (ret)
2877 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2878 __func__, ret, retries);
2879 else
2880 break;
2881 }
2882
2883 if (ret)
2884 dev_err(hba->dev,
2885 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2886 __func__, idn, ret, QUERY_REQ_RETRIES);
2887 return ret;
2888}
2889
a70e91b8 2890static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2891 enum query_opcode opcode, enum desc_idn idn, u8 index,
2892 u8 selector, u8 *desc_buf, int *buf_len)
2893{
2894 struct ufs_query_req *request = NULL;
2895 struct ufs_query_res *response = NULL;
2896 int err;
2897
2898 BUG_ON(!hba);
2899
1ab27c9c 2900 ufshcd_hold(hba, false);
d44a5f98
DR		 2901 if (!desc_buf) {
2902 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2903 __func__, opcode);
2904 err = -EINVAL;
2905 goto out;
2906 }
2907
a4b0e8a4 2908 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2909 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2910 __func__, *buf_len);
2911 err = -EINVAL;
2912 goto out;
2913 }
2914
2915 mutex_lock(&hba->dev_cmd.lock);
2916 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2917 selector);
2918 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2919 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2920
2921 switch (opcode) {
2922 case UPIU_QUERY_OPCODE_WRITE_DESC:
2923 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2924 break;
2925 case UPIU_QUERY_OPCODE_READ_DESC:
2926 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2927 break;
2928 default:
2929 dev_err(hba->dev,
2930 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2931 __func__, opcode);
2932 err = -EINVAL;
2933 goto out_unlock;
2934 }
2935
2936 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2937
2938 if (err) {
4b761b58
YG		 2939 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2940 __func__, opcode, idn, index, err);
d44a5f98
DR		 2941 goto out_unlock;
2942 }
2943
ea2aab24 2944 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2945
2946out_unlock:
cfcbae38 2947 hba->dev_cmd.query.descriptor = NULL;
d44a5f98
DR		 2948 mutex_unlock(&hba->dev_cmd.lock);
2949out:
1ab27c9c 2950 ufshcd_release(hba);
d44a5f98
DR		 2951 return err;
2952}
2953
a70e91b8 2954/**
8aa29f19
BVA		 2955 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
2956 * @hba: per-adapter instance
2957 * @opcode: attribute opcode
2958 * @idn: attribute idn to access
2959 * @index: index field
2960 * @selector: selector field
2961 * @desc_buf: the buffer that contains the descriptor
2962 * @buf_len: length parameter passed to the device
a70e91b8
YG		 2963 *
2964 * Returns 0 for success, non-zero in case of failure.
2965 * The buf_len parameter will contain, on return, the length parameter
2966 * received on the response.
2967 */
2238d31c
SN		 2968int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2969 enum query_opcode opcode,
2970 enum desc_idn idn, u8 index,
2971 u8 selector,
2972 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 2973{
2974 int err;
2975 int retries;
2976
2977 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2978 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2979 selector, desc_buf, buf_len);
2980 if (!err || err == -EINVAL)
2981 break;
2982 }
2983
2984 return err;
2985}
a70e91b8 2986
a4b0e8a4
PM		 2987/**
2988 * ufshcd_read_desc_length - read the specified descriptor length from header
2989 * @hba: Pointer to adapter instance
2990 * @desc_id: descriptor idn value
2991 * @desc_index: descriptor index
2992 * @desc_length: pointer to variable to read the length of descriptor
2993 *
2994 * Return 0 in case of success, non-zero otherwise
2995 */
2996static int ufshcd_read_desc_length(struct ufs_hba *hba,
2997 enum desc_idn desc_id,
2998 int desc_index,
2999 int *desc_length)
3000{
3001 int ret;
3002 u8 header[QUERY_DESC_HDR_SIZE];
3003 int header_len = QUERY_DESC_HDR_SIZE;
3004
3005 if (desc_id >= QUERY_DESC_IDN_MAX)
3006 return -EINVAL;
3007
3008 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3009 desc_id, desc_index, 0, header,
3010 &header_len);
3011
3012 if (ret) {
3013 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3014 __func__, desc_id);
3015 return ret;
3016 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3017 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3018 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3019 desc_id);
3020 ret = -EINVAL;
3021 }
3022
3023 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3024 return ret;
3025
3026}
3027
3028/**
3029 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3030 * @hba: Pointer to adapter instance
3031 * @desc_id: descriptor idn value
3032 * @desc_len: mapped desc length (out)
3033 *
3034 * Return 0 in case of success, non-zero otherwise
3035 */
3036int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3037 enum desc_idn desc_id, int *desc_len)
3038{
3039 switch (desc_id) {
3040 case QUERY_DESC_IDN_DEVICE:
3041 *desc_len = hba->desc_size.dev_desc;
3042 break;
3043 case QUERY_DESC_IDN_POWER:
3044 *desc_len = hba->desc_size.pwr_desc;
3045 break;
3046 case QUERY_DESC_IDN_GEOMETRY:
3047 *desc_len = hba->desc_size.geom_desc;
3048 break;
3049 case QUERY_DESC_IDN_CONFIGURATION:
3050 *desc_len = hba->desc_size.conf_desc;
3051 break;
3052 case QUERY_DESC_IDN_UNIT:
3053 *desc_len = hba->desc_size.unit_desc;
3054 break;
3055 case QUERY_DESC_IDN_INTERCONNECT:
3056 *desc_len = hba->desc_size.interc_desc;
3057 break;
3058 case QUERY_DESC_IDN_STRING:
3059 *desc_len = QUERY_DESC_MAX_SIZE;
3060 break;
c648c2d2
SN		 3061 case QUERY_DESC_IDN_HEALTH:
3062 *desc_len = hba->desc_size.hlth_desc;
3063 break;
a4b0e8a4
PM		 3064 case QUERY_DESC_IDN_RFU_0:
3065 case QUERY_DESC_IDN_RFU_1:
3066 *desc_len = 0;
3067 break;
3068 default:
3069 *desc_len = 0;
3070 return -EINVAL;
3071 }
3072 return 0;
3073}
3074EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3075
da461cec
SJ		 3076/**
3077 * ufshcd_read_desc_param - read the specified descriptor parameter
3078 * @hba: Pointer to adapter instance
3079 * @desc_id: descriptor idn value
3080 * @desc_index: descriptor index
3081 * @param_offset: offset of the parameter to read
3082 * @param_read_buf: pointer to buffer where parameter would be read
3083 * @param_size: sizeof(param_read_buf)
3084 *
3085 * Return 0 in case of success, non-zero otherwise
3086 */
45bced87
SN		 3087int ufshcd_read_desc_param(struct ufs_hba *hba,
3088 enum desc_idn desc_id,
3089 int desc_index,
3090 u8 param_offset,
3091 u8 *param_read_buf,
3092 u8 param_size)
da461cec
SJ		 3093{
3094 int ret;
3095 u8 *desc_buf;
a4b0e8a4 3096 int buff_len;
da461cec
SJ		 3097 bool is_kmalloc = true;
3098
a4b0e8a4
PM		 3099 /* Safety check */
3100 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3101 return -EINVAL;
3102
a4b0e8a4
PM		 3103 /* Get the max length of descriptor from structure filled up at probe
3104 * time.
3105 */
3106 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3107
a4b0e8a4
PM		 3108 /* Sanity checks */
3109 if (ret || !buff_len) {
3110 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3111 __func__);
3112 return ret;
3113 }
3114
3115 /* Check whether we need temp memory */
3116 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3117 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3118 if (!desc_buf)
3119 return -ENOMEM;
a4b0e8a4
PM		 3120 } else {
3121 desc_buf = param_read_buf;
3122 is_kmalloc = false;
da461cec
SJ		 3123 }
3124
a4b0e8a4 3125 /* Request for full descriptor */
a70e91b8 3126 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3127 desc_id, desc_index, 0,
3128 desc_buf, &buff_len);
da461cec 3129
bde44bb6
SJ		 3130 if (ret) {
3131 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3132 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3133 goto out;
3134 }
3135
bde44bb6
SJ		 3136 /* Sanity check */
3137 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3138 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3139 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3140 ret = -EINVAL;
3141 goto out;
3142 }
3143
a4b0e8a4
PM		 3144 /* Check wherher we will not copy more data, than available */
3145 if (is_kmalloc && param_size > buff_len)
3146 param_size = buff_len;
bde44bb6 3147
da461cec
SJ		 3148 if (is_kmalloc)
3149 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3150out:
3151 if (is_kmalloc)
3152 kfree(desc_buf);
3153 return ret;
3154}
3155
3156static inline int ufshcd_read_desc(struct ufs_hba *hba,
3157 enum desc_idn desc_id,
3158 int desc_index,
4b828fe1 3159 void *buf,
da461cec
SJ		 3160 u32 size)
3161{
3162 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3163}
3164
b573d484 3165
4b828fe1
TW		 3166/**
3167 * struct uc_string_id - unicode string
3168 *
3169 * @len: size of this descriptor inclusive
3170 * @type: descriptor type
3171 * @uc: unicode string character
3172 */
3173struct uc_string_id {
3174 u8 len;
3175 u8 type;
3176 wchar_t uc[0];
3177} __packed;
3178
3179/* replace non-printable or non-ASCII characters with spaces */
3180static inline char ufshcd_remove_non_printable(u8 ch)
3181{
3182 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3183}
3184
b573d484
YG		 3185/**
3186 * ufshcd_read_string_desc - read string descriptor
3187 * @hba: pointer to adapter instance
3188 * @desc_index: descriptor index
4b828fe1
TW		 3189 * @buf: pointer to buffer where descriptor would be read,
3190 * the caller should free the memory.
b573d484 3191 * @ascii: if true convert from unicode to ascii characters
4b828fe1 3192 * null terminated string.
b573d484 3193 *
4b828fe1
TW		 3194 * Return:
3195 * * string size on success.
3196 * * -ENOMEM: on allocation failure
3197 * * -EINVAL: on a wrong parameter
b573d484 3198 */
4b828fe1
TW		 3199int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3200 u8 **buf, bool ascii)
b573d484 3201{
4b828fe1
TW		 3202 struct uc_string_id *uc_str;
3203 u8 *str;
3204 int ret;
b573d484 3205
4b828fe1
TW		 3206 if (!buf)
3207 return -EINVAL;
b573d484 3208
4b828fe1
TW		 3209 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3210 if (!uc_str)
3211 return -ENOMEM;
b573d484 3212
4b828fe1
TW		 3213 ret = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING,
3214 desc_index, uc_str,
3215 QUERY_DESC_MAX_SIZE);
3216 if (ret < 0) {
3217 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3218 QUERY_REQ_RETRIES, ret);
3219 str = NULL;
3220 goto out;
3221 }
3222
3223 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3224 dev_dbg(hba->dev, "String Desc is of zero length\n");
3225 str = NULL;
3226 ret = 0;
b573d484
YG		 3227 goto out;
3228 }
3229
3230 if (ascii) {
4b828fe1 3231 ssize_t ascii_len;
b573d484 3232 int i;
b573d484 3233 /* remove header and divide by 2 to move from UTF16 to UTF8 */
4b828fe1
TW		 3234 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3235 str = kzalloc(ascii_len, GFP_KERNEL);
3236 if (!str) {
3237 ret = -ENOMEM;
fcbefc3b 3238 goto out;
b573d484
YG		 3239 }
3240
3241 /*
3242 * the descriptor contains string in UTF16 format
3243 * we need to convert to utf-8 so it can be displayed
3244 */
4b828fe1
TW		 3245 ret = utf16s_to_utf8s(uc_str->uc,
3246 uc_str->len - QUERY_DESC_HDR_SIZE,
3247 UTF16_BIG_ENDIAN, str, ascii_len);
b573d484
YG		 3248
3249 /* replace non-printable or non-ASCII characters with spaces */
4b828fe1
TW		 3250 for (i = 0; i < ret; i++)
3251 str[i] = ufshcd_remove_non_printable(str[i]);
b573d484 3252
4b828fe1
TW		 3253 str[ret++] = '\0';
3254
3255 } else {
5f57704d 3256 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
4b828fe1
TW		 3257 if (!str) {
3258 ret = -ENOMEM;
3259 goto out;
3260 }
4b828fe1 3261 ret = uc_str->len;
b573d484
YG		 3262 }
3263out:
4b828fe1
TW		 3264 *buf = str;
3265 kfree(uc_str);
3266 return ret;
b573d484 3267}
b573d484 3268
da461cec
SJ		 3269/**
3270 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3271 * @hba: Pointer to adapter instance
3272 * @lun: lun id
3273 * @param_offset: offset of the parameter to read
3274 * @param_read_buf: pointer to buffer where parameter would be read
3275 * @param_size: sizeof(param_read_buf)
3276 *
3277 * Return 0 in case of success, non-zero otherwise
3278 */
3279static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3280 int lun,
3281 enum unit_desc_param param_offset,
3282 u8 *param_read_buf,
3283 u32 param_size)
3284{
3285 /*
3286 * Unit descriptors are only available for general purpose LUs (LUN id
3287 * from 0 to 7) and RPMB Well known LU.
3288 */
1baa8011 3289 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
da461cec
SJ		 3290 return -EOPNOTSUPP;
3291
3292 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3293 param_offset, param_read_buf, param_size);
3294}
3295
09f17791
CG		 3296static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3297{
3298 int err = 0;
3299 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3300
3301 if (hba->dev_info.wspecversion >= 0x300) {
3302 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3303 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3304 &gating_wait);
3305 if (err)
3306 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3307 err, gating_wait);
3308
3309 if (gating_wait == 0) {
3310 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3311 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3312 gating_wait);
3313 }
3314
3315 hba->dev_info.clk_gating_wait_us = gating_wait;
3316 }
3317
3318 return err;
3319}
3320
7a3e97b0
SY		 3321/**
3322 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3323 * @hba: per adapter instance
3324 *
3325 * 1. Allocate DMA memory for Command Descriptor array
3326 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3327 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3328 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3329 * (UTMRDL)
3330 * 4. Allocate memory for local reference block(lrb).
3331 *
3332 * Returns 0 for success, non-zero in case of failure
3333 */
3334static int ufshcd_memory_alloc(struct ufs_hba *hba)
3335{
3336 size_t utmrdl_size, utrdl_size, ucdl_size;
3337
3338 /* Allocate memory for UTP command descriptors */
3339 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3340 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3341 ucdl_size,
3342 &hba->ucdl_dma_addr,
3343 GFP_KERNEL);
7a3e97b0
SY		 3344
3345 /*
3346 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3347 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3348 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3349 * be aligned to 128 bytes as well
3350 */
3351 if (!hba->ucdl_base_addr ||
3352 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3353 dev_err(hba->dev,
7a3e97b0
SY		 3354 "Command Descriptor Memory allocation failed\n");
3355 goto out;
3356 }
3357
3358 /*
3359 * Allocate memory for UTP Transfer descriptors
3360 * UFSHCI requires 1024 byte alignment of UTRD
3361 */
3362 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3363 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3364 utrdl_size,
3365 &hba->utrdl_dma_addr,
3366 GFP_KERNEL);
7a3e97b0
SY		 3367 if (!hba->utrdl_base_addr ||
3368 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3369 dev_err(hba->dev,
7a3e97b0
SY		 3370 "Transfer Descriptor Memory allocation failed\n");
3371 goto out;
3372 }
3373
3374 /*
3375 * Allocate memory for UTP Task Management descriptors
3376 * UFSHCI requires 1024 byte alignment of UTMRD
3377 */
3378 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3379 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3380 utmrdl_size,
3381 &hba->utmrdl_dma_addr,
3382 GFP_KERNEL);
7a3e97b0
SY		 3383 if (!hba->utmrdl_base_addr ||
3384 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3385 dev_err(hba->dev,
7a3e97b0
SY		 3386 "Task Management Descriptor Memory allocation failed\n");
3387 goto out;
3388 }
3389
3390 /* Allocate memory for local reference block */
a86854d0
KC		 3391 hba->lrb = devm_kcalloc(hba->dev,
3392 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3393 GFP_KERNEL);
7a3e97b0 3394 if (!hba->lrb) {
3b1d0580 3395 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3396 goto out;
3397 }
3398 return 0;
3399out:
7a3e97b0
SY		 3400 return -ENOMEM;
3401}
3402
3403/**
3404 * ufshcd_host_memory_configure - configure local reference block with
3405 * memory offsets
3406 * @hba: per adapter instance
3407 *
3408 * Configure Host memory space
3409 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3410 * address.
3411 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3412 * and PRDT offset.
3413 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3414 * into local reference block.
3415 */
3416static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3417{
7a3e97b0
SY		 3418 struct utp_transfer_req_desc *utrdlp;
3419 dma_addr_t cmd_desc_dma_addr;
3420 dma_addr_t cmd_desc_element_addr;
3421 u16 response_offset;
3422 u16 prdt_offset;
3423 int cmd_desc_size;
3424 int i;
3425
3426 utrdlp = hba->utrdl_base_addr;
7a3e97b0
SY		 3427
3428 response_offset =
3429 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3430 prdt_offset =
3431 offsetof(struct utp_transfer_cmd_desc, prd_table);
3432
3433 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3434 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3435
3436 for (i = 0; i < hba->nutrs; i++) {
3437 /* Configure UTRD with command descriptor base address */
3438 cmd_desc_element_addr =
3439 (cmd_desc_dma_addr + (cmd_desc_size * i));
3440 utrdlp[i].command_desc_base_addr_lo =
3441 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3442 utrdlp[i].command_desc_base_addr_hi =
3443 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3444
3445 /* Response upiu and prdt offset should be in double words */
49200199
CH		 3446 utrdlp[i].response_upiu_offset =
3447 cpu_to_le16(response_offset >> 2);
3448 utrdlp[i].prd_table_offset = cpu_to_le16(prdt_offset >> 2);
3449 utrdlp[i].response_upiu_length =
3450 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0 3451
4d2b8d40 3452 ufshcd_init_lrb(hba, &hba->lrb[i], i);
7a3e97b0
SY		 3453 }
3454}
3455
3456/**
3457 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3458 * @hba: per adapter instance
3459 *
3460 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3461 * in order to initialize the Unipro link startup procedure.
3462 * Once the Unipro links are up, the device connected to the controller
3463 * is detected.
3464 *
3465 * Returns 0 on success, non-zero value on failure
3466 */
3467static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3468{
6ccf44fe
SJ		 3469 struct uic_command uic_cmd = {0};
3470 int ret;
7a3e97b0 3471
6ccf44fe 3472 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3473
6ccf44fe
SJ		 3474 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3475 if (ret)
ff8e20c6 3476 dev_dbg(hba->dev,
6ccf44fe
SJ		 3477 "dme-link-startup: error code %d\n", ret);
3478 return ret;
7a3e97b0
SY		 3479}
3480
cad2e03d
YG		 3481static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3482{
3483 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3484 unsigned long min_sleep_time_us;
3485
3486 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3487 return;
3488
3489 /*
3490 * last_dme_cmd_tstamp will be 0 only for 1st call to
3491 * this function
3492 */
3493 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3494 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3495 } else {
3496 unsigned long delta =
3497 (unsigned long) ktime_to_us(
3498 ktime_sub(ktime_get(),
3499 hba->last_dme_cmd_tstamp));
3500
3501 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3502 min_sleep_time_us =
3503 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3504 else
3505 return; /* no more delay required */
3506 }
3507
3508 /* allow sleep for extra 50us if needed */
3509 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3510}
3511
12b4fdb4
SJ		 3512/**
3513 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3514 * @hba: per adapter instance
3515 * @attr_sel: uic command argument1
3516 * @attr_set: attribute set type as uic command argument2
3517 * @mib_val: setting value as uic command argument3
3518 * @peer: indicate whether peer or local
3519 *
3520 * Returns 0 on success, non-zero value on failure
3521 */
3522int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3523 u8 attr_set, u32 mib_val, u8 peer)
3524{
3525 struct uic_command uic_cmd = {0};
3526 static const char *const action[] = {
3527 "dme-set",
3528 "dme-peer-set"
3529 };
3530 const char *set = action[!!peer];
3531 int ret;
64238fbd 3532 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3533
3534 uic_cmd.command = peer ?
3535 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3536 uic_cmd.argument1 = attr_sel;
3537 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3538 uic_cmd.argument3 = mib_val;
3539
64238fbd
YG		 3540 do {
3541 /* for peer attributes we retry upon failure */
3542 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3543 if (ret)
3544 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3545 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3546 } while (ret && peer && --retries);
3547
f37e9f8c 3548 if (ret)
64238fbd 3549 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3550 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3551 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3552
3553 return ret;
3554}
3555EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3556
3557/**
3558 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3559 * @hba: per adapter instance
3560 * @attr_sel: uic command argument1
3561 * @mib_val: the value of the attribute as returned by the UIC command
3562 * @peer: indicate whether peer or local
3563 *
3564 * Returns 0 on success, non-zero value on failure
3565 */
3566int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3567 u32 *mib_val, u8 peer)
3568{
3569 struct uic_command uic_cmd = {0};
3570 static const char *const action[] = {
3571 "dme-get",
3572 "dme-peer-get"
3573 };
3574 const char *get = action[!!peer];
3575 int ret;
64238fbd 3576 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3577 struct ufs_pa_layer_attr orig_pwr_info;
3578 struct ufs_pa_layer_attr temp_pwr_info;
3579 bool pwr_mode_change = false;
3580
3581 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3582 orig_pwr_info = hba->pwr_info;
3583 temp_pwr_info = orig_pwr_info;
3584
3585 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3586 orig_pwr_info.pwr_rx == FAST_MODE) {
3587 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3588 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3589 pwr_mode_change = true;
3590 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3591 orig_pwr_info.pwr_rx == SLOW_MODE) {
3592 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3593 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3594 pwr_mode_change = true;
3595 }
3596 if (pwr_mode_change) {
3597 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3598 if (ret)
3599 goto out;
3600 }
3601 }
12b4fdb4
SJ		 3602
3603 uic_cmd.command = peer ?
3604 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3605 uic_cmd.argument1 = attr_sel;
3606
64238fbd
YG		 3607 do {
3608 /* for peer attributes we retry upon failure */
3609 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3610 if (ret)
3611 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3612 get, UIC_GET_ATTR_ID(attr_sel), ret);
3613 } while (ret && peer && --retries);
3614
f37e9f8c 3615 if (ret)
64238fbd 3616 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3617 get, UIC_GET_ATTR_ID(attr_sel),
3618 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3619
64238fbd 3620 if (mib_val && !ret)
12b4fdb4 3621 *mib_val = uic_cmd.argument3;
874237f7
YG		 3622
3623 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3624 && pwr_mode_change)
3625 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3626out:
3627 return ret;
3628}
3629EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3630
53b3d9c3 3631/**
57d104c1
SJ		 3632 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3633 * state) and waits for it to take effect.
3634 *
53b3d9c3 3635 * @hba: per adapter instance
57d104c1
SJ		 3636 * @cmd: UIC command to execute
3637 *
3638 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3639 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3640 * and device UniPro link and hence it's final completion would be indicated by
3641 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3642 * addition to normal UIC command completion Status (UCCS). This function only
3643 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3644 *
3645 * Returns 0 on success, non-zero value on failure
3646 */
57d104c1 3647static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3648{
57d104c1 3649 struct completion uic_async_done;
53b3d9c3
SJ		 3650 unsigned long flags;
3651 u8 status;
3652 int ret;
d75f7fe4 3653 bool reenable_intr = false;
53b3d9c3 3654
53b3d9c3 3655 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3656 init_completion(&uic_async_done);
cad2e03d 3657 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3658
3659 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3660 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3661 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3662 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3663 /*
3664 * Make sure UIC command completion interrupt is disabled before
3665 * issuing UIC command.
3666 */
3667 wmb();
3668 reenable_intr = true;
57d104c1 3669 }
d75f7fe4
YG		 3670 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3671 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3672 if (ret) {
3673 dev_err(hba->dev,
3674 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3675 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3676 goto out;
3677 }
3678
57d104c1 3679 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3680 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3681 dev_err(hba->dev,
57d104c1
SJ		 3682 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3683 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3684 ret = -ETIMEDOUT;
3685 goto out;
3686 }
3687
3688 status = ufshcd_get_upmcrs(hba);
3689 if (status != PWR_LOCAL) {
3690 dev_err(hba->dev,
479da360 3691 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3692 cmd->command, status);
53b3d9c3
SJ		 3693 ret = (status != PWR_OK) ? status : -1;
3694 }
3695out:
7942f7b5
VG		 3696 if (ret) {
3697 ufshcd_print_host_state(hba);
3698 ufshcd_print_pwr_info(hba);
3699 ufshcd_print_host_regs(hba);
3700 }
3701
53b3d9c3 3702 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3703 hba->active_uic_cmd = NULL;
57d104c1 3704 hba->uic_async_done = NULL;
d75f7fe4
YG		 3705 if (reenable_intr)
3706 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3707 spin_unlock_irqrestore(hba->host->host_lock, flags);
3708 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3709
53b3d9c3
SJ		 3710 return ret;
3711}
3712
57d104c1
SJ		 3713/**
3714 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3715 * using DME_SET primitives.
3716 * @hba: per adapter instance
3717 * @mode: powr mode value
3718 *
3719 * Returns 0 on success, non-zero value on failure
3720 */
3721static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3722{
3723 struct uic_command uic_cmd = {0};
1ab27c9c 3724 int ret;
57d104c1 3725
c3a2f9ee
YG		 3726 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3727 ret = ufshcd_dme_set(hba,
3728 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3729 if (ret) {
3730 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3731 __func__, ret);
3732 goto out;
3733 }
3734 }
3735
57d104c1
SJ		 3736 uic_cmd.command = UIC_CMD_DME_SET;
3737 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3738 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3739 ufshcd_hold(hba, false);
3740 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3741 ufshcd_release(hba);
57d104c1 3742
c3a2f9ee 3743out:
1ab27c9c 3744 return ret;
57d104c1
SJ		 3745}
3746
53c12d0e
YG		 3747static int ufshcd_link_recovery(struct ufs_hba *hba)
3748{
3749 int ret;
3750 unsigned long flags;
3751
3752 spin_lock_irqsave(hba->host->host_lock, flags);
3753 hba->ufshcd_state = UFSHCD_STATE_RESET;
3754 ufshcd_set_eh_in_progress(hba);
3755 spin_unlock_irqrestore(hba->host->host_lock, flags);
3756
ebdd1dfd
CG		 3757 /* Reset the attached device */
3758 ufshcd_vops_device_reset(hba);
3759
53c12d0e
YG		 3760 ret = ufshcd_host_reset_and_restore(hba);
3761
3762 spin_lock_irqsave(hba->host->host_lock, flags);
3763 if (ret)
3764 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3765 ufshcd_clear_eh_in_progress(hba);
3766 spin_unlock_irqrestore(hba->host->host_lock, flags);
3767
3768 if (ret)
3769 dev_err(hba->dev, "%s: link recovery failed, err %d",
3770 __func__, ret);
3771
3772 return ret;
3773}
3774
87d0b4a6 3775static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3776{
87d0b4a6 3777 int ret;
57d104c1 3778 struct uic_command uic_cmd = {0};
911a0771 3779 ktime_t start = ktime_get();
57d104c1 3780
ee32c909
KK		 3781 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3782
57d104c1 3783 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3784 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3785 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3786 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3787
53c12d0e 3788 if (ret) {
6d303e4b
SJ		 3789 int err;
3790
87d0b4a6
YG		 3791 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3792 __func__, ret);
3793
53c12d0e 3794 /*
6d303e4b
SJ		 3795 * If link recovery fails then return error code returned from
3796 * ufshcd_link_recovery().
3797 * If link recovery succeeds then return -EAGAIN to attempt
3798 * hibern8 enter retry again.
53c12d0e 3799 */
6d303e4b
SJ		 3800 err = ufshcd_link_recovery(hba);
3801 if (err) {
3802 dev_err(hba->dev, "%s: link recovery failed", __func__);
3803 ret = err;
3804 } else {
3805 ret = -EAGAIN;
3806 }
ee32c909
KK		 3807 } else
3808 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3809 POST_CHANGE);
53c12d0e 3810
87d0b4a6
YG		 3811 return ret;
3812}
3813
3814static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3815{
3816 int ret = 0, retries;
57d104c1 3817
87d0b4a6
YG		 3818 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3819 ret = __ufshcd_uic_hibern8_enter(hba);
6d303e4b 3820 if (!ret)
87d0b4a6
YG		 3821 goto out;
3822 }
3823out:
3824 return ret;
57d104c1
SJ		 3825}
3826
9d19bf7a 3827int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
57d104c1
SJ		 3828{
3829 struct uic_command uic_cmd = {0};
3830 int ret;
911a0771 3831 ktime_t start = ktime_get();
57d104c1 3832
ee32c909
KK		 3833 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3834
57d104c1
SJ		 3835 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3836 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3837 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3838 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3839
57d104c1 3840 if (ret) {
53c12d0e
YG		 3841 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3842 __func__, ret);
3843 ret = ufshcd_link_recovery(hba);
ff8e20c6 3844 } else {
ee32c909
KK		 3845 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3846 POST_CHANGE);
ff8e20c6
DR		 3847 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3848 hba->ufs_stats.hibern8_exit_cnt++;
3849 }
57d104c1
SJ		 3850
3851 return ret;
3852}
9d19bf7a 3853EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
57d104c1 3854
ba7af5ec
SC		 3855void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
3856{
3857 unsigned long flags;
3858
3859 if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT))
3860 return;
3861
3862 spin_lock_irqsave(hba->host->host_lock, flags);
3863 if (hba->ahit == ahit)
3864 goto out_unlock;
3865 hba->ahit = ahit;
3866 if (!pm_runtime_suspended(hba->dev))
3867 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3868out_unlock:
3869 spin_unlock_irqrestore(hba->host->host_lock, flags);
3870}
3871EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
3872
71d848b8 3873void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
ad448378
AH		 3874{
3875 unsigned long flags;
3876
ee5f1042 3877 if (!ufshcd_is_auto_hibern8_supported(hba) || !hba->ahit)
ad448378
AH		 3878 return;
3879
3880 spin_lock_irqsave(hba->host->host_lock, flags);
3881 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3882 spin_unlock_irqrestore(hba->host->host_lock, flags);
3883}
3884
5064636c
YG		 3885 /**
3886 * ufshcd_init_pwr_info - setting the POR (power on reset)
3887 * values in hba power info
3888 * @hba: per-adapter instance
3889 */
3890static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3891{
3892 hba->pwr_info.gear_rx = UFS_PWM_G1;
3893 hba->pwr_info.gear_tx = UFS_PWM_G1;
3894 hba->pwr_info.lane_rx = 1;
3895 hba->pwr_info.lane_tx = 1;
3896 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3897 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3898 hba->pwr_info.hs_rate = 0;
3899}
3900
d3e89bac 3901/**
7eb584db
DR		 3902 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3903 * @hba: per-adapter instance
d3e89bac 3904 */
7eb584db 3905static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3906{
7eb584db
DR		 3907 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3908
3909 if (hba->max_pwr_info.is_valid)
3910 return 0;
3911
2349b533
SJ		 3912 pwr_info->pwr_tx = FAST_MODE;
3913 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3914 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3915
3916 /* Get the connected lane count */
7eb584db
DR		 3917 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3918 &pwr_info->lane_rx);
3919 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3920 &pwr_info->lane_tx);
3921
3922 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3923 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3924 __func__,
3925 pwr_info->lane_rx,
3926 pwr_info->lane_tx);
3927 return -EINVAL;
3928 }
d3e89bac
SJ		 3929
3930 /*
3931 * First, get the maximum gears of HS speed.
3932 * If a zero value, it means there is no HSGEAR capability.
3933 * Then, get the maximum gears of PWM speed.
3934 */
7eb584db
DR		 3935 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3936 if (!pwr_info->gear_rx) {
3937 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3938 &pwr_info->gear_rx);
3939 if (!pwr_info->gear_rx) {
3940 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3941 __func__, pwr_info->gear_rx);
3942 return -EINVAL;
3943 }
2349b533 3944 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3945 }
3946
7eb584db
DR		 3947 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3948 &pwr_info->gear_tx);
3949 if (!pwr_info->gear_tx) {
d3e89bac 3950 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3951 &pwr_info->gear_tx);
3952 if (!pwr_info->gear_tx) {
3953 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3954 __func__, pwr_info->gear_tx);
3955 return -EINVAL;
3956 }
2349b533 3957 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3958 }
3959
3960 hba->max_pwr_info.is_valid = true;
3961 return 0;
3962}
3963
3964static int ufshcd_change_power_mode(struct ufs_hba *hba,
3965 struct ufs_pa_layer_attr *pwr_mode)
3966{
3967 int ret;
3968
3969 /* if already configured to the requested pwr_mode */
3970 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3971 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3972 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3973 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
3974 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
3975 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
3976 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
3977 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
3978 return 0;
d3e89bac
SJ		 3979 }
3980
3981 /*
3982 * Configure attributes for power mode change with below.
3983 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
3984 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
3985 * - PA_HSSERIES
3986 */
7eb584db
DR		 3987 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
3988 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
3989 pwr_mode->lane_rx);
3990 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3991 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 3992 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 3993 else
3994 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 3995
7eb584db
DR		 3996 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
3997 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
3998 pwr_mode->lane_tx);
3999 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4000 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4001 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4002 else
4003 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4004
7eb584db
DR		 4005 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4006 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4007 pwr_mode->pwr_rx == FAST_MODE ||
4008 pwr_mode->pwr_tx == FAST_MODE)
4009 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4010 pwr_mode->hs_rate);
d3e89bac 4011
08342537
CG		 4012 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4013 DL_FC0ProtectionTimeOutVal_Default);
4014 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4015 DL_TC0ReplayTimeOutVal_Default);
4016 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4017 DL_AFC0ReqTimeOutVal_Default);
4018 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4019 DL_FC1ProtectionTimeOutVal_Default);
4020 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4021 DL_TC1ReplayTimeOutVal_Default);
4022 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4023 DL_AFC1ReqTimeOutVal_Default);
4024
4025 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4026 DL_FC0ProtectionTimeOutVal_Default);
4027 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4028 DL_TC0ReplayTimeOutVal_Default);
4029 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4030 DL_AFC0ReqTimeOutVal_Default);
4031
7eb584db
DR		 4032 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4033 | pwr_mode->pwr_tx);
4034
4035 if (ret) {
d3e89bac 4036 dev_err(hba->dev,
7eb584db
DR		 4037 "%s: power mode change failed %d\n", __func__, ret);
4038 } else {
0263bcd0
YG		 4039 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4040 pwr_mode);
7eb584db
DR		 4041
4042 memcpy(&hba->pwr_info, pwr_mode,
4043 sizeof(struct ufs_pa_layer_attr));
4044 }
4045
4046 return ret;
4047}
4048
4049/**
4050 * ufshcd_config_pwr_mode - configure a new power mode
4051 * @hba: per-adapter instance
4052 * @desired_pwr_mode: desired power configuration
4053 */
0d846e70 4054int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4055 struct ufs_pa_layer_attr *desired_pwr_mode)
4056{
4057 struct ufs_pa_layer_attr final_params = { 0 };
4058 int ret;
4059
0263bcd0
YG		 4060 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4061 desired_pwr_mode, &final_params);
4062
4063 if (ret)
7eb584db
DR		 4064 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4065
4066 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5
SJ		 4067 if (!ret)
4068 ufshcd_print_pwr_info(hba);
d3e89bac
SJ		 4069
4070 return ret;
4071}
0d846e70 4072EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4073
68078d5c
DR		 4074/**
4075 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4076 * @hba: per-adapter instance
68078d5c
DR		 4077 *
4078 * Set fDeviceInit flag and poll until device toggles it.
4079 */
4080static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4081{
dc3c8d3a
YG		 4082 int i;
4083 int err;
68078d5c
DR		 4084 bool flag_res = 1;
4085
dc3c8d3a
YG		 4086 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4087 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 4088 if (err) {
4089 dev_err(hba->dev,
4090 "%s setting fDeviceInit flag failed with error %d\n",
4091 __func__, err);
4092 goto out;
4093 }
4094
dc3c8d3a
YG		 4095 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4096 for (i = 0; i < 1000 && !err && flag_res; i++)
4097 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4098 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4099
68078d5c
DR		 4100 if (err)
4101 dev_err(hba->dev,
4102 "%s reading fDeviceInit flag failed with error %d\n",
4103 __func__, err);
4104 else if (flag_res)
4105 dev_err(hba->dev,
4106 "%s fDeviceInit was not cleared by the device\n",
4107 __func__);
4108
4109out:
4110 return err;
4111}
4112
7a3e97b0
SY		 4113/**
4114 * ufshcd_make_hba_operational - Make UFS controller operational
4115 * @hba: per adapter instance
4116 *
4117 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4118 * 1. Enable required interrupts
4119 * 2. Configure interrupt aggregation
897efe62 4120 * 3. Program UTRL and UTMRL base address
5c0c28a8 4121 * 4. Configure run-stop-registers
7a3e97b0
SY		 4122 *
4123 * Returns 0 on success, non-zero value on failure
4124 */
9d19bf7a 4125int ufshcd_make_hba_operational(struct ufs_hba *hba)
7a3e97b0
SY		 4126{
4127 int err = 0;
4128 u32 reg;
4129
6ccf44fe
SJ		 4130 /* Enable required interrupts */
4131 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4132
4133 /* Configure interrupt aggregation */
b852190e
YG		 4134 if (ufshcd_is_intr_aggr_allowed(hba))
4135 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4136 else
4137 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4138
4139 /* Configure UTRL and UTMRL base address registers */
4140 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4141 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4142 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4143 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4144 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4145 REG_UTP_TASK_REQ_LIST_BASE_L);
4146 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4147 REG_UTP_TASK_REQ_LIST_BASE_H);
4148
897efe62
YG		 4149 /*
4150 * Make sure base address and interrupt setup are updated before
4151 * enabling the run/stop registers below.
4152 */
4153 wmb();
4154
7a3e97b0
SY		 4155 /*
4156 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4157 */
5c0c28a8 4158 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4159 if (!(ufshcd_get_lists_status(reg))) {
4160 ufshcd_enable_run_stop_reg(hba);
4161 } else {
3b1d0580 4162 dev_err(hba->dev,
7a3e97b0
SY		 4163 "Host controller not ready to process requests");
4164 err = -EIO;
4165 goto out;
4166 }
4167
7a3e97b0
SY		 4168out:
4169 return err;
4170}
9d19bf7a 4171EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
7a3e97b0 4172
596585a2
YG		 4173/**
4174 * ufshcd_hba_stop - Send controller to reset state
4175 * @hba: per adapter instance
4176 * @can_sleep: perform sleep or just spin
4177 */
4178static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4179{
4180 int err;
4181
4182 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4183 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4184 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4185 10, 1, can_sleep);
4186 if (err)
4187 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4188}
4189
7a3e97b0 4190/**
49200199 4191 * ufshcd_hba_enable - initialize the controller
7a3e97b0
SY		 4192 * @hba: per adapter instance
4193 *
4194 * The controller resets itself and controller firmware initialization
4195 * sequence kicks off. When controller is ready it will set
4196 * the Host Controller Enable bit to 1.
4197 *
4198 * Returns 0 on success, non-zero value on failure
4199 */
49200199 4200int ufshcd_hba_enable(struct ufs_hba *hba)
7a3e97b0
SY		 4201{
4202 int retry;
4203
596585a2 4204 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4205 /* change controller state to "reset state" */
596585a2 4206 ufshcd_hba_stop(hba, true);
7a3e97b0 4207
57d104c1
SJ		 4208 /* UniPro link is disabled at this point */
4209 ufshcd_set_link_off(hba);
4210
0263bcd0 4211 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4212
7a3e97b0
SY		 4213 /* start controller initialization sequence */
4214 ufshcd_hba_start(hba);
4215
4216 /*
4217 * To initialize a UFS host controller HCE bit must be set to 1.
4218 * During initialization the HCE bit value changes from 1->0->1.
4219 * When the host controller completes initialization sequence
4220 * it sets the value of HCE bit to 1. The same HCE bit is read back
4221 * to check if the controller has completed initialization sequence.
4222 * So without this delay the value HCE = 1, set in the previous
4223 * instruction might be read back.
4224 * This delay can be changed based on the controller.
4225 */
838c1efc 4226 usleep_range(1000, 1100);
7a3e97b0
SY		 4227
4228 /* wait for the host controller to complete initialization */
4229 retry = 10;
4230 while (ufshcd_is_hba_active(hba)) {
4231 if (retry) {
4232 retry--;
4233 } else {
3b1d0580 4234 dev_err(hba->dev,
7a3e97b0
SY		 4235 "Controller enable failed\n");
4236 return -EIO;
4237 }
838c1efc 4238 usleep_range(5000, 5100);
7a3e97b0 4239 }
5c0c28a8 4240
1d337ec2 4241 /* enable UIC related interrupts */
57d104c1 4242 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4243
0263bcd0 4244 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4245
7a3e97b0
SY		 4246 return 0;
4247}
9d19bf7a
SC		 4248EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4249
7ca38cf3
YG		 4250static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4251{
ba0320fb 4252 int tx_lanes = 0, i, err = 0;
7ca38cf3
YG		 4253
4254 if (!peer)
4255 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4256 &tx_lanes);
4257 else
4258 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4259 &tx_lanes);
4260 for (i = 0; i < tx_lanes; i++) {
4261 if (!peer)
4262 err = ufshcd_dme_set(hba,
4263 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4264 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4265 0);
4266 else
4267 err = ufshcd_dme_peer_set(hba,
4268 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4269 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4270 0);
4271 if (err) {
4272 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4273 __func__, peer, i, err);
4274 break;
4275 }
4276 }
4277
4278 return err;
4279}
4280
4281static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4282{
4283 return ufshcd_disable_tx_lcc(hba, true);
4284}
4285
a5fe372d
SC		 4286void ufshcd_update_reg_hist(struct ufs_err_reg_hist *reg_hist,
4287 u32 reg)
8808b4e9
SC		 4288{
4289 reg_hist->reg[reg_hist->pos] = reg;
4290 reg_hist->tstamp[reg_hist->pos] = ktime_get();
4291 reg_hist->pos = (reg_hist->pos + 1) % UFS_ERR_REG_HIST_LENGTH;
4292}
a5fe372d 4293EXPORT_SYMBOL_GPL(ufshcd_update_reg_hist);
8808b4e9 4294
7a3e97b0 4295/**
6ccf44fe 4296 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4297 * @hba: per adapter instance
4298 *
6ccf44fe 4299 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4300 */
6ccf44fe 4301static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4302{
6ccf44fe 4303 int ret;
1d337ec2 4304 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4305 bool link_startup_again = false;
7a3e97b0 4306
7caf489b
SJ		 4307 /*
4308 * If UFS device isn't active then we will have to issue link startup
4309 * 2 times to make sure the device state move to active.
4310 */
4311 if (!ufshcd_is_ufs_dev_active(hba))
4312 link_startup_again = true;
7a3e97b0 4313
7caf489b 4314link_startup:
1d337ec2 4315 do {
0263bcd0 4316 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4317
1d337ec2 4318 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4319
1d337ec2
SRT		 4320 /* check if device is detected by inter-connect layer */
4321 if (!ret && !ufshcd_is_device_present(hba)) {
8808b4e9
SC		 4322 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4323 0);
1d337ec2
SRT		 4324 dev_err(hba->dev, "%s: Device not present\n", __func__);
4325 ret = -ENXIO;
4326 goto out;
4327 }
6ccf44fe 4328
1d337ec2
SRT		 4329 /*
4330 * DME link lost indication is only received when link is up,
4331 * but we can't be sure if the link is up until link startup
4332 * succeeds. So reset the local Uni-Pro and try again.
4333 */
8808b4e9
SC		 4334 if (ret && ufshcd_hba_enable(hba)) {
4335 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4336 (u32)ret);
1d337ec2 4337 goto out;
8808b4e9 4338 }
1d337ec2
SRT		 4339 } while (ret && retries--);
4340
8808b4e9 4341 if (ret) {
1d337ec2 4342 /* failed to get the link up... retire */
8808b4e9
SC		 4343 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4344 (u32)ret);
5c0c28a8 4345 goto out;
8808b4e9 4346 }
5c0c28a8 4347
7caf489b
SJ		 4348 if (link_startup_again) {
4349 link_startup_again = false;
4350 retries = DME_LINKSTARTUP_RETRIES;
4351 goto link_startup;
4352 }
4353
d2aebb9b
SJ		 4354 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4355 ufshcd_init_pwr_info(hba);
4356 ufshcd_print_pwr_info(hba);
4357
7ca38cf3
YG		 4358 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4359 ret = ufshcd_disable_device_tx_lcc(hba);
4360 if (ret)
4361 goto out;
4362 }
4363
5c0c28a8 4364 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4365 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4366 if (ret)
4367 goto out;
7a3e97b0 4368
5c0c28a8 4369 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4370out:
7942f7b5 4371 if (ret) {
6ccf44fe 4372 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4373 ufshcd_print_host_state(hba);
4374 ufshcd_print_pwr_info(hba);
4375 ufshcd_print_host_regs(hba);
4376 }
6ccf44fe 4377 return ret;
7a3e97b0
SY		 4378}
4379
5a0b0cb9
SRT		 4380/**
4381 * ufshcd_verify_dev_init() - Verify device initialization
4382 * @hba: per-adapter instance
4383 *
4384 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4385 * device Transport Protocol (UTP) layer is ready after a reset.
4386 * If the UTP layer at the device side is not initialized, it may
4387 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4388 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4389 */
4390static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4391{
4392 int err = 0;
4393 int retries;
4394
1ab27c9c 4395 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4396 mutex_lock(&hba->dev_cmd.lock);
4397 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4398 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4399 NOP_OUT_TIMEOUT);
4400
4401 if (!err || err == -ETIMEDOUT)
4402 break;
4403
4404 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4405 }
4406 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4407 ufshcd_release(hba);
5a0b0cb9
SRT		 4408
4409 if (err)
4410 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4411 return err;
4412}
4413
0ce147d4
SJ		 4414/**
4415 * ufshcd_set_queue_depth - set lun queue depth
4416 * @sdev: pointer to SCSI device
4417 *
4418 * Read bLUQueueDepth value and activate scsi tagged command
4419 * queueing. For WLUN, queue depth is set to 1. For best-effort
4420 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4421 * value that host can queue.
4422 */
4423static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4424{
4425 int ret = 0;
4426 u8 lun_qdepth;
4427 struct ufs_hba *hba;
4428
4429 hba = shost_priv(sdev->host);
4430
4431 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4432 ret = ufshcd_read_unit_desc_param(hba,
4433 ufshcd_scsi_to_upiu_lun(sdev->lun),
4434 UNIT_DESC_PARAM_LU_Q_DEPTH,
4435 &lun_qdepth,
4436 sizeof(lun_qdepth));
0ce147d4
SJ		 4437
4438 /* Some WLUN doesn't support unit descriptor */
4439 if (ret == -EOPNOTSUPP)
4440 lun_qdepth = 1;
4441 else if (!lun_qdepth)
4442 /* eventually, we can figure out the real queue depth */
4443 lun_qdepth = hba->nutrs;
4444 else
4445 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4446
4447 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4448 __func__, lun_qdepth);
db5ed4df 4449 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4450}
4451
57d104c1
SJ		 4452/*
4453 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4454 * @hba: per-adapter instance
4455 * @lun: UFS device lun id
4456 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4457 *
4458 * Returns 0 in case of success and b_lu_write_protect status would be returned
4459 * @b_lu_write_protect parameter.
4460 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4461 * Returns -EINVAL in case of invalid parameters passed to this function.
4462 */
4463static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4464 u8 lun,
4465 u8 *b_lu_write_protect)
4466{
4467 int ret;
4468
4469 if (!b_lu_write_protect)
4470 ret = -EINVAL;
4471 /*
4472 * According to UFS device spec, RPMB LU can't be write
4473 * protected so skip reading bLUWriteProtect parameter for
4474 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4475 */
1baa8011 4476 else if (lun >= hba->dev_info.max_lu_supported)
57d104c1
SJ		 4477 ret = -ENOTSUPP;
4478 else
4479 ret = ufshcd_read_unit_desc_param(hba,
4480 lun,
4481 UNIT_DESC_PARAM_LU_WR_PROTECT,
4482 b_lu_write_protect,
4483 sizeof(*b_lu_write_protect));
4484 return ret;
4485}
4486
4487/**
4488 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4489 * status
4490 * @hba: per-adapter instance
4491 * @sdev: pointer to SCSI device
4492 *
4493 */
4494static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4495 struct scsi_device *sdev)
4496{
4497 if (hba->dev_info.f_power_on_wp_en &&
4498 !hba->dev_info.is_lu_power_on_wp) {
4499 u8 b_lu_write_protect;
4500
4501 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4502 &b_lu_write_protect) &&
4503 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4504 hba->dev_info.is_lu_power_on_wp = true;
4505 }
4506}
4507
7a3e97b0
SY		 4508/**
4509 * ufshcd_slave_alloc - handle initial SCSI device configurations
4510 * @sdev: pointer to SCSI device
4511 *
4512 * Returns success
4513 */
4514static int ufshcd_slave_alloc(struct scsi_device *sdev)
4515{
4516 struct ufs_hba *hba;
4517
4518 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4519
4520 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4521 sdev->use_10_for_ms = 1;
a3a76391
CG		 4522
4523 /* DBD field should be set to 1 in mode sense(10) */
4524 sdev->set_dbd_for_ms = 1;
7a3e97b0 4525
e8e7f271
SRT		 4526 /* allow SCSI layer to restart the device in case of errors */
4527 sdev->allow_restart = 1;
4264fd61 4528
b2a6c522
SRT		 4529 /* REPORT SUPPORTED OPERATION CODES is not supported */
4530 sdev->no_report_opcodes = 1;
4531
84af7e8b
SRT		 4532 /* WRITE_SAME command is not supported */
4533 sdev->no_write_same = 1;
e8e7f271 4534
0ce147d4 4535 ufshcd_set_queue_depth(sdev);
4264fd61 4536
57d104c1
SJ		 4537 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4538
7a3e97b0
SY		 4539 return 0;
4540}
4541
4264fd61
SRT		 4542/**
4543 * ufshcd_change_queue_depth - change queue depth
4544 * @sdev: pointer to SCSI device
4545 * @depth: required depth to set
4264fd61 4546 *
db5ed4df 4547 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4548 */
db5ed4df 4549static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4550{
4551 struct ufs_hba *hba = shost_priv(sdev->host);
4552
4553 if (depth > hba->nutrs)
4554 depth = hba->nutrs;
db5ed4df 4555 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4556}
4557
eeda4749
AM		 4558/**
4559 * ufshcd_slave_configure - adjust SCSI device configurations
4560 * @sdev: pointer to SCSI device
4561 */
4562static int ufshcd_slave_configure(struct scsi_device *sdev)
4563{
49615ba1 4564 struct ufs_hba *hba = shost_priv(sdev->host);
eeda4749
AM		 4565 struct request_queue *q = sdev->request_queue;
4566
4567 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
49615ba1
SC		 4568
4569 if (ufshcd_is_rpm_autosuspend_allowed(hba))
4570 sdev->rpm_autosuspend = 1;
4571
eeda4749
AM		 4572 return 0;
4573}
4574
7a3e97b0
SY		 4575/**
4576 * ufshcd_slave_destroy - remove SCSI device configurations
4577 * @sdev: pointer to SCSI device
4578 */
4579static void ufshcd_slave_destroy(struct scsi_device *sdev)
4580{
4581 struct ufs_hba *hba;
4582
4583 hba = shost_priv(sdev->host);
0ce147d4 4584 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4585 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4586 unsigned long flags;
4587
4588 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4589 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4590 spin_unlock_irqrestore(hba->host->host_lock, flags);
4591 }
7a3e97b0
SY		 4592}
4593
7a3e97b0
SY		 4594/**
4595 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 4596 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4597 * @scsi_status: SCSI command status
4598 *
4599 * Returns value base on SCSI command status
4600 */
4601static inline int
4602ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4603{
4604 int result = 0;
4605
4606 switch (scsi_status) {
7a3e97b0 4607 case SAM_STAT_CHECK_CONDITION:
1c2623c5 4608 ufshcd_copy_sense_data(lrbp);
30eb2e4c 4609 /* fallthrough */
1c2623c5 4610 case SAM_STAT_GOOD:
7a3e97b0
SY		 4611 result |= DID_OK << 16 |
4612 COMMAND_COMPLETE << 8 |
1c2623c5 4613 scsi_status;
7a3e97b0
SY		 4614 break;
4615 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4616 case SAM_STAT_BUSY:
7a3e97b0 4617 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4618 ufshcd_copy_sense_data(lrbp);
4619 result |= scsi_status;
7a3e97b0
SY		 4620 break;
4621 default:
4622 result |= DID_ERROR << 16;
4623 break;
4624 } /* end of switch */
4625
4626 return result;
4627}
4628
4629/**
4630 * ufshcd_transfer_rsp_status - Get overall status of the response
4631 * @hba: per adapter instance
8aa29f19 4632 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4633 *
4634 * Returns result of the command to notify SCSI midlayer
4635 */
4636static inline int
4637ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4638{
4639 int result = 0;
4640 int scsi_status;
4641 int ocs;
4642
4643 /* overall command status of utrd */
4644 ocs = ufshcd_get_tr_ocs(lrbp);
4645
4646 switch (ocs) {
4647 case OCS_SUCCESS:
5a0b0cb9 4648 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4649 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4650 switch (result) {
4651 case UPIU_TRANSACTION_RESPONSE:
4652 /*
4653 * get the response UPIU result to extract
4654 * the SCSI command status
4655 */
4656 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4657
4658 /*
4659 * get the result based on SCSI status response
4660 * to notify the SCSI midlayer of the command status
4661 */
4662 scsi_status = result & MASK_SCSI_STATUS;
4663 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4664
f05ac2e5
YG		 4665 /*
4666 * Currently we are only supporting BKOPs exception
4667 * events hence we can ignore BKOPs exception event
4668 * during power management callbacks. BKOPs exception
4669 * event is not expected to be raised in runtime suspend
4670 * callback as it allows the urgent bkops.
4671 * During system suspend, we are anyway forcefully
4672 * disabling the bkops and if urgent bkops is needed
4673 * it will be enabled on system resume. Long term
4674 * solution could be to abort the system suspend if
4675 * UFS device needs urgent BKOPs.
4676 */
4677 if (!hba->pm_op_in_progress &&
2824ec9f
SL		 4678 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr) &&
4679 schedule_work(&hba->eeh_work)) {
4680 /*
4681 * Prevent suspend once eeh_work is scheduled
4682 * to avoid deadlock between ufshcd_suspend
4683 * and exception event handler.
4684 */
4685 pm_runtime_get_noresume(hba->dev);
4686 }
5a0b0cb9
SRT		 4687 break;
4688 case UPIU_TRANSACTION_REJECT_UPIU:
4689 /* TODO: handle Reject UPIU Response */
4690 result = DID_ERROR << 16;
3b1d0580 4691 dev_err(hba->dev,
5a0b0cb9
SRT		 4692 "Reject UPIU not fully implemented\n");
4693 break;
4694 default:
5a0b0cb9
SRT		 4695 dev_err(hba->dev,
4696 "Unexpected request response code = %x\n",
4697 result);
e0347d89 4698 result = DID_ERROR << 16;
7a3e97b0
SY		 4699 break;
4700 }
7a3e97b0
SY		 4701 break;
4702 case OCS_ABORTED:
4703 result |= DID_ABORT << 16;
4704 break;
e8e7f271
SRT		 4705 case OCS_INVALID_COMMAND_STATUS:
4706 result |= DID_REQUEUE << 16;
4707 break;
7a3e97b0
SY		 4708 case OCS_INVALID_CMD_TABLE_ATTR:
4709 case OCS_INVALID_PRDT_ATTR:
4710 case OCS_MISMATCH_DATA_BUF_SIZE:
4711 case OCS_MISMATCH_RESP_UPIU_SIZE:
4712 case OCS_PEER_COMM_FAILURE:
4713 case OCS_FATAL_ERROR:
4714 default:
4715 result |= DID_ERROR << 16;
3b1d0580 4716 dev_err(hba->dev,
ff8e20c6
DR		 4717 "OCS error from controller = %x for tag %d\n",
4718 ocs, lrbp->task_tag);
4719 ufshcd_print_host_regs(hba);
6ba65588 4720 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4721 break;
4722 } /* end of switch */
4723
2df74b69 4724 if ((host_byte(result) != DID_OK) && !hba->silence_err_logs)
66cc820f 4725 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4726 return result;
4727}
4728
6ccf44fe
SJ		 4729/**
4730 * ufshcd_uic_cmd_compl - handle completion of uic command
4731 * @hba: per adapter instance
53b3d9c3 4732 * @intr_status: interrupt status generated by the controller
9333d775
VG		 4733 *
4734 * Returns
4735 * IRQ_HANDLED - If interrupt is valid
4736 * IRQ_NONE - If invalid interrupt
6ccf44fe 4737 */
9333d775 4738static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4739{
9333d775
VG		 4740 irqreturn_t retval = IRQ_NONE;
4741
53b3d9c3 4742 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4743 hba->active_uic_cmd->argument2 |=
4744 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4745 hba->active_uic_cmd->argument3 =
4746 ufshcd_get_dme_attr_val(hba);
6ccf44fe 4747 complete(&hba->active_uic_cmd->done);
9333d775 4748 retval = IRQ_HANDLED;
6ccf44fe 4749 }
53b3d9c3 4750
9333d775 4751 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
57d104c1 4752 complete(hba->uic_async_done);
9333d775
VG		 4753 retval = IRQ_HANDLED;
4754 }
4755 return retval;
6ccf44fe
SJ		 4756}
4757
7a3e97b0 4758/**
9a47ec7c 4759 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4760 * @hba: per adapter instance
9a47ec7c 4761 * @completed_reqs: requests to complete
7a3e97b0 4762 */
9a47ec7c
YG		 4763static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4764 unsigned long completed_reqs)
7a3e97b0 4765{
5a0b0cb9
SRT		 4766 struct ufshcd_lrb *lrbp;
4767 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4768 int result;
4769 int index;
e9d501b1 4770
e9d501b1
DR		 4771 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4772 lrbp = &hba->lrb[index];
4773 cmd = lrbp->cmd;
4774 if (cmd) {
1a07f2d9 4775 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4776 result = ufshcd_transfer_rsp_status(hba, lrbp);
4777 scsi_dma_unmap(cmd);
4778 cmd->result = result;
4779 /* Mark completed command as NULL in LRB */
4780 lrbp->cmd = NULL;
74a527a2 4781 lrbp->compl_time_stamp = ktime_get();
e9d501b1
DR		 4782 /* Do not touch lrbp after scsi done */
4783 cmd->scsi_done(cmd);
1ab27c9c 4784 __ufshcd_release(hba);
300bb13f
JP		 4785 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4786 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
74a527a2 4787 lrbp->compl_time_stamp = ktime_get();
1a07f2d9
LS		 4788 if (hba->dev_cmd.complete) {
4789 ufshcd_add_command_trace(hba, index,
4790 "dev_complete");
e9d501b1 4791 complete(hba->dev_cmd.complete);
1a07f2d9 4792 }
e9d501b1 4793 }
401f1e44
SJ		 4794 if (ufshcd_is_clkscaling_supported(hba))
4795 hba->clk_scaling.active_reqs--;
e9d501b1 4796 }
7a3e97b0
SY		 4797
4798 /* clear corresponding bits of completed commands */
4799 hba->outstanding_reqs ^= completed_reqs;
4800
856b3483 4801 ufshcd_clk_scaling_update_busy(hba);
7a3e97b0
SY		 4802}
4803
9a47ec7c
YG		 4804/**
4805 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4806 * @hba: per adapter instance
9333d775
VG		 4807 *
4808 * Returns
4809 * IRQ_HANDLED - If interrupt is valid
4810 * IRQ_NONE - If invalid interrupt
9a47ec7c 4811 */
9333d775 4812static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
9a47ec7c
YG		 4813{
4814 unsigned long completed_reqs;
4815 u32 tr_doorbell;
4816
4817 /* Resetting interrupt aggregation counters first and reading the
4818 * DOOR_BELL afterward allows us to handle all the completed requests.
4819 * In order to prevent other interrupts starvation the DB is read once
4820 * after reset. The down side of this solution is the possibility of
4821 * false interrupt if device completes another request after resetting
4822 * aggregation and before reading the DB.
4823 */
49200199 4824 if (ufshcd_is_intr_aggr_allowed(hba))
9a47ec7c
YG		 4825 ufshcd_reset_intr_aggr(hba);
4826
4827 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4828 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4829
9333d775
VG		 4830 if (completed_reqs) {
4831 __ufshcd_transfer_req_compl(hba, completed_reqs);
4832 return IRQ_HANDLED;
4833 } else {
4834 return IRQ_NONE;
4835 }
9a47ec7c
YG		 4836}
4837
66ec6d59
SRT		 4838/**
4839 * ufshcd_disable_ee - disable exception event
4840 * @hba: per-adapter instance
4841 * @mask: exception event to disable
4842 *
4843 * Disables exception event in the device so that the EVENT_ALERT
4844 * bit is not set.
4845 *
4846 * Returns zero on success, non-zero error value on failure.
4847 */
4848static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4849{
4850 int err = 0;
4851 u32 val;
4852
4853 if (!(hba->ee_ctrl_mask & mask))
4854 goto out;
4855
4856 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4857 val &= MASK_EE_STATUS;
5e86ae44 4858 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4859 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4860 if (!err)
4861 hba->ee_ctrl_mask &= ~mask;
4862out:
4863 return err;
4864}
4865
4866/**
4867 * ufshcd_enable_ee - enable exception event
4868 * @hba: per-adapter instance
4869 * @mask: exception event to enable
4870 *
4871 * Enable corresponding exception event in the device to allow
4872 * device to alert host in critical scenarios.
4873 *
4874 * Returns zero on success, non-zero error value on failure.
4875 */
4876static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4877{
4878 int err = 0;
4879 u32 val;
4880
4881 if (hba->ee_ctrl_mask & mask)
4882 goto out;
4883
4884 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4885 val &= MASK_EE_STATUS;
5e86ae44 4886 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4887 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4888 if (!err)
4889 hba->ee_ctrl_mask |= mask;
4890out:
4891 return err;
4892}
4893
4894/**
4895 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4896 * @hba: per-adapter instance
4897 *
4898 * Allow device to manage background operations on its own. Enabling
4899 * this might lead to inconsistent latencies during normal data transfers
4900 * as the device is allowed to manage its own way of handling background
4901 * operations.
4902 *
4903 * Returns zero on success, non-zero on failure.
4904 */
4905static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4906{
4907 int err = 0;
4908
4909 if (hba->auto_bkops_enabled)
4910 goto out;
4911
dc3c8d3a 4912 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4913 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4914 if (err) {
4915 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4916 __func__, err);
4917 goto out;
4918 }
4919
4920 hba->auto_bkops_enabled = true;
7ff5ab47 4921 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4922
4923 /* No need of URGENT_BKOPS exception from the device */
4924 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4925 if (err)
4926 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4927 __func__, err);
4928out:
4929 return err;
4930}
4931
4932/**
4933 * ufshcd_disable_auto_bkops - block device in doing background operations
4934 * @hba: per-adapter instance
4935 *
4936 * Disabling background operations improves command response latency but
4937 * has drawback of device moving into critical state where the device is
4938 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4939 * host is idle so that BKOPS are managed effectively without any negative
4940 * impacts.
4941 *
4942 * Returns zero on success, non-zero on failure.
4943 */
4944static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4945{
4946 int err = 0;
4947
4948 if (!hba->auto_bkops_enabled)
4949 goto out;
4950
4951 /*
4952 * If host assisted BKOPs is to be enabled, make sure
4953 * urgent bkops exception is allowed.
4954 */
4955 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4956 if (err) {
4957 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4958 __func__, err);
4959 goto out;
4960 }
4961
dc3c8d3a 4962 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 4963 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4964 if (err) {
4965 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4966 __func__, err);
4967 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4968 goto out;
4969 }
4970
4971 hba->auto_bkops_enabled = false;
7ff5ab47 4972 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
24366c2a 4973 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 4974out:
4975 return err;
4976}
4977
4978/**
4e768e76 4979 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 4980 * @hba: per adapter instance
4981 *
4982 * After a device reset the device may toggle the BKOPS_EN flag
4983 * to default value. The s/w tracking variables should be updated
4e768e76
SJ		 4984 * as well. This function would change the auto-bkops state based on
4985 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 4986 */
4e768e76 4987static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 4988{
4e768e76
SJ		 4989 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4990 hba->auto_bkops_enabled = false;
4991 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4992 ufshcd_enable_auto_bkops(hba);
4993 } else {
4994 hba->auto_bkops_enabled = true;
4995 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4996 ufshcd_disable_auto_bkops(hba);
4997 }
24366c2a 4998 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 4999}
5000
5001static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5002{
5e86ae44 5003 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5004 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5005}
5006
5007/**
57d104c1 5008 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5009 * @hba: per-adapter instance
57d104c1 5010 * @status: bkops_status value
66ec6d59 5011 *
57d104c1
SJ		 5012 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5013 * flag in the device to permit background operations if the device
5014 * bkops_status is greater than or equal to "status" argument passed to
5015 * this function, disable otherwise.
5016 *
5017 * Returns 0 for success, non-zero in case of failure.
5018 *
5019 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5020 * to know whether auto bkops is enabled or disabled after this function
5021 * returns control to it.
66ec6d59 5022 */
57d104c1
SJ		 5023static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5024 enum bkops_status status)
66ec6d59
SRT		 5025{
5026 int err;
57d104c1 5027 u32 curr_status = 0;
66ec6d59 5028
57d104c1 5029 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5030 if (err) {
5031 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5032 __func__, err);
5033 goto out;
57d104c1
SJ		 5034 } else if (curr_status > BKOPS_STATUS_MAX) {
5035 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5036 __func__, curr_status);
5037 err = -EINVAL;
5038 goto out;
66ec6d59
SRT		 5039 }
5040
57d104c1 5041 if (curr_status >= status)
66ec6d59 5042 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5043 else
5044 err = ufshcd_disable_auto_bkops(hba);
24366c2a 5045 hba->urgent_bkops_lvl = curr_status;
66ec6d59
SRT		 5046out:
5047 return err;
5048}
5049
57d104c1
SJ		 5050/**
5051 * ufshcd_urgent_bkops - handle urgent bkops exception event
5052 * @hba: per-adapter instance
5053 *
5054 * Enable fBackgroundOpsEn flag in the device to permit background
5055 * operations.
5056 *
5057 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5058 * and negative error value for any other failure.
5059 */
5060static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5061{
afdfff59 5062 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5063}
5064
66ec6d59
SRT		 5065static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5066{
5e86ae44 5067 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5068 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5069}
5070
afdfff59
YG		 5071static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5072{
5073 int err;
5074 u32 curr_status = 0;
5075
5076 if (hba->is_urgent_bkops_lvl_checked)
5077 goto enable_auto_bkops;
5078
5079 err = ufshcd_get_bkops_status(hba, &curr_status);
5080 if (err) {
5081 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5082 __func__, err);
5083 goto out;
5084 }
5085
5086 /*
5087 * We are seeing that some devices are raising the urgent bkops
5088 * exception events even when BKOPS status doesn't indicate performace
5089 * impacted or critical. Handle these device by determining their urgent
5090 * bkops status at runtime.
5091 */
5092 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5093 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5094 __func__, curr_status);
5095 /* update the current status as the urgent bkops level */
5096 hba->urgent_bkops_lvl = curr_status;
5097 hba->is_urgent_bkops_lvl_checked = true;
5098 }
5099
5100enable_auto_bkops:
5101 err = ufshcd_enable_auto_bkops(hba);
5102out:
5103 if (err < 0)
5104 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5105 __func__, err);
5106}
5107
66ec6d59
SRT		 5108/**
5109 * ufshcd_exception_event_handler - handle exceptions raised by device
5110 * @work: pointer to work data
5111 *
5112 * Read bExceptionEventStatus attribute from the device and handle the
5113 * exception event accordingly.
5114 */
5115static void ufshcd_exception_event_handler(struct work_struct *work)
5116{
5117 struct ufs_hba *hba;
5118 int err;
5119 u32 status = 0;
5120 hba = container_of(work, struct ufs_hba, eeh_work);
5121
62694735 5122 pm_runtime_get_sync(hba->dev);
03e1d28e 5123 ufshcd_scsi_block_requests(hba);
66ec6d59
SRT		 5124 err = ufshcd_get_ee_status(hba, &status);
5125 if (err) {
5126 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5127 __func__, err);
5128 goto out;
5129 }
5130
5131 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5132
5133 if (status & MASK_EE_URGENT_BKOPS)
5134 ufshcd_bkops_exception_event_handler(hba);
5135
66ec6d59 5136out:
03e1d28e 5137 ufshcd_scsi_unblock_requests(hba);
2824ec9f
SL		 5138 /*
5139 * pm_runtime_get_noresume is called while scheduling
5140 * eeh_work to avoid suspend racing with exception work.
5141 * Hence decrement usage counter using pm_runtime_put_noidle
5142 * to allow suspend on completion of exception event handler.
5143 */
5144 pm_runtime_put_noidle(hba->dev);
5145 pm_runtime_put(hba->dev);
66ec6d59
SRT		 5146 return;
5147}
5148
9a47ec7c
YG		 5149/* Complete requests that have door-bell cleared */
5150static void ufshcd_complete_requests(struct ufs_hba *hba)
5151{
5152 ufshcd_transfer_req_compl(hba);
5153 ufshcd_tmc_handler(hba);
5154}
5155
583fa62d
YG		 5156/**
5157 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5158 * to recover from the DL NAC errors or not.
5159 * @hba: per-adapter instance
5160 *
5161 * Returns true if error handling is required, false otherwise
5162 */
5163static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5164{
5165 unsigned long flags;
5166 bool err_handling = true;
5167
5168 spin_lock_irqsave(hba->host->host_lock, flags);
5169 /*
5170 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5171 * device fatal error and/or DL NAC & REPLAY timeout errors.
5172 */
5173 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5174 goto out;
5175
5176 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5177 ((hba->saved_err & UIC_ERROR) &&
5178 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5179 goto out;
5180
5181 if ((hba->saved_err & UIC_ERROR) &&
5182 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5183 int err;
5184 /*
5185 * wait for 50ms to see if we can get any other errors or not.
5186 */
5187 spin_unlock_irqrestore(hba->host->host_lock, flags);
5188 msleep(50);
5189 spin_lock_irqsave(hba->host->host_lock, flags);
5190
5191 /*
5192 * now check if we have got any other severe errors other than
5193 * DL NAC error?
5194 */
5195 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5196 ((hba->saved_err & UIC_ERROR) &&
5197 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5198 goto out;
5199
5200 /*
5201 * As DL NAC is the only error received so far, send out NOP
5202 * command to confirm if link is still active or not.
5203 * - If we don't get any response then do error recovery.
5204 * - If we get response then clear the DL NAC error bit.
5205 */
5206
5207 spin_unlock_irqrestore(hba->host->host_lock, flags);
5208 err = ufshcd_verify_dev_init(hba);
5209 spin_lock_irqsave(hba->host->host_lock, flags);
5210
5211 if (err)
5212 goto out;
5213
5214 /* Link seems to be alive hence ignore the DL NAC errors */
5215 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5216 hba->saved_err &= ~UIC_ERROR;
5217 /* clear NAC error */
5218 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5219 if (!hba->saved_uic_err) {
5220 err_handling = false;
5221 goto out;
5222 }
5223 }
5224out:
5225 spin_unlock_irqrestore(hba->host->host_lock, flags);
5226 return err_handling;
5227}
5228
7a3e97b0 5229/**
e8e7f271
SRT		 5230 * ufshcd_err_handler - handle UFS errors that require s/w attention
5231 * @work: pointer to work structure
7a3e97b0 5232 */
e8e7f271 5233static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5234{
5235 struct ufs_hba *hba;
e8e7f271
SRT		 5236 unsigned long flags;
5237 u32 err_xfer = 0;
5238 u32 err_tm = 0;
5239 int err = 0;
5240 int tag;
9a47ec7c 5241 bool needs_reset = false;
e8e7f271
SRT		 5242
5243 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5244
62694735 5245 pm_runtime_get_sync(hba->dev);
1ab27c9c 5246 ufshcd_hold(hba, false);
e8e7f271
SRT		 5247
5248 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5249 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5250 goto out;
e8e7f271
SRT		 5251
5252 hba->ufshcd_state = UFSHCD_STATE_RESET;
5253 ufshcd_set_eh_in_progress(hba);
5254
5255 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5256 ufshcd_complete_requests(hba);
583fa62d
YG		 5257
5258 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5259 bool ret;
5260
5261 spin_unlock_irqrestore(hba->host->host_lock, flags);
5262 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5263 ret = ufshcd_quirk_dl_nac_errors(hba);
5264 spin_lock_irqsave(hba->host->host_lock, flags);
5265 if (!ret)
5266 goto skip_err_handling;
5267 }
9a47ec7c 5268 if ((hba->saved_err & INT_FATAL_ERRORS) ||
82174440 5269 (hba->saved_err & UFSHCD_UIC_HIBERN8_MASK) ||
9a47ec7c
YG		 5270 ((hba->saved_err & UIC_ERROR) &&
5271 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5272 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5273 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5274 needs_reset = true;
e8e7f271 5275
9a47ec7c
YG		 5276 /*
5277 * if host reset is required then skip clearing the pending
2df74b69
CG		 5278 * transfers forcefully because they will get cleared during
5279 * host reset and restore
9a47ec7c
YG		 5280 */
5281 if (needs_reset)
5282 goto skip_pending_xfer_clear;
5283
5284 /* release lock as clear command might sleep */
5285 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5286 /* Clear pending transfer requests */
9a47ec7c
YG		 5287 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5288 if (ufshcd_clear_cmd(hba, tag)) {
5289 err_xfer = true;
5290 goto lock_skip_pending_xfer_clear;
5291 }
5292 }
e8e7f271
SRT		 5293
5294 /* Clear pending task management requests */
9a47ec7c
YG		 5295 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5296 if (ufshcd_clear_tm_cmd(hba, tag)) {
5297 err_tm = true;
5298 goto lock_skip_pending_xfer_clear;
5299 }
5300 }
e8e7f271 5301
9a47ec7c 5302lock_skip_pending_xfer_clear:
e8e7f271 5303 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5304
9a47ec7c
YG		 5305 /* Complete the requests that are cleared by s/w */
5306 ufshcd_complete_requests(hba);
5307
5308 if (err_xfer || err_tm)
5309 needs_reset = true;
5310
5311skip_pending_xfer_clear:
e8e7f271 5312 /* Fatal errors need reset */
9a47ec7c
YG		 5313 if (needs_reset) {
5314 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5315
5316 /*
5317 * ufshcd_reset_and_restore() does the link reinitialization
5318 * which will need atleast one empty doorbell slot to send the
5319 * device management commands (NOP and query commands).
5320 * If there is no slot empty at this moment then free up last
5321 * slot forcefully.
5322 */
5323 if (hba->outstanding_reqs == max_doorbells)
5324 __ufshcd_transfer_req_compl(hba,
5325 (1UL << (hba->nutrs - 1)));
5326
5327 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5328 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5329 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5330 if (err) {
5331 dev_err(hba->dev, "%s: reset and restore failed\n",
5332 __func__);
5333 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5334 }
5335 /*
5336 * Inform scsi mid-layer that we did reset and allow to handle
5337 * Unit Attention properly.
5338 */
5339 scsi_report_bus_reset(hba->host, 0);
5340 hba->saved_err = 0;
5341 hba->saved_uic_err = 0;
5342 }
9a47ec7c 5343
583fa62d 5344skip_err_handling:
9a47ec7c
YG		 5345 if (!needs_reset) {
5346 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5347 if (hba->saved_err || hba->saved_uic_err)
5348 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5349 __func__, hba->saved_err, hba->saved_uic_err);
5350 }
5351
e8e7f271
SRT		 5352 ufshcd_clear_eh_in_progress(hba);
5353
5354out:
9a47ec7c 5355 spin_unlock_irqrestore(hba->host->host_lock, flags);
38135535 5356 ufshcd_scsi_unblock_requests(hba);
1ab27c9c 5357 ufshcd_release(hba);
62694735 5358 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5359}
5360
5361/**
e8e7f271
SRT		 5362 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5363 * @hba: per-adapter instance
9333d775
VG		 5364 *
5365 * Returns
5366 * IRQ_HANDLED - If interrupt is valid
5367 * IRQ_NONE - If invalid interrupt
7a3e97b0 5368 */
9333d775 5369static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5370{
5371 u32 reg;
9333d775 5372 irqreturn_t retval = IRQ_NONE;
7a3e97b0 5373
fb7b45f0
DR		 5374 /* PHY layer lane error */
5375 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5376 /* Ignore LINERESET indication, as this is not an error */
5377 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
9333d775 5378 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5379 /*
5380 * To know whether this error is fatal or not, DB timeout
5381 * must be checked but this error is handled separately.
5382 */
5383 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
48d5b973 5384 ufshcd_update_reg_hist(&hba->ufs_stats.pa_err, reg);
9333d775 5385 retval |= IRQ_HANDLED;
ff8e20c6 5386 }
fb7b45f0 5387
e8e7f271
SRT		 5388 /* PA_INIT_ERROR is fatal and needs UIC reset */
5389 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
9333d775
VG		 5390 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
5391 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
48d5b973 5392 ufshcd_update_reg_hist(&hba->ufs_stats.dl_err, reg);
ff8e20c6 5393
9333d775
VG		 5394 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5395 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
5396 else if (hba->dev_quirks &
5397 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5398 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5399 hba->uic_error |=
5400 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5401 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5402 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5403 }
5404 retval |= IRQ_HANDLED;
583fa62d 5405 }
e8e7f271
SRT		 5406
5407 /* UIC NL/TL/DME errors needs software retry */
5408 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
9333d775
VG		 5409 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
5410 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
48d5b973 5411 ufshcd_update_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5412 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
9333d775 5413 retval |= IRQ_HANDLED;
ff8e20c6 5414 }
e8e7f271
SRT		 5415
5416 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
9333d775
VG		 5417 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
5418 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
48d5b973 5419 ufshcd_update_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5420 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
9333d775 5421 retval |= IRQ_HANDLED;
ff8e20c6 5422 }
e8e7f271
SRT		 5423
5424 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
9333d775
VG		 5425 if ((reg & UIC_DME_ERROR) &&
5426 (reg & UIC_DME_ERROR_CODE_MASK)) {
48d5b973 5427 ufshcd_update_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5428 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
9333d775 5429 retval |= IRQ_HANDLED;
ff8e20c6 5430 }
e8e7f271
SRT		 5431
5432 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5433 __func__, hba->uic_error);
9333d775 5434 return retval;
e8e7f271
SRT		 5435}
5436
82174440
SC		 5437static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5438 u32 intr_mask)
5439{
5a244e0e
SC		 5440 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5441 !ufshcd_is_auto_hibern8_enabled(hba))
82174440
SC		 5442 return false;
5443
5444 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5445 return false;
5446
5447 if (hba->active_uic_cmd &&
5448 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5449 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5450 return false;
5451
5452 return true;
5453}
5454
e8e7f271
SRT		 5455/**
5456 * ufshcd_check_errors - Check for errors that need s/w attention
5457 * @hba: per-adapter instance
9333d775
VG		 5458 *
5459 * Returns
5460 * IRQ_HANDLED - If interrupt is valid
5461 * IRQ_NONE - If invalid interrupt
e8e7f271 5462 */
9333d775 5463static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba)
e8e7f271
SRT		 5464{
5465 bool queue_eh_work = false;
9333d775 5466 irqreturn_t retval = IRQ_NONE;
e8e7f271 5467
d3c615bf
SC		 5468 if (hba->errors & INT_FATAL_ERRORS) {
5469 ufshcd_update_reg_hist(&hba->ufs_stats.fatal_err, hba->errors);
e8e7f271 5470 queue_eh_work = true;
d3c615bf 5471 }
7a3e97b0
SY		 5472
5473 if (hba->errors & UIC_ERROR) {
e8e7f271 5474 hba->uic_error = 0;
9333d775 5475 retval = ufshcd_update_uic_error(hba);
e8e7f271
SRT		 5476 if (hba->uic_error)
5477 queue_eh_work = true;
7a3e97b0 5478 }
e8e7f271 5479
82174440
SC		 5480 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
5481 dev_err(hba->dev,
5482 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
5483 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
5484 "Enter" : "Exit",
5485 hba->errors, ufshcd_get_upmcrs(hba));
d3c615bf
SC		 5486 ufshcd_update_reg_hist(&hba->ufs_stats.auto_hibern8_err,
5487 hba->errors);
82174440
SC		 5488 queue_eh_work = true;
5489 }
5490
e8e7f271 5491 if (queue_eh_work) {
9a47ec7c
YG		 5492 /*
5493 * update the transfer error masks to sticky bits, let's do this
5494 * irrespective of current ufshcd_state.
5495 */
5496 hba->saved_err |= hba->errors;
5497 hba->saved_uic_err |= hba->uic_error;
5498
e8e7f271
SRT		 5499 /* handle fatal errors only when link is functional */
5500 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5501 /* block commands from scsi mid-layer */
38135535 5502 ufshcd_scsi_block_requests(hba);
e8e7f271 5503
141f8165 5504 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5505
5506 /* dump controller state before resetting */
5507 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5508 bool pr_prdt = !!(hba->saved_err &
5509 SYSTEM_BUS_FATAL_ERROR);
5510
5511 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5512 __func__, hba->saved_err,
5513 hba->saved_uic_err);
5514
5515 ufshcd_print_host_regs(hba);
5516 ufshcd_print_pwr_info(hba);
5517 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5518 ufshcd_print_trs(hba, hba->outstanding_reqs,
5519 pr_prdt);
5520 }
e8e7f271
SRT		 5521 schedule_work(&hba->eh_work);
5522 }
9333d775 5523 retval |= IRQ_HANDLED;
3441da7d 5524 }
e8e7f271
SRT		 5525 /*
5526 * if (!queue_eh_work) -
5527 * Other errors are either non-fatal where host recovers
5528 * itself without s/w intervention or errors that will be
5529 * handled by the SCSI core layer.
5530 */
9333d775 5531 return retval;
7a3e97b0
SY		 5532}
5533
69a6c269
BVA		 5534struct ctm_info {
5535 struct ufs_hba *hba;
5536 unsigned long pending;
5537 unsigned int ncpl;
5538};
5539
5540static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
5541{
5542 struct ctm_info *const ci = priv;
5543 struct completion *c;
5544
5545 WARN_ON_ONCE(reserved);
5546 if (test_bit(req->tag, &ci->pending))
5547 return true;
5548 ci->ncpl++;
5549 c = req->end_io_data;
5550 if (c)
5551 complete(c);
5552 return true;
5553}
5554
7a3e97b0
SY		 5555/**
5556 * ufshcd_tmc_handler - handle task management function completion
5557 * @hba: per adapter instance
9333d775
VG		 5558 *
5559 * Returns
5560 * IRQ_HANDLED - If interrupt is valid
5561 * IRQ_NONE - If invalid interrupt
7a3e97b0 5562 */
9333d775 5563static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7a3e97b0 5564{
69a6c269
BVA		 5565 struct request_queue *q = hba->tmf_queue;
5566 struct ctm_info ci = {
5567 .hba = hba,
5568 .pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL),
5569 };
7a3e97b0 5570
69a6c269
BVA		 5571 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
5572 return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
7a3e97b0
SY		 5573}
5574
5575/**
5576 * ufshcd_sl_intr - Interrupt service routine
5577 * @hba: per adapter instance
5578 * @intr_status: contains interrupts generated by the controller
9333d775
VG		 5579 *
5580 * Returns
5581 * IRQ_HANDLED - If interrupt is valid
5582 * IRQ_NONE - If invalid interrupt
7a3e97b0 5583 */
9333d775 5584static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7a3e97b0 5585{
9333d775
VG		 5586 irqreturn_t retval = IRQ_NONE;
5587
7a3e97b0 5588 hba->errors = UFSHCD_ERROR_MASK & intr_status;
82174440
SC		 5589
5590 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5591 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5592
7a3e97b0 5593 if (hba->errors)
9333d775 5594 retval |= ufshcd_check_errors(hba);
7a3e97b0 5595
53b3d9c3 5596 if (intr_status & UFSHCD_UIC_MASK)
9333d775 5597 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5598
5599 if (intr_status & UTP_TASK_REQ_COMPL)
9333d775 5600 retval |= ufshcd_tmc_handler(hba);
7a3e97b0
SY		 5601
5602 if (intr_status & UTP_TRANSFER_REQ_COMPL)
9333d775
VG		 5603 retval |= ufshcd_transfer_req_compl(hba);
5604
5605 return retval;
7a3e97b0
SY		 5606}
5607
5608/**
5609 * ufshcd_intr - Main interrupt service routine
5610 * @irq: irq number
5611 * @__hba: pointer to adapter instance
5612 *
9333d775
VG		 5613 * Returns
5614 * IRQ_HANDLED - If interrupt is valid
5615 * IRQ_NONE - If invalid interrupt
7a3e97b0
SY		 5616 */
5617static irqreturn_t ufshcd_intr(int irq, void *__hba)
5618{
d75f7fe4 5619 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5620 irqreturn_t retval = IRQ_NONE;
5621 struct ufs_hba *hba = __hba;
7f6ba4f1 5622 int retries = hba->nutrs;
7a3e97b0
SY		 5623
5624 spin_lock(hba->host->host_lock);
b873a275 5625 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0 5626
7f6ba4f1
VG		 5627 /*
5628 * There could be max of hba->nutrs reqs in flight and in worst case
5629 * if the reqs get finished 1 by 1 after the interrupt status is
5630 * read, make sure we handle them by checking the interrupt status
5631 * again in a loop until we process all of the reqs before returning.
5632 */
5633 do {
5634 enabled_intr_status =
5635 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5636 if (intr_status)
5637 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
9333d775
VG		 5638 if (enabled_intr_status)
5639 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7f6ba4f1
VG		 5640
5641 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5642 } while (intr_status && --retries);
d75f7fe4 5643
9333d775
VG		 5644 if (retval == IRQ_NONE) {
5645 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n",
5646 __func__, intr_status);
5647 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
5648 }
5649
7a3e97b0
SY		 5650 spin_unlock(hba->host->host_lock);
5651 return retval;
5652}
5653
e2933132
SRT		 5654static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5655{
5656 int err = 0;
5657 u32 mask = 1 << tag;
5658 unsigned long flags;
5659
5660 if (!test_bit(tag, &hba->outstanding_tasks))
5661 goto out;
5662
5663 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 5664 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5665 spin_unlock_irqrestore(hba->host->host_lock, flags);
5666
5667 /* poll for max. 1 sec to clear door bell register by h/w */
5668 err = ufshcd_wait_for_register(hba,
5669 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5670 mask, 0, 1000, 1000, true);
e2933132
SRT		 5671out:
5672 return err;
5673}
5674
c6049cd9
CH		 5675static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
5676 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 5677{
69a6c269 5678 struct request_queue *q = hba->tmf_queue;
c6049cd9 5679 struct Scsi_Host *host = hba->host;
69a6c269
BVA		 5680 DECLARE_COMPLETION_ONSTACK(wait);
5681 struct request *req;
7a3e97b0 5682 unsigned long flags;
c6049cd9 5683 int free_slot, task_tag, err;
7a3e97b0 5684
e2933132
SRT		 5685 /*
5686 * Get free slot, sleep if slots are unavailable.
5687 * Even though we use wait_event() which sleeps indefinitely,
5688 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5689 */
69a6c269
BVA		 5690 req = blk_get_request(q, REQ_OP_DRV_OUT, BLK_MQ_REQ_RESERVED);
5691 req->end_io_data = &wait;
5692 free_slot = req->tag;
5693 WARN_ON_ONCE(free_slot < 0 || free_slot >= hba->nutmrs);
1ab27c9c 5694 ufshcd_hold(hba, false);
7a3e97b0 5695
e2933132 5696 spin_lock_irqsave(host->host_lock, flags);
e2933132 5697 task_tag = hba->nutrs + free_slot;
7a3e97b0 5698
c6049cd9
CH		 5699 treq->req_header.dword_0 |= cpu_to_be32(task_tag);
5700
5701 memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
d2877be4
KK		 5702 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5703
7a3e97b0
SY		 5704 /* send command to the controller */
5705 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5706
5707 /* Make sure descriptors are ready before ringing the task doorbell */
5708 wmb();
5709
b873a275 5710 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5711 /* Make sure that doorbell is committed immediately */
5712 wmb();
7a3e97b0
SY		 5713
5714 spin_unlock_irqrestore(host->host_lock, flags);
5715
6667e6d9
OS		 5716 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5717
7a3e97b0 5718 /* wait until the task management command is completed */
69a6c269 5719 err = wait_for_completion_io_timeout(&wait,
e2933132 5720 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5721 if (!err) {
69a6c269
BVA		 5722 /*
5723 * Make sure that ufshcd_compl_tm() does not trigger a
5724 * use-after-free.
5725 */
5726 req->end_io_data = NULL;
6667e6d9 5727 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
e2933132
SRT		 5728 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5729 __func__, tm_function);
5730 if (ufshcd_clear_tm_cmd(hba, free_slot))
5731 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5732 __func__, free_slot);
5733 err = -ETIMEDOUT;
5734 } else {
c6049cd9
CH		 5735 err = 0;
5736 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
5737
6667e6d9 5738 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
7a3e97b0 5739 }
e2933132 5740
b557217c
SC		 5741 spin_lock_irqsave(hba->host->host_lock, flags);
5742 __clear_bit(free_slot, &hba->outstanding_tasks);
5743 spin_unlock_irqrestore(hba->host->host_lock, flags);
5744
69a6c269 5745 blk_put_request(req);
e2933132 5746
1ab27c9c 5747 ufshcd_release(hba);
7a3e97b0
SY		 5748 return err;
5749}
5750
c6049cd9
CH		 5751/**
5752 * ufshcd_issue_tm_cmd - issues task management commands to controller
5753 * @hba: per adapter instance
5754 * @lun_id: LUN ID to which TM command is sent
5755 * @task_id: task ID to which the TM command is applicable
5756 * @tm_function: task management function opcode
5757 * @tm_response: task management service response return value
5758 *
5759 * Returns non-zero value on error, zero on success.
5760 */
5761static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5762 u8 tm_function, u8 *tm_response)
5763{
5764 struct utp_task_req_desc treq = { { 0 }, };
5765 int ocs_value, err;
5766
5767 /* Configure task request descriptor */
5768 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5769 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5770
5771 /* Configure task request UPIU */
5772 treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
5773 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
5774 treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
5775
5776 /*
5777 * The host shall provide the same value for LUN field in the basic
5778 * header and for Input Parameter.
5779 */
5780 treq.input_param1 = cpu_to_be32(lun_id);
5781 treq.input_param2 = cpu_to_be32(task_id);
5782
5783 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
5784 if (err == -ETIMEDOUT)
5785 return err;
5786
5787 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5788 if (ocs_value != OCS_SUCCESS)
5789 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
5790 __func__, ocs_value);
5791 else if (tm_response)
5792 *tm_response = be32_to_cpu(treq.output_param1) &
5793 MASK_TM_SERVICE_RESP;
5794 return err;
5795}
5796
5e0a86ee
AA		 5797/**
5798 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
5799 * @hba: per-adapter instance
5800 * @req_upiu: upiu request
5801 * @rsp_upiu: upiu reply
5e0a86ee
AA		 5802 * @desc_buff: pointer to descriptor buffer, NULL if NA
5803 * @buff_len: descriptor size, 0 if NA
d0e9760d 5804 * @cmd_type: specifies the type (NOP, Query...)
5e0a86ee
AA		 5805 * @desc_op: descriptor operation
5806 *
5807 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
5808 * Therefore, it "rides" the device management infrastructure: uses its tag and
5809 * tasks work queues.
5810 *
5811 * Since there is only one available tag for device management commands,
5812 * the caller is expected to hold the hba->dev_cmd.lock mutex.
5813 */
5814static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
5815 struct utp_upiu_req *req_upiu,
5816 struct utp_upiu_req *rsp_upiu,
5817 u8 *desc_buff, int *buff_len,
7f674c38 5818 enum dev_cmd_type cmd_type,
5e0a86ee
AA		 5819 enum query_opcode desc_op)
5820{
7252a360
BVA		 5821 struct request_queue *q = hba->cmd_queue;
5822 struct request *req;
5e0a86ee
AA		 5823 struct ufshcd_lrb *lrbp;
5824 int err = 0;
5825 int tag;
5826 struct completion wait;
5827 unsigned long flags;
5828 u32 upiu_flags;
5829
5830 down_read(&hba->clk_scaling_lock);
5831
7252a360 5832 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
bb14dd15
DC		 5833 if (IS_ERR(req)) {
5834 err = PTR_ERR(req);
5835 goto out_unlock;
5836 }
7252a360
BVA		 5837 tag = req->tag;
5838 WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
5e0a86ee
AA		 5839
5840 init_completion(&wait);
5841 lrbp = &hba->lrb[tag];
5842 WARN_ON(lrbp->cmd);
5843
5844 lrbp->cmd = NULL;
5845 lrbp->sense_bufflen = 0;
5846 lrbp->sense_buffer = NULL;
5847 lrbp->task_tag = tag;
5848 lrbp->lun = 0;
5849 lrbp->intr_cmd = true;
5850 hba->dev_cmd.type = cmd_type;
5851
5852 switch (hba->ufs_version) {
5853 case UFSHCI_VERSION_10:
5854 case UFSHCI_VERSION_11:
5855 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
5856 break;
5857 default:
5858 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5859 break;
5860 }
5861
5862 /* update the task tag in the request upiu */
5863 req_upiu->header.dword_0 |= cpu_to_be32(tag);
5864
5865 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
5866
5867 /* just copy the upiu request as it is */
5868 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
5869 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
5870 /* The Data Segment Area is optional depending upon the query
5871 * function value. for WRITE DESCRIPTOR, the data segment
5872 * follows right after the tsf.
5873 */
5874 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
5875 *buff_len = 0;
5876 }
5877
5878 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5879
5880 hba->dev_cmd.complete = &wait;
5881
5882 /* Make sure descriptors are ready before ringing the doorbell */
5883 wmb();
5884 spin_lock_irqsave(hba->host->host_lock, flags);
5885 ufshcd_send_command(hba, tag);
5886 spin_unlock_irqrestore(hba->host->host_lock, flags);
5887
5888 /*
5889 * ignore the returning value here - ufshcd_check_query_response is
5890 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
5891 * read the response directly ignoring all errors.
5892 */
5893 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
5894
5895 /* just copy the upiu response as it is */
5896 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
4bbbe242
AA		 5897 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
5898 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
5899 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
5900 MASK_QUERY_DATA_SEG_LEN;
5901
5902 if (*buff_len >= resp_len) {
5903 memcpy(desc_buff, descp, resp_len);
5904 *buff_len = resp_len;
5905 } else {
3d4881d1
BH		 5906 dev_warn(hba->dev,
5907 "%s: rsp size %d is bigger than buffer size %d",
5908 __func__, resp_len, *buff_len);
4bbbe242
AA		 5909 *buff_len = 0;
5910 err = -EINVAL;
5911 }
5912 }
5e0a86ee 5913
7252a360 5914 blk_put_request(req);
bb14dd15 5915out_unlock:
5e0a86ee
AA		 5916 up_read(&hba->clk_scaling_lock);
5917 return err;
5918}
5919
5920/**
5921 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
5922 * @hba: per-adapter instance
5923 * @req_upiu: upiu request
5924 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
5925 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
5926 * @desc_buff: pointer to descriptor buffer, NULL if NA
5927 * @buff_len: descriptor size, 0 if NA
5928 * @desc_op: descriptor operation
5929 *
5930 * Supports UTP Transfer requests (nop and query), and UTP Task
5931 * Management requests.
5932 * It is up to the caller to fill the upiu conent properly, as it will
5933 * be copied without any further input validations.
5934 */
5935int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
5936 struct utp_upiu_req *req_upiu,
5937 struct utp_upiu_req *rsp_upiu,
5938 int msgcode,
5939 u8 *desc_buff, int *buff_len,
5940 enum query_opcode desc_op)
5941{
5942 int err;
7f674c38 5943 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
5e0a86ee
AA		 5944 struct utp_task_req_desc treq = { { 0 }, };
5945 int ocs_value;
5946 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
5947
5e0a86ee
AA		 5948 switch (msgcode) {
5949 case UPIU_TRANSACTION_NOP_OUT:
5950 cmd_type = DEV_CMD_TYPE_NOP;
5951 /* fall through */
5952 case UPIU_TRANSACTION_QUERY_REQ:
5953 ufshcd_hold(hba, false);
5954 mutex_lock(&hba->dev_cmd.lock);
5955 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
5956 desc_buff, buff_len,
5957 cmd_type, desc_op);
5958 mutex_unlock(&hba->dev_cmd.lock);
5959 ufshcd_release(hba);
5960
5961 break;
5962 case UPIU_TRANSACTION_TASK_REQ:
5963 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5964 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5965
5966 memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
5967
5968 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
5969 if (err == -ETIMEDOUT)
5970 break;
5971
5972 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5973 if (ocs_value != OCS_SUCCESS) {
5974 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
5975 ocs_value);
5976 break;
5977 }
5978
5979 memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
5980
5981 break;
5982 default:
5983 err = -EINVAL;
5984
5985 break;
5986 }
5987
5e0a86ee
AA		 5988 return err;
5989}
5990
7a3e97b0 5991/**
3441da7d
SRT		 5992 * ufshcd_eh_device_reset_handler - device reset handler registered to
5993 * scsi layer.
7a3e97b0
SY		 5994 * @cmd: SCSI command pointer
5995 *
5996 * Returns SUCCESS/FAILED
5997 */
3441da7d 5998static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5999{
6000 struct Scsi_Host *host;
6001 struct ufs_hba *hba;
6002 unsigned int tag;
6003 u32 pos;
6004 int err;
e2933132
SRT		 6005 u8 resp = 0xF;
6006 struct ufshcd_lrb *lrbp;
3441da7d 6007 unsigned long flags;
7a3e97b0
SY		 6008
6009 host = cmd->device->host;
6010 hba = shost_priv(host);
6011 tag = cmd->request->tag;
6012
e2933132
SRT		 6013 lrbp = &hba->lrb[tag];
6014 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
6015 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 6016 if (!err)
6017 err = resp;
7a3e97b0 6018 goto out;
e2933132 6019 }
7a3e97b0 6020
3441da7d
SRT		 6021 /* clear the commands that were pending for corresponding LUN */
6022 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6023 if (hba->lrb[pos].lun == lrbp->lun) {
6024 err = ufshcd_clear_cmd(hba, pos);
6025 if (err)
6026 break;
7a3e97b0 6027 }
3441da7d
SRT		 6028 }
6029 spin_lock_irqsave(host->host_lock, flags);
6030 ufshcd_transfer_req_compl(hba);
6031 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 6032
7a3e97b0 6033out:
7fabb77b 6034 hba->req_abort_count = 0;
8808b4e9 6035 ufshcd_update_reg_hist(&hba->ufs_stats.dev_reset, (u32)err);
3441da7d
SRT		 6036 if (!err) {
6037 err = SUCCESS;
6038 } else {
6039 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6040 err = FAILED;
6041 }
7a3e97b0
SY		 6042 return err;
6043}
6044
e0b299e3
GB		 6045static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6046{
6047 struct ufshcd_lrb *lrbp;
6048 int tag;
6049
6050 for_each_set_bit(tag, &bitmap, hba->nutrs) {
6051 lrbp = &hba->lrb[tag];
6052 lrbp->req_abort_skip = true;
6053 }
6054}
6055
7a3e97b0
SY		 6056/**
6057 * ufshcd_abort - abort a specific command
6058 * @cmd: SCSI command pointer
6059 *
f20810d8
SRT		 6060 * Abort the pending command in device by sending UFS_ABORT_TASK task management
6061 * command, and in host controller by clearing the door-bell register. There can
6062 * be race between controller sending the command to the device while abort is
6063 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6064 * really issued and then try to abort it.
6065 *
7a3e97b0
SY		 6066 * Returns SUCCESS/FAILED
6067 */
6068static int ufshcd_abort(struct scsi_cmnd *cmd)
6069{
6070 struct Scsi_Host *host;
6071 struct ufs_hba *hba;
6072 unsigned long flags;
6073 unsigned int tag;
f20810d8
SRT		 6074 int err = 0;
6075 int poll_cnt;
e2933132
SRT		 6076 u8 resp = 0xF;
6077 struct ufshcd_lrb *lrbp;
e9d501b1 6078 u32 reg;
7a3e97b0
SY		 6079
6080 host = cmd->device->host;
6081 hba = shost_priv(host);
6082 tag = cmd->request->tag;
e7d38257 6083 lrbp = &hba->lrb[tag];
14497328
YG		 6084 if (!ufshcd_valid_tag(hba, tag)) {
6085 dev_err(hba->dev,
6086 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
6087 __func__, tag, cmd, cmd->request);
6088 BUG();
6089 }
7a3e97b0 6090
e7d38257
DR		 6091 /*
6092 * Task abort to the device W-LUN is illegal. When this command
6093 * will fail, due to spec violation, scsi err handling next step
6094 * will be to send LU reset which, again, is a spec violation.
6095 * To avoid these unnecessary/illegal step we skip to the last error
6096 * handling stage: reset and restore.
6097 */
6098 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
6099 return ufshcd_eh_host_reset_handler(cmd);
6100
1ab27c9c 6101 ufshcd_hold(hba, false);
14497328 6102 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 6103 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 6104 if (!(test_bit(tag, &hba->outstanding_reqs))) {
6105 dev_err(hba->dev,
6106 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6107 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 6108 goto out;
14497328 6109 }
7a3e97b0 6110
e9d501b1
DR		 6111 if (!(reg & (1 << tag))) {
6112 dev_err(hba->dev,
6113 "%s: cmd was completed, but without a notifying intr, tag = %d",
6114 __func__, tag);
6115 }
6116
66cc820f
DR		 6117 /* Print Transfer Request of aborted task */
6118 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 6119
7fabb77b
GB		 6120 /*
6121 * Print detailed info about aborted request.
6122 * As more than one request might get aborted at the same time,
6123 * print full information only for the first aborted request in order
6124 * to reduce repeated printouts. For other aborted requests only print
6125 * basic details.
6126 */
6127 scsi_print_command(hba->lrb[tag].cmd);
6128 if (!hba->req_abort_count) {
8808b4e9 6129 ufshcd_update_reg_hist(&hba->ufs_stats.task_abort, 0);
7fabb77b 6130 ufshcd_print_host_regs(hba);
6ba65588 6131 ufshcd_print_host_state(hba);
7fabb77b
GB		 6132 ufshcd_print_pwr_info(hba);
6133 ufshcd_print_trs(hba, 1 << tag, true);
6134 } else {
6135 ufshcd_print_trs(hba, 1 << tag, false);
6136 }
6137 hba->req_abort_count++;
e0b299e3
GB		 6138
6139 /* Skip task abort in case previous aborts failed and report failure */
6140 if (lrbp->req_abort_skip) {
6141 err = -EIO;
6142 goto out;
6143 }
6144
f20810d8
SRT		 6145 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6146 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6147 UFS_QUERY_TASK, &resp);
6148 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6149 /* cmd pending in the device */
ff8e20c6
DR		 6150 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6151 __func__, tag);
f20810d8
SRT		 6152 break;
6153 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 6154 /*
6155 * cmd not pending in the device, check if it is
6156 * in transition.
6157 */
ff8e20c6
DR		 6158 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6159 __func__, tag);
f20810d8
SRT		 6160 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6161 if (reg & (1 << tag)) {
6162 /* sleep for max. 200us to stabilize */
6163 usleep_range(100, 200);
6164 continue;
6165 }
6166 /* command completed already */
ff8e20c6
DR		 6167 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6168 __func__, tag);
f20810d8
SRT		 6169 goto out;
6170 } else {
ff8e20c6
DR		 6171 dev_err(hba->dev,
6172 "%s: no response from device. tag = %d, err %d\n",
6173 __func__, tag, err);
f20810d8
SRT		 6174 if (!err)
6175 err = resp; /* service response error */
6176 goto out;
6177 }
6178 }
6179
6180 if (!poll_cnt) {
6181 err = -EBUSY;
7a3e97b0
SY		 6182 goto out;
6183 }
7a3e97b0 6184
e2933132
SRT		 6185 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6186 UFS_ABORT_TASK, &resp);
6187 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 6188 if (!err) {
f20810d8 6189 err = resp; /* service response error */
ff8e20c6
DR		 6190 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6191 __func__, tag, err);
6192 }
7a3e97b0 6193 goto out;
e2933132 6194 }
7a3e97b0 6195
f20810d8 6196 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 6197 if (err) {
6198 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6199 __func__, tag, err);
f20810d8 6200 goto out;
ff8e20c6 6201 }
f20810d8 6202
7a3e97b0
SY		 6203 scsi_dma_unmap(cmd);
6204
6205 spin_lock_irqsave(host->host_lock, flags);
a48353f6 6206 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 6207 hba->lrb[tag].cmd = NULL;
6208 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9 6209
7a3e97b0 6210out:
f20810d8
SRT		 6211 if (!err) {
6212 err = SUCCESS;
6213 } else {
6214 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 6215 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 6216 err = FAILED;
6217 }
6218
1ab27c9c
ST		 6219 /*
6220 * This ufshcd_release() corresponds to the original scsi cmd that got
6221 * aborted here (as we won't get any IRQ for it).
6222 */
6223 ufshcd_release(hba);
7a3e97b0
SY		 6224 return err;
6225}
6226
3441da7d
SRT		 6227/**
6228 * ufshcd_host_reset_and_restore - reset and restore host controller
6229 * @hba: per-adapter instance
6230 *
6231 * Note that host controller reset may issue DME_RESET to
6232 * local and remote (device) Uni-Pro stack and the attributes
6233 * are reset to default state.
6234 *
6235 * Returns zero on success, non-zero on failure
6236 */
6237static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6238{
6239 int err;
3441da7d
SRT		 6240 unsigned long flags;
6241
2df74b69
CG		 6242 /*
6243 * Stop the host controller and complete the requests
6244 * cleared by h/w
6245 */
3441da7d 6246 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 6247 ufshcd_hba_stop(hba, false);
2df74b69
CG		 6248 hba->silence_err_logs = true;
6249 ufshcd_complete_requests(hba);
6250 hba->silence_err_logs = false;
3441da7d
SRT		 6251 spin_unlock_irqrestore(hba->host->host_lock, flags);
6252
a3cd5ec5
SJ		 6253 /* scale up clocks to max frequency before full reinitialization */
6254 ufshcd_scale_clks(hba, true);
6255
3441da7d
SRT		 6256 err = ufshcd_hba_enable(hba);
6257 if (err)
6258 goto out;
6259
6260 /* Establish the link again and restore the device */
1b9e2141 6261 err = ufshcd_probe_hba(hba, false);
1d337ec2
SRT		 6262
6263 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 6264 err = -EIO;
6265out:
6266 if (err)
6267 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
8808b4e9 6268 ufshcd_update_reg_hist(&hba->ufs_stats.host_reset, (u32)err);
3441da7d
SRT		 6269 return err;
6270}
6271
6272/**
6273 * ufshcd_reset_and_restore - reset and re-initialize host/device
6274 * @hba: per-adapter instance
6275 *
6276 * Reset and recover device, host and re-establish link. This
6277 * is helpful to recover the communication in fatal error conditions.
6278 *
6279 * Returns zero on success, non-zero on failure
6280 */
6281static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6282{
6283 int err = 0;
1d337ec2 6284 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 6285
1d337ec2 6286 do {
d8d9f793
BA		 6287 /* Reset the attached device */
6288 ufshcd_vops_device_reset(hba);
6289
1d337ec2
SRT		 6290 err = ufshcd_host_reset_and_restore(hba);
6291 } while (err && --retries);
3441da7d 6292
3441da7d
SRT		 6293 return err;
6294}
6295
6296/**
6297 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 6298 * @cmd: SCSI command pointer
3441da7d
SRT		 6299 *
6300 * Returns SUCCESS/FAILED
6301 */
6302static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6303{
6304 int err;
6305 unsigned long flags;
6306 struct ufs_hba *hba;
6307
6308 hba = shost_priv(cmd->device->host);
6309
1ab27c9c 6310 ufshcd_hold(hba, false);
3441da7d
SRT		 6311 /*
6312 * Check if there is any race with fatal error handling.
6313 * If so, wait for it to complete. Even though fatal error
6314 * handling does reset and restore in some cases, don't assume
6315 * anything out of it. We are just avoiding race here.
6316 */
6317 do {
6318 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6319 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6320 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6321 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6322 break;
6323 spin_unlock_irqrestore(hba->host->host_lock, flags);
6324 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6325 flush_work(&hba->eh_work);
3441da7d
SRT		 6326 } while (1);
6327
6328 hba->ufshcd_state = UFSHCD_STATE_RESET;
6329 ufshcd_set_eh_in_progress(hba);
6330 spin_unlock_irqrestore(hba->host->host_lock, flags);
6331
6332 err = ufshcd_reset_and_restore(hba);
6333
6334 spin_lock_irqsave(hba->host->host_lock, flags);
6335 if (!err) {
6336 err = SUCCESS;
6337 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6338 } else {
6339 err = FAILED;
6340 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6341 }
6342 ufshcd_clear_eh_in_progress(hba);
6343 spin_unlock_irqrestore(hba->host->host_lock, flags);
6344
1ab27c9c 6345 ufshcd_release(hba);
3441da7d
SRT		 6346 return err;
6347}
6348
3a4bf06d
YG		 6349/**
6350 * ufshcd_get_max_icc_level - calculate the ICC level
6351 * @sup_curr_uA: max. current supported by the regulator
6352 * @start_scan: row at the desc table to start scan from
6353 * @buff: power descriptor buffer
6354 *
6355 * Returns calculated max ICC level for specific regulator
6356 */
6357static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6358{
6359 int i;
6360 int curr_uA;
6361 u16 data;
6362 u16 unit;
6363
6364 for (i = start_scan; i >= 0; i--) {
d79713f9 6365 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6366 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6367 ATTR_ICC_LVL_UNIT_OFFSET;
6368 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6369 switch (unit) {
6370 case UFSHCD_NANO_AMP:
6371 curr_uA = curr_uA / 1000;
6372 break;
6373 case UFSHCD_MILI_AMP:
6374 curr_uA = curr_uA * 1000;
6375 break;
6376 case UFSHCD_AMP:
6377 curr_uA = curr_uA * 1000 * 1000;
6378 break;
6379 case UFSHCD_MICRO_AMP:
6380 default:
6381 break;
6382 }
6383 if (sup_curr_uA >= curr_uA)
6384 break;
6385 }
6386 if (i < 0) {
6387 i = 0;
6388 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6389 }
6390
6391 return (u32)i;
6392}
6393
6394/**
6395 * ufshcd_calc_icc_level - calculate the max ICC level
6396 * In case regulators are not initialized we'll return 0
6397 * @hba: per-adapter instance
6398 * @desc_buf: power descriptor buffer to extract ICC levels from.
6399 * @len: length of desc_buff
6400 *
6401 * Returns calculated ICC level
6402 */
6403static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6404 u8 *desc_buf, int len)
6405{
6406 u32 icc_level = 0;
6407
6408 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6409 !hba->vreg_info.vccq2) {
6410 dev_err(hba->dev,
6411 "%s: Regulator capability was not set, actvIccLevel=%d",
6412 __func__, icc_level);
6413 goto out;
6414 }
6415
0487fff7 6416 if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
3a4bf06d
YG		 6417 icc_level = ufshcd_get_max_icc_level(
6418 hba->vreg_info.vcc->max_uA,
6419 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6420 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6421
0487fff7 6422 if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
3a4bf06d
YG		 6423 icc_level = ufshcd_get_max_icc_level(
6424 hba->vreg_info.vccq->max_uA,
6425 icc_level,
6426 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6427
0487fff7 6428 if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
3a4bf06d
YG		 6429 icc_level = ufshcd_get_max_icc_level(
6430 hba->vreg_info.vccq2->max_uA,
6431 icc_level,
6432 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6433out:
6434 return icc_level;
6435}
6436
6437static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6438{
6439 int ret;
a4b0e8a4 6440 int buff_len = hba->desc_size.pwr_desc;
bbe21d7a
KC		 6441 u8 *desc_buf;
6442
6443 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6444 if (!desc_buf)
6445 return;
3a4bf06d 6446
8c9a51b0
BH		 6447 ret = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0,
6448 desc_buf, buff_len);
3a4bf06d
YG		 6449 if (ret) {
6450 dev_err(hba->dev,
6451 "%s: Failed reading power descriptor.len = %d ret = %d",
6452 __func__, buff_len, ret);
bbe21d7a 6453 goto out;
3a4bf06d
YG		 6454 }
6455
6456 hba->init_prefetch_data.icc_level =
6457 ufshcd_find_max_sup_active_icc_level(hba,
6458 desc_buf, buff_len);
6459 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6460 __func__, hba->init_prefetch_data.icc_level);
6461
dbd34a61
SM		 6462 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6463 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6464 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 6465
6466 if (ret)
6467 dev_err(hba->dev,
6468 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6469 __func__, hba->init_prefetch_data.icc_level , ret);
6470
bbe21d7a
KC		 6471out:
6472 kfree(desc_buf);
3a4bf06d
YG		 6473}
6474
2a8fa600
SJ		 6475/**
6476 * ufshcd_scsi_add_wlus - Adds required W-LUs
6477 * @hba: per-adapter instance
6478 *
6479 * UFS device specification requires the UFS devices to support 4 well known
6480 * logical units:
6481 * "REPORT_LUNS" (address: 01h)
6482 * "UFS Device" (address: 50h)
6483 * "RPMB" (address: 44h)
6484 * "BOOT" (address: 30h)
6485 * UFS device's power management needs to be controlled by "POWER CONDITION"
6486 * field of SSU (START STOP UNIT) command. But this "power condition" field
6487 * will take effect only when its sent to "UFS device" well known logical unit
6488 * hence we require the scsi_device instance to represent this logical unit in
6489 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 6490 *
2a8fa600
SJ		 6491 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6492 * Block) LU so user space process can control this LU. User space may also
6493 * want to have access to BOOT LU.
8aa29f19 6494 *
2a8fa600
SJ		 6495 * This function adds scsi device instances for each of all well known LUs
6496 * (except "REPORT LUNS" LU).
6497 *
6498 * Returns zero on success (all required W-LUs are added successfully),
6499 * non-zero error value on failure (if failed to add any of the required W-LU).
6500 */
6501static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6502{
6503 int ret = 0;
7c48bfd0
AM		 6504 struct scsi_device *sdev_rpmb;
6505 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6506
6507 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6508 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6509 if (IS_ERR(hba->sdev_ufs_device)) {
6510 ret = PTR_ERR(hba->sdev_ufs_device);
6511 hba->sdev_ufs_device = NULL;
6512 goto out;
6513 }
7c48bfd0 6514 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6515
7c48bfd0 6516 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6517 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6518 if (IS_ERR(sdev_rpmb)) {
6519 ret = PTR_ERR(sdev_rpmb);
3d21fbde 6520 goto remove_sdev_ufs_device;
2a8fa600 6521 }
7c48bfd0 6522 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 6523
6524 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6525 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
6526 if (IS_ERR(sdev_boot))
6527 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
6528 else
6529 scsi_device_put(sdev_boot);
2a8fa600
SJ		 6530 goto out;
6531
2a8fa600
SJ		 6532remove_sdev_ufs_device:
6533 scsi_remove_device(hba->sdev_ufs_device);
6534out:
6535 return ret;
6536}
6537
09750066 6538static int ufs_get_device_desc(struct ufs_hba *hba)
c58ab7aa
YG		 6539{
6540 int err;
bbe21d7a 6541 size_t buff_len;
c58ab7aa 6542 u8 model_index;
bbe21d7a 6543 u8 *desc_buf;
09750066 6544 struct ufs_dev_info *dev_info = &hba->dev_info;
4b828fe1 6545
bbe21d7a
KC		 6546 buff_len = max_t(size_t, hba->desc_size.dev_desc,
6547 QUERY_DESC_MAX_SIZE + 1);
6548 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6549 if (!desc_buf) {
6550 err = -ENOMEM;
6551 goto out;
6552 }
c58ab7aa 6553
8c9a51b0
BH		 6554 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, desc_buf,
6555 hba->desc_size.dev_desc);
c58ab7aa
YG		 6556 if (err) {
6557 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6558 __func__, err);
6559 goto out;
6560 }
6561
6562 /*
6563 * getting vendor (manufacturerID) and Bank Index in big endian
6564 * format
6565 */
09750066 6566 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6567 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6568
09f17791
CG		 6569 /* getting Specification Version in big endian format */
6570 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
6571 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
6572
c58ab7aa 6573 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
4b828fe1 6574 err = ufshcd_read_string_desc(hba, model_index,
09750066 6575 &dev_info->model, SD_ASCII_STD);
4b828fe1 6576 if (err < 0) {
c58ab7aa
YG		 6577 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6578 __func__, err);
6579 goto out;
6580 }
6581
4b828fe1
TW		 6582 /*
6583 * ufshcd_read_string_desc returns size of the string
6584 * reset the error value
6585 */
6586 err = 0;
c58ab7aa
YG		 6587
6588out:
bbe21d7a 6589 kfree(desc_buf);
c58ab7aa
YG		 6590 return err;
6591}
6592
09750066 6593static void ufs_put_device_desc(struct ufs_hba *hba)
4b828fe1 6594{
09750066
BH		 6595 struct ufs_dev_info *dev_info = &hba->dev_info;
6596
6597 kfree(dev_info->model);
6598 dev_info->model = NULL;
4b828fe1
TW		 6599}
6600
09750066 6601static void ufs_fixup_device_setup(struct ufs_hba *hba)
c58ab7aa 6602{
c58ab7aa 6603 struct ufs_dev_fix *f;
09750066 6604 struct ufs_dev_info *dev_info = &hba->dev_info;
c58ab7aa
YG		 6605
6606 for (f = ufs_fixups; f->quirk; f++) {
09750066
BH		 6607 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
6608 f->wmanufacturerid == UFS_ANY_VENDOR) &&
6609 ((dev_info->model &&
6610 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
6611 !strcmp(f->model, UFS_ANY_MODEL)))
c58ab7aa
YG		 6612 hba->dev_quirks |= f->quirk;
6613 }
6614}
6615
37113106
YG		 6616/**
6617 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6618 * @hba: per-adapter instance
6619 *
6620 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6621 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6622 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6623 * the hibern8 exit latency.
6624 *
6625 * Returns zero on success, non-zero error value on failure.
6626 */
6627static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6628{
6629 int ret = 0;
6630 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6631
6632 ret = ufshcd_dme_peer_get(hba,
6633 UIC_ARG_MIB_SEL(
6634 RX_MIN_ACTIVATETIME_CAPABILITY,
6635 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6636 &peer_rx_min_activatetime);
6637 if (ret)
6638 goto out;
6639
6640 /* make sure proper unit conversion is applied */
6641 tuned_pa_tactivate =
6642 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6643 / PA_TACTIVATE_TIME_UNIT_US);
6644 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6645 tuned_pa_tactivate);
6646
6647out:
6648 return ret;
6649}
6650
6651/**
6652 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6653 * @hba: per-adapter instance
6654 *
6655 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6656 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6657 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6658 * This optimal value can help reduce the hibern8 exit latency.
6659 *
6660 * Returns zero on success, non-zero error value on failure.
6661 */
6662static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6663{
6664 int ret = 0;
6665 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6666 u32 max_hibern8_time, tuned_pa_hibern8time;
6667
6668 ret = ufshcd_dme_get(hba,
6669 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6670 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6671 &local_tx_hibern8_time_cap);
6672 if (ret)
6673 goto out;
6674
6675 ret = ufshcd_dme_peer_get(hba,
6676 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6677 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6678 &peer_rx_hibern8_time_cap);
6679 if (ret)
6680 goto out;
6681
6682 max_hibern8_time = max(local_tx_hibern8_time_cap,
6683 peer_rx_hibern8_time_cap);
6684 /* make sure proper unit conversion is applied */
6685 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6686 / PA_HIBERN8_TIME_UNIT_US);
6687 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6688 tuned_pa_hibern8time);
6689out:
6690 return ret;
6691}
6692
c6a6db43
SJ		 6693/**
6694 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6695 * less than device PA_TACTIVATE time.
6696 * @hba: per-adapter instance
6697 *
6698 * Some UFS devices require host PA_TACTIVATE to be lower than device
6699 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6700 * for such devices.
6701 *
6702 * Returns zero on success, non-zero error value on failure.
6703 */
6704static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6705{
6706 int ret = 0;
6707 u32 granularity, peer_granularity;
6708 u32 pa_tactivate, peer_pa_tactivate;
6709 u32 pa_tactivate_us, peer_pa_tactivate_us;
6710 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6711
6712 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6713 &granularity);
6714 if (ret)
6715 goto out;
6716
6717 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6718 &peer_granularity);
6719 if (ret)
6720 goto out;
6721
6722 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6723 (granularity > PA_GRANULARITY_MAX_VAL)) {
6724 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6725 __func__, granularity);
6726 return -EINVAL;
6727 }
6728
6729 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6730 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6731 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6732 __func__, peer_granularity);
6733 return -EINVAL;
6734 }
6735
6736 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6737 if (ret)
6738 goto out;
6739
6740 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6741 &peer_pa_tactivate);
6742 if (ret)
6743 goto out;
6744
6745 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6746 peer_pa_tactivate_us = peer_pa_tactivate *
6747 gran_to_us_table[peer_granularity - 1];
6748
6749 if (pa_tactivate_us > peer_pa_tactivate_us) {
6750 u32 new_peer_pa_tactivate;
6751
6752 new_peer_pa_tactivate = pa_tactivate_us /
6753 gran_to_us_table[peer_granularity - 1];
6754 new_peer_pa_tactivate++;
6755 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6756 new_peer_pa_tactivate);
6757 }
6758
6759out:
6760 return ret;
6761}
6762
09750066 6763static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
37113106
YG		 6764{
6765 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6766 ufshcd_tune_pa_tactivate(hba);
6767 ufshcd_tune_pa_hibern8time(hba);
6768 }
6769
e91ed9e0
CG		 6770 ufshcd_vops_apply_dev_quirks(hba);
6771
37113106
YG		 6772 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6773 /* set 1ms timeout for PA_TACTIVATE */
6774 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43
SJ		 6775
6776 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6777 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 6778}
6779
ff8e20c6
DR		 6780static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6781{
ff8e20c6
DR		 6782 hba->ufs_stats.hibern8_exit_cnt = 0;
6783 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7fabb77b 6784 hba->req_abort_count = 0;
ff8e20c6
DR		 6785}
6786
a4b0e8a4
PM		 6787static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6788{
6789 int err;
6790
6791 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6792 &hba->desc_size.dev_desc);
6793 if (err)
6794 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6795
6796 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6797 &hba->desc_size.pwr_desc);
6798 if (err)
6799 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6800
6801 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6802 &hba->desc_size.interc_desc);
6803 if (err)
6804 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6805
6806 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6807 &hba->desc_size.conf_desc);
6808 if (err)
6809 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6810
6811 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6812 &hba->desc_size.unit_desc);
6813 if (err)
6814 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6815
6816 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6817 &hba->desc_size.geom_desc);
6818 if (err)
6819 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
059efd84 6820
c648c2d2
SN		 6821 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
6822 &hba->desc_size.hlth_desc);
6823 if (err)
6824 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 6825}
6826
731f0621
BH		 6827static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
6828{
6829 int err;
6830 size_t buff_len;
6831 u8 *desc_buf;
6832
6833 buff_len = hba->desc_size.geom_desc;
6834 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6835 if (!desc_buf) {
6836 err = -ENOMEM;
6837 goto out;
6838 }
6839
6840 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6841 desc_buf, buff_len);
6842 if (err) {
6843 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
6844 __func__, err);
6845 goto out;
6846 }
6847
6848 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
6849 hba->dev_info.max_lu_supported = 32;
6850 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
6851 hba->dev_info.max_lu_supported = 8;
6852
6853out:
6854 kfree(desc_buf);
6855 return err;
6856}
6857
9e1e8a75
SJ		 6858static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
6859 {19200000, REF_CLK_FREQ_19_2_MHZ},
6860 {26000000, REF_CLK_FREQ_26_MHZ},
6861 {38400000, REF_CLK_FREQ_38_4_MHZ},
6862 {52000000, REF_CLK_FREQ_52_MHZ},
6863 {0, REF_CLK_FREQ_INVAL},
6864};
6865
6866static enum ufs_ref_clk_freq
6867ufs_get_bref_clk_from_hz(unsigned long freq)
6868{
6869 int i;
6870
6871 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
6872 if (ufs_ref_clk_freqs[i].freq_hz == freq)
6873 return ufs_ref_clk_freqs[i].val;
6874
6875 return REF_CLK_FREQ_INVAL;
6876}
6877
6878void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
6879{
6880 unsigned long freq;
6881
6882 freq = clk_get_rate(refclk);
6883
6884 hba->dev_ref_clk_freq =
6885 ufs_get_bref_clk_from_hz(freq);
6886
6887 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
6888 dev_err(hba->dev,
6889 "invalid ref_clk setting = %ld\n", freq);
6890}
6891
6892static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
6893{
6894 int err;
6895 u32 ref_clk;
6896 u32 freq = hba->dev_ref_clk_freq;
6897
6898 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6899 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
6900
6901 if (err) {
6902 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
6903 err);
6904 goto out;
6905 }
6906
6907 if (ref_clk == freq)
6908 goto out; /* nothing to update */
6909
6910 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6911 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
6912
6913 if (err) {
6914 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
6915 ufs_ref_clk_freqs[freq].freq_hz);
6916 goto out;
6917 }
6918
6919 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
6920 ufs_ref_clk_freqs[freq].freq_hz);
6921
6922out:
6923 return err;
6924}
6925
1b9e2141
BH		 6926static int ufshcd_device_params_init(struct ufs_hba *hba)
6927{
6928 bool flag;
6929 int ret;
6930
731f0621
BH		 6931 /* Clear any previous UFS device information */
6932 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
6933
1b9e2141
BH		 6934 /* Init check for device descriptor sizes */
6935 ufshcd_init_desc_sizes(hba);
6936
731f0621
BH		 6937 /* Init UFS geometry descriptor related parameters */
6938 ret = ufshcd_device_geo_params_init(hba);
6939 if (ret)
6940 goto out;
6941
1b9e2141
BH		 6942 /* Check and apply UFS device quirks */
6943 ret = ufs_get_device_desc(hba);
6944 if (ret) {
6945 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6946 __func__, ret);
6947 goto out;
6948 }
6949
09f17791
CG		 6950 ufshcd_get_ref_clk_gating_wait(hba);
6951
1b9e2141
BH		 6952 ufs_fixup_device_setup(hba);
6953
1b9e2141
BH		 6954 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6955 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
6956 hba->dev_info.f_power_on_wp_en = flag;
6957
2b35b2ad
BH		 6958 /* Probe maximum power mode co-supported by both UFS host and device */
6959 if (ufshcd_get_max_pwr_mode(hba))
6960 dev_err(hba->dev,
6961 "%s: Failed getting max supported power mode\n",
6962 __func__);
1b9e2141
BH		 6963out:
6964 return ret;
6965}
6966
6967/**
6968 * ufshcd_add_lus - probe and add UFS logical units
6969 * @hba: per-adapter instance
6970 */
6971static int ufshcd_add_lus(struct ufs_hba *hba)
6972{
6973 int ret;
6974
046c1e6f 6975 ufshcd_init_icc_levels(hba);
1b9e2141
BH		 6976
6977 /* Add required well known logical units to scsi mid layer */
6978 ret = ufshcd_scsi_add_wlus(hba);
6979 if (ret)
6980 goto out;
6981
6982 /* Initialize devfreq after UFS device is detected */
6983 if (ufshcd_is_clkscaling_supported(hba)) {
6984 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6985 &hba->pwr_info,
6986 sizeof(struct ufs_pa_layer_attr));
6987 hba->clk_scaling.saved_pwr_info.is_valid = true;
6988 if (!hba->devfreq) {
6989 ret = ufshcd_devfreq_init(hba);
6990 if (ret)
6991 goto out;
6992 }
6993
6994 hba->clk_scaling.is_allowed = true;
6995 }
6996
6997 ufs_bsg_probe(hba);
6998 scsi_scan_host(hba->host);
6999 pm_runtime_put_sync(hba->dev);
7000
1b9e2141
BH		 7001out:
7002 return ret;
7003}
7004
6ccf44fe 7005/**
1d337ec2
SRT		 7006 * ufshcd_probe_hba - probe hba to detect device and initialize
7007 * @hba: per-adapter instance
1b9e2141 7008 * @async: asynchronous execution or not
1d337ec2
SRT		 7009 *
7010 * Execute link-startup and verify device initialization
6ccf44fe 7011 */
1b9e2141 7012static int ufshcd_probe_hba(struct ufs_hba *hba, bool async)
6ccf44fe 7013{
6ccf44fe 7014 int ret;
7ff5ab47 7015 ktime_t start = ktime_get();
6ccf44fe
SJ		 7016
7017 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 7018 if (ret)
7019 goto out;
7020
afdfff59
YG		 7021 /* set the default level for urgent bkops */
7022 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
7023 hba->is_urgent_bkops_lvl_checked = false;
7024
ff8e20c6
DR		 7025 /* Debug counters initialization */
7026 ufshcd_clear_dbg_ufs_stats(hba);
7027
57d104c1
SJ		 7028 /* UniPro link is active now */
7029 ufshcd_set_link_active(hba);
d3e89bac 7030
1b9e2141 7031 /* Verify device initialization by sending NOP OUT UPIU */
5a0b0cb9
SRT		 7032 ret = ufshcd_verify_dev_init(hba);
7033 if (ret)
7034 goto out;
68078d5c 7035
1b9e2141 7036 /* Initiate UFS initialization, and waiting until completion */
68078d5c
DR		 7037 ret = ufshcd_complete_dev_init(hba);
7038 if (ret)
7039 goto out;
5a0b0cb9 7040
1b9e2141
BH		 7041 /*
7042 * Initialize UFS device parameters used by driver, these
7043 * parameters are associated with UFS descriptors.
7044 */
7045 if (async) {
7046 ret = ufshcd_device_params_init(hba);
7047 if (ret)
7048 goto out;
93fdd5ac
TW		 7049 }
7050
09750066 7051 ufshcd_tune_unipro_params(hba);
4b828fe1 7052
57d104c1
SJ		 7053 /* UFS device is also active now */
7054 ufshcd_set_ufs_dev_active(hba);
66ec6d59 7055 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 7056 hba->wlun_dev_clr_ua = true;
7057
2b35b2ad
BH		 7058 /* Gear up to HS gear if supported */
7059 if (hba->max_pwr_info.is_valid) {
9e1e8a75
SJ		 7060 /*
7061 * Set the right value to bRefClkFreq before attempting to
7062 * switch to HS gears.
7063 */
7064 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
7065 ufshcd_set_dev_ref_clk(hba);
7eb584db 7066 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 7067 if (ret) {
7eb584db
DR		 7068 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
7069 __func__, ret);
8643ae66
DL		 7070 goto out;
7071 }
7eb584db 7072 }
57d104c1 7073
53c12d0e
YG		 7074 /* set the state as operational after switching to desired gear */
7075 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 7076
71d848b8
CG		 7077 /* Enable Auto-Hibernate if configured */
7078 ufshcd_auto_hibern8_enable(hba);
7079
5a0b0cb9 7080out:
1d337ec2 7081
7ff5ab47
SJ		 7082 trace_ufshcd_init(dev_name(hba->dev), ret,
7083 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7084 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 7085 return ret;
7086}
7087
7088/**
7089 * ufshcd_async_scan - asynchronous execution for probing hba
7090 * @data: data pointer to pass to this function
7091 * @cookie: cookie data
7092 */
7093static void ufshcd_async_scan(void *data, async_cookie_t cookie)
7094{
7095 struct ufs_hba *hba = (struct ufs_hba *)data;
1b9e2141 7096 int ret;
1d337ec2 7097
1b9e2141
BH		 7098 /* Initialize hba, detect and initialize UFS device */
7099 ret = ufshcd_probe_hba(hba, true);
7100 if (ret)
7101 goto out;
7102
7103 /* Probe and add UFS logical units */
7104 ret = ufshcd_add_lus(hba);
7105out:
7106 /*
7107 * If we failed to initialize the device or the device is not
7108 * present, turn off the power/clocks etc.
7109 */
7110 if (ret) {
7111 pm_runtime_put_sync(hba->dev);
7112 ufshcd_exit_clk_scaling(hba);
7113 ufshcd_hba_exit(hba);
7114 }
6ccf44fe
SJ		 7115}
7116
d829fc8a
SN		 7117static const struct attribute_group *ufshcd_driver_groups[] = {
7118 &ufs_sysfs_unit_descriptor_group,
ec92b59c 7119 &ufs_sysfs_lun_attributes_group,
d829fc8a
SN		 7120 NULL,
7121};
7122
7a3e97b0
SY		 7123static struct scsi_host_template ufshcd_driver_template = {
7124 .module = THIS_MODULE,
7125 .name = UFSHCD,
7126 .proc_name = UFSHCD,
7127 .queuecommand = ufshcd_queuecommand,
7128 .slave_alloc = ufshcd_slave_alloc,
eeda4749 7129 .slave_configure = ufshcd_slave_configure,
7a3e97b0 7130 .slave_destroy = ufshcd_slave_destroy,
4264fd61 7131 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 7132 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 7133 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
7134 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 7135 .this_id = -1,
7136 .sg_tablesize = SG_ALL,
7137 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
7138 .can_queue = UFSHCD_CAN_QUEUE,
552a990c 7139 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
1ab27c9c 7140 .max_host_blocked = 1,
c40ecc12 7141 .track_queue_depth = 1,
d829fc8a 7142 .sdev_groups = ufshcd_driver_groups,
4af14d11 7143 .dma_boundary = PAGE_SIZE - 1,
49615ba1 7144 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
7a3e97b0
SY		 7145};
7146
57d104c1
SJ		 7147static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
7148 int ua)
7149{
7b16a07c 7150 int ret;
57d104c1 7151
7b16a07c
BA		 7152 if (!vreg)
7153 return 0;
57d104c1 7154
0487fff7
SC		 7155 /*
7156 * "set_load" operation shall be required on those regulators
7157 * which specifically configured current limitation. Otherwise
7158 * zero max_uA may cause unexpected behavior when regulator is
7159 * enabled or set as high power mode.
7160 */
7161 if (!vreg->max_uA)
7162 return 0;
7163
7b16a07c
BA		 7164 ret = regulator_set_load(vreg->reg, ua);
7165 if (ret < 0) {
7166 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7167 __func__, vreg->name, ua, ret);
57d104c1
SJ		 7168 }
7169
7170 return ret;
7171}
7172
7173static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
7174 struct ufs_vreg *vreg)
7175{
73067981 7176 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 7177}
7178
7179static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
7180 struct ufs_vreg *vreg)
7181{
7c7cfdcf
AH		 7182 if (!vreg)
7183 return 0;
7184
73067981 7185 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 7186}
7187
aa497613
SRT		 7188static int ufshcd_config_vreg(struct device *dev,
7189 struct ufs_vreg *vreg, bool on)
7190{
7191 int ret = 0;
72753590
GS		 7192 struct regulator *reg;
7193 const char *name;
aa497613
SRT		 7194 int min_uV, uA_load;
7195
7196 BUG_ON(!vreg);
7197
72753590
GS		 7198 reg = vreg->reg;
7199 name = vreg->name;
7200
aa497613 7201 if (regulator_count_voltages(reg) > 0) {
90d88f47
AD		 7202 uA_load = on ? vreg->max_uA : 0;
7203 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
7204 if (ret)
7205 goto out;
7206
3b141e8c
SC		 7207 if (vreg->min_uV && vreg->max_uV) {
7208 min_uV = on ? vreg->min_uV : 0;
7209 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
7210 if (ret) {
7211 dev_err(dev,
7212 "%s: %s set voltage failed, err=%d\n",
aa497613 7213 __func__, name, ret);
3b141e8c
SC		 7214 goto out;
7215 }
aa497613 7216 }
aa497613
SRT		 7217 }
7218out:
7219 return ret;
7220}
7221
7222static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
7223{
7224 int ret = 0;
7225
73067981 7226 if (!vreg || vreg->enabled)
aa497613
SRT		 7227 goto out;
7228
7229 ret = ufshcd_config_vreg(dev, vreg, true);
7230 if (!ret)
7231 ret = regulator_enable(vreg->reg);
7232
7233 if (!ret)
7234 vreg->enabled = true;
7235 else
7236 dev_err(dev, "%s: %s enable failed, err=%d\n",
7237 __func__, vreg->name, ret);
7238out:
7239 return ret;
7240}
7241
7242static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7243{
7244 int ret = 0;
7245
73067981 7246 if (!vreg || !vreg->enabled)
aa497613
SRT		 7247 goto out;
7248
7249 ret = regulator_disable(vreg->reg);
7250
7251 if (!ret) {
7252 /* ignore errors on applying disable config */
7253 ufshcd_config_vreg(dev, vreg, false);
7254 vreg->enabled = false;
7255 } else {
7256 dev_err(dev, "%s: %s disable failed, err=%d\n",
7257 __func__, vreg->name, ret);
7258 }
7259out:
7260 return ret;
7261}
7262
7263static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7264{
7265 int ret = 0;
7266 struct device *dev = hba->dev;
7267 struct ufs_vreg_info *info = &hba->vreg_info;
7268
aa497613
SRT		 7269 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7270 if (ret)
7271 goto out;
7272
7273 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7274 if (ret)
7275 goto out;
7276
7277 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7278 if (ret)
7279 goto out;
7280
7281out:
7282 if (ret) {
7283 ufshcd_toggle_vreg(dev, info->vccq2, false);
7284 ufshcd_toggle_vreg(dev, info->vccq, false);
7285 ufshcd_toggle_vreg(dev, info->vcc, false);
7286 }
7287 return ret;
7288}
7289
6a771a65
RS		 7290static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7291{
7292 struct ufs_vreg_info *info = &hba->vreg_info;
7293
60b7b823 7294 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6a771a65
RS		 7295}
7296
aa497613
SRT		 7297static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7298{
7299 int ret = 0;
7300
7301 if (!vreg)
7302 goto out;
7303
7304 vreg->reg = devm_regulator_get(dev, vreg->name);
7305 if (IS_ERR(vreg->reg)) {
7306 ret = PTR_ERR(vreg->reg);
7307 dev_err(dev, "%s: %s get failed, err=%d\n",
7308 __func__, vreg->name, ret);
7309 }
7310out:
7311 return ret;
7312}
7313
7314static int ufshcd_init_vreg(struct ufs_hba *hba)
7315{
7316 int ret = 0;
7317 struct device *dev = hba->dev;
7318 struct ufs_vreg_info *info = &hba->vreg_info;
7319
aa497613
SRT		 7320 ret = ufshcd_get_vreg(dev, info->vcc);
7321 if (ret)
7322 goto out;
7323
7324 ret = ufshcd_get_vreg(dev, info->vccq);
7325 if (ret)
7326 goto out;
7327
7328 ret = ufshcd_get_vreg(dev, info->vccq2);
7329out:
7330 return ret;
7331}
7332
6a771a65
RS		 7333static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7334{
7335 struct ufs_vreg_info *info = &hba->vreg_info;
7336
7337 if (info)
7338 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7339
7340 return 0;
7341}
7342
57d104c1
SJ		 7343static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7344 bool skip_ref_clk)
c6e79dac
SRT		 7345{
7346 int ret = 0;
7347 struct ufs_clk_info *clki;
7348 struct list_head *head = &hba->clk_list_head;
1ab27c9c 7349 unsigned long flags;
911a0771
SJ		 7350 ktime_t start = ktime_get();
7351 bool clk_state_changed = false;
c6e79dac 7352
566ec9ad 7353 if (list_empty(head))
c6e79dac
SRT		 7354 goto out;
7355
38f3242e
CG		 7356 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7357 if (ret)
7358 return ret;
1e879e8f 7359
c6e79dac
SRT		 7360 list_for_each_entry(clki, head, list) {
7361 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 7362 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7363 continue;
7364
911a0771 7365 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7366 if (on && !clki->enabled) {
7367 ret = clk_prepare_enable(clki->clk);
7368 if (ret) {
7369 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7370 __func__, clki->name, ret);
7371 goto out;
7372 }
7373 } else if (!on && clki->enabled) {
7374 clk_disable_unprepare(clki->clk);
7375 }
7376 clki->enabled = on;
7377 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7378 clki->name, on ? "en" : "dis");
7379 }
7380 }
1ab27c9c 7381
38f3242e
CG		 7382 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7383 if (ret)
7384 return ret;
1e879e8f 7385
c6e79dac
SRT		 7386out:
7387 if (ret) {
7388 list_for_each_entry(clki, head, list) {
7389 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7390 clk_disable_unprepare(clki->clk);
7391 }
7ff5ab47 7392 } else if (!ret && on) {
1ab27c9c
ST		 7393 spin_lock_irqsave(hba->host->host_lock, flags);
7394 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 7395 trace_ufshcd_clk_gating(dev_name(hba->dev),
7396 hba->clk_gating.state);
1ab27c9c 7397 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7398 }
7ff5ab47 7399
911a0771
SJ		 7400 if (clk_state_changed)
7401 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7402 (on ? "on" : "off"),
7403 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7404 return ret;
7405}
7406
57d104c1
SJ		 7407static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7408{
7409 return __ufshcd_setup_clocks(hba, on, false);
7410}
7411
c6e79dac
SRT		 7412static int ufshcd_init_clocks(struct ufs_hba *hba)
7413{
7414 int ret = 0;
7415 struct ufs_clk_info *clki;
7416 struct device *dev = hba->dev;
7417 struct list_head *head = &hba->clk_list_head;
7418
566ec9ad 7419 if (list_empty(head))
c6e79dac
SRT		 7420 goto out;
7421
7422 list_for_each_entry(clki, head, list) {
7423 if (!clki->name)
7424 continue;
7425
7426 clki->clk = devm_clk_get(dev, clki->name);
7427 if (IS_ERR(clki->clk)) {
7428 ret = PTR_ERR(clki->clk);
7429 dev_err(dev, "%s: %s clk get failed, %d\n",
7430 __func__, clki->name, ret);
7431 goto out;
7432 }
7433
9e1e8a75
SJ		 7434 /*
7435 * Parse device ref clk freq as per device tree "ref_clk".
7436 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
7437 * in ufshcd_alloc_host().
7438 */
7439 if (!strcmp(clki->name, "ref_clk"))
7440 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
7441
c6e79dac
SRT		 7442 if (clki->max_freq) {
7443 ret = clk_set_rate(clki->clk, clki->max_freq);
7444 if (ret) {
7445 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7446 __func__, clki->name,
7447 clki->max_freq, ret);
7448 goto out;
7449 }
856b3483 7450 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 7451 }
7452 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7453 clki->name, clk_get_rate(clki->clk));
7454 }
7455out:
7456 return ret;
7457}
7458
5c0c28a8
SRT		 7459static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7460{
7461 int err = 0;
7462
7463 if (!hba->vops)
7464 goto out;
7465
0263bcd0
YG		 7466 err = ufshcd_vops_init(hba);
7467 if (err)
7468 goto out;
5c0c28a8 7469
0263bcd0
YG		 7470 err = ufshcd_vops_setup_regulators(hba, true);
7471 if (err)
7472 goto out_exit;
5c0c28a8
SRT		 7473
7474 goto out;
7475
5c0c28a8 7476out_exit:
0263bcd0 7477 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7478out:
7479 if (err)
7480 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7481 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7482 return err;
7483}
7484
7485static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7486{
7487 if (!hba->vops)
7488 return;
7489
0263bcd0 7490 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7491
0263bcd0 7492 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7493}
7494
aa497613
SRT		 7495static int ufshcd_hba_init(struct ufs_hba *hba)
7496{
7497 int err;
7498
6a771a65
RS		 7499 /*
7500 * Handle host controller power separately from the UFS device power
7501 * rails as it will help controlling the UFS host controller power
7502 * collapse easily which is different than UFS device power collapse.
7503 * Also, enable the host controller power before we go ahead with rest
7504 * of the initialization here.
7505 */
7506 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7507 if (err)
7508 goto out;
7509
6a771a65 7510 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7511 if (err)
7512 goto out;
7513
6a771a65
RS		 7514 err = ufshcd_init_clocks(hba);
7515 if (err)
7516 goto out_disable_hba_vreg;
7517
7518 err = ufshcd_setup_clocks(hba, true);
7519 if (err)
7520 goto out_disable_hba_vreg;
7521
c6e79dac
SRT		 7522 err = ufshcd_init_vreg(hba);
7523 if (err)
7524 goto out_disable_clks;
7525
7526 err = ufshcd_setup_vreg(hba, true);
7527 if (err)
7528 goto out_disable_clks;
7529
aa497613
SRT		 7530 err = ufshcd_variant_hba_init(hba);
7531 if (err)
7532 goto out_disable_vreg;
7533
1d337ec2 7534 hba->is_powered = true;
aa497613
SRT		 7535 goto out;
7536
7537out_disable_vreg:
7538 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7539out_disable_clks:
7540 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7541out_disable_hba_vreg:
7542 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7543out:
7544 return err;
7545}
7546
7547static void ufshcd_hba_exit(struct ufs_hba *hba)
7548{
1d337ec2
SRT		 7549 if (hba->is_powered) {
7550 ufshcd_variant_hba_exit(hba);
7551 ufshcd_setup_vreg(hba, false);
a508253d 7552 ufshcd_suspend_clkscaling(hba);
eebcc196 7553 if (ufshcd_is_clkscaling_supported(hba))
0701e49d
SJ		 7554 if (hba->devfreq)
7555 ufshcd_suspend_clkscaling(hba);
1d337ec2
SRT		 7556 ufshcd_setup_clocks(hba, false);
7557 ufshcd_setup_hba_vreg(hba, false);
7558 hba->is_powered = false;
09750066 7559 ufs_put_device_desc(hba);
1d337ec2 7560 }
aa497613
SRT		 7561}
7562
57d104c1
SJ		 7563static int
7564ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7565{
7566 unsigned char cmd[6] = {REQUEST_SENSE,
7567 0,
7568 0,
7569 0,
09a5a24f 7570 UFS_SENSE_SIZE,
57d104c1
SJ		 7571 0};
7572 char *buffer;
7573 int ret;
7574
09a5a24f 7575 buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7576 if (!buffer) {
7577 ret = -ENOMEM;
7578 goto out;
7579 }
7580
fcbfffe2 7581 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
09a5a24f 7582 UFS_SENSE_SIZE, NULL, NULL,
fcbfffe2 7583 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7584 if (ret)
7585 pr_err("%s: failed with err %d\n", __func__, ret);
7586
7587 kfree(buffer);
7588out:
7589 return ret;
7590}
7591
7592/**
7593 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7594 * power mode
7595 * @hba: per adapter instance
7596 * @pwr_mode: device power mode to set
7597 *
7598 * Returns 0 if requested power mode is set successfully
7599 * Returns non-zero if failed to set the requested power mode
7600 */
7601static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7602 enum ufs_dev_pwr_mode pwr_mode)
7603{
7604 unsigned char cmd[6] = { START_STOP };
7605 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7606 struct scsi_device *sdp;
7607 unsigned long flags;
57d104c1
SJ		 7608 int ret;
7609
7c48bfd0
AM		 7610 spin_lock_irqsave(hba->host->host_lock, flags);
7611 sdp = hba->sdev_ufs_device;
7612 if (sdp) {
7613 ret = scsi_device_get(sdp);
7614 if (!ret && !scsi_device_online(sdp)) {
7615 ret = -ENODEV;
7616 scsi_device_put(sdp);
7617 }
7618 } else {
7619 ret = -ENODEV;
7620 }
7621 spin_unlock_irqrestore(hba->host->host_lock, flags);
7622
7623 if (ret)
7624 return ret;
57d104c1
SJ		 7625
7626 /*
7627 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7628 * handling, which would wait for host to be resumed. Since we know
7629 * we are functional while we are here, skip host resume in error
7630 * handling context.
7631 */
7632 hba->host->eh_noresume = 1;
7633 if (hba->wlun_dev_clr_ua) {
7634 ret = ufshcd_send_request_sense(hba, sdp);
7635 if (ret)
7636 goto out;
7637 /* Unit attention condition is cleared now */
7638 hba->wlun_dev_clr_ua = false;
7639 }
7640
7641 cmd[4] = pwr_mode << 4;
7642
7643 /*
7644 * Current function would be generally called from the power management
e8064021 7645 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7646 * already suspended childs.
7647 */
fcbfffe2
CH		 7648 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7649 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7650 if (ret) {
7651 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7652 "START_STOP failed for power mode: %d, result %x\n",
7653 pwr_mode, ret);
c65be1a6 7654 if (driver_byte(ret) == DRIVER_SENSE)
21045519 7655 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7656 }
7657
7658 if (!ret)
7659 hba->curr_dev_pwr_mode = pwr_mode;
7660out:
7c48bfd0 7661 scsi_device_put(sdp);
57d104c1
SJ		 7662 hba->host->eh_noresume = 0;
7663 return ret;
7664}
7665
7666static int ufshcd_link_state_transition(struct ufs_hba *hba,
7667 enum uic_link_state req_link_state,
7668 int check_for_bkops)
7669{
7670 int ret = 0;
7671
7672 if (req_link_state == hba->uic_link_state)
7673 return 0;
7674
7675 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7676 ret = ufshcd_uic_hibern8_enter(hba);
7677 if (!ret)
7678 ufshcd_set_link_hibern8(hba);
7679 else
7680 goto out;
7681 }
7682 /*
7683 * If autobkops is enabled, link can't be turned off because
7684 * turning off the link would also turn off the device.
7685 */
7686 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
dc30c9e6 7687 (!check_for_bkops || !hba->auto_bkops_enabled)) {
f3099fbd
YG		 7688 /*
7689 * Let's make sure that link is in low power mode, we are doing
7690 * this currently by putting the link in Hibern8. Otherway to
7691 * put the link in low power mode is to send the DME end point
7692 * to device and then send the DME reset command to local
7693 * unipro. But putting the link in hibern8 is much faster.
7694 */
7695 ret = ufshcd_uic_hibern8_enter(hba);
7696 if (ret)
7697 goto out;
57d104c1
SJ		 7698 /*
7699 * Change controller state to "reset state" which
7700 * should also put the link in off/reset state
7701 */
596585a2 7702 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 7703 /*
7704 * TODO: Check if we need any delay to make sure that
7705 * controller is reset
7706 */
7707 ufshcd_set_link_off(hba);
7708 }
7709
7710out:
7711 return ret;
7712}
7713
7714static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7715{
b799fdf7
YG		 7716 /*
7717 * It seems some UFS devices may keep drawing more than sleep current
7718 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7719 * To avoid this situation, add 2ms delay before putting these UFS
7720 * rails in LPM mode.
7721 */
7722 if (!ufshcd_is_link_active(hba) &&
7723 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7724 usleep_range(2000, 2100);
7725
57d104c1
SJ		 7726 /*
7727 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7728 * power.
7729 *
7730 * If UFS device and link is in OFF state, all power supplies (VCC,
7731 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7732 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7733 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7734 *
7735 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7736 * in low power state which would save some power.
7737 */
7738 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7739 !hba->dev_info.is_lu_power_on_wp) {
7740 ufshcd_setup_vreg(hba, false);
7741 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7742 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7743 if (!ufshcd_is_link_active(hba)) {
7744 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7745 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7746 }
7747 }
7748}
7749
7750static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7751{
7752 int ret = 0;
7753
7754 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7755 !hba->dev_info.is_lu_power_on_wp) {
7756 ret = ufshcd_setup_vreg(hba, true);
7757 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7758 if (!ret && !ufshcd_is_link_active(hba)) {
7759 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7760 if (ret)
7761 goto vcc_disable;
7762 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7763 if (ret)
7764 goto vccq_lpm;
7765 }
69d72ac8 7766 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7767 }
7768 goto out;
7769
7770vccq_lpm:
7771 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7772vcc_disable:
7773 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7774out:
7775 return ret;
7776}
7777
7778static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7779{
7780 if (ufshcd_is_link_off(hba))
7781 ufshcd_setup_hba_vreg(hba, false);
7782}
7783
7784static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7785{
7786 if (ufshcd_is_link_off(hba))
7787 ufshcd_setup_hba_vreg(hba, true);
7788}
7789
7a3e97b0 7790/**
57d104c1 7791 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7792 * @hba: per adapter instance
57d104c1
SJ		 7793 * @pm_op: desired low power operation type
7794 *
7795 * This function will try to put the UFS device and link into low power
7796 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7797 * (System PM level).
7798 *
7799 * If this function is called during shutdown, it will make sure that
7800 * both UFS device and UFS link is powered off.
7a3e97b0 7801 *
57d104c1
SJ		 7802 * NOTE: UFS device & link must be active before we enter in this function.
7803 *
7804 * Returns 0 for success and non-zero for failure
7a3e97b0 7805 */
57d104c1 7806static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7807{
57d104c1
SJ		 7808 int ret = 0;
7809 enum ufs_pm_level pm_lvl;
7810 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7811 enum uic_link_state req_link_state;
7812
7813 hba->pm_op_in_progress = 1;
7814 if (!ufshcd_is_shutdown_pm(pm_op)) {
7815 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7816 hba->rpm_lvl : hba->spm_lvl;
7817 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7818 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7819 } else {
7820 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7821 req_link_state = UIC_LINK_OFF_STATE;
7822 }
7823
7a3e97b0 7824 /*
57d104c1
SJ		 7825 * If we can't transition into any of the low power modes
7826 * just gate the clocks.
7a3e97b0 7827 */
1ab27c9c
ST		 7828 ufshcd_hold(hba, false);
7829 hba->clk_gating.is_suspended = true;
7830
401f1e44
SJ		 7831 if (hba->clk_scaling.is_allowed) {
7832 cancel_work_sync(&hba->clk_scaling.suspend_work);
7833 cancel_work_sync(&hba->clk_scaling.resume_work);
7834 ufshcd_suspend_clkscaling(hba);
7835 }
d6fcf81a 7836
57d104c1
SJ		 7837 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7838 req_link_state == UIC_LINK_ACTIVE_STATE) {
7839 goto disable_clks;
7840 }
7a3e97b0 7841
57d104c1
SJ		 7842 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7843 (req_link_state == hba->uic_link_state))
d6fcf81a 7844 goto enable_gating;
57d104c1
SJ		 7845
7846 /* UFS device & link must be active before we enter in this function */
7847 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7848 ret = -EINVAL;
d6fcf81a 7849 goto enable_gating;
57d104c1
SJ		 7850 }
7851
7852 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7853 if (ufshcd_can_autobkops_during_suspend(hba)) {
7854 /*
7855 * The device is idle with no requests in the queue,
7856 * allow background operations if bkops status shows
7857 * that performance might be impacted.
7858 */
7859 ret = ufshcd_urgent_bkops(hba);
7860 if (ret)
7861 goto enable_gating;
7862 } else {
7863 /* make sure that auto bkops is disabled */
7864 ufshcd_disable_auto_bkops(hba);
7865 }
57d104c1
SJ		 7866 }
7867
7868 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7869 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7870 !ufshcd_is_runtime_pm(pm_op))) {
7871 /* ensure that bkops is disabled */
7872 ufshcd_disable_auto_bkops(hba);
7873 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7874 if (ret)
1ab27c9c 7875 goto enable_gating;
57d104c1
SJ		 7876 }
7877
2824ec9f 7878 flush_work(&hba->eeh_work);
57d104c1
SJ		 7879 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7880 if (ret)
7881 goto set_dev_active;
7882
7883 ufshcd_vreg_set_lpm(hba);
7884
7885disable_clks:
7886 /*
7887 * Call vendor specific suspend callback. As these callbacks may access
7888 * vendor specific host controller register space call them before the
7889 * host clocks are ON.
7890 */
0263bcd0
YG		 7891 ret = ufshcd_vops_suspend(hba, pm_op);
7892 if (ret)
7893 goto set_link_active;
dcb6cec5
SC		 7894 /*
7895 * Disable the host irq as host controller as there won't be any
7896 * host controller transaction expected till resume.
7897 */
7898 ufshcd_disable_irq(hba);
57d104c1 7899
57d104c1
SJ		 7900 if (!ufshcd_is_link_active(hba))
7901 ufshcd_setup_clocks(hba, false);
7902 else
7903 /* If link is active, device ref_clk can't be switched off */
7904 __ufshcd_setup_clocks(hba, false, true);
7905
1ab27c9c 7906 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7907 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
dcb6cec5 7908
57d104c1
SJ		 7909 /* Put the host controller in low power mode if possible */
7910 ufshcd_hba_vreg_set_lpm(hba);
7911 goto out;
7912
57d104c1 7913set_link_active:
401f1e44
SJ		 7914 if (hba->clk_scaling.is_allowed)
7915 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 7916 ufshcd_vreg_set_hpm(hba);
7917 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7918 ufshcd_set_link_active(hba);
7919 else if (ufshcd_is_link_off(hba))
7920 ufshcd_host_reset_and_restore(hba);
7921set_dev_active:
7922 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7923 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7924enable_gating:
401f1e44
SJ		 7925 if (hba->clk_scaling.is_allowed)
7926 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7927 hba->clk_gating.is_suspended = false;
7928 ufshcd_release(hba);
57d104c1
SJ		 7929out:
7930 hba->pm_op_in_progress = 0;
8808b4e9
SC		 7931 if (ret)
7932 ufshcd_update_reg_hist(&hba->ufs_stats.suspend_err, (u32)ret);
57d104c1 7933 return ret;
7a3e97b0
SY		 7934}
7935
7936/**
57d104c1 7937 * ufshcd_resume - helper function for resume operations
3b1d0580 7938 * @hba: per adapter instance
57d104c1 7939 * @pm_op: runtime PM or system PM
7a3e97b0 7940 *
57d104c1
SJ		 7941 * This function basically brings the UFS device, UniPro link and controller
7942 * to active state.
7943 *
7944 * Returns 0 for success and non-zero for failure
7a3e97b0 7945 */
57d104c1 7946static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7947{
57d104c1
SJ		 7948 int ret;
7949 enum uic_link_state old_link_state;
7950
7951 hba->pm_op_in_progress = 1;
7952 old_link_state = hba->uic_link_state;
7953
7954 ufshcd_hba_vreg_set_hpm(hba);
7955 /* Make sure clocks are enabled before accessing controller */
7956 ret = ufshcd_setup_clocks(hba, true);
7957 if (ret)
7958 goto out;
7959
57d104c1 7960 /* enable the host irq as host controller would be active soon */
5231d38c 7961 ufshcd_enable_irq(hba);
57d104c1
SJ		 7962
7963 ret = ufshcd_vreg_set_hpm(hba);
7964 if (ret)
7965 goto disable_irq_and_vops_clks;
7966
7a3e97b0 7967 /*
57d104c1
SJ		 7968 * Call vendor specific resume callback. As these callbacks may access
7969 * vendor specific host controller register space call them when the
7970 * host clocks are ON.
7a3e97b0 7971 */
0263bcd0
YG		 7972 ret = ufshcd_vops_resume(hba, pm_op);
7973 if (ret)
7974 goto disable_vreg;
57d104c1
SJ		 7975
7976 if (ufshcd_is_link_hibern8(hba)) {
7977 ret = ufshcd_uic_hibern8_exit(hba);
7978 if (!ret)
7979 ufshcd_set_link_active(hba);
7980 else
7981 goto vendor_suspend;
7982 } else if (ufshcd_is_link_off(hba)) {
7983 ret = ufshcd_host_reset_and_restore(hba);
7984 /*
7985 * ufshcd_host_reset_and_restore() should have already
7986 * set the link state as active
7987 */
7988 if (ret || !ufshcd_is_link_active(hba))
7989 goto vendor_suspend;
7990 }
7991
7992 if (!ufshcd_is_ufs_dev_active(hba)) {
7993 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7994 if (ret)
7995 goto set_old_link_state;
7996 }
7997
4e768e76
SJ		 7998 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7999 ufshcd_enable_auto_bkops(hba);
8000 else
8001 /*
8002 * If BKOPs operations are urgently needed at this moment then
8003 * keep auto-bkops enabled or else disable it.
8004 */
8005 ufshcd_urgent_bkops(hba);
8006
1ab27c9c
ST		 8007 hba->clk_gating.is_suspended = false;
8008
fcb0c4b0
ST		 8009 if (hba->clk_scaling.is_allowed)
8010 ufshcd_resume_clkscaling(hba);
856b3483 8011
ad448378
AH		 8012 /* Enable Auto-Hibernate if configured */
8013 ufshcd_auto_hibern8_enable(hba);
8014
71d848b8
CG		 8015 /* Schedule clock gating in case of no access to UFS device yet */
8016 ufshcd_release(hba);
8017
57d104c1
SJ		 8018 goto out;
8019
8020set_old_link_state:
8021 ufshcd_link_state_transition(hba, old_link_state, 0);
8022vendor_suspend:
0263bcd0 8023 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 8024disable_vreg:
8025 ufshcd_vreg_set_lpm(hba);
8026disable_irq_and_vops_clks:
8027 ufshcd_disable_irq(hba);
401f1e44
SJ		 8028 if (hba->clk_scaling.is_allowed)
8029 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 8030 ufshcd_setup_clocks(hba, false);
8031out:
8032 hba->pm_op_in_progress = 0;
8808b4e9
SC		 8033 if (ret)
8034 ufshcd_update_reg_hist(&hba->ufs_stats.resume_err, (u32)ret);
57d104c1
SJ		 8035 return ret;
8036}
8037
8038/**
8039 * ufshcd_system_suspend - system suspend routine
8040 * @hba: per adapter instance
57d104c1
SJ		 8041 *
8042 * Check the description of ufshcd_suspend() function for more details.
8043 *
8044 * Returns 0 for success and non-zero for failure
8045 */
8046int ufshcd_system_suspend(struct ufs_hba *hba)
8047{
8048 int ret = 0;
7ff5ab47 8049 ktime_t start = ktime_get();
57d104c1
SJ		 8050
8051 if (!hba || !hba->is_powered)
233b594b 8052 return 0;
57d104c1 8053
0b257734
SJ		 8054 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
8055 hba->curr_dev_pwr_mode) &&
8056 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
8057 hba->uic_link_state))
8058 goto out;
57d104c1 8059
0b257734 8060 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 8061 /*
8062 * UFS device and/or UFS link low power states during runtime
8063 * suspend seems to be different than what is expected during
8064 * system suspend. Hence runtime resume the devic & link and
8065 * let the system suspend low power states to take effect.
8066 * TODO: If resume takes longer time, we might have optimize
8067 * it in future by not resuming everything if possible.
8068 */
8069 ret = ufshcd_runtime_resume(hba);
8070 if (ret)
8071 goto out;
8072 }
8073
8074 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
8075out:
7ff5ab47
SJ		 8076 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
8077 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8078 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 8079 if (!ret)
8080 hba->is_sys_suspended = true;
57d104c1
SJ		 8081 return ret;
8082}
8083EXPORT_SYMBOL(ufshcd_system_suspend);
8084
8085/**
8086 * ufshcd_system_resume - system resume routine
8087 * @hba: per adapter instance
8088 *
8089 * Returns 0 for success and non-zero for failure
8090 */
7a3e97b0 8091
57d104c1
SJ		 8092int ufshcd_system_resume(struct ufs_hba *hba)
8093{
7ff5ab47
SJ		 8094 int ret = 0;
8095 ktime_t start = ktime_get();
8096
e3ce73d6
YG		 8097 if (!hba)
8098 return -EINVAL;
8099
8100 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 8101 /*
8102 * Let the runtime resume take care of resuming
8103 * if runtime suspended.
8104 */
7ff5ab47
SJ		 8105 goto out;
8106 else
8107 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
8108out:
8109 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
8110 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8111 hba->curr_dev_pwr_mode, hba->uic_link_state);
ce9e7bce
SC		 8112 if (!ret)
8113 hba->is_sys_suspended = false;
7ff5ab47 8114 return ret;
7a3e97b0 8115}
57d104c1 8116EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 8117
57d104c1
SJ		 8118/**
8119 * ufshcd_runtime_suspend - runtime suspend routine
8120 * @hba: per adapter instance
8121 *
8122 * Check the description of ufshcd_suspend() function for more details.
8123 *
8124 * Returns 0 for success and non-zero for failure
8125 */
66ec6d59
SRT		 8126int ufshcd_runtime_suspend(struct ufs_hba *hba)
8127{
7ff5ab47
SJ		 8128 int ret = 0;
8129 ktime_t start = ktime_get();
8130
e3ce73d6
YG		 8131 if (!hba)
8132 return -EINVAL;
8133
8134 if (!hba->is_powered)
7ff5ab47
SJ		 8135 goto out;
8136 else
8137 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
8138out:
8139 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
8140 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8141 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8142 return ret;
66ec6d59
SRT		 8143}
8144EXPORT_SYMBOL(ufshcd_runtime_suspend);
8145
57d104c1
SJ		 8146/**
8147 * ufshcd_runtime_resume - runtime resume routine
8148 * @hba: per adapter instance
8149 *
8150 * This function basically brings the UFS device, UniPro link and controller
8151 * to active state. Following operations are done in this function:
8152 *
8153 * 1. Turn on all the controller related clocks
8154 * 2. Bring the UniPro link out of Hibernate state
8155 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
8156 * to active state.
8157 * 4. If auto-bkops is enabled on the device, disable it.
8158 *
8159 * So following would be the possible power state after this function return
8160 * successfully:
8161 * S1: UFS device in Active state with VCC rail ON
8162 * UniPro link in Active state
8163 * All the UFS/UniPro controller clocks are ON
8164 *
8165 * Returns 0 for success and non-zero for failure
8166 */
66ec6d59
SRT		 8167int ufshcd_runtime_resume(struct ufs_hba *hba)
8168{
7ff5ab47
SJ		 8169 int ret = 0;
8170 ktime_t start = ktime_get();
8171
e3ce73d6
YG		 8172 if (!hba)
8173 return -EINVAL;
8174
8175 if (!hba->is_powered)
7ff5ab47
SJ		 8176 goto out;
8177 else
8178 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
8179out:
8180 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
8181 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8182 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8183 return ret;
66ec6d59
SRT		 8184}
8185EXPORT_SYMBOL(ufshcd_runtime_resume);
8186
8187int ufshcd_runtime_idle(struct ufs_hba *hba)
8188{
8189 return 0;
8190}
8191EXPORT_SYMBOL(ufshcd_runtime_idle);
8192
57d104c1
SJ		 8193/**
8194 * ufshcd_shutdown - shutdown routine
8195 * @hba: per adapter instance
8196 *
8197 * This function would power off both UFS device and UFS link.
8198 *
8199 * Returns 0 always to allow force shutdown even in case of errors.
8200 */
8201int ufshcd_shutdown(struct ufs_hba *hba)
8202{
8203 int ret = 0;
8204
f51913ee
SC		 8205 if (!hba->is_powered)
8206 goto out;
8207
57d104c1
SJ		 8208 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8209 goto out;
8210
8211 if (pm_runtime_suspended(hba->dev)) {
8212 ret = ufshcd_runtime_resume(hba);
8213 if (ret)
8214 goto out;
8215 }
8216
8217 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8218out:
8219 if (ret)
8220 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8221 /* allow force shutdown even in case of errors */
8222 return 0;
8223}
8224EXPORT_SYMBOL(ufshcd_shutdown);
8225
7a3e97b0 8226/**
3b1d0580 8227 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 8228 * data structure memory
8aa29f19 8229 * @hba: per adapter instance
7a3e97b0 8230 */
3b1d0580 8231void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 8232{
df032bf2 8233 ufs_bsg_remove(hba);
cbb6813e 8234 ufs_sysfs_remove_nodes(hba->dev);
69a6c269
BVA		 8235 blk_cleanup_queue(hba->tmf_queue);
8236 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360 8237 blk_cleanup_queue(hba->cmd_queue);
cfdf9c91 8238 scsi_remove_host(hba->host);
7a3e97b0 8239 /* disable interrupts */
2fbd009b 8240 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 8241 ufshcd_hba_stop(hba, true);
7a3e97b0 8242
eebcc196 8243 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8244 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 8245 if (ufshcd_is_clkscaling_supported(hba))
8246 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 8247 ufshcd_hba_exit(hba);
3b1d0580
VH		 8248}
8249EXPORT_SYMBOL_GPL(ufshcd_remove);
8250
47555a5c
YG		 8251/**
8252 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
8253 * @hba: pointer to Host Bus Adapter (HBA)
8254 */
8255void ufshcd_dealloc_host(struct ufs_hba *hba)
8256{
8257 scsi_host_put(hba->host);
8258}
8259EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8260
ca3d7bf9
AM		 8261/**
8262 * ufshcd_set_dma_mask - Set dma mask based on the controller
8263 * addressing capability
8264 * @hba: per adapter instance
8265 *
8266 * Returns 0 for success, non-zero for failure
8267 */
8268static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8269{
8270 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8271 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8272 return 0;
8273 }
8274 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8275}
8276
7a3e97b0 8277/**
5c0c28a8 8278 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 8279 * @dev: pointer to device handle
8280 * @hba_handle: driver private handle
7a3e97b0
SY		 8281 * Returns 0 on success, non-zero value on failure
8282 */
5c0c28a8 8283int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 8284{
8285 struct Scsi_Host *host;
8286 struct ufs_hba *hba;
5c0c28a8 8287 int err = 0;
7a3e97b0 8288
3b1d0580
VH		 8289 if (!dev) {
8290 dev_err(dev,
8291 "Invalid memory reference for dev is NULL\n");
8292 err = -ENODEV;
7a3e97b0
SY		 8293 goto out_error;
8294 }
8295
7a3e97b0
SY		 8296 host = scsi_host_alloc(&ufshcd_driver_template,
8297 sizeof(struct ufs_hba));
8298 if (!host) {
3b1d0580 8299 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 8300 err = -ENOMEM;
3b1d0580 8301 goto out_error;
7a3e97b0
SY		 8302 }
8303 hba = shost_priv(host);
7a3e97b0 8304 hba->host = host;
3b1d0580 8305 hba->dev = dev;
5c0c28a8 8306 *hba_handle = hba;
9e1e8a75 8307 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
5c0c28a8 8308
566ec9ad
SM		 8309 INIT_LIST_HEAD(&hba->clk_list_head);
8310
5c0c28a8
SRT		 8311out_error:
8312 return err;
8313}
8314EXPORT_SYMBOL(ufshcd_alloc_host);
8315
69a6c269
BVA		 8316/* This function exists because blk_mq_alloc_tag_set() requires this. */
8317static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
8318 const struct blk_mq_queue_data *qd)
8319{
8320 WARN_ON_ONCE(true);
8321 return BLK_STS_NOTSUPP;
8322}
8323
8324static const struct blk_mq_ops ufshcd_tmf_ops = {
8325 .queue_rq = ufshcd_queue_tmf,
8326};
8327
5c0c28a8
SRT		 8328/**
8329 * ufshcd_init - Driver initialization routine
8330 * @hba: per-adapter instance
8331 * @mmio_base: base register address
8332 * @irq: Interrupt line of device
8333 * Returns 0 on success, non-zero value on failure
8334 */
8335int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8336{
8337 int err;
8338 struct Scsi_Host *host = hba->host;
8339 struct device *dev = hba->dev;
8340
8341 if (!mmio_base) {
8342 dev_err(hba->dev,
8343 "Invalid memory reference for mmio_base is NULL\n");
8344 err = -ENODEV;
8345 goto out_error;
8346 }
8347
3b1d0580
VH		 8348 hba->mmio_base = mmio_base;
8349 hba->irq = irq;
7a3e97b0 8350
aa497613 8351 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 8352 if (err)
8353 goto out_error;
8354
7a3e97b0
SY		 8355 /* Read capabilities registers */
8356 ufshcd_hba_capabilities(hba);
8357
8358 /* Get UFS version supported by the controller */
8359 hba->ufs_version = ufshcd_get_ufs_version(hba);
8360
c01848c6
YG		 8361 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8362 (hba->ufs_version != UFSHCI_VERSION_11) &&
8363 (hba->ufs_version != UFSHCI_VERSION_20) &&
8364 (hba->ufs_version != UFSHCI_VERSION_21))
8365 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8366 hba->ufs_version);
8367
2fbd009b
SJ		 8368 /* Get Interrupt bit mask per version */
8369 hba->intr_mask = ufshcd_get_intr_mask(hba);
8370
ca3d7bf9
AM		 8371 err = ufshcd_set_dma_mask(hba);
8372 if (err) {
8373 dev_err(hba->dev, "set dma mask failed\n");
8374 goto out_disable;
8375 }
8376
7a3e97b0
SY		 8377 /* Allocate memory for host memory space */
8378 err = ufshcd_memory_alloc(hba);
8379 if (err) {
3b1d0580
VH		 8380 dev_err(hba->dev, "Memory allocation failed\n");
8381 goto out_disable;
7a3e97b0
SY		 8382 }
8383
8384 /* Configure LRB */
8385 ufshcd_host_memory_configure(hba);
8386
8387 host->can_queue = hba->nutrs;
8388 host->cmd_per_lun = hba->nutrs;
8389 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8390 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8391 host->max_channel = UFSHCD_MAX_CHANNEL;
8392 host->unique_id = host->host_no;
a851b2bd 8393 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 8394
7eb584db
DR		 8395 hba->max_pwr_info.is_valid = false;
8396
7a3e97b0 8397 /* Initialize work queues */
e8e7f271 8398 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8399 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8400
6ccf44fe
SJ		 8401 /* Initialize UIC command mutex */
8402 mutex_init(&hba->uic_cmd_mutex);
8403
5a0b0cb9
SRT		 8404 /* Initialize mutex for device management commands */
8405 mutex_init(&hba->dev_cmd.lock);
8406
a3cd5ec5
SJ		 8407 init_rwsem(&hba->clk_scaling_lock);
8408
1ab27c9c 8409 ufshcd_init_clk_gating(hba);
199ef13c 8410
eebcc196
VG		 8411 ufshcd_init_clk_scaling(hba);
8412
199ef13c
YG		 8413 /*
8414 * In order to avoid any spurious interrupt immediately after
8415 * registering UFS controller interrupt handler, clear any pending UFS
8416 * interrupt status and disable all the UFS interrupts.
8417 */
8418 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8419 REG_INTERRUPT_STATUS);
8420 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8421 /*
8422 * Make sure that UFS interrupts are disabled and any pending interrupt
8423 * status is cleared before registering UFS interrupt handler.
8424 */
8425 mb();
8426
7a3e97b0 8427 /* IRQ registration */
2953f850 8428 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8429 if (err) {
3b1d0580 8430 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8431 goto exit_gating;
57d104c1
SJ		 8432 } else {
8433 hba->is_irq_enabled = true;
7a3e97b0
SY		 8434 }
8435
3b1d0580 8436 err = scsi_add_host(host, hba->dev);
7a3e97b0 8437 if (err) {
3b1d0580 8438 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8439 goto exit_gating;
7a3e97b0
SY		 8440 }
8441
7252a360
BVA		 8442 hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
8443 if (IS_ERR(hba->cmd_queue)) {
8444 err = PTR_ERR(hba->cmd_queue);
8445 goto out_remove_scsi_host;
8446 }
8447
69a6c269
BVA		 8448 hba->tmf_tag_set = (struct blk_mq_tag_set) {
8449 .nr_hw_queues = 1,
8450 .queue_depth = hba->nutmrs,
8451 .ops = &ufshcd_tmf_ops,
8452 .flags = BLK_MQ_F_NO_SCHED,
8453 };
8454 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
8455 if (err < 0)
8456 goto free_cmd_queue;
8457 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
8458 if (IS_ERR(hba->tmf_queue)) {
8459 err = PTR_ERR(hba->tmf_queue);
8460 goto free_tmf_tag_set;
8461 }
8462
d8d9f793
BA		 8463 /* Reset the attached device */
8464 ufshcd_vops_device_reset(hba);
8465
6ccf44fe
SJ		 8466 /* Host controller enable */
8467 err = ufshcd_hba_enable(hba);
7a3e97b0 8468 if (err) {
6ccf44fe 8469 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 8470 ufshcd_print_host_regs(hba);
6ba65588 8471 ufshcd_print_host_state(hba);
69a6c269 8472 goto free_tmf_queue;
7a3e97b0 8473 }
6ccf44fe 8474
0c8f7586
SJ		 8475 /*
8476 * Set the default power management level for runtime and system PM.
8477 * Default power saving mode is to keep UFS link in Hibern8 state
8478 * and UFS device in sleep state.
8479 */
8480 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8481 UFS_SLEEP_PWR_MODE,
8482 UIC_LINK_HIBERN8_STATE);
8483 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8484 UFS_SLEEP_PWR_MODE,
8485 UIC_LINK_HIBERN8_STATE);
8486
ad448378 8487 /* Set the default auto-hiberate idle timer value to 150 ms */
f571b377 8488 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
ad448378
AH		 8489 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8490 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8491 }
8492
62694735
SRT		 8493 /* Hold auto suspend until async scan completes */
8494 pm_runtime_get_sync(dev);
38135535 8495 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 8496 /*
7caf489b
SJ		 8497 * We are assuming that device wasn't put in sleep/power-down
8498 * state exclusively during the boot stage before kernel.
8499 * This assumption helps avoid doing link startup twice during
8500 * ufshcd_probe_hba().
57d104c1 8501 */
7caf489b 8502 ufshcd_set_ufs_dev_active(hba);
57d104c1 8503
6ccf44fe 8504 async_schedule(ufshcd_async_scan, hba);
cbb6813e 8505 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 8506
7a3e97b0
SY		 8507 return 0;
8508
69a6c269
BVA		 8509free_tmf_queue:
8510 blk_cleanup_queue(hba->tmf_queue);
8511free_tmf_tag_set:
8512 blk_mq_free_tag_set(&hba->tmf_tag_set);
7252a360
BVA		 8513free_cmd_queue:
8514 blk_cleanup_queue(hba->cmd_queue);
3b1d0580
VH		 8515out_remove_scsi_host:
8516 scsi_remove_host(hba->host);
1ab27c9c 8517exit_gating:
eebcc196 8518 ufshcd_exit_clk_scaling(hba);
1ab27c9c 8519 ufshcd_exit_clk_gating(hba);
3b1d0580 8520out_disable:
57d104c1 8521 hba->is_irq_enabled = false;
aa497613 8522 ufshcd_hba_exit(hba);
3b1d0580
VH		 8523out_error:
8524 return err;
8525}
8526EXPORT_SYMBOL_GPL(ufshcd_init);
8527
3b1d0580
VH		 8528MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8529MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8530MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8531MODULE_LICENSE("GPL");
8532MODULE_VERSION(UFSHCD_DRIVER_VERSION);
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