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scsi: qla2xxx: Fix issue reported by static checker for qla2x00_els_dcmd2_sp_done()
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
ad448378 44#include <linux/bitfield.h>
e0eca63e 45#include "ufshcd.h"
c58ab7aa 46#include "ufs_quirks.h"
53b3d9c3 47#include "unipro.h"
cbb6813e 48#include "ufs-sysfs.h"
7a3e97b0 49
7ff5ab47
SJ		 50#define CREATE_TRACE_POINTS
51#include <trace/events/ufs.h>
52
dcea0bfb
GB		 53#define UFSHCD_REQ_SENSE_SIZE 18
54
2fbd009b
SJ		 55#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
56 UTP_TASK_REQ_COMPL |\
57 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 58/* UIC command timeout, unit: ms */
59#define UIC_CMD_TIMEOUT 500
2fbd009b 60
5a0b0cb9
SRT		 61/* NOP OUT retries waiting for NOP IN response */
62#define NOP_OUT_RETRIES 10
63/* Timeout after 30 msecs if NOP OUT hangs without response */
64#define NOP_OUT_TIMEOUT 30 /* msecs */
65
68078d5c 66/* Query request retries */
10fe5888 67#define QUERY_REQ_RETRIES 3
68078d5c 68/* Query request timeout */
10fe5888 69#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 70
e2933132
SRT		 71/* Task management command timeout */
72#define TM_CMD_TIMEOUT 100 /* msecs */
73
64238fbd
YG		 74/* maximum number of retries for a general UIC command */
75#define UFS_UIC_COMMAND_RETRIES 3
76
1d337ec2
SRT		 77/* maximum number of link-startup retries */
78#define DME_LINKSTARTUP_RETRIES 3
79
87d0b4a6
YG		 80/* Maximum retries for Hibern8 enter */
81#define UIC_HIBERN8_ENTER_RETRIES 3
82
1d337ec2
SRT		 83/* maximum number of reset retries before giving up */
84#define MAX_HOST_RESET_RETRIES 5
85
68078d5c
DR		 86/* Expose the flag value from utp_upiu_query.value */
87#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
88
7d568652
SJ		 89/* Interrupt aggregation default timeout, unit: 40us */
90#define INT_AGGR_DEF_TO 0x02
91
aa497613
SRT		 92#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
93 ({ \
94 int _ret; \
95 if (_on) \
96 _ret = ufshcd_enable_vreg(_dev, _vreg); \
97 else \
98 _ret = ufshcd_disable_vreg(_dev, _vreg); \
99 _ret; \
100 })
101
ba80917d
TW		 102#define ufshcd_hex_dump(prefix_str, buf, len) do { \
103 size_t __len = (len); \
104 print_hex_dump(KERN_ERR, prefix_str, \
105 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
106 16, 4, buf, __len, false); \
107} while (0)
108
109int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
110 const char *prefix)
111{
112 u8 *regs;
113
114 regs = kzalloc(len, GFP_KERNEL);
115 if (!regs)
116 return -ENOMEM;
117
118 memcpy_fromio(regs, hba->mmio_base + offset, len);
119 ufshcd_hex_dump(prefix, regs, len);
120 kfree(regs);
121
122 return 0;
123}
124EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 125
7a3e97b0
SY		 126enum {
127 UFSHCD_MAX_CHANNEL = 0,
128 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 129 UFSHCD_CMD_PER_LUN = 32,
130 UFSHCD_CAN_QUEUE = 32,
131};
132
133/* UFSHCD states */
134enum {
7a3e97b0
SY		 135 UFSHCD_STATE_RESET,
136 UFSHCD_STATE_ERROR,
3441da7d 137 UFSHCD_STATE_OPERATIONAL,
141f8165 138 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 139};
140
141/* UFSHCD error handling flags */
142enum {
143 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 144};
145
e8e7f271
SRT		 146/* UFSHCD UIC layer error flags */
147enum {
148 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 149 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
150 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
151 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
152 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
153 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 154};
155
3441da7d 156#define ufshcd_set_eh_in_progress(h) \
9c490d2d 157 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 158#define ufshcd_eh_in_progress(h) \
9c490d2d 159 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 160#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 161 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 162
57d104c1
SJ		 163#define ufshcd_set_ufs_dev_active(h) \
164 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
165#define ufshcd_set_ufs_dev_sleep(h) \
166 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
167#define ufshcd_set_ufs_dev_poweroff(h) \
168 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
169#define ufshcd_is_ufs_dev_active(h) \
170 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
171#define ufshcd_is_ufs_dev_sleep(h) \
172 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
173#define ufshcd_is_ufs_dev_poweroff(h) \
174 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
175
cbb6813e 176struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
57d104c1
SJ		 177 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
178 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
179 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
180 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
181 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
182 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
183};
184
185static inline enum ufs_dev_pwr_mode
186ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
187{
188 return ufs_pm_lvl_states[lvl].dev_state;
189}
190
191static inline enum uic_link_state
192ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
193{
194 return ufs_pm_lvl_states[lvl].link_state;
195}
196
0c8f7586
SJ		 197static inline enum ufs_pm_level
198ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
199 enum uic_link_state link_state)
200{
201 enum ufs_pm_level lvl;
202
203 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
204 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
205 (ufs_pm_lvl_states[lvl].link_state == link_state))
206 return lvl;
207 }
208
209 /* if no match found, return the level 0 */
210 return UFS_PM_LVL_0;
211}
212
56d4a186
SJ		 213static struct ufs_dev_fix ufs_fixups[] = {
214 /* UFS cards deviations table */
215 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
216 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
217 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
218 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
219 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
220 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
221 UFS_DEVICE_NO_FASTAUTO),
222 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
223 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
224 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
225 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
226 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
227 UFS_DEVICE_QUIRK_PA_TACTIVATE),
228 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
229 UFS_DEVICE_QUIRK_PA_TACTIVATE),
230 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
231 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
232 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
233
234 END_FIX
235};
236
3441da7d
SRT		 237static void ufshcd_tmc_handler(struct ufs_hba *hba);
238static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 239static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 240static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 241static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 242static void ufshcd_hba_exit(struct ufs_hba *hba);
243static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 244static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
245 bool skip_ref_clk);
246static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 247static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 248static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
249static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 250static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 251static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 252static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
253static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 254static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 255static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 256static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 257static int ufshcd_change_power_mode(struct ufs_hba *hba,
258 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 259static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
260{
261 return tag >= 0 && tag < hba->nutrs;
262}
57d104c1
SJ		 263
264static inline int ufshcd_enable_irq(struct ufs_hba *hba)
265{
266 int ret = 0;
267
268 if (!hba->is_irq_enabled) {
269 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
270 hba);
271 if (ret)
272 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
273 __func__, ret);
274 hba->is_irq_enabled = true;
275 }
276
277 return ret;
278}
279
280static inline void ufshcd_disable_irq(struct ufs_hba *hba)
281{
282 if (hba->is_irq_enabled) {
283 free_irq(hba->irq, hba);
284 hba->is_irq_enabled = false;
285 }
286}
3441da7d 287
38135535
SJ		 288static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
289{
290 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
291 scsi_unblock_requests(hba->host);
292}
293
294static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
295{
296 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
297 scsi_block_requests(hba->host);
298}
299
b573d484
YG		 300/* replace non-printable or non-ASCII characters with spaces */
301static inline void ufshcd_remove_non_printable(char *val)
302{
303 if (!val)
304 return;
305
306 if (*val < 0x20 || *val > 0x7e)
307 *val = ' ';
308}
309
6667e6d9
OS		 310static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
311 const char *str)
312{
313 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
314
315 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
316}
317
318static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
319 const char *str)
320{
321 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
322
323 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
324}
325
326static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
327 const char *str)
328{
329 struct utp_task_req_desc *descp;
330 struct utp_upiu_task_req *task_req;
331 int off = (int)tag - hba->nutrs;
332
333 descp = &hba->utmrdl_base_addr[off];
334 task_req = (struct utp_upiu_task_req *)descp->task_req_upiu;
335 trace_ufshcd_upiu(dev_name(hba->dev), str, &task_req->header,
336 &task_req->input_param1);
337}
338
1a07f2d9
LS		 339static void ufshcd_add_command_trace(struct ufs_hba *hba,
340 unsigned int tag, const char *str)
341{
342 sector_t lba = -1;
343 u8 opcode = 0;
344 u32 intr, doorbell;
345 struct ufshcd_lrb *lrbp;
346 int transfer_len = -1;
347
6667e6d9
OS		 348 /* trace UPIU also */
349 ufshcd_add_cmd_upiu_trace(hba, tag, str);
350
1a07f2d9
LS		 351 if (!trace_ufshcd_command_enabled())
352 return;
353
354 lrbp = &hba->lrb[tag];
355
356 if (lrbp->cmd) { /* data phase exists */
357 opcode = (u8)(*lrbp->cmd->cmnd);
358 if ((opcode == READ_10) || (opcode == WRITE_10)) {
359 /*
360 * Currently we only fully trace read(10) and write(10)
361 * commands
362 */
363 if (lrbp->cmd->request && lrbp->cmd->request->bio)
364 lba =
365 lrbp->cmd->request->bio->bi_iter.bi_sector;
366 transfer_len = be32_to_cpu(
367 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
368 }
369 }
370
371 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
372 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
373 trace_ufshcd_command(dev_name(hba->dev), str, tag,
374 doorbell, transfer_len, intr, lba, opcode);
375}
376
ff8e20c6
DR		 377static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
378{
379 struct ufs_clk_info *clki;
380 struct list_head *head = &hba->clk_list_head;
381
566ec9ad 382 if (list_empty(head))
ff8e20c6
DR		 383 return;
384
385 list_for_each_entry(clki, head, list) {
386 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
387 clki->max_freq)
388 dev_err(hba->dev, "clk: %s, rate: %u\n",
389 clki->name, clki->curr_freq);
390 }
391}
392
393static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
394 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
395{
396 int i;
397
398 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
399 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
400
401 if (err_hist->reg[p] == 0)
402 continue;
403 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
404 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
405 }
406}
407
66cc820f
DR		 408static void ufshcd_print_host_regs(struct ufs_hba *hba)
409{
ba80917d 410 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
66cc820f
DR		 411 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
412 hba->ufs_version, hba->capabilities);
413 dev_err(hba->dev,
414 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
415 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 416 dev_err(hba->dev,
417 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
418 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
419 hba->ufs_stats.hibern8_exit_cnt);
420
421 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
422 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
423 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
424 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
425 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
426
427 ufshcd_print_clk_freqs(hba);
428
429 if (hba->vops && hba->vops->dbg_register_dump)
430 hba->vops->dbg_register_dump(hba);
66cc820f
DR		 431}
432
433static
434void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
435{
436 struct ufshcd_lrb *lrbp;
7fabb77b 437 int prdt_length;
66cc820f
DR		 438 int tag;
439
440 for_each_set_bit(tag, &bitmap, hba->nutrs) {
441 lrbp = &hba->lrb[tag];
442
ff8e20c6
DR		 443 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
444 tag, ktime_to_us(lrbp->issue_time_stamp));
09017188
ZL		 445 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
446 tag, ktime_to_us(lrbp->compl_time_stamp));
ff8e20c6
DR		 447 dev_err(hba->dev,
448 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
449 tag, (u64)lrbp->utrd_dma_addr);
450
66cc820f
DR		 451 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
452 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 453 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
454 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 455 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
456 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 457 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
458 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 459 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
460 sizeof(struct utp_upiu_rsp));
66cc820f 461
7fabb77b
GB		 462 prdt_length = le16_to_cpu(
463 lrbp->utr_descriptor_ptr->prd_table_length);
464 dev_err(hba->dev,
465 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
466 tag, prdt_length,
467 (u64)lrbp->ucd_prdt_dma_addr);
468
469 if (pr_prdt)
66cc820f 470 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 471 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 472 }
473}
474
475static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
476{
477 struct utp_task_req_desc *tmrdp;
478 int tag;
479
480 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
481 tmrdp = &hba->utmrdl_base_addr[tag];
482 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
483 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
484 sizeof(struct request_desc_header));
485 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
486 tag);
487 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
488 sizeof(struct utp_upiu_req));
489 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
490 tag);
491 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
492 sizeof(struct utp_task_req_desc));
493 }
494}
495
6ba65588
GB		 496static void ufshcd_print_host_state(struct ufs_hba *hba)
497{
498 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
499 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
e002e651 500 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 501 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
502 hba->saved_err, hba->saved_uic_err);
503 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
504 hba->curr_dev_pwr_mode, hba->uic_link_state);
505 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
506 hba->pm_op_in_progress, hba->is_sys_suspended);
507 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
508 hba->auto_bkops_enabled, hba->host->host_self_blocked);
509 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
510 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
511 hba->eh_flags, hba->req_abort_count);
512 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
513 hba->capabilities, hba->caps);
514 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
515 hba->dev_quirks);
516}
517
ff8e20c6
DR		 518/**
519 * ufshcd_print_pwr_info - print power params as saved in hba
520 * power info
521 * @hba: per-adapter instance
522 */
523static void ufshcd_print_pwr_info(struct ufs_hba *hba)
524{
525 static const char * const names[] = {
526 "INVALID MODE",
527 "FAST MODE",
528 "SLOW_MODE",
529 "INVALID MODE",
530 "FASTAUTO_MODE",
531 "SLOWAUTO_MODE",
532 "INVALID MODE",
533 };
534
535 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
536 __func__,
537 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
538 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
539 names[hba->pwr_info.pwr_rx],
540 names[hba->pwr_info.pwr_tx],
541 hba->pwr_info.hs_rate);
542}
543
5a0b0cb9
SRT		 544/*
545 * ufshcd_wait_for_register - wait for register value to change
546 * @hba - per-adapter interface
547 * @reg - mmio register offset
548 * @mask - mask to apply to read register value
549 * @val - wait condition
550 * @interval_us - polling interval in microsecs
551 * @timeout_ms - timeout in millisecs
596585a2 552 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 553 *
554 * Returns -ETIMEDOUT on error, zero on success
555 */
596585a2
YG		 556int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
557 u32 val, unsigned long interval_us,
558 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 559{
560 int err = 0;
561 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
562
563 /* ignore bits that we don't intend to wait on */
564 val = val & mask;
565
566 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 567 if (can_sleep)
568 usleep_range(interval_us, interval_us + 50);
569 else
570 udelay(interval_us);
5a0b0cb9
SRT		 571 if (time_after(jiffies, timeout)) {
572 if ((ufshcd_readl(hba, reg) & mask) != val)
573 err = -ETIMEDOUT;
574 break;
575 }
576 }
577
578 return err;
579}
580
2fbd009b
SJ		 581/**
582 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 583 * @hba: Pointer to adapter instance
2fbd009b
SJ		 584 *
585 * Returns interrupt bit mask per version
586 */
587static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
588{
c01848c6
YG		 589 u32 intr_mask = 0;
590
591 switch (hba->ufs_version) {
592 case UFSHCI_VERSION_10:
593 intr_mask = INTERRUPT_MASK_ALL_VER_10;
594 break;
c01848c6
YG		 595 case UFSHCI_VERSION_11:
596 case UFSHCI_VERSION_20:
597 intr_mask = INTERRUPT_MASK_ALL_VER_11;
598 break;
c01848c6
YG		 599 case UFSHCI_VERSION_21:
600 default:
601 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 602 break;
c01848c6
YG		 603 }
604
605 return intr_mask;
2fbd009b
SJ		 606}
607
7a3e97b0
SY		 608/**
609 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 610 * @hba: Pointer to adapter instance
7a3e97b0
SY		 611 *
612 * Returns UFSHCI version supported by the controller
613 */
614static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
615{
0263bcd0
YG		 616 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
617 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 618
b873a275 619 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 620}
621
622/**
623 * ufshcd_is_device_present - Check if any device connected to
624 * the host controller
5c0c28a8 625 * @hba: pointer to adapter instance
7a3e97b0 626 *
c9e6010b 627 * Returns true if device present, false if no device detected
7a3e97b0 628 */
c9e6010b 629static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 630{
5c0c28a8 631 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 632 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 633}
634
635/**
636 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 637 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 638 *
639 * This function is used to get the OCS field from UTRD
640 * Returns the OCS field in the UTRD
641 */
642static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
643{
e8c8e82a 644 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 645}
646
647/**
648 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
649 * @task_req_descp: pointer to utp_task_req_desc structure
650 *
651 * This function is used to get the OCS field from UTMRD
652 * Returns the OCS field in the UTMRD
653 */
654static inline int
655ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
656{
e8c8e82a 657 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 658}
659
660/**
661 * ufshcd_get_tm_free_slot - get a free slot for task management request
662 * @hba: per adapter instance
e2933132 663 * @free_slot: pointer to variable with available slot value
7a3e97b0 664 *
e2933132
SRT		 665 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
666 * Returns 0 if free slot is not available, else return 1 with tag value
667 * in @free_slot.
7a3e97b0 668 */
e2933132 669static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 670{
e2933132
SRT		 671 int tag;
672 bool ret = false;
673
674 if (!free_slot)
675 goto out;
676
677 do {
678 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
679 if (tag >= hba->nutmrs)
680 goto out;
681 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
682
683 *free_slot = tag;
684 ret = true;
685out:
686 return ret;
687}
688
689static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
690{
691 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 692}
693
694/**
695 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
696 * @hba: per adapter instance
697 * @pos: position of the bit to be cleared
698 */
699static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
700{
1399c5b0
AA		 701 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
702 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
703 else
704 ufshcd_writel(hba, ~(1 << pos),
705 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
706}
707
708/**
709 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
710 * @hba: per adapter instance
711 * @pos: position of the bit to be cleared
712 */
713static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
714{
715 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
716 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
717 else
718 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 719}
720
a48353f6
YG		 721/**
722 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
723 * @hba: per adapter instance
724 * @tag: position of the bit to be cleared
725 */
726static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
727{
728 __clear_bit(tag, &hba->outstanding_reqs);
729}
730
7a3e97b0
SY		 731/**
732 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
733 * @reg: Register value of host controller status
734 *
735 * Returns integer, 0 on Success and positive value if failed
736 */
737static inline int ufshcd_get_lists_status(u32 reg)
738{
6cf16115 739 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 740}
741
742/**
743 * ufshcd_get_uic_cmd_result - Get the UIC command result
744 * @hba: Pointer to adapter instance
745 *
746 * This function gets the result of UIC command completion
747 * Returns 0 on success, non zero value on error
748 */
749static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
750{
b873a275 751 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 752 MASK_UIC_COMMAND_RESULT;
753}
754
12b4fdb4
SJ		 755/**
756 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
757 * @hba: Pointer to adapter instance
758 *
759 * This function gets UIC command argument3
760 * Returns 0 on success, non zero value on error
761 */
762static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
763{
764 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
765}
766
7a3e97b0 767/**
5a0b0cb9 768 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 769 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 770 */
771static inline int
5a0b0cb9 772ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 773{
5a0b0cb9 774 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 775}
776
777/**
778 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
779 * @ucd_rsp_ptr: pointer to response UPIU
780 *
781 * This function gets the response status and scsi_status from response UPIU
782 * Returns the response result code.
783 */
784static inline int
785ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
786{
787 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
788}
789
1c2623c5
SJ		 790/*
791 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
792 * from response UPIU
793 * @ucd_rsp_ptr: pointer to response UPIU
794 *
795 * Return the data segment length.
796 */
797static inline unsigned int
798ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
799{
800 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
801 MASK_RSP_UPIU_DATA_SEG_LEN;
802}
803
66ec6d59
SRT		 804/**
805 * ufshcd_is_exception_event - Check if the device raised an exception event
806 * @ucd_rsp_ptr: pointer to response UPIU
807 *
808 * The function checks if the device raised an exception event indicated in
809 * the Device Information field of response UPIU.
810 *
811 * Returns true if exception is raised, false otherwise.
812 */
813static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
814{
815 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
816 MASK_RSP_EXCEPTION_EVENT ? true : false;
817}
818
7a3e97b0 819/**
7d568652 820 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 821 * @hba: per adapter instance
7a3e97b0
SY		 822 */
823static inline void
7d568652 824ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 825{
7d568652
SJ		 826 ufshcd_writel(hba, INT_AGGR_ENABLE |
827 INT_AGGR_COUNTER_AND_TIMER_RESET,
828 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
829}
830
831/**
832 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
833 * @hba: per adapter instance
834 * @cnt: Interrupt aggregation counter threshold
835 * @tmout: Interrupt aggregation timeout value
836 */
837static inline void
838ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
839{
840 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
841 INT_AGGR_COUNTER_THLD_VAL(cnt) |
842 INT_AGGR_TIMEOUT_VAL(tmout),
843 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 844}
845
b852190e
YG		 846/**
847 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
848 * @hba: per adapter instance
849 */
850static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
851{
852 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
853}
854
7a3e97b0
SY		 855/**
856 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
857 * When run-stop registers are set to 1, it indicates the
858 * host controller that it can process the requests
859 * @hba: per adapter instance
860 */
861static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
862{
b873a275
SJ		 863 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
864 REG_UTP_TASK_REQ_LIST_RUN_STOP);
865 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
866 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 867}
868
7a3e97b0
SY		 869/**
870 * ufshcd_hba_start - Start controller initialization sequence
871 * @hba: per adapter instance
872 */
873static inline void ufshcd_hba_start(struct ufs_hba *hba)
874{
b873a275 875 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 876}
877
878/**
879 * ufshcd_is_hba_active - Get controller state
880 * @hba: per adapter instance
881 *
c9e6010b 882 * Returns false if controller is active, true otherwise
7a3e97b0 883 */
c9e6010b 884static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 885{
4a8eec2b
TK		 886 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
887 ? false : true;
7a3e97b0
SY		 888}
889
37113106
YG		 890u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
891{
892 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
893 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
894 (hba->ufs_version == UFSHCI_VERSION_11))
895 return UFS_UNIPRO_VER_1_41;
896 else
897 return UFS_UNIPRO_VER_1_6;
898}
899EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
900
901static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
902{
903 /*
904 * If both host and device support UniPro ver1.6 or later, PA layer
905 * parameters tuning happens during link startup itself.
906 *
907 * We can manually tune PA layer parameters if either host or device
908 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
909 * logic simple, we will only do manual tuning if local unipro version
910 * doesn't support ver1.6 or later.
911 */
912 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
913 return true;
914 else
915 return false;
916}
917
a3cd5ec5
SJ		 918static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
919{
920 int ret = 0;
921 struct ufs_clk_info *clki;
922 struct list_head *head = &hba->clk_list_head;
923 ktime_t start = ktime_get();
924 bool clk_state_changed = false;
925
566ec9ad 926 if (list_empty(head))
a3cd5ec5
SJ		 927 goto out;
928
929 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
930 if (ret)
931 return ret;
932
933 list_for_each_entry(clki, head, list) {
934 if (!IS_ERR_OR_NULL(clki->clk)) {
935 if (scale_up && clki->max_freq) {
936 if (clki->curr_freq == clki->max_freq)
937 continue;
938
939 clk_state_changed = true;
940 ret = clk_set_rate(clki->clk, clki->max_freq);
941 if (ret) {
942 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
943 __func__, clki->name,
944 clki->max_freq, ret);
945 break;
946 }
947 trace_ufshcd_clk_scaling(dev_name(hba->dev),
948 "scaled up", clki->name,
949 clki->curr_freq,
950 clki->max_freq);
951
952 clki->curr_freq = clki->max_freq;
953
954 } else if (!scale_up && clki->min_freq) {
955 if (clki->curr_freq == clki->min_freq)
956 continue;
957
958 clk_state_changed = true;
959 ret = clk_set_rate(clki->clk, clki->min_freq);
960 if (ret) {
961 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
962 __func__, clki->name,
963 clki->min_freq, ret);
964 break;
965 }
966 trace_ufshcd_clk_scaling(dev_name(hba->dev),
967 "scaled down", clki->name,
968 clki->curr_freq,
969 clki->min_freq);
970 clki->curr_freq = clki->min_freq;
971 }
972 }
973 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
974 clki->name, clk_get_rate(clki->clk));
975 }
976
977 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
978
979out:
980 if (clk_state_changed)
981 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
982 (scale_up ? "up" : "down"),
983 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
984 return ret;
985}
986
987/**
988 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
989 * @hba: per adapter instance
990 * @scale_up: True if scaling up and false if scaling down
991 *
992 * Returns true if scaling is required, false otherwise.
993 */
994static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
995 bool scale_up)
996{
997 struct ufs_clk_info *clki;
998 struct list_head *head = &hba->clk_list_head;
999
566ec9ad 1000 if (list_empty(head))
a3cd5ec5
SJ		 1001 return false;
1002
1003 list_for_each_entry(clki, head, list) {
1004 if (!IS_ERR_OR_NULL(clki->clk)) {
1005 if (scale_up && clki->max_freq) {
1006 if (clki->curr_freq == clki->max_freq)
1007 continue;
1008 return true;
1009 } else if (!scale_up && clki->min_freq) {
1010 if (clki->curr_freq == clki->min_freq)
1011 continue;
1012 return true;
1013 }
1014 }
1015 }
1016
1017 return false;
1018}
1019
1020static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1021 u64 wait_timeout_us)
1022{
1023 unsigned long flags;
1024 int ret = 0;
1025 u32 tm_doorbell;
1026 u32 tr_doorbell;
1027 bool timeout = false, do_last_check = false;
1028 ktime_t start;
1029
1030 ufshcd_hold(hba, false);
1031 spin_lock_irqsave(hba->host->host_lock, flags);
1032 /*
1033 * Wait for all the outstanding tasks/transfer requests.
1034 * Verify by checking the doorbell registers are clear.
1035 */
1036 start = ktime_get();
1037 do {
1038 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1039 ret = -EBUSY;
1040 goto out;
1041 }
1042
1043 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1044 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1045 if (!tm_doorbell && !tr_doorbell) {
1046 timeout = false;
1047 break;
1048 } else if (do_last_check) {
1049 break;
1050 }
1051
1052 spin_unlock_irqrestore(hba->host->host_lock, flags);
1053 schedule();
1054 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1055 wait_timeout_us) {
1056 timeout = true;
1057 /*
1058 * We might have scheduled out for long time so make
1059 * sure to check if doorbells are cleared by this time
1060 * or not.
1061 */
1062 do_last_check = true;
1063 }
1064 spin_lock_irqsave(hba->host->host_lock, flags);
1065 } while (tm_doorbell || tr_doorbell);
1066
1067 if (timeout) {
1068 dev_err(hba->dev,
1069 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1070 __func__, tm_doorbell, tr_doorbell);
1071 ret = -EBUSY;
1072 }
1073out:
1074 spin_unlock_irqrestore(hba->host->host_lock, flags);
1075 ufshcd_release(hba);
1076 return ret;
1077}
1078
1079/**
1080 * ufshcd_scale_gear - scale up/down UFS gear
1081 * @hba: per adapter instance
1082 * @scale_up: True for scaling up gear and false for scaling down
1083 *
1084 * Returns 0 for success,
1085 * Returns -EBUSY if scaling can't happen at this time
1086 * Returns non-zero for any other errors
1087 */
1088static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1089{
1090 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1091 int ret = 0;
1092 struct ufs_pa_layer_attr new_pwr_info;
1093
1094 if (scale_up) {
1095 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1096 sizeof(struct ufs_pa_layer_attr));
1097 } else {
1098 memcpy(&new_pwr_info, &hba->pwr_info,
1099 sizeof(struct ufs_pa_layer_attr));
1100
1101 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1102 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1103 /* save the current power mode */
1104 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1105 &hba->pwr_info,
1106 sizeof(struct ufs_pa_layer_attr));
1107
1108 /* scale down gear */
1109 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1110 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1111 }
1112 }
1113
1114 /* check if the power mode needs to be changed or not? */
1115 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1116
1117 if (ret)
1118 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1119 __func__, ret,
1120 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1121 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1122
1123 return ret;
1124}
1125
1126static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1127{
1128 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1129 int ret = 0;
1130 /*
1131 * make sure that there are no outstanding requests when
1132 * clock scaling is in progress
1133 */
38135535 1134 ufshcd_scsi_block_requests(hba);
a3cd5ec5
SJ		 1135 down_write(&hba->clk_scaling_lock);
1136 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1137 ret = -EBUSY;
1138 up_write(&hba->clk_scaling_lock);
38135535 1139 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5
SJ		 1140 }
1141
1142 return ret;
1143}
1144
1145static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1146{
1147 up_write(&hba->clk_scaling_lock);
38135535 1148 ufshcd_scsi_unblock_requests(hba);
a3cd5ec5
SJ		 1149}
1150
1151/**
1152 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1153 * @hba: per adapter instance
1154 * @scale_up: True for scaling up and false for scalin down
1155 *
1156 * Returns 0 for success,
1157 * Returns -EBUSY if scaling can't happen at this time
1158 * Returns non-zero for any other errors
1159 */
1160static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1161{
1162 int ret = 0;
1163
401f1e44
SJ		 1164 /* let's not get into low power until clock scaling is completed */
1165 ufshcd_hold(hba, false);
1166
a3cd5ec5
SJ		 1167 ret = ufshcd_clock_scaling_prepare(hba);
1168 if (ret)
1169 return ret;
1170
1171 /* scale down the gear before scaling down clocks */
1172 if (!scale_up) {
1173 ret = ufshcd_scale_gear(hba, false);
1174 if (ret)
1175 goto out;
1176 }
1177
1178 ret = ufshcd_scale_clks(hba, scale_up);
1179 if (ret) {
1180 if (!scale_up)
1181 ufshcd_scale_gear(hba, true);
1182 goto out;
1183 }
1184
1185 /* scale up the gear after scaling up clocks */
1186 if (scale_up) {
1187 ret = ufshcd_scale_gear(hba, true);
1188 if (ret) {
1189 ufshcd_scale_clks(hba, false);
1190 goto out;
1191 }
1192 }
1193
1194 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1195
1196out:
1197 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1198 ufshcd_release(hba);
a3cd5ec5
SJ		 1199 return ret;
1200}
1201
401f1e44
SJ		 1202static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1203{
1204 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1205 clk_scaling.suspend_work);
1206 unsigned long irq_flags;
1207
1208 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1209 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1210 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1211 return;
1212 }
1213 hba->clk_scaling.is_suspended = true;
1214 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1215
1216 __ufshcd_suspend_clkscaling(hba);
1217}
1218
1219static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1220{
1221 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1222 clk_scaling.resume_work);
1223 unsigned long irq_flags;
1224
1225 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1226 if (!hba->clk_scaling.is_suspended) {
1227 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1228 return;
1229 }
1230 hba->clk_scaling.is_suspended = false;
1231 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1232
1233 devfreq_resume_device(hba->devfreq);
1234}
1235
a3cd5ec5
SJ		 1236static int ufshcd_devfreq_target(struct device *dev,
1237 unsigned long *freq, u32 flags)
1238{
1239 int ret = 0;
1240 struct ufs_hba *hba = dev_get_drvdata(dev);
1241 ktime_t start;
401f1e44 1242 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1243 struct list_head *clk_list = &hba->clk_list_head;
1244 struct ufs_clk_info *clki;
a3cd5ec5
SJ		 1245 unsigned long irq_flags;
1246
1247 if (!ufshcd_is_clkscaling_supported(hba))
1248 return -EINVAL;
1249
a3cd5ec5
SJ		 1250 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1251 if (ufshcd_eh_in_progress(hba)) {
1252 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1253 return 0;
1254 }
1255
401f1e44
SJ		 1256 if (!hba->clk_scaling.active_reqs)
1257 sched_clk_scaling_suspend_work = true;
1258
092b4558
BA		 1259 if (list_empty(clk_list)) {
1260 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1261 goto out;
1262 }
1263
1264 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1265 scale_up = (*freq == clki->max_freq) ? true : false;
401f1e44
SJ		 1266 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1267 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1268 ret = 0;
1269 goto out; /* no state change required */
a3cd5ec5
SJ		 1270 }
1271 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1272
1273 start = ktime_get();
a3cd5ec5
SJ		 1274 ret = ufshcd_devfreq_scale(hba, scale_up);
1275
a3cd5ec5
SJ		 1276 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1277 (scale_up ? "up" : "down"),
1278 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1279
401f1e44
SJ		 1280out:
1281 if (sched_clk_scaling_suspend_work)
1282 queue_work(hba->clk_scaling.workq,
1283 &hba->clk_scaling.suspend_work);
1284
a3cd5ec5
SJ		 1285 return ret;
1286}
1287
1288
1289static int ufshcd_devfreq_get_dev_status(struct device *dev,
1290 struct devfreq_dev_status *stat)
1291{
1292 struct ufs_hba *hba = dev_get_drvdata(dev);
1293 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1294 unsigned long flags;
1295
1296 if (!ufshcd_is_clkscaling_supported(hba))
1297 return -EINVAL;
1298
1299 memset(stat, 0, sizeof(*stat));
1300
1301 spin_lock_irqsave(hba->host->host_lock, flags);
1302 if (!scaling->window_start_t)
1303 goto start_window;
1304
1305 if (scaling->is_busy_started)
1306 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1307 scaling->busy_start_t));
1308
1309 stat->total_time = jiffies_to_usecs((long)jiffies -
1310 (long)scaling->window_start_t);
1311 stat->busy_time = scaling->tot_busy_t;
1312start_window:
1313 scaling->window_start_t = jiffies;
1314 scaling->tot_busy_t = 0;
1315
1316 if (hba->outstanding_reqs) {
1317 scaling->busy_start_t = ktime_get();
1318 scaling->is_busy_started = true;
1319 } else {
1320 scaling->busy_start_t = 0;
1321 scaling->is_busy_started = false;
1322 }
1323 spin_unlock_irqrestore(hba->host->host_lock, flags);
1324 return 0;
1325}
1326
1327static struct devfreq_dev_profile ufs_devfreq_profile = {
1328 .polling_ms = 100,
1329 .target = ufshcd_devfreq_target,
1330 .get_dev_status = ufshcd_devfreq_get_dev_status,
1331};
1332
deac444f
BA		 1333static int ufshcd_devfreq_init(struct ufs_hba *hba)
1334{
092b4558
BA		 1335 struct list_head *clk_list = &hba->clk_list_head;
1336 struct ufs_clk_info *clki;
deac444f
BA		 1337 struct devfreq *devfreq;
1338 int ret;
1339
092b4558
BA		 1340 /* Skip devfreq if we don't have any clocks in the list */
1341 if (list_empty(clk_list))
1342 return 0;
1343
1344 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1345 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1346 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1347
1348 devfreq = devfreq_add_device(hba->dev,
deac444f
BA		 1349 &ufs_devfreq_profile,
1350 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1351 NULL);
1352 if (IS_ERR(devfreq)) {
1353 ret = PTR_ERR(devfreq);
1354 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1355
1356 dev_pm_opp_remove(hba->dev, clki->min_freq);
1357 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1358 return ret;
1359 }
1360
1361 hba->devfreq = devfreq;
1362
1363 return 0;
1364}
1365
092b4558
BA		 1366static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1367{
1368 struct list_head *clk_list = &hba->clk_list_head;
1369 struct ufs_clk_info *clki;
1370
1371 if (!hba->devfreq)
1372 return;
1373
1374 devfreq_remove_device(hba->devfreq);
1375 hba->devfreq = NULL;
1376
1377 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1378 dev_pm_opp_remove(hba->dev, clki->min_freq);
1379 dev_pm_opp_remove(hba->dev, clki->max_freq);
1380}
1381
401f1e44
SJ		 1382static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1383{
1384 unsigned long flags;
1385
1386 devfreq_suspend_device(hba->devfreq);
1387 spin_lock_irqsave(hba->host->host_lock, flags);
1388 hba->clk_scaling.window_start_t = 0;
1389 spin_unlock_irqrestore(hba->host->host_lock, flags);
1390}
a3cd5ec5 1391
a508253d
GB		 1392static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1393{
401f1e44
SJ		 1394 unsigned long flags;
1395 bool suspend = false;
1396
fcb0c4b0
ST		 1397 if (!ufshcd_is_clkscaling_supported(hba))
1398 return;
1399
401f1e44
SJ		 1400 spin_lock_irqsave(hba->host->host_lock, flags);
1401 if (!hba->clk_scaling.is_suspended) {
1402 suspend = true;
1403 hba->clk_scaling.is_suspended = true;
1404 }
1405 spin_unlock_irqrestore(hba->host->host_lock, flags);
1406
1407 if (suspend)
1408 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1409}
1410
1411static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1412{
401f1e44
SJ		 1413 unsigned long flags;
1414 bool resume = false;
1415
1416 if (!ufshcd_is_clkscaling_supported(hba))
1417 return;
1418
1419 spin_lock_irqsave(hba->host->host_lock, flags);
1420 if (hba->clk_scaling.is_suspended) {
1421 resume = true;
1422 hba->clk_scaling.is_suspended = false;
1423 }
1424 spin_unlock_irqrestore(hba->host->host_lock, flags);
1425
1426 if (resume)
1427 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1428}
1429
1430static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1431 struct device_attribute *attr, char *buf)
1432{
1433 struct ufs_hba *hba = dev_get_drvdata(dev);
1434
1435 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1436}
1437
1438static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1439 struct device_attribute *attr, const char *buf, size_t count)
1440{
1441 struct ufs_hba *hba = dev_get_drvdata(dev);
1442 u32 value;
1443 int err;
1444
1445 if (kstrtou32(buf, 0, &value))
1446 return -EINVAL;
1447
1448 value = !!value;
1449 if (value == hba->clk_scaling.is_allowed)
1450 goto out;
1451
1452 pm_runtime_get_sync(hba->dev);
1453 ufshcd_hold(hba, false);
1454
401f1e44
SJ		 1455 cancel_work_sync(&hba->clk_scaling.suspend_work);
1456 cancel_work_sync(&hba->clk_scaling.resume_work);
1457
1458 hba->clk_scaling.is_allowed = value;
1459
fcb0c4b0
ST		 1460 if (value) {
1461 ufshcd_resume_clkscaling(hba);
1462 } else {
1463 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1464 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1465 if (err)
1466 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1467 __func__, err);
1468 }
fcb0c4b0
ST		 1469
1470 ufshcd_release(hba);
1471 pm_runtime_put_sync(hba->dev);
1472out:
1473 return count;
a508253d
GB		 1474}
1475
a3cd5ec5
SJ		 1476static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1477{
1478 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1479 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1480 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1481 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1482 hba->clk_scaling.enable_attr.attr.mode = 0644;
1483 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1484 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1485}
1486
1ab27c9c
ST		 1487static void ufshcd_ungate_work(struct work_struct *work)
1488{
1489 int ret;
1490 unsigned long flags;
1491 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1492 clk_gating.ungate_work);
1493
1494 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1495
1496 spin_lock_irqsave(hba->host->host_lock, flags);
1497 if (hba->clk_gating.state == CLKS_ON) {
1498 spin_unlock_irqrestore(hba->host->host_lock, flags);
1499 goto unblock_reqs;
1500 }
1501
1502 spin_unlock_irqrestore(hba->host->host_lock, flags);
1503 ufshcd_setup_clocks(hba, true);
1504
1505 /* Exit from hibern8 */
1506 if (ufshcd_can_hibern8_during_gating(hba)) {
1507 /* Prevent gating in this path */
1508 hba->clk_gating.is_suspended = true;
1509 if (ufshcd_is_link_hibern8(hba)) {
1510 ret = ufshcd_uic_hibern8_exit(hba);
1511 if (ret)
1512 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1513 __func__, ret);
1514 else
1515 ufshcd_set_link_active(hba);
1516 }
1517 hba->clk_gating.is_suspended = false;
1518 }
1519unblock_reqs:
38135535 1520 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1521}
1522
1523/**
1524 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1525 * Also, exit from hibern8 mode and set the link as active.
1526 * @hba: per adapter instance
1527 * @async: This indicates whether caller should ungate clocks asynchronously.
1528 */
1529int ufshcd_hold(struct ufs_hba *hba, bool async)
1530{
1531 int rc = 0;
1532 unsigned long flags;
1533
1534 if (!ufshcd_is_clkgating_allowed(hba))
1535 goto out;
1ab27c9c
ST		 1536 spin_lock_irqsave(hba->host->host_lock, flags);
1537 hba->clk_gating.active_reqs++;
1538
53c12d0e
YG		 1539 if (ufshcd_eh_in_progress(hba)) {
1540 spin_unlock_irqrestore(hba->host->host_lock, flags);
1541 return 0;
1542 }
1543
856b3483 1544start:
1ab27c9c
ST		 1545 switch (hba->clk_gating.state) {
1546 case CLKS_ON:
f2a785ac
VG		 1547 /*
1548 * Wait for the ungate work to complete if in progress.
1549 * Though the clocks may be in ON state, the link could
1550 * still be in hibner8 state if hibern8 is allowed
1551 * during clock gating.
1552 * Make sure we exit hibern8 state also in addition to
1553 * clocks being ON.
1554 */
1555 if (ufshcd_can_hibern8_during_gating(hba) &&
1556 ufshcd_is_link_hibern8(hba)) {
1557 spin_unlock_irqrestore(hba->host->host_lock, flags);
1558 flush_work(&hba->clk_gating.ungate_work);
1559 spin_lock_irqsave(hba->host->host_lock, flags);
1560 goto start;
1561 }
1ab27c9c
ST		 1562 break;
1563 case REQ_CLKS_OFF:
1564 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1565 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1566 trace_ufshcd_clk_gating(dev_name(hba->dev),
1567 hba->clk_gating.state);
1ab27c9c
ST		 1568 break;
1569 }
1570 /*
9c490d2d 1571 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1572 * currently running. Hence, fall through to cancel gating
1573 * work and to enable clocks.
1574 */
1575 case CLKS_OFF:
38135535 1576 ufshcd_scsi_block_requests(hba);
1ab27c9c 1577 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47
SJ		 1578 trace_ufshcd_clk_gating(dev_name(hba->dev),
1579 hba->clk_gating.state);
10e5e375
VV		 1580 queue_work(hba->clk_gating.clk_gating_workq,
1581 &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1582 /*
1583 * fall through to check if we should wait for this
1584 * work to be done or not.
1585 */
1586 case REQ_CLKS_ON:
1587 if (async) {
1588 rc = -EAGAIN;
1589 hba->clk_gating.active_reqs--;
1590 break;
1591 }
1592
1593 spin_unlock_irqrestore(hba->host->host_lock, flags);
1594 flush_work(&hba->clk_gating.ungate_work);
1595 /* Make sure state is CLKS_ON before returning */
856b3483 1596 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1597 goto start;
1598 default:
1599 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1600 __func__, hba->clk_gating.state);
1601 break;
1602 }
1603 spin_unlock_irqrestore(hba->host->host_lock, flags);
1604out:
1605 return rc;
1606}
6e3fd44d 1607EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1608
1609static void ufshcd_gate_work(struct work_struct *work)
1610{
1611 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1612 clk_gating.gate_work.work);
1613 unsigned long flags;
1614
1615 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1616 /*
1617 * In case you are here to cancel this work the gating state
1618 * would be marked as REQ_CLKS_ON. In this case save time by
1619 * skipping the gating work and exit after changing the clock
1620 * state to CLKS_ON.
1621 */
1622 if (hba->clk_gating.is_suspended ||
1623 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1624 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1625 trace_ufshcd_clk_gating(dev_name(hba->dev),
1626 hba->clk_gating.state);
1ab27c9c
ST		 1627 goto rel_lock;
1628 }
1629
1630 if (hba->clk_gating.active_reqs
1631 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1632 || hba->lrb_in_use || hba->outstanding_tasks
1633 || hba->active_uic_cmd || hba->uic_async_done)
1634 goto rel_lock;
1635
1636 spin_unlock_irqrestore(hba->host->host_lock, flags);
1637
1638 /* put the link into hibern8 mode before turning off clocks */
1639 if (ufshcd_can_hibern8_during_gating(hba)) {
1640 if (ufshcd_uic_hibern8_enter(hba)) {
1641 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1642 trace_ufshcd_clk_gating(dev_name(hba->dev),
1643 hba->clk_gating.state);
1ab27c9c
ST		 1644 goto out;
1645 }
1646 ufshcd_set_link_hibern8(hba);
1647 }
1648
1649 if (!ufshcd_is_link_active(hba))
1650 ufshcd_setup_clocks(hba, false);
1651 else
1652 /* If link is active, device ref_clk can't be switched off */
1653 __ufshcd_setup_clocks(hba, false, true);
1654
1655 /*
1656 * In case you are here to cancel this work the gating state
1657 * would be marked as REQ_CLKS_ON. In this case keep the state
1658 * as REQ_CLKS_ON which would anyway imply that clocks are off
1659 * and a request to turn them on is pending. By doing this way,
1660 * we keep the state machine in tact and this would ultimately
1661 * prevent from doing cancel work multiple times when there are
1662 * new requests arriving before the current cancel work is done.
1663 */
1664 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1665 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1666 hba->clk_gating.state = CLKS_OFF;
7ff5ab47
SJ		 1667 trace_ufshcd_clk_gating(dev_name(hba->dev),
1668 hba->clk_gating.state);
1669 }
1ab27c9c
ST		 1670rel_lock:
1671 spin_unlock_irqrestore(hba->host->host_lock, flags);
1672out:
1673 return;
1674}
1675
1676/* host lock must be held before calling this variant */
1677static void __ufshcd_release(struct ufs_hba *hba)
1678{
1679 if (!ufshcd_is_clkgating_allowed(hba))
1680 return;
1681
1682 hba->clk_gating.active_reqs--;
1683
1684 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1685 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1686 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 1687 || hba->active_uic_cmd || hba->uic_async_done
1688 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1689 return;
1690
1691 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1692 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1ab27c9c
ST		 1693 schedule_delayed_work(&hba->clk_gating.gate_work,
1694 msecs_to_jiffies(hba->clk_gating.delay_ms));
1695}
1696
1697void ufshcd_release(struct ufs_hba *hba)
1698{
1699 unsigned long flags;
1700
1701 spin_lock_irqsave(hba->host->host_lock, flags);
1702 __ufshcd_release(hba);
1703 spin_unlock_irqrestore(hba->host->host_lock, flags);
1704}
6e3fd44d 1705EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1706
1707static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1708 struct device_attribute *attr, char *buf)
1709{
1710 struct ufs_hba *hba = dev_get_drvdata(dev);
1711
1712 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1713}
1714
1715static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1716 struct device_attribute *attr, const char *buf, size_t count)
1717{
1718 struct ufs_hba *hba = dev_get_drvdata(dev);
1719 unsigned long flags, value;
1720
1721 if (kstrtoul(buf, 0, &value))
1722 return -EINVAL;
1723
1724 spin_lock_irqsave(hba->host->host_lock, flags);
1725 hba->clk_gating.delay_ms = value;
1726 spin_unlock_irqrestore(hba->host->host_lock, flags);
1727 return count;
1728}
1729
b427411a
ST		 1730static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1731 struct device_attribute *attr, char *buf)
1732{
1733 struct ufs_hba *hba = dev_get_drvdata(dev);
1734
1735 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1736}
1737
1738static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1739 struct device_attribute *attr, const char *buf, size_t count)
1740{
1741 struct ufs_hba *hba = dev_get_drvdata(dev);
1742 unsigned long flags;
1743 u32 value;
1744
1745 if (kstrtou32(buf, 0, &value))
1746 return -EINVAL;
1747
1748 value = !!value;
1749 if (value == hba->clk_gating.is_enabled)
1750 goto out;
1751
1752 if (value) {
1753 ufshcd_release(hba);
1754 } else {
1755 spin_lock_irqsave(hba->host->host_lock, flags);
1756 hba->clk_gating.active_reqs++;
1757 spin_unlock_irqrestore(hba->host->host_lock, flags);
1758 }
1759
1760 hba->clk_gating.is_enabled = value;
1761out:
1762 return count;
1763}
1764
1ab27c9c
ST		 1765static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1766{
10e5e375
VV		 1767 char wq_name[sizeof("ufs_clk_gating_00")];
1768
1ab27c9c
ST		 1769 if (!ufshcd_is_clkgating_allowed(hba))
1770 return;
1771
1772 hba->clk_gating.delay_ms = 150;
1773 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1774 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1775
10e5e375
VV		 1776 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1777 hba->host->host_no);
1778 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1779 WQ_MEM_RECLAIM);
1780
b427411a
ST		 1781 hba->clk_gating.is_enabled = true;
1782
1ab27c9c
ST		 1783 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1784 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1785 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1786 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1787 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1788 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1789 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1790
1791 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1792 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1793 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1794 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1795 hba->clk_gating.enable_attr.attr.mode = 0644;
1796 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1797 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1798}
1799
1800static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1801{
1802 if (!ufshcd_is_clkgating_allowed(hba))
1803 return;
1804 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1805 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1806 cancel_work_sync(&hba->clk_gating.ungate_work);
1807 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
10e5e375 1808 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 1809}
1810
856b3483
ST		 1811/* Must be called with host lock acquired */
1812static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1813{
401f1e44
SJ		 1814 bool queue_resume_work = false;
1815
fcb0c4b0 1816 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1817 return;
1818
401f1e44
SJ		 1819 if (!hba->clk_scaling.active_reqs++)
1820 queue_resume_work = true;
1821
1822 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1823 return;
1824
1825 if (queue_resume_work)
1826 queue_work(hba->clk_scaling.workq,
1827 &hba->clk_scaling.resume_work);
1828
1829 if (!hba->clk_scaling.window_start_t) {
1830 hba->clk_scaling.window_start_t = jiffies;
1831 hba->clk_scaling.tot_busy_t = 0;
1832 hba->clk_scaling.is_busy_started = false;
1833 }
1834
856b3483
ST		 1835 if (!hba->clk_scaling.is_busy_started) {
1836 hba->clk_scaling.busy_start_t = ktime_get();
1837 hba->clk_scaling.is_busy_started = true;
1838 }
1839}
1840
1841static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1842{
1843 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1844
fcb0c4b0 1845 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1846 return;
1847
1848 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1849 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1850 scaling->busy_start_t));
8b0e1953 1851 scaling->busy_start_t = 0;
856b3483
ST		 1852 scaling->is_busy_started = false;
1853 }
1854}
7a3e97b0
SY		 1855/**
1856 * ufshcd_send_command - Send SCSI or device management commands
1857 * @hba: per adapter instance
1858 * @task_tag: Task tag of the command
1859 */
1860static inline
1861void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1862{
ff8e20c6 1863 hba->lrb[task_tag].issue_time_stamp = ktime_get();
09017188 1864 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
856b3483 1865 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1866 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1867 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1868 /* Make sure that doorbell is committed immediately */
1869 wmb();
1a07f2d9 1870 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY		 1871}
1872
1873/**
1874 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 1875 * @lrbp: pointer to local reference block
7a3e97b0
SY		 1876 */
1877static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1878{
1879 int len;
1c2623c5
SJ		 1880 if (lrbp->sense_buffer &&
1881 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1882 int len_to_copy;
1883
5a0b0cb9 1884 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1885 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1886
7a3e97b0 1887 memcpy(lrbp->sense_buffer,
5a0b0cb9 1888 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1889 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1890 }
1891}
1892
68078d5c
DR		 1893/**
1894 * ufshcd_copy_query_response() - Copy the Query Response and the data
1895 * descriptor
1896 * @hba: per adapter instance
8aa29f19 1897 * @lrbp: pointer to local reference block
68078d5c
DR		 1898 */
1899static
c6d4a831 1900int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1901{
1902 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1903
68078d5c 1904 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1905
68078d5c
DR		 1906 /* Get the descriptor */
1907 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1908 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1909 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1910 u16 resp_len;
1911 u16 buf_len;
68078d5c
DR		 1912
1913 /* data segment length */
c6d4a831 1914 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1915 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1916 buf_len = be16_to_cpu(
1917 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1918 if (likely(buf_len >= resp_len)) {
1919 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1920 } else {
1921 dev_warn(hba->dev,
1922 "%s: Response size is bigger than buffer",
1923 __func__);
1924 return -EINVAL;
1925 }
68078d5c 1926 }
c6d4a831
DR		 1927
1928 return 0;
68078d5c
DR		 1929}
1930
7a3e97b0
SY		 1931/**
1932 * ufshcd_hba_capabilities - Read controller capabilities
1933 * @hba: per adapter instance
1934 */
1935static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1936{
b873a275 1937 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1938
1939 /* nutrs and nutmrs are 0 based values */
1940 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1941 hba->nutmrs =
1942 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1943}
1944
1945/**
6ccf44fe
SJ		 1946 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1947 * to accept UIC commands
7a3e97b0 1948 * @hba: per adapter instance
6ccf44fe
SJ		 1949 * Return true on success, else false
1950 */
1951static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1952{
1953 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1954 return true;
1955 else
1956 return false;
1957}
1958
53b3d9c3
SJ		 1959/**
1960 * ufshcd_get_upmcrs - Get the power mode change request status
1961 * @hba: Pointer to adapter instance
1962 *
1963 * This function gets the UPMCRS field of HCS register
1964 * Returns value of UPMCRS field
1965 */
1966static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1967{
1968 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1969}
1970
6ccf44fe
SJ		 1971/**
1972 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1973 * @hba: per adapter instance
1974 * @uic_cmd: UIC command
1975 *
1976 * Mutex must be held.
7a3e97b0
SY		 1977 */
1978static inline void
6ccf44fe 1979ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1980{
6ccf44fe
SJ		 1981 WARN_ON(hba->active_uic_cmd);
1982
1983 hba->active_uic_cmd = uic_cmd;
1984
7a3e97b0 1985 /* Write Args */
6ccf44fe
SJ		 1986 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1987 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1988 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1989
1990 /* Write UIC Cmd */
6ccf44fe 1991 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1992 REG_UIC_COMMAND);
7a3e97b0
SY		 1993}
1994
6ccf44fe
SJ		 1995/**
1996 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1997 * @hba: per adapter instance
8aa29f19 1998 * @uic_cmd: UIC command
6ccf44fe
SJ		 1999 *
2000 * Must be called with mutex held.
2001 * Returns 0 only if success.
2002 */
2003static int
2004ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2005{
2006 int ret;
2007 unsigned long flags;
2008
2009 if (wait_for_completion_timeout(&uic_cmd->done,
2010 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2011 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2012 else
2013 ret = -ETIMEDOUT;
2014
2015 spin_lock_irqsave(hba->host->host_lock, flags);
2016 hba->active_uic_cmd = NULL;
2017 spin_unlock_irqrestore(hba->host->host_lock, flags);
2018
2019 return ret;
2020}
2021
2022/**
2023 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2024 * @hba: per adapter instance
2025 * @uic_cmd: UIC command
d75f7fe4 2026 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 2027 *
2028 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 2029 * with mutex held and host_lock locked.
6ccf44fe
SJ		 2030 * Returns 0 only if success.
2031 */
2032static int
d75f7fe4
YG		 2033__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2034 bool completion)
6ccf44fe 2035{
6ccf44fe
SJ		 2036 if (!ufshcd_ready_for_uic_cmd(hba)) {
2037 dev_err(hba->dev,
2038 "Controller not ready to accept UIC commands\n");
2039 return -EIO;
2040 }
2041
d75f7fe4
YG		 2042 if (completion)
2043 init_completion(&uic_cmd->done);
6ccf44fe 2044
6ccf44fe 2045 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2046
57d104c1 2047 return 0;
6ccf44fe
SJ		 2048}
2049
2050/**
2051 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2052 * @hba: per adapter instance
2053 * @uic_cmd: UIC command
2054 *
2055 * Returns 0 only if success.
2056 */
2057static int
2058ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2059{
2060 int ret;
57d104c1 2061 unsigned long flags;
6ccf44fe 2062
1ab27c9c 2063 ufshcd_hold(hba, false);
6ccf44fe 2064 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2065 ufshcd_add_delay_before_dme_cmd(hba);
2066
57d104c1 2067 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2068 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2069 spin_unlock_irqrestore(hba->host->host_lock, flags);
2070 if (!ret)
2071 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2072
6ccf44fe
SJ		 2073 mutex_unlock(&hba->uic_cmd_mutex);
2074
1ab27c9c 2075 ufshcd_release(hba);
6ccf44fe
SJ		 2076 return ret;
2077}
2078
7a3e97b0
SY		 2079/**
2080 * ufshcd_map_sg - Map scatter-gather list to prdt
8aa29f19
BVA		 2081 * @hba: per adapter instance
2082 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2083 *
2084 * Returns 0 in case of success, non-zero value in case of failure
2085 */
75b1cc4a 2086static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2087{
2088 struct ufshcd_sg_entry *prd_table;
2089 struct scatterlist *sg;
2090 struct scsi_cmnd *cmd;
2091 int sg_segments;
2092 int i;
2093
2094 cmd = lrbp->cmd;
2095 sg_segments = scsi_dma_map(cmd);
2096 if (sg_segments < 0)
2097 return sg_segments;
2098
2099 if (sg_segments) {
75b1cc4a
KK		 2100 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2101 lrbp->utr_descriptor_ptr->prd_table_length =
2102 cpu_to_le16((u16)(sg_segments *
2103 sizeof(struct ufshcd_sg_entry)));
2104 else
2105 lrbp->utr_descriptor_ptr->prd_table_length =
2106 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2107
2108 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2109
2110 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2111 prd_table[i].size =
2112 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2113 prd_table[i].base_addr =
2114 cpu_to_le32(lower_32_bits(sg->dma_address));
2115 prd_table[i].upper_addr =
2116 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2117 prd_table[i].reserved = 0;
7a3e97b0
SY		 2118 }
2119 } else {
2120 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2121 }
2122
2123 return 0;
2124}
2125
2126/**
2fbd009b 2127 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2128 * @hba: per adapter instance
2fbd009b 2129 * @intrs: interrupt bits
7a3e97b0 2130 */
2fbd009b 2131static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2132{
2fbd009b
SJ		 2133 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2134
2135 if (hba->ufs_version == UFSHCI_VERSION_10) {
2136 u32 rw;
2137 rw = set & INTERRUPT_MASK_RW_VER_10;
2138 set = rw | ((set ^ intrs) & intrs);
2139 } else {
2140 set |= intrs;
2141 }
2142
2143 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2144}
2145
2146/**
2147 * ufshcd_disable_intr - disable interrupts
2148 * @hba: per adapter instance
2149 * @intrs: interrupt bits
2150 */
2151static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2152{
2153 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2154
2155 if (hba->ufs_version == UFSHCI_VERSION_10) {
2156 u32 rw;
2157 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2158 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2159 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2160
2161 } else {
2162 set &= ~intrs;
7a3e97b0 2163 }
2fbd009b
SJ		 2164
2165 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2166}
2167
5a0b0cb9
SRT		 2168/**
2169 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2170 * descriptor according to request
2171 * @lrbp: pointer to local reference block
2172 * @upiu_flags: flags required in the header
2173 * @cmd_dir: requests data direction
2174 */
2175static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2176 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2177{
2178 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2179 u32 data_direction;
2180 u32 dword_0;
2181
2182 if (cmd_dir == DMA_FROM_DEVICE) {
2183 data_direction = UTP_DEVICE_TO_HOST;
2184 *upiu_flags = UPIU_CMD_FLAGS_READ;
2185 } else if (cmd_dir == DMA_TO_DEVICE) {
2186 data_direction = UTP_HOST_TO_DEVICE;
2187 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2188 } else {
2189 data_direction = UTP_NO_DATA_TRANSFER;
2190 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2191 }
2192
2193 dword_0 = data_direction | (lrbp->command_type
2194 << UPIU_COMMAND_TYPE_OFFSET);
2195 if (lrbp->intr_cmd)
2196 dword_0 |= UTP_REQ_DESC_INT_CMD;
2197
2198 /* Transfer request descriptor header fields */
2199 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2200 /* dword_1 is reserved, hence it is set to 0 */
2201 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2202 /*
2203 * assigning invalid value for command status. Controller
2204 * updates OCS on command completion, with the command
2205 * status
2206 */
2207 req_desc->header.dword_2 =
2208 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2209 /* dword_3 is reserved, hence it is set to 0 */
2210 req_desc->header.dword_3 = 0;
51047266
YG		 2211
2212 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2213}
2214
2215/**
2216 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2217 * for scsi commands
8aa29f19
BVA		 2218 * @lrbp: local reference block pointer
2219 * @upiu_flags: flags
5a0b0cb9
SRT		 2220 */
2221static
2222void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2223{
2224 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2225 unsigned short cdb_len;
5a0b0cb9
SRT		 2226
2227 /* command descriptor fields */
2228 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2229 UPIU_TRANSACTION_COMMAND, upiu_flags,
2230 lrbp->lun, lrbp->task_tag);
2231 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2232 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2233
2234 /* Total EHS length and Data segment length will be zero */
2235 ucd_req_ptr->header.dword_2 = 0;
2236
2237 ucd_req_ptr->sc.exp_data_transfer_len =
2238 cpu_to_be32(lrbp->cmd->sdb.length);
2239
52ac95fe
YG		 2240 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
2241 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
2242 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2243
2244 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2245}
2246
68078d5c
DR		 2247/**
2248 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2249 * for query requsts
2250 * @hba: UFS hba
2251 * @lrbp: local reference block pointer
2252 * @upiu_flags: flags
2253 */
2254static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2255 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2256{
2257 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2258 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2259 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2260 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2261
2262 /* Query request header */
2263 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2264 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2265 lrbp->lun, lrbp->task_tag);
2266 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2267 0, query->request.query_func, 0, 0);
2268
6861285c
ZL		 2269 /* Data segment length only need for WRITE_DESC */
2270 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2271 ucd_req_ptr->header.dword_2 =
2272 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2273 else
2274 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2275
2276 /* Copy the Query Request buffer as is */
2277 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2278 QUERY_OSF_SIZE);
68078d5c
DR		 2279
2280 /* Copy the Descriptor */
c6d4a831
DR		 2281 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2282 memcpy(descp, query->descriptor, len);
2283
51047266 2284 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2285}
2286
5a0b0cb9
SRT		 2287static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2288{
2289 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2290
2291 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2292
2293 /* command descriptor fields */
2294 ucd_req_ptr->header.dword_0 =
2295 UPIU_HEADER_DWORD(
2296 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2297 /* clear rest of the fields of basic header */
2298 ucd_req_ptr->header.dword_1 = 0;
2299 ucd_req_ptr->header.dword_2 = 0;
2300
2301 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2302}
2303
7a3e97b0 2304/**
300bb13f
JP		 2305 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2306 * for Device Management Purposes
8aa29f19
BVA		 2307 * @hba: per adapter instance
2308 * @lrbp: pointer to local reference block
7a3e97b0 2309 */
300bb13f 2310static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2311{
7a3e97b0 2312 u32 upiu_flags;
5a0b0cb9 2313 int ret = 0;
7a3e97b0 2314
83dc7e3d 2315 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2316 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2317 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2318 else
2319 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2320
2321 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2322 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2323 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2324 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2325 ufshcd_prepare_utp_nop_upiu(lrbp);
2326 else
2327 ret = -EINVAL;
2328
2329 return ret;
2330}
2331
2332/**
2333 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2334 * for SCSI Purposes
8aa29f19
BVA		 2335 * @hba: per adapter instance
2336 * @lrbp: pointer to local reference block
300bb13f
JP		 2337 */
2338static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2339{
2340 u32 upiu_flags;
2341 int ret = 0;
2342
83dc7e3d 2343 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2344 (hba->ufs_version == UFSHCI_VERSION_11))
300bb13f 2345 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2346 else
2347 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2348
2349 if (likely(lrbp->cmd)) {
2350 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2351 lrbp->cmd->sc_data_direction);
2352 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2353 } else {
2354 ret = -EINVAL;
2355 }
5a0b0cb9
SRT		 2356
2357 return ret;
7a3e97b0
SY		 2358}
2359
2a8fa600
SJ		 2360/**
2361 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2362 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2363 *
2364 * Returns SCSI W-LUN id
2365 */
2366static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2367{
2368 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2369}
2370
7a3e97b0
SY		 2371/**
2372 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2373 * @host: SCSI host pointer
7a3e97b0 2374 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2375 *
2376 * Returns 0 for success, non-zero in case of failure
2377 */
2378static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2379{
2380 struct ufshcd_lrb *lrbp;
2381 struct ufs_hba *hba;
2382 unsigned long flags;
2383 int tag;
2384 int err = 0;
2385
2386 hba = shost_priv(host);
2387
2388 tag = cmd->request->tag;
14497328
YG		 2389 if (!ufshcd_valid_tag(hba, tag)) {
2390 dev_err(hba->dev,
2391 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2392 __func__, tag, cmd, cmd->request);
2393 BUG();
2394 }
7a3e97b0 2395
a3cd5ec5
SJ		 2396 if (!down_read_trylock(&hba->clk_scaling_lock))
2397 return SCSI_MLQUEUE_HOST_BUSY;
2398
3441da7d
SRT		 2399 spin_lock_irqsave(hba->host->host_lock, flags);
2400 switch (hba->ufshcd_state) {
2401 case UFSHCD_STATE_OPERATIONAL:
2402 break;
141f8165 2403 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2404 case UFSHCD_STATE_RESET:
7a3e97b0 2405 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2406 goto out_unlock;
2407 case UFSHCD_STATE_ERROR:
2408 set_host_byte(cmd, DID_ERROR);
2409 cmd->scsi_done(cmd);
2410 goto out_unlock;
2411 default:
2412 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2413 __func__, hba->ufshcd_state);
2414 set_host_byte(cmd, DID_BAD_TARGET);
2415 cmd->scsi_done(cmd);
2416 goto out_unlock;
7a3e97b0 2417 }
53c12d0e
YG		 2418
2419 /* if error handling is in progress, don't issue commands */
2420 if (ufshcd_eh_in_progress(hba)) {
2421 set_host_byte(cmd, DID_ERROR);
2422 cmd->scsi_done(cmd);
2423 goto out_unlock;
2424 }
3441da7d 2425 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2426
7fabb77b
GB		 2427 hba->req_abort_count = 0;
2428
5a0b0cb9
SRT		 2429 /* acquire the tag to make sure device cmds don't use it */
2430 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2431 /*
2432 * Dev manage command in progress, requeue the command.
2433 * Requeuing the command helps in cases where the request *may*
2434 * find different tag instead of waiting for dev manage command
2435 * completion.
2436 */
2437 err = SCSI_MLQUEUE_HOST_BUSY;
2438 goto out;
2439 }
2440
1ab27c9c
ST		 2441 err = ufshcd_hold(hba, true);
2442 if (err) {
2443 err = SCSI_MLQUEUE_HOST_BUSY;
2444 clear_bit_unlock(tag, &hba->lrb_in_use);
2445 goto out;
2446 }
2447 WARN_ON(hba->clk_gating.state != CLKS_ON);
2448
7a3e97b0
SY		 2449 lrbp = &hba->lrb[tag];
2450
5a0b0cb9 2451 WARN_ON(lrbp->cmd);
7a3e97b0 2452 lrbp->cmd = cmd;
dcea0bfb 2453 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 2454 lrbp->sense_buffer = cmd->sense_buffer;
2455 lrbp->task_tag = tag;
0ce147d4 2456 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2457 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2458 lrbp->req_abort_skip = false;
7a3e97b0 2459
300bb13f
JP		 2460 ufshcd_comp_scsi_upiu(hba, lrbp);
2461
75b1cc4a 2462 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2463 if (err) {
2464 lrbp->cmd = NULL;
2465 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2466 goto out;
5a0b0cb9 2467 }
ad1a1b9c
GB		 2468 /* Make sure descriptors are ready before ringing the doorbell */
2469 wmb();
7a3e97b0
SY		 2470
2471 /* issue command to the controller */
2472 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2473 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 2474 ufshcd_send_command(hba, tag);
3441da7d 2475out_unlock:
7a3e97b0
SY		 2476 spin_unlock_irqrestore(hba->host->host_lock, flags);
2477out:
a3cd5ec5 2478 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2479 return err;
2480}
2481
5a0b0cb9
SRT		 2482static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2483 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2484{
2485 lrbp->cmd = NULL;
2486 lrbp->sense_bufflen = 0;
2487 lrbp->sense_buffer = NULL;
2488 lrbp->task_tag = tag;
2489 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2490 lrbp->intr_cmd = true; /* No interrupt aggregation */
2491 hba->dev_cmd.type = cmd_type;
2492
300bb13f 2493 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2494}
2495
2496static int
2497ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2498{
2499 int err = 0;
2500 unsigned long flags;
2501 u32 mask = 1 << tag;
2502
2503 /* clear outstanding transaction before retry */
2504 spin_lock_irqsave(hba->host->host_lock, flags);
2505 ufshcd_utrl_clear(hba, tag);
2506 spin_unlock_irqrestore(hba->host->host_lock, flags);
2507
2508 /*
2509 * wait for for h/w to clear corresponding bit in door-bell.
2510 * max. wait is 1 sec.
2511 */
2512 err = ufshcd_wait_for_register(hba,
2513 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2514 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2515
2516 return err;
2517}
2518
c6d4a831
DR		 2519static int
2520ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2521{
2522 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2523
2524 /* Get the UPIU response */
2525 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2526 UPIU_RSP_CODE_OFFSET;
2527 return query_res->response;
2528}
2529
5a0b0cb9
SRT		 2530/**
2531 * ufshcd_dev_cmd_completion() - handles device management command responses
2532 * @hba: per adapter instance
2533 * @lrbp: pointer to local reference block
2534 */
2535static int
2536ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2537{
2538 int resp;
2539 int err = 0;
2540
ff8e20c6 2541 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2542 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2543
2544 switch (resp) {
2545 case UPIU_TRANSACTION_NOP_IN:
2546 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2547 err = -EINVAL;
2548 dev_err(hba->dev, "%s: unexpected response %x\n",
2549 __func__, resp);
2550 }
2551 break;
68078d5c 2552 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2553 err = ufshcd_check_query_response(hba, lrbp);
2554 if (!err)
2555 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2556 break;
5a0b0cb9
SRT		 2557 case UPIU_TRANSACTION_REJECT_UPIU:
2558 /* TODO: handle Reject UPIU Response */
2559 err = -EPERM;
2560 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2561 __func__);
2562 break;
2563 default:
2564 err = -EINVAL;
2565 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2566 __func__, resp);
2567 break;
2568 }
2569
2570 return err;
2571}
2572
2573static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2574 struct ufshcd_lrb *lrbp, int max_timeout)
2575{
2576 int err = 0;
2577 unsigned long time_left;
2578 unsigned long flags;
2579
2580 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2581 msecs_to_jiffies(max_timeout));
2582
ad1a1b9c
GB		 2583 /* Make sure descriptors are ready before ringing the doorbell */
2584 wmb();
5a0b0cb9
SRT		 2585 spin_lock_irqsave(hba->host->host_lock, flags);
2586 hba->dev_cmd.complete = NULL;
2587 if (likely(time_left)) {
2588 err = ufshcd_get_tr_ocs(lrbp);
2589 if (!err)
2590 err = ufshcd_dev_cmd_completion(hba, lrbp);
2591 }
2592 spin_unlock_irqrestore(hba->host->host_lock, flags);
2593
2594 if (!time_left) {
2595 err = -ETIMEDOUT;
a48353f6
YG		 2596 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2597 __func__, lrbp->task_tag);
5a0b0cb9 2598 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2599 /* successfully cleared the command, retry if needed */
5a0b0cb9 2600 err = -EAGAIN;
a48353f6
YG		 2601 /*
2602 * in case of an error, after clearing the doorbell,
2603 * we also need to clear the outstanding_request
2604 * field in hba
2605 */
2606 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2607 }
2608
2609 return err;
2610}
2611
2612/**
2613 * ufshcd_get_dev_cmd_tag - Get device management command tag
2614 * @hba: per-adapter instance
8aa29f19 2615 * @tag_out: pointer to variable with available slot value
5a0b0cb9
SRT		 2616 *
2617 * Get a free slot and lock it until device management command
2618 * completes.
2619 *
2620 * Returns false if free slot is unavailable for locking, else
2621 * return true with tag value in @tag.
2622 */
2623static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2624{
2625 int tag;
2626 bool ret = false;
2627 unsigned long tmp;
2628
2629 if (!tag_out)
2630 goto out;
2631
2632 do {
2633 tmp = ~hba->lrb_in_use;
2634 tag = find_last_bit(&tmp, hba->nutrs);
2635 if (tag >= hba->nutrs)
2636 goto out;
2637 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2638
2639 *tag_out = tag;
2640 ret = true;
2641out:
2642 return ret;
2643}
2644
2645static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2646{
2647 clear_bit_unlock(tag, &hba->lrb_in_use);
2648}
2649
2650/**
2651 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 2652 * @hba: UFS hba
2653 * @cmd_type: specifies the type (NOP, Query...)
2654 * @timeout: time in seconds
5a0b0cb9 2655 *
68078d5c
DR		 2656 * NOTE: Since there is only one available tag for device management commands,
2657 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2658 */
2659static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2660 enum dev_cmd_type cmd_type, int timeout)
2661{
2662 struct ufshcd_lrb *lrbp;
2663 int err;
2664 int tag;
2665 struct completion wait;
2666 unsigned long flags;
2667
a3cd5ec5
SJ		 2668 down_read(&hba->clk_scaling_lock);
2669
5a0b0cb9
SRT		 2670 /*
2671 * Get free slot, sleep if slots are unavailable.
2672 * Even though we use wait_event() which sleeps indefinitely,
2673 * the maximum wait time is bounded by SCSI request timeout.
2674 */
2675 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2676
2677 init_completion(&wait);
2678 lrbp = &hba->lrb[tag];
2679 WARN_ON(lrbp->cmd);
2680 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2681 if (unlikely(err))
2682 goto out_put_tag;
2683
2684 hba->dev_cmd.complete = &wait;
2685
6667e6d9 2686 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
e3dfdc53
YG		 2687 /* Make sure descriptors are ready before ringing the doorbell */
2688 wmb();
5a0b0cb9 2689 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2690 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 2691 ufshcd_send_command(hba, tag);
2692 spin_unlock_irqrestore(hba->host->host_lock, flags);
2693
2694 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2695
6667e6d9
OS		 2696 ufshcd_add_query_upiu_trace(hba, tag,
2697 err ? "query_complete_err" : "query_complete");
2698
5a0b0cb9
SRT		 2699out_put_tag:
2700 ufshcd_put_dev_cmd_tag(hba, tag);
2701 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2702 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2703 return err;
2704}
2705
d44a5f98
DR		 2706/**
2707 * ufshcd_init_query() - init the query response and request parameters
2708 * @hba: per-adapter instance
2709 * @request: address of the request pointer to be initialized
2710 * @response: address of the response pointer to be initialized
2711 * @opcode: operation to perform
2712 * @idn: flag idn to access
2713 * @index: LU number to access
2714 * @selector: query/flag/descriptor further identification
2715 */
2716static inline void ufshcd_init_query(struct ufs_hba *hba,
2717 struct ufs_query_req **request, struct ufs_query_res **response,
2718 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2719{
2720 *request = &hba->dev_cmd.query.request;
2721 *response = &hba->dev_cmd.query.response;
2722 memset(*request, 0, sizeof(struct ufs_query_req));
2723 memset(*response, 0, sizeof(struct ufs_query_res));
2724 (*request)->upiu_req.opcode = opcode;
2725 (*request)->upiu_req.idn = idn;
2726 (*request)->upiu_req.index = index;
2727 (*request)->upiu_req.selector = selector;
2728}
2729
dc3c8d3a
YG		 2730static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2731 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2732{
2733 int ret;
2734 int retries;
2735
2736 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2737 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2738 if (ret)
2739 dev_dbg(hba->dev,
2740 "%s: failed with error %d, retries %d\n",
2741 __func__, ret, retries);
2742 else
2743 break;
2744 }
2745
2746 if (ret)
2747 dev_err(hba->dev,
2748 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2749 __func__, opcode, idn, ret, retries);
2750 return ret;
2751}
2752
68078d5c
DR		 2753/**
2754 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 2755 * @hba: per-adapter instance
2756 * @opcode: flag query to perform
2757 * @idn: flag idn to access
2758 * @flag_res: the flag value after the query request completes
68078d5c
DR		 2759 *
2760 * Returns 0 for success, non-zero in case of failure
2761 */
dc3c8d3a 2762int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2763 enum flag_idn idn, bool *flag_res)
2764{
d44a5f98
DR		 2765 struct ufs_query_req *request = NULL;
2766 struct ufs_query_res *response = NULL;
2767 int err, index = 0, selector = 0;
e5ad406c 2768 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2769
2770 BUG_ON(!hba);
2771
1ab27c9c 2772 ufshcd_hold(hba, false);
68078d5c 2773 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2774 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2775 selector);
68078d5c
DR		 2776
2777 switch (opcode) {
2778 case UPIU_QUERY_OPCODE_SET_FLAG:
2779 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2780 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2781 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2782 break;
2783 case UPIU_QUERY_OPCODE_READ_FLAG:
2784 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2785 if (!flag_res) {
2786 /* No dummy reads */
2787 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2788 __func__);
2789 err = -EINVAL;
2790 goto out_unlock;
2791 }
2792 break;
2793 default:
2794 dev_err(hba->dev,
2795 "%s: Expected query flag opcode but got = %d\n",
2796 __func__, opcode);
2797 err = -EINVAL;
2798 goto out_unlock;
2799 }
68078d5c 2800
e5ad406c 2801 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2802
2803 if (err) {
2804 dev_err(hba->dev,
2805 "%s: Sending flag query for idn %d failed, err = %d\n",
2806 __func__, idn, err);
2807 goto out_unlock;
2808 }
2809
2810 if (flag_res)
e8c8e82a 2811 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2812 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2813
2814out_unlock:
2815 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2816 ufshcd_release(hba);
68078d5c
DR		 2817 return err;
2818}
2819
66ec6d59
SRT		 2820/**
2821 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 2822 * @hba: per-adapter instance
2823 * @opcode: attribute opcode
2824 * @idn: attribute idn to access
2825 * @index: index field
2826 * @selector: selector field
2827 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 2828 *
2829 * Returns 0 for success, non-zero in case of failure
2830*/
ec92b59c
SN		 2831int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2832 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 2833{
d44a5f98
DR		 2834 struct ufs_query_req *request = NULL;
2835 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2836 int err;
2837
2838 BUG_ON(!hba);
2839
1ab27c9c 2840 ufshcd_hold(hba, false);
66ec6d59
SRT		 2841 if (!attr_val) {
2842 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2843 __func__, opcode);
2844 err = -EINVAL;
2845 goto out;
2846 }
2847
2848 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2849 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2850 selector);
66ec6d59
SRT		 2851
2852 switch (opcode) {
2853 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2854 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2855 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2856 break;
2857 case UPIU_QUERY_OPCODE_READ_ATTR:
2858 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2859 break;
2860 default:
2861 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2862 __func__, opcode);
2863 err = -EINVAL;
2864 goto out_unlock;
2865 }
2866
d44a5f98 2867 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2868
2869 if (err) {
4b761b58
YG		 2870 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2871 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2872 goto out_unlock;
2873 }
2874
e8c8e82a 2875 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2876
2877out_unlock:
2878 mutex_unlock(&hba->dev_cmd.lock);
2879out:
1ab27c9c 2880 ufshcd_release(hba);
66ec6d59
SRT		 2881 return err;
2882}
2883
5e86ae44
YG		 2884/**
2885 * ufshcd_query_attr_retry() - API function for sending query
2886 * attribute with retries
2887 * @hba: per-adapter instance
2888 * @opcode: attribute opcode
2889 * @idn: attribute idn to access
2890 * @index: index field
2891 * @selector: selector field
2892 * @attr_val: the attribute value after the query request
2893 * completes
2894 *
2895 * Returns 0 for success, non-zero in case of failure
2896*/
2897static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2898 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2899 u32 *attr_val)
2900{
2901 int ret = 0;
2902 u32 retries;
2903
2904 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2905 ret = ufshcd_query_attr(hba, opcode, idn, index,
2906 selector, attr_val);
2907 if (ret)
2908 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2909 __func__, ret, retries);
2910 else
2911 break;
2912 }
2913
2914 if (ret)
2915 dev_err(hba->dev,
2916 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2917 __func__, idn, ret, QUERY_REQ_RETRIES);
2918 return ret;
2919}
2920
a70e91b8 2921static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2922 enum query_opcode opcode, enum desc_idn idn, u8 index,
2923 u8 selector, u8 *desc_buf, int *buf_len)
2924{
2925 struct ufs_query_req *request = NULL;
2926 struct ufs_query_res *response = NULL;
2927 int err;
2928
2929 BUG_ON(!hba);
2930
1ab27c9c 2931 ufshcd_hold(hba, false);
d44a5f98
DR		 2932 if (!desc_buf) {
2933 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2934 __func__, opcode);
2935 err = -EINVAL;
2936 goto out;
2937 }
2938
a4b0e8a4 2939 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2940 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2941 __func__, *buf_len);
2942 err = -EINVAL;
2943 goto out;
2944 }
2945
2946 mutex_lock(&hba->dev_cmd.lock);
2947 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2948 selector);
2949 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2950 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2951
2952 switch (opcode) {
2953 case UPIU_QUERY_OPCODE_WRITE_DESC:
2954 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2955 break;
2956 case UPIU_QUERY_OPCODE_READ_DESC:
2957 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2958 break;
2959 default:
2960 dev_err(hba->dev,
2961 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2962 __func__, opcode);
2963 err = -EINVAL;
2964 goto out_unlock;
2965 }
2966
2967 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2968
2969 if (err) {
4b761b58
YG		 2970 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2971 __func__, opcode, idn, index, err);
d44a5f98
DR		 2972 goto out_unlock;
2973 }
2974
2975 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2976 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2977
2978out_unlock:
2979 mutex_unlock(&hba->dev_cmd.lock);
2980out:
1ab27c9c 2981 ufshcd_release(hba);
d44a5f98
DR		 2982 return err;
2983}
2984
a70e91b8 2985/**
8aa29f19
BVA		 2986 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
2987 * @hba: per-adapter instance
2988 * @opcode: attribute opcode
2989 * @idn: attribute idn to access
2990 * @index: index field
2991 * @selector: selector field
2992 * @desc_buf: the buffer that contains the descriptor
2993 * @buf_len: length parameter passed to the device
a70e91b8
YG		 2994 *
2995 * Returns 0 for success, non-zero in case of failure.
2996 * The buf_len parameter will contain, on return, the length parameter
2997 * received on the response.
2998 */
2238d31c
SN		 2999int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3000 enum query_opcode opcode,
3001 enum desc_idn idn, u8 index,
3002 u8 selector,
3003 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3004{
3005 int err;
3006 int retries;
3007
3008 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3009 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3010 selector, desc_buf, buf_len);
3011 if (!err || err == -EINVAL)
3012 break;
3013 }
3014
3015 return err;
3016}
a70e91b8 3017
a4b0e8a4
PM		 3018/**
3019 * ufshcd_read_desc_length - read the specified descriptor length from header
3020 * @hba: Pointer to adapter instance
3021 * @desc_id: descriptor idn value
3022 * @desc_index: descriptor index
3023 * @desc_length: pointer to variable to read the length of descriptor
3024 *
3025 * Return 0 in case of success, non-zero otherwise
3026 */
3027static int ufshcd_read_desc_length(struct ufs_hba *hba,
3028 enum desc_idn desc_id,
3029 int desc_index,
3030 int *desc_length)
3031{
3032 int ret;
3033 u8 header[QUERY_DESC_HDR_SIZE];
3034 int header_len = QUERY_DESC_HDR_SIZE;
3035
3036 if (desc_id >= QUERY_DESC_IDN_MAX)
3037 return -EINVAL;
3038
3039 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3040 desc_id, desc_index, 0, header,
3041 &header_len);
3042
3043 if (ret) {
3044 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3045 __func__, desc_id);
3046 return ret;
3047 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3048 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3049 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3050 desc_id);
3051 ret = -EINVAL;
3052 }
3053
3054 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3055 return ret;
3056
3057}
3058
3059/**
3060 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3061 * @hba: Pointer to adapter instance
3062 * @desc_id: descriptor idn value
3063 * @desc_len: mapped desc length (out)
3064 *
3065 * Return 0 in case of success, non-zero otherwise
3066 */
3067int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3068 enum desc_idn desc_id, int *desc_len)
3069{
3070 switch (desc_id) {
3071 case QUERY_DESC_IDN_DEVICE:
3072 *desc_len = hba->desc_size.dev_desc;
3073 break;
3074 case QUERY_DESC_IDN_POWER:
3075 *desc_len = hba->desc_size.pwr_desc;
3076 break;
3077 case QUERY_DESC_IDN_GEOMETRY:
3078 *desc_len = hba->desc_size.geom_desc;
3079 break;
3080 case QUERY_DESC_IDN_CONFIGURATION:
3081 *desc_len = hba->desc_size.conf_desc;
3082 break;
3083 case QUERY_DESC_IDN_UNIT:
3084 *desc_len = hba->desc_size.unit_desc;
3085 break;
3086 case QUERY_DESC_IDN_INTERCONNECT:
3087 *desc_len = hba->desc_size.interc_desc;
3088 break;
3089 case QUERY_DESC_IDN_STRING:
3090 *desc_len = QUERY_DESC_MAX_SIZE;
3091 break;
c648c2d2
SN		 3092 case QUERY_DESC_IDN_HEALTH:
3093 *desc_len = hba->desc_size.hlth_desc;
3094 break;
a4b0e8a4
PM		 3095 case QUERY_DESC_IDN_RFU_0:
3096 case QUERY_DESC_IDN_RFU_1:
3097 *desc_len = 0;
3098 break;
3099 default:
3100 *desc_len = 0;
3101 return -EINVAL;
3102 }
3103 return 0;
3104}
3105EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3106
da461cec
SJ		 3107/**
3108 * ufshcd_read_desc_param - read the specified descriptor parameter
3109 * @hba: Pointer to adapter instance
3110 * @desc_id: descriptor idn value
3111 * @desc_index: descriptor index
3112 * @param_offset: offset of the parameter to read
3113 * @param_read_buf: pointer to buffer where parameter would be read
3114 * @param_size: sizeof(param_read_buf)
3115 *
3116 * Return 0 in case of success, non-zero otherwise
3117 */
45bced87
SN		 3118int ufshcd_read_desc_param(struct ufs_hba *hba,
3119 enum desc_idn desc_id,
3120 int desc_index,
3121 u8 param_offset,
3122 u8 *param_read_buf,
3123 u8 param_size)
da461cec
SJ		 3124{
3125 int ret;
3126 u8 *desc_buf;
a4b0e8a4 3127 int buff_len;
da461cec
SJ		 3128 bool is_kmalloc = true;
3129
a4b0e8a4
PM		 3130 /* Safety check */
3131 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3132 return -EINVAL;
3133
a4b0e8a4
PM		 3134 /* Get the max length of descriptor from structure filled up at probe
3135 * time.
3136 */
3137 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3138
a4b0e8a4
PM		 3139 /* Sanity checks */
3140 if (ret || !buff_len) {
3141 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3142 __func__);
3143 return ret;
3144 }
3145
3146 /* Check whether we need temp memory */
3147 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3148 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3149 if (!desc_buf)
3150 return -ENOMEM;
a4b0e8a4
PM		 3151 } else {
3152 desc_buf = param_read_buf;
3153 is_kmalloc = false;
da461cec
SJ		 3154 }
3155
a4b0e8a4 3156 /* Request for full descriptor */
a70e91b8 3157 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3158 desc_id, desc_index, 0,
3159 desc_buf, &buff_len);
da461cec 3160
bde44bb6
SJ		 3161 if (ret) {
3162 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3163 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3164 goto out;
3165 }
3166
bde44bb6
SJ		 3167 /* Sanity check */
3168 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3169 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3170 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3171 ret = -EINVAL;
3172 goto out;
3173 }
3174
a4b0e8a4
PM		 3175 /* Check wherher we will not copy more data, than available */
3176 if (is_kmalloc && param_size > buff_len)
3177 param_size = buff_len;
bde44bb6 3178
da461cec
SJ		 3179 if (is_kmalloc)
3180 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3181out:
3182 if (is_kmalloc)
3183 kfree(desc_buf);
3184 return ret;
3185}
3186
3187static inline int ufshcd_read_desc(struct ufs_hba *hba,
3188 enum desc_idn desc_id,
3189 int desc_index,
3190 u8 *buf,
3191 u32 size)
3192{
3193 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3194}
3195
3196static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3197 u8 *buf,
3198 u32 size)
3199{
dbd34a61 3200 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
da461cec
SJ		 3201}
3202
8209b6d5 3203static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3204{
3205 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3206}
b573d484
YG		 3207
3208/**
3209 * ufshcd_read_string_desc - read string descriptor
3210 * @hba: pointer to adapter instance
3211 * @desc_index: descriptor index
3212 * @buf: pointer to buffer where descriptor would be read
3213 * @size: size of buf
3214 * @ascii: if true convert from unicode to ascii characters
3215 *
3216 * Return 0 in case of success, non-zero otherwise
3217 */
2238d31c
SN		 3218int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3219 u8 *buf, u32 size, bool ascii)
b573d484
YG		 3220{
3221 int err = 0;
3222
3223 err = ufshcd_read_desc(hba,
3224 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3225
3226 if (err) {
3227 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3228 __func__, QUERY_REQ_RETRIES, err);
3229 goto out;
3230 }
3231
3232 if (ascii) {
3233 int desc_len;
3234 int ascii_len;
3235 int i;
3236 char *buff_ascii;
3237
3238 desc_len = buf[0];
3239 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3240 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3241 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3242 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3243 __func__);
3244 err = -ENOMEM;
3245 goto out;
3246 }
3247
3248 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3249 if (!buff_ascii) {
3250 err = -ENOMEM;
fcbefc3b 3251 goto out;
b573d484
YG		 3252 }
3253
3254 /*
3255 * the descriptor contains string in UTF16 format
3256 * we need to convert to utf-8 so it can be displayed
3257 */
3258 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3259 desc_len - QUERY_DESC_HDR_SIZE,
3260 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3261
3262 /* replace non-printable or non-ASCII characters with spaces */
3263 for (i = 0; i < ascii_len; i++)
3264 ufshcd_remove_non_printable(&buff_ascii[i]);
3265
3266 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3267 size - QUERY_DESC_HDR_SIZE);
3268 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3269 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 3270 kfree(buff_ascii);
3271 }
3272out:
3273 return err;
3274}
b573d484 3275
da461cec
SJ		 3276/**
3277 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3278 * @hba: Pointer to adapter instance
3279 * @lun: lun id
3280 * @param_offset: offset of the parameter to read
3281 * @param_read_buf: pointer to buffer where parameter would be read
3282 * @param_size: sizeof(param_read_buf)
3283 *
3284 * Return 0 in case of success, non-zero otherwise
3285 */
3286static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3287 int lun,
3288 enum unit_desc_param param_offset,
3289 u8 *param_read_buf,
3290 u32 param_size)
3291{
3292 /*
3293 * Unit descriptors are only available for general purpose LUs (LUN id
3294 * from 0 to 7) and RPMB Well known LU.
3295 */
d829fc8a 3296 if (!ufs_is_valid_unit_desc_lun(lun))
da461cec
SJ		 3297 return -EOPNOTSUPP;
3298
3299 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3300 param_offset, param_read_buf, param_size);
3301}
3302
7a3e97b0
SY		 3303/**
3304 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3305 * @hba: per adapter instance
3306 *
3307 * 1. Allocate DMA memory for Command Descriptor array
3308 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3309 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3310 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3311 * (UTMRDL)
3312 * 4. Allocate memory for local reference block(lrb).
3313 *
3314 * Returns 0 for success, non-zero in case of failure
3315 */
3316static int ufshcd_memory_alloc(struct ufs_hba *hba)
3317{
3318 size_t utmrdl_size, utrdl_size, ucdl_size;
3319
3320 /* Allocate memory for UTP command descriptors */
3321 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3322 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3323 ucdl_size,
3324 &hba->ucdl_dma_addr,
3325 GFP_KERNEL);
7a3e97b0
SY		 3326
3327 /*
3328 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3329 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3330 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3331 * be aligned to 128 bytes as well
3332 */
3333 if (!hba->ucdl_base_addr ||
3334 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3335 dev_err(hba->dev,
7a3e97b0
SY		 3336 "Command Descriptor Memory allocation failed\n");
3337 goto out;
3338 }
3339
3340 /*
3341 * Allocate memory for UTP Transfer descriptors
3342 * UFSHCI requires 1024 byte alignment of UTRD
3343 */
3344 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3345 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3346 utrdl_size,
3347 &hba->utrdl_dma_addr,
3348 GFP_KERNEL);
7a3e97b0
SY		 3349 if (!hba->utrdl_base_addr ||
3350 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3351 dev_err(hba->dev,
7a3e97b0
SY		 3352 "Transfer Descriptor Memory allocation failed\n");
3353 goto out;
3354 }
3355
3356 /*
3357 * Allocate memory for UTP Task Management descriptors
3358 * UFSHCI requires 1024 byte alignment of UTMRD
3359 */
3360 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3361 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3362 utmrdl_size,
3363 &hba->utmrdl_dma_addr,
3364 GFP_KERNEL);
7a3e97b0
SY		 3365 if (!hba->utmrdl_base_addr ||
3366 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3367 dev_err(hba->dev,
7a3e97b0
SY		 3368 "Task Management Descriptor Memory allocation failed\n");
3369 goto out;
3370 }
3371
3372 /* Allocate memory for local reference block */
a86854d0
KC		 3373 hba->lrb = devm_kcalloc(hba->dev,
3374 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3375 GFP_KERNEL);
7a3e97b0 3376 if (!hba->lrb) {
3b1d0580 3377 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3378 goto out;
3379 }
3380 return 0;
3381out:
7a3e97b0
SY		 3382 return -ENOMEM;
3383}
3384
3385/**
3386 * ufshcd_host_memory_configure - configure local reference block with
3387 * memory offsets
3388 * @hba: per adapter instance
3389 *
3390 * Configure Host memory space
3391 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3392 * address.
3393 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3394 * and PRDT offset.
3395 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3396 * into local reference block.
3397 */
3398static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3399{
3400 struct utp_transfer_cmd_desc *cmd_descp;
3401 struct utp_transfer_req_desc *utrdlp;
3402 dma_addr_t cmd_desc_dma_addr;
3403 dma_addr_t cmd_desc_element_addr;
3404 u16 response_offset;
3405 u16 prdt_offset;
3406 int cmd_desc_size;
3407 int i;
3408
3409 utrdlp = hba->utrdl_base_addr;
3410 cmd_descp = hba->ucdl_base_addr;
3411
3412 response_offset =
3413 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3414 prdt_offset =
3415 offsetof(struct utp_transfer_cmd_desc, prd_table);
3416
3417 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3418 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3419
3420 for (i = 0; i < hba->nutrs; i++) {
3421 /* Configure UTRD with command descriptor base address */
3422 cmd_desc_element_addr =
3423 (cmd_desc_dma_addr + (cmd_desc_size * i));
3424 utrdlp[i].command_desc_base_addr_lo =
3425 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3426 utrdlp[i].command_desc_base_addr_hi =
3427 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3428
3429 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3430 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3431 utrdlp[i].response_upiu_offset =
3432 cpu_to_le16(response_offset);
3433 utrdlp[i].prd_table_offset =
3434 cpu_to_le16(prdt_offset);
3435 utrdlp[i].response_upiu_length =
3436 cpu_to_le16(ALIGNED_UPIU_SIZE);
3437 } else {
3438 utrdlp[i].response_upiu_offset =
7a3e97b0 3439 cpu_to_le16((response_offset >> 2));
75b1cc4a 3440 utrdlp[i].prd_table_offset =
7a3e97b0 3441 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3442 utrdlp[i].response_upiu_length =
3ca316c5 3443 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3444 }
7a3e97b0
SY		 3445
3446 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3447 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3448 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3449 hba->lrb[i].ucd_req_ptr =
3450 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3451 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3452 hba->lrb[i].ucd_rsp_ptr =
3453 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3454 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3455 response_offset;
7a3e97b0
SY		 3456 hba->lrb[i].ucd_prdt_ptr =
3457 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3458 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3459 prdt_offset;
7a3e97b0
SY		 3460 }
3461}
3462
3463/**
3464 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3465 * @hba: per adapter instance
3466 *
3467 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3468 * in order to initialize the Unipro link startup procedure.
3469 * Once the Unipro links are up, the device connected to the controller
3470 * is detected.
3471 *
3472 * Returns 0 on success, non-zero value on failure
3473 */
3474static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3475{
6ccf44fe
SJ		 3476 struct uic_command uic_cmd = {0};
3477 int ret;
7a3e97b0 3478
6ccf44fe 3479 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3480
6ccf44fe
SJ		 3481 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3482 if (ret)
ff8e20c6 3483 dev_dbg(hba->dev,
6ccf44fe
SJ		 3484 "dme-link-startup: error code %d\n", ret);
3485 return ret;
7a3e97b0 3486}
4404c5de
AA		 3487/**
3488 * ufshcd_dme_reset - UIC command for DME_RESET
3489 * @hba: per adapter instance
3490 *
3491 * DME_RESET command is issued in order to reset UniPro stack.
3492 * This function now deal with cold reset.
3493 *
3494 * Returns 0 on success, non-zero value on failure
3495 */
3496static int ufshcd_dme_reset(struct ufs_hba *hba)
3497{
3498 struct uic_command uic_cmd = {0};
3499 int ret;
3500
3501 uic_cmd.command = UIC_CMD_DME_RESET;
3502
3503 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3504 if (ret)
3505 dev_err(hba->dev,
3506 "dme-reset: error code %d\n", ret);
3507
3508 return ret;
3509}
3510
3511/**
3512 * ufshcd_dme_enable - UIC command for DME_ENABLE
3513 * @hba: per adapter instance
3514 *
3515 * DME_ENABLE command is issued in order to enable UniPro stack.
3516 *
3517 * Returns 0 on success, non-zero value on failure
3518 */
3519static int ufshcd_dme_enable(struct ufs_hba *hba)
3520{
3521 struct uic_command uic_cmd = {0};
3522 int ret;
3523
3524 uic_cmd.command = UIC_CMD_DME_ENABLE;
3525
3526 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3527 if (ret)
3528 dev_err(hba->dev,
3529 "dme-reset: error code %d\n", ret);
3530
3531 return ret;
3532}
7a3e97b0 3533
cad2e03d
YG		 3534static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3535{
3536 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3537 unsigned long min_sleep_time_us;
3538
3539 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3540 return;
3541
3542 /*
3543 * last_dme_cmd_tstamp will be 0 only for 1st call to
3544 * this function
3545 */
3546 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3547 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3548 } else {
3549 unsigned long delta =
3550 (unsigned long) ktime_to_us(
3551 ktime_sub(ktime_get(),
3552 hba->last_dme_cmd_tstamp));
3553
3554 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3555 min_sleep_time_us =
3556 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3557 else
3558 return; /* no more delay required */
3559 }
3560
3561 /* allow sleep for extra 50us if needed */
3562 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3563}
3564
12b4fdb4
SJ		 3565/**
3566 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3567 * @hba: per adapter instance
3568 * @attr_sel: uic command argument1
3569 * @attr_set: attribute set type as uic command argument2
3570 * @mib_val: setting value as uic command argument3
3571 * @peer: indicate whether peer or local
3572 *
3573 * Returns 0 on success, non-zero value on failure
3574 */
3575int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3576 u8 attr_set, u32 mib_val, u8 peer)
3577{
3578 struct uic_command uic_cmd = {0};
3579 static const char *const action[] = {
3580 "dme-set",
3581 "dme-peer-set"
3582 };
3583 const char *set = action[!!peer];
3584 int ret;
64238fbd 3585 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3586
3587 uic_cmd.command = peer ?
3588 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3589 uic_cmd.argument1 = attr_sel;
3590 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3591 uic_cmd.argument3 = mib_val;
3592
64238fbd
YG		 3593 do {
3594 /* for peer attributes we retry upon failure */
3595 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3596 if (ret)
3597 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3598 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3599 } while (ret && peer && --retries);
3600
f37e9f8c 3601 if (ret)
64238fbd 3602 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3603 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3604 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3605
3606 return ret;
3607}
3608EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3609
3610/**
3611 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3612 * @hba: per adapter instance
3613 * @attr_sel: uic command argument1
3614 * @mib_val: the value of the attribute as returned by the UIC command
3615 * @peer: indicate whether peer or local
3616 *
3617 * Returns 0 on success, non-zero value on failure
3618 */
3619int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3620 u32 *mib_val, u8 peer)
3621{
3622 struct uic_command uic_cmd = {0};
3623 static const char *const action[] = {
3624 "dme-get",
3625 "dme-peer-get"
3626 };
3627 const char *get = action[!!peer];
3628 int ret;
64238fbd 3629 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3630 struct ufs_pa_layer_attr orig_pwr_info;
3631 struct ufs_pa_layer_attr temp_pwr_info;
3632 bool pwr_mode_change = false;
3633
3634 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3635 orig_pwr_info = hba->pwr_info;
3636 temp_pwr_info = orig_pwr_info;
3637
3638 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3639 orig_pwr_info.pwr_rx == FAST_MODE) {
3640 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3641 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3642 pwr_mode_change = true;
3643 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3644 orig_pwr_info.pwr_rx == SLOW_MODE) {
3645 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3646 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3647 pwr_mode_change = true;
3648 }
3649 if (pwr_mode_change) {
3650 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3651 if (ret)
3652 goto out;
3653 }
3654 }
12b4fdb4
SJ		 3655
3656 uic_cmd.command = peer ?
3657 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3658 uic_cmd.argument1 = attr_sel;
3659
64238fbd
YG		 3660 do {
3661 /* for peer attributes we retry upon failure */
3662 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3663 if (ret)
3664 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3665 get, UIC_GET_ATTR_ID(attr_sel), ret);
3666 } while (ret && peer && --retries);
3667
f37e9f8c 3668 if (ret)
64238fbd 3669 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3670 get, UIC_GET_ATTR_ID(attr_sel),
3671 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3672
64238fbd 3673 if (mib_val && !ret)
12b4fdb4 3674 *mib_val = uic_cmd.argument3;
874237f7
YG		 3675
3676 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3677 && pwr_mode_change)
3678 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3679out:
3680 return ret;
3681}
3682EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3683
53b3d9c3 3684/**
57d104c1
SJ		 3685 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3686 * state) and waits for it to take effect.
3687 *
53b3d9c3 3688 * @hba: per adapter instance
57d104c1
SJ		 3689 * @cmd: UIC command to execute
3690 *
3691 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3692 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3693 * and device UniPro link and hence it's final completion would be indicated by
3694 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3695 * addition to normal UIC command completion Status (UCCS). This function only
3696 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3697 *
3698 * Returns 0 on success, non-zero value on failure
3699 */
57d104c1 3700static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3701{
57d104c1 3702 struct completion uic_async_done;
53b3d9c3
SJ		 3703 unsigned long flags;
3704 u8 status;
3705 int ret;
d75f7fe4 3706 bool reenable_intr = false;
53b3d9c3 3707
53b3d9c3 3708 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3709 init_completion(&uic_async_done);
cad2e03d 3710 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3711
3712 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3713 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3714 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3715 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3716 /*
3717 * Make sure UIC command completion interrupt is disabled before
3718 * issuing UIC command.
3719 */
3720 wmb();
3721 reenable_intr = true;
57d104c1 3722 }
d75f7fe4
YG		 3723 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3724 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3725 if (ret) {
3726 dev_err(hba->dev,
3727 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3728 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3729 goto out;
3730 }
3731
57d104c1 3732 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3733 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3734 dev_err(hba->dev,
57d104c1
SJ		 3735 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3736 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3737 ret = -ETIMEDOUT;
3738 goto out;
3739 }
3740
3741 status = ufshcd_get_upmcrs(hba);
3742 if (status != PWR_LOCAL) {
3743 dev_err(hba->dev,
479da360 3744 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 3745 cmd->command, status);
53b3d9c3
SJ		 3746 ret = (status != PWR_OK) ? status : -1;
3747 }
3748out:
7942f7b5
VG		 3749 if (ret) {
3750 ufshcd_print_host_state(hba);
3751 ufshcd_print_pwr_info(hba);
3752 ufshcd_print_host_regs(hba);
3753 }
3754
53b3d9c3 3755 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3756 hba->active_uic_cmd = NULL;
57d104c1 3757 hba->uic_async_done = NULL;
d75f7fe4
YG		 3758 if (reenable_intr)
3759 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3760 spin_unlock_irqrestore(hba->host->host_lock, flags);
3761 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3762
53b3d9c3
SJ		 3763 return ret;
3764}
3765
57d104c1
SJ		 3766/**
3767 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3768 * using DME_SET primitives.
3769 * @hba: per adapter instance
3770 * @mode: powr mode value
3771 *
3772 * Returns 0 on success, non-zero value on failure
3773 */
3774static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3775{
3776 struct uic_command uic_cmd = {0};
1ab27c9c 3777 int ret;
57d104c1 3778
c3a2f9ee
YG		 3779 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3780 ret = ufshcd_dme_set(hba,
3781 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3782 if (ret) {
3783 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3784 __func__, ret);
3785 goto out;
3786 }
3787 }
3788
57d104c1
SJ		 3789 uic_cmd.command = UIC_CMD_DME_SET;
3790 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3791 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3792 ufshcd_hold(hba, false);
3793 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3794 ufshcd_release(hba);
57d104c1 3795
c3a2f9ee 3796out:
1ab27c9c 3797 return ret;
57d104c1
SJ		 3798}
3799
53c12d0e
YG		 3800static int ufshcd_link_recovery(struct ufs_hba *hba)
3801{
3802 int ret;
3803 unsigned long flags;
3804
3805 spin_lock_irqsave(hba->host->host_lock, flags);
3806 hba->ufshcd_state = UFSHCD_STATE_RESET;
3807 ufshcd_set_eh_in_progress(hba);
3808 spin_unlock_irqrestore(hba->host->host_lock, flags);
3809
3810 ret = ufshcd_host_reset_and_restore(hba);
3811
3812 spin_lock_irqsave(hba->host->host_lock, flags);
3813 if (ret)
3814 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3815 ufshcd_clear_eh_in_progress(hba);
3816 spin_unlock_irqrestore(hba->host->host_lock, flags);
3817
3818 if (ret)
3819 dev_err(hba->dev, "%s: link recovery failed, err %d",
3820 __func__, ret);
3821
3822 return ret;
3823}
3824
87d0b4a6 3825static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3826{
87d0b4a6 3827 int ret;
57d104c1 3828 struct uic_command uic_cmd = {0};
911a0771 3829 ktime_t start = ktime_get();
57d104c1 3830
ee32c909
KK		 3831 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3832
57d104c1 3833 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3834 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3835 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3836 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3837
53c12d0e 3838 if (ret) {
87d0b4a6
YG		 3839 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3840 __func__, ret);
3841
53c12d0e
YG		 3842 /*
3843 * If link recovery fails then return error so that caller
3844 * don't retry the hibern8 enter again.
3845 */
3846 if (ufshcd_link_recovery(hba))
3847 ret = -ENOLINK;
ee32c909
KK		 3848 } else
3849 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3850 POST_CHANGE);
53c12d0e 3851
87d0b4a6
YG		 3852 return ret;
3853}
3854
3855static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3856{
3857 int ret = 0, retries;
57d104c1 3858
87d0b4a6
YG		 3859 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3860 ret = __ufshcd_uic_hibern8_enter(hba);
3861 if (!ret || ret == -ENOLINK)
3862 goto out;
3863 }
3864out:
3865 return ret;
57d104c1
SJ		 3866}
3867
3868static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3869{
3870 struct uic_command uic_cmd = {0};
3871 int ret;
911a0771 3872 ktime_t start = ktime_get();
57d104c1 3873
ee32c909
KK		 3874 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3875
57d104c1
SJ		 3876 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3877 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3878 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3879 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3880
57d104c1 3881 if (ret) {
53c12d0e
YG		 3882 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3883 __func__, ret);
3884 ret = ufshcd_link_recovery(hba);
ff8e20c6 3885 } else {
ee32c909
KK		 3886 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3887 POST_CHANGE);
ff8e20c6
DR		 3888 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3889 hba->ufs_stats.hibern8_exit_cnt++;
3890 }
57d104c1
SJ		 3891
3892 return ret;
3893}
3894
ad448378
AH		 3895static void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
3896{
3897 unsigned long flags;
3898
3899 if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) || !hba->ahit)
3900 return;
3901
3902 spin_lock_irqsave(hba->host->host_lock, flags);
3903 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3904 spin_unlock_irqrestore(hba->host->host_lock, flags);
3905}
3906
5064636c
YG		 3907 /**
3908 * ufshcd_init_pwr_info - setting the POR (power on reset)
3909 * values in hba power info
3910 * @hba: per-adapter instance
3911 */
3912static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3913{
3914 hba->pwr_info.gear_rx = UFS_PWM_G1;
3915 hba->pwr_info.gear_tx = UFS_PWM_G1;
3916 hba->pwr_info.lane_rx = 1;
3917 hba->pwr_info.lane_tx = 1;
3918 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3919 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3920 hba->pwr_info.hs_rate = 0;
3921}
3922
d3e89bac 3923/**
7eb584db
DR		 3924 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3925 * @hba: per-adapter instance
d3e89bac 3926 */
7eb584db 3927static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3928{
7eb584db
DR		 3929 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3930
3931 if (hba->max_pwr_info.is_valid)
3932 return 0;
3933
2349b533
SJ		 3934 pwr_info->pwr_tx = FAST_MODE;
3935 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3936 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3937
3938 /* Get the connected lane count */
7eb584db
DR		 3939 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3940 &pwr_info->lane_rx);
3941 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3942 &pwr_info->lane_tx);
3943
3944 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3945 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3946 __func__,
3947 pwr_info->lane_rx,
3948 pwr_info->lane_tx);
3949 return -EINVAL;
3950 }
d3e89bac
SJ		 3951
3952 /*
3953 * First, get the maximum gears of HS speed.
3954 * If a zero value, it means there is no HSGEAR capability.
3955 * Then, get the maximum gears of PWM speed.
3956 */
7eb584db
DR		 3957 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3958 if (!pwr_info->gear_rx) {
3959 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3960 &pwr_info->gear_rx);
3961 if (!pwr_info->gear_rx) {
3962 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3963 __func__, pwr_info->gear_rx);
3964 return -EINVAL;
3965 }
2349b533 3966 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3967 }
3968
7eb584db
DR		 3969 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3970 &pwr_info->gear_tx);
3971 if (!pwr_info->gear_tx) {
d3e89bac 3972 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3973 &pwr_info->gear_tx);
3974 if (!pwr_info->gear_tx) {
3975 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3976 __func__, pwr_info->gear_tx);
3977 return -EINVAL;
3978 }
2349b533 3979 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3980 }
3981
3982 hba->max_pwr_info.is_valid = true;
3983 return 0;
3984}
3985
3986static int ufshcd_change_power_mode(struct ufs_hba *hba,
3987 struct ufs_pa_layer_attr *pwr_mode)
3988{
3989 int ret;
3990
3991 /* if already configured to the requested pwr_mode */
3992 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3993 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3994 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3995 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
3996 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
3997 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
3998 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
3999 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4000 return 0;
d3e89bac
SJ		 4001 }
4002
4003 /*
4004 * Configure attributes for power mode change with below.
4005 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4006 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4007 * - PA_HSSERIES
4008 */
7eb584db
DR		 4009 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4010 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4011 pwr_mode->lane_rx);
4012 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4013 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4014 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4015 else
4016 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4017
7eb584db
DR		 4018 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4019 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4020 pwr_mode->lane_tx);
4021 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4022 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4023 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4024 else
4025 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4026
7eb584db
DR		 4027 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4028 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4029 pwr_mode->pwr_rx == FAST_MODE ||
4030 pwr_mode->pwr_tx == FAST_MODE)
4031 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4032 pwr_mode->hs_rate);
d3e89bac 4033
7eb584db
DR		 4034 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4035 | pwr_mode->pwr_tx);
4036
4037 if (ret) {
d3e89bac 4038 dev_err(hba->dev,
7eb584db
DR		 4039 "%s: power mode change failed %d\n", __func__, ret);
4040 } else {
0263bcd0
YG		 4041 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4042 pwr_mode);
7eb584db
DR		 4043
4044 memcpy(&hba->pwr_info, pwr_mode,
4045 sizeof(struct ufs_pa_layer_attr));
4046 }
4047
4048 return ret;
4049}
4050
4051/**
4052 * ufshcd_config_pwr_mode - configure a new power mode
4053 * @hba: per-adapter instance
4054 * @desired_pwr_mode: desired power configuration
4055 */
0d846e70 4056int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4057 struct ufs_pa_layer_attr *desired_pwr_mode)
4058{
4059 struct ufs_pa_layer_attr final_params = { 0 };
4060 int ret;
4061
0263bcd0
YG		 4062 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4063 desired_pwr_mode, &final_params);
4064
4065 if (ret)
7eb584db
DR		 4066 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4067
4068 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5
SJ		 4069 if (!ret)
4070 ufshcd_print_pwr_info(hba);
d3e89bac
SJ		 4071
4072 return ret;
4073}
0d846e70 4074EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4075
68078d5c
DR		 4076/**
4077 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4078 * @hba: per-adapter instance
68078d5c
DR		 4079 *
4080 * Set fDeviceInit flag and poll until device toggles it.
4081 */
4082static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4083{
dc3c8d3a
YG		 4084 int i;
4085 int err;
68078d5c
DR		 4086 bool flag_res = 1;
4087
dc3c8d3a
YG		 4088 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4089 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 4090 if (err) {
4091 dev_err(hba->dev,
4092 "%s setting fDeviceInit flag failed with error %d\n",
4093 __func__, err);
4094 goto out;
4095 }
4096
dc3c8d3a
YG		 4097 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4098 for (i = 0; i < 1000 && !err && flag_res; i++)
4099 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4100 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4101
68078d5c
DR		 4102 if (err)
4103 dev_err(hba->dev,
4104 "%s reading fDeviceInit flag failed with error %d\n",
4105 __func__, err);
4106 else if (flag_res)
4107 dev_err(hba->dev,
4108 "%s fDeviceInit was not cleared by the device\n",
4109 __func__);
4110
4111out:
4112 return err;
4113}
4114
7a3e97b0
SY		 4115/**
4116 * ufshcd_make_hba_operational - Make UFS controller operational
4117 * @hba: per adapter instance
4118 *
4119 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4120 * 1. Enable required interrupts
4121 * 2. Configure interrupt aggregation
897efe62 4122 * 3. Program UTRL and UTMRL base address
5c0c28a8 4123 * 4. Configure run-stop-registers
7a3e97b0
SY		 4124 *
4125 * Returns 0 on success, non-zero value on failure
4126 */
4127static int ufshcd_make_hba_operational(struct ufs_hba *hba)
4128{
4129 int err = 0;
4130 u32 reg;
4131
6ccf44fe
SJ		 4132 /* Enable required interrupts */
4133 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4134
4135 /* Configure interrupt aggregation */
b852190e
YG		 4136 if (ufshcd_is_intr_aggr_allowed(hba))
4137 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4138 else
4139 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4140
4141 /* Configure UTRL and UTMRL base address registers */
4142 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4143 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4144 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4145 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4146 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4147 REG_UTP_TASK_REQ_LIST_BASE_L);
4148 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4149 REG_UTP_TASK_REQ_LIST_BASE_H);
4150
897efe62
YG		 4151 /*
4152 * Make sure base address and interrupt setup are updated before
4153 * enabling the run/stop registers below.
4154 */
4155 wmb();
4156
7a3e97b0
SY		 4157 /*
4158 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4159 */
5c0c28a8 4160 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4161 if (!(ufshcd_get_lists_status(reg))) {
4162 ufshcd_enable_run_stop_reg(hba);
4163 } else {
3b1d0580 4164 dev_err(hba->dev,
7a3e97b0
SY		 4165 "Host controller not ready to process requests");
4166 err = -EIO;
4167 goto out;
4168 }
4169
7a3e97b0
SY		 4170out:
4171 return err;
4172}
4173
596585a2
YG		 4174/**
4175 * ufshcd_hba_stop - Send controller to reset state
4176 * @hba: per adapter instance
4177 * @can_sleep: perform sleep or just spin
4178 */
4179static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4180{
4181 int err;
4182
4183 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4184 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4185 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4186 10, 1, can_sleep);
4187 if (err)
4188 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4189}
4190
7a3e97b0 4191/**
4404c5de 4192 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4193 * @hba: per adapter instance
4194 *
4195 * The controller resets itself and controller firmware initialization
4196 * sequence kicks off. When controller is ready it will set
4197 * the Host Controller Enable bit to 1.
4198 *
4199 * Returns 0 on success, non-zero value on failure
4200 */
4404c5de 4201static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0
SY		 4202{
4203 int retry;
4204
4205 /*
4206 * msleep of 1 and 5 used in this function might result in msleep(20),
4207 * but it was necessary to send the UFS FPGA to reset mode during
4208 * development and testing of this driver. msleep can be changed to
4209 * mdelay and retry count can be reduced based on the controller.
4210 */
596585a2 4211 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4212 /* change controller state to "reset state" */
596585a2 4213 ufshcd_hba_stop(hba, true);
7a3e97b0 4214
57d104c1
SJ		 4215 /* UniPro link is disabled at this point */
4216 ufshcd_set_link_off(hba);
4217
0263bcd0 4218 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4219
7a3e97b0
SY		 4220 /* start controller initialization sequence */
4221 ufshcd_hba_start(hba);
4222
4223 /*
4224 * To initialize a UFS host controller HCE bit must be set to 1.
4225 * During initialization the HCE bit value changes from 1->0->1.
4226 * When the host controller completes initialization sequence
4227 * it sets the value of HCE bit to 1. The same HCE bit is read back
4228 * to check if the controller has completed initialization sequence.
4229 * So without this delay the value HCE = 1, set in the previous
4230 * instruction might be read back.
4231 * This delay can be changed based on the controller.
4232 */
4233 msleep(1);
4234
4235 /* wait for the host controller to complete initialization */
4236 retry = 10;
4237 while (ufshcd_is_hba_active(hba)) {
4238 if (retry) {
4239 retry--;
4240 } else {
3b1d0580 4241 dev_err(hba->dev,
7a3e97b0
SY		 4242 "Controller enable failed\n");
4243 return -EIO;
4244 }
4245 msleep(5);
4246 }
5c0c28a8 4247
1d337ec2 4248 /* enable UIC related interrupts */
57d104c1 4249 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4250
0263bcd0 4251 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4252
7a3e97b0
SY		 4253 return 0;
4254}
4255
4404c5de
AA		 4256static int ufshcd_hba_enable(struct ufs_hba *hba)
4257{
4258 int ret;
4259
4260 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4261 ufshcd_set_link_off(hba);
4262 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4263
4264 /* enable UIC related interrupts */
4265 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4266 ret = ufshcd_dme_reset(hba);
4267 if (!ret) {
4268 ret = ufshcd_dme_enable(hba);
4269 if (!ret)
4270 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4271 if (ret)
4272 dev_err(hba->dev,
4273 "Host controller enable failed with non-hce\n");
4274 }
4275 } else {
4276 ret = ufshcd_hba_execute_hce(hba);
4277 }
4278
4279 return ret;
4280}
7ca38cf3
YG		 4281static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4282{
4283 int tx_lanes, i, err = 0;
4284
4285 if (!peer)
4286 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4287 &tx_lanes);
4288 else
4289 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4290 &tx_lanes);
4291 for (i = 0; i < tx_lanes; i++) {
4292 if (!peer)
4293 err = ufshcd_dme_set(hba,
4294 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4295 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4296 0);
4297 else
4298 err = ufshcd_dme_peer_set(hba,
4299 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4300 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4301 0);
4302 if (err) {
4303 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4304 __func__, peer, i, err);
4305 break;
4306 }
4307 }
4308
4309 return err;
4310}
4311
4312static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4313{
4314 return ufshcd_disable_tx_lcc(hba, true);
4315}
4316
7a3e97b0 4317/**
6ccf44fe 4318 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4319 * @hba: per adapter instance
4320 *
6ccf44fe 4321 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4322 */
6ccf44fe 4323static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4324{
6ccf44fe 4325 int ret;
1d337ec2 4326 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4327 bool link_startup_again = false;
7a3e97b0 4328
7caf489b
SJ		 4329 /*
4330 * If UFS device isn't active then we will have to issue link startup
4331 * 2 times to make sure the device state move to active.
4332 */
4333 if (!ufshcd_is_ufs_dev_active(hba))
4334 link_startup_again = true;
7a3e97b0 4335
7caf489b 4336link_startup:
1d337ec2 4337 do {
0263bcd0 4338 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4339
1d337ec2 4340 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4341
1d337ec2
SRT		 4342 /* check if device is detected by inter-connect layer */
4343 if (!ret && !ufshcd_is_device_present(hba)) {
4344 dev_err(hba->dev, "%s: Device not present\n", __func__);
4345 ret = -ENXIO;
4346 goto out;
4347 }
6ccf44fe 4348
1d337ec2
SRT		 4349 /*
4350 * DME link lost indication is only received when link is up,
4351 * but we can't be sure if the link is up until link startup
4352 * succeeds. So reset the local Uni-Pro and try again.
4353 */
4354 if (ret && ufshcd_hba_enable(hba))
4355 goto out;
4356 } while (ret && retries--);
4357
4358 if (ret)
4359 /* failed to get the link up... retire */
5c0c28a8 4360 goto out;
5c0c28a8 4361
7caf489b
SJ		 4362 if (link_startup_again) {
4363 link_startup_again = false;
4364 retries = DME_LINKSTARTUP_RETRIES;
4365 goto link_startup;
4366 }
4367
d2aebb9b
SJ		 4368 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4369 ufshcd_init_pwr_info(hba);
4370 ufshcd_print_pwr_info(hba);
4371
7ca38cf3
YG		 4372 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4373 ret = ufshcd_disable_device_tx_lcc(hba);
4374 if (ret)
4375 goto out;
4376 }
4377
5c0c28a8 4378 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4379 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4380 if (ret)
4381 goto out;
7a3e97b0 4382
5c0c28a8 4383 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4384out:
7942f7b5 4385 if (ret) {
6ccf44fe 4386 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4387 ufshcd_print_host_state(hba);
4388 ufshcd_print_pwr_info(hba);
4389 ufshcd_print_host_regs(hba);
4390 }
6ccf44fe 4391 return ret;
7a3e97b0
SY		 4392}
4393
5a0b0cb9
SRT		 4394/**
4395 * ufshcd_verify_dev_init() - Verify device initialization
4396 * @hba: per-adapter instance
4397 *
4398 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4399 * device Transport Protocol (UTP) layer is ready after a reset.
4400 * If the UTP layer at the device side is not initialized, it may
4401 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4402 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4403 */
4404static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4405{
4406 int err = 0;
4407 int retries;
4408
1ab27c9c 4409 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4410 mutex_lock(&hba->dev_cmd.lock);
4411 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4412 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4413 NOP_OUT_TIMEOUT);
4414
4415 if (!err || err == -ETIMEDOUT)
4416 break;
4417
4418 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4419 }
4420 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4421 ufshcd_release(hba);
5a0b0cb9
SRT		 4422
4423 if (err)
4424 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4425 return err;
4426}
4427
0ce147d4
SJ		 4428/**
4429 * ufshcd_set_queue_depth - set lun queue depth
4430 * @sdev: pointer to SCSI device
4431 *
4432 * Read bLUQueueDepth value and activate scsi tagged command
4433 * queueing. For WLUN, queue depth is set to 1. For best-effort
4434 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4435 * value that host can queue.
4436 */
4437static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4438{
4439 int ret = 0;
4440 u8 lun_qdepth;
4441 struct ufs_hba *hba;
4442
4443 hba = shost_priv(sdev->host);
4444
4445 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4446 ret = ufshcd_read_unit_desc_param(hba,
4447 ufshcd_scsi_to_upiu_lun(sdev->lun),
4448 UNIT_DESC_PARAM_LU_Q_DEPTH,
4449 &lun_qdepth,
4450 sizeof(lun_qdepth));
0ce147d4
SJ		 4451
4452 /* Some WLUN doesn't support unit descriptor */
4453 if (ret == -EOPNOTSUPP)
4454 lun_qdepth = 1;
4455 else if (!lun_qdepth)
4456 /* eventually, we can figure out the real queue depth */
4457 lun_qdepth = hba->nutrs;
4458 else
4459 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4460
4461 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4462 __func__, lun_qdepth);
db5ed4df 4463 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4464}
4465
57d104c1
SJ		 4466/*
4467 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4468 * @hba: per-adapter instance
4469 * @lun: UFS device lun id
4470 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4471 *
4472 * Returns 0 in case of success and b_lu_write_protect status would be returned
4473 * @b_lu_write_protect parameter.
4474 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4475 * Returns -EINVAL in case of invalid parameters passed to this function.
4476 */
4477static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4478 u8 lun,
4479 u8 *b_lu_write_protect)
4480{
4481 int ret;
4482
4483 if (!b_lu_write_protect)
4484 ret = -EINVAL;
4485 /*
4486 * According to UFS device spec, RPMB LU can't be write
4487 * protected so skip reading bLUWriteProtect parameter for
4488 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4489 */
4490 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4491 ret = -ENOTSUPP;
4492 else
4493 ret = ufshcd_read_unit_desc_param(hba,
4494 lun,
4495 UNIT_DESC_PARAM_LU_WR_PROTECT,
4496 b_lu_write_protect,
4497 sizeof(*b_lu_write_protect));
4498 return ret;
4499}
4500
4501/**
4502 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4503 * status
4504 * @hba: per-adapter instance
4505 * @sdev: pointer to SCSI device
4506 *
4507 */
4508static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4509 struct scsi_device *sdev)
4510{
4511 if (hba->dev_info.f_power_on_wp_en &&
4512 !hba->dev_info.is_lu_power_on_wp) {
4513 u8 b_lu_write_protect;
4514
4515 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4516 &b_lu_write_protect) &&
4517 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4518 hba->dev_info.is_lu_power_on_wp = true;
4519 }
4520}
4521
7a3e97b0
SY		 4522/**
4523 * ufshcd_slave_alloc - handle initial SCSI device configurations
4524 * @sdev: pointer to SCSI device
4525 *
4526 * Returns success
4527 */
4528static int ufshcd_slave_alloc(struct scsi_device *sdev)
4529{
4530 struct ufs_hba *hba;
4531
4532 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4533
4534 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4535 sdev->use_10_for_ms = 1;
7a3e97b0 4536
e8e7f271
SRT		 4537 /* allow SCSI layer to restart the device in case of errors */
4538 sdev->allow_restart = 1;
4264fd61 4539
b2a6c522
SRT		 4540 /* REPORT SUPPORTED OPERATION CODES is not supported */
4541 sdev->no_report_opcodes = 1;
4542
84af7e8b
SRT		 4543 /* WRITE_SAME command is not supported */
4544 sdev->no_write_same = 1;
e8e7f271 4545
0ce147d4 4546 ufshcd_set_queue_depth(sdev);
4264fd61 4547
57d104c1
SJ		 4548 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4549
7a3e97b0
SY		 4550 return 0;
4551}
4552
4264fd61
SRT		 4553/**
4554 * ufshcd_change_queue_depth - change queue depth
4555 * @sdev: pointer to SCSI device
4556 * @depth: required depth to set
4264fd61 4557 *
db5ed4df 4558 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4559 */
db5ed4df 4560static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4561{
4562 struct ufs_hba *hba = shost_priv(sdev->host);
4563
4564 if (depth > hba->nutrs)
4565 depth = hba->nutrs;
db5ed4df 4566 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4567}
4568
eeda4749
AM		 4569/**
4570 * ufshcd_slave_configure - adjust SCSI device configurations
4571 * @sdev: pointer to SCSI device
4572 */
4573static int ufshcd_slave_configure(struct scsi_device *sdev)
4574{
4575 struct request_queue *q = sdev->request_queue;
4576
4577 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4578 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4579
4580 return 0;
4581}
4582
7a3e97b0
SY		 4583/**
4584 * ufshcd_slave_destroy - remove SCSI device configurations
4585 * @sdev: pointer to SCSI device
4586 */
4587static void ufshcd_slave_destroy(struct scsi_device *sdev)
4588{
4589 struct ufs_hba *hba;
4590
4591 hba = shost_priv(sdev->host);
0ce147d4 4592 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4593 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4594 unsigned long flags;
4595
4596 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4597 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4598 spin_unlock_irqrestore(hba->host->host_lock, flags);
4599 }
7a3e97b0
SY		 4600}
4601
4602/**
4603 * ufshcd_task_req_compl - handle task management request completion
4604 * @hba: per adapter instance
4605 * @index: index of the completed request
e2933132 4606 * @resp: task management service response
7a3e97b0 4607 *
e2933132 4608 * Returns non-zero value on error, zero on success
7a3e97b0 4609 */
e2933132 4610static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 4611{
4612 struct utp_task_req_desc *task_req_descp;
4613 struct utp_upiu_task_rsp *task_rsp_upiup;
4614 unsigned long flags;
4615 int ocs_value;
4616 int task_result;
4617
4618 spin_lock_irqsave(hba->host->host_lock, flags);
4619
4620 /* Clear completed tasks from outstanding_tasks */
4621 __clear_bit(index, &hba->outstanding_tasks);
4622
4623 task_req_descp = hba->utmrdl_base_addr;
4624 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
4625
4626 if (ocs_value == OCS_SUCCESS) {
4627 task_rsp_upiup = (struct utp_upiu_task_rsp *)
4628 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 4629 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
4630 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 4631 if (resp)
4632 *resp = (u8)task_result;
7a3e97b0 4633 } else {
e2933132
SRT		 4634 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
4635 __func__, ocs_value);
7a3e97b0
SY		 4636 }
4637 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 4638
4639 return ocs_value;
7a3e97b0
SY		 4640}
4641
7a3e97b0
SY		 4642/**
4643 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 4644 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4645 * @scsi_status: SCSI command status
4646 *
4647 * Returns value base on SCSI command status
4648 */
4649static inline int
4650ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4651{
4652 int result = 0;
4653
4654 switch (scsi_status) {
7a3e97b0 4655 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 4656 ufshcd_copy_sense_data(lrbp);
4657 case SAM_STAT_GOOD:
7a3e97b0
SY		 4658 result |= DID_OK << 16 |
4659 COMMAND_COMPLETE << 8 |
1c2623c5 4660 scsi_status;
7a3e97b0
SY		 4661 break;
4662 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4663 case SAM_STAT_BUSY:
7a3e97b0 4664 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4665 ufshcd_copy_sense_data(lrbp);
4666 result |= scsi_status;
7a3e97b0
SY		 4667 break;
4668 default:
4669 result |= DID_ERROR << 16;
4670 break;
4671 } /* end of switch */
4672
4673 return result;
4674}
4675
4676/**
4677 * ufshcd_transfer_rsp_status - Get overall status of the response
4678 * @hba: per adapter instance
8aa29f19 4679 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 4680 *
4681 * Returns result of the command to notify SCSI midlayer
4682 */
4683static inline int
4684ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4685{
4686 int result = 0;
4687 int scsi_status;
4688 int ocs;
4689
4690 /* overall command status of utrd */
4691 ocs = ufshcd_get_tr_ocs(lrbp);
4692
4693 switch (ocs) {
4694 case OCS_SUCCESS:
5a0b0cb9 4695 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4696 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4697 switch (result) {
4698 case UPIU_TRANSACTION_RESPONSE:
4699 /*
4700 * get the response UPIU result to extract
4701 * the SCSI command status
4702 */
4703 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4704
4705 /*
4706 * get the result based on SCSI status response
4707 * to notify the SCSI midlayer of the command status
4708 */
4709 scsi_status = result & MASK_SCSI_STATUS;
4710 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4711
f05ac2e5
YG		 4712 /*
4713 * Currently we are only supporting BKOPs exception
4714 * events hence we can ignore BKOPs exception event
4715 * during power management callbacks. BKOPs exception
4716 * event is not expected to be raised in runtime suspend
4717 * callback as it allows the urgent bkops.
4718 * During system suspend, we are anyway forcefully
4719 * disabling the bkops and if urgent bkops is needed
4720 * it will be enabled on system resume. Long term
4721 * solution could be to abort the system suspend if
4722 * UFS device needs urgent BKOPs.
4723 */
4724 if (!hba->pm_op_in_progress &&
4725 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 4726 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 4727 break;
4728 case UPIU_TRANSACTION_REJECT_UPIU:
4729 /* TODO: handle Reject UPIU Response */
4730 result = DID_ERROR << 16;
3b1d0580 4731 dev_err(hba->dev,
5a0b0cb9
SRT		 4732 "Reject UPIU not fully implemented\n");
4733 break;
4734 default:
4735 result = DID_ERROR << 16;
4736 dev_err(hba->dev,
4737 "Unexpected request response code = %x\n",
4738 result);
7a3e97b0
SY		 4739 break;
4740 }
7a3e97b0
SY		 4741 break;
4742 case OCS_ABORTED:
4743 result |= DID_ABORT << 16;
4744 break;
e8e7f271
SRT		 4745 case OCS_INVALID_COMMAND_STATUS:
4746 result |= DID_REQUEUE << 16;
4747 break;
7a3e97b0
SY		 4748 case OCS_INVALID_CMD_TABLE_ATTR:
4749 case OCS_INVALID_PRDT_ATTR:
4750 case OCS_MISMATCH_DATA_BUF_SIZE:
4751 case OCS_MISMATCH_RESP_UPIU_SIZE:
4752 case OCS_PEER_COMM_FAILURE:
4753 case OCS_FATAL_ERROR:
4754 default:
4755 result |= DID_ERROR << 16;
3b1d0580 4756 dev_err(hba->dev,
ff8e20c6
DR		 4757 "OCS error from controller = %x for tag %d\n",
4758 ocs, lrbp->task_tag);
4759 ufshcd_print_host_regs(hba);
6ba65588 4760 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4761 break;
4762 } /* end of switch */
4763
66cc820f
DR		 4764 if (host_byte(result) != DID_OK)
4765 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4766 return result;
4767}
4768
6ccf44fe
SJ		 4769/**
4770 * ufshcd_uic_cmd_compl - handle completion of uic command
4771 * @hba: per adapter instance
53b3d9c3 4772 * @intr_status: interrupt status generated by the controller
6ccf44fe 4773 */
53b3d9c3 4774static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4775{
53b3d9c3 4776 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4777 hba->active_uic_cmd->argument2 |=
4778 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4779 hba->active_uic_cmd->argument3 =
4780 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 4781 complete(&hba->active_uic_cmd->done);
4782 }
53b3d9c3 4783
57d104c1
SJ		 4784 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4785 complete(hba->uic_async_done);
6ccf44fe
SJ		 4786}
4787
7a3e97b0 4788/**
9a47ec7c 4789 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4790 * @hba: per adapter instance
9a47ec7c 4791 * @completed_reqs: requests to complete
7a3e97b0 4792 */
9a47ec7c
YG		 4793static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4794 unsigned long completed_reqs)
7a3e97b0 4795{
5a0b0cb9
SRT		 4796 struct ufshcd_lrb *lrbp;
4797 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4798 int result;
4799 int index;
e9d501b1 4800
e9d501b1
DR		 4801 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4802 lrbp = &hba->lrb[index];
4803 cmd = lrbp->cmd;
4804 if (cmd) {
1a07f2d9 4805 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4806 result = ufshcd_transfer_rsp_status(hba, lrbp);
4807 scsi_dma_unmap(cmd);
4808 cmd->result = result;
4809 /* Mark completed command as NULL in LRB */
4810 lrbp->cmd = NULL;
4811 clear_bit_unlock(index, &hba->lrb_in_use);
4812 /* Do not touch lrbp after scsi done */
4813 cmd->scsi_done(cmd);
1ab27c9c 4814 __ufshcd_release(hba);
300bb13f
JP		 4815 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4816 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 4817 if (hba->dev_cmd.complete) {
4818 ufshcd_add_command_trace(hba, index,
4819 "dev_complete");
e9d501b1 4820 complete(hba->dev_cmd.complete);
1a07f2d9 4821 }
e9d501b1 4822 }
401f1e44
SJ		 4823 if (ufshcd_is_clkscaling_supported(hba))
4824 hba->clk_scaling.active_reqs--;
09017188
ZL		 4825
4826 lrbp->compl_time_stamp = ktime_get();
e9d501b1 4827 }
7a3e97b0
SY		 4828
4829 /* clear corresponding bits of completed commands */
4830 hba->outstanding_reqs ^= completed_reqs;
4831
856b3483
ST		 4832 ufshcd_clk_scaling_update_busy(hba);
4833
5a0b0cb9
SRT		 4834 /* we might have free'd some tags above */
4835 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 4836}
4837
9a47ec7c
YG		 4838/**
4839 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4840 * @hba: per adapter instance
4841 */
4842static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4843{
4844 unsigned long completed_reqs;
4845 u32 tr_doorbell;
4846
4847 /* Resetting interrupt aggregation counters first and reading the
4848 * DOOR_BELL afterward allows us to handle all the completed requests.
4849 * In order to prevent other interrupts starvation the DB is read once
4850 * after reset. The down side of this solution is the possibility of
4851 * false interrupt if device completes another request after resetting
4852 * aggregation and before reading the DB.
4853 */
5ac6abc9
AA		 4854 if (ufshcd_is_intr_aggr_allowed(hba) &&
4855 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 4856 ufshcd_reset_intr_aggr(hba);
4857
4858 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4859 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4860
4861 __ufshcd_transfer_req_compl(hba, completed_reqs);
4862}
4863
66ec6d59
SRT		 4864/**
4865 * ufshcd_disable_ee - disable exception event
4866 * @hba: per-adapter instance
4867 * @mask: exception event to disable
4868 *
4869 * Disables exception event in the device so that the EVENT_ALERT
4870 * bit is not set.
4871 *
4872 * Returns zero on success, non-zero error value on failure.
4873 */
4874static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4875{
4876 int err = 0;
4877 u32 val;
4878
4879 if (!(hba->ee_ctrl_mask & mask))
4880 goto out;
4881
4882 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4883 val &= MASK_EE_STATUS;
5e86ae44 4884 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4885 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4886 if (!err)
4887 hba->ee_ctrl_mask &= ~mask;
4888out:
4889 return err;
4890}
4891
4892/**
4893 * ufshcd_enable_ee - enable exception event
4894 * @hba: per-adapter instance
4895 * @mask: exception event to enable
4896 *
4897 * Enable corresponding exception event in the device to allow
4898 * device to alert host in critical scenarios.
4899 *
4900 * Returns zero on success, non-zero error value on failure.
4901 */
4902static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4903{
4904 int err = 0;
4905 u32 val;
4906
4907 if (hba->ee_ctrl_mask & mask)
4908 goto out;
4909
4910 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4911 val &= MASK_EE_STATUS;
5e86ae44 4912 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4913 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4914 if (!err)
4915 hba->ee_ctrl_mask |= mask;
4916out:
4917 return err;
4918}
4919
4920/**
4921 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4922 * @hba: per-adapter instance
4923 *
4924 * Allow device to manage background operations on its own. Enabling
4925 * this might lead to inconsistent latencies during normal data transfers
4926 * as the device is allowed to manage its own way of handling background
4927 * operations.
4928 *
4929 * Returns zero on success, non-zero on failure.
4930 */
4931static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4932{
4933 int err = 0;
4934
4935 if (hba->auto_bkops_enabled)
4936 goto out;
4937
dc3c8d3a 4938 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4939 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4940 if (err) {
4941 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4942 __func__, err);
4943 goto out;
4944 }
4945
4946 hba->auto_bkops_enabled = true;
7ff5ab47 4947 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4948
4949 /* No need of URGENT_BKOPS exception from the device */
4950 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4951 if (err)
4952 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4953 __func__, err);
4954out:
4955 return err;
4956}
4957
4958/**
4959 * ufshcd_disable_auto_bkops - block device in doing background operations
4960 * @hba: per-adapter instance
4961 *
4962 * Disabling background operations improves command response latency but
4963 * has drawback of device moving into critical state where the device is
4964 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4965 * host is idle so that BKOPS are managed effectively without any negative
4966 * impacts.
4967 *
4968 * Returns zero on success, non-zero on failure.
4969 */
4970static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4971{
4972 int err = 0;
4973
4974 if (!hba->auto_bkops_enabled)
4975 goto out;
4976
4977 /*
4978 * If host assisted BKOPs is to be enabled, make sure
4979 * urgent bkops exception is allowed.
4980 */
4981 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4982 if (err) {
4983 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4984 __func__, err);
4985 goto out;
4986 }
4987
dc3c8d3a 4988 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 4989 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4990 if (err) {
4991 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4992 __func__, err);
4993 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4994 goto out;
4995 }
4996
4997 hba->auto_bkops_enabled = false;
7ff5ab47 4998 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 4999out:
5000 return err;
5001}
5002
5003/**
4e768e76 5004 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5005 * @hba: per adapter instance
5006 *
5007 * After a device reset the device may toggle the BKOPS_EN flag
5008 * to default value. The s/w tracking variables should be updated
4e768e76
SJ		 5009 * as well. This function would change the auto-bkops state based on
5010 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5011 */
4e768e76 5012static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5013{
4e768e76
SJ		 5014 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5015 hba->auto_bkops_enabled = false;
5016 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5017 ufshcd_enable_auto_bkops(hba);
5018 } else {
5019 hba->auto_bkops_enabled = true;
5020 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5021 ufshcd_disable_auto_bkops(hba);
5022 }
66ec6d59
SRT		 5023}
5024
5025static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5026{
5e86ae44 5027 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5028 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5029}
5030
5031/**
57d104c1 5032 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5033 * @hba: per-adapter instance
57d104c1 5034 * @status: bkops_status value
66ec6d59 5035 *
57d104c1
SJ		 5036 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5037 * flag in the device to permit background operations if the device
5038 * bkops_status is greater than or equal to "status" argument passed to
5039 * this function, disable otherwise.
5040 *
5041 * Returns 0 for success, non-zero in case of failure.
5042 *
5043 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5044 * to know whether auto bkops is enabled or disabled after this function
5045 * returns control to it.
66ec6d59 5046 */
57d104c1
SJ		 5047static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5048 enum bkops_status status)
66ec6d59
SRT		 5049{
5050 int err;
57d104c1 5051 u32 curr_status = 0;
66ec6d59 5052
57d104c1 5053 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5054 if (err) {
5055 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5056 __func__, err);
5057 goto out;
57d104c1
SJ		 5058 } else if (curr_status > BKOPS_STATUS_MAX) {
5059 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5060 __func__, curr_status);
5061 err = -EINVAL;
5062 goto out;
66ec6d59
SRT		 5063 }
5064
57d104c1 5065 if (curr_status >= status)
66ec6d59 5066 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5067 else
5068 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5069out:
5070 return err;
5071}
5072
57d104c1
SJ		 5073/**
5074 * ufshcd_urgent_bkops - handle urgent bkops exception event
5075 * @hba: per-adapter instance
5076 *
5077 * Enable fBackgroundOpsEn flag in the device to permit background
5078 * operations.
5079 *
5080 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5081 * and negative error value for any other failure.
5082 */
5083static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5084{
afdfff59 5085 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5086}
5087
66ec6d59
SRT		 5088static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5089{
5e86ae44 5090 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5091 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5092}
5093
afdfff59
YG		 5094static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5095{
5096 int err;
5097 u32 curr_status = 0;
5098
5099 if (hba->is_urgent_bkops_lvl_checked)
5100 goto enable_auto_bkops;
5101
5102 err = ufshcd_get_bkops_status(hba, &curr_status);
5103 if (err) {
5104 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5105 __func__, err);
5106 goto out;
5107 }
5108
5109 /*
5110 * We are seeing that some devices are raising the urgent bkops
5111 * exception events even when BKOPS status doesn't indicate performace
5112 * impacted or critical. Handle these device by determining their urgent
5113 * bkops status at runtime.
5114 */
5115 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5116 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5117 __func__, curr_status);
5118 /* update the current status as the urgent bkops level */
5119 hba->urgent_bkops_lvl = curr_status;
5120 hba->is_urgent_bkops_lvl_checked = true;
5121 }
5122
5123enable_auto_bkops:
5124 err = ufshcd_enable_auto_bkops(hba);
5125out:
5126 if (err < 0)
5127 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5128 __func__, err);
5129}
5130
66ec6d59
SRT		 5131/**
5132 * ufshcd_exception_event_handler - handle exceptions raised by device
5133 * @work: pointer to work data
5134 *
5135 * Read bExceptionEventStatus attribute from the device and handle the
5136 * exception event accordingly.
5137 */
5138static void ufshcd_exception_event_handler(struct work_struct *work)
5139{
5140 struct ufs_hba *hba;
5141 int err;
5142 u32 status = 0;
5143 hba = container_of(work, struct ufs_hba, eeh_work);
5144
62694735 5145 pm_runtime_get_sync(hba->dev);
2e3611e9 5146 scsi_block_requests(hba->host);
66ec6d59
SRT		 5147 err = ufshcd_get_ee_status(hba, &status);
5148 if (err) {
5149 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5150 __func__, err);
5151 goto out;
5152 }
5153
5154 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5155
5156 if (status & MASK_EE_URGENT_BKOPS)
5157 ufshcd_bkops_exception_event_handler(hba);
5158
66ec6d59 5159out:
2e3611e9 5160 scsi_unblock_requests(hba->host);
62694735 5161 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 5162 return;
5163}
5164
9a47ec7c
YG		 5165/* Complete requests that have door-bell cleared */
5166static void ufshcd_complete_requests(struct ufs_hba *hba)
5167{
5168 ufshcd_transfer_req_compl(hba);
5169 ufshcd_tmc_handler(hba);
5170}
5171
583fa62d
YG		 5172/**
5173 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5174 * to recover from the DL NAC errors or not.
5175 * @hba: per-adapter instance
5176 *
5177 * Returns true if error handling is required, false otherwise
5178 */
5179static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5180{
5181 unsigned long flags;
5182 bool err_handling = true;
5183
5184 spin_lock_irqsave(hba->host->host_lock, flags);
5185 /*
5186 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5187 * device fatal error and/or DL NAC & REPLAY timeout errors.
5188 */
5189 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5190 goto out;
5191
5192 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5193 ((hba->saved_err & UIC_ERROR) &&
5194 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5195 goto out;
5196
5197 if ((hba->saved_err & UIC_ERROR) &&
5198 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5199 int err;
5200 /*
5201 * wait for 50ms to see if we can get any other errors or not.
5202 */
5203 spin_unlock_irqrestore(hba->host->host_lock, flags);
5204 msleep(50);
5205 spin_lock_irqsave(hba->host->host_lock, flags);
5206
5207 /*
5208 * now check if we have got any other severe errors other than
5209 * DL NAC error?
5210 */
5211 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5212 ((hba->saved_err & UIC_ERROR) &&
5213 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5214 goto out;
5215
5216 /*
5217 * As DL NAC is the only error received so far, send out NOP
5218 * command to confirm if link is still active or not.
5219 * - If we don't get any response then do error recovery.
5220 * - If we get response then clear the DL NAC error bit.
5221 */
5222
5223 spin_unlock_irqrestore(hba->host->host_lock, flags);
5224 err = ufshcd_verify_dev_init(hba);
5225 spin_lock_irqsave(hba->host->host_lock, flags);
5226
5227 if (err)
5228 goto out;
5229
5230 /* Link seems to be alive hence ignore the DL NAC errors */
5231 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5232 hba->saved_err &= ~UIC_ERROR;
5233 /* clear NAC error */
5234 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5235 if (!hba->saved_uic_err) {
5236 err_handling = false;
5237 goto out;
5238 }
5239 }
5240out:
5241 spin_unlock_irqrestore(hba->host->host_lock, flags);
5242 return err_handling;
5243}
5244
7a3e97b0 5245/**
e8e7f271
SRT		 5246 * ufshcd_err_handler - handle UFS errors that require s/w attention
5247 * @work: pointer to work structure
7a3e97b0 5248 */
e8e7f271 5249static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5250{
5251 struct ufs_hba *hba;
e8e7f271
SRT		 5252 unsigned long flags;
5253 u32 err_xfer = 0;
5254 u32 err_tm = 0;
5255 int err = 0;
5256 int tag;
9a47ec7c 5257 bool needs_reset = false;
e8e7f271
SRT		 5258
5259 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5260
62694735 5261 pm_runtime_get_sync(hba->dev);
1ab27c9c 5262 ufshcd_hold(hba, false);
e8e7f271
SRT		 5263
5264 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5265 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5266 goto out;
e8e7f271
SRT		 5267
5268 hba->ufshcd_state = UFSHCD_STATE_RESET;
5269 ufshcd_set_eh_in_progress(hba);
5270
5271 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5272 ufshcd_complete_requests(hba);
583fa62d
YG		 5273
5274 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5275 bool ret;
5276
5277 spin_unlock_irqrestore(hba->host->host_lock, flags);
5278 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5279 ret = ufshcd_quirk_dl_nac_errors(hba);
5280 spin_lock_irqsave(hba->host->host_lock, flags);
5281 if (!ret)
5282 goto skip_err_handling;
5283 }
9a47ec7c
YG		 5284 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5285 ((hba->saved_err & UIC_ERROR) &&
5286 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5287 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5288 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5289 needs_reset = true;
e8e7f271 5290
9a47ec7c
YG		 5291 /*
5292 * if host reset is required then skip clearing the pending
5293 * transfers forcefully because they will automatically get
5294 * cleared after link startup.
5295 */
5296 if (needs_reset)
5297 goto skip_pending_xfer_clear;
5298
5299 /* release lock as clear command might sleep */
5300 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5301 /* Clear pending transfer requests */
9a47ec7c
YG		 5302 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5303 if (ufshcd_clear_cmd(hba, tag)) {
5304 err_xfer = true;
5305 goto lock_skip_pending_xfer_clear;
5306 }
5307 }
e8e7f271
SRT		 5308
5309 /* Clear pending task management requests */
9a47ec7c
YG		 5310 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5311 if (ufshcd_clear_tm_cmd(hba, tag)) {
5312 err_tm = true;
5313 goto lock_skip_pending_xfer_clear;
5314 }
5315 }
e8e7f271 5316
9a47ec7c 5317lock_skip_pending_xfer_clear:
e8e7f271 5318 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5319
9a47ec7c
YG		 5320 /* Complete the requests that are cleared by s/w */
5321 ufshcd_complete_requests(hba);
5322
5323 if (err_xfer || err_tm)
5324 needs_reset = true;
5325
5326skip_pending_xfer_clear:
e8e7f271 5327 /* Fatal errors need reset */
9a47ec7c
YG		 5328 if (needs_reset) {
5329 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5330
5331 /*
5332 * ufshcd_reset_and_restore() does the link reinitialization
5333 * which will need atleast one empty doorbell slot to send the
5334 * device management commands (NOP and query commands).
5335 * If there is no slot empty at this moment then free up last
5336 * slot forcefully.
5337 */
5338 if (hba->outstanding_reqs == max_doorbells)
5339 __ufshcd_transfer_req_compl(hba,
5340 (1UL << (hba->nutrs - 1)));
5341
5342 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5343 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5344 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5345 if (err) {
5346 dev_err(hba->dev, "%s: reset and restore failed\n",
5347 __func__);
5348 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5349 }
5350 /*
5351 * Inform scsi mid-layer that we did reset and allow to handle
5352 * Unit Attention properly.
5353 */
5354 scsi_report_bus_reset(hba->host, 0);
5355 hba->saved_err = 0;
5356 hba->saved_uic_err = 0;
5357 }
9a47ec7c 5358
583fa62d 5359skip_err_handling:
9a47ec7c
YG		 5360 if (!needs_reset) {
5361 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5362 if (hba->saved_err || hba->saved_uic_err)
5363 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5364 __func__, hba->saved_err, hba->saved_uic_err);
5365 }
5366
e8e7f271
SRT		 5367 ufshcd_clear_eh_in_progress(hba);
5368
5369out:
9a47ec7c 5370 spin_unlock_irqrestore(hba->host->host_lock, flags);
38135535 5371 ufshcd_scsi_unblock_requests(hba);
1ab27c9c 5372 ufshcd_release(hba);
62694735 5373 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5374}
5375
ff8e20c6
DR		 5376static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5377 u32 reg)
5378{
5379 reg_hist->reg[reg_hist->pos] = reg;
5380 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5381 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5382}
5383
7a3e97b0 5384/**
e8e7f271
SRT		 5385 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5386 * @hba: per-adapter instance
7a3e97b0 5387 */
e8e7f271 5388static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5389{
5390 u32 reg;
5391
fb7b45f0
DR		 5392 /* PHY layer lane error */
5393 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5394 /* Ignore LINERESET indication, as this is not an error */
5395 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5396 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5397 /*
5398 * To know whether this error is fatal or not, DB timeout
5399 * must be checked but this error is handled separately.
5400 */
5401 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR		 5402 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5403 }
fb7b45f0 5404
e8e7f271
SRT		 5405 /* PA_INIT_ERROR is fatal and needs UIC reset */
5406 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR		 5407 if (reg)
5408 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5409
e8e7f271
SRT		 5410 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5411 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 5412 else if (hba->dev_quirks &
5413 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5414 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5415 hba->uic_error |=
5416 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5417 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5418 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5419 }
e8e7f271
SRT		 5420
5421 /* UIC NL/TL/DME errors needs software retry */
5422 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR		 5423 if (reg) {
5424 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5425 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5426 }
e8e7f271
SRT		 5427
5428 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR		 5429 if (reg) {
5430 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5431 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5432 }
e8e7f271
SRT		 5433
5434 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR		 5435 if (reg) {
5436 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5437 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5438 }
e8e7f271
SRT		 5439
5440 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5441 __func__, hba->uic_error);
5442}
5443
5444/**
5445 * ufshcd_check_errors - Check for errors that need s/w attention
5446 * @hba: per-adapter instance
5447 */
5448static void ufshcd_check_errors(struct ufs_hba *hba)
5449{
5450 bool queue_eh_work = false;
5451
7a3e97b0 5452 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5453 queue_eh_work = true;
7a3e97b0
SY		 5454
5455 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 5456 hba->uic_error = 0;
5457 ufshcd_update_uic_error(hba);
5458 if (hba->uic_error)
5459 queue_eh_work = true;
7a3e97b0 5460 }
e8e7f271
SRT		 5461
5462 if (queue_eh_work) {
9a47ec7c
YG		 5463 /*
5464 * update the transfer error masks to sticky bits, let's do this
5465 * irrespective of current ufshcd_state.
5466 */
5467 hba->saved_err |= hba->errors;
5468 hba->saved_uic_err |= hba->uic_error;
5469
e8e7f271
SRT		 5470 /* handle fatal errors only when link is functional */
5471 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5472 /* block commands from scsi mid-layer */
38135535 5473 ufshcd_scsi_block_requests(hba);
e8e7f271 5474
141f8165 5475 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5476
5477 /* dump controller state before resetting */
5478 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5479 bool pr_prdt = !!(hba->saved_err &
5480 SYSTEM_BUS_FATAL_ERROR);
5481
5482 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5483 __func__, hba->saved_err,
5484 hba->saved_uic_err);
5485
5486 ufshcd_print_host_regs(hba);
5487 ufshcd_print_pwr_info(hba);
5488 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5489 ufshcd_print_trs(hba, hba->outstanding_reqs,
5490 pr_prdt);
5491 }
e8e7f271
SRT		 5492 schedule_work(&hba->eh_work);
5493 }
3441da7d 5494 }
e8e7f271
SRT		 5495 /*
5496 * if (!queue_eh_work) -
5497 * Other errors are either non-fatal where host recovers
5498 * itself without s/w intervention or errors that will be
5499 * handled by the SCSI core layer.
5500 */
7a3e97b0
SY		 5501}
5502
5503/**
5504 * ufshcd_tmc_handler - handle task management function completion
5505 * @hba: per adapter instance
5506 */
5507static void ufshcd_tmc_handler(struct ufs_hba *hba)
5508{
5509 u32 tm_doorbell;
5510
b873a275 5511 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5512 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 5513 wake_up(&hba->tm_wq);
7a3e97b0
SY		 5514}
5515
5516/**
5517 * ufshcd_sl_intr - Interrupt service routine
5518 * @hba: per adapter instance
5519 * @intr_status: contains interrupts generated by the controller
5520 */
5521static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5522{
5523 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5524 if (hba->errors)
e8e7f271 5525 ufshcd_check_errors(hba);
7a3e97b0 5526
53b3d9c3
SJ		 5527 if (intr_status & UFSHCD_UIC_MASK)
5528 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5529
5530 if (intr_status & UTP_TASK_REQ_COMPL)
5531 ufshcd_tmc_handler(hba);
5532
5533 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5534 ufshcd_transfer_req_compl(hba);
5535}
5536
5537/**
5538 * ufshcd_intr - Main interrupt service routine
5539 * @irq: irq number
5540 * @__hba: pointer to adapter instance
5541 *
5542 * Returns IRQ_HANDLED - If interrupt is valid
5543 * IRQ_NONE - If invalid interrupt
5544 */
5545static irqreturn_t ufshcd_intr(int irq, void *__hba)
5546{
d75f7fe4 5547 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5548 irqreturn_t retval = IRQ_NONE;
5549 struct ufs_hba *hba = __hba;
7f6ba4f1 5550 int retries = hba->nutrs;
7a3e97b0
SY		 5551
5552 spin_lock(hba->host->host_lock);
b873a275 5553 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0 5554
7f6ba4f1
VG		 5555 /*
5556 * There could be max of hba->nutrs reqs in flight and in worst case
5557 * if the reqs get finished 1 by 1 after the interrupt status is
5558 * read, make sure we handle them by checking the interrupt status
5559 * again in a loop until we process all of the reqs before returning.
5560 */
5561 do {
5562 enabled_intr_status =
5563 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5564 if (intr_status)
5565 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
5566 if (enabled_intr_status) {
5567 ufshcd_sl_intr(hba, enabled_intr_status);
5568 retval = IRQ_HANDLED;
5569 }
5570
5571 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5572 } while (intr_status && --retries);
d75f7fe4 5573
7a3e97b0
SY		 5574 spin_unlock(hba->host->host_lock);
5575 return retval;
5576}
5577
e2933132
SRT		 5578static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5579{
5580 int err = 0;
5581 u32 mask = 1 << tag;
5582 unsigned long flags;
5583
5584 if (!test_bit(tag, &hba->outstanding_tasks))
5585 goto out;
5586
5587 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 5588 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5589 spin_unlock_irqrestore(hba->host->host_lock, flags);
5590
5591 /* poll for max. 1 sec to clear door bell register by h/w */
5592 err = ufshcd_wait_for_register(hba,
5593 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5594 mask, 0, 1000, 1000, true);
e2933132
SRT		 5595out:
5596 return err;
5597}
5598
7a3e97b0
SY		 5599/**
5600 * ufshcd_issue_tm_cmd - issues task management commands to controller
5601 * @hba: per adapter instance
e2933132
SRT		 5602 * @lun_id: LUN ID to which TM command is sent
5603 * @task_id: task ID to which the TM command is applicable
5604 * @tm_function: task management function opcode
5605 * @tm_response: task management service response return value
7a3e97b0 5606 *
e2933132 5607 * Returns non-zero value on error, zero on success.
7a3e97b0 5608 */
e2933132
SRT		 5609static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5610 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 5611{
5612 struct utp_task_req_desc *task_req_descp;
5613 struct utp_upiu_task_req *task_req_upiup;
5614 struct Scsi_Host *host;
5615 unsigned long flags;
e2933132 5616 int free_slot;
7a3e97b0 5617 int err;
e2933132 5618 int task_tag;
7a3e97b0
SY		 5619
5620 host = hba->host;
5621
e2933132
SRT		 5622 /*
5623 * Get free slot, sleep if slots are unavailable.
5624 * Even though we use wait_event() which sleeps indefinitely,
5625 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5626 */
5627 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5628 ufshcd_hold(hba, false);
7a3e97b0 5629
e2933132 5630 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 5631 task_req_descp = hba->utmrdl_base_addr;
5632 task_req_descp += free_slot;
5633
5634 /* Configure task request descriptor */
5635 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5636 task_req_descp->header.dword_2 =
5637 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5638
5639 /* Configure task request UPIU */
5640 task_req_upiup =
5641 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 5642 task_tag = hba->nutrs + free_slot;
7a3e97b0 5643 task_req_upiup->header.dword_0 =
5a0b0cb9 5644 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 5645 lun_id, task_tag);
7a3e97b0 5646 task_req_upiup->header.dword_1 =
5a0b0cb9 5647 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 5648 /*
5649 * The host shall provide the same value for LUN field in the basic
5650 * header and for Input Parameter.
5651 */
e2933132
SRT		 5652 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
5653 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 5654
d2877be4
KK		 5655 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5656
7a3e97b0
SY		 5657 /* send command to the controller */
5658 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5659
5660 /* Make sure descriptors are ready before ringing the task doorbell */
5661 wmb();
5662
b873a275 5663 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5664 /* Make sure that doorbell is committed immediately */
5665 wmb();
7a3e97b0
SY		 5666
5667 spin_unlock_irqrestore(host->host_lock, flags);
5668
6667e6d9
OS		 5669 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5670
7a3e97b0 5671 /* wait until the task management command is completed */
e2933132
SRT		 5672 err = wait_event_timeout(hba->tm_wq,
5673 test_bit(free_slot, &hba->tm_condition),
5674 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5675 if (!err) {
6667e6d9 5676 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
e2933132
SRT		 5677 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5678 __func__, tm_function);
5679 if (ufshcd_clear_tm_cmd(hba, free_slot))
5680 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5681 __func__, free_slot);
5682 err = -ETIMEDOUT;
5683 } else {
5684 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
6667e6d9 5685 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
7a3e97b0 5686 }
e2933132 5687
7a3e97b0 5688 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 5689 ufshcd_put_tm_slot(hba, free_slot);
5690 wake_up(&hba->tm_tag_wq);
5691
1ab27c9c 5692 ufshcd_release(hba);
7a3e97b0
SY		 5693 return err;
5694}
5695
5696/**
3441da7d
SRT		 5697 * ufshcd_eh_device_reset_handler - device reset handler registered to
5698 * scsi layer.
7a3e97b0
SY		 5699 * @cmd: SCSI command pointer
5700 *
5701 * Returns SUCCESS/FAILED
5702 */
3441da7d 5703static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5704{
5705 struct Scsi_Host *host;
5706 struct ufs_hba *hba;
5707 unsigned int tag;
5708 u32 pos;
5709 int err;
e2933132
SRT		 5710 u8 resp = 0xF;
5711 struct ufshcd_lrb *lrbp;
3441da7d 5712 unsigned long flags;
7a3e97b0
SY		 5713
5714 host = cmd->device->host;
5715 hba = shost_priv(host);
5716 tag = cmd->request->tag;
5717
e2933132
SRT		 5718 lrbp = &hba->lrb[tag];
5719 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5720 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 5721 if (!err)
5722 err = resp;
7a3e97b0 5723 goto out;
e2933132 5724 }
7a3e97b0 5725
3441da7d
SRT		 5726 /* clear the commands that were pending for corresponding LUN */
5727 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5728 if (hba->lrb[pos].lun == lrbp->lun) {
5729 err = ufshcd_clear_cmd(hba, pos);
5730 if (err)
5731 break;
7a3e97b0 5732 }
3441da7d
SRT		 5733 }
5734 spin_lock_irqsave(host->host_lock, flags);
5735 ufshcd_transfer_req_compl(hba);
5736 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5737
7a3e97b0 5738out:
7fabb77b 5739 hba->req_abort_count = 0;
3441da7d
SRT		 5740 if (!err) {
5741 err = SUCCESS;
5742 } else {
5743 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5744 err = FAILED;
5745 }
7a3e97b0
SY		 5746 return err;
5747}
5748
e0b299e3
GB		 5749static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5750{
5751 struct ufshcd_lrb *lrbp;
5752 int tag;
5753
5754 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5755 lrbp = &hba->lrb[tag];
5756 lrbp->req_abort_skip = true;
5757 }
5758}
5759
7a3e97b0
SY		 5760/**
5761 * ufshcd_abort - abort a specific command
5762 * @cmd: SCSI command pointer
5763 *
f20810d8
SRT		 5764 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5765 * command, and in host controller by clearing the door-bell register. There can
5766 * be race between controller sending the command to the device while abort is
5767 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5768 * really issued and then try to abort it.
5769 *
7a3e97b0
SY		 5770 * Returns SUCCESS/FAILED
5771 */
5772static int ufshcd_abort(struct scsi_cmnd *cmd)
5773{
5774 struct Scsi_Host *host;
5775 struct ufs_hba *hba;
5776 unsigned long flags;
5777 unsigned int tag;
f20810d8
SRT		 5778 int err = 0;
5779 int poll_cnt;
e2933132
SRT		 5780 u8 resp = 0xF;
5781 struct ufshcd_lrb *lrbp;
e9d501b1 5782 u32 reg;
7a3e97b0
SY		 5783
5784 host = cmd->device->host;
5785 hba = shost_priv(host);
5786 tag = cmd->request->tag;
e7d38257 5787 lrbp = &hba->lrb[tag];
14497328
YG		 5788 if (!ufshcd_valid_tag(hba, tag)) {
5789 dev_err(hba->dev,
5790 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5791 __func__, tag, cmd, cmd->request);
5792 BUG();
5793 }
7a3e97b0 5794
e7d38257
DR		 5795 /*
5796 * Task abort to the device W-LUN is illegal. When this command
5797 * will fail, due to spec violation, scsi err handling next step
5798 * will be to send LU reset which, again, is a spec violation.
5799 * To avoid these unnecessary/illegal step we skip to the last error
5800 * handling stage: reset and restore.
5801 */
5802 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5803 return ufshcd_eh_host_reset_handler(cmd);
5804
1ab27c9c 5805 ufshcd_hold(hba, false);
14497328 5806 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5807 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 5808 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5809 dev_err(hba->dev,
5810 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5811 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 5812 goto out;
14497328 5813 }
7a3e97b0 5814
e9d501b1
DR		 5815 if (!(reg & (1 << tag))) {
5816 dev_err(hba->dev,
5817 "%s: cmd was completed, but without a notifying intr, tag = %d",
5818 __func__, tag);
5819 }
5820
66cc820f
DR		 5821 /* Print Transfer Request of aborted task */
5822 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 5823
7fabb77b
GB		 5824 /*
5825 * Print detailed info about aborted request.
5826 * As more than one request might get aborted at the same time,
5827 * print full information only for the first aborted request in order
5828 * to reduce repeated printouts. For other aborted requests only print
5829 * basic details.
5830 */
5831 scsi_print_command(hba->lrb[tag].cmd);
5832 if (!hba->req_abort_count) {
5833 ufshcd_print_host_regs(hba);
6ba65588 5834 ufshcd_print_host_state(hba);
7fabb77b
GB		 5835 ufshcd_print_pwr_info(hba);
5836 ufshcd_print_trs(hba, 1 << tag, true);
5837 } else {
5838 ufshcd_print_trs(hba, 1 << tag, false);
5839 }
5840 hba->req_abort_count++;
e0b299e3
GB		 5841
5842 /* Skip task abort in case previous aborts failed and report failure */
5843 if (lrbp->req_abort_skip) {
5844 err = -EIO;
5845 goto out;
5846 }
5847
f20810d8
SRT		 5848 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
5849 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5850 UFS_QUERY_TASK, &resp);
5851 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
5852 /* cmd pending in the device */
ff8e20c6
DR		 5853 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
5854 __func__, tag);
f20810d8
SRT		 5855 break;
5856 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 5857 /*
5858 * cmd not pending in the device, check if it is
5859 * in transition.
5860 */
ff8e20c6
DR		 5861 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
5862 __func__, tag);
f20810d8
SRT		 5863 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5864 if (reg & (1 << tag)) {
5865 /* sleep for max. 200us to stabilize */
5866 usleep_range(100, 200);
5867 continue;
5868 }
5869 /* command completed already */
ff8e20c6
DR		 5870 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
5871 __func__, tag);
f20810d8
SRT		 5872 goto out;
5873 } else {
ff8e20c6
DR		 5874 dev_err(hba->dev,
5875 "%s: no response from device. tag = %d, err %d\n",
5876 __func__, tag, err);
f20810d8
SRT		 5877 if (!err)
5878 err = resp; /* service response error */
5879 goto out;
5880 }
5881 }
5882
5883 if (!poll_cnt) {
5884 err = -EBUSY;
7a3e97b0
SY		 5885 goto out;
5886 }
7a3e97b0 5887
e2933132
SRT		 5888 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5889 UFS_ABORT_TASK, &resp);
5890 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 5891 if (!err) {
f20810d8 5892 err = resp; /* service response error */
ff8e20c6
DR		 5893 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
5894 __func__, tag, err);
5895 }
7a3e97b0 5896 goto out;
e2933132 5897 }
7a3e97b0 5898
f20810d8 5899 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 5900 if (err) {
5901 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
5902 __func__, tag, err);
f20810d8 5903 goto out;
ff8e20c6 5904 }
f20810d8 5905
7a3e97b0
SY		 5906 scsi_dma_unmap(cmd);
5907
5908 spin_lock_irqsave(host->host_lock, flags);
a48353f6 5909 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 5910 hba->lrb[tag].cmd = NULL;
5911 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 5912
5913 clear_bit_unlock(tag, &hba->lrb_in_use);
5914 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 5915
7a3e97b0 5916out:
f20810d8
SRT		 5917 if (!err) {
5918 err = SUCCESS;
5919 } else {
5920 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 5921 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 5922 err = FAILED;
5923 }
5924
1ab27c9c
ST		 5925 /*
5926 * This ufshcd_release() corresponds to the original scsi cmd that got
5927 * aborted here (as we won't get any IRQ for it).
5928 */
5929 ufshcd_release(hba);
7a3e97b0
SY		 5930 return err;
5931}
5932
3441da7d
SRT		 5933/**
5934 * ufshcd_host_reset_and_restore - reset and restore host controller
5935 * @hba: per-adapter instance
5936 *
5937 * Note that host controller reset may issue DME_RESET to
5938 * local and remote (device) Uni-Pro stack and the attributes
5939 * are reset to default state.
5940 *
5941 * Returns zero on success, non-zero on failure
5942 */
5943static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
5944{
5945 int err;
3441da7d
SRT		 5946 unsigned long flags;
5947
5948 /* Reset the host controller */
5949 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 5950 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 5951 spin_unlock_irqrestore(hba->host->host_lock, flags);
5952
a3cd5ec5
SJ		 5953 /* scale up clocks to max frequency before full reinitialization */
5954 ufshcd_scale_clks(hba, true);
5955
3441da7d
SRT		 5956 err = ufshcd_hba_enable(hba);
5957 if (err)
5958 goto out;
5959
5960 /* Establish the link again and restore the device */
1d337ec2
SRT		 5961 err = ufshcd_probe_hba(hba);
5962
5963 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 5964 err = -EIO;
5965out:
5966 if (err)
5967 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
5968
5969 return err;
5970}
5971
5972/**
5973 * ufshcd_reset_and_restore - reset and re-initialize host/device
5974 * @hba: per-adapter instance
5975 *
5976 * Reset and recover device, host and re-establish link. This
5977 * is helpful to recover the communication in fatal error conditions.
5978 *
5979 * Returns zero on success, non-zero on failure
5980 */
5981static int ufshcd_reset_and_restore(struct ufs_hba *hba)
5982{
5983 int err = 0;
5984 unsigned long flags;
1d337ec2 5985 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 5986
1d337ec2
SRT		 5987 do {
5988 err = ufshcd_host_reset_and_restore(hba);
5989 } while (err && --retries);
3441da7d
SRT		 5990
5991 /*
5992 * After reset the door-bell might be cleared, complete
5993 * outstanding requests in s/w here.
5994 */
5995 spin_lock_irqsave(hba->host->host_lock, flags);
5996 ufshcd_transfer_req_compl(hba);
5997 ufshcd_tmc_handler(hba);
5998 spin_unlock_irqrestore(hba->host->host_lock, flags);
5999
6000 return err;
6001}
6002
6003/**
6004 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 6005 * @cmd: SCSI command pointer
3441da7d
SRT		 6006 *
6007 * Returns SUCCESS/FAILED
6008 */
6009static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6010{
6011 int err;
6012 unsigned long flags;
6013 struct ufs_hba *hba;
6014
6015 hba = shost_priv(cmd->device->host);
6016
1ab27c9c 6017 ufshcd_hold(hba, false);
3441da7d
SRT		 6018 /*
6019 * Check if there is any race with fatal error handling.
6020 * If so, wait for it to complete. Even though fatal error
6021 * handling does reset and restore in some cases, don't assume
6022 * anything out of it. We are just avoiding race here.
6023 */
6024 do {
6025 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6026 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6027 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6028 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6029 break;
6030 spin_unlock_irqrestore(hba->host->host_lock, flags);
6031 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6032 flush_work(&hba->eh_work);
3441da7d
SRT		 6033 } while (1);
6034
6035 hba->ufshcd_state = UFSHCD_STATE_RESET;
6036 ufshcd_set_eh_in_progress(hba);
6037 spin_unlock_irqrestore(hba->host->host_lock, flags);
6038
6039 err = ufshcd_reset_and_restore(hba);
6040
6041 spin_lock_irqsave(hba->host->host_lock, flags);
6042 if (!err) {
6043 err = SUCCESS;
6044 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6045 } else {
6046 err = FAILED;
6047 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6048 }
6049 ufshcd_clear_eh_in_progress(hba);
6050 spin_unlock_irqrestore(hba->host->host_lock, flags);
6051
1ab27c9c 6052 ufshcd_release(hba);
3441da7d
SRT		 6053 return err;
6054}
6055
3a4bf06d
YG		 6056/**
6057 * ufshcd_get_max_icc_level - calculate the ICC level
6058 * @sup_curr_uA: max. current supported by the regulator
6059 * @start_scan: row at the desc table to start scan from
6060 * @buff: power descriptor buffer
6061 *
6062 * Returns calculated max ICC level for specific regulator
6063 */
6064static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6065{
6066 int i;
6067 int curr_uA;
6068 u16 data;
6069 u16 unit;
6070
6071 for (i = start_scan; i >= 0; i--) {
d79713f9 6072 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6073 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6074 ATTR_ICC_LVL_UNIT_OFFSET;
6075 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6076 switch (unit) {
6077 case UFSHCD_NANO_AMP:
6078 curr_uA = curr_uA / 1000;
6079 break;
6080 case UFSHCD_MILI_AMP:
6081 curr_uA = curr_uA * 1000;
6082 break;
6083 case UFSHCD_AMP:
6084 curr_uA = curr_uA * 1000 * 1000;
6085 break;
6086 case UFSHCD_MICRO_AMP:
6087 default:
6088 break;
6089 }
6090 if (sup_curr_uA >= curr_uA)
6091 break;
6092 }
6093 if (i < 0) {
6094 i = 0;
6095 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6096 }
6097
6098 return (u32)i;
6099}
6100
6101/**
6102 * ufshcd_calc_icc_level - calculate the max ICC level
6103 * In case regulators are not initialized we'll return 0
6104 * @hba: per-adapter instance
6105 * @desc_buf: power descriptor buffer to extract ICC levels from.
6106 * @len: length of desc_buff
6107 *
6108 * Returns calculated ICC level
6109 */
6110static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6111 u8 *desc_buf, int len)
6112{
6113 u32 icc_level = 0;
6114
6115 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6116 !hba->vreg_info.vccq2) {
6117 dev_err(hba->dev,
6118 "%s: Regulator capability was not set, actvIccLevel=%d",
6119 __func__, icc_level);
6120 goto out;
6121 }
6122
6123 if (hba->vreg_info.vcc)
6124 icc_level = ufshcd_get_max_icc_level(
6125 hba->vreg_info.vcc->max_uA,
6126 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6127 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6128
6129 if (hba->vreg_info.vccq)
6130 icc_level = ufshcd_get_max_icc_level(
6131 hba->vreg_info.vccq->max_uA,
6132 icc_level,
6133 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6134
6135 if (hba->vreg_info.vccq2)
6136 icc_level = ufshcd_get_max_icc_level(
6137 hba->vreg_info.vccq2->max_uA,
6138 icc_level,
6139 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6140out:
6141 return icc_level;
6142}
6143
6144static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6145{
6146 int ret;
a4b0e8a4 6147 int buff_len = hba->desc_size.pwr_desc;
bbe21d7a
KC		 6148 u8 *desc_buf;
6149
6150 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6151 if (!desc_buf)
6152 return;
3a4bf06d
YG		 6153
6154 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
6155 if (ret) {
6156 dev_err(hba->dev,
6157 "%s: Failed reading power descriptor.len = %d ret = %d",
6158 __func__, buff_len, ret);
bbe21d7a 6159 goto out;
3a4bf06d
YG		 6160 }
6161
6162 hba->init_prefetch_data.icc_level =
6163 ufshcd_find_max_sup_active_icc_level(hba,
6164 desc_buf, buff_len);
6165 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6166 __func__, hba->init_prefetch_data.icc_level);
6167
dbd34a61
SM		 6168 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6169 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6170 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 6171
6172 if (ret)
6173 dev_err(hba->dev,
6174 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6175 __func__, hba->init_prefetch_data.icc_level , ret);
6176
bbe21d7a
KC		 6177out:
6178 kfree(desc_buf);
3a4bf06d
YG		 6179}
6180
2a8fa600
SJ		 6181/**
6182 * ufshcd_scsi_add_wlus - Adds required W-LUs
6183 * @hba: per-adapter instance
6184 *
6185 * UFS device specification requires the UFS devices to support 4 well known
6186 * logical units:
6187 * "REPORT_LUNS" (address: 01h)
6188 * "UFS Device" (address: 50h)
6189 * "RPMB" (address: 44h)
6190 * "BOOT" (address: 30h)
6191 * UFS device's power management needs to be controlled by "POWER CONDITION"
6192 * field of SSU (START STOP UNIT) command. But this "power condition" field
6193 * will take effect only when its sent to "UFS device" well known logical unit
6194 * hence we require the scsi_device instance to represent this logical unit in
6195 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 6196 *
2a8fa600
SJ		 6197 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6198 * Block) LU so user space process can control this LU. User space may also
6199 * want to have access to BOOT LU.
8aa29f19 6200 *
2a8fa600
SJ		 6201 * This function adds scsi device instances for each of all well known LUs
6202 * (except "REPORT LUNS" LU).
6203 *
6204 * Returns zero on success (all required W-LUs are added successfully),
6205 * non-zero error value on failure (if failed to add any of the required W-LU).
6206 */
6207static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6208{
6209 int ret = 0;
7c48bfd0
AM		 6210 struct scsi_device *sdev_rpmb;
6211 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6212
6213 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6214 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6215 if (IS_ERR(hba->sdev_ufs_device)) {
6216 ret = PTR_ERR(hba->sdev_ufs_device);
6217 hba->sdev_ufs_device = NULL;
6218 goto out;
6219 }
7c48bfd0 6220 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6221
7c48bfd0 6222 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6223 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6224 if (IS_ERR(sdev_rpmb)) {
6225 ret = PTR_ERR(sdev_rpmb);
3d21fbde 6226 goto remove_sdev_ufs_device;
2a8fa600 6227 }
7c48bfd0 6228 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 6229
6230 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6231 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
6232 if (IS_ERR(sdev_boot))
6233 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
6234 else
6235 scsi_device_put(sdev_boot);
2a8fa600
SJ		 6236 goto out;
6237
2a8fa600
SJ		 6238remove_sdev_ufs_device:
6239 scsi_remove_device(hba->sdev_ufs_device);
6240out:
6241 return ret;
6242}
6243
93fdd5ac
TW		 6244static int ufs_get_device_desc(struct ufs_hba *hba,
6245 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6246{
6247 int err;
bbe21d7a 6248 size_t buff_len;
c58ab7aa 6249 u8 model_index;
bbe21d7a
KC		 6250 u8 *desc_buf;
6251
6252 buff_len = max_t(size_t, hba->desc_size.dev_desc,
6253 QUERY_DESC_MAX_SIZE + 1);
6254 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6255 if (!desc_buf) {
6256 err = -ENOMEM;
6257 goto out;
6258 }
c58ab7aa 6259
a4b0e8a4 6260 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
c58ab7aa
YG		 6261 if (err) {
6262 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6263 __func__, err);
6264 goto out;
6265 }
6266
6267 /*
6268 * getting vendor (manufacturerID) and Bank Index in big endian
6269 * format
6270 */
93fdd5ac 6271 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6272 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6273
6274 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6275
bbe21d7a
KC		 6276 /* Zero-pad entire buffer for string termination. */
6277 memset(desc_buf, 0, buff_len);
6278
6279 err = ufshcd_read_string_desc(hba, model_index, desc_buf,
8aa29f19 6280 QUERY_DESC_MAX_SIZE, true/*ASCII*/);
c58ab7aa
YG		 6281 if (err) {
6282 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6283 __func__, err);
6284 goto out;
6285 }
6286
bbe21d7a
KC		 6287 desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
6288 strlcpy(dev_desc->model, (desc_buf + QUERY_DESC_HDR_SIZE),
6289 min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
c58ab7aa
YG		 6290 MAX_MODEL_LEN));
6291
6292 /* Null terminate the model string */
93fdd5ac 6293 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG		 6294
6295out:
bbe21d7a 6296 kfree(desc_buf);
c58ab7aa
YG		 6297 return err;
6298}
6299
93fdd5ac
TW		 6300static void ufs_fixup_device_setup(struct ufs_hba *hba,
6301 struct ufs_dev_desc *dev_desc)
c58ab7aa 6302{
c58ab7aa 6303 struct ufs_dev_fix *f;
c58ab7aa
YG		 6304
6305 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6306 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6307 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6308 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG		 6309 !strcmp(f->card.model, UFS_ANY_MODEL)))
6310 hba->dev_quirks |= f->quirk;
6311 }
6312}
6313
37113106
YG		 6314/**
6315 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6316 * @hba: per-adapter instance
6317 *
6318 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6319 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6320 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6321 * the hibern8 exit latency.
6322 *
6323 * Returns zero on success, non-zero error value on failure.
6324 */
6325static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6326{
6327 int ret = 0;
6328 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6329
6330 ret = ufshcd_dme_peer_get(hba,
6331 UIC_ARG_MIB_SEL(
6332 RX_MIN_ACTIVATETIME_CAPABILITY,
6333 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6334 &peer_rx_min_activatetime);
6335 if (ret)
6336 goto out;
6337
6338 /* make sure proper unit conversion is applied */
6339 tuned_pa_tactivate =
6340 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6341 / PA_TACTIVATE_TIME_UNIT_US);
6342 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6343 tuned_pa_tactivate);
6344
6345out:
6346 return ret;
6347}
6348
6349/**
6350 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6351 * @hba: per-adapter instance
6352 *
6353 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6354 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6355 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6356 * This optimal value can help reduce the hibern8 exit latency.
6357 *
6358 * Returns zero on success, non-zero error value on failure.
6359 */
6360static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6361{
6362 int ret = 0;
6363 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6364 u32 max_hibern8_time, tuned_pa_hibern8time;
6365
6366 ret = ufshcd_dme_get(hba,
6367 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6368 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6369 &local_tx_hibern8_time_cap);
6370 if (ret)
6371 goto out;
6372
6373 ret = ufshcd_dme_peer_get(hba,
6374 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6375 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6376 &peer_rx_hibern8_time_cap);
6377 if (ret)
6378 goto out;
6379
6380 max_hibern8_time = max(local_tx_hibern8_time_cap,
6381 peer_rx_hibern8_time_cap);
6382 /* make sure proper unit conversion is applied */
6383 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6384 / PA_HIBERN8_TIME_UNIT_US);
6385 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6386 tuned_pa_hibern8time);
6387out:
6388 return ret;
6389}
6390
c6a6db43
SJ		 6391/**
6392 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6393 * less than device PA_TACTIVATE time.
6394 * @hba: per-adapter instance
6395 *
6396 * Some UFS devices require host PA_TACTIVATE to be lower than device
6397 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6398 * for such devices.
6399 *
6400 * Returns zero on success, non-zero error value on failure.
6401 */
6402static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6403{
6404 int ret = 0;
6405 u32 granularity, peer_granularity;
6406 u32 pa_tactivate, peer_pa_tactivate;
6407 u32 pa_tactivate_us, peer_pa_tactivate_us;
6408 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6409
6410 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6411 &granularity);
6412 if (ret)
6413 goto out;
6414
6415 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6416 &peer_granularity);
6417 if (ret)
6418 goto out;
6419
6420 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6421 (granularity > PA_GRANULARITY_MAX_VAL)) {
6422 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6423 __func__, granularity);
6424 return -EINVAL;
6425 }
6426
6427 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6428 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6429 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6430 __func__, peer_granularity);
6431 return -EINVAL;
6432 }
6433
6434 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6435 if (ret)
6436 goto out;
6437
6438 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6439 &peer_pa_tactivate);
6440 if (ret)
6441 goto out;
6442
6443 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6444 peer_pa_tactivate_us = peer_pa_tactivate *
6445 gran_to_us_table[peer_granularity - 1];
6446
6447 if (pa_tactivate_us > peer_pa_tactivate_us) {
6448 u32 new_peer_pa_tactivate;
6449
6450 new_peer_pa_tactivate = pa_tactivate_us /
6451 gran_to_us_table[peer_granularity - 1];
6452 new_peer_pa_tactivate++;
6453 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6454 new_peer_pa_tactivate);
6455 }
6456
6457out:
6458 return ret;
6459}
6460
37113106
YG		 6461static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6462{
6463 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6464 ufshcd_tune_pa_tactivate(hba);
6465 ufshcd_tune_pa_hibern8time(hba);
6466 }
6467
6468 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6469 /* set 1ms timeout for PA_TACTIVATE */
6470 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43
SJ		 6471
6472 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6473 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6474
6475 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6476}
6477
ff8e20c6
DR		 6478static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6479{
6480 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6481
6482 hba->ufs_stats.hibern8_exit_cnt = 0;
6483 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6484
6485 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6486 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6487 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6488 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6489 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB		 6490
6491 hba->req_abort_count = 0;
ff8e20c6
DR		 6492}
6493
a4b0e8a4
PM		 6494static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6495{
6496 int err;
6497
6498 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6499 &hba->desc_size.dev_desc);
6500 if (err)
6501 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6502
6503 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6504 &hba->desc_size.pwr_desc);
6505 if (err)
6506 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6507
6508 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6509 &hba->desc_size.interc_desc);
6510 if (err)
6511 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6512
6513 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6514 &hba->desc_size.conf_desc);
6515 if (err)
6516 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6517
6518 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6519 &hba->desc_size.unit_desc);
6520 if (err)
6521 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6522
6523 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6524 &hba->desc_size.geom_desc);
6525 if (err)
6526 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
c648c2d2
SN		 6527 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
6528 &hba->desc_size.hlth_desc);
6529 if (err)
6530 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 6531}
6532
6533static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6534{
6535 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6536 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6537 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6538 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6539 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6540 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
c648c2d2 6541 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
a4b0e8a4
PM		 6542}
6543
6ccf44fe 6544/**
1d337ec2
SRT		 6545 * ufshcd_probe_hba - probe hba to detect device and initialize
6546 * @hba: per-adapter instance
6547 *
6548 * Execute link-startup and verify device initialization
6ccf44fe 6549 */
1d337ec2 6550static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6551{
93fdd5ac 6552 struct ufs_dev_desc card = {0};
6ccf44fe 6553 int ret;
7ff5ab47 6554 ktime_t start = ktime_get();
6ccf44fe
SJ		 6555
6556 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6557 if (ret)
6558 goto out;
6559
afdfff59
YG		 6560 /* set the default level for urgent bkops */
6561 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6562 hba->is_urgent_bkops_lvl_checked = false;
6563
ff8e20c6
DR		 6564 /* Debug counters initialization */
6565 ufshcd_clear_dbg_ufs_stats(hba);
6566
57d104c1
SJ		 6567 /* UniPro link is active now */
6568 ufshcd_set_link_active(hba);
d3e89bac 6569
ad448378
AH		 6570 /* Enable Auto-Hibernate if configured */
6571 ufshcd_auto_hibern8_enable(hba);
6572
5a0b0cb9
SRT		 6573 ret = ufshcd_verify_dev_init(hba);
6574 if (ret)
6575 goto out;
68078d5c
DR		 6576
6577 ret = ufshcd_complete_dev_init(hba);
6578 if (ret)
6579 goto out;
5a0b0cb9 6580
a4b0e8a4
PM		 6581 /* Init check for device descriptor sizes */
6582 ufshcd_init_desc_sizes(hba);
6583
93fdd5ac
TW		 6584 ret = ufs_get_device_desc(hba, &card);
6585 if (ret) {
6586 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6587 __func__, ret);
6588 goto out;
6589 }
6590
6591 ufs_fixup_device_setup(hba, &card);
37113106 6592 ufshcd_tune_unipro_params(hba);
60f01870
YG		 6593
6594 ret = ufshcd_set_vccq_rail_unused(hba,
6595 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6596 if (ret)
6597 goto out;
6598
57d104c1
SJ		 6599 /* UFS device is also active now */
6600 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6601 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6602 hba->wlun_dev_clr_ua = true;
6603
7eb584db
DR		 6604 if (ufshcd_get_max_pwr_mode(hba)) {
6605 dev_err(hba->dev,
6606 "%s: Failed getting max supported power mode\n",
6607 __func__);
6608 } else {
6609 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6610 if (ret) {
7eb584db
DR		 6611 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6612 __func__, ret);
8643ae66
DL		 6613 goto out;
6614 }
7eb584db 6615 }
57d104c1 6616
53c12d0e
YG		 6617 /* set the state as operational after switching to desired gear */
6618 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 6619
57d104c1
SJ		 6620 /*
6621 * If we are in error handling context or in power management callbacks
6622 * context, no need to scan the host
6623 */
6624 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6625 bool flag;
6626
6627 /* clear any previous UFS device information */
6628 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 6629 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6630 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6631 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6632
3a4bf06d
YG		 6633 if (!hba->is_init_prefetch)
6634 ufshcd_init_icc_levels(hba);
6635
2a8fa600
SJ		 6636 /* Add required well known logical units to scsi mid layer */
6637 if (ufshcd_scsi_add_wlus(hba))
6638 goto out;
6639
0701e49d
SJ		 6640 /* Initialize devfreq after UFS device is detected */
6641 if (ufshcd_is_clkscaling_supported(hba)) {
6642 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6643 &hba->pwr_info,
6644 sizeof(struct ufs_pa_layer_attr));
6645 hba->clk_scaling.saved_pwr_info.is_valid = true;
6646 if (!hba->devfreq) {
deac444f
BA		 6647 ret = ufshcd_devfreq_init(hba);
6648 if (ret)
0701e49d 6649 goto out;
0701e49d
SJ		 6650 }
6651 hba->clk_scaling.is_allowed = true;
6652 }
6653
3441da7d
SRT		 6654 scsi_scan_host(hba->host);
6655 pm_runtime_put_sync(hba->dev);
6656 }
3a4bf06d
YG		 6657
6658 if (!hba->is_init_prefetch)
6659 hba->is_init_prefetch = true;
6660
5a0b0cb9 6661out:
1d337ec2
SRT		 6662 /*
6663 * If we failed to initialize the device or the device is not
6664 * present, turn off the power/clocks etc.
6665 */
57d104c1
SJ		 6666 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6667 pm_runtime_put_sync(hba->dev);
1d337ec2 6668 ufshcd_hba_exit(hba);
57d104c1 6669 }
1d337ec2 6670
7ff5ab47
SJ		 6671 trace_ufshcd_init(dev_name(hba->dev), ret,
6672 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6673 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 6674 return ret;
6675}
6676
6677/**
6678 * ufshcd_async_scan - asynchronous execution for probing hba
6679 * @data: data pointer to pass to this function
6680 * @cookie: cookie data
6681 */
6682static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6683{
6684 struct ufs_hba *hba = (struct ufs_hba *)data;
6685
6686 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 6687}
6688
f550c65b
YG		 6689static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6690{
6691 unsigned long flags;
6692 struct Scsi_Host *host;
6693 struct ufs_hba *hba;
6694 int index;
6695 bool found = false;
6696
6697 if (!scmd || !scmd->device || !scmd->device->host)
6600593c 6698 return BLK_EH_DONE;
f550c65b
YG		 6699
6700 host = scmd->device->host;
6701 hba = shost_priv(host);
6702 if (!hba)
6600593c 6703 return BLK_EH_DONE;
f550c65b
YG		 6704
6705 spin_lock_irqsave(host->host_lock, flags);
6706
6707 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6708 if (hba->lrb[index].cmd == scmd) {
6709 found = true;
6710 break;
6711 }
6712 }
6713
6714 spin_unlock_irqrestore(host->host_lock, flags);
6715
6716 /*
6717 * Bypass SCSI error handling and reset the block layer timer if this
6718 * SCSI command was not actually dispatched to UFS driver, otherwise
6719 * let SCSI layer handle the error as usual.
6720 */
6600593c 6721 return found ? BLK_EH_DONE : BLK_EH_RESET_TIMER;
f550c65b
YG		 6722}
6723
d829fc8a
SN		 6724static const struct attribute_group *ufshcd_driver_groups[] = {
6725 &ufs_sysfs_unit_descriptor_group,
ec92b59c 6726 &ufs_sysfs_lun_attributes_group,
d829fc8a
SN		 6727 NULL,
6728};
6729
7a3e97b0
SY		 6730static struct scsi_host_template ufshcd_driver_template = {
6731 .module = THIS_MODULE,
6732 .name = UFSHCD,
6733 .proc_name = UFSHCD,
6734 .queuecommand = ufshcd_queuecommand,
6735 .slave_alloc = ufshcd_slave_alloc,
eeda4749 6736 .slave_configure = ufshcd_slave_configure,
7a3e97b0 6737 .slave_destroy = ufshcd_slave_destroy,
4264fd61 6738 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 6739 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 6740 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6741 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 6742 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 6743 .this_id = -1,
6744 .sg_tablesize = SG_ALL,
6745 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6746 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 6747 .max_host_blocked = 1,
c40ecc12 6748 .track_queue_depth = 1,
d829fc8a 6749 .sdev_groups = ufshcd_driver_groups,
7a3e97b0
SY		 6750};
6751
57d104c1
SJ		 6752static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6753 int ua)
6754{
7b16a07c 6755 int ret;
57d104c1 6756
7b16a07c
BA		 6757 if (!vreg)
6758 return 0;
57d104c1 6759
7b16a07c
BA		 6760 ret = regulator_set_load(vreg->reg, ua);
6761 if (ret < 0) {
6762 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6763 __func__, vreg->name, ua, ret);
57d104c1
SJ		 6764 }
6765
6766 return ret;
6767}
6768
6769static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6770 struct ufs_vreg *vreg)
6771{
60f01870
YG		 6772 if (!vreg)
6773 return 0;
6774 else if (vreg->unused)
6775 return 0;
6776 else
6777 return ufshcd_config_vreg_load(hba->dev, vreg,
6778 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 6779}
6780
6781static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6782 struct ufs_vreg *vreg)
6783{
60f01870
YG		 6784 if (!vreg)
6785 return 0;
6786 else if (vreg->unused)
6787 return 0;
6788 else
6789 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 6790}
6791
aa497613
SRT		 6792static int ufshcd_config_vreg(struct device *dev,
6793 struct ufs_vreg *vreg, bool on)
6794{
6795 int ret = 0;
72753590
GS		 6796 struct regulator *reg;
6797 const char *name;
aa497613
SRT		 6798 int min_uV, uA_load;
6799
6800 BUG_ON(!vreg);
6801
72753590
GS		 6802 reg = vreg->reg;
6803 name = vreg->name;
6804
aa497613
SRT		 6805 if (regulator_count_voltages(reg) > 0) {
6806 min_uV = on ? vreg->min_uV : 0;
6807 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6808 if (ret) {
6809 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6810 __func__, name, ret);
6811 goto out;
6812 }
6813
6814 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 6815 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6816 if (ret)
aa497613 6817 goto out;
aa497613
SRT		 6818 }
6819out:
6820 return ret;
6821}
6822
6823static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6824{
6825 int ret = 0;
6826
60f01870
YG		 6827 if (!vreg)
6828 goto out;
6829 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 6830 goto out;
6831
6832 ret = ufshcd_config_vreg(dev, vreg, true);
6833 if (!ret)
6834 ret = regulator_enable(vreg->reg);
6835
6836 if (!ret)
6837 vreg->enabled = true;
6838 else
6839 dev_err(dev, "%s: %s enable failed, err=%d\n",
6840 __func__, vreg->name, ret);
6841out:
6842 return ret;
6843}
6844
6845static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
6846{
6847 int ret = 0;
6848
60f01870
YG		 6849 if (!vreg)
6850 goto out;
6851 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 6852 goto out;
6853
6854 ret = regulator_disable(vreg->reg);
6855
6856 if (!ret) {
6857 /* ignore errors on applying disable config */
6858 ufshcd_config_vreg(dev, vreg, false);
6859 vreg->enabled = false;
6860 } else {
6861 dev_err(dev, "%s: %s disable failed, err=%d\n",
6862 __func__, vreg->name, ret);
6863 }
6864out:
6865 return ret;
6866}
6867
6868static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
6869{
6870 int ret = 0;
6871 struct device *dev = hba->dev;
6872 struct ufs_vreg_info *info = &hba->vreg_info;
6873
6874 if (!info)
6875 goto out;
6876
6877 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
6878 if (ret)
6879 goto out;
6880
6881 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
6882 if (ret)
6883 goto out;
6884
6885 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
6886 if (ret)
6887 goto out;
6888
6889out:
6890 if (ret) {
6891 ufshcd_toggle_vreg(dev, info->vccq2, false);
6892 ufshcd_toggle_vreg(dev, info->vccq, false);
6893 ufshcd_toggle_vreg(dev, info->vcc, false);
6894 }
6895 return ret;
6896}
6897
6a771a65
RS		 6898static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
6899{
6900 struct ufs_vreg_info *info = &hba->vreg_info;
6901
6902 if (info)
6903 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6904
6905 return 0;
6906}
6907
aa497613
SRT		 6908static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
6909{
6910 int ret = 0;
6911
6912 if (!vreg)
6913 goto out;
6914
6915 vreg->reg = devm_regulator_get(dev, vreg->name);
6916 if (IS_ERR(vreg->reg)) {
6917 ret = PTR_ERR(vreg->reg);
6918 dev_err(dev, "%s: %s get failed, err=%d\n",
6919 __func__, vreg->name, ret);
6920 }
6921out:
6922 return ret;
6923}
6924
6925static int ufshcd_init_vreg(struct ufs_hba *hba)
6926{
6927 int ret = 0;
6928 struct device *dev = hba->dev;
6929 struct ufs_vreg_info *info = &hba->vreg_info;
6930
6931 if (!info)
6932 goto out;
6933
6934 ret = ufshcd_get_vreg(dev, info->vcc);
6935 if (ret)
6936 goto out;
6937
6938 ret = ufshcd_get_vreg(dev, info->vccq);
6939 if (ret)
6940 goto out;
6941
6942 ret = ufshcd_get_vreg(dev, info->vccq2);
6943out:
6944 return ret;
6945}
6946
6a771a65
RS		 6947static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
6948{
6949 struct ufs_vreg_info *info = &hba->vreg_info;
6950
6951 if (info)
6952 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
6953
6954 return 0;
6955}
6956
60f01870
YG		 6957static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
6958{
6959 int ret = 0;
6960 struct ufs_vreg_info *info = &hba->vreg_info;
6961
6962 if (!info)
6963 goto out;
6964 else if (!info->vccq)
6965 goto out;
6966
6967 if (unused) {
6968 /* shut off the rail here */
6969 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
6970 /*
6971 * Mark this rail as no longer used, so it doesn't get enabled
6972 * later by mistake
6973 */
6974 if (!ret)
6975 info->vccq->unused = true;
6976 } else {
6977 /*
6978 * rail should have been already enabled hence just make sure
6979 * that unused flag is cleared.
6980 */
6981 info->vccq->unused = false;
6982 }
6983out:
6984 return ret;
6985}
6986
57d104c1
SJ		 6987static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
6988 bool skip_ref_clk)
c6e79dac
SRT		 6989{
6990 int ret = 0;
6991 struct ufs_clk_info *clki;
6992 struct list_head *head = &hba->clk_list_head;
1ab27c9c 6993 unsigned long flags;
911a0771
SJ		 6994 ktime_t start = ktime_get();
6995 bool clk_state_changed = false;
c6e79dac 6996
566ec9ad 6997 if (list_empty(head))
c6e79dac
SRT		 6998 goto out;
6999
b334456e
SJ		 7000 /*
7001 * vendor specific setup_clocks ops may depend on clocks managed by
7002 * this standard driver hence call the vendor specific setup_clocks
7003 * before disabling the clocks managed here.
7004 */
7005 if (!on) {
7006 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7007 if (ret)
7008 return ret;
7009 }
1e879e8f 7010
c6e79dac
SRT		 7011 list_for_each_entry(clki, head, list) {
7012 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 7013 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7014 continue;
7015
911a0771 7016 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7017 if (on && !clki->enabled) {
7018 ret = clk_prepare_enable(clki->clk);
7019 if (ret) {
7020 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7021 __func__, clki->name, ret);
7022 goto out;
7023 }
7024 } else if (!on && clki->enabled) {
7025 clk_disable_unprepare(clki->clk);
7026 }
7027 clki->enabled = on;
7028 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7029 clki->name, on ? "en" : "dis");
7030 }
7031 }
1ab27c9c 7032
b334456e
SJ		 7033 /*
7034 * vendor specific setup_clocks ops may depend on clocks managed by
7035 * this standard driver hence call the vendor specific setup_clocks
7036 * after enabling the clocks managed here.
7037 */
7038 if (on) {
7039 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7040 if (ret)
7041 return ret;
7042 }
1e879e8f 7043
c6e79dac
SRT		 7044out:
7045 if (ret) {
7046 list_for_each_entry(clki, head, list) {
7047 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7048 clk_disable_unprepare(clki->clk);
7049 }
7ff5ab47 7050 } else if (!ret && on) {
1ab27c9c
ST		 7051 spin_lock_irqsave(hba->host->host_lock, flags);
7052 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 7053 trace_ufshcd_clk_gating(dev_name(hba->dev),
7054 hba->clk_gating.state);
1ab27c9c 7055 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7056 }
7ff5ab47 7057
911a0771
SJ		 7058 if (clk_state_changed)
7059 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7060 (on ? "on" : "off"),
7061 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7062 return ret;
7063}
7064
57d104c1
SJ		 7065static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7066{
7067 return __ufshcd_setup_clocks(hba, on, false);
7068}
7069
c6e79dac
SRT		 7070static int ufshcd_init_clocks(struct ufs_hba *hba)
7071{
7072 int ret = 0;
7073 struct ufs_clk_info *clki;
7074 struct device *dev = hba->dev;
7075 struct list_head *head = &hba->clk_list_head;
7076
566ec9ad 7077 if (list_empty(head))
c6e79dac
SRT		 7078 goto out;
7079
7080 list_for_each_entry(clki, head, list) {
7081 if (!clki->name)
7082 continue;
7083
7084 clki->clk = devm_clk_get(dev, clki->name);
7085 if (IS_ERR(clki->clk)) {
7086 ret = PTR_ERR(clki->clk);
7087 dev_err(dev, "%s: %s clk get failed, %d\n",
7088 __func__, clki->name, ret);
7089 goto out;
7090 }
7091
7092 if (clki->max_freq) {
7093 ret = clk_set_rate(clki->clk, clki->max_freq);
7094 if (ret) {
7095 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7096 __func__, clki->name,
7097 clki->max_freq, ret);
7098 goto out;
7099 }
856b3483 7100 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 7101 }
7102 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7103 clki->name, clk_get_rate(clki->clk));
7104 }
7105out:
7106 return ret;
7107}
7108
5c0c28a8
SRT		 7109static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7110{
7111 int err = 0;
7112
7113 if (!hba->vops)
7114 goto out;
7115
0263bcd0
YG		 7116 err = ufshcd_vops_init(hba);
7117 if (err)
7118 goto out;
5c0c28a8 7119
0263bcd0
YG		 7120 err = ufshcd_vops_setup_regulators(hba, true);
7121 if (err)
7122 goto out_exit;
5c0c28a8
SRT		 7123
7124 goto out;
7125
5c0c28a8 7126out_exit:
0263bcd0 7127 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7128out:
7129 if (err)
7130 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7131 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7132 return err;
7133}
7134
7135static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7136{
7137 if (!hba->vops)
7138 return;
7139
0263bcd0 7140 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7141
0263bcd0 7142 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7143}
7144
aa497613
SRT		 7145static int ufshcd_hba_init(struct ufs_hba *hba)
7146{
7147 int err;
7148
6a771a65
RS		 7149 /*
7150 * Handle host controller power separately from the UFS device power
7151 * rails as it will help controlling the UFS host controller power
7152 * collapse easily which is different than UFS device power collapse.
7153 * Also, enable the host controller power before we go ahead with rest
7154 * of the initialization here.
7155 */
7156 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7157 if (err)
7158 goto out;
7159
6a771a65 7160 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7161 if (err)
7162 goto out;
7163
6a771a65
RS		 7164 err = ufshcd_init_clocks(hba);
7165 if (err)
7166 goto out_disable_hba_vreg;
7167
7168 err = ufshcd_setup_clocks(hba, true);
7169 if (err)
7170 goto out_disable_hba_vreg;
7171
c6e79dac
SRT		 7172 err = ufshcd_init_vreg(hba);
7173 if (err)
7174 goto out_disable_clks;
7175
7176 err = ufshcd_setup_vreg(hba, true);
7177 if (err)
7178 goto out_disable_clks;
7179
aa497613
SRT		 7180 err = ufshcd_variant_hba_init(hba);
7181 if (err)
7182 goto out_disable_vreg;
7183
1d337ec2 7184 hba->is_powered = true;
aa497613
SRT		 7185 goto out;
7186
7187out_disable_vreg:
7188 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7189out_disable_clks:
7190 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7191out_disable_hba_vreg:
7192 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7193out:
7194 return err;
7195}
7196
7197static void ufshcd_hba_exit(struct ufs_hba *hba)
7198{
1d337ec2
SRT		 7199 if (hba->is_powered) {
7200 ufshcd_variant_hba_exit(hba);
7201 ufshcd_setup_vreg(hba, false);
a508253d 7202 ufshcd_suspend_clkscaling(hba);
401f1e44 7203 if (ufshcd_is_clkscaling_supported(hba)) {
0701e49d
SJ		 7204 if (hba->devfreq)
7205 ufshcd_suspend_clkscaling(hba);
401f1e44 7206 destroy_workqueue(hba->clk_scaling.workq);
092b4558 7207 ufshcd_devfreq_remove(hba);
401f1e44 7208 }
1d337ec2
SRT		 7209 ufshcd_setup_clocks(hba, false);
7210 ufshcd_setup_hba_vreg(hba, false);
7211 hba->is_powered = false;
7212 }
aa497613
SRT		 7213}
7214
57d104c1
SJ		 7215static int
7216ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7217{
7218 unsigned char cmd[6] = {REQUEST_SENSE,
7219 0,
7220 0,
7221 0,
dcea0bfb 7222 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 7223 0};
7224 char *buffer;
7225 int ret;
7226
dcea0bfb 7227 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7228 if (!buffer) {
7229 ret = -ENOMEM;
7230 goto out;
7231 }
7232
fcbfffe2
CH		 7233 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
7234 UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
7235 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7236 if (ret)
7237 pr_err("%s: failed with err %d\n", __func__, ret);
7238
7239 kfree(buffer);
7240out:
7241 return ret;
7242}
7243
7244/**
7245 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7246 * power mode
7247 * @hba: per adapter instance
7248 * @pwr_mode: device power mode to set
7249 *
7250 * Returns 0 if requested power mode is set successfully
7251 * Returns non-zero if failed to set the requested power mode
7252 */
7253static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7254 enum ufs_dev_pwr_mode pwr_mode)
7255{
7256 unsigned char cmd[6] = { START_STOP };
7257 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7258 struct scsi_device *sdp;
7259 unsigned long flags;
57d104c1
SJ		 7260 int ret;
7261
7c48bfd0
AM		 7262 spin_lock_irqsave(hba->host->host_lock, flags);
7263 sdp = hba->sdev_ufs_device;
7264 if (sdp) {
7265 ret = scsi_device_get(sdp);
7266 if (!ret && !scsi_device_online(sdp)) {
7267 ret = -ENODEV;
7268 scsi_device_put(sdp);
7269 }
7270 } else {
7271 ret = -ENODEV;
7272 }
7273 spin_unlock_irqrestore(hba->host->host_lock, flags);
7274
7275 if (ret)
7276 return ret;
57d104c1
SJ		 7277
7278 /*
7279 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7280 * handling, which would wait for host to be resumed. Since we know
7281 * we are functional while we are here, skip host resume in error
7282 * handling context.
7283 */
7284 hba->host->eh_noresume = 1;
7285 if (hba->wlun_dev_clr_ua) {
7286 ret = ufshcd_send_request_sense(hba, sdp);
7287 if (ret)
7288 goto out;
7289 /* Unit attention condition is cleared now */
7290 hba->wlun_dev_clr_ua = false;
7291 }
7292
7293 cmd[4] = pwr_mode << 4;
7294
7295 /*
7296 * Current function would be generally called from the power management
e8064021 7297 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7298 * already suspended childs.
7299 */
fcbfffe2
CH		 7300 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7301 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7302 if (ret) {
7303 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7304 "START_STOP failed for power mode: %d, result %x\n",
7305 pwr_mode, ret);
c65be1a6 7306 if (driver_byte(ret) == DRIVER_SENSE)
21045519 7307 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7308 }
7309
7310 if (!ret)
7311 hba->curr_dev_pwr_mode = pwr_mode;
7312out:
7c48bfd0 7313 scsi_device_put(sdp);
57d104c1
SJ		 7314 hba->host->eh_noresume = 0;
7315 return ret;
7316}
7317
7318static int ufshcd_link_state_transition(struct ufs_hba *hba,
7319 enum uic_link_state req_link_state,
7320 int check_for_bkops)
7321{
7322 int ret = 0;
7323
7324 if (req_link_state == hba->uic_link_state)
7325 return 0;
7326
7327 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7328 ret = ufshcd_uic_hibern8_enter(hba);
7329 if (!ret)
7330 ufshcd_set_link_hibern8(hba);
7331 else
7332 goto out;
7333 }
7334 /*
7335 * If autobkops is enabled, link can't be turned off because
7336 * turning off the link would also turn off the device.
7337 */
7338 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7339 (!check_for_bkops || (check_for_bkops &&
7340 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 7341 /*
7342 * Let's make sure that link is in low power mode, we are doing
7343 * this currently by putting the link in Hibern8. Otherway to
7344 * put the link in low power mode is to send the DME end point
7345 * to device and then send the DME reset command to local
7346 * unipro. But putting the link in hibern8 is much faster.
7347 */
7348 ret = ufshcd_uic_hibern8_enter(hba);
7349 if (ret)
7350 goto out;
57d104c1
SJ		 7351 /*
7352 * Change controller state to "reset state" which
7353 * should also put the link in off/reset state
7354 */
596585a2 7355 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 7356 /*
7357 * TODO: Check if we need any delay to make sure that
7358 * controller is reset
7359 */
7360 ufshcd_set_link_off(hba);
7361 }
7362
7363out:
7364 return ret;
7365}
7366
7367static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7368{
b799fdf7
YG		 7369 /*
7370 * It seems some UFS devices may keep drawing more than sleep current
7371 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7372 * To avoid this situation, add 2ms delay before putting these UFS
7373 * rails in LPM mode.
7374 */
7375 if (!ufshcd_is_link_active(hba) &&
7376 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7377 usleep_range(2000, 2100);
7378
57d104c1
SJ		 7379 /*
7380 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7381 * power.
7382 *
7383 * If UFS device and link is in OFF state, all power supplies (VCC,
7384 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7385 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7386 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7387 *
7388 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7389 * in low power state which would save some power.
7390 */
7391 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7392 !hba->dev_info.is_lu_power_on_wp) {
7393 ufshcd_setup_vreg(hba, false);
7394 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7395 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7396 if (!ufshcd_is_link_active(hba)) {
7397 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7398 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7399 }
7400 }
7401}
7402
7403static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7404{
7405 int ret = 0;
7406
7407 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7408 !hba->dev_info.is_lu_power_on_wp) {
7409 ret = ufshcd_setup_vreg(hba, true);
7410 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7411 if (!ret && !ufshcd_is_link_active(hba)) {
7412 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7413 if (ret)
7414 goto vcc_disable;
7415 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7416 if (ret)
7417 goto vccq_lpm;
7418 }
69d72ac8 7419 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7420 }
7421 goto out;
7422
7423vccq_lpm:
7424 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7425vcc_disable:
7426 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7427out:
7428 return ret;
7429}
7430
7431static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7432{
7433 if (ufshcd_is_link_off(hba))
7434 ufshcd_setup_hba_vreg(hba, false);
7435}
7436
7437static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7438{
7439 if (ufshcd_is_link_off(hba))
7440 ufshcd_setup_hba_vreg(hba, true);
7441}
7442
7a3e97b0 7443/**
57d104c1 7444 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7445 * @hba: per adapter instance
57d104c1
SJ		 7446 * @pm_op: desired low power operation type
7447 *
7448 * This function will try to put the UFS device and link into low power
7449 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7450 * (System PM level).
7451 *
7452 * If this function is called during shutdown, it will make sure that
7453 * both UFS device and UFS link is powered off.
7a3e97b0 7454 *
57d104c1
SJ		 7455 * NOTE: UFS device & link must be active before we enter in this function.
7456 *
7457 * Returns 0 for success and non-zero for failure
7a3e97b0 7458 */
57d104c1 7459static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7460{
57d104c1
SJ		 7461 int ret = 0;
7462 enum ufs_pm_level pm_lvl;
7463 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7464 enum uic_link_state req_link_state;
7465
7466 hba->pm_op_in_progress = 1;
7467 if (!ufshcd_is_shutdown_pm(pm_op)) {
7468 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7469 hba->rpm_lvl : hba->spm_lvl;
7470 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7471 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7472 } else {
7473 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7474 req_link_state = UIC_LINK_OFF_STATE;
7475 }
7476
7a3e97b0 7477 /*
57d104c1
SJ		 7478 * If we can't transition into any of the low power modes
7479 * just gate the clocks.
7a3e97b0 7480 */
1ab27c9c
ST		 7481 ufshcd_hold(hba, false);
7482 hba->clk_gating.is_suspended = true;
7483
401f1e44
SJ		 7484 if (hba->clk_scaling.is_allowed) {
7485 cancel_work_sync(&hba->clk_scaling.suspend_work);
7486 cancel_work_sync(&hba->clk_scaling.resume_work);
7487 ufshcd_suspend_clkscaling(hba);
7488 }
d6fcf81a 7489
57d104c1
SJ		 7490 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7491 req_link_state == UIC_LINK_ACTIVE_STATE) {
7492 goto disable_clks;
7493 }
7a3e97b0 7494
57d104c1
SJ		 7495 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7496 (req_link_state == hba->uic_link_state))
d6fcf81a 7497 goto enable_gating;
57d104c1
SJ		 7498
7499 /* UFS device & link must be active before we enter in this function */
7500 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7501 ret = -EINVAL;
d6fcf81a 7502 goto enable_gating;
57d104c1
SJ		 7503 }
7504
7505 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7506 if (ufshcd_can_autobkops_during_suspend(hba)) {
7507 /*
7508 * The device is idle with no requests in the queue,
7509 * allow background operations if bkops status shows
7510 * that performance might be impacted.
7511 */
7512 ret = ufshcd_urgent_bkops(hba);
7513 if (ret)
7514 goto enable_gating;
7515 } else {
7516 /* make sure that auto bkops is disabled */
7517 ufshcd_disable_auto_bkops(hba);
7518 }
57d104c1
SJ		 7519 }
7520
7521 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7522 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7523 !ufshcd_is_runtime_pm(pm_op))) {
7524 /* ensure that bkops is disabled */
7525 ufshcd_disable_auto_bkops(hba);
7526 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7527 if (ret)
1ab27c9c 7528 goto enable_gating;
57d104c1
SJ		 7529 }
7530
7531 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7532 if (ret)
7533 goto set_dev_active;
7534
7535 ufshcd_vreg_set_lpm(hba);
7536
7537disable_clks:
7538 /*
7539 * Call vendor specific suspend callback. As these callbacks may access
7540 * vendor specific host controller register space call them before the
7541 * host clocks are ON.
7542 */
0263bcd0
YG		 7543 ret = ufshcd_vops_suspend(hba, pm_op);
7544 if (ret)
7545 goto set_link_active;
57d104c1 7546
57d104c1
SJ		 7547 if (!ufshcd_is_link_active(hba))
7548 ufshcd_setup_clocks(hba, false);
7549 else
7550 /* If link is active, device ref_clk can't be switched off */
7551 __ufshcd_setup_clocks(hba, false, true);
7552
1ab27c9c 7553 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7554 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1
SJ		 7555 /*
7556 * Disable the host irq as host controller as there won't be any
0263bcd0 7557 * host controller transaction expected till resume.
57d104c1
SJ		 7558 */
7559 ufshcd_disable_irq(hba);
7560 /* Put the host controller in low power mode if possible */
7561 ufshcd_hba_vreg_set_lpm(hba);
7562 goto out;
7563
57d104c1 7564set_link_active:
401f1e44
SJ		 7565 if (hba->clk_scaling.is_allowed)
7566 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 7567 ufshcd_vreg_set_hpm(hba);
7568 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7569 ufshcd_set_link_active(hba);
7570 else if (ufshcd_is_link_off(hba))
7571 ufshcd_host_reset_and_restore(hba);
7572set_dev_active:
7573 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7574 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7575enable_gating:
401f1e44
SJ		 7576 if (hba->clk_scaling.is_allowed)
7577 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7578 hba->clk_gating.is_suspended = false;
7579 ufshcd_release(hba);
57d104c1
SJ		 7580out:
7581 hba->pm_op_in_progress = 0;
7582 return ret;
7a3e97b0
SY		 7583}
7584
7585/**
57d104c1 7586 * ufshcd_resume - helper function for resume operations
3b1d0580 7587 * @hba: per adapter instance
57d104c1 7588 * @pm_op: runtime PM or system PM
7a3e97b0 7589 *
57d104c1
SJ		 7590 * This function basically brings the UFS device, UniPro link and controller
7591 * to active state.
7592 *
7593 * Returns 0 for success and non-zero for failure
7a3e97b0 7594 */
57d104c1 7595static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7596{
57d104c1
SJ		 7597 int ret;
7598 enum uic_link_state old_link_state;
7599
7600 hba->pm_op_in_progress = 1;
7601 old_link_state = hba->uic_link_state;
7602
7603 ufshcd_hba_vreg_set_hpm(hba);
7604 /* Make sure clocks are enabled before accessing controller */
7605 ret = ufshcd_setup_clocks(hba, true);
7606 if (ret)
7607 goto out;
7608
57d104c1
SJ		 7609 /* enable the host irq as host controller would be active soon */
7610 ret = ufshcd_enable_irq(hba);
7611 if (ret)
7612 goto disable_irq_and_vops_clks;
7613
7614 ret = ufshcd_vreg_set_hpm(hba);
7615 if (ret)
7616 goto disable_irq_and_vops_clks;
7617
7a3e97b0 7618 /*
57d104c1
SJ		 7619 * Call vendor specific resume callback. As these callbacks may access
7620 * vendor specific host controller register space call them when the
7621 * host clocks are ON.
7a3e97b0 7622 */
0263bcd0
YG		 7623 ret = ufshcd_vops_resume(hba, pm_op);
7624 if (ret)
7625 goto disable_vreg;
57d104c1
SJ		 7626
7627 if (ufshcd_is_link_hibern8(hba)) {
7628 ret = ufshcd_uic_hibern8_exit(hba);
7629 if (!ret)
7630 ufshcd_set_link_active(hba);
7631 else
7632 goto vendor_suspend;
7633 } else if (ufshcd_is_link_off(hba)) {
7634 ret = ufshcd_host_reset_and_restore(hba);
7635 /*
7636 * ufshcd_host_reset_and_restore() should have already
7637 * set the link state as active
7638 */
7639 if (ret || !ufshcd_is_link_active(hba))
7640 goto vendor_suspend;
7641 }
7642
7643 if (!ufshcd_is_ufs_dev_active(hba)) {
7644 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7645 if (ret)
7646 goto set_old_link_state;
7647 }
7648
4e768e76
SJ		 7649 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7650 ufshcd_enable_auto_bkops(hba);
7651 else
7652 /*
7653 * If BKOPs operations are urgently needed at this moment then
7654 * keep auto-bkops enabled or else disable it.
7655 */
7656 ufshcd_urgent_bkops(hba);
7657
1ab27c9c
ST		 7658 hba->clk_gating.is_suspended = false;
7659
fcb0c4b0
ST		 7660 if (hba->clk_scaling.is_allowed)
7661 ufshcd_resume_clkscaling(hba);
856b3483 7662
1ab27c9c
ST		 7663 /* Schedule clock gating in case of no access to UFS device yet */
7664 ufshcd_release(hba);
ad448378
AH		 7665
7666 /* Enable Auto-Hibernate if configured */
7667 ufshcd_auto_hibern8_enable(hba);
7668
57d104c1
SJ		 7669 goto out;
7670
7671set_old_link_state:
7672 ufshcd_link_state_transition(hba, old_link_state, 0);
7673vendor_suspend:
0263bcd0 7674 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 7675disable_vreg:
7676 ufshcd_vreg_set_lpm(hba);
7677disable_irq_and_vops_clks:
7678 ufshcd_disable_irq(hba);
401f1e44
SJ		 7679 if (hba->clk_scaling.is_allowed)
7680 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 7681 ufshcd_setup_clocks(hba, false);
7682out:
7683 hba->pm_op_in_progress = 0;
7684 return ret;
7685}
7686
7687/**
7688 * ufshcd_system_suspend - system suspend routine
7689 * @hba: per adapter instance
57d104c1
SJ		 7690 *
7691 * Check the description of ufshcd_suspend() function for more details.
7692 *
7693 * Returns 0 for success and non-zero for failure
7694 */
7695int ufshcd_system_suspend(struct ufs_hba *hba)
7696{
7697 int ret = 0;
7ff5ab47 7698 ktime_t start = ktime_get();
57d104c1
SJ		 7699
7700 if (!hba || !hba->is_powered)
233b594b 7701 return 0;
57d104c1 7702
0b257734
SJ		 7703 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7704 hba->curr_dev_pwr_mode) &&
7705 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7706 hba->uic_link_state))
7707 goto out;
57d104c1 7708
0b257734 7709 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 7710 /*
7711 * UFS device and/or UFS link low power states during runtime
7712 * suspend seems to be different than what is expected during
7713 * system suspend. Hence runtime resume the devic & link and
7714 * let the system suspend low power states to take effect.
7715 * TODO: If resume takes longer time, we might have optimize
7716 * it in future by not resuming everything if possible.
7717 */
7718 ret = ufshcd_runtime_resume(hba);
7719 if (ret)
7720 goto out;
7721 }
7722
7723 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7724out:
7ff5ab47
SJ		 7725 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7726 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7727 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 7728 if (!ret)
7729 hba->is_sys_suspended = true;
57d104c1
SJ		 7730 return ret;
7731}
7732EXPORT_SYMBOL(ufshcd_system_suspend);
7733
7734/**
7735 * ufshcd_system_resume - system resume routine
7736 * @hba: per adapter instance
7737 *
7738 * Returns 0 for success and non-zero for failure
7739 */
7a3e97b0 7740
57d104c1
SJ		 7741int ufshcd_system_resume(struct ufs_hba *hba)
7742{
7ff5ab47
SJ		 7743 int ret = 0;
7744 ktime_t start = ktime_get();
7745
e3ce73d6
YG		 7746 if (!hba)
7747 return -EINVAL;
7748
7749 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 7750 /*
7751 * Let the runtime resume take care of resuming
7752 * if runtime suspended.
7753 */
7ff5ab47
SJ		 7754 goto out;
7755 else
7756 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7757out:
7758 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7759 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7760 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7761 return ret;
7a3e97b0 7762}
57d104c1 7763EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 7764
57d104c1
SJ		 7765/**
7766 * ufshcd_runtime_suspend - runtime suspend routine
7767 * @hba: per adapter instance
7768 *
7769 * Check the description of ufshcd_suspend() function for more details.
7770 *
7771 * Returns 0 for success and non-zero for failure
7772 */
66ec6d59
SRT		 7773int ufshcd_runtime_suspend(struct ufs_hba *hba)
7774{
7ff5ab47
SJ		 7775 int ret = 0;
7776 ktime_t start = ktime_get();
7777
e3ce73d6
YG		 7778 if (!hba)
7779 return -EINVAL;
7780
7781 if (!hba->is_powered)
7ff5ab47
SJ		 7782 goto out;
7783 else
7784 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7785out:
7786 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7787 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7788 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7789 return ret;
66ec6d59
SRT		 7790}
7791EXPORT_SYMBOL(ufshcd_runtime_suspend);
7792
57d104c1
SJ		 7793/**
7794 * ufshcd_runtime_resume - runtime resume routine
7795 * @hba: per adapter instance
7796 *
7797 * This function basically brings the UFS device, UniPro link and controller
7798 * to active state. Following operations are done in this function:
7799 *
7800 * 1. Turn on all the controller related clocks
7801 * 2. Bring the UniPro link out of Hibernate state
7802 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7803 * to active state.
7804 * 4. If auto-bkops is enabled on the device, disable it.
7805 *
7806 * So following would be the possible power state after this function return
7807 * successfully:
7808 * S1: UFS device in Active state with VCC rail ON
7809 * UniPro link in Active state
7810 * All the UFS/UniPro controller clocks are ON
7811 *
7812 * Returns 0 for success and non-zero for failure
7813 */
66ec6d59
SRT		 7814int ufshcd_runtime_resume(struct ufs_hba *hba)
7815{
7ff5ab47
SJ		 7816 int ret = 0;
7817 ktime_t start = ktime_get();
7818
e3ce73d6
YG		 7819 if (!hba)
7820 return -EINVAL;
7821
7822 if (!hba->is_powered)
7ff5ab47
SJ		 7823 goto out;
7824 else
7825 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7826out:
7827 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7828 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7829 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7830 return ret;
66ec6d59
SRT		 7831}
7832EXPORT_SYMBOL(ufshcd_runtime_resume);
7833
7834int ufshcd_runtime_idle(struct ufs_hba *hba)
7835{
7836 return 0;
7837}
7838EXPORT_SYMBOL(ufshcd_runtime_idle);
7839
57d104c1
SJ		 7840/**
7841 * ufshcd_shutdown - shutdown routine
7842 * @hba: per adapter instance
7843 *
7844 * This function would power off both UFS device and UFS link.
7845 *
7846 * Returns 0 always to allow force shutdown even in case of errors.
7847 */
7848int ufshcd_shutdown(struct ufs_hba *hba)
7849{
7850 int ret = 0;
7851
7852 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
7853 goto out;
7854
7855 if (pm_runtime_suspended(hba->dev)) {
7856 ret = ufshcd_runtime_resume(hba);
7857 if (ret)
7858 goto out;
7859 }
7860
7861 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
7862out:
7863 if (ret)
7864 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
7865 /* allow force shutdown even in case of errors */
7866 return 0;
7867}
7868EXPORT_SYMBOL(ufshcd_shutdown);
7869
7a3e97b0 7870/**
3b1d0580 7871 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 7872 * data structure memory
8aa29f19 7873 * @hba: per adapter instance
7a3e97b0 7874 */
3b1d0580 7875void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 7876{
cbb6813e 7877 ufs_sysfs_remove_nodes(hba->dev);
cfdf9c91 7878 scsi_remove_host(hba->host);
7a3e97b0 7879 /* disable interrupts */
2fbd009b 7880 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 7881 ufshcd_hba_stop(hba, true);
7a3e97b0 7882
1ab27c9c 7883 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 7884 if (ufshcd_is_clkscaling_supported(hba))
7885 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 7886 ufshcd_hba_exit(hba);
3b1d0580
VH		 7887}
7888EXPORT_SYMBOL_GPL(ufshcd_remove);
7889
47555a5c
YG		 7890/**
7891 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
7892 * @hba: pointer to Host Bus Adapter (HBA)
7893 */
7894void ufshcd_dealloc_host(struct ufs_hba *hba)
7895{
7896 scsi_host_put(hba->host);
7897}
7898EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
7899
ca3d7bf9
AM		 7900/**
7901 * ufshcd_set_dma_mask - Set dma mask based on the controller
7902 * addressing capability
7903 * @hba: per adapter instance
7904 *
7905 * Returns 0 for success, non-zero for failure
7906 */
7907static int ufshcd_set_dma_mask(struct ufs_hba *hba)
7908{
7909 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
7910 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
7911 return 0;
7912 }
7913 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
7914}
7915
7a3e97b0 7916/**
5c0c28a8 7917 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 7918 * @dev: pointer to device handle
7919 * @hba_handle: driver private handle
7a3e97b0
SY		 7920 * Returns 0 on success, non-zero value on failure
7921 */
5c0c28a8 7922int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 7923{
7924 struct Scsi_Host *host;
7925 struct ufs_hba *hba;
5c0c28a8 7926 int err = 0;
7a3e97b0 7927
3b1d0580
VH		 7928 if (!dev) {
7929 dev_err(dev,
7930 "Invalid memory reference for dev is NULL\n");
7931 err = -ENODEV;
7a3e97b0
SY		 7932 goto out_error;
7933 }
7934
7a3e97b0
SY		 7935 host = scsi_host_alloc(&ufshcd_driver_template,
7936 sizeof(struct ufs_hba));
7937 if (!host) {
3b1d0580 7938 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 7939 err = -ENOMEM;
3b1d0580 7940 goto out_error;
7a3e97b0
SY		 7941 }
7942 hba = shost_priv(host);
7a3e97b0 7943 hba->host = host;
3b1d0580 7944 hba->dev = dev;
5c0c28a8
SRT		 7945 *hba_handle = hba;
7946
566ec9ad
SM		 7947 INIT_LIST_HEAD(&hba->clk_list_head);
7948
5c0c28a8
SRT		 7949out_error:
7950 return err;
7951}
7952EXPORT_SYMBOL(ufshcd_alloc_host);
7953
7954/**
7955 * ufshcd_init - Driver initialization routine
7956 * @hba: per-adapter instance
7957 * @mmio_base: base register address
7958 * @irq: Interrupt line of device
7959 * Returns 0 on success, non-zero value on failure
7960 */
7961int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
7962{
7963 int err;
7964 struct Scsi_Host *host = hba->host;
7965 struct device *dev = hba->dev;
7966
7967 if (!mmio_base) {
7968 dev_err(hba->dev,
7969 "Invalid memory reference for mmio_base is NULL\n");
7970 err = -ENODEV;
7971 goto out_error;
7972 }
7973
3b1d0580
VH		 7974 hba->mmio_base = mmio_base;
7975 hba->irq = irq;
7a3e97b0 7976
a4b0e8a4
PM		 7977 /* Set descriptor lengths to specification defaults */
7978 ufshcd_def_desc_sizes(hba);
7979
aa497613 7980 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 7981 if (err)
7982 goto out_error;
7983
7a3e97b0
SY		 7984 /* Read capabilities registers */
7985 ufshcd_hba_capabilities(hba);
7986
7987 /* Get UFS version supported by the controller */
7988 hba->ufs_version = ufshcd_get_ufs_version(hba);
7989
c01848c6
YG		 7990 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
7991 (hba->ufs_version != UFSHCI_VERSION_11) &&
7992 (hba->ufs_version != UFSHCI_VERSION_20) &&
7993 (hba->ufs_version != UFSHCI_VERSION_21))
7994 dev_err(hba->dev, "invalid UFS version 0x%x\n",
7995 hba->ufs_version);
7996
2fbd009b
SJ		 7997 /* Get Interrupt bit mask per version */
7998 hba->intr_mask = ufshcd_get_intr_mask(hba);
7999
ca3d7bf9
AM		 8000 err = ufshcd_set_dma_mask(hba);
8001 if (err) {
8002 dev_err(hba->dev, "set dma mask failed\n");
8003 goto out_disable;
8004 }
8005
7a3e97b0
SY		 8006 /* Allocate memory for host memory space */
8007 err = ufshcd_memory_alloc(hba);
8008 if (err) {
3b1d0580
VH		 8009 dev_err(hba->dev, "Memory allocation failed\n");
8010 goto out_disable;
7a3e97b0
SY		 8011 }
8012
8013 /* Configure LRB */
8014 ufshcd_host_memory_configure(hba);
8015
8016 host->can_queue = hba->nutrs;
8017 host->cmd_per_lun = hba->nutrs;
8018 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8019 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8020 host->max_channel = UFSHCD_MAX_CHANNEL;
8021 host->unique_id = host->host_no;
8022 host->max_cmd_len = MAX_CDB_SIZE;
8023
7eb584db
DR		 8024 hba->max_pwr_info.is_valid = false;
8025
7a3e97b0 8026 /* Initailize wait queue for task management */
e2933132
SRT		 8027 init_waitqueue_head(&hba->tm_wq);
8028 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 8029
8030 /* Initialize work queues */
e8e7f271 8031 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8032 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8033
6ccf44fe
SJ		 8034 /* Initialize UIC command mutex */
8035 mutex_init(&hba->uic_cmd_mutex);
8036
5a0b0cb9
SRT		 8037 /* Initialize mutex for device management commands */
8038 mutex_init(&hba->dev_cmd.lock);
8039
a3cd5ec5
SJ		 8040 init_rwsem(&hba->clk_scaling_lock);
8041
5a0b0cb9
SRT		 8042 /* Initialize device management tag acquire wait queue */
8043 init_waitqueue_head(&hba->dev_cmd.tag_wq);
8044
1ab27c9c 8045 ufshcd_init_clk_gating(hba);
199ef13c
YG		 8046
8047 /*
8048 * In order to avoid any spurious interrupt immediately after
8049 * registering UFS controller interrupt handler, clear any pending UFS
8050 * interrupt status and disable all the UFS interrupts.
8051 */
8052 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8053 REG_INTERRUPT_STATUS);
8054 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8055 /*
8056 * Make sure that UFS interrupts are disabled and any pending interrupt
8057 * status is cleared before registering UFS interrupt handler.
8058 */
8059 mb();
8060
7a3e97b0 8061 /* IRQ registration */
2953f850 8062 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8063 if (err) {
3b1d0580 8064 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8065 goto exit_gating;
57d104c1
SJ		 8066 } else {
8067 hba->is_irq_enabled = true;
7a3e97b0
SY		 8068 }
8069
3b1d0580 8070 err = scsi_add_host(host, hba->dev);
7a3e97b0 8071 if (err) {
3b1d0580 8072 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8073 goto exit_gating;
7a3e97b0
SY		 8074 }
8075
6ccf44fe
SJ		 8076 /* Host controller enable */
8077 err = ufshcd_hba_enable(hba);
7a3e97b0 8078 if (err) {
6ccf44fe 8079 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 8080 ufshcd_print_host_regs(hba);
6ba65588 8081 ufshcd_print_host_state(hba);
3b1d0580 8082 goto out_remove_scsi_host;
7a3e97b0 8083 }
6ccf44fe 8084
fcb0c4b0 8085 if (ufshcd_is_clkscaling_supported(hba)) {
401f1e44
SJ		 8086 char wq_name[sizeof("ufs_clkscaling_00")];
8087
401f1e44
SJ		 8088 INIT_WORK(&hba->clk_scaling.suspend_work,
8089 ufshcd_clk_scaling_suspend_work);
8090 INIT_WORK(&hba->clk_scaling.resume_work,
8091 ufshcd_clk_scaling_resume_work);
8092
d985c6ea 8093 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
401f1e44
SJ		 8094 host->host_no);
8095 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
8096
fcb0c4b0 8097 ufshcd_clkscaling_init_sysfs(hba);
856b3483
ST		 8098 }
8099
0c8f7586
SJ		 8100 /*
8101 * Set the default power management level for runtime and system PM.
8102 * Default power saving mode is to keep UFS link in Hibern8 state
8103 * and UFS device in sleep state.
8104 */
8105 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8106 UFS_SLEEP_PWR_MODE,
8107 UIC_LINK_HIBERN8_STATE);
8108 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8109 UFS_SLEEP_PWR_MODE,
8110 UIC_LINK_HIBERN8_STATE);
8111
ad448378
AH		 8112 /* Set the default auto-hiberate idle timer value to 150 ms */
8113 if (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) {
8114 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8115 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8116 }
8117
62694735
SRT		 8118 /* Hold auto suspend until async scan completes */
8119 pm_runtime_get_sync(dev);
38135535 8120 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 8121 /*
7caf489b
SJ		 8122 * We are assuming that device wasn't put in sleep/power-down
8123 * state exclusively during the boot stage before kernel.
8124 * This assumption helps avoid doing link startup twice during
8125 * ufshcd_probe_hba().
57d104c1 8126 */
7caf489b 8127 ufshcd_set_ufs_dev_active(hba);
57d104c1 8128
6ccf44fe 8129 async_schedule(ufshcd_async_scan, hba);
cbb6813e 8130 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 8131
7a3e97b0
SY		 8132 return 0;
8133
3b1d0580
VH		 8134out_remove_scsi_host:
8135 scsi_remove_host(hba->host);
1ab27c9c
ST		 8136exit_gating:
8137 ufshcd_exit_clk_gating(hba);
3b1d0580 8138out_disable:
57d104c1 8139 hba->is_irq_enabled = false;
aa497613 8140 ufshcd_hba_exit(hba);
3b1d0580
VH		 8141out_error:
8142 return err;
8143}
8144EXPORT_SYMBOL_GPL(ufshcd_init);
8145
3b1d0580
VH		 8146MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8147MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8148MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8149MODULE_LICENSE("GPL");
8150MODULE_VERSION(UFSHCD_DRIVER_VERSION);
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