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7a3e97b0 SY |
1 | /* |
2 | * Universal Flash Storage Host controller driver | |
3 | * | |
4 | * This code is based on drivers/scsi/ufs/ufshci.h | |
3b1d0580 | 5 | * Copyright (C) 2011-2013 Samsung India Software Operations |
7a3e97b0 | 6 | * |
3b1d0580 VH |
7 | * Authors: |
8 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
9 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
7a3e97b0 SY |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version 2 | |
14 | * of the License, or (at your option) any later version. | |
3b1d0580 VH |
15 | * See the COPYING file in the top-level directory or visit |
16 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
7a3e97b0 SY |
17 | * |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
3b1d0580 VH |
23 | * This program is provided "AS IS" and "WITH ALL FAULTS" and |
24 | * without warranty of any kind. You are solely responsible for | |
25 | * determining the appropriateness of using and distributing | |
26 | * the program and assume all risks associated with your exercise | |
27 | * of rights with respect to the program, including but not limited | |
28 | * to infringement of third party rights, the risks and costs of | |
29 | * program errors, damage to or loss of data, programs or equipment, | |
30 | * and unavailability or interruption of operations. Under no | |
31 | * circumstances will the contributor of this Program be liable for | |
32 | * any damages of any kind arising from your use or distribution of | |
33 | * this program. | |
7a3e97b0 SY |
34 | */ |
35 | ||
36 | #ifndef _UFSHCI_H | |
37 | #define _UFSHCI_H | |
38 | ||
39 | enum { | |
40 | TASK_REQ_UPIU_SIZE_DWORDS = 8, | |
41 | TASK_RSP_UPIU_SIZE_DWORDS = 8, | |
68078d5c | 42 | ALIGNED_UPIU_SIZE = 512, |
7a3e97b0 SY |
43 | }; |
44 | ||
45 | /* UFSHCI Registers */ | |
46 | enum { | |
47 | REG_CONTROLLER_CAPABILITIES = 0x00, | |
48 | REG_UFS_VERSION = 0x08, | |
49 | REG_CONTROLLER_DEV_ID = 0x10, | |
50 | REG_CONTROLLER_PROD_ID = 0x14, | |
51 | REG_INTERRUPT_STATUS = 0x20, | |
52 | REG_INTERRUPT_ENABLE = 0x24, | |
53 | REG_CONTROLLER_STATUS = 0x30, | |
54 | REG_CONTROLLER_ENABLE = 0x34, | |
55 | REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, | |
56 | REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, | |
57 | REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, | |
58 | REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, | |
59 | REG_UIC_ERROR_CODE_DME = 0x48, | |
60 | REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, | |
61 | REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, | |
62 | REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, | |
63 | REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, | |
64 | REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, | |
65 | REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, | |
66 | REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, | |
67 | REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, | |
68 | REG_UTP_TASK_REQ_DOOR_BELL = 0x78, | |
69 | REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, | |
70 | REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, | |
71 | REG_UIC_COMMAND = 0x90, | |
72 | REG_UIC_COMMAND_ARG_1 = 0x94, | |
73 | REG_UIC_COMMAND_ARG_2 = 0x98, | |
74 | REG_UIC_COMMAND_ARG_3 = 0x9C, | |
75 | }; | |
76 | ||
77 | /* Controller capability masks */ | |
78 | enum { | |
79 | MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, | |
80 | MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, | |
81 | MASK_64_ADDRESSING_SUPPORT = 0x01000000, | |
82 | MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, | |
83 | MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, | |
84 | }; | |
85 | ||
86 | /* UFS Version 08h */ | |
87 | #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) | |
88 | #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) | |
89 | ||
90 | /* Controller UFSHCI version */ | |
91 | enum { | |
92 | UFSHCI_VERSION_10 = 0x00010000, | |
93 | UFSHCI_VERSION_11 = 0x00010100, | |
94 | }; | |
95 | ||
96 | /* | |
97 | * HCDDID - Host Controller Identification Descriptor | |
98 | * - Device ID and Device Class 10h | |
99 | */ | |
100 | #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) | |
101 | #define DEVICE_ID UFS_MASK(0xFF, 24) | |
102 | ||
103 | /* | |
104 | * HCPMID - Host Controller Identification Descriptor | |
105 | * - Product/Manufacturer ID 14h | |
106 | */ | |
107 | #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) | |
108 | #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) | |
109 | ||
110 | #define UFS_BIT(x) (1L << (x)) | |
111 | ||
112 | #define UTP_TRANSFER_REQ_COMPL UFS_BIT(0) | |
113 | #define UIC_DME_END_PT_RESET UFS_BIT(1) | |
114 | #define UIC_ERROR UFS_BIT(2) | |
115 | #define UIC_TEST_MODE UFS_BIT(3) | |
116 | #define UIC_POWER_MODE UFS_BIT(4) | |
117 | #define UIC_HIBERNATE_EXIT UFS_BIT(5) | |
118 | #define UIC_HIBERNATE_ENTER UFS_BIT(6) | |
119 | #define UIC_LINK_LOST UFS_BIT(7) | |
120 | #define UIC_LINK_STARTUP UFS_BIT(8) | |
121 | #define UTP_TASK_REQ_COMPL UFS_BIT(9) | |
122 | #define UIC_COMMAND_COMPL UFS_BIT(10) | |
123 | #define DEVICE_FATAL_ERROR UFS_BIT(11) | |
124 | #define CONTROLLER_FATAL_ERROR UFS_BIT(16) | |
125 | #define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17) | |
126 | ||
57d104c1 SJ |
127 | #define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\ |
128 | UIC_HIBERNATE_EXIT |\ | |
129 | UIC_POWER_MODE) | |
130 | ||
131 | #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) | |
53b3d9c3 | 132 | |
7a3e97b0 SY |
133 | #define UFSHCD_ERROR_MASK (UIC_ERROR |\ |
134 | DEVICE_FATAL_ERROR |\ | |
135 | CONTROLLER_FATAL_ERROR |\ | |
136 | SYSTEM_BUS_FATAL_ERROR) | |
137 | ||
138 | #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ | |
139 | CONTROLLER_FATAL_ERROR |\ | |
140 | SYSTEM_BUS_FATAL_ERROR) | |
141 | ||
142 | /* HCS - Host Controller Status 30h */ | |
143 | #define DEVICE_PRESENT UFS_BIT(0) | |
144 | #define UTP_TRANSFER_REQ_LIST_READY UFS_BIT(1) | |
145 | #define UTP_TASK_REQ_LIST_READY UFS_BIT(2) | |
146 | #define UIC_COMMAND_READY UFS_BIT(3) | |
147 | #define HOST_ERROR_INDICATOR UFS_BIT(4) | |
148 | #define DEVICE_ERROR_INDICATOR UFS_BIT(5) | |
149 | #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) | |
150 | ||
53b3d9c3 SJ |
151 | enum { |
152 | PWR_OK = 0x0, | |
153 | PWR_LOCAL = 0x01, | |
154 | PWR_REMOTE = 0x02, | |
155 | PWR_BUSY = 0x03, | |
156 | PWR_ERROR_CAP = 0x04, | |
157 | PWR_FATAL_ERROR = 0x05, | |
158 | }; | |
159 | ||
7a3e97b0 SY |
160 | /* HCE - Host Controller Enable 34h */ |
161 | #define CONTROLLER_ENABLE UFS_BIT(0) | |
162 | #define CONTROLLER_DISABLE 0x0 | |
163 | ||
164 | /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ | |
165 | #define UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31) | |
166 | #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F | |
167 | ||
168 | /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ | |
169 | #define UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31) | |
170 | #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF | |
171 | #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 | |
172 | ||
173 | /* UECN - Host UIC Error Code Network Layer 40h */ | |
174 | #define UIC_NETWORK_LAYER_ERROR UFS_BIT(31) | |
175 | #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 | |
176 | ||
177 | /* UECT - Host UIC Error Code Transport Layer 44h */ | |
178 | #define UIC_TRANSPORT_LAYER_ERROR UFS_BIT(31) | |
179 | #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F | |
180 | ||
181 | /* UECDME - Host UIC Error Code DME 48h */ | |
182 | #define UIC_DME_ERROR UFS_BIT(31) | |
183 | #define UIC_DME_ERROR_CODE_MASK 0x1 | |
184 | ||
185 | #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF | |
186 | #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) | |
187 | #define INT_AGGR_COUNTER_AND_TIMER_RESET UFS_BIT(16) | |
188 | #define INT_AGGR_STATUS_BIT UFS_BIT(20) | |
189 | #define INT_AGGR_PARAM_WRITE UFS_BIT(24) | |
190 | #define INT_AGGR_ENABLE UFS_BIT(31) | |
191 | ||
192 | /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ | |
193 | #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT UFS_BIT(0) | |
194 | ||
195 | /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ | |
196 | #define UTP_TASK_REQ_LIST_RUN_STOP_BIT UFS_BIT(0) | |
197 | ||
198 | /* UICCMD - UIC Command */ | |
199 | #define COMMAND_OPCODE_MASK 0xFF | |
200 | #define GEN_SELECTOR_INDEX_MASK 0xFFFF | |
201 | ||
202 | #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) | |
203 | #define RESET_LEVEL 0xFF | |
204 | ||
205 | #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) | |
206 | #define CONFIG_RESULT_CODE_MASK 0xFF | |
207 | #define GENERIC_ERROR_CODE_MASK 0xFF | |
208 | ||
12b4fdb4 SJ |
209 | #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ |
210 | ((sel) & 0xFFFF)) | |
211 | #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) | |
212 | #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) | |
213 | #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) | |
214 | ||
7a3e97b0 | 215 | /* UIC Commands */ |
57d104c1 | 216 | enum uic_cmd_dme { |
7a3e97b0 SY |
217 | UIC_CMD_DME_GET = 0x01, |
218 | UIC_CMD_DME_SET = 0x02, | |
219 | UIC_CMD_DME_PEER_GET = 0x03, | |
220 | UIC_CMD_DME_PEER_SET = 0x04, | |
221 | UIC_CMD_DME_POWERON = 0x10, | |
222 | UIC_CMD_DME_POWEROFF = 0x11, | |
223 | UIC_CMD_DME_ENABLE = 0x12, | |
224 | UIC_CMD_DME_RESET = 0x14, | |
225 | UIC_CMD_DME_END_PT_RST = 0x15, | |
226 | UIC_CMD_DME_LINK_STARTUP = 0x16, | |
227 | UIC_CMD_DME_HIBER_ENTER = 0x17, | |
228 | UIC_CMD_DME_HIBER_EXIT = 0x18, | |
229 | UIC_CMD_DME_TEST_MODE = 0x1A, | |
230 | }; | |
231 | ||
232 | /* UIC Config result code / Generic error code */ | |
233 | enum { | |
234 | UIC_CMD_RESULT_SUCCESS = 0x00, | |
235 | UIC_CMD_RESULT_INVALID_ATTR = 0x01, | |
236 | UIC_CMD_RESULT_FAILURE = 0x01, | |
237 | UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, | |
238 | UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, | |
239 | UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, | |
240 | UIC_CMD_RESULT_BAD_INDEX = 0x05, | |
241 | UIC_CMD_RESULT_LOCKED_ATTR = 0x06, | |
242 | UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, | |
243 | UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, | |
244 | UIC_CMD_RESULT_BUSY = 0x09, | |
245 | UIC_CMD_RESULT_DME_FAILURE = 0x0A, | |
246 | }; | |
247 | ||
248 | #define MASK_UIC_COMMAND_RESULT 0xFF | |
249 | ||
7d568652 SJ |
250 | #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) |
251 | #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) | |
7a3e97b0 SY |
252 | |
253 | /* Interrupt disable masks */ | |
254 | enum { | |
255 | /* Interrupt disable mask for UFSHCI v1.0 */ | |
2fbd009b SJ |
256 | INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, |
257 | INTERRUPT_MASK_RW_VER_10 = 0x30000, | |
7a3e97b0 SY |
258 | |
259 | /* Interrupt disable mask for UFSHCI v1.1 */ | |
2fbd009b | 260 | INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, |
7a3e97b0 SY |
261 | }; |
262 | ||
263 | /* | |
264 | * Request Descriptor Definitions | |
265 | */ | |
266 | ||
267 | /* Transfer request command type */ | |
268 | enum { | |
269 | UTP_CMD_TYPE_SCSI = 0x0, | |
270 | UTP_CMD_TYPE_UFS = 0x1, | |
271 | UTP_CMD_TYPE_DEV_MANAGE = 0x2, | |
272 | }; | |
273 | ||
274 | enum { | |
275 | UTP_SCSI_COMMAND = 0x00000000, | |
276 | UTP_NATIVE_UFS_COMMAND = 0x10000000, | |
277 | UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, | |
278 | UTP_REQ_DESC_INT_CMD = 0x01000000, | |
279 | }; | |
280 | ||
281 | /* UTP Transfer Request Data Direction (DD) */ | |
282 | enum { | |
283 | UTP_NO_DATA_TRANSFER = 0x00000000, | |
284 | UTP_HOST_TO_DEVICE = 0x02000000, | |
285 | UTP_DEVICE_TO_HOST = 0x04000000, | |
286 | }; | |
287 | ||
288 | /* Overall command status values */ | |
289 | enum { | |
290 | OCS_SUCCESS = 0x0, | |
291 | OCS_INVALID_CMD_TABLE_ATTR = 0x1, | |
292 | OCS_INVALID_PRDT_ATTR = 0x2, | |
293 | OCS_MISMATCH_DATA_BUF_SIZE = 0x3, | |
294 | OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, | |
295 | OCS_PEER_COMM_FAILURE = 0x5, | |
296 | OCS_ABORTED = 0x6, | |
297 | OCS_FATAL_ERROR = 0x7, | |
298 | OCS_INVALID_COMMAND_STATUS = 0x0F, | |
299 | MASK_OCS = 0x0F, | |
300 | }; | |
301 | ||
eeda4749 AM |
302 | /* The maximum length of the data byte count field in the PRDT is 256KB */ |
303 | #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) | |
304 | /* The granularity of the data byte count field in the PRDT is 32-bit */ | |
305 | #define PRDT_DATA_BYTE_COUNT_PAD 4 | |
306 | ||
7a3e97b0 SY |
307 | /** |
308 | * struct ufshcd_sg_entry - UFSHCI PRD Entry | |
309 | * @base_addr: Lower 32bit physical address DW-0 | |
310 | * @upper_addr: Upper 32bit physical address DW-1 | |
311 | * @reserved: Reserved for future use DW-2 | |
312 | * @size: size of physical segment DW-3 | |
313 | */ | |
314 | struct ufshcd_sg_entry { | |
e8c8e82a SRT |
315 | __le32 base_addr; |
316 | __le32 upper_addr; | |
317 | __le32 reserved; | |
318 | __le32 size; | |
7a3e97b0 SY |
319 | }; |
320 | ||
321 | /** | |
322 | * struct utp_transfer_cmd_desc - UFS Command Descriptor structure | |
323 | * @command_upiu: Command UPIU Frame address | |
324 | * @response_upiu: Response UPIU Frame address | |
325 | * @prd_table: Physical Region Descriptor | |
326 | */ | |
327 | struct utp_transfer_cmd_desc { | |
328 | u8 command_upiu[ALIGNED_UPIU_SIZE]; | |
329 | u8 response_upiu[ALIGNED_UPIU_SIZE]; | |
330 | struct ufshcd_sg_entry prd_table[SG_ALL]; | |
331 | }; | |
332 | ||
333 | /** | |
334 | * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD | |
335 | * @dword0: Descriptor Header DW0 | |
336 | * @dword1: Descriptor Header DW1 | |
337 | * @dword2: Descriptor Header DW2 | |
338 | * @dword3: Descriptor Header DW3 | |
339 | */ | |
340 | struct request_desc_header { | |
e8c8e82a SRT |
341 | __le32 dword_0; |
342 | __le32 dword_1; | |
343 | __le32 dword_2; | |
344 | __le32 dword_3; | |
7a3e97b0 SY |
345 | }; |
346 | ||
347 | /** | |
348 | * struct utp_transfer_req_desc - UTRD structure | |
349 | * @header: UTRD header DW-0 to DW-3 | |
350 | * @command_desc_base_addr_lo: UCD base address low DW-4 | |
351 | * @command_desc_base_addr_hi: UCD base address high DW-5 | |
352 | * @response_upiu_length: response UPIU length DW-6 | |
353 | * @response_upiu_offset: response UPIU offset DW-6 | |
354 | * @prd_table_length: Physical region descriptor length DW-7 | |
355 | * @prd_table_offset: Physical region descriptor offset DW-7 | |
356 | */ | |
357 | struct utp_transfer_req_desc { | |
358 | ||
359 | /* DW 0-3 */ | |
360 | struct request_desc_header header; | |
361 | ||
362 | /* DW 4-5*/ | |
e8c8e82a SRT |
363 | __le32 command_desc_base_addr_lo; |
364 | __le32 command_desc_base_addr_hi; | |
7a3e97b0 SY |
365 | |
366 | /* DW 6 */ | |
e8c8e82a SRT |
367 | __le16 response_upiu_length; |
368 | __le16 response_upiu_offset; | |
7a3e97b0 SY |
369 | |
370 | /* DW 7 */ | |
e8c8e82a SRT |
371 | __le16 prd_table_length; |
372 | __le16 prd_table_offset; | |
7a3e97b0 SY |
373 | }; |
374 | ||
375 | /** | |
376 | * struct utp_task_req_desc - UTMRD structure | |
377 | * @header: UTMRD header DW-0 to DW-3 | |
378 | * @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11 | |
379 | * @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19 | |
380 | */ | |
381 | struct utp_task_req_desc { | |
382 | ||
383 | /* DW 0-3 */ | |
384 | struct request_desc_header header; | |
385 | ||
386 | /* DW 4-11 */ | |
e8c8e82a | 387 | __le32 task_req_upiu[TASK_REQ_UPIU_SIZE_DWORDS]; |
7a3e97b0 SY |
388 | |
389 | /* DW 12-19 */ | |
e8c8e82a | 390 | __le32 task_rsp_upiu[TASK_RSP_UPIU_SIZE_DWORDS]; |
7a3e97b0 SY |
391 | }; |
392 | ||
393 | #endif /* End of Header */ |