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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
48a31030 OZ |
2 | /* |
3 | * Driver for Western Digital WD7193, WD7197 and WD7296 SCSI cards | |
4 | * Copyright 2013 Ondrej Zary | |
5 | * | |
6 | * Original driver by | |
7 | * Aaron Dewell <dewell@woods.net> | |
8 | * Gaerti <Juergen.Gaertner@mbox.si.uni-hannover.de> | |
9 | * | |
10 | * HW documentation available in book: | |
11 | * | |
12 | * SPIDER Command Protocol | |
13 | * by Chandru M. Sippy | |
14 | * SCSI Storage Products (MCP) | |
15 | * Western Digital Corporation | |
16 | * 09-15-95 | |
17 | * | |
18 | * http://web.archive.org/web/20070717175254/http://sun1.rrzn.uni-hannover.de/gaertner.juergen/wd719x/Linux/Docu/Spider/ | |
19 | */ | |
20 | ||
21 | /* | |
22 | * Driver workflow: | |
23 | * 1. SCSI command is transformed to SCB (Spider Control Block) by the | |
24 | * queuecommand function. | |
25 | * 2. The address of the SCB is stored in a list to be able to access it, if | |
26 | * something goes wrong. | |
27 | * 3. The address of the SCB is written to the Controller, which loads the SCB | |
28 | * via BM-DMA and processes it. | |
29 | * 4. After it has finished, it generates an interrupt, and sets registers. | |
30 | * | |
31 | * flaws: | |
32 | * - abort/reset functions | |
33 | * | |
34 | * ToDo: | |
35 | * - tagged queueing | |
36 | */ | |
37 | ||
38 | #include <linux/interrupt.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/firmware.h> | |
43 | #include <linux/eeprom_93cx6.h> | |
44 | #include <scsi/scsi_cmnd.h> | |
45 | #include <scsi/scsi_device.h> | |
46 | #include <scsi/scsi_host.h> | |
47 | #include "wd719x.h" | |
48 | ||
49 | /* low-level register access */ | |
50 | static inline u8 wd719x_readb(struct wd719x *wd, u8 reg) | |
51 | { | |
52 | return ioread8(wd->base + reg); | |
53 | } | |
54 | ||
55 | static inline u32 wd719x_readl(struct wd719x *wd, u8 reg) | |
56 | { | |
57 | return ioread32(wd->base + reg); | |
58 | } | |
59 | ||
60 | static inline void wd719x_writeb(struct wd719x *wd, u8 reg, u8 val) | |
61 | { | |
62 | iowrite8(val, wd->base + reg); | |
63 | } | |
64 | ||
65 | static inline void wd719x_writew(struct wd719x *wd, u8 reg, u16 val) | |
66 | { | |
67 | iowrite16(val, wd->base + reg); | |
68 | } | |
69 | ||
70 | static inline void wd719x_writel(struct wd719x *wd, u8 reg, u32 val) | |
71 | { | |
72 | iowrite32(val, wd->base + reg); | |
73 | } | |
74 | ||
75 | /* wait until the command register is ready */ | |
76 | static inline int wd719x_wait_ready(struct wd719x *wd) | |
77 | { | |
78 | int i = 0; | |
79 | ||
80 | do { | |
81 | if (wd719x_readb(wd, WD719X_AMR_COMMAND) == WD719X_CMD_READY) | |
82 | return 0; | |
83 | udelay(1); | |
84 | } while (i++ < WD719X_WAIT_FOR_CMD_READY); | |
85 | ||
86 | dev_err(&wd->pdev->dev, "command register is not ready: 0x%02x\n", | |
87 | wd719x_readb(wd, WD719X_AMR_COMMAND)); | |
88 | ||
89 | return -ETIMEDOUT; | |
90 | } | |
91 | ||
92 | /* poll interrupt status register until command finishes */ | |
93 | static inline int wd719x_wait_done(struct wd719x *wd, int timeout) | |
94 | { | |
95 | u8 status; | |
96 | ||
97 | while (timeout > 0) { | |
98 | status = wd719x_readb(wd, WD719X_AMR_INT_STATUS); | |
99 | if (status) | |
100 | break; | |
101 | timeout--; | |
102 | udelay(1); | |
103 | } | |
104 | ||
105 | if (timeout <= 0) { | |
106 | dev_err(&wd->pdev->dev, "direct command timed out\n"); | |
107 | return -ETIMEDOUT; | |
108 | } | |
109 | ||
110 | if (status != WD719X_INT_NOERRORS) { | |
5da1faa0 OZ |
111 | u8 sue = wd719x_readb(wd, WD719X_AMR_SCB_ERROR); |
112 | /* we get this after wd719x_dev_reset, it's not an error */ | |
113 | if (sue == WD719X_SUE_TERM) | |
114 | return 0; | |
115 | /* we get this after wd719x_bus_reset, it's not an error */ | |
116 | if (sue == WD719X_SUE_RESET) | |
117 | return 0; | |
48a31030 | 118 | dev_err(&wd->pdev->dev, "direct command failed, status 0x%02x, SUE 0x%02x\n", |
5da1faa0 | 119 | status, sue); |
48a31030 OZ |
120 | return -EIO; |
121 | } | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static int wd719x_direct_cmd(struct wd719x *wd, u8 opcode, u8 dev, u8 lun, | |
127 | u8 tag, dma_addr_t data, int timeout) | |
128 | { | |
129 | int ret = 0; | |
130 | ||
131 | /* clear interrupt status register (allow command register to clear) */ | |
132 | wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE); | |
133 | ||
134 | /* Wait for the Command register to become free */ | |
135 | if (wd719x_wait_ready(wd)) | |
136 | return -ETIMEDOUT; | |
137 | ||
5da1faa0 OZ |
138 | /* disable interrupts except for RESET/ABORT (it breaks them) */ |
139 | if (opcode != WD719X_CMD_BUSRESET && opcode != WD719X_CMD_ABORT && | |
140 | opcode != WD719X_CMD_ABORT_TAG && opcode != WD719X_CMD_RESET) | |
141 | dev |= WD719X_DISABLE_INT; | |
48a31030 OZ |
142 | wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, dev); |
143 | wd719x_writeb(wd, WD719X_AMR_CMD_PARAM_2, lun); | |
144 | wd719x_writeb(wd, WD719X_AMR_CMD_PARAM_3, tag); | |
145 | if (data) | |
146 | wd719x_writel(wd, WD719X_AMR_SCB_IN, data); | |
147 | ||
148 | /* clear interrupt status register again */ | |
149 | wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE); | |
150 | ||
151 | /* Now, write the command */ | |
152 | wd719x_writeb(wd, WD719X_AMR_COMMAND, opcode); | |
153 | ||
154 | if (timeout) /* wait for the command to complete */ | |
155 | ret = wd719x_wait_done(wd, timeout); | |
156 | ||
157 | /* clear interrupt status register (clean up) */ | |
158 | if (opcode != WD719X_CMD_READ_FIRMVER) | |
159 | wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE); | |
160 | ||
161 | return ret; | |
162 | } | |
163 | ||
164 | static void wd719x_destroy(struct wd719x *wd) | |
165 | { | |
48a31030 OZ |
166 | /* stop the RISC */ |
167 | if (wd719x_direct_cmd(wd, WD719X_CMD_SLEEP, 0, 0, 0, 0, | |
168 | WD719X_WAIT_FOR_RISC)) | |
169 | dev_warn(&wd->pdev->dev, "RISC sleep command failed\n"); | |
170 | /* disable RISC */ | |
171 | wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0); | |
172 | ||
d9c30dbc CH |
173 | WARN_ON_ONCE(!list_empty(&wd->active_scbs)); |
174 | ||
48a31030 | 175 | /* free internal buffers */ |
236bd823 CH |
176 | dma_free_coherent(&wd->pdev->dev, wd->fw_size, wd->fw_virt, |
177 | wd->fw_phys); | |
48a31030 | 178 | wd->fw_virt = NULL; |
236bd823 CH |
179 | dma_free_coherent(&wd->pdev->dev, WD719X_HASH_TABLE_SIZE, wd->hash_virt, |
180 | wd->hash_phys); | |
48a31030 | 181 | wd->hash_virt = NULL; |
236bd823 CH |
182 | dma_free_coherent(&wd->pdev->dev, sizeof(struct wd719x_host_param), |
183 | wd->params, wd->params_phys); | |
48a31030 OZ |
184 | wd->params = NULL; |
185 | free_irq(wd->pdev->irq, wd); | |
186 | } | |
187 | ||
fde46e96 CH |
188 | /* finish a SCSI command, unmap buffers */ |
189 | static void wd719x_finish_cmd(struct wd719x_scb *scb, int result) | |
48a31030 | 190 | { |
fde46e96 | 191 | struct scsi_cmnd *cmd = scb->cmd; |
48a31030 | 192 | struct wd719x *wd = shost_priv(cmd->device->host); |
48a31030 | 193 | |
fde46e96 CH |
194 | list_del(&scb->list); |
195 | ||
196 | dma_unmap_single(&wd->pdev->dev, scb->phys, | |
197 | sizeof(struct wd719x_scb), DMA_BIDIRECTIONAL); | |
198 | scsi_dma_unmap(cmd); | |
199 | dma_unmap_single(&wd->pdev->dev, cmd->SCp.dma_handle, | |
200 | SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); | |
201 | ||
48a31030 OZ |
202 | cmd->result = result << 16; |
203 | cmd->scsi_done(cmd); | |
204 | } | |
205 | ||
206 | /* Build a SCB and send it to the card */ | |
207 | static int wd719x_queuecommand(struct Scsi_Host *sh, struct scsi_cmnd *cmd) | |
208 | { | |
209 | int i, count_sg; | |
210 | unsigned long flags; | |
fde46e96 | 211 | struct wd719x_scb *scb = scsi_cmd_priv(cmd); |
48a31030 | 212 | struct wd719x *wd = shost_priv(sh); |
48a31030 | 213 | |
48a31030 | 214 | scb->cmd = cmd; |
48a31030 OZ |
215 | |
216 | scb->CDB_tag = 0; /* Tagged queueing not supported yet */ | |
217 | scb->devid = cmd->device->id; | |
218 | scb->lun = cmd->device->lun; | |
219 | ||
220 | /* copy the command */ | |
221 | memcpy(scb->CDB, cmd->cmnd, cmd->cmd_len); | |
222 | ||
fde46e96 CH |
223 | /* map SCB */ |
224 | scb->phys = dma_map_single(&wd->pdev->dev, scb, sizeof(*scb), | |
225 | DMA_BIDIRECTIONAL); | |
226 | ||
227 | if (dma_mapping_error(&wd->pdev->dev, scb->phys)) | |
228 | goto out_error; | |
229 | ||
48a31030 OZ |
230 | /* map sense buffer */ |
231 | scb->sense_buf_length = SCSI_SENSE_BUFFERSIZE; | |
232 | cmd->SCp.dma_handle = dma_map_single(&wd->pdev->dev, cmd->sense_buffer, | |
233 | SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); | |
fde46e96 CH |
234 | if (dma_mapping_error(&wd->pdev->dev, cmd->SCp.dma_handle)) |
235 | goto out_unmap_scb; | |
48a31030 OZ |
236 | scb->sense_buf = cpu_to_le32(cmd->SCp.dma_handle); |
237 | ||
238 | /* request autosense */ | |
239 | scb->SCB_options |= WD719X_SCB_FLAGS_AUTO_REQUEST_SENSE; | |
240 | ||
241 | /* check direction */ | |
242 | if (cmd->sc_data_direction == DMA_TO_DEVICE) | |
243 | scb->SCB_options |= WD719X_SCB_FLAGS_CHECK_DIRECTION | |
244 | | WD719X_SCB_FLAGS_PCI_TO_SCSI; | |
245 | else if (cmd->sc_data_direction == DMA_FROM_DEVICE) | |
246 | scb->SCB_options |= WD719X_SCB_FLAGS_CHECK_DIRECTION; | |
247 | ||
248 | /* Scather/gather */ | |
249 | count_sg = scsi_dma_map(cmd); | |
fde46e96 CH |
250 | if (count_sg < 0) |
251 | goto out_unmap_sense; | |
48a31030 OZ |
252 | BUG_ON(count_sg > WD719X_SG); |
253 | ||
254 | if (count_sg) { | |
255 | struct scatterlist *sg; | |
256 | ||
257 | scb->data_length = cpu_to_le32(count_sg * | |
258 | sizeof(struct wd719x_sglist)); | |
259 | scb->data_p = cpu_to_le32(scb->phys + | |
260 | offsetof(struct wd719x_scb, sg_list)); | |
261 | ||
262 | scsi_for_each_sg(cmd, sg, count_sg, i) { | |
263 | scb->sg_list[i].ptr = cpu_to_le32(sg_dma_address(sg)); | |
264 | scb->sg_list[i].length = cpu_to_le32(sg_dma_len(sg)); | |
265 | } | |
266 | scb->SCB_options |= WD719X_SCB_FLAGS_DO_SCATTER_GATHER; | |
267 | } else { /* zero length */ | |
268 | scb->data_length = 0; | |
269 | scb->data_p = 0; | |
270 | } | |
271 | ||
fde46e96 CH |
272 | spin_lock_irqsave(wd->sh->host_lock, flags); |
273 | ||
48a31030 OZ |
274 | /* check if the Command register is free */ |
275 | if (wd719x_readb(wd, WD719X_AMR_COMMAND) != WD719X_CMD_READY) { | |
276 | spin_unlock_irqrestore(wd->sh->host_lock, flags); | |
277 | return SCSI_MLQUEUE_HOST_BUSY; | |
278 | } | |
279 | ||
fde46e96 CH |
280 | list_add(&scb->list, &wd->active_scbs); |
281 | ||
48a31030 OZ |
282 | /* write pointer to the AMR */ |
283 | wd719x_writel(wd, WD719X_AMR_SCB_IN, scb->phys); | |
284 | /* send SCB opcode */ | |
285 | wd719x_writeb(wd, WD719X_AMR_COMMAND, WD719X_CMD_PROCESS_SCB); | |
286 | ||
287 | spin_unlock_irqrestore(wd->sh->host_lock, flags); | |
fde46e96 | 288 | return 0; |
48a31030 | 289 | |
fde46e96 CH |
290 | out_unmap_sense: |
291 | dma_unmap_single(&wd->pdev->dev, cmd->SCp.dma_handle, | |
292 | SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); | |
293 | out_unmap_scb: | |
294 | dma_unmap_single(&wd->pdev->dev, scb->phys, sizeof(*scb), | |
295 | DMA_BIDIRECTIONAL); | |
296 | out_error: | |
297 | cmd->result = DID_ERROR << 16; | |
298 | cmd->scsi_done(cmd); | |
48a31030 OZ |
299 | return 0; |
300 | } | |
301 | ||
302 | static int wd719x_chip_init(struct wd719x *wd) | |
303 | { | |
304 | int i, ret; | |
305 | u32 risc_init[3]; | |
306 | const struct firmware *fw_wcs, *fw_risc; | |
307 | const char fwname_wcs[] = "wd719x-wcs.bin"; | |
308 | const char fwname_risc[] = "wd719x-risc.bin"; | |
309 | ||
310 | memset(wd->hash_virt, 0, WD719X_HASH_TABLE_SIZE); | |
311 | ||
312 | /* WCS (sequencer) firmware */ | |
313 | ret = request_firmware(&fw_wcs, fwname_wcs, &wd->pdev->dev); | |
314 | if (ret) { | |
315 | dev_err(&wd->pdev->dev, "Unable to load firmware %s: %d\n", | |
316 | fwname_wcs, ret); | |
317 | return ret; | |
318 | } | |
319 | /* RISC firmware */ | |
320 | ret = request_firmware(&fw_risc, fwname_risc, &wd->pdev->dev); | |
321 | if (ret) { | |
322 | dev_err(&wd->pdev->dev, "Unable to load firmware %s: %d\n", | |
323 | fwname_risc, ret); | |
324 | release_firmware(fw_wcs); | |
325 | return ret; | |
326 | } | |
327 | wd->fw_size = ALIGN(fw_wcs->size, 4) + fw_risc->size; | |
328 | ||
329 | if (!wd->fw_virt) | |
236bd823 CH |
330 | wd->fw_virt = dma_alloc_coherent(&wd->pdev->dev, wd->fw_size, |
331 | &wd->fw_phys, GFP_KERNEL); | |
48a31030 OZ |
332 | if (!wd->fw_virt) { |
333 | ret = -ENOMEM; | |
334 | goto wd719x_init_end; | |
335 | } | |
336 | ||
337 | /* make a fresh copy of WCS and RISC code */ | |
338 | memcpy(wd->fw_virt, fw_wcs->data, fw_wcs->size); | |
339 | memcpy(wd->fw_virt + ALIGN(fw_wcs->size, 4), fw_risc->data, | |
340 | fw_risc->size); | |
341 | ||
342 | /* Reset the Spider Chip and adapter itself */ | |
343 | wd719x_writeb(wd, WD719X_PCI_PORT_RESET, WD719X_PCI_RESET); | |
344 | udelay(WD719X_WAIT_FOR_RISC); | |
345 | /* Clear PIO mode bits set by BIOS */ | |
346 | wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, 0); | |
347 | /* ensure RISC is not running */ | |
348 | wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0); | |
349 | /* ensure command port is ready */ | |
350 | wd719x_writeb(wd, WD719X_AMR_COMMAND, 0); | |
351 | if (wd719x_wait_ready(wd)) { | |
352 | ret = -ETIMEDOUT; | |
353 | goto wd719x_init_end; | |
354 | } | |
355 | ||
356 | /* Transfer the first 2K words of RISC code to kick start the uP */ | |
357 | risc_init[0] = wd->fw_phys; /* WCS FW */ | |
358 | risc_init[1] = wd->fw_phys + ALIGN(fw_wcs->size, 4); /* RISC FW */ | |
359 | risc_init[2] = wd->hash_phys; /* hash table */ | |
360 | ||
361 | /* clear DMA status */ | |
362 | wd719x_writeb(wd, WD719X_PCI_CHANNEL2_3STATUS, 0); | |
363 | ||
364 | /* address to read firmware from */ | |
365 | wd719x_writel(wd, WD719X_PCI_EXTERNAL_ADDR, risc_init[1]); | |
366 | /* base address to write firmware to (on card) */ | |
367 | wd719x_writew(wd, WD719X_PCI_INTERNAL_ADDR, WD719X_PRAM_BASE_ADDR); | |
368 | /* size: first 2K words */ | |
369 | wd719x_writew(wd, WD719X_PCI_DMA_TRANSFER_SIZE, 2048 * 2); | |
370 | /* start DMA */ | |
371 | wd719x_writeb(wd, WD719X_PCI_CHANNEL2_3CMD, WD719X_START_CHANNEL2_3DMA); | |
372 | ||
373 | /* wait for DMA to complete */ | |
374 | i = WD719X_WAIT_FOR_RISC; | |
375 | while (i-- > 0) { | |
376 | u8 status = wd719x_readb(wd, WD719X_PCI_CHANNEL2_3STATUS); | |
377 | if (status == WD719X_START_CHANNEL2_3DONE) | |
378 | break; | |
379 | if (status == WD719X_START_CHANNEL2_3ABORT) { | |
380 | dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA aborted\n"); | |
381 | ret = -EIO; | |
382 | goto wd719x_init_end; | |
383 | } | |
384 | udelay(1); | |
385 | } | |
386 | if (i < 1) { | |
387 | dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA timeout\n"); | |
388 | ret = -ETIMEDOUT; | |
389 | goto wd719x_init_end; | |
390 | } | |
391 | ||
392 | /* firmware is loaded, now initialize and wake up the RISC */ | |
393 | /* write RISC initialization long words to Spider */ | |
394 | wd719x_writel(wd, WD719X_AMR_SCB_IN, risc_init[0]); | |
395 | wd719x_writel(wd, WD719X_AMR_SCB_IN + 4, risc_init[1]); | |
396 | wd719x_writel(wd, WD719X_AMR_SCB_IN + 8, risc_init[2]); | |
397 | ||
398 | /* disable interrupts during initialization of RISC */ | |
399 | wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, WD719X_DISABLE_INT); | |
400 | ||
401 | /* issue INITIALIZE RISC comand */ | |
402 | wd719x_writeb(wd, WD719X_AMR_COMMAND, WD719X_CMD_INIT_RISC); | |
403 | /* enable advanced mode (wake up RISC) */ | |
404 | wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, WD719X_ENABLE_ADVANCE_MODE); | |
405 | udelay(WD719X_WAIT_FOR_RISC); | |
406 | ||
407 | ret = wd719x_wait_done(wd, WD719X_WAIT_FOR_RISC); | |
408 | /* clear interrupt status register */ | |
409 | wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE); | |
410 | if (ret) { | |
411 | dev_warn(&wd->pdev->dev, "Unable to initialize RISC\n"); | |
412 | goto wd719x_init_end; | |
413 | } | |
414 | /* RISC is up and running */ | |
415 | ||
416 | /* Read FW version from RISC */ | |
417 | ret = wd719x_direct_cmd(wd, WD719X_CMD_READ_FIRMVER, 0, 0, 0, 0, | |
418 | WD719X_WAIT_FOR_RISC); | |
419 | if (ret) { | |
420 | dev_warn(&wd->pdev->dev, "Unable to read firmware version\n"); | |
421 | goto wd719x_init_end; | |
422 | } | |
423 | dev_info(&wd->pdev->dev, "RISC initialized with firmware version %.2x.%.2x\n", | |
424 | wd719x_readb(wd, WD719X_AMR_SCB_OUT + 1), | |
425 | wd719x_readb(wd, WD719X_AMR_SCB_OUT)); | |
426 | ||
427 | /* RESET SCSI bus */ | |
428 | ret = wd719x_direct_cmd(wd, WD719X_CMD_BUSRESET, 0, 0, 0, 0, | |
429 | WD719X_WAIT_FOR_SCSI_RESET); | |
430 | if (ret) { | |
431 | dev_warn(&wd->pdev->dev, "SCSI bus reset failed\n"); | |
432 | goto wd719x_init_end; | |
433 | } | |
434 | ||
435 | /* use HostParameter structure to set Spider's Host Parameter Block */ | |
436 | ret = wd719x_direct_cmd(wd, WD719X_CMD_SET_PARAM, 0, | |
437 | sizeof(struct wd719x_host_param), 0, | |
438 | wd->params_phys, WD719X_WAIT_FOR_RISC); | |
439 | if (ret) { | |
440 | dev_warn(&wd->pdev->dev, "Failed to set HOST PARAMETERS\n"); | |
441 | goto wd719x_init_end; | |
442 | } | |
443 | ||
444 | /* initiate SCAM (does nothing if disabled in BIOS) */ | |
445 | /* bug?: we should pass a mask of static IDs which we don't have */ | |
446 | ret = wd719x_direct_cmd(wd, WD719X_CMD_INIT_SCAM, 0, 0, 0, 0, | |
447 | WD719X_WAIT_FOR_SCSI_RESET); | |
448 | if (ret) { | |
449 | dev_warn(&wd->pdev->dev, "SCAM initialization failed\n"); | |
450 | goto wd719x_init_end; | |
451 | } | |
452 | ||
453 | /* clear AMR_BIOS_SHARE_INT register */ | |
454 | wd719x_writeb(wd, WD719X_AMR_BIOS_SHARE_INT, 0); | |
455 | ||
456 | wd719x_init_end: | |
457 | release_firmware(fw_wcs); | |
458 | release_firmware(fw_risc); | |
459 | ||
460 | return ret; | |
461 | } | |
462 | ||
463 | static int wd719x_abort(struct scsi_cmnd *cmd) | |
464 | { | |
465 | int action, result; | |
466 | unsigned long flags; | |
fde46e96 | 467 | struct wd719x_scb *scb = scsi_cmd_priv(cmd); |
48a31030 OZ |
468 | struct wd719x *wd = shost_priv(cmd->device->host); |
469 | ||
470 | dev_info(&wd->pdev->dev, "abort command, tag: %x\n", cmd->tag); | |
471 | ||
472 | action = /*cmd->tag ? WD719X_CMD_ABORT_TAG : */WD719X_CMD_ABORT; | |
473 | ||
474 | spin_lock_irqsave(wd->sh->host_lock, flags); | |
475 | result = wd719x_direct_cmd(wd, action, cmd->device->id, | |
476 | cmd->device->lun, cmd->tag, scb->phys, 0); | |
5da1faa0 | 477 | wd719x_finish_cmd(scb, DID_ABORT); |
48a31030 OZ |
478 | spin_unlock_irqrestore(wd->sh->host_lock, flags); |
479 | if (result) | |
480 | return FAILED; | |
481 | ||
482 | return SUCCESS; | |
483 | } | |
484 | ||
485 | static int wd719x_reset(struct scsi_cmnd *cmd, u8 opcode, u8 device) | |
486 | { | |
487 | int result; | |
488 | unsigned long flags; | |
489 | struct wd719x *wd = shost_priv(cmd->device->host); | |
5da1faa0 | 490 | struct wd719x_scb *scb, *tmp; |
48a31030 OZ |
491 | |
492 | dev_info(&wd->pdev->dev, "%s reset requested\n", | |
493 | (opcode == WD719X_CMD_BUSRESET) ? "bus" : "device"); | |
494 | ||
495 | spin_lock_irqsave(wd->sh->host_lock, flags); | |
496 | result = wd719x_direct_cmd(wd, opcode, device, 0, 0, 0, | |
497 | WD719X_WAIT_FOR_SCSI_RESET); | |
5da1faa0 OZ |
498 | /* flush all SCBs (or all for a device if dev_reset) */ |
499 | list_for_each_entry_safe(scb, tmp, &wd->active_scbs, list) { | |
500 | if (opcode == WD719X_CMD_BUSRESET || | |
501 | scb->cmd->device->id == device) | |
502 | wd719x_finish_cmd(scb, DID_RESET); | |
503 | } | |
48a31030 OZ |
504 | spin_unlock_irqrestore(wd->sh->host_lock, flags); |
505 | if (result) | |
506 | return FAILED; | |
507 | ||
508 | return SUCCESS; | |
509 | } | |
510 | ||
511 | static int wd719x_dev_reset(struct scsi_cmnd *cmd) | |
512 | { | |
513 | return wd719x_reset(cmd, WD719X_CMD_RESET, cmd->device->id); | |
514 | } | |
515 | ||
516 | static int wd719x_bus_reset(struct scsi_cmnd *cmd) | |
517 | { | |
518 | return wd719x_reset(cmd, WD719X_CMD_BUSRESET, 0); | |
519 | } | |
520 | ||
521 | static int wd719x_host_reset(struct scsi_cmnd *cmd) | |
522 | { | |
523 | struct wd719x *wd = shost_priv(cmd->device->host); | |
524 | struct wd719x_scb *scb, *tmp; | |
525 | unsigned long flags; | |
48a31030 OZ |
526 | |
527 | dev_info(&wd->pdev->dev, "host reset requested\n"); | |
528 | spin_lock_irqsave(wd->sh->host_lock, flags); | |
5da1faa0 OZ |
529 | /* stop the RISC */ |
530 | if (wd719x_direct_cmd(wd, WD719X_CMD_SLEEP, 0, 0, 0, 0, | |
531 | WD719X_WAIT_FOR_RISC)) | |
532 | dev_warn(&wd->pdev->dev, "RISC sleep command failed\n"); | |
533 | /* disable RISC */ | |
534 | wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0); | |
48a31030 OZ |
535 | |
536 | /* flush all SCBs */ | |
fde46e96 | 537 | list_for_each_entry_safe(scb, tmp, &wd->active_scbs, list) |
5da1faa0 | 538 | wd719x_finish_cmd(scb, DID_RESET); |
48a31030 OZ |
539 | spin_unlock_irqrestore(wd->sh->host_lock, flags); |
540 | ||
5da1faa0 OZ |
541 | /* Try to reinit the RISC */ |
542 | return wd719x_chip_init(wd) == 0 ? SUCCESS : FAILED; | |
48a31030 OZ |
543 | } |
544 | ||
545 | static int wd719x_biosparam(struct scsi_device *sdev, struct block_device *bdev, | |
546 | sector_t capacity, int geom[]) | |
547 | { | |
548 | if (capacity >= 0x200000) { | |
549 | geom[0] = 255; /* heads */ | |
550 | geom[1] = 63; /* sectors */ | |
551 | } else { | |
552 | geom[0] = 64; /* heads */ | |
553 | geom[1] = 32; /* sectors */ | |
554 | } | |
555 | geom[2] = sector_div(capacity, geom[0] * geom[1]); /* cylinders */ | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | /* process a SCB-completion interrupt */ | |
561 | static inline void wd719x_interrupt_SCB(struct wd719x *wd, | |
562 | union wd719x_regs regs, | |
563 | struct wd719x_scb *scb) | |
564 | { | |
48a31030 OZ |
565 | int result; |
566 | ||
567 | /* now have to find result from card */ | |
568 | switch (regs.bytes.SUE) { | |
569 | case WD719X_SUE_NOERRORS: | |
570 | result = DID_OK; | |
571 | break; | |
572 | case WD719X_SUE_REJECTED: | |
573 | dev_err(&wd->pdev->dev, "command rejected\n"); | |
574 | result = DID_ERROR; | |
575 | break; | |
576 | case WD719X_SUE_SCBQFULL: | |
577 | dev_err(&wd->pdev->dev, "SCB queue is full\n"); | |
578 | result = DID_ERROR; | |
579 | break; | |
580 | case WD719X_SUE_TERM: | |
581 | dev_dbg(&wd->pdev->dev, "SCB terminated by direct command\n"); | |
582 | result = DID_ABORT; /* or DID_RESET? */ | |
583 | break; | |
584 | case WD719X_SUE_CHAN1ABORT: | |
585 | case WD719X_SUE_CHAN23ABORT: | |
586 | result = DID_ABORT; | |
587 | dev_err(&wd->pdev->dev, "DMA abort\n"); | |
588 | break; | |
589 | case WD719X_SUE_CHAN1PAR: | |
590 | case WD719X_SUE_CHAN23PAR: | |
591 | result = DID_PARITY; | |
592 | dev_err(&wd->pdev->dev, "DMA parity error\n"); | |
593 | break; | |
594 | case WD719X_SUE_TIMEOUT: | |
595 | result = DID_TIME_OUT; | |
596 | dev_dbg(&wd->pdev->dev, "selection timeout\n"); | |
597 | break; | |
598 | case WD719X_SUE_RESET: | |
804ff603 | 599 | dev_dbg(&wd->pdev->dev, "bus reset occurred\n"); |
48a31030 OZ |
600 | result = DID_RESET; |
601 | break; | |
602 | case WD719X_SUE_BUSERROR: | |
603 | dev_dbg(&wd->pdev->dev, "SCSI bus error\n"); | |
604 | result = DID_ERROR; | |
605 | break; | |
606 | case WD719X_SUE_WRONGWAY: | |
607 | dev_err(&wd->pdev->dev, "wrong data transfer direction\n"); | |
608 | result = DID_ERROR; | |
609 | break; | |
610 | case WD719X_SUE_BADPHASE: | |
611 | dev_err(&wd->pdev->dev, "invalid SCSI phase\n"); | |
612 | result = DID_ERROR; | |
613 | break; | |
614 | case WD719X_SUE_TOOLONG: | |
615 | dev_err(&wd->pdev->dev, "record too long\n"); | |
616 | result = DID_ERROR; | |
617 | break; | |
618 | case WD719X_SUE_BUSFREE: | |
619 | dev_err(&wd->pdev->dev, "unexpected bus free\n"); | |
620 | result = DID_NO_CONNECT; /* or DID_ERROR ???*/ | |
621 | break; | |
622 | case WD719X_SUE_ARSDONE: | |
623 | dev_dbg(&wd->pdev->dev, "auto request sense\n"); | |
624 | if (regs.bytes.SCSI == 0) | |
625 | result = DID_OK; | |
626 | else | |
627 | result = DID_PARITY; | |
628 | break; | |
629 | case WD719X_SUE_IGNORED: | |
630 | dev_err(&wd->pdev->dev, "target id %d ignored command\n", | |
631 | scb->cmd->device->id); | |
632 | result = DID_NO_CONNECT; | |
633 | break; | |
634 | case WD719X_SUE_WRONGTAGS: | |
635 | dev_err(&wd->pdev->dev, "reversed tags\n"); | |
636 | result = DID_ERROR; | |
637 | break; | |
638 | case WD719X_SUE_BADTAGS: | |
639 | dev_err(&wd->pdev->dev, "tag type not supported by target\n"); | |
640 | result = DID_ERROR; | |
641 | break; | |
642 | case WD719X_SUE_NOSCAMID: | |
643 | dev_err(&wd->pdev->dev, "no SCAM soft ID available\n"); | |
644 | result = DID_ERROR; | |
645 | break; | |
646 | default: | |
647 | dev_warn(&wd->pdev->dev, "unknown SUE error code: 0x%x\n", | |
648 | regs.bytes.SUE); | |
649 | result = DID_ERROR; | |
650 | break; | |
651 | } | |
48a31030 | 652 | |
fde46e96 | 653 | wd719x_finish_cmd(scb, result); |
48a31030 OZ |
654 | } |
655 | ||
656 | static irqreturn_t wd719x_interrupt(int irq, void *dev_id) | |
657 | { | |
658 | struct wd719x *wd = dev_id; | |
659 | union wd719x_regs regs; | |
660 | unsigned long flags; | |
661 | u32 SCB_out; | |
662 | ||
663 | spin_lock_irqsave(wd->sh->host_lock, flags); | |
664 | /* read SCB pointer back from card */ | |
665 | SCB_out = wd719x_readl(wd, WD719X_AMR_SCB_OUT); | |
666 | /* read all status info at once */ | |
667 | regs.all = cpu_to_le32(wd719x_readl(wd, WD719X_AMR_OP_CODE)); | |
668 | ||
669 | switch (regs.bytes.INT) { | |
670 | case WD719X_INT_NONE: | |
671 | spin_unlock_irqrestore(wd->sh->host_lock, flags); | |
672 | return IRQ_NONE; | |
673 | case WD719X_INT_LINKNOSTATUS: | |
674 | dev_err(&wd->pdev->dev, "linked command completed with no status\n"); | |
675 | break; | |
676 | case WD719X_INT_BADINT: | |
677 | dev_err(&wd->pdev->dev, "unsolicited interrupt\n"); | |
678 | break; | |
679 | case WD719X_INT_NOERRORS: | |
680 | case WD719X_INT_LINKNOERRORS: | |
681 | case WD719X_INT_ERRORSLOGGED: | |
682 | case WD719X_INT_SPIDERFAILED: | |
683 | /* was the cmd completed a direct or SCB command? */ | |
684 | if (regs.bytes.OPC == WD719X_CMD_PROCESS_SCB) { | |
685 | struct wd719x_scb *scb; | |
686 | list_for_each_entry(scb, &wd->active_scbs, list) | |
687 | if (SCB_out == scb->phys) | |
688 | break; | |
689 | if (SCB_out == scb->phys) | |
690 | wd719x_interrupt_SCB(wd, regs, scb); | |
691 | else | |
692 | dev_err(&wd->pdev->dev, "card returned invalid SCB pointer\n"); | |
693 | } else | |
5da1faa0 | 694 | dev_dbg(&wd->pdev->dev, "direct command 0x%x completed\n", |
48a31030 OZ |
695 | regs.bytes.OPC); |
696 | break; | |
697 | case WD719X_INT_PIOREADY: | |
698 | dev_err(&wd->pdev->dev, "card indicates PIO data ready but we never use PIO\n"); | |
699 | /* interrupt will not be cleared until all data is read */ | |
700 | break; | |
701 | default: | |
702 | dev_err(&wd->pdev->dev, "unknown interrupt reason: %d\n", | |
703 | regs.bytes.INT); | |
704 | ||
705 | } | |
706 | /* clear interrupt so another can happen */ | |
707 | wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE); | |
708 | spin_unlock_irqrestore(wd->sh->host_lock, flags); | |
709 | ||
710 | return IRQ_HANDLED; | |
711 | } | |
712 | ||
713 | static void wd719x_eeprom_reg_read(struct eeprom_93cx6 *eeprom) | |
714 | { | |
715 | struct wd719x *wd = eeprom->data; | |
716 | u8 reg = wd719x_readb(wd, WD719X_PCI_GPIO_DATA); | |
717 | ||
718 | eeprom->reg_data_out = reg & WD719X_EE_DO; | |
719 | } | |
720 | ||
721 | static void wd719x_eeprom_reg_write(struct eeprom_93cx6 *eeprom) | |
722 | { | |
723 | struct wd719x *wd = eeprom->data; | |
724 | u8 reg = 0; | |
725 | ||
726 | if (eeprom->reg_data_in) | |
727 | reg |= WD719X_EE_DI; | |
728 | if (eeprom->reg_data_clock) | |
729 | reg |= WD719X_EE_CLK; | |
730 | if (eeprom->reg_chip_select) | |
731 | reg |= WD719X_EE_CS; | |
732 | ||
733 | wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, reg); | |
734 | } | |
735 | ||
736 | /* read config from EEPROM so it can be downloaded by the RISC on (re-)init */ | |
737 | static void wd719x_read_eeprom(struct wd719x *wd) | |
738 | { | |
739 | struct eeprom_93cx6 eeprom; | |
740 | u8 gpio; | |
741 | struct wd719x_eeprom_header header; | |
742 | ||
743 | eeprom.data = wd; | |
744 | eeprom.register_read = wd719x_eeprom_reg_read; | |
745 | eeprom.register_write = wd719x_eeprom_reg_write; | |
746 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
747 | ||
748 | /* set all outputs to low */ | |
749 | wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, 0); | |
750 | /* configure GPIO pins */ | |
751 | gpio = wd719x_readb(wd, WD719X_PCI_GPIO_CONTROL); | |
752 | /* GPIO outputs */ | |
753 | gpio &= (~(WD719X_EE_CLK | WD719X_EE_DI | WD719X_EE_CS)); | |
754 | /* GPIO input */ | |
755 | gpio |= WD719X_EE_DO; | |
756 | wd719x_writeb(wd, WD719X_PCI_GPIO_CONTROL, gpio); | |
757 | ||
758 | /* read EEPROM header */ | |
759 | eeprom_93cx6_multireadb(&eeprom, 0, (u8 *)&header, sizeof(header)); | |
760 | ||
761 | if (header.sig1 == 'W' && header.sig2 == 'D') | |
762 | eeprom_93cx6_multireadb(&eeprom, header.cfg_offset, | |
763 | (u8 *)wd->params, | |
764 | sizeof(struct wd719x_host_param)); | |
765 | else { /* default EEPROM values */ | |
766 | dev_warn(&wd->pdev->dev, "EEPROM signature is invalid (0x%02x 0x%02x), using default values\n", | |
767 | header.sig1, header.sig2); | |
768 | wd->params->ch_1_th = 0x10; /* 16 DWs = 64 B */ | |
769 | wd->params->scsi_conf = 0x4c; /* 48ma, spue, parity check */ | |
770 | wd->params->own_scsi_id = 0x07; /* ID 7, SCAM disabled */ | |
771 | wd->params->sel_timeout = 0x4d; /* 250 ms */ | |
772 | wd->params->sleep_timer = 0x01; | |
773 | wd->params->cdb_size = cpu_to_le16(0x5555); /* all 6 B */ | |
774 | wd->params->scsi_pad = 0x1b; | |
775 | if (wd->type == WD719X_TYPE_7193) /* narrow card - disable */ | |
776 | wd->params->wide = cpu_to_le32(0x00000000); | |
777 | else /* initiate & respond to WIDE messages */ | |
778 | wd->params->wide = cpu_to_le32(0xffffffff); | |
779 | wd->params->sync = cpu_to_le32(0xffffffff); | |
780 | wd->params->soft_mask = 0x00; /* all disabled */ | |
781 | wd->params->unsol_mask = 0x00; /* all disabled */ | |
782 | } | |
783 | /* disable TAGGED messages */ | |
784 | wd->params->tag_en = cpu_to_le16(0x0000); | |
785 | } | |
786 | ||
787 | /* Read card type from GPIO bits 1 and 3 */ | |
788 | static enum wd719x_card_type wd719x_detect_type(struct wd719x *wd) | |
789 | { | |
790 | u8 card = wd719x_readb(wd, WD719X_PCI_GPIO_CONTROL); | |
791 | ||
792 | card |= WD719X_GPIO_ID_BITS; | |
793 | wd719x_writeb(wd, WD719X_PCI_GPIO_CONTROL, card); | |
794 | card = wd719x_readb(wd, WD719X_PCI_GPIO_DATA) & WD719X_GPIO_ID_BITS; | |
795 | switch (card) { | |
796 | case 0x08: | |
797 | return WD719X_TYPE_7193; | |
798 | case 0x02: | |
799 | return WD719X_TYPE_7197; | |
800 | case 0x00: | |
801 | return WD719X_TYPE_7296; | |
802 | default: | |
803 | dev_warn(&wd->pdev->dev, "unknown card type 0x%x\n", card); | |
804 | return WD719X_TYPE_UNKNOWN; | |
805 | } | |
806 | } | |
807 | ||
808 | static int wd719x_board_found(struct Scsi_Host *sh) | |
809 | { | |
810 | struct wd719x *wd = shost_priv(sh); | |
d828e5c6 CIK |
811 | static const char * const card_types[] = { |
812 | "Unknown card", "WD7193", "WD7197", "WD7296" | |
813 | }; | |
48a31030 OZ |
814 | int ret; |
815 | ||
816 | INIT_LIST_HEAD(&wd->active_scbs); | |
48a31030 OZ |
817 | |
818 | sh->base = pci_resource_start(wd->pdev, 0); | |
819 | ||
820 | wd->type = wd719x_detect_type(wd); | |
821 | ||
822 | wd->sh = sh; | |
823 | sh->irq = wd->pdev->irq; | |
824 | wd->fw_virt = NULL; | |
825 | ||
826 | /* memory area for host (EEPROM) parameters */ | |
236bd823 CH |
827 | wd->params = dma_alloc_coherent(&wd->pdev->dev, |
828 | sizeof(struct wd719x_host_param), | |
829 | &wd->params_phys, GFP_KERNEL); | |
48a31030 OZ |
830 | if (!wd->params) { |
831 | dev_warn(&wd->pdev->dev, "unable to allocate parameter buffer\n"); | |
832 | return -ENOMEM; | |
833 | } | |
834 | ||
835 | /* memory area for the RISC for hash table of outstanding requests */ | |
236bd823 CH |
836 | wd->hash_virt = dma_alloc_coherent(&wd->pdev->dev, |
837 | WD719X_HASH_TABLE_SIZE, | |
838 | &wd->hash_phys, GFP_KERNEL); | |
48a31030 OZ |
839 | if (!wd->hash_virt) { |
840 | dev_warn(&wd->pdev->dev, "unable to allocate hash buffer\n"); | |
841 | ret = -ENOMEM; | |
842 | goto fail_free_params; | |
843 | } | |
844 | ||
845 | ret = request_irq(wd->pdev->irq, wd719x_interrupt, IRQF_SHARED, | |
846 | "wd719x", wd); | |
847 | if (ret) { | |
848 | dev_warn(&wd->pdev->dev, "unable to assign IRQ %d\n", | |
849 | wd->pdev->irq); | |
850 | goto fail_free_hash; | |
851 | } | |
852 | ||
853 | /* read parameters from EEPROM */ | |
854 | wd719x_read_eeprom(wd); | |
855 | ||
856 | ret = wd719x_chip_init(wd); | |
857 | if (ret) | |
858 | goto fail_free_irq; | |
859 | ||
860 | sh->this_id = wd->params->own_scsi_id & WD719X_EE_SCSI_ID_MASK; | |
861 | ||
862 | dev_info(&wd->pdev->dev, "%s at I/O 0x%lx, IRQ %u, SCSI ID %d\n", | |
863 | card_types[wd->type], sh->base, sh->irq, sh->this_id); | |
864 | ||
865 | return 0; | |
866 | ||
867 | fail_free_irq: | |
868 | free_irq(wd->pdev->irq, wd); | |
869 | fail_free_hash: | |
236bd823 | 870 | dma_free_coherent(&wd->pdev->dev, WD719X_HASH_TABLE_SIZE, wd->hash_virt, |
48a31030 OZ |
871 | wd->hash_phys); |
872 | fail_free_params: | |
236bd823 | 873 | dma_free_coherent(&wd->pdev->dev, sizeof(struct wd719x_host_param), |
48a31030 OZ |
874 | wd->params, wd->params_phys); |
875 | ||
876 | return ret; | |
877 | } | |
878 | ||
879 | static struct scsi_host_template wd719x_template = { | |
2ecf8e0a | 880 | .module = THIS_MODULE, |
48a31030 | 881 | .name = "Western Digital 719x", |
fde46e96 | 882 | .cmd_size = sizeof(struct wd719x_scb), |
48a31030 OZ |
883 | .queuecommand = wd719x_queuecommand, |
884 | .eh_abort_handler = wd719x_abort, | |
885 | .eh_device_reset_handler = wd719x_dev_reset, | |
886 | .eh_bus_reset_handler = wd719x_bus_reset, | |
887 | .eh_host_reset_handler = wd719x_host_reset, | |
888 | .bios_param = wd719x_biosparam, | |
889 | .proc_name = "wd719x", | |
890 | .can_queue = 255, | |
891 | .this_id = 7, | |
892 | .sg_tablesize = WD719X_SG, | |
48a31030 OZ |
893 | }; |
894 | ||
895 | static int wd719x_pci_probe(struct pci_dev *pdev, const struct pci_device_id *d) | |
896 | { | |
897 | int err; | |
898 | struct Scsi_Host *sh; | |
899 | struct wd719x *wd; | |
900 | ||
901 | err = pci_enable_device(pdev); | |
902 | if (err) | |
903 | goto fail; | |
904 | ||
236bd823 | 905 | if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { |
48a31030 OZ |
906 | dev_warn(&pdev->dev, "Unable to set 32-bit DMA mask\n"); |
907 | goto disable_device; | |
908 | } | |
909 | ||
910 | err = pci_request_regions(pdev, "wd719x"); | |
911 | if (err) | |
912 | goto disable_device; | |
913 | pci_set_master(pdev); | |
914 | ||
915 | err = -ENODEV; | |
916 | if (pci_resource_len(pdev, 0) == 0) | |
917 | goto release_region; | |
918 | ||
919 | err = -ENOMEM; | |
920 | sh = scsi_host_alloc(&wd719x_template, sizeof(struct wd719x)); | |
921 | if (!sh) | |
922 | goto release_region; | |
923 | ||
924 | wd = shost_priv(sh); | |
925 | wd->base = pci_iomap(pdev, 0, 0); | |
926 | if (!wd->base) | |
927 | goto free_host; | |
928 | wd->pdev = pdev; | |
929 | ||
930 | err = wd719x_board_found(sh); | |
931 | if (err) | |
932 | goto unmap; | |
933 | ||
934 | err = scsi_add_host(sh, &wd->pdev->dev); | |
935 | if (err) | |
936 | goto destroy; | |
937 | ||
938 | scsi_scan_host(sh); | |
939 | ||
940 | pci_set_drvdata(pdev, sh); | |
941 | return 0; | |
942 | ||
943 | destroy: | |
944 | wd719x_destroy(wd); | |
945 | unmap: | |
946 | pci_iounmap(pdev, wd->base); | |
947 | free_host: | |
948 | scsi_host_put(sh); | |
949 | release_region: | |
950 | pci_release_regions(pdev); | |
951 | disable_device: | |
952 | pci_disable_device(pdev); | |
953 | fail: | |
954 | return err; | |
955 | } | |
956 | ||
957 | ||
958 | static void wd719x_pci_remove(struct pci_dev *pdev) | |
959 | { | |
960 | struct Scsi_Host *sh = pci_get_drvdata(pdev); | |
961 | struct wd719x *wd = shost_priv(sh); | |
962 | ||
963 | scsi_remove_host(sh); | |
964 | wd719x_destroy(wd); | |
965 | pci_iounmap(pdev, wd->base); | |
966 | pci_release_regions(pdev); | |
967 | pci_disable_device(pdev); | |
968 | ||
969 | scsi_host_put(sh); | |
970 | } | |
971 | ||
8a793bea | 972 | static const struct pci_device_id wd719x_pci_table[] = { |
48a31030 OZ |
973 | { PCI_DEVICE(PCI_VENDOR_ID_WD, 0x3296) }, |
974 | {} | |
975 | }; | |
976 | ||
977 | MODULE_DEVICE_TABLE(pci, wd719x_pci_table); | |
978 | ||
979 | static struct pci_driver wd719x_pci_driver = { | |
980 | .name = "wd719x", | |
981 | .id_table = wd719x_pci_table, | |
982 | .probe = wd719x_pci_probe, | |
983 | .remove = wd719x_pci_remove, | |
984 | }; | |
985 | ||
3e1bbc56 | 986 | module_pci_driver(wd719x_pci_driver); |
48a31030 OZ |
987 | |
988 | MODULE_DESCRIPTION("Western Digital WD7193/7197/7296 SCSI driver"); | |
989 | MODULE_AUTHOR("Ondrej Zary, Aaron Dewell, Juergen Gaertner"); | |
990 | MODULE_LICENSE("GPL"); | |
991 | MODULE_FIRMWARE("wd719x-wcs.bin"); | |
992 | MODULE_FIRMWARE("wd719x-risc.bin"); |