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[SPARC64]: Use compat_sys_futimesat in 32-bit syscall table.
[mirror_ubuntu-artful-kernel.git] / drivers / serial / 8250.c
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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
d052d1be 36#include <linux/platform_device.h>
1da177e4
LT		 37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
78512ece 43#include <linux/nmi.h>
f392ecfa 44#include <linux/mutex.h>
1da177e4
LT		 45
46#include <asm/io.h>
47#include <asm/irq.h>
48
49#include "8250.h"
50
51/*
52 * Configuration:
53 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
1da177e4
LT		 60/*
61 * Debugging.
62 */
63#if 0
64#define DEBUG_AUTOCONF(fmt...) printk(fmt)
65#else
66#define DEBUG_AUTOCONF(fmt...) do { } while (0)
67#endif
68
69#if 0
70#define DEBUG_INTR(fmt...) printk(fmt)
71#else
72#define DEBUG_INTR(fmt...) do { } while (0)
73#endif
74
75#define PASS_LIMIT 256
76
77/*
78 * We default to IRQ0 for the "no irq" hack. Some
79 * machine types want others as well - they're free
80 * to redefine this in their header file.
81 */
82#define is_real_interrupt(irq) ((irq) != 0)
83
1da177e4
LT		 84#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
85#define CONFIG_SERIAL_DETECT_IRQ 1
86#endif
1da177e4
LT		 87#ifdef CONFIG_SERIAL_8250_MANY_PORTS
88#define CONFIG_SERIAL_MANY_PORTS 1
89#endif
90
91/*
92 * HUB6 is always on. This will be removed once the header
93 * files have been cleaned.
94 */
95#define CONFIG_HUB6 1
96
97#include <asm/serial.h>
98
99/*
100 * SERIAL_PORT_DFNS tells us about built-in ports that have no
101 * standard enumeration mechanism. Platforms that can find all
102 * serial ports via mechanisms like ACPI or PCI need not supply it.
103 */
104#ifndef SERIAL_PORT_DFNS
105#define SERIAL_PORT_DFNS
106#endif
107
cb3592be 108static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 109 SERIAL_PORT_DFNS /* defined in asm/serial.h */
110};
111
026d02a2 112#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 113
114#ifdef CONFIG_SERIAL_8250_RSA
115
116#define PORT_RSA_MAX 4
117static unsigned long probe_rsa[PORT_RSA_MAX];
118static unsigned int probe_rsa_count;
119#endif /* CONFIG_SERIAL_8250_RSA */
120
121struct uart_8250_port {
122 struct uart_port port;
123 struct timer_list timer; /* "no irq" timer */
124 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 125 unsigned short capabilities; /* port capabilities */
126 unsigned short bugs; /* port bugs */
1da177e4 127 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 128 unsigned char acr;
129 unsigned char ier;
130 unsigned char lcr;
131 unsigned char mcr;
132 unsigned char mcr_mask; /* mask of user bits */
133 unsigned char mcr_force; /* mask of forced bits */
134 unsigned char lsr_break_flag;
135
136 /*
137 * We provide a per-port pm hook.
138 */
139 void (*pm)(struct uart_port *port,
140 unsigned int state, unsigned int old);
141};
142
143struct irq_info {
144 spinlock_t lock;
145 struct list_head *head;
146};
147
148static struct irq_info irq_lists[NR_IRQS];
149
150/*
151 * Here we define the default xmit fifo size used for each type of UART.
152 */
153static const struct serial8250_config uart_config[] = {
154 [PORT_UNKNOWN] = {
155 .name = "unknown",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_8250] = {
160 .name = "8250",
161 .fifo_size = 1,
162 .tx_loadsz = 1,
163 },
164 [PORT_16450] = {
165 .name = "16450",
166 .fifo_size = 1,
167 .tx_loadsz = 1,
168 },
169 [PORT_16550] = {
170 .name = "16550",
171 .fifo_size = 1,
172 .tx_loadsz = 1,
173 },
174 [PORT_16550A] = {
175 .name = "16550A",
176 .fifo_size = 16,
177 .tx_loadsz = 16,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
179 .flags = UART_CAP_FIFO,
180 },
181 [PORT_CIRRUS] = {
182 .name = "Cirrus",
183 .fifo_size = 1,
184 .tx_loadsz = 1,
185 },
186 [PORT_16650] = {
187 .name = "ST16650",
188 .fifo_size = 1,
189 .tx_loadsz = 1,
190 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
191 },
192 [PORT_16650V2] = {
193 .name = "ST16650V2",
194 .fifo_size = 32,
195 .tx_loadsz = 16,
196 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
197 UART_FCR_T_TRIG_00,
198 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
199 },
200 [PORT_16750] = {
201 .name = "TI16750",
202 .fifo_size = 64,
203 .tx_loadsz = 64,
204 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
205 UART_FCR7_64BYTE,
206 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
207 },
208 [PORT_STARTECH] = {
209 .name = "Startech",
210 .fifo_size = 1,
211 .tx_loadsz = 1,
212 },
213 [PORT_16C950] = {
214 .name = "16C950/954",
215 .fifo_size = 128,
216 .tx_loadsz = 128,
217 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
218 .flags = UART_CAP_FIFO,
219 },
220 [PORT_16654] = {
221 .name = "ST16654",
222 .fifo_size = 64,
223 .tx_loadsz = 32,
224 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
225 UART_FCR_T_TRIG_10,
226 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
227 },
228 [PORT_16850] = {
229 .name = "XR16850",
230 .fifo_size = 128,
231 .tx_loadsz = 128,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
234 },
235 [PORT_RSA] = {
236 .name = "RSA",
237 .fifo_size = 2048,
238 .tx_loadsz = 2048,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
240 .flags = UART_CAP_FIFO,
241 },
242 [PORT_NS16550A] = {
243 .name = "NS16550A",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO | UART_NATSEMI,
248 },
249 [PORT_XSCALE] = {
250 .name = "XScale",
251 .fifo_size = 32,
252 .tx_loadsz = 32,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO | UART_CAP_UUE,
255 },
256};
257
21c614a7
PA		 258#ifdef CONFIG_SERIAL_8250_AU1X00
259
260/* Au1x00 UART hardware has a weird register layout */
261static const u8 au_io_in_map[] = {
262 [UART_RX] = 0,
263 [UART_IER] = 2,
264 [UART_IIR] = 3,
265 [UART_LCR] = 5,
266 [UART_MCR] = 6,
267 [UART_LSR] = 7,
268 [UART_MSR] = 8,
269};
270
271static const u8 au_io_out_map[] = {
272 [UART_TX] = 1,
273 [UART_IER] = 2,
274 [UART_FCR] = 4,
275 [UART_LCR] = 5,
276 [UART_MCR] = 6,
277};
278
279/* sane hardware needs no mapping */
280static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
281{
282 if (up->port.iotype != UPIO_AU)
283 return offset;
284 return au_io_in_map[offset];
285}
286
287static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
288{
289 if (up->port.iotype != UPIO_AU)
290 return offset;
291 return au_io_out_map[offset];
292}
293
294#else
295
296/* sane hardware needs no mapping */
297#define map_8250_in_reg(up, offset) (offset)
298#define map_8250_out_reg(up, offset) (offset)
299
300#endif
301
ea8874dc 302static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 303{
21c614a7 304 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 305
306 switch (up->port.iotype) {
307 case UPIO_HUB6:
308 outb(up->port.hub6 - 1 + offset, up->port.iobase);
309 return inb(up->port.iobase + 1);
310
311 case UPIO_MEM:
312 return readb(up->port.membase + offset);
313
314 case UPIO_MEM32:
315 return readl(up->port.membase + offset);
316
21c614a7
PA		 317#ifdef CONFIG_SERIAL_8250_AU1X00
318 case UPIO_AU:
319 return __raw_readl(up->port.membase + offset);
320#endif
321
1da177e4
LT		 322 default:
323 return inb(up->port.iobase + offset);
324 }
325}
326
ea8874dc 327static void
1da177e4
LT		 328serial_out(struct uart_8250_port *up, int offset, int value)
329{
21c614a7 330 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 331
332 switch (up->port.iotype) {
333 case UPIO_HUB6:
334 outb(up->port.hub6 - 1 + offset, up->port.iobase);
335 outb(value, up->port.iobase + 1);
336 break;
337
338 case UPIO_MEM:
339 writeb(value, up->port.membase + offset);
340 break;
341
342 case UPIO_MEM32:
343 writel(value, up->port.membase + offset);
344 break;
345
21c614a7
PA		 346#ifdef CONFIG_SERIAL_8250_AU1X00
347 case UPIO_AU:
348 __raw_writel(value, up->port.membase + offset);
349 break;
350#endif
351
1da177e4
LT		 352 default:
353 outb(value, up->port.iobase + offset);
354 }
355}
356
357/*
358 * We used to support using pause I/O for certain machines. We
359 * haven't supported this for a while, but just in case it's badly
360 * needed for certain old 386 machines, I've left these #define's
361 * in....
362 */
363#define serial_inp(up, offset) serial_in(up, offset)
364#define serial_outp(up, offset, value) serial_out(up, offset, value)
365
366
367/*
368 * For the 16C950
369 */
370static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
371{
372 serial_out(up, UART_SCR, offset);
373 serial_out(up, UART_ICR, value);
374}
375
376static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
377{
378 unsigned int value;
379
380 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
381 serial_out(up, UART_SCR, offset);
382 value = serial_in(up, UART_ICR);
383 serial_icr_write(up, UART_ACR, up->acr);
384
385 return value;
386}
387
388/*
389 * FIFO support.
390 */
391static inline void serial8250_clear_fifos(struct uart_8250_port *p)
392{
393 if (p->capabilities & UART_CAP_FIFO) {
394 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
395 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
396 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
397 serial_outp(p, UART_FCR, 0);
398 }
399}
400
401/*
402 * IER sleep support. UARTs which have EFRs need the "extended
403 * capability" bit enabled. Note that on XR16C850s, we need to
404 * reset LCR to write to IER.
405 */
406static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
407{
408 if (p->capabilities & UART_CAP_SLEEP) {
409 if (p->capabilities & UART_CAP_EFR) {
410 serial_outp(p, UART_LCR, 0xBF);
411 serial_outp(p, UART_EFR, UART_EFR_ECB);
412 serial_outp(p, UART_LCR, 0);
413 }
414 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
415 if (p->capabilities & UART_CAP_EFR) {
416 serial_outp(p, UART_LCR, 0xBF);
417 serial_outp(p, UART_EFR, 0);
418 serial_outp(p, UART_LCR, 0);
419 }
420 }
421}
422
423#ifdef CONFIG_SERIAL_8250_RSA
424/*
425 * Attempts to turn on the RSA FIFO. Returns zero on failure.
426 * We set the port uart clock rate if we succeed.
427 */
428static int __enable_rsa(struct uart_8250_port *up)
429{
430 unsigned char mode;
431 int result;
432
433 mode = serial_inp(up, UART_RSA_MSR);
434 result = mode & UART_RSA_MSR_FIFO;
435
436 if (!result) {
437 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
438 mode = serial_inp(up, UART_RSA_MSR);
439 result = mode & UART_RSA_MSR_FIFO;
440 }
441
442 if (result)
443 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
444
445 return result;
446}
447
448static void enable_rsa(struct uart_8250_port *up)
449{
450 if (up->port.type == PORT_RSA) {
451 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
452 spin_lock_irq(&up->port.lock);
453 __enable_rsa(up);
454 spin_unlock_irq(&up->port.lock);
455 }
456 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
457 serial_outp(up, UART_RSA_FRR, 0);
458 }
459}
460
461/*
462 * Attempts to turn off the RSA FIFO. Returns zero on failure.
463 * It is unknown why interrupts were disabled in here. However,
464 * the caller is expected to preserve this behaviour by grabbing
465 * the spinlock before calling this function.
466 */
467static void disable_rsa(struct uart_8250_port *up)
468{
469 unsigned char mode;
470 int result;
471
472 if (up->port.type == PORT_RSA &&
473 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
474 spin_lock_irq(&up->port.lock);
475
476 mode = serial_inp(up, UART_RSA_MSR);
477 result = !(mode & UART_RSA_MSR_FIFO);
478
479 if (!result) {
480 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
481 mode = serial_inp(up, UART_RSA_MSR);
482 result = !(mode & UART_RSA_MSR_FIFO);
483 }
484
485 if (result)
486 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
487 spin_unlock_irq(&up->port.lock);
488 }
489}
490#endif /* CONFIG_SERIAL_8250_RSA */
491
492/*
493 * This is a quickie test to see how big the FIFO is.
494 * It doesn't work at all the time, more's the pity.
495 */
496static int size_fifo(struct uart_8250_port *up)
497{
498 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
499 int count;
500
501 old_lcr = serial_inp(up, UART_LCR);
502 serial_outp(up, UART_LCR, 0);
503 old_fcr = serial_inp(up, UART_FCR);
504 old_mcr = serial_inp(up, UART_MCR);
505 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
506 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
507 serial_outp(up, UART_MCR, UART_MCR_LOOP);
508 serial_outp(up, UART_LCR, UART_LCR_DLAB);
509 old_dll = serial_inp(up, UART_DLL);
510 old_dlm = serial_inp(up, UART_DLM);
511 serial_outp(up, UART_DLL, 0x01);
512 serial_outp(up, UART_DLM, 0x00);
513 serial_outp(up, UART_LCR, 0x03);
514 for (count = 0; count < 256; count++)
515 serial_outp(up, UART_TX, count);
516 mdelay(20);/* FIXME - schedule_timeout */
517 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
518 (count < 256); count++)
519 serial_inp(up, UART_RX);
520 serial_outp(up, UART_FCR, old_fcr);
521 serial_outp(up, UART_MCR, old_mcr);
522 serial_outp(up, UART_LCR, UART_LCR_DLAB);
523 serial_outp(up, UART_DLL, old_dll);
524 serial_outp(up, UART_DLM, old_dlm);
525 serial_outp(up, UART_LCR, old_lcr);
526
527 return count;
528}
529
530/*
531 * Read UART ID using the divisor method - set DLL and DLM to zero
532 * and the revision will be in DLL and device type in DLM. We
533 * preserve the device state across this.
534 */
535static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
536{
537 unsigned char old_dll, old_dlm, old_lcr;
538 unsigned int id;
539
540 old_lcr = serial_inp(p, UART_LCR);
541 serial_outp(p, UART_LCR, UART_LCR_DLAB);
542
543 old_dll = serial_inp(p, UART_DLL);
544 old_dlm = serial_inp(p, UART_DLM);
545
546 serial_outp(p, UART_DLL, 0);
547 serial_outp(p, UART_DLM, 0);
548
549 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
550
551 serial_outp(p, UART_DLL, old_dll);
552 serial_outp(p, UART_DLM, old_dlm);
553 serial_outp(p, UART_LCR, old_lcr);
554
555 return id;
556}
557
558/*
559 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
560 * When this function is called we know it is at least a StarTech
561 * 16650 V2, but it might be one of several StarTech UARTs, or one of
562 * its clones. (We treat the broken original StarTech 16650 V1 as a
563 * 16550, and why not? Startech doesn't seem to even acknowledge its
564 * existence.)
565 *
566 * What evil have men's minds wrought...
567 */
568static void autoconfig_has_efr(struct uart_8250_port *up)
569{
570 unsigned int id1, id2, id3, rev;
571
572 /*
573 * Everything with an EFR has SLEEP
574 */
575 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
576
577 /*
578 * First we check to see if it's an Oxford Semiconductor UART.
579 *
580 * If we have to do this here because some non-National
581 * Semiconductor clone chips lock up if you try writing to the
582 * LSR register (which serial_icr_read does)
583 */
584
585 /*
586 * Check for Oxford Semiconductor 16C950.
587 *
588 * EFR [4] must be set else this test fails.
589 *
590 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
591 * claims that it's needed for 952 dual UART's (which are not
592 * recommended for new designs).
593 */
594 up->acr = 0;
595 serial_out(up, UART_LCR, 0xBF);
596 serial_out(up, UART_EFR, UART_EFR_ECB);
597 serial_out(up, UART_LCR, 0x00);
598 id1 = serial_icr_read(up, UART_ID1);
599 id2 = serial_icr_read(up, UART_ID2);
600 id3 = serial_icr_read(up, UART_ID3);
601 rev = serial_icr_read(up, UART_REV);
602
603 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
604
605 if (id1 == 0x16 && id2 == 0xC9 &&
606 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
607 up->port.type = PORT_16C950;
4ba5e35d
RK		 608
609 /*
610 * Enable work around for the Oxford Semiconductor 952 rev B
611 * chip which causes it to seriously miscalculate baud rates
612 * when DLL is 0.
613 */
614 if (id3 == 0x52 && rev == 0x01)
615 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 616 return;
617 }
618
619 /*
620 * We check for a XR16C850 by setting DLL and DLM to 0, and then
621 * reading back DLL and DLM. The chip type depends on the DLM
622 * value read back:
623 * 0x10 - XR16C850 and the DLL contains the chip revision.
624 * 0x12 - XR16C2850.
625 * 0x14 - XR16C854.
626 */
627 id1 = autoconfig_read_divisor_id(up);
628 DEBUG_AUTOCONF("850id=%04x ", id1);
629
630 id2 = id1 >> 8;
631 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 632 up->port.type = PORT_16850;
633 return;
634 }
635
636 /*
637 * It wasn't an XR16C850.
638 *
639 * We distinguish between the '654 and the '650 by counting
640 * how many bytes are in the FIFO. I'm using this for now,
641 * since that's the technique that was sent to me in the
642 * serial driver update, but I'm not convinced this works.
643 * I've had problems doing this in the past. -TYT
644 */
645 if (size_fifo(up) == 64)
646 up->port.type = PORT_16654;
647 else
648 up->port.type = PORT_16650V2;
649}
650
651/*
652 * We detected a chip without a FIFO. Only two fall into
653 * this category - the original 8250 and the 16450. The
654 * 16450 has a scratch register (accessible with LCR=0)
655 */
656static void autoconfig_8250(struct uart_8250_port *up)
657{
658 unsigned char scratch, status1, status2;
659
660 up->port.type = PORT_8250;
661
662 scratch = serial_in(up, UART_SCR);
663 serial_outp(up, UART_SCR, 0xa5);
664 status1 = serial_in(up, UART_SCR);
665 serial_outp(up, UART_SCR, 0x5a);
666 status2 = serial_in(up, UART_SCR);
667 serial_outp(up, UART_SCR, scratch);
668
669 if (status1 == 0xa5 && status2 == 0x5a)
670 up->port.type = PORT_16450;
671}
672
673static int broken_efr(struct uart_8250_port *up)
674{
675 /*
676 * Exar ST16C2550 "A2" devices incorrectly detect as
677 * having an EFR, and report an ID of 0x0201. See
678 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
679 */
680 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
681 return 1;
682
683 return 0;
684}
685
686/*
687 * We know that the chip has FIFOs. Does it have an EFR? The
688 * EFR is located in the same register position as the IIR and
689 * we know the top two bits of the IIR are currently set. The
690 * EFR should contain zero. Try to read the EFR.
691 */
692static void autoconfig_16550a(struct uart_8250_port *up)
693{
694 unsigned char status1, status2;
695 unsigned int iersave;
696
697 up->port.type = PORT_16550A;
698 up->capabilities |= UART_CAP_FIFO;
699
700 /*
701 * Check for presence of the EFR when DLAB is set.
702 * Only ST16C650V1 UARTs pass this test.
703 */
704 serial_outp(up, UART_LCR, UART_LCR_DLAB);
705 if (serial_in(up, UART_EFR) == 0) {
706 serial_outp(up, UART_EFR, 0xA8);
707 if (serial_in(up, UART_EFR) != 0) {
708 DEBUG_AUTOCONF("EFRv1 ");
709 up->port.type = PORT_16650;
710 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
711 } else {
712 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
713 }
714 serial_outp(up, UART_EFR, 0);
715 return;
716 }
717
718 /*
719 * Maybe it requires 0xbf to be written to the LCR.
720 * (other ST16C650V2 UARTs, TI16C752A, etc)
721 */
722 serial_outp(up, UART_LCR, 0xBF);
723 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
724 DEBUG_AUTOCONF("EFRv2 ");
725 autoconfig_has_efr(up);
726 return;
727 }
728
729 /*
730 * Check for a National Semiconductor SuperIO chip.
731 * Attempt to switch to bank 2, read the value of the LOOP bit
732 * from EXCR1. Switch back to bank 0, change it in MCR. Then
733 * switch back to bank 2, read it from EXCR1 again and check
734 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 735 */
736 serial_outp(up, UART_LCR, 0);
737 status1 = serial_in(up, UART_MCR);
738 serial_outp(up, UART_LCR, 0xE0);
739 status2 = serial_in(up, 0x02); /* EXCR1 */
740
741 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
742 serial_outp(up, UART_LCR, 0);
743 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
744 serial_outp(up, UART_LCR, 0xE0);
745 status2 = serial_in(up, 0x02); /* EXCR1 */
746 serial_outp(up, UART_LCR, 0);
747 serial_outp(up, UART_MCR, status1);
748
749 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 750 unsigned short quot;
751
1da177e4 752 serial_outp(up, UART_LCR, 0xE0);
857dde2e
DW		 753
754 quot = serial_inp(up, UART_DLM) << 8;
755 quot += serial_inp(up, UART_DLL);
756 quot <<= 3;
757
1da177e4
LT		 758 status1 = serial_in(up, 0x04); /* EXCR1 */
759 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
760 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
761 serial_outp(up, 0x04, status1);
857dde2e
DW		 762
763 serial_outp(up, UART_DLL, quot & 0xff);
764 serial_outp(up, UART_DLM, quot >> 8);
765
1da177e4 766 serial_outp(up, UART_LCR, 0);
1da177e4 767
857dde2e 768 up->port.uartclk = 921600*16;
1da177e4
LT		 769 up->port.type = PORT_NS16550A;
770 up->capabilities |= UART_NATSEMI;
771 return;
772 }
773 }
774
775 /*
776 * No EFR. Try to detect a TI16750, which only sets bit 5 of
777 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
778 * Try setting it with and without DLAB set. Cheap clones
779 * set bit 5 without DLAB set.
780 */
781 serial_outp(up, UART_LCR, 0);
782 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
783 status1 = serial_in(up, UART_IIR) >> 5;
784 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
785 serial_outp(up, UART_LCR, UART_LCR_DLAB);
786 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
787 status2 = serial_in(up, UART_IIR) >> 5;
788 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
789 serial_outp(up, UART_LCR, 0);
790
791 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
792
793 if (status1 == 6 && status2 == 7) {
794 up->port.type = PORT_16750;
795 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
796 return;
797 }
798
799 /*
800 * Try writing and reading the UART_IER_UUE bit (b6).
801 * If it works, this is probably one of the Xscale platform's
802 * internal UARTs.
803 * We're going to explicitly set the UUE bit to 0 before
804 * trying to write and read a 1 just to make sure it's not
805 * already a 1 and maybe locked there before we even start start.
806 */
807 iersave = serial_in(up, UART_IER);
808 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
809 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
810 /*
811 * OK it's in a known zero state, try writing and reading
812 * without disturbing the current state of the other bits.
813 */
814 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
815 if (serial_in(up, UART_IER) & UART_IER_UUE) {
816 /*
817 * It's an Xscale.
818 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
819 */
820 DEBUG_AUTOCONF("Xscale ");
821 up->port.type = PORT_XSCALE;
822 up->capabilities |= UART_CAP_UUE;
823 return;
824 }
825 } else {
826 /*
827 * If we got here we couldn't force the IER_UUE bit to 0.
828 * Log it and continue.
829 */
830 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
831 }
832 serial_outp(up, UART_IER, iersave);
833}
834
835/*
836 * This routine is called by rs_init() to initialize a specific serial
837 * port. It determines what type of UART chip this serial port is
838 * using: 8250, 16450, 16550, 16550A. The important question is
839 * whether or not this UART is a 16550A or not, since this will
840 * determine whether or not we can use its FIFO features or not.
841 */
842static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
843{
844 unsigned char status1, scratch, scratch2, scratch3;
845 unsigned char save_lcr, save_mcr;
846 unsigned long flags;
847
848 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
849 return;
850
851 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
852 up->port.line, up->port.iobase, up->port.membase);
853
854 /*
855 * We really do need global IRQs disabled here - we're going to
856 * be frobbing the chips IRQ enable register to see if it exists.
857 */
858 spin_lock_irqsave(&up->port.lock, flags);
859// save_flags(flags); cli();
860
861 up->capabilities = 0;
4ba5e35d 862 up->bugs = 0;
1da177e4
LT		 863
864 if (!(up->port.flags & UPF_BUGGY_UART)) {
865 /*
866 * Do a simple existence test first; if we fail this,
867 * there's no point trying anything else.
868 *
869 * 0x80 is used as a nonsense port to prevent against
870 * false positives due to ISA bus float. The
871 * assumption is that 0x80 is a non-existent port;
872 * which should be safe since include/asm/io.h also
873 * makes this assumption.
874 *
875 * Note: this is safe as long as MCR bit 4 is clear
876 * and the device is in "PC" mode.
877 */
878 scratch = serial_inp(up, UART_IER);
879 serial_outp(up, UART_IER, 0);
880#ifdef __i386__
881 outb(0xff, 0x080);
882#endif
883 scratch2 = serial_inp(up, UART_IER);
884 serial_outp(up, UART_IER, 0x0F);
885#ifdef __i386__
886 outb(0, 0x080);
887#endif
888 scratch3 = serial_inp(up, UART_IER);
889 serial_outp(up, UART_IER, scratch);
890 if (scratch2 != 0 || scratch3 != 0x0F) {
891 /*
892 * We failed; there's nothing here
893 */
894 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
895 scratch2, scratch3);
896 goto out;
897 }
898 }
899
900 save_mcr = serial_in(up, UART_MCR);
901 save_lcr = serial_in(up, UART_LCR);
902
903 /*
904 * Check to see if a UART is really there. Certain broken
905 * internal modems based on the Rockwell chipset fail this
906 * test, because they apparently don't implement the loopback
907 * test mode. So this test is skipped on the COM 1 through
908 * COM 4 ports. This *should* be safe, since no board
909 * manufacturer would be stupid enough to design a board
910 * that conflicts with COM 1-4 --- we hope!
911 */
912 if (!(up->port.flags & UPF_SKIP_TEST)) {
913 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
914 status1 = serial_inp(up, UART_MSR) & 0xF0;
915 serial_outp(up, UART_MCR, save_mcr);
916 if (status1 != 0x90) {
917 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
918 status1);
919 goto out;
920 }
921 }
922
923 /*
924 * We're pretty sure there's a port here. Lets find out what
925 * type of port it is. The IIR top two bits allows us to find
6f0d618f 926 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 927 * determines what we test for next.
928 *
929 * We also initialise the EFR (if any) to zero for later. The
930 * EFR occupies the same register location as the FCR and IIR.
931 */
932 serial_outp(up, UART_LCR, 0xBF);
933 serial_outp(up, UART_EFR, 0);
934 serial_outp(up, UART_LCR, 0);
935
936 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
937 scratch = serial_in(up, UART_IIR) >> 6;
938
939 DEBUG_AUTOCONF("iir=%d ", scratch);
940
941 switch (scratch) {
942 case 0:
943 autoconfig_8250(up);
944 break;
945 case 1:
946 up->port.type = PORT_UNKNOWN;
947 break;
948 case 2:
949 up->port.type = PORT_16550;
950 break;
951 case 3:
952 autoconfig_16550a(up);
953 break;
954 }
955
956#ifdef CONFIG_SERIAL_8250_RSA
957 /*
958 * Only probe for RSA ports if we got the region.
959 */
960 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
961 int i;
962
963 for (i = 0 ; i < probe_rsa_count; ++i) {
964 if (probe_rsa[i] == up->port.iobase &&
965 __enable_rsa(up)) {
966 up->port.type = PORT_RSA;
967 break;
968 }
969 }
970 }
971#endif
21c614a7
PA		 972
973#ifdef CONFIG_SERIAL_8250_AU1X00
974 /* if access method is AU, it is a 16550 with a quirk */
975 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
976 up->bugs |= UART_BUG_NOMSR;
977#endif
978
1da177e4
LT		 979 serial_outp(up, UART_LCR, save_lcr);
980
981 if (up->capabilities != uart_config[up->port.type].flags) {
982 printk(KERN_WARNING
983 "ttyS%d: detected caps %08x should be %08x\n",
984 up->port.line, up->capabilities,
985 uart_config[up->port.type].flags);
986 }
987
988 up->port.fifosize = uart_config[up->port.type].fifo_size;
989 up->capabilities = uart_config[up->port.type].flags;
990 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
991
992 if (up->port.type == PORT_UNKNOWN)
993 goto out;
994
995 /*
996 * Reset the UART.
997 */
998#ifdef CONFIG_SERIAL_8250_RSA
999 if (up->port.type == PORT_RSA)
1000 serial_outp(up, UART_RSA_FRR, 0);
1001#endif
1002 serial_outp(up, UART_MCR, save_mcr);
1003 serial8250_clear_fifos(up);
1004 (void)serial_in(up, UART_RX);
5c8c755c
LB		 1005 if (up->capabilities & UART_CAP_UUE)
1006 serial_outp(up, UART_IER, UART_IER_UUE);
1007 else
1008 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1009
1010 out:
1011 spin_unlock_irqrestore(&up->port.lock, flags);
1012// restore_flags(flags);
1013 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1014}
1015
1016static void autoconfig_irq(struct uart_8250_port *up)
1017{
1018 unsigned char save_mcr, save_ier;
1019 unsigned char save_ICP = 0;
1020 unsigned int ICP = 0;
1021 unsigned long irqs;
1022 int irq;
1023
1024 if (up->port.flags & UPF_FOURPORT) {
1025 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1026 save_ICP = inb_p(ICP);
1027 outb_p(0x80, ICP);
1028 (void) inb_p(ICP);
1029 }
1030
1031 /* forget possible initially masked and pending IRQ */
1032 probe_irq_off(probe_irq_on());
1033 save_mcr = serial_inp(up, UART_MCR);
1034 save_ier = serial_inp(up, UART_IER);
1035 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1036
1037 irqs = probe_irq_on();
1038 serial_outp(up, UART_MCR, 0);
1039 udelay (10);
1040 if (up->port.flags & UPF_FOURPORT) {
1041 serial_outp(up, UART_MCR,
1042 UART_MCR_DTR | UART_MCR_RTS);
1043 } else {
1044 serial_outp(up, UART_MCR,
1045 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1046 }
1047 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1048 (void)serial_inp(up, UART_LSR);
1049 (void)serial_inp(up, UART_RX);
1050 (void)serial_inp(up, UART_IIR);
1051 (void)serial_inp(up, UART_MSR);
1052 serial_outp(up, UART_TX, 0xFF);
1053 udelay (20);
1054 irq = probe_irq_off(irqs);
1055
1056 serial_outp(up, UART_MCR, save_mcr);
1057 serial_outp(up, UART_IER, save_ier);
1058
1059 if (up->port.flags & UPF_FOURPORT)
1060 outb_p(save_ICP, ICP);
1061
1062 up->port.irq = (irq > 0) ? irq : 0;
1063}
1064
e763b90c
RK		 1065static inline void __stop_tx(struct uart_8250_port *p)
1066{
1067 if (p->ier & UART_IER_THRI) {
1068 p->ier &= ~UART_IER_THRI;
1069 serial_out(p, UART_IER, p->ier);
1070 }
1071}
1072
b129a8cc 1073static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1074{
1075 struct uart_8250_port *up = (struct uart_8250_port *)port;
1076
e763b90c 1077 __stop_tx(up);
1da177e4
LT		 1078
1079 /*
e763b90c 1080 * We really want to stop the transmitter from sending.
1da177e4 1081 */
e763b90c 1082 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1083 up->acr |= UART_ACR_TXDIS;
1084 serial_icr_write(up, UART_ACR, up->acr);
1085 }
1086}
1087
55d3b282
RK		 1088static void transmit_chars(struct uart_8250_port *up);
1089
b129a8cc 1090static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1091{
1092 struct uart_8250_port *up = (struct uart_8250_port *)port;
1093
1094 if (!(up->ier & UART_IER_THRI)) {
1095 up->ier |= UART_IER_THRI;
1096 serial_out(up, UART_IER, up->ier);
55d3b282 1097
67f7654e 1098 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1099 unsigned char lsr, iir;
1100 lsr = serial_in(up, UART_LSR);
1101 iir = serial_in(up, UART_IIR);
1102 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1103 transmit_chars(up);
1104 }
1da177e4 1105 }
e763b90c 1106
1da177e4 1107 /*
e763b90c 1108 * Re-enable the transmitter if we disabled it.
1da177e4 1109 */
e763b90c 1110 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1111 up->acr &= ~UART_ACR_TXDIS;
1112 serial_icr_write(up, UART_ACR, up->acr);
1113 }
1114}
1115
1116static void serial8250_stop_rx(struct uart_port *port)
1117{
1118 struct uart_8250_port *up = (struct uart_8250_port *)port;
1119
1120 up->ier &= ~UART_IER_RLSI;
1121 up->port.read_status_mask &= ~UART_LSR_DR;
1122 serial_out(up, UART_IER, up->ier);
1123}
1124
1125static void serial8250_enable_ms(struct uart_port *port)
1126{
1127 struct uart_8250_port *up = (struct uart_8250_port *)port;
1128
21c614a7
PA		 1129 /* no MSR capabilities */
1130 if (up->bugs & UART_BUG_NOMSR)
1131 return;
1132
1da177e4
LT		 1133 up->ier |= UART_IER_MSI;
1134 serial_out(up, UART_IER, up->ier);
1135}
1136
ea8874dc 1137static void
1da177e4
LT		 1138receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1139{
1140 struct tty_struct *tty = up->port.info->tty;
1141 unsigned char ch, lsr = *status;
1142 int max_count = 256;
1143 char flag;
1144
1145 do {
1da177e4
LT		 1146 ch = serial_inp(up, UART_RX);
1147 flag = TTY_NORMAL;
1148 up->port.icount.rx++;
1149
1150#ifdef CONFIG_SERIAL_8250_CONSOLE
1151 /*
1152 * Recover the break flag from console xmit
1153 */
1154 if (up->port.line == up->port.cons->index) {
1155 lsr |= up->lsr_break_flag;
1156 up->lsr_break_flag = 0;
1157 }
1158#endif
1159
1160 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1161 UART_LSR_FE | UART_LSR_OE))) {
1162 /*
1163 * For statistics only
1164 */
1165 if (lsr & UART_LSR_BI) {
1166 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1167 up->port.icount.brk++;
1168 /*
1169 * We do the SysRQ and SAK checking
1170 * here because otherwise the break
1171 * may get masked by ignore_status_mask
1172 * or read_status_mask.
1173 */
1174 if (uart_handle_break(&up->port))
1175 goto ignore_char;
1176 } else if (lsr & UART_LSR_PE)
1177 up->port.icount.parity++;
1178 else if (lsr & UART_LSR_FE)
1179 up->port.icount.frame++;
1180 if (lsr & UART_LSR_OE)
1181 up->port.icount.overrun++;
1182
1183 /*
23907eb8 1184 * Mask off conditions which should be ignored.
1da177e4
LT		 1185 */
1186 lsr &= up->port.read_status_mask;
1187
1188 if (lsr & UART_LSR_BI) {
1189 DEBUG_INTR("handling break....");
1190 flag = TTY_BREAK;
1191 } else if (lsr & UART_LSR_PE)
1192 flag = TTY_PARITY;
1193 else if (lsr & UART_LSR_FE)
1194 flag = TTY_FRAME;
1195 }
1196 if (uart_handle_sysrq_char(&up->port, ch, regs))
1197 goto ignore_char;
05ab3014
RK		 1198
1199 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1200
1da177e4
LT		 1201 ignore_char:
1202 lsr = serial_inp(up, UART_LSR);
1203 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1204 spin_unlock(&up->port.lock);
1205 tty_flip_buffer_push(tty);
1206 spin_lock(&up->port.lock);
1207 *status = lsr;
1208}
1209
ea8874dc 1210static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1211{
1212 struct circ_buf *xmit = &up->port.info->xmit;
1213 int count;
1214
1215 if (up->port.x_char) {
1216 serial_outp(up, UART_TX, up->port.x_char);
1217 up->port.icount.tx++;
1218 up->port.x_char = 0;
1219 return;
1220 }
b129a8cc
RK		 1221 if (uart_tx_stopped(&up->port)) {
1222 serial8250_stop_tx(&up->port);
1223 return;
1224 }
1225 if (uart_circ_empty(xmit)) {
e763b90c 1226 __stop_tx(up);
1da177e4
LT		 1227 return;
1228 }
1229
1230 count = up->tx_loadsz;
1231 do {
1232 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1233 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1234 up->port.icount.tx++;
1235 if (uart_circ_empty(xmit))
1236 break;
1237 } while (--count > 0);
1238
1239 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1240 uart_write_wakeup(&up->port);
1241
1242 DEBUG_INTR("THRE...");
1243
1244 if (uart_circ_empty(xmit))
e763b90c 1245 __stop_tx(up);
1da177e4
LT		 1246}
1247
2af7cd68 1248static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1249{
2af7cd68
RK		 1250 unsigned int status = serial_in(up, UART_MSR);
1251
1252 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1253 if (status & UART_MSR_TERI)
1254 up->port.icount.rng++;
1255 if (status & UART_MSR_DDSR)
1256 up->port.icount.dsr++;
1257 if (status & UART_MSR_DDCD)
1258 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1259 if (status & UART_MSR_DCTS)
1260 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1261
1262 wake_up_interruptible(&up->port.info->delta_msr_wait);
1263 }
1da177e4 1264
2af7cd68 1265 return status;
1da177e4
LT		 1266}
1267
1268/*
1269 * This handles the interrupt from one port.
1270 */
1271static inline void
1272serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1273{
45e24601
RK		 1274 unsigned int status;
1275
1276 spin_lock(&up->port.lock);
1277
1278 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1279
1280 DEBUG_INTR("status = %x...", status);
1281
1282 if (status & UART_LSR_DR)
1283 receive_chars(up, &status, regs);
1284 check_modem_status(up);
1285 if (status & UART_LSR_THRE)
1286 transmit_chars(up);
45e24601
RK		 1287
1288 spin_unlock(&up->port.lock);
1da177e4
LT		 1289}
1290
1291/*
1292 * This is the serial driver's interrupt routine.
1293 *
1294 * Arjan thinks the old way was overly complex, so it got simplified.
1295 * Alan disagrees, saying that need the complexity to handle the weird
1296 * nature of ISA shared interrupts. (This is a special exception.)
1297 *
1298 * In order to handle ISA shared interrupts properly, we need to check
1299 * that all ports have been serviced, and therefore the ISA interrupt
1300 * line has been de-asserted.
1301 *
1302 * This means we need to loop through all ports. checking that they
1303 * don't have an interrupt pending.
1304 */
1305static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1306{
1307 struct irq_info *i = dev_id;
1308 struct list_head *l, *end = NULL;
1309 int pass_counter = 0, handled = 0;
1310
1311 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1312
1313 spin_lock(&i->lock);
1314
1315 l = i->head;
1316 do {
1317 struct uart_8250_port *up;
1318 unsigned int iir;
1319
1320 up = list_entry(l, struct uart_8250_port, list);
1321
1322 iir = serial_in(up, UART_IIR);
1323 if (!(iir & UART_IIR_NO_INT)) {
1da177e4 1324 serial8250_handle_port(up, regs);
1da177e4
LT		 1325
1326 handled = 1;
1327
1328 end = NULL;
1329 } else if (end == NULL)
1330 end = l;
1331
1332 l = l->next;
1333
1334 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1335 /* If we hit this, we're dead. */
1336 printk(KERN_ERR "serial8250: too much work for "
1337 "irq%d\n", irq);
1338 break;
1339 }
1340 } while (l != end);
1341
1342 spin_unlock(&i->lock);
1343
1344 DEBUG_INTR("end.\n");
1345
1346 return IRQ_RETVAL(handled);
1347}
1348
1349/*
1350 * To support ISA shared interrupts, we need to have one interrupt
1351 * handler that ensures that the IRQ line has been deasserted
1352 * before returning. Failing to do this will result in the IRQ
1353 * line being stuck active, and, since ISA irqs are edge triggered,
1354 * no more IRQs will be seen.
1355 */
1356static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1357{
1358 spin_lock_irq(&i->lock);
1359
1360 if (!list_empty(i->head)) {
1361 if (i->head == &up->list)
1362 i->head = i->head->next;
1363 list_del(&up->list);
1364 } else {
1365 BUG_ON(i->head != &up->list);
1366 i->head = NULL;
1367 }
1368
1369 spin_unlock_irq(&i->lock);
1370}
1371
1372static int serial_link_irq_chain(struct uart_8250_port *up)
1373{
1374 struct irq_info *i = irq_lists + up->port.irq;
1375 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1376
1377 spin_lock_irq(&i->lock);
1378
1379 if (i->head) {
1380 list_add(&up->list, i->head);
1381 spin_unlock_irq(&i->lock);
1382
1383 ret = 0;
1384 } else {
1385 INIT_LIST_HEAD(&up->list);
1386 i->head = &up->list;
1387 spin_unlock_irq(&i->lock);
1388
1389 ret = request_irq(up->port.irq, serial8250_interrupt,
1390 irq_flags, "serial", i);
1391 if (ret < 0)
1392 serial_do_unlink(i, up);
1393 }
1394
1395 return ret;
1396}
1397
1398static void serial_unlink_irq_chain(struct uart_8250_port *up)
1399{
1400 struct irq_info *i = irq_lists + up->port.irq;
1401
1402 BUG_ON(i->head == NULL);
1403
1404 if (list_empty(i->head))
1405 free_irq(up->port.irq, i);
1406
1407 serial_do_unlink(i, up);
1408}
1409
1410/*
1411 * This function is used to handle ports that do not have an
1412 * interrupt. This doesn't work very well for 16450's, but gives
1413 * barely passable results for a 16550A. (Although at the expense
1414 * of much CPU overhead).
1415 */
1416static void serial8250_timeout(unsigned long data)
1417{
1418 struct uart_8250_port *up = (struct uart_8250_port *)data;
1419 unsigned int timeout;
1420 unsigned int iir;
1421
1422 iir = serial_in(up, UART_IIR);
45e24601 1423 if (!(iir & UART_IIR_NO_INT))
1da177e4 1424 serial8250_handle_port(up, NULL);
1da177e4
LT		 1425
1426 timeout = up->port.timeout;
1427 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1428 mod_timer(&up->timer, jiffies + timeout);
1429}
1430
1431static unsigned int serial8250_tx_empty(struct uart_port *port)
1432{
1433 struct uart_8250_port *up = (struct uart_8250_port *)port;
1434 unsigned long flags;
1435 unsigned int ret;
1436
1437 spin_lock_irqsave(&up->port.lock, flags);
1438 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1439 spin_unlock_irqrestore(&up->port.lock, flags);
1440
1441 return ret;
1442}
1443
1444static unsigned int serial8250_get_mctrl(struct uart_port *port)
1445{
1446 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1447 unsigned int status;
1da177e4
LT		 1448 unsigned int ret;
1449
2af7cd68 1450 status = check_modem_status(up);
1da177e4
LT		 1451
1452 ret = 0;
1453 if (status & UART_MSR_DCD)
1454 ret |= TIOCM_CAR;
1455 if (status & UART_MSR_RI)
1456 ret |= TIOCM_RNG;
1457 if (status & UART_MSR_DSR)
1458 ret |= TIOCM_DSR;
1459 if (status & UART_MSR_CTS)
1460 ret |= TIOCM_CTS;
1461 return ret;
1462}
1463
1464static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1465{
1466 struct uart_8250_port *up = (struct uart_8250_port *)port;
1467 unsigned char mcr = 0;
1468
1469 if (mctrl & TIOCM_RTS)
1470 mcr |= UART_MCR_RTS;
1471 if (mctrl & TIOCM_DTR)
1472 mcr |= UART_MCR_DTR;
1473 if (mctrl & TIOCM_OUT1)
1474 mcr |= UART_MCR_OUT1;
1475 if (mctrl & TIOCM_OUT2)
1476 mcr |= UART_MCR_OUT2;
1477 if (mctrl & TIOCM_LOOP)
1478 mcr |= UART_MCR_LOOP;
1479
1480 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1481
1482 serial_out(up, UART_MCR, mcr);
1483}
1484
1485static void serial8250_break_ctl(struct uart_port *port, int break_state)
1486{
1487 struct uart_8250_port *up = (struct uart_8250_port *)port;
1488 unsigned long flags;
1489
1490 spin_lock_irqsave(&up->port.lock, flags);
1491 if (break_state == -1)
1492 up->lcr |= UART_LCR_SBC;
1493 else
1494 up->lcr &= ~UART_LCR_SBC;
1495 serial_out(up, UART_LCR, up->lcr);
1496 spin_unlock_irqrestore(&up->port.lock, flags);
1497}
1498
1499static int serial8250_startup(struct uart_port *port)
1500{
1501 struct uart_8250_port *up = (struct uart_8250_port *)port;
1502 unsigned long flags;
55d3b282 1503 unsigned char lsr, iir;
1da177e4
LT		 1504 int retval;
1505
1506 up->capabilities = uart_config[up->port.type].flags;
1507 up->mcr = 0;
1508
1509 if (up->port.type == PORT_16C950) {
1510 /* Wake up and initialize UART */
1511 up->acr = 0;
1512 serial_outp(up, UART_LCR, 0xBF);
1513 serial_outp(up, UART_EFR, UART_EFR_ECB);
1514 serial_outp(up, UART_IER, 0);
1515 serial_outp(up, UART_LCR, 0);
1516 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1517 serial_outp(up, UART_LCR, 0xBF);
1518 serial_outp(up, UART_EFR, UART_EFR_ECB);
1519 serial_outp(up, UART_LCR, 0);
1520 }
1521
1522#ifdef CONFIG_SERIAL_8250_RSA
1523 /*
1524 * If this is an RSA port, see if we can kick it up to the
1525 * higher speed clock.
1526 */
1527 enable_rsa(up);
1528#endif
1529
1530 /*
1531 * Clear the FIFO buffers and disable them.
1532 * (they will be reeanbled in set_termios())
1533 */
1534 serial8250_clear_fifos(up);
1535
1536 /*
1537 * Clear the interrupt registers.
1538 */
1539 (void) serial_inp(up, UART_LSR);
1540 (void) serial_inp(up, UART_RX);
1541 (void) serial_inp(up, UART_IIR);
1542 (void) serial_inp(up, UART_MSR);
1543
1544 /*
1545 * At this point, there's no way the LSR could still be 0xff;
1546 * if it is, then bail out, because there's likely no UART
1547 * here.
1548 */
1549 if (!(up->port.flags & UPF_BUGGY_UART) &&
1550 (serial_inp(up, UART_LSR) == 0xff)) {
1551 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1552 return -ENODEV;
1553 }
1554
1555 /*
1556 * For a XR16C850, we need to set the trigger levels
1557 */
1558 if (up->port.type == PORT_16850) {
1559 unsigned char fctr;
1560
1561 serial_outp(up, UART_LCR, 0xbf);
1562
1563 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1564 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1565 serial_outp(up, UART_TRG, UART_TRG_96);
1566 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1567 serial_outp(up, UART_TRG, UART_TRG_96);
1568
1569 serial_outp(up, UART_LCR, 0);
1570 }
1571
1572 /*
1573 * If the "interrupt" for this port doesn't correspond with any
1574 * hardware interrupt, we use a timer-based system. The original
1575 * driver used to do this with IRQ0.
1576 */
1577 if (!is_real_interrupt(up->port.irq)) {
1578 unsigned int timeout = up->port.timeout;
1579
1580 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1581
1582 up->timer.data = (unsigned long)up;
1583 mod_timer(&up->timer, jiffies + timeout);
1584 } else {
1585 retval = serial_link_irq_chain(up);
1586 if (retval)
1587 return retval;
1588 }
1589
1590 /*
1591 * Now, initialize the UART
1592 */
1593 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1594
1595 spin_lock_irqsave(&up->port.lock, flags);
1596 if (up->port.flags & UPF_FOURPORT) {
1597 if (!is_real_interrupt(up->port.irq))
1598 up->port.mctrl |= TIOCM_OUT1;
1599 } else
1600 /*
1601 * Most PC uarts need OUT2 raised to enable interrupts.
1602 */
1603 if (is_real_interrupt(up->port.irq))
1604 up->port.mctrl |= TIOCM_OUT2;
1605
1606 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1607
1608 /*
1609 * Do a quick test to see if we receive an
1610 * interrupt when we enable the TX irq.
1611 */
1612 serial_outp(up, UART_IER, UART_IER_THRI);
1613 lsr = serial_in(up, UART_LSR);
1614 iir = serial_in(up, UART_IIR);
1615 serial_outp(up, UART_IER, 0);
1616
1617 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1618 if (!(up->bugs & UART_BUG_TXEN)) {
1619 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1620 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1621 port->line);
1622 }
1623 } else {
67f7654e 1624 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1625 }
1626
1da177e4
LT		 1627 spin_unlock_irqrestore(&up->port.lock, flags);
1628
1629 /*
1630 * Finally, enable interrupts. Note: Modem status interrupts
1631 * are set via set_termios(), which will be occurring imminently
1632 * anyway, so we don't enable them here.
1633 */
1634 up->ier = UART_IER_RLSI | UART_IER_RDI;
1635 serial_outp(up, UART_IER, up->ier);
1636
1637 if (up->port.flags & UPF_FOURPORT) {
1638 unsigned int icp;
1639 /*
1640 * Enable interrupts on the AST Fourport board
1641 */
1642 icp = (up->port.iobase & 0xfe0) | 0x01f;
1643 outb_p(0x80, icp);
1644 (void) inb_p(icp);
1645 }
1646
1647 /*
1648 * And clear the interrupt registers again for luck.
1649 */
1650 (void) serial_inp(up, UART_LSR);
1651 (void) serial_inp(up, UART_RX);
1652 (void) serial_inp(up, UART_IIR);
1653 (void) serial_inp(up, UART_MSR);
1654
1655 return 0;
1656}
1657
1658static void serial8250_shutdown(struct uart_port *port)
1659{
1660 struct uart_8250_port *up = (struct uart_8250_port *)port;
1661 unsigned long flags;
1662
1663 /*
1664 * Disable interrupts from this port
1665 */
1666 up->ier = 0;
1667 serial_outp(up, UART_IER, 0);
1668
1669 spin_lock_irqsave(&up->port.lock, flags);
1670 if (up->port.flags & UPF_FOURPORT) {
1671 /* reset interrupts on the AST Fourport board */
1672 inb((up->port.iobase & 0xfe0) | 0x1f);
1673 up->port.mctrl |= TIOCM_OUT1;
1674 } else
1675 up->port.mctrl &= ~TIOCM_OUT2;
1676
1677 serial8250_set_mctrl(&up->port, up->port.mctrl);
1678 spin_unlock_irqrestore(&up->port.lock, flags);
1679
1680 /*
1681 * Disable break condition and FIFOs
1682 */
1683 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1684 serial8250_clear_fifos(up);
1685
1686#ifdef CONFIG_SERIAL_8250_RSA
1687 /*
1688 * Reset the RSA board back to 115kbps compat mode.
1689 */
1690 disable_rsa(up);
1691#endif
1692
1693 /*
1694 * Read data port to reset things, and then unlink from
1695 * the IRQ chain.
1696 */
1697 (void) serial_in(up, UART_RX);
1698
1699 if (!is_real_interrupt(up->port.irq))
1700 del_timer_sync(&up->timer);
1701 else
1702 serial_unlink_irq_chain(up);
1703}
1704
1705static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1706{
1707 unsigned int quot;
1708
1709 /*
1710 * Handle magic divisors for baud rates above baud_base on
1711 * SMSC SuperIO chips.
1712 */
1713 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1714 baud == (port->uartclk/4))
1715 quot = 0x8001;
1716 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1717 baud == (port->uartclk/8))
1718 quot = 0x8002;
1719 else
1720 quot = uart_get_divisor(port, baud);
1721
1722 return quot;
1723}
1724
1725static void
1726serial8250_set_termios(struct uart_port *port, struct termios *termios,
1727 struct termios *old)
1728{
1729 struct uart_8250_port *up = (struct uart_8250_port *)port;
1730 unsigned char cval, fcr = 0;
1731 unsigned long flags;
1732 unsigned int baud, quot;
1733
1734 switch (termios->c_cflag & CSIZE) {
1735 case CS5:
0a8b80c5 1736 cval = UART_LCR_WLEN5;
1da177e4
LT		 1737 break;
1738 case CS6:
0a8b80c5 1739 cval = UART_LCR_WLEN6;
1da177e4
LT		 1740 break;
1741 case CS7:
0a8b80c5 1742 cval = UART_LCR_WLEN7;
1da177e4
LT		 1743 break;
1744 default:
1745 case CS8:
0a8b80c5 1746 cval = UART_LCR_WLEN8;
1da177e4
LT		 1747 break;
1748 }
1749
1750 if (termios->c_cflag & CSTOPB)
0a8b80c5 1751 cval |= UART_LCR_STOP;
1da177e4
LT		 1752 if (termios->c_cflag & PARENB)
1753 cval |= UART_LCR_PARITY;
1754 if (!(termios->c_cflag & PARODD))
1755 cval |= UART_LCR_EPAR;
1756#ifdef CMSPAR
1757 if (termios->c_cflag & CMSPAR)
1758 cval |= UART_LCR_SPAR;
1759#endif
1760
1761 /*
1762 * Ask the core to calculate the divisor for us.
1763 */
1764 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1765 quot = serial8250_get_divisor(port, baud);
1766
1767 /*
4ba5e35d 1768 * Oxford Semi 952 rev B workaround
1da177e4 1769 */
4ba5e35d 1770 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1771 quot ++;
1772
1773 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1774 if (baud < 2400)
1775 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1776 else
1777 fcr = uart_config[up->port.type].fcr;
1778 }
1779
1780 /*
1781 * MCR-based auto flow control. When AFE is enabled, RTS will be
1782 * deasserted when the receive FIFO contains more characters than
1783 * the trigger, or the MCR RTS bit is cleared. In the case where
1784 * the remote UART is not using CTS auto flow control, we must
1785 * have sufficient FIFO entries for the latency of the remote
1786 * UART to respond. IOW, at least 32 bytes of FIFO.
1787 */
1788 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1789 up->mcr &= ~UART_MCR_AFE;
1790 if (termios->c_cflag & CRTSCTS)
1791 up->mcr |= UART_MCR_AFE;
1792 }
1793
1794 /*
1795 * Ok, we're now changing the port state. Do it with
1796 * interrupts disabled.
1797 */
1798 spin_lock_irqsave(&up->port.lock, flags);
1799
1800 /*
1801 * Update the per-port timeout.
1802 */
1803 uart_update_timeout(port, termios->c_cflag, baud);
1804
1805 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1806 if (termios->c_iflag & INPCK)
1807 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1808 if (termios->c_iflag & (BRKINT | PARMRK))
1809 up->port.read_status_mask |= UART_LSR_BI;
1810
1811 /*
1812 * Characteres to ignore
1813 */
1814 up->port.ignore_status_mask = 0;
1815 if (termios->c_iflag & IGNPAR)
1816 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1817 if (termios->c_iflag & IGNBRK) {
1818 up->port.ignore_status_mask |= UART_LSR_BI;
1819 /*
1820 * If we're ignoring parity and break indicators,
1821 * ignore overruns too (for real raw support).
1822 */
1823 if (termios->c_iflag & IGNPAR)
1824 up->port.ignore_status_mask |= UART_LSR_OE;
1825 }
1826
1827 /*
1828 * ignore all characters if CREAD is not set
1829 */
1830 if ((termios->c_cflag & CREAD) == 0)
1831 up->port.ignore_status_mask |= UART_LSR_DR;
1832
1833 /*
1834 * CTS flow control flag and modem status interrupts
1835 */
1836 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1837 if (!(up->bugs & UART_BUG_NOMSR) &&
1838 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1839 up->ier |= UART_IER_MSI;
1840 if (up->capabilities & UART_CAP_UUE)
1841 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1842
1843 serial_out(up, UART_IER, up->ier);
1844
1845 if (up->capabilities & UART_CAP_EFR) {
1846 unsigned char efr = 0;
1847 /*
1848 * TI16C752/Startech hardware flow control. FIXME:
1849 * - TI16C752 requires control thresholds to be set.
1850 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1851 */
1852 if (termios->c_cflag & CRTSCTS)
1853 efr |= UART_EFR_CTS;
1854
1855 serial_outp(up, UART_LCR, 0xBF);
1856 serial_outp(up, UART_EFR, efr);
1857 }
1858
1859 if (up->capabilities & UART_NATSEMI) {
1860 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1861 serial_outp(up, UART_LCR, 0xe0);
1862 } else {
1863 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1864 }
1865
1866 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1867 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1868
1869 /*
1870 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1871 * is written without DLAB set, this mode will be disabled.
1872 */
1873 if (up->port.type == PORT_16750)
1874 serial_outp(up, UART_FCR, fcr);
1875
1876 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1877 up->lcr = cval; /* Save LCR */
1878 if (up->port.type != PORT_16750) {
1879 if (fcr & UART_FCR_ENABLE_FIFO) {
1880 /* emulated UARTs (Lucent Venus 167x) need two steps */
1881 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1882 }
1883 serial_outp(up, UART_FCR, fcr); /* set fcr */
1884 }
1885 serial8250_set_mctrl(&up->port, up->port.mctrl);
1886 spin_unlock_irqrestore(&up->port.lock, flags);
1887}
1888
1889static void
1890serial8250_pm(struct uart_port *port, unsigned int state,
1891 unsigned int oldstate)
1892{
1893 struct uart_8250_port *p = (struct uart_8250_port *)port;
1894
1895 serial8250_set_sleep(p, state != 0);
1896
1897 if (p->pm)
1898 p->pm(port, state, oldstate);
1899}
1900
1901/*
1902 * Resource handling.
1903 */
1904static int serial8250_request_std_resource(struct uart_8250_port *up)
1905{
1906 unsigned int size = 8 << up->port.regshift;
1907 int ret = 0;
1908
1909 switch (up->port.iotype) {
1910 case UPIO_MEM:
1911 if (!up->port.mapbase)
1912 break;
1913
1914 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1915 ret = -EBUSY;
1916 break;
1917 }
1918
1919 if (up->port.flags & UPF_IOREMAP) {
1920 up->port.membase = ioremap(up->port.mapbase, size);
1921 if (!up->port.membase) {
1922 release_mem_region(up->port.mapbase, size);
1923 ret = -ENOMEM;
1924 }
1925 }
1926 break;
1927
1928 case UPIO_HUB6:
1929 case UPIO_PORT:
1930 if (!request_region(up->port.iobase, size, "serial"))
1931 ret = -EBUSY;
1932 break;
1933 }
1934 return ret;
1935}
1936
1937static void serial8250_release_std_resource(struct uart_8250_port *up)
1938{
1939 unsigned int size = 8 << up->port.regshift;
1940
1941 switch (up->port.iotype) {
1942 case UPIO_MEM:
1943 if (!up->port.mapbase)
1944 break;
1945
1946 if (up->port.flags & UPF_IOREMAP) {
1947 iounmap(up->port.membase);
1948 up->port.membase = NULL;
1949 }
1950
1951 release_mem_region(up->port.mapbase, size);
1952 break;
1953
1954 case UPIO_HUB6:
1955 case UPIO_PORT:
1956 release_region(up->port.iobase, size);
1957 break;
1958 }
1959}
1960
1961static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1962{
1963 unsigned long start = UART_RSA_BASE << up->port.regshift;
1964 unsigned int size = 8 << up->port.regshift;
1965 int ret = 0;
1966
1967 switch (up->port.iotype) {
1968 case UPIO_MEM:
1969 ret = -EINVAL;
1970 break;
1971
1972 case UPIO_HUB6:
1973 case UPIO_PORT:
1974 start += up->port.iobase;
1975 if (!request_region(start, size, "serial-rsa"))
1976 ret = -EBUSY;
1977 break;
1978 }
1979
1980 return ret;
1981}
1982
1983static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1984{
1985 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1986 unsigned int size = 8 << up->port.regshift;
1987
1988 switch (up->port.iotype) {
1989 case UPIO_MEM:
1990 break;
1991
1992 case UPIO_HUB6:
1993 case UPIO_PORT:
1994 release_region(up->port.iobase + offset, size);
1995 break;
1996 }
1997}
1998
1999static void serial8250_release_port(struct uart_port *port)
2000{
2001 struct uart_8250_port *up = (struct uart_8250_port *)port;
2002
2003 serial8250_release_std_resource(up);
2004 if (up->port.type == PORT_RSA)
2005 serial8250_release_rsa_resource(up);
2006}
2007
2008static int serial8250_request_port(struct uart_port *port)
2009{
2010 struct uart_8250_port *up = (struct uart_8250_port *)port;
2011 int ret = 0;
2012
2013 ret = serial8250_request_std_resource(up);
2014 if (ret == 0 && up->port.type == PORT_RSA) {
2015 ret = serial8250_request_rsa_resource(up);
2016 if (ret < 0)
2017 serial8250_release_std_resource(up);
2018 }
2019
2020 return ret;
2021}
2022
2023static void serial8250_config_port(struct uart_port *port, int flags)
2024{
2025 struct uart_8250_port *up = (struct uart_8250_port *)port;
2026 int probeflags = PROBE_ANY;
2027 int ret;
2028
2029 /*
2030 * Don't probe for MCA ports on non-MCA machines.
2031 */
2032 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
2033 return;
2034
2035 /*
2036 * Find the region that we can probe for. This in turn
2037 * tells us whether we can probe for the type of port.
2038 */
2039 ret = serial8250_request_std_resource(up);
2040 if (ret < 0)
2041 return;
2042
2043 ret = serial8250_request_rsa_resource(up);
2044 if (ret < 0)
2045 probeflags &= ~PROBE_RSA;
2046
2047 if (flags & UART_CONFIG_TYPE)
2048 autoconfig(up, probeflags);
2049 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2050 autoconfig_irq(up);
2051
2052 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2053 serial8250_release_rsa_resource(up);
2054 if (up->port.type == PORT_UNKNOWN)
2055 serial8250_release_std_resource(up);
2056}
2057
2058static int
2059serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2060{
2061 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2062 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2063 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2064 ser->type == PORT_STARTECH)
2065 return -EINVAL;
2066 return 0;
2067}
2068
2069static const char *
2070serial8250_type(struct uart_port *port)
2071{
2072 int type = port->type;
2073
2074 if (type >= ARRAY_SIZE(uart_config))
2075 type = 0;
2076 return uart_config[type].name;
2077}
2078
2079static struct uart_ops serial8250_pops = {
2080 .tx_empty = serial8250_tx_empty,
2081 .set_mctrl = serial8250_set_mctrl,
2082 .get_mctrl = serial8250_get_mctrl,
2083 .stop_tx = serial8250_stop_tx,
2084 .start_tx = serial8250_start_tx,
2085 .stop_rx = serial8250_stop_rx,
2086 .enable_ms = serial8250_enable_ms,
2087 .break_ctl = serial8250_break_ctl,
2088 .startup = serial8250_startup,
2089 .shutdown = serial8250_shutdown,
2090 .set_termios = serial8250_set_termios,
2091 .pm = serial8250_pm,
2092 .type = serial8250_type,
2093 .release_port = serial8250_release_port,
2094 .request_port = serial8250_request_port,
2095 .config_port = serial8250_config_port,
2096 .verify_port = serial8250_verify_port,
2097};
2098
2099static struct uart_8250_port serial8250_ports[UART_NR];
2100
2101static void __init serial8250_isa_init_ports(void)
2102{
2103 struct uart_8250_port *up;
2104 static int first = 1;
2105 int i;
2106
2107 if (!first)
2108 return;
2109 first = 0;
2110
a61c2d78 2111 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2112 struct uart_8250_port *up = &serial8250_ports[i];
2113
2114 up->port.line = i;
2115 spin_lock_init(&up->port.lock);
2116
2117 init_timer(&up->timer);
2118 up->timer.function = serial8250_timeout;
2119
2120 /*
2121 * ALPHA_KLUDGE_MCR needs to be killed.
2122 */
2123 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2124 up->mcr_force = ALPHA_KLUDGE_MCR;
2125
2126 up->port.ops = &serial8250_pops;
2127 }
2128
44454bcd 2129 for (i = 0, up = serial8250_ports;
a61c2d78 2130 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2131 i++, up++) {
2132 up->port.iobase = old_serial_port[i].port;
2133 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2134 up->port.uartclk = old_serial_port[i].baud_base * 16;
2135 up->port.flags = old_serial_port[i].flags;
2136 up->port.hub6 = old_serial_port[i].hub6;
2137 up->port.membase = old_serial_port[i].iomem_base;
2138 up->port.iotype = old_serial_port[i].io_type;
2139 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2140 if (share_irqs)
2141 up->port.flags |= UPF_SHARE_IRQ;
2142 }
2143}
2144
2145static void __init
2146serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2147{
2148 int i;
2149
2150 serial8250_isa_init_ports();
2151
a61c2d78 2152 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2153 struct uart_8250_port *up = &serial8250_ports[i];
2154
2155 up->port.dev = dev;
2156 uart_add_one_port(drv, &up->port);
2157 }
2158}
2159
2160#ifdef CONFIG_SERIAL_8250_CONSOLE
2161
2162#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2163
2164/*
2165 * Wait for transmitter & holding register to empty
2166 */
2167static inline void wait_for_xmitr(struct uart_8250_port *up)
2168{
2169 unsigned int status, tmout = 10000;
2170
2171 /* Wait up to 10ms for the character(s) to be sent. */
2172 do {
2173 status = serial_in(up, UART_LSR);
2174
2175 if (status & UART_LSR_BI)
2176 up->lsr_break_flag = UART_LSR_BI;
2177
2178 if (--tmout == 0)
2179 break;
2180 udelay(1);
2181 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2182
2183 /* Wait up to 1s for flow control if necessary */
2184 if (up->port.flags & UPF_CONS_FLOW) {
2185 tmout = 1000000;
2186 while (--tmout &&
2187 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2188 udelay(1);
2189 }
2190}
2191
2192/*
2193 * Print a string to the serial port trying not to disturb
2194 * any possible real use of the port...
2195 *
2196 * The console_lock must be held when we get here.
2197 */
2198static void
2199serial8250_console_write(struct console *co, const char *s, unsigned int count)
2200{
2201 struct uart_8250_port *up = &serial8250_ports[co->index];
2202 unsigned int ier;
2203 int i;
2204
78512ece
AM		 2205 touch_nmi_watchdog();
2206
1da177e4
LT		 2207 /*
2208 * First save the UER then disable the interrupts
2209 */
2210 ier = serial_in(up, UART_IER);
2211
2212 if (up->capabilities & UART_CAP_UUE)
2213 serial_out(up, UART_IER, UART_IER_UUE);
2214 else
2215 serial_out(up, UART_IER, 0);
2216
2217 /*
2218 * Now, do each character
2219 */
2220 for (i = 0; i < count; i++, s++) {
2221 wait_for_xmitr(up);
2222
2223 /*
2224 * Send the character out.
2225 * If a LF, also do CR...
2226 */
2227 serial_out(up, UART_TX, *s);
2228 if (*s == 10) {
2229 wait_for_xmitr(up);
2230 serial_out(up, UART_TX, 13);
2231 }
2232 }
2233
2234 /*
2235 * Finally, wait for transmitter to become empty
2236 * and restore the IER
2237 */
2238 wait_for_xmitr(up);
2239 serial_out(up, UART_IER, ier);
2240}
2241
2242static int serial8250_console_setup(struct console *co, char *options)
2243{
2244 struct uart_port *port;
2245 int baud = 9600;
2246 int bits = 8;
2247 int parity = 'n';
2248 int flow = 'n';
2249
2250 /*
2251 * Check whether an invalid uart number has been specified, and
2252 * if so, search for the first available port that does have
2253 * console support.
2254 */
a61c2d78 2255 if (co->index >= nr_uarts)
1da177e4
LT		 2256 co->index = 0;
2257 port = &serial8250_ports[co->index].port;
2258 if (!port->iobase && !port->membase)
2259 return -ENODEV;
2260
2261 if (options)
2262 uart_parse_options(options, &baud, &parity, &bits, &flow);
2263
2264 return uart_set_options(port, co, baud, parity, bits, flow);
2265}
2266
2267static struct uart_driver serial8250_reg;
2268static struct console serial8250_console = {
2269 .name = "ttyS",
2270 .write = serial8250_console_write,
2271 .device = uart_console_device,
2272 .setup = serial8250_console_setup,
2273 .flags = CON_PRINTBUFFER,
2274 .index = -1,
2275 .data = &serial8250_reg,
2276};
2277
2278static int __init serial8250_console_init(void)
2279{
2280 serial8250_isa_init_ports();
2281 register_console(&serial8250_console);
2282 return 0;
2283}
2284console_initcall(serial8250_console_init);
2285
2286static int __init find_port(struct uart_port *p)
2287{
2288 int line;
2289 struct uart_port *port;
2290
a61c2d78 2291 for (line = 0; line < nr_uarts; line++) {
1da177e4 2292 port = &serial8250_ports[line].port;
50aec3b5 2293 if (uart_match_port(p, port))
1da177e4
LT		 2294 return line;
2295 }
2296 return -ENODEV;
2297}
2298
2299int __init serial8250_start_console(struct uart_port *port, char *options)
2300{
2301 int line;
2302
2303 line = find_port(port);
2304 if (line < 0)
2305 return -ENODEV;
2306
2307 add_preferred_console("ttyS", line, options);
2308 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2309 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2310 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2311 (unsigned long) port->iobase, options);
2312 if (!(serial8250_console.flags & CON_ENABLED)) {
2313 serial8250_console.flags &= ~CON_PRINTBUFFER;
2314 register_console(&serial8250_console);
2315 }
2316 return line;
2317}
2318
2319#define SERIAL8250_CONSOLE &serial8250_console
2320#else
2321#define SERIAL8250_CONSOLE NULL
2322#endif
2323
2324static struct uart_driver serial8250_reg = {
2325 .owner = THIS_MODULE,
2326 .driver_name = "serial",
2327 .devfs_name = "tts/",
2328 .dev_name = "ttyS",
2329 .major = TTY_MAJOR,
2330 .minor = 64,
2331 .nr = UART_NR,
2332 .cons = SERIAL8250_CONSOLE,
2333};
2334
2335int __init early_serial_setup(struct uart_port *port)
2336{
2337 if (port->line >= ARRAY_SIZE(serial8250_ports))
2338 return -ENODEV;
2339
2340 serial8250_isa_init_ports();
2341 serial8250_ports[port->line].port = *port;
2342 serial8250_ports[port->line].port.ops = &serial8250_pops;
2343 return 0;
2344}
2345
2346/**
2347 * serial8250_suspend_port - suspend one serial port
2348 * @line: serial line number
2349 * @level: the level of port suspension, as per uart_suspend_port
2350 *
2351 * Suspend one serial port.
2352 */
2353void serial8250_suspend_port(int line)
2354{
2355 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2356}
2357
2358/**
2359 * serial8250_resume_port - resume one serial port
2360 * @line: serial line number
2361 * @level: the level of port resumption, as per uart_resume_port
2362 *
2363 * Resume one serial port.
2364 */
2365void serial8250_resume_port(int line)
2366{
2367 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2368}
2369
2370/*
2371 * Register a set of serial devices attached to a platform device. The
2372 * list is terminated with a zero flags entry, which means we expect
2373 * all entries to have at least UPF_BOOT_AUTOCONF set.
2374 */
3ae5eaec 2375static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2376{
3ae5eaec 2377 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2378 struct uart_port port;
ec9f47cd 2379 int ret, i;
1da177e4
LT		 2380
2381 memset(&port, 0, sizeof(struct uart_port));
2382
ec9f47cd 2383 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2384 port.iobase = p->iobase;
2385 port.membase = p->membase;
2386 port.irq = p->irq;
2387 port.uartclk = p->uartclk;
2388 port.regshift = p->regshift;
2389 port.iotype = p->iotype;
2390 port.flags = p->flags;
2391 port.mapbase = p->mapbase;
ec9f47cd 2392 port.hub6 = p->hub6;
3ae5eaec 2393 port.dev = &dev->dev;
1da177e4
LT		 2394 if (share_irqs)
2395 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2396 ret = serial8250_register_port(&port);
2397 if (ret < 0) {
3ae5eaec 2398 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2399 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2400 p->iobase, p->mapbase, p->irq, ret);
2401 }
1da177e4
LT		 2402 }
2403 return 0;
2404}
2405
2406/*
2407 * Remove serial ports registered against a platform device.
2408 */
3ae5eaec 2409static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2410{
2411 int i;
2412
a61c2d78 2413 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2414 struct uart_8250_port *up = &serial8250_ports[i];
2415
3ae5eaec 2416 if (up->port.dev == &dev->dev)
1da177e4
LT		 2417 serial8250_unregister_port(i);
2418 }
2419 return 0;
2420}
2421
3ae5eaec 2422static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2423{
2424 int i;
2425
1da177e4
LT		 2426 for (i = 0; i < UART_NR; i++) {
2427 struct uart_8250_port *up = &serial8250_ports[i];
2428
3ae5eaec 2429 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2430 uart_suspend_port(&serial8250_reg, &up->port);
2431 }
2432
2433 return 0;
2434}
2435
3ae5eaec 2436static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2437{
2438 int i;
2439
1da177e4
LT		 2440 for (i = 0; i < UART_NR; i++) {
2441 struct uart_8250_port *up = &serial8250_ports[i];
2442
3ae5eaec 2443 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2444 uart_resume_port(&serial8250_reg, &up->port);
2445 }
2446
2447 return 0;
2448}
2449
3ae5eaec 2450static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2451 .probe = serial8250_probe,
2452 .remove = __devexit_p(serial8250_remove),
2453 .suspend = serial8250_suspend,
2454 .resume = serial8250_resume,
3ae5eaec
RK		 2455 .driver = {
2456 .name = "serial8250",
7493a314 2457 .owner = THIS_MODULE,
3ae5eaec 2458 },
1da177e4
LT		 2459};
2460
2461/*
2462 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2463 * in the table in include/asm/serial.h
2464 */
2465static struct platform_device *serial8250_isa_devs;
2466
2467/*
2468 * serial8250_register_port and serial8250_unregister_port allows for
2469 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2470 * modems and PCI multiport cards.
2471 */
f392ecfa 2472static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2473
2474static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2475{
2476 int i;
2477
2478 /*
2479 * First, find a port entry which matches.
2480 */
a61c2d78 2481 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2482 if (uart_match_port(&serial8250_ports[i].port, port))
2483 return &serial8250_ports[i];
2484
2485 /*
2486 * We didn't find a matching entry, so look for the first
2487 * free entry. We look for one which hasn't been previously
2488 * used (indicated by zero iobase).
2489 */
a61c2d78 2490 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2491 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2492 serial8250_ports[i].port.iobase == 0)
2493 return &serial8250_ports[i];
2494
2495 /*
2496 * That also failed. Last resort is to find any entry which
2497 * doesn't have a real port associated with it.
2498 */
a61c2d78 2499 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2500 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2501 return &serial8250_ports[i];
2502
2503 return NULL;
2504}
2505
2506/**
2507 * serial8250_register_port - register a serial port
2508 * @port: serial port template
2509 *
2510 * Configure the serial port specified by the request. If the
2511 * port exists and is in use, it is hung up and unregistered
2512 * first.
2513 *
2514 * The port is then probed and if necessary the IRQ is autodetected
2515 * If this fails an error is returned.
2516 *
2517 * On success the port is ready to use and the line number is returned.
2518 */
2519int serial8250_register_port(struct uart_port *port)
2520{
2521 struct uart_8250_port *uart;
2522 int ret = -ENOSPC;
2523
2524 if (port->uartclk == 0)
2525 return -EINVAL;
2526
f392ecfa 2527 mutex_lock(&serial_mutex);
1da177e4
LT		 2528
2529 uart = serial8250_find_match_or_unused(port);
2530 if (uart) {
2531 uart_remove_one_port(&serial8250_reg, &uart->port);
2532
2533 uart->port.iobase = port->iobase;
2534 uart->port.membase = port->membase;
2535 uart->port.irq = port->irq;
2536 uart->port.uartclk = port->uartclk;
2537 uart->port.fifosize = port->fifosize;
2538 uart->port.regshift = port->regshift;
2539 uart->port.iotype = port->iotype;
2540 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2541 uart->port.mapbase = port->mapbase;
2542 if (port->dev)
2543 uart->port.dev = port->dev;
2544
2545 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2546 if (ret == 0)
2547 ret = uart->port.line;
2548 }
f392ecfa 2549 mutex_unlock(&serial_mutex);
1da177e4
LT		 2550
2551 return ret;
2552}
2553EXPORT_SYMBOL(serial8250_register_port);
2554
2555/**
2556 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2557 * @line: serial line number
2558 *
2559 * Remove one serial port. This may not be called from interrupt
2560 * context. We hand the port back to the our control.
2561 */
2562void serial8250_unregister_port(int line)
2563{
2564 struct uart_8250_port *uart = &serial8250_ports[line];
2565
f392ecfa 2566 mutex_lock(&serial_mutex);
1da177e4
LT		 2567 uart_remove_one_port(&serial8250_reg, &uart->port);
2568 if (serial8250_isa_devs) {
2569 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2570 uart->port.type = PORT_UNKNOWN;
2571 uart->port.dev = &serial8250_isa_devs->dev;
2572 uart_add_one_port(&serial8250_reg, &uart->port);
2573 } else {
2574 uart->port.dev = NULL;
2575 }
f392ecfa 2576 mutex_unlock(&serial_mutex);
1da177e4
LT		 2577}
2578EXPORT_SYMBOL(serial8250_unregister_port);
2579
2580static int __init serial8250_init(void)
2581{
2582 int ret, i;
2583
a61c2d78
DJ		 2584 if (nr_uarts > UART_NR)
2585 nr_uarts = UART_NR;
2586
1da177e4 2587 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2588 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2589 share_irqs ? "en" : "dis");
2590
2591 for (i = 0; i < NR_IRQS; i++)
2592 spin_lock_init(&irq_lists[i].lock);
2593
2594 ret = uart_register_driver(&serial8250_reg);
2595 if (ret)
2596 goto out;
2597
7493a314
DT		 2598 serial8250_isa_devs = platform_device_alloc("serial8250",
2599 PLAT8250_DEV_LEGACY);
2600 if (!serial8250_isa_devs) {
2601 ret = -ENOMEM;
bc965a7f 2602 goto unreg_uart_drv;
1da177e4
LT		 2603 }
2604
7493a314
DT		 2605 ret = platform_device_add(serial8250_isa_devs);
2606 if (ret)
2607 goto put_dev;
2608
1da177e4
LT		 2609 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2610
bc965a7f
RK		 2611 ret = platform_driver_register(&serial8250_isa_driver);
2612 if (ret == 0)
2613 goto out;
1da177e4 2614
bc965a7f 2615 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2616 put_dev:
2617 platform_device_put(serial8250_isa_devs);
7493a314 2618 unreg_uart_drv:
1da177e4
LT		 2619 uart_unregister_driver(&serial8250_reg);
2620 out:
2621 return ret;
2622}
2623
2624static void __exit serial8250_exit(void)
2625{
2626 struct platform_device *isa_dev = serial8250_isa_devs;
2627
2628 /*
2629 * This tells serial8250_unregister_port() not to re-register
2630 * the ports (thereby making serial8250_isa_driver permanently
2631 * in use.)
2632 */
2633 serial8250_isa_devs = NULL;
2634
3ae5eaec 2635 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2636 platform_device_unregister(isa_dev);
2637
2638 uart_unregister_driver(&serial8250_reg);
2639}
2640
2641module_init(serial8250_init);
2642module_exit(serial8250_exit);
2643
2644EXPORT_SYMBOL(serial8250_suspend_port);
2645EXPORT_SYMBOL(serial8250_resume_port);
2646
2647MODULE_LICENSE("GPL");
2648MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2649
2650module_param(share_irqs, uint, 0644);
2651MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2652 " (unsafe)");
2653
a61c2d78
DJ		 2654module_param(nr_uarts, uint, 0644);
2655MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2656
1da177e4
LT		 2657#ifdef CONFIG_SERIAL_8250_RSA
2658module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2659MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2660#endif
2661MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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