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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
1da177e4
LT		 22
23#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
1da177e4 33#include <linux/delay.h>
d052d1be 34#include <linux/platform_device.h>
1da177e4
LT		 35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_reg.h>
38#include <linux/serial_core.h>
39#include <linux/serial.h>
40#include <linux/serial_8250.h>
78512ece 41#include <linux/nmi.h>
f392ecfa 42#include <linux/mutex.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
40663cc7 51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 55
a61c2d78
DJ		 56static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
57
1da177e4
LT		 58/*
59 * Debugging.
60 */
61#if 0
62#define DEBUG_AUTOCONF(fmt...) printk(fmt)
63#else
64#define DEBUG_AUTOCONF(fmt...) do { } while (0)
65#endif
66
67#if 0
68#define DEBUG_INTR(fmt...) printk(fmt)
69#else
70#define DEBUG_INTR(fmt...) do { } while (0)
71#endif
72
73#define PASS_LIMIT 256
74
75/*
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
79 */
80#define is_real_interrupt(irq) ((irq) != 0)
81
1da177e4
LT		 82#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83#define CONFIG_SERIAL_DETECT_IRQ 1
84#endif
1da177e4
LT		 85#ifdef CONFIG_SERIAL_8250_MANY_PORTS
86#define CONFIG_SERIAL_MANY_PORTS 1
87#endif
88
89/*
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
92 */
93#define CONFIG_HUB6 1
94
95#include <asm/serial.h>
96
97/*
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
101 */
102#ifndef SERIAL_PORT_DFNS
103#define SERIAL_PORT_DFNS
104#endif
105
cb3592be 106static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
108};
109
026d02a2 110#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 111
112#ifdef CONFIG_SERIAL_8250_RSA
113
114#define PORT_RSA_MAX 4
115static unsigned long probe_rsa[PORT_RSA_MAX];
116static unsigned int probe_rsa_count;
117#endif /* CONFIG_SERIAL_8250_RSA */
118
119struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
1da177e4 125 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 126 unsigned char acr;
127 unsigned char ier;
128 unsigned char lcr;
129 unsigned char mcr;
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
132 unsigned char lsr_break_flag;
133
134 /*
135 * We provide a per-port pm hook.
136 */
137 void (*pm)(struct uart_port *port,
138 unsigned int state, unsigned int old);
139};
140
141struct irq_info {
142 spinlock_t lock;
143 struct list_head *head;
144};
145
146static struct irq_info irq_lists[NR_IRQS];
147
148/*
149 * Here we define the default xmit fifo size used for each type of UART.
150 */
151static const struct serial8250_config uart_config[] = {
152 [PORT_UNKNOWN] = {
153 .name = "unknown",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_8250] = {
158 .name = "8250",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16450] = {
163 .name = "16450",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550] = {
168 .name = "16550",
169 .fifo_size = 1,
170 .tx_loadsz = 1,
171 },
172 [PORT_16550A] = {
173 .name = "16550A",
174 .fifo_size = 16,
175 .tx_loadsz = 16,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
177 .flags = UART_CAP_FIFO,
178 },
179 [PORT_CIRRUS] = {
180 .name = "Cirrus",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16650] = {
185 .name = "ST16650",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 },
190 [PORT_16650V2] = {
191 .name = "ST16650V2",
192 .fifo_size = 32,
193 .tx_loadsz = 16,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_00,
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 },
198 [PORT_16750] = {
199 .name = "TI16750",
200 .fifo_size = 64,
201 .tx_loadsz = 64,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
203 UART_FCR7_64BYTE,
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
205 },
206 [PORT_STARTECH] = {
207 .name = "Startech",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 },
211 [PORT_16C950] = {
212 .name = "16C950/954",
213 .fifo_size = 128,
214 .tx_loadsz = 128,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
216 .flags = UART_CAP_FIFO,
217 },
218 [PORT_16654] = {
219 .name = "ST16654",
220 .fifo_size = 64,
221 .tx_loadsz = 32,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_10,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16850] = {
227 .name = "XR16850",
228 .fifo_size = 128,
229 .tx_loadsz = 128,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
232 },
233 [PORT_RSA] = {
234 .name = "RSA",
235 .fifo_size = 2048,
236 .tx_loadsz = 2048,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_NS16550A] = {
241 .name = "NS16550A",
242 .fifo_size = 16,
243 .tx_loadsz = 16,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_NATSEMI,
246 },
247 [PORT_XSCALE] = {
248 .name = "XScale",
249 .fifo_size = 32,
250 .tx_loadsz = 32,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_UUE,
253 },
254};
255
21c614a7
PA		 256#ifdef CONFIG_SERIAL_8250_AU1X00
257
258/* Au1x00 UART hardware has a weird register layout */
259static const u8 au_io_in_map[] = {
260 [UART_RX] = 0,
261 [UART_IER] = 2,
262 [UART_IIR] = 3,
263 [UART_LCR] = 5,
264 [UART_MCR] = 6,
265 [UART_LSR] = 7,
266 [UART_MSR] = 8,
267};
268
269static const u8 au_io_out_map[] = {
270 [UART_TX] = 1,
271 [UART_IER] = 2,
272 [UART_FCR] = 4,
273 [UART_LCR] = 5,
274 [UART_MCR] = 6,
275};
276
277/* sane hardware needs no mapping */
278static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
279{
280 if (up->port.iotype != UPIO_AU)
281 return offset;
282 return au_io_in_map[offset];
283}
284
285static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
286{
287 if (up->port.iotype != UPIO_AU)
288 return offset;
289 return au_io_out_map[offset];
290}
291
292#else
293
294/* sane hardware needs no mapping */
295#define map_8250_in_reg(up, offset) (offset)
296#define map_8250_out_reg(up, offset) (offset)
297
298#endif
299
ea8874dc 300static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 301{
3be91ec7 302 unsigned int tmp;
21c614a7 303 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 304
305 switch (up->port.iotype) {
306 case UPIO_HUB6:
307 outb(up->port.hub6 - 1 + offset, up->port.iobase);
308 return inb(up->port.iobase + 1);
309
310 case UPIO_MEM:
311 return readb(up->port.membase + offset);
312
313 case UPIO_MEM32:
314 return readl(up->port.membase + offset);
315
21c614a7
PA		 316#ifdef CONFIG_SERIAL_8250_AU1X00
317 case UPIO_AU:
318 return __raw_readl(up->port.membase + offset);
319#endif
320
3be91ec7
ZR		 321 case UPIO_TSI:
322 if (offset == UART_IIR) {
9e84b60e
AV		 323 tmp = readl(up->port.membase + (UART_IIR & ~3));
324 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
3be91ec7
ZR		 325 } else
326 return readb(up->port.membase + offset);
327
1da177e4
LT		 328 default:
329 return inb(up->port.iobase + offset);
330 }
331}
332
ea8874dc 333static void
1da177e4
LT		 334serial_out(struct uart_8250_port *up, int offset, int value)
335{
21c614a7 336 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 337
338 switch (up->port.iotype) {
339 case UPIO_HUB6:
340 outb(up->port.hub6 - 1 + offset, up->port.iobase);
341 outb(value, up->port.iobase + 1);
342 break;
343
344 case UPIO_MEM:
345 writeb(value, up->port.membase + offset);
346 break;
347
348 case UPIO_MEM32:
349 writel(value, up->port.membase + offset);
350 break;
351
21c614a7
PA		 352#ifdef CONFIG_SERIAL_8250_AU1X00
353 case UPIO_AU:
354 __raw_writel(value, up->port.membase + offset);
355 break;
356#endif
3be91ec7
ZR		 357 case UPIO_TSI:
358 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
359 writeb(value, up->port.membase + offset);
360 break;
21c614a7 361
1da177e4
LT		 362 default:
363 outb(value, up->port.iobase + offset);
364 }
365}
366
40b36daa
AW		 367static void
368serial_out_sync(struct uart_8250_port *up, int offset, int value)
369{
370 switch (up->port.iotype) {
371 case UPIO_MEM:
372 case UPIO_MEM32:
373#ifdef CONFIG_SERIAL_8250_AU1X00
374 case UPIO_AU:
375#endif
376 serial_out(up, offset, value);
377 serial_in(up, UART_LCR); /* safe, no side-effects */
378 break;
379 default:
380 serial_out(up, offset, value);
381 }
382}
383
1da177e4
LT		 384/*
385 * We used to support using pause I/O for certain machines. We
386 * haven't supported this for a while, but just in case it's badly
387 * needed for certain old 386 machines, I've left these #define's
388 * in....
389 */
390#define serial_inp(up, offset) serial_in(up, offset)
391#define serial_outp(up, offset, value) serial_out(up, offset, value)
392
b32b19b8
JAH		 393/* Uart divisor latch read */
394static inline int _serial_dl_read(struct uart_8250_port *up)
395{
396 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
397}
398
399/* Uart divisor latch write */
400static inline void _serial_dl_write(struct uart_8250_port *up, int value)
401{
402 serial_outp(up, UART_DLL, value & 0xff);
403 serial_outp(up, UART_DLM, value >> 8 & 0xff);
404}
405
406#ifdef CONFIG_SERIAL_8250_AU1X00
407/* Au1x00 haven't got a standard divisor latch */
408static int serial_dl_read(struct uart_8250_port *up)
409{
410 if (up->port.iotype == UPIO_AU)
411 return __raw_readl(up->port.membase + 0x28);
412 else
413 return _serial_dl_read(up);
414}
415
416static void serial_dl_write(struct uart_8250_port *up, int value)
417{
418 if (up->port.iotype == UPIO_AU)
419 __raw_writel(value, up->port.membase + 0x28);
420 else
421 _serial_dl_write(up, value);
422}
423#else
424#define serial_dl_read(up) _serial_dl_read(up)
425#define serial_dl_write(up, value) _serial_dl_write(up, value)
426#endif
1da177e4
LT		 427
428/*
429 * For the 16C950
430 */
431static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
432{
433 serial_out(up, UART_SCR, offset);
434 serial_out(up, UART_ICR, value);
435}
436
437static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
438{
439 unsigned int value;
440
441 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
442 serial_out(up, UART_SCR, offset);
443 value = serial_in(up, UART_ICR);
444 serial_icr_write(up, UART_ACR, up->acr);
445
446 return value;
447}
448
449/*
450 * FIFO support.
451 */
452static inline void serial8250_clear_fifos(struct uart_8250_port *p)
453{
454 if (p->capabilities & UART_CAP_FIFO) {
455 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
456 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
457 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
458 serial_outp(p, UART_FCR, 0);
459 }
460}
461
462/*
463 * IER sleep support. UARTs which have EFRs need the "extended
464 * capability" bit enabled. Note that on XR16C850s, we need to
465 * reset LCR to write to IER.
466 */
467static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
468{
469 if (p->capabilities & UART_CAP_SLEEP) {
470 if (p->capabilities & UART_CAP_EFR) {
471 serial_outp(p, UART_LCR, 0xBF);
472 serial_outp(p, UART_EFR, UART_EFR_ECB);
473 serial_outp(p, UART_LCR, 0);
474 }
475 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
476 if (p->capabilities & UART_CAP_EFR) {
477 serial_outp(p, UART_LCR, 0xBF);
478 serial_outp(p, UART_EFR, 0);
479 serial_outp(p, UART_LCR, 0);
480 }
481 }
482}
483
484#ifdef CONFIG_SERIAL_8250_RSA
485/*
486 * Attempts to turn on the RSA FIFO. Returns zero on failure.
487 * We set the port uart clock rate if we succeed.
488 */
489static int __enable_rsa(struct uart_8250_port *up)
490{
491 unsigned char mode;
492 int result;
493
494 mode = serial_inp(up, UART_RSA_MSR);
495 result = mode & UART_RSA_MSR_FIFO;
496
497 if (!result) {
498 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
499 mode = serial_inp(up, UART_RSA_MSR);
500 result = mode & UART_RSA_MSR_FIFO;
501 }
502
503 if (result)
504 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
505
506 return result;
507}
508
509static void enable_rsa(struct uart_8250_port *up)
510{
511 if (up->port.type == PORT_RSA) {
512 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
513 spin_lock_irq(&up->port.lock);
514 __enable_rsa(up);
515 spin_unlock_irq(&up->port.lock);
516 }
517 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
518 serial_outp(up, UART_RSA_FRR, 0);
519 }
520}
521
522/*
523 * Attempts to turn off the RSA FIFO. Returns zero on failure.
524 * It is unknown why interrupts were disabled in here. However,
525 * the caller is expected to preserve this behaviour by grabbing
526 * the spinlock before calling this function.
527 */
528static void disable_rsa(struct uart_8250_port *up)
529{
530 unsigned char mode;
531 int result;
532
533 if (up->port.type == PORT_RSA &&
534 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
535 spin_lock_irq(&up->port.lock);
536
537 mode = serial_inp(up, UART_RSA_MSR);
538 result = !(mode & UART_RSA_MSR_FIFO);
539
540 if (!result) {
541 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
542 mode = serial_inp(up, UART_RSA_MSR);
543 result = !(mode & UART_RSA_MSR_FIFO);
544 }
545
546 if (result)
547 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
548 spin_unlock_irq(&up->port.lock);
549 }
550}
551#endif /* CONFIG_SERIAL_8250_RSA */
552
553/*
554 * This is a quickie test to see how big the FIFO is.
555 * It doesn't work at all the time, more's the pity.
556 */
557static int size_fifo(struct uart_8250_port *up)
558{
b32b19b8
JAH		 559 unsigned char old_fcr, old_mcr, old_lcr;
560 unsigned short old_dl;
1da177e4
LT		 561 int count;
562
563 old_lcr = serial_inp(up, UART_LCR);
564 serial_outp(up, UART_LCR, 0);
565 old_fcr = serial_inp(up, UART_FCR);
566 old_mcr = serial_inp(up, UART_MCR);
567 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
568 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
569 serial_outp(up, UART_MCR, UART_MCR_LOOP);
570 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 571 old_dl = serial_dl_read(up);
572 serial_dl_write(up, 0x0001);
1da177e4
LT		 573 serial_outp(up, UART_LCR, 0x03);
574 for (count = 0; count < 256; count++)
575 serial_outp(up, UART_TX, count);
576 mdelay(20);/* FIXME - schedule_timeout */
577 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
578 (count < 256); count++)
579 serial_inp(up, UART_RX);
580 serial_outp(up, UART_FCR, old_fcr);
581 serial_outp(up, UART_MCR, old_mcr);
582 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 583 serial_dl_write(up, old_dl);
1da177e4
LT		 584 serial_outp(up, UART_LCR, old_lcr);
585
586 return count;
587}
588
589/*
590 * Read UART ID using the divisor method - set DLL and DLM to zero
591 * and the revision will be in DLL and device type in DLM. We
592 * preserve the device state across this.
593 */
594static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
595{
596 unsigned char old_dll, old_dlm, old_lcr;
597 unsigned int id;
598
599 old_lcr = serial_inp(p, UART_LCR);
600 serial_outp(p, UART_LCR, UART_LCR_DLAB);
601
602 old_dll = serial_inp(p, UART_DLL);
603 old_dlm = serial_inp(p, UART_DLM);
604
605 serial_outp(p, UART_DLL, 0);
606 serial_outp(p, UART_DLM, 0);
607
608 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
609
610 serial_outp(p, UART_DLL, old_dll);
611 serial_outp(p, UART_DLM, old_dlm);
612 serial_outp(p, UART_LCR, old_lcr);
613
614 return id;
615}
616
617/*
618 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
619 * When this function is called we know it is at least a StarTech
620 * 16650 V2, but it might be one of several StarTech UARTs, or one of
621 * its clones. (We treat the broken original StarTech 16650 V1 as a
622 * 16550, and why not? Startech doesn't seem to even acknowledge its
623 * existence.)
624 *
625 * What evil have men's minds wrought...
626 */
627static void autoconfig_has_efr(struct uart_8250_port *up)
628{
629 unsigned int id1, id2, id3, rev;
630
631 /*
632 * Everything with an EFR has SLEEP
633 */
634 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
635
636 /*
637 * First we check to see if it's an Oxford Semiconductor UART.
638 *
639 * If we have to do this here because some non-National
640 * Semiconductor clone chips lock up if you try writing to the
641 * LSR register (which serial_icr_read does)
642 */
643
644 /*
645 * Check for Oxford Semiconductor 16C950.
646 *
647 * EFR [4] must be set else this test fails.
648 *
649 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
650 * claims that it's needed for 952 dual UART's (which are not
651 * recommended for new designs).
652 */
653 up->acr = 0;
654 serial_out(up, UART_LCR, 0xBF);
655 serial_out(up, UART_EFR, UART_EFR_ECB);
656 serial_out(up, UART_LCR, 0x00);
657 id1 = serial_icr_read(up, UART_ID1);
658 id2 = serial_icr_read(up, UART_ID2);
659 id3 = serial_icr_read(up, UART_ID3);
660 rev = serial_icr_read(up, UART_REV);
661
662 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
663
664 if (id1 == 0x16 && id2 == 0xC9 &&
665 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
666 up->port.type = PORT_16C950;
4ba5e35d
RK		 667
668 /*
669 * Enable work around for the Oxford Semiconductor 952 rev B
670 * chip which causes it to seriously miscalculate baud rates
671 * when DLL is 0.
672 */
673 if (id3 == 0x52 && rev == 0x01)
674 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 675 return;
676 }
677
678 /*
679 * We check for a XR16C850 by setting DLL and DLM to 0, and then
680 * reading back DLL and DLM. The chip type depends on the DLM
681 * value read back:
682 * 0x10 - XR16C850 and the DLL contains the chip revision.
683 * 0x12 - XR16C2850.
684 * 0x14 - XR16C854.
685 */
686 id1 = autoconfig_read_divisor_id(up);
687 DEBUG_AUTOCONF("850id=%04x ", id1);
688
689 id2 = id1 >> 8;
690 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 691 up->port.type = PORT_16850;
692 return;
693 }
694
695 /*
696 * It wasn't an XR16C850.
697 *
698 * We distinguish between the '654 and the '650 by counting
699 * how many bytes are in the FIFO. I'm using this for now,
700 * since that's the technique that was sent to me in the
701 * serial driver update, but I'm not convinced this works.
702 * I've had problems doing this in the past. -TYT
703 */
704 if (size_fifo(up) == 64)
705 up->port.type = PORT_16654;
706 else
707 up->port.type = PORT_16650V2;
708}
709
710/*
711 * We detected a chip without a FIFO. Only two fall into
712 * this category - the original 8250 and the 16450. The
713 * 16450 has a scratch register (accessible with LCR=0)
714 */
715static void autoconfig_8250(struct uart_8250_port *up)
716{
717 unsigned char scratch, status1, status2;
718
719 up->port.type = PORT_8250;
720
721 scratch = serial_in(up, UART_SCR);
722 serial_outp(up, UART_SCR, 0xa5);
723 status1 = serial_in(up, UART_SCR);
724 serial_outp(up, UART_SCR, 0x5a);
725 status2 = serial_in(up, UART_SCR);
726 serial_outp(up, UART_SCR, scratch);
727
728 if (status1 == 0xa5 && status2 == 0x5a)
729 up->port.type = PORT_16450;
730}
731
732static int broken_efr(struct uart_8250_port *up)
733{
734 /*
735 * Exar ST16C2550 "A2" devices incorrectly detect as
736 * having an EFR, and report an ID of 0x0201. See
737 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
738 */
739 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
740 return 1;
741
742 return 0;
743}
744
745/*
746 * We know that the chip has FIFOs. Does it have an EFR? The
747 * EFR is located in the same register position as the IIR and
748 * we know the top two bits of the IIR are currently set. The
749 * EFR should contain zero. Try to read the EFR.
750 */
751static void autoconfig_16550a(struct uart_8250_port *up)
752{
753 unsigned char status1, status2;
754 unsigned int iersave;
755
756 up->port.type = PORT_16550A;
757 up->capabilities |= UART_CAP_FIFO;
758
759 /*
760 * Check for presence of the EFR when DLAB is set.
761 * Only ST16C650V1 UARTs pass this test.
762 */
763 serial_outp(up, UART_LCR, UART_LCR_DLAB);
764 if (serial_in(up, UART_EFR) == 0) {
765 serial_outp(up, UART_EFR, 0xA8);
766 if (serial_in(up, UART_EFR) != 0) {
767 DEBUG_AUTOCONF("EFRv1 ");
768 up->port.type = PORT_16650;
769 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
770 } else {
771 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
772 }
773 serial_outp(up, UART_EFR, 0);
774 return;
775 }
776
777 /*
778 * Maybe it requires 0xbf to be written to the LCR.
779 * (other ST16C650V2 UARTs, TI16C752A, etc)
780 */
781 serial_outp(up, UART_LCR, 0xBF);
782 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
783 DEBUG_AUTOCONF("EFRv2 ");
784 autoconfig_has_efr(up);
785 return;
786 }
787
788 /*
789 * Check for a National Semiconductor SuperIO chip.
790 * Attempt to switch to bank 2, read the value of the LOOP bit
791 * from EXCR1. Switch back to bank 0, change it in MCR. Then
792 * switch back to bank 2, read it from EXCR1 again and check
793 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 794 */
795 serial_outp(up, UART_LCR, 0);
796 status1 = serial_in(up, UART_MCR);
797 serial_outp(up, UART_LCR, 0xE0);
798 status2 = serial_in(up, 0x02); /* EXCR1 */
799
800 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
801 serial_outp(up, UART_LCR, 0);
802 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
803 serial_outp(up, UART_LCR, 0xE0);
804 status2 = serial_in(up, 0x02); /* EXCR1 */
805 serial_outp(up, UART_LCR, 0);
806 serial_outp(up, UART_MCR, status1);
807
808 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 809 unsigned short quot;
810
1da177e4 811 serial_outp(up, UART_LCR, 0xE0);
857dde2e 812
b32b19b8 813 quot = serial_dl_read(up);
857dde2e
DW		 814 quot <<= 3;
815
1da177e4
LT		 816 status1 = serial_in(up, 0x04); /* EXCR1 */
817 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
818 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
819 serial_outp(up, 0x04, status1);
857dde2e 820
b32b19b8 821 serial_dl_write(up, quot);
857dde2e 822
1da177e4 823 serial_outp(up, UART_LCR, 0);
1da177e4 824
857dde2e 825 up->port.uartclk = 921600*16;
1da177e4
LT		 826 up->port.type = PORT_NS16550A;
827 up->capabilities |= UART_NATSEMI;
828 return;
829 }
830 }
831
832 /*
833 * No EFR. Try to detect a TI16750, which only sets bit 5 of
834 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
835 * Try setting it with and without DLAB set. Cheap clones
836 * set bit 5 without DLAB set.
837 */
838 serial_outp(up, UART_LCR, 0);
839 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
840 status1 = serial_in(up, UART_IIR) >> 5;
841 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
842 serial_outp(up, UART_LCR, UART_LCR_DLAB);
843 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
844 status2 = serial_in(up, UART_IIR) >> 5;
845 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
846 serial_outp(up, UART_LCR, 0);
847
848 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
849
850 if (status1 == 6 && status2 == 7) {
851 up->port.type = PORT_16750;
852 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
853 return;
854 }
855
856 /*
857 * Try writing and reading the UART_IER_UUE bit (b6).
858 * If it works, this is probably one of the Xscale platform's
859 * internal UARTs.
860 * We're going to explicitly set the UUE bit to 0 before
861 * trying to write and read a 1 just to make sure it's not
862 * already a 1 and maybe locked there before we even start start.
863 */
864 iersave = serial_in(up, UART_IER);
865 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
866 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
867 /*
868 * OK it's in a known zero state, try writing and reading
869 * without disturbing the current state of the other bits.
870 */
871 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
872 if (serial_in(up, UART_IER) & UART_IER_UUE) {
873 /*
874 * It's an Xscale.
875 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
876 */
877 DEBUG_AUTOCONF("Xscale ");
878 up->port.type = PORT_XSCALE;
879 up->capabilities |= UART_CAP_UUE;
880 return;
881 }
882 } else {
883 /*
884 * If we got here we couldn't force the IER_UUE bit to 0.
885 * Log it and continue.
886 */
887 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
888 }
889 serial_outp(up, UART_IER, iersave);
890}
891
892/*
893 * This routine is called by rs_init() to initialize a specific serial
894 * port. It determines what type of UART chip this serial port is
895 * using: 8250, 16450, 16550, 16550A. The important question is
896 * whether or not this UART is a 16550A or not, since this will
897 * determine whether or not we can use its FIFO features or not.
898 */
899static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
900{
901 unsigned char status1, scratch, scratch2, scratch3;
902 unsigned char save_lcr, save_mcr;
903 unsigned long flags;
904
905 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
906 return;
907
908 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
909 up->port.line, up->port.iobase, up->port.membase);
910
911 /*
912 * We really do need global IRQs disabled here - we're going to
913 * be frobbing the chips IRQ enable register to see if it exists.
914 */
915 spin_lock_irqsave(&up->port.lock, flags);
916// save_flags(flags); cli();
917
918 up->capabilities = 0;
4ba5e35d 919 up->bugs = 0;
1da177e4
LT		 920
921 if (!(up->port.flags & UPF_BUGGY_UART)) {
922 /*
923 * Do a simple existence test first; if we fail this,
924 * there's no point trying anything else.
925 *
926 * 0x80 is used as a nonsense port to prevent against
927 * false positives due to ISA bus float. The
928 * assumption is that 0x80 is a non-existent port;
929 * which should be safe since include/asm/io.h also
930 * makes this assumption.
931 *
932 * Note: this is safe as long as MCR bit 4 is clear
933 * and the device is in "PC" mode.
934 */
935 scratch = serial_inp(up, UART_IER);
936 serial_outp(up, UART_IER, 0);
937#ifdef __i386__
938 outb(0xff, 0x080);
939#endif
48212008
TH		 940 /*
941 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
942 * 16C754B) allow only to modify them if an EFR bit is set.
943 */
944 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 945 serial_outp(up, UART_IER, 0x0F);
946#ifdef __i386__
947 outb(0, 0x080);
948#endif
48212008 949 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 950 serial_outp(up, UART_IER, scratch);
951 if (scratch2 != 0 || scratch3 != 0x0F) {
952 /*
953 * We failed; there's nothing here
954 */
955 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
956 scratch2, scratch3);
957 goto out;
958 }
959 }
960
961 save_mcr = serial_in(up, UART_MCR);
962 save_lcr = serial_in(up, UART_LCR);
963
964 /*
965 * Check to see if a UART is really there. Certain broken
966 * internal modems based on the Rockwell chipset fail this
967 * test, because they apparently don't implement the loopback
968 * test mode. So this test is skipped on the COM 1 through
969 * COM 4 ports. This *should* be safe, since no board
970 * manufacturer would be stupid enough to design a board
971 * that conflicts with COM 1-4 --- we hope!
972 */
973 if (!(up->port.flags & UPF_SKIP_TEST)) {
974 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
975 status1 = serial_inp(up, UART_MSR) & 0xF0;
976 serial_outp(up, UART_MCR, save_mcr);
977 if (status1 != 0x90) {
978 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
979 status1);
980 goto out;
981 }
982 }
983
984 /*
985 * We're pretty sure there's a port here. Lets find out what
986 * type of port it is. The IIR top two bits allows us to find
6f0d618f 987 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 988 * determines what we test for next.
989 *
990 * We also initialise the EFR (if any) to zero for later. The
991 * EFR occupies the same register location as the FCR and IIR.
992 */
993 serial_outp(up, UART_LCR, 0xBF);
994 serial_outp(up, UART_EFR, 0);
995 serial_outp(up, UART_LCR, 0);
996
997 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
998 scratch = serial_in(up, UART_IIR) >> 6;
999
1000 DEBUG_AUTOCONF("iir=%d ", scratch);
1001
1002 switch (scratch) {
1003 case 0:
1004 autoconfig_8250(up);
1005 break;
1006 case 1:
1007 up->port.type = PORT_UNKNOWN;
1008 break;
1009 case 2:
1010 up->port.type = PORT_16550;
1011 break;
1012 case 3:
1013 autoconfig_16550a(up);
1014 break;
1015 }
1016
1017#ifdef CONFIG_SERIAL_8250_RSA
1018 /*
1019 * Only probe for RSA ports if we got the region.
1020 */
1021 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1022 int i;
1023
1024 for (i = 0 ; i < probe_rsa_count; ++i) {
1025 if (probe_rsa[i] == up->port.iobase &&
1026 __enable_rsa(up)) {
1027 up->port.type = PORT_RSA;
1028 break;
1029 }
1030 }
1031 }
1032#endif
21c614a7
PA		 1033
1034#ifdef CONFIG_SERIAL_8250_AU1X00
1035 /* if access method is AU, it is a 16550 with a quirk */
1036 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1037 up->bugs |= UART_BUG_NOMSR;
1038#endif
1039
1da177e4
LT		 1040 serial_outp(up, UART_LCR, save_lcr);
1041
1042 if (up->capabilities != uart_config[up->port.type].flags) {
1043 printk(KERN_WARNING
1044 "ttyS%d: detected caps %08x should be %08x\n",
1045 up->port.line, up->capabilities,
1046 uart_config[up->port.type].flags);
1047 }
1048
1049 up->port.fifosize = uart_config[up->port.type].fifo_size;
1050 up->capabilities = uart_config[up->port.type].flags;
1051 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1052
1053 if (up->port.type == PORT_UNKNOWN)
1054 goto out;
1055
1056 /*
1057 * Reset the UART.
1058 */
1059#ifdef CONFIG_SERIAL_8250_RSA
1060 if (up->port.type == PORT_RSA)
1061 serial_outp(up, UART_RSA_FRR, 0);
1062#endif
1063 serial_outp(up, UART_MCR, save_mcr);
1064 serial8250_clear_fifos(up);
40b36daa 1065 serial_in(up, UART_RX);
5c8c755c
LB		 1066 if (up->capabilities & UART_CAP_UUE)
1067 serial_outp(up, UART_IER, UART_IER_UUE);
1068 else
1069 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1070
1071 out:
1072 spin_unlock_irqrestore(&up->port.lock, flags);
1073// restore_flags(flags);
1074 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1075}
1076
1077static void autoconfig_irq(struct uart_8250_port *up)
1078{
1079 unsigned char save_mcr, save_ier;
1080 unsigned char save_ICP = 0;
1081 unsigned int ICP = 0;
1082 unsigned long irqs;
1083 int irq;
1084
1085 if (up->port.flags & UPF_FOURPORT) {
1086 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1087 save_ICP = inb_p(ICP);
1088 outb_p(0x80, ICP);
1089 (void) inb_p(ICP);
1090 }
1091
1092 /* forget possible initially masked and pending IRQ */
1093 probe_irq_off(probe_irq_on());
1094 save_mcr = serial_inp(up, UART_MCR);
1095 save_ier = serial_inp(up, UART_IER);
1096 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1097
1098 irqs = probe_irq_on();
1099 serial_outp(up, UART_MCR, 0);
1100 udelay (10);
1101 if (up->port.flags & UPF_FOURPORT) {
1102 serial_outp(up, UART_MCR,
1103 UART_MCR_DTR | UART_MCR_RTS);
1104 } else {
1105 serial_outp(up, UART_MCR,
1106 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1107 }
1108 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1109 (void)serial_inp(up, UART_LSR);
1110 (void)serial_inp(up, UART_RX);
1111 (void)serial_inp(up, UART_IIR);
1112 (void)serial_inp(up, UART_MSR);
1113 serial_outp(up, UART_TX, 0xFF);
1114 udelay (20);
1115 irq = probe_irq_off(irqs);
1116
1117 serial_outp(up, UART_MCR, save_mcr);
1118 serial_outp(up, UART_IER, save_ier);
1119
1120 if (up->port.flags & UPF_FOURPORT)
1121 outb_p(save_ICP, ICP);
1122
1123 up->port.irq = (irq > 0) ? irq : 0;
1124}
1125
e763b90c
RK		 1126static inline void __stop_tx(struct uart_8250_port *p)
1127{
1128 if (p->ier & UART_IER_THRI) {
1129 p->ier &= ~UART_IER_THRI;
1130 serial_out(p, UART_IER, p->ier);
1131 }
1132}
1133
b129a8cc 1134static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1135{
1136 struct uart_8250_port *up = (struct uart_8250_port *)port;
1137
e763b90c 1138 __stop_tx(up);
1da177e4
LT		 1139
1140 /*
e763b90c 1141 * We really want to stop the transmitter from sending.
1da177e4 1142 */
e763b90c 1143 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1144 up->acr |= UART_ACR_TXDIS;
1145 serial_icr_write(up, UART_ACR, up->acr);
1146 }
1147}
1148
55d3b282
RK		 1149static void transmit_chars(struct uart_8250_port *up);
1150
b129a8cc 1151static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1152{
1153 struct uart_8250_port *up = (struct uart_8250_port *)port;
1154
1155 if (!(up->ier & UART_IER_THRI)) {
1156 up->ier |= UART_IER_THRI;
1157 serial_out(up, UART_IER, up->ier);
55d3b282 1158
67f7654e 1159 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1160 unsigned char lsr, iir;
1161 lsr = serial_in(up, UART_LSR);
1162 iir = serial_in(up, UART_IIR);
1163 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1164 transmit_chars(up);
1165 }
1da177e4 1166 }
e763b90c 1167
1da177e4 1168 /*
e763b90c 1169 * Re-enable the transmitter if we disabled it.
1da177e4 1170 */
e763b90c 1171 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1172 up->acr &= ~UART_ACR_TXDIS;
1173 serial_icr_write(up, UART_ACR, up->acr);
1174 }
1175}
1176
1177static void serial8250_stop_rx(struct uart_port *port)
1178{
1179 struct uart_8250_port *up = (struct uart_8250_port *)port;
1180
1181 up->ier &= ~UART_IER_RLSI;
1182 up->port.read_status_mask &= ~UART_LSR_DR;
1183 serial_out(up, UART_IER, up->ier);
1184}
1185
1186static void serial8250_enable_ms(struct uart_port *port)
1187{
1188 struct uart_8250_port *up = (struct uart_8250_port *)port;
1189
21c614a7
PA		 1190 /* no MSR capabilities */
1191 if (up->bugs & UART_BUG_NOMSR)
1192 return;
1193
1da177e4
LT		 1194 up->ier |= UART_IER_MSI;
1195 serial_out(up, UART_IER, up->ier);
1196}
1197
ea8874dc 1198static void
cc79aa9d 1199receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4
LT		 1200{
1201 struct tty_struct *tty = up->port.info->tty;
1202 unsigned char ch, lsr = *status;
1203 int max_count = 256;
1204 char flag;
1205
1206 do {
1da177e4
LT		 1207 ch = serial_inp(up, UART_RX);
1208 flag = TTY_NORMAL;
1209 up->port.icount.rx++;
1210
1211#ifdef CONFIG_SERIAL_8250_CONSOLE
1212 /*
1213 * Recover the break flag from console xmit
1214 */
1215 if (up->port.line == up->port.cons->index) {
1216 lsr |= up->lsr_break_flag;
1217 up->lsr_break_flag = 0;
1218 }
1219#endif
1220
1221 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1222 UART_LSR_FE | UART_LSR_OE))) {
1223 /*
1224 * For statistics only
1225 */
1226 if (lsr & UART_LSR_BI) {
1227 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1228 up->port.icount.brk++;
1229 /*
1230 * We do the SysRQ and SAK checking
1231 * here because otherwise the break
1232 * may get masked by ignore_status_mask
1233 * or read_status_mask.
1234 */
1235 if (uart_handle_break(&up->port))
1236 goto ignore_char;
1237 } else if (lsr & UART_LSR_PE)
1238 up->port.icount.parity++;
1239 else if (lsr & UART_LSR_FE)
1240 up->port.icount.frame++;
1241 if (lsr & UART_LSR_OE)
1242 up->port.icount.overrun++;
1243
1244 /*
23907eb8 1245 * Mask off conditions which should be ignored.
1da177e4
LT		 1246 */
1247 lsr &= up->port.read_status_mask;
1248
1249 if (lsr & UART_LSR_BI) {
1250 DEBUG_INTR("handling break....");
1251 flag = TTY_BREAK;
1252 } else if (lsr & UART_LSR_PE)
1253 flag = TTY_PARITY;
1254 else if (lsr & UART_LSR_FE)
1255 flag = TTY_FRAME;
1256 }
7d12e780 1257 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1258 goto ignore_char;
05ab3014
RK		 1259
1260 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1261
1da177e4
LT		 1262 ignore_char:
1263 lsr = serial_inp(up, UART_LSR);
1264 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1265 spin_unlock(&up->port.lock);
1266 tty_flip_buffer_push(tty);
1267 spin_lock(&up->port.lock);
1268 *status = lsr;
1269}
1270
ea8874dc 1271static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1272{
1273 struct circ_buf *xmit = &up->port.info->xmit;
1274 int count;
1275
1276 if (up->port.x_char) {
1277 serial_outp(up, UART_TX, up->port.x_char);
1278 up->port.icount.tx++;
1279 up->port.x_char = 0;
1280 return;
1281 }
b129a8cc
RK		 1282 if (uart_tx_stopped(&up->port)) {
1283 serial8250_stop_tx(&up->port);
1284 return;
1285 }
1286 if (uart_circ_empty(xmit)) {
e763b90c 1287 __stop_tx(up);
1da177e4
LT		 1288 return;
1289 }
1290
1291 count = up->tx_loadsz;
1292 do {
1293 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1294 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1295 up->port.icount.tx++;
1296 if (uart_circ_empty(xmit))
1297 break;
1298 } while (--count > 0);
1299
1300 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1301 uart_write_wakeup(&up->port);
1302
1303 DEBUG_INTR("THRE...");
1304
1305 if (uart_circ_empty(xmit))
e763b90c 1306 __stop_tx(up);
1da177e4
LT		 1307}
1308
2af7cd68 1309static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1310{
2af7cd68
RK		 1311 unsigned int status = serial_in(up, UART_MSR);
1312
fdc30b3d
TI		 1313 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1314 up->port.info != NULL) {
2af7cd68
RK		 1315 if (status & UART_MSR_TERI)
1316 up->port.icount.rng++;
1317 if (status & UART_MSR_DDSR)
1318 up->port.icount.dsr++;
1319 if (status & UART_MSR_DDCD)
1320 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1321 if (status & UART_MSR_DCTS)
1322 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1323
1324 wake_up_interruptible(&up->port.info->delta_msr_wait);
1325 }
1da177e4 1326
2af7cd68 1327 return status;
1da177e4
LT		 1328}
1329
1330/*
1331 * This handles the interrupt from one port.
1332 */
1333static inline void
7d12e780 1334serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1335{
45e24601 1336 unsigned int status;
4bf3631c 1337 unsigned long flags;
45e24601 1338
4bf3631c 1339 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1340
1341 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1342
1343 DEBUG_INTR("status = %x...", status);
1344
1345 if (status & UART_LSR_DR)
7d12e780 1346 receive_chars(up, &status);
1da177e4
LT		 1347 check_modem_status(up);
1348 if (status & UART_LSR_THRE)
1349 transmit_chars(up);
45e24601 1350
4bf3631c 1351 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1352}
1353
1354/*
1355 * This is the serial driver's interrupt routine.
1356 *
1357 * Arjan thinks the old way was overly complex, so it got simplified.
1358 * Alan disagrees, saying that need the complexity to handle the weird
1359 * nature of ISA shared interrupts. (This is a special exception.)
1360 *
1361 * In order to handle ISA shared interrupts properly, we need to check
1362 * that all ports have been serviced, and therefore the ISA interrupt
1363 * line has been de-asserted.
1364 *
1365 * This means we need to loop through all ports. checking that they
1366 * don't have an interrupt pending.
1367 */
7d12e780 1368static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1369{
1370 struct irq_info *i = dev_id;
1371 struct list_head *l, *end = NULL;
1372 int pass_counter = 0, handled = 0;
1373
1374 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1375
1376 spin_lock(&i->lock);
1377
1378 l = i->head;
1379 do {
1380 struct uart_8250_port *up;
1381 unsigned int iir;
1382
1383 up = list_entry(l, struct uart_8250_port, list);
1384
1385 iir = serial_in(up, UART_IIR);
1386 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1387 serial8250_handle_port(up);
1da177e4
LT		 1388
1389 handled = 1;
1390
1391 end = NULL;
1392 } else if (end == NULL)
1393 end = l;
1394
1395 l = l->next;
1396
1397 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1398 /* If we hit this, we're dead. */
1399 printk(KERN_ERR "serial8250: too much work for "
1400 "irq%d\n", irq);
1401 break;
1402 }
1403 } while (l != end);
1404
1405 spin_unlock(&i->lock);
1406
1407 DEBUG_INTR("end.\n");
1408
1409 return IRQ_RETVAL(handled);
1410}
1411
1412/*
1413 * To support ISA shared interrupts, we need to have one interrupt
1414 * handler that ensures that the IRQ line has been deasserted
1415 * before returning. Failing to do this will result in the IRQ
1416 * line being stuck active, and, since ISA irqs are edge triggered,
1417 * no more IRQs will be seen.
1418 */
1419static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1420{
1421 spin_lock_irq(&i->lock);
1422
1423 if (!list_empty(i->head)) {
1424 if (i->head == &up->list)
1425 i->head = i->head->next;
1426 list_del(&up->list);
1427 } else {
1428 BUG_ON(i->head != &up->list);
1429 i->head = NULL;
1430 }
1431
1432 spin_unlock_irq(&i->lock);
1433}
1434
1435static int serial_link_irq_chain(struct uart_8250_port *up)
1436{
1437 struct irq_info *i = irq_lists + up->port.irq;
40663cc7 1438 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4
LT		 1439
1440 spin_lock_irq(&i->lock);
1441
1442 if (i->head) {
1443 list_add(&up->list, i->head);
1444 spin_unlock_irq(&i->lock);
1445
1446 ret = 0;
1447 } else {
1448 INIT_LIST_HEAD(&up->list);
1449 i->head = &up->list;
1450 spin_unlock_irq(&i->lock);
1451
1452 ret = request_irq(up->port.irq, serial8250_interrupt,
1453 irq_flags, "serial", i);
1454 if (ret < 0)
1455 serial_do_unlink(i, up);
1456 }
1457
1458 return ret;
1459}
1460
1461static void serial_unlink_irq_chain(struct uart_8250_port *up)
1462{
1463 struct irq_info *i = irq_lists + up->port.irq;
1464
1465 BUG_ON(i->head == NULL);
1466
1467 if (list_empty(i->head))
1468 free_irq(up->port.irq, i);
1469
1470 serial_do_unlink(i, up);
1471}
1472
40b36daa
AW		 1473/* Base timer interval for polling */
1474static inline int poll_timeout(int timeout)
1475{
1476 return timeout > 6 ? (timeout / 2 - 2) : 1;
1477}
1478
1da177e4
LT		 1479/*
1480 * This function is used to handle ports that do not have an
1481 * interrupt. This doesn't work very well for 16450's, but gives
1482 * barely passable results for a 16550A. (Although at the expense
1483 * of much CPU overhead).
1484 */
1485static void serial8250_timeout(unsigned long data)
1486{
1487 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1488 unsigned int iir;
1489
1490 iir = serial_in(up, UART_IIR);
45e24601 1491 if (!(iir & UART_IIR_NO_INT))
7d12e780 1492 serial8250_handle_port(up);
40b36daa
AW		 1493 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1494}
1495
1496static void serial8250_backup_timeout(unsigned long data)
1497{
1498 struct uart_8250_port *up = (struct uart_8250_port *)data;
1499 unsigned int iir, ier = 0;
1500
1501 /*
1502 * Must disable interrupts or else we risk racing with the interrupt
1503 * based handler.
1504 */
1505 if (is_real_interrupt(up->port.irq)) {
1506 ier = serial_in(up, UART_IER);
1507 serial_out(up, UART_IER, 0);
1508 }
1da177e4 1509
40b36daa
AW		 1510 iir = serial_in(up, UART_IIR);
1511
1512 /*
1513 * This should be a safe test for anyone who doesn't trust the
1514 * IIR bits on their UART, but it's specifically designed for
1515 * the "Diva" UART used on the management processor on many HP
1516 * ia64 and parisc boxes.
1517 */
1518 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1519 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1520 (serial_in(up, UART_LSR) & UART_LSR_THRE)) {
1521 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1522 iir |= UART_IIR_THRI;
1523 }
1524
1525 if (!(iir & UART_IIR_NO_INT))
1526 serial8250_handle_port(up);
1527
1528 if (is_real_interrupt(up->port.irq))
1529 serial_out(up, UART_IER, ier);
1530
1531 /* Standard timer interval plus 0.2s to keep the port running */
1532 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout) + HZ/5);
1da177e4
LT		 1533}
1534
1535static unsigned int serial8250_tx_empty(struct uart_port *port)
1536{
1537 struct uart_8250_port *up = (struct uart_8250_port *)port;
1538 unsigned long flags;
1539 unsigned int ret;
1540
1541 spin_lock_irqsave(&up->port.lock, flags);
1542 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1543 spin_unlock_irqrestore(&up->port.lock, flags);
1544
1545 return ret;
1546}
1547
1548static unsigned int serial8250_get_mctrl(struct uart_port *port)
1549{
1550 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1551 unsigned int status;
1da177e4
LT		 1552 unsigned int ret;
1553
2af7cd68 1554 status = check_modem_status(up);
1da177e4
LT		 1555
1556 ret = 0;
1557 if (status & UART_MSR_DCD)
1558 ret |= TIOCM_CAR;
1559 if (status & UART_MSR_RI)
1560 ret |= TIOCM_RNG;
1561 if (status & UART_MSR_DSR)
1562 ret |= TIOCM_DSR;
1563 if (status & UART_MSR_CTS)
1564 ret |= TIOCM_CTS;
1565 return ret;
1566}
1567
1568static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1569{
1570 struct uart_8250_port *up = (struct uart_8250_port *)port;
1571 unsigned char mcr = 0;
1572
1573 if (mctrl & TIOCM_RTS)
1574 mcr |= UART_MCR_RTS;
1575 if (mctrl & TIOCM_DTR)
1576 mcr |= UART_MCR_DTR;
1577 if (mctrl & TIOCM_OUT1)
1578 mcr |= UART_MCR_OUT1;
1579 if (mctrl & TIOCM_OUT2)
1580 mcr |= UART_MCR_OUT2;
1581 if (mctrl & TIOCM_LOOP)
1582 mcr |= UART_MCR_LOOP;
1583
1584 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1585
1586 serial_out(up, UART_MCR, mcr);
1587}
1588
1589static void serial8250_break_ctl(struct uart_port *port, int break_state)
1590{
1591 struct uart_8250_port *up = (struct uart_8250_port *)port;
1592 unsigned long flags;
1593
1594 spin_lock_irqsave(&up->port.lock, flags);
1595 if (break_state == -1)
1596 up->lcr |= UART_LCR_SBC;
1597 else
1598 up->lcr &= ~UART_LCR_SBC;
1599 serial_out(up, UART_LCR, up->lcr);
1600 spin_unlock_irqrestore(&up->port.lock, flags);
1601}
1602
40b36daa
AW		 1603#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1604
1605/*
1606 * Wait for transmitter & holding register to empty
1607 */
1608static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1609{
1610 unsigned int status, tmout = 10000;
1611
1612 /* Wait up to 10ms for the character(s) to be sent. */
1613 do {
1614 status = serial_in(up, UART_LSR);
1615
1616 if (status & UART_LSR_BI)
1617 up->lsr_break_flag = UART_LSR_BI;
1618
1619 if (--tmout == 0)
1620 break;
1621 udelay(1);
1622 } while ((status & bits) != bits);
1623
1624 /* Wait up to 1s for flow control if necessary */
1625 if (up->port.flags & UPF_CONS_FLOW) {
1626 tmout = 1000000;
1627 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
1628 udelay(1);
1629 touch_nmi_watchdog();
1630 }
1631 }
1632}
1633
1da177e4
LT		 1634static int serial8250_startup(struct uart_port *port)
1635{
1636 struct uart_8250_port *up = (struct uart_8250_port *)port;
1637 unsigned long flags;
55d3b282 1638 unsigned char lsr, iir;
1da177e4
LT		 1639 int retval;
1640
1641 up->capabilities = uart_config[up->port.type].flags;
1642 up->mcr = 0;
1643
1644 if (up->port.type == PORT_16C950) {
1645 /* Wake up and initialize UART */
1646 up->acr = 0;
1647 serial_outp(up, UART_LCR, 0xBF);
1648 serial_outp(up, UART_EFR, UART_EFR_ECB);
1649 serial_outp(up, UART_IER, 0);
1650 serial_outp(up, UART_LCR, 0);
1651 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1652 serial_outp(up, UART_LCR, 0xBF);
1653 serial_outp(up, UART_EFR, UART_EFR_ECB);
1654 serial_outp(up, UART_LCR, 0);
1655 }
1656
1657#ifdef CONFIG_SERIAL_8250_RSA
1658 /*
1659 * If this is an RSA port, see if we can kick it up to the
1660 * higher speed clock.
1661 */
1662 enable_rsa(up);
1663#endif
1664
1665 /*
1666 * Clear the FIFO buffers and disable them.
7f927fcc 1667 * (they will be reenabled in set_termios())
1da177e4
LT		 1668 */
1669 serial8250_clear_fifos(up);
1670
1671 /*
1672 * Clear the interrupt registers.
1673 */
1674 (void) serial_inp(up, UART_LSR);
1675 (void) serial_inp(up, UART_RX);
1676 (void) serial_inp(up, UART_IIR);
1677 (void) serial_inp(up, UART_MSR);
1678
1679 /*
1680 * At this point, there's no way the LSR could still be 0xff;
1681 * if it is, then bail out, because there's likely no UART
1682 * here.
1683 */
1684 if (!(up->port.flags & UPF_BUGGY_UART) &&
1685 (serial_inp(up, UART_LSR) == 0xff)) {
1686 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1687 return -ENODEV;
1688 }
1689
1690 /*
1691 * For a XR16C850, we need to set the trigger levels
1692 */
1693 if (up->port.type == PORT_16850) {
1694 unsigned char fctr;
1695
1696 serial_outp(up, UART_LCR, 0xbf);
1697
1698 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1699 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1700 serial_outp(up, UART_TRG, UART_TRG_96);
1701 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1702 serial_outp(up, UART_TRG, UART_TRG_96);
1703
1704 serial_outp(up, UART_LCR, 0);
1705 }
1706
40b36daa
AW		 1707 if (is_real_interrupt(up->port.irq)) {
1708 /*
1709 * Test for UARTs that do not reassert THRE when the
1710 * transmitter is idle and the interrupt has already
1711 * been cleared. Real 16550s should always reassert
1712 * this interrupt whenever the transmitter is idle and
1713 * the interrupt is enabled. Delays are necessary to
1714 * allow register changes to become visible.
1715 */
1716 spin_lock_irqsave(&up->port.lock, flags);
1717
1718 wait_for_xmitr(up, UART_LSR_THRE);
1719 serial_out_sync(up, UART_IER, UART_IER_THRI);
1720 udelay(1); /* allow THRE to set */
1721 serial_in(up, UART_IIR);
1722 serial_out(up, UART_IER, 0);
1723 serial_out_sync(up, UART_IER, UART_IER_THRI);
1724 udelay(1); /* allow a working UART time to re-assert THRE */
1725 iir = serial_in(up, UART_IIR);
1726 serial_out(up, UART_IER, 0);
1727
1728 spin_unlock_irqrestore(&up->port.lock, flags);
1729
1730 /*
1731 * If the interrupt is not reasserted, setup a timer to
1732 * kick the UART on a regular basis.
1733 */
1734 if (iir & UART_IIR_NO_INT) {
1735 pr_debug("ttyS%d - using backup timer\n", port->line);
1736 up->timer.function = serial8250_backup_timeout;
1737 up->timer.data = (unsigned long)up;
1738 mod_timer(&up->timer, jiffies +
1739 poll_timeout(up->port.timeout) + HZ/5);
1740 }
1741 }
1742
1da177e4
LT		 1743 /*
1744 * If the "interrupt" for this port doesn't correspond with any
1745 * hardware interrupt, we use a timer-based system. The original
1746 * driver used to do this with IRQ0.
1747 */
1748 if (!is_real_interrupt(up->port.irq)) {
1da177e4 1749 up->timer.data = (unsigned long)up;
40b36daa 1750 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 1751 } else {
1752 retval = serial_link_irq_chain(up);
1753 if (retval)
1754 return retval;
1755 }
1756
1757 /*
1758 * Now, initialize the UART
1759 */
1760 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1761
1762 spin_lock_irqsave(&up->port.lock, flags);
1763 if (up->port.flags & UPF_FOURPORT) {
1764 if (!is_real_interrupt(up->port.irq))
1765 up->port.mctrl |= TIOCM_OUT1;
1766 } else
1767 /*
1768 * Most PC uarts need OUT2 raised to enable interrupts.
1769 */
1770 if (is_real_interrupt(up->port.irq))
1771 up->port.mctrl |= TIOCM_OUT2;
1772
1773 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1774
1775 /*
1776 * Do a quick test to see if we receive an
1777 * interrupt when we enable the TX irq.
1778 */
1779 serial_outp(up, UART_IER, UART_IER_THRI);
1780 lsr = serial_in(up, UART_LSR);
1781 iir = serial_in(up, UART_IIR);
1782 serial_outp(up, UART_IER, 0);
1783
1784 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1785 if (!(up->bugs & UART_BUG_TXEN)) {
1786 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1787 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1788 port->line);
1789 }
1790 } else {
67f7654e 1791 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1792 }
1793
1da177e4
LT		 1794 spin_unlock_irqrestore(&up->port.lock, flags);
1795
1796 /*
1797 * Finally, enable interrupts. Note: Modem status interrupts
1798 * are set via set_termios(), which will be occurring imminently
1799 * anyway, so we don't enable them here.
1800 */
1801 up->ier = UART_IER_RLSI | UART_IER_RDI;
1802 serial_outp(up, UART_IER, up->ier);
1803
1804 if (up->port.flags & UPF_FOURPORT) {
1805 unsigned int icp;
1806 /*
1807 * Enable interrupts on the AST Fourport board
1808 */
1809 icp = (up->port.iobase & 0xfe0) | 0x01f;
1810 outb_p(0x80, icp);
1811 (void) inb_p(icp);
1812 }
1813
1814 /*
1815 * And clear the interrupt registers again for luck.
1816 */
1817 (void) serial_inp(up, UART_LSR);
1818 (void) serial_inp(up, UART_RX);
1819 (void) serial_inp(up, UART_IIR);
1820 (void) serial_inp(up, UART_MSR);
1821
1822 return 0;
1823}
1824
1825static void serial8250_shutdown(struct uart_port *port)
1826{
1827 struct uart_8250_port *up = (struct uart_8250_port *)port;
1828 unsigned long flags;
1829
1830 /*
1831 * Disable interrupts from this port
1832 */
1833 up->ier = 0;
1834 serial_outp(up, UART_IER, 0);
1835
1836 spin_lock_irqsave(&up->port.lock, flags);
1837 if (up->port.flags & UPF_FOURPORT) {
1838 /* reset interrupts on the AST Fourport board */
1839 inb((up->port.iobase & 0xfe0) | 0x1f);
1840 up->port.mctrl |= TIOCM_OUT1;
1841 } else
1842 up->port.mctrl &= ~TIOCM_OUT2;
1843
1844 serial8250_set_mctrl(&up->port, up->port.mctrl);
1845 spin_unlock_irqrestore(&up->port.lock, flags);
1846
1847 /*
1848 * Disable break condition and FIFOs
1849 */
1850 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1851 serial8250_clear_fifos(up);
1852
1853#ifdef CONFIG_SERIAL_8250_RSA
1854 /*
1855 * Reset the RSA board back to 115kbps compat mode.
1856 */
1857 disable_rsa(up);
1858#endif
1859
1860 /*
1861 * Read data port to reset things, and then unlink from
1862 * the IRQ chain.
1863 */
1864 (void) serial_in(up, UART_RX);
1865
40b36daa
AW		 1866 del_timer_sync(&up->timer);
1867 up->timer.function = serial8250_timeout;
1868 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 1869 serial_unlink_irq_chain(up);
1870}
1871
1872static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1873{
1874 unsigned int quot;
1875
1876 /*
1877 * Handle magic divisors for baud rates above baud_base on
1878 * SMSC SuperIO chips.
1879 */
1880 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1881 baud == (port->uartclk/4))
1882 quot = 0x8001;
1883 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1884 baud == (port->uartclk/8))
1885 quot = 0x8002;
1886 else
1887 quot = uart_get_divisor(port, baud);
1888
1889 return quot;
1890}
1891
1892static void
606d099c
AC		 1893serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
1894 struct ktermios *old)
1da177e4
LT		 1895{
1896 struct uart_8250_port *up = (struct uart_8250_port *)port;
1897 unsigned char cval, fcr = 0;
1898 unsigned long flags;
1899 unsigned int baud, quot;
1900
1901 switch (termios->c_cflag & CSIZE) {
1902 case CS5:
0a8b80c5 1903 cval = UART_LCR_WLEN5;
1da177e4
LT		 1904 break;
1905 case CS6:
0a8b80c5 1906 cval = UART_LCR_WLEN6;
1da177e4
LT		 1907 break;
1908 case CS7:
0a8b80c5 1909 cval = UART_LCR_WLEN7;
1da177e4
LT		 1910 break;
1911 default:
1912 case CS8:
0a8b80c5 1913 cval = UART_LCR_WLEN8;
1da177e4
LT		 1914 break;
1915 }
1916
1917 if (termios->c_cflag & CSTOPB)
0a8b80c5 1918 cval |= UART_LCR_STOP;
1da177e4
LT		 1919 if (termios->c_cflag & PARENB)
1920 cval |= UART_LCR_PARITY;
1921 if (!(termios->c_cflag & PARODD))
1922 cval |= UART_LCR_EPAR;
1923#ifdef CMSPAR
1924 if (termios->c_cflag & CMSPAR)
1925 cval |= UART_LCR_SPAR;
1926#endif
1927
1928 /*
1929 * Ask the core to calculate the divisor for us.
1930 */
1931 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1932 quot = serial8250_get_divisor(port, baud);
1933
1934 /*
4ba5e35d 1935 * Oxford Semi 952 rev B workaround
1da177e4 1936 */
4ba5e35d 1937 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1938 quot ++;
1939
1940 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1941 if (baud < 2400)
1942 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1943 else
1944 fcr = uart_config[up->port.type].fcr;
1945 }
1946
1947 /*
1948 * MCR-based auto flow control. When AFE is enabled, RTS will be
1949 * deasserted when the receive FIFO contains more characters than
1950 * the trigger, or the MCR RTS bit is cleared. In the case where
1951 * the remote UART is not using CTS auto flow control, we must
1952 * have sufficient FIFO entries for the latency of the remote
1953 * UART to respond. IOW, at least 32 bytes of FIFO.
1954 */
1955 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1956 up->mcr &= ~UART_MCR_AFE;
1957 if (termios->c_cflag & CRTSCTS)
1958 up->mcr |= UART_MCR_AFE;
1959 }
1960
1961 /*
1962 * Ok, we're now changing the port state. Do it with
1963 * interrupts disabled.
1964 */
1965 spin_lock_irqsave(&up->port.lock, flags);
1966
1967 /*
1968 * Update the per-port timeout.
1969 */
1970 uart_update_timeout(port, termios->c_cflag, baud);
1971
1972 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1973 if (termios->c_iflag & INPCK)
1974 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1975 if (termios->c_iflag & (BRKINT | PARMRK))
1976 up->port.read_status_mask |= UART_LSR_BI;
1977
1978 /*
1979 * Characteres to ignore
1980 */
1981 up->port.ignore_status_mask = 0;
1982 if (termios->c_iflag & IGNPAR)
1983 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1984 if (termios->c_iflag & IGNBRK) {
1985 up->port.ignore_status_mask |= UART_LSR_BI;
1986 /*
1987 * If we're ignoring parity and break indicators,
1988 * ignore overruns too (for real raw support).
1989 */
1990 if (termios->c_iflag & IGNPAR)
1991 up->port.ignore_status_mask |= UART_LSR_OE;
1992 }
1993
1994 /*
1995 * ignore all characters if CREAD is not set
1996 */
1997 if ((termios->c_cflag & CREAD) == 0)
1998 up->port.ignore_status_mask |= UART_LSR_DR;
1999
2000 /*
2001 * CTS flow control flag and modem status interrupts
2002 */
2003 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2004 if (!(up->bugs & UART_BUG_NOMSR) &&
2005 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2006 up->ier |= UART_IER_MSI;
2007 if (up->capabilities & UART_CAP_UUE)
2008 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2009
2010 serial_out(up, UART_IER, up->ier);
2011
2012 if (up->capabilities & UART_CAP_EFR) {
2013 unsigned char efr = 0;
2014 /*
2015 * TI16C752/Startech hardware flow control. FIXME:
2016 * - TI16C752 requires control thresholds to be set.
2017 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2018 */
2019 if (termios->c_cflag & CRTSCTS)
2020 efr |= UART_EFR_CTS;
2021
2022 serial_outp(up, UART_LCR, 0xBF);
2023 serial_outp(up, UART_EFR, efr);
2024 }
2025
255341c6
JM		 2026#ifdef CONFIG_ARCH_OMAP15XX
2027 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2028 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2029 if (baud == 115200) {
2030 quot = 1;
2031 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2032 } else
2033 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2034 }
2035#endif
2036
1da177e4
LT		 2037 if (up->capabilities & UART_NATSEMI) {
2038 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2039 serial_outp(up, UART_LCR, 0xe0);
2040 } else {
2041 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2042 }
2043
b32b19b8 2044 serial_dl_write(up, quot);
1da177e4
LT		 2045
2046 /*
2047 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2048 * is written without DLAB set, this mode will be disabled.
2049 */
2050 if (up->port.type == PORT_16750)
2051 serial_outp(up, UART_FCR, fcr);
2052
2053 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2054 up->lcr = cval; /* Save LCR */
2055 if (up->port.type != PORT_16750) {
2056 if (fcr & UART_FCR_ENABLE_FIFO) {
2057 /* emulated UARTs (Lucent Venus 167x) need two steps */
2058 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2059 }
2060 serial_outp(up, UART_FCR, fcr); /* set fcr */
2061 }
2062 serial8250_set_mctrl(&up->port, up->port.mctrl);
2063 spin_unlock_irqrestore(&up->port.lock, flags);
2064}
2065
2066static void
2067serial8250_pm(struct uart_port *port, unsigned int state,
2068 unsigned int oldstate)
2069{
2070 struct uart_8250_port *p = (struct uart_8250_port *)port;
2071
2072 serial8250_set_sleep(p, state != 0);
2073
2074 if (p->pm)
2075 p->pm(port, state, oldstate);
2076}
2077
2078/*
2079 * Resource handling.
2080 */
2081static int serial8250_request_std_resource(struct uart_8250_port *up)
2082{
2083 unsigned int size = 8 << up->port.regshift;
2084 int ret = 0;
2085
2086 switch (up->port.iotype) {
85835f44
SS		 2087 case UPIO_AU:
2088 size = 0x100000;
2089 /* fall thru */
0b30d668
SS		 2090 case UPIO_TSI:
2091 case UPIO_MEM32:
1da177e4
LT		 2092 case UPIO_MEM:
2093 if (!up->port.mapbase)
2094 break;
2095
2096 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2097 ret = -EBUSY;
2098 break;
2099 }
2100
2101 if (up->port.flags & UPF_IOREMAP) {
2102 up->port.membase = ioremap(up->port.mapbase, size);
2103 if (!up->port.membase) {
2104 release_mem_region(up->port.mapbase, size);
2105 ret = -ENOMEM;
2106 }
2107 }
2108 break;
2109
2110 case UPIO_HUB6:
2111 case UPIO_PORT:
2112 if (!request_region(up->port.iobase, size, "serial"))
2113 ret = -EBUSY;
2114 break;
2115 }
2116 return ret;
2117}
2118
2119static void serial8250_release_std_resource(struct uart_8250_port *up)
2120{
2121 unsigned int size = 8 << up->port.regshift;
2122
2123 switch (up->port.iotype) {
85835f44
SS		 2124 case UPIO_AU:
2125 size = 0x100000;
2126 /* fall thru */
0b30d668
SS		 2127 case UPIO_TSI:
2128 case UPIO_MEM32:
1da177e4
LT		 2129 case UPIO_MEM:
2130 if (!up->port.mapbase)
2131 break;
2132
2133 if (up->port.flags & UPF_IOREMAP) {
2134 iounmap(up->port.membase);
2135 up->port.membase = NULL;
2136 }
2137
2138 release_mem_region(up->port.mapbase, size);
2139 break;
2140
2141 case UPIO_HUB6:
2142 case UPIO_PORT:
2143 release_region(up->port.iobase, size);
2144 break;
2145 }
2146}
2147
2148static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2149{
2150 unsigned long start = UART_RSA_BASE << up->port.regshift;
2151 unsigned int size = 8 << up->port.regshift;
0b30d668 2152 int ret = -EINVAL;
1da177e4
LT		 2153
2154 switch (up->port.iotype) {
1da177e4
LT		 2155 case UPIO_HUB6:
2156 case UPIO_PORT:
2157 start += up->port.iobase;
0b30d668
SS		 2158 if (request_region(start, size, "serial-rsa"))
2159 ret = 0;
2160 else
1da177e4
LT		 2161 ret = -EBUSY;
2162 break;
2163 }
2164
2165 return ret;
2166}
2167
2168static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2169{
2170 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2171 unsigned int size = 8 << up->port.regshift;
2172
2173 switch (up->port.iotype) {
1da177e4
LT		 2174 case UPIO_HUB6:
2175 case UPIO_PORT:
2176 release_region(up->port.iobase + offset, size);
2177 break;
2178 }
2179}
2180
2181static void serial8250_release_port(struct uart_port *port)
2182{
2183 struct uart_8250_port *up = (struct uart_8250_port *)port;
2184
2185 serial8250_release_std_resource(up);
2186 if (up->port.type == PORT_RSA)
2187 serial8250_release_rsa_resource(up);
2188}
2189
2190static int serial8250_request_port(struct uart_port *port)
2191{
2192 struct uart_8250_port *up = (struct uart_8250_port *)port;
2193 int ret = 0;
2194
2195 ret = serial8250_request_std_resource(up);
2196 if (ret == 0 && up->port.type == PORT_RSA) {
2197 ret = serial8250_request_rsa_resource(up);
2198 if (ret < 0)
2199 serial8250_release_std_resource(up);
2200 }
2201
2202 return ret;
2203}
2204
2205static void serial8250_config_port(struct uart_port *port, int flags)
2206{
2207 struct uart_8250_port *up = (struct uart_8250_port *)port;
2208 int probeflags = PROBE_ANY;
2209 int ret;
2210
1da177e4
LT		 2211 /*
2212 * Find the region that we can probe for. This in turn
2213 * tells us whether we can probe for the type of port.
2214 */
2215 ret = serial8250_request_std_resource(up);
2216 if (ret < 0)
2217 return;
2218
2219 ret = serial8250_request_rsa_resource(up);
2220 if (ret < 0)
2221 probeflags &= ~PROBE_RSA;
2222
2223 if (flags & UART_CONFIG_TYPE)
2224 autoconfig(up, probeflags);
2225 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2226 autoconfig_irq(up);
2227
2228 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2229 serial8250_release_rsa_resource(up);
2230 if (up->port.type == PORT_UNKNOWN)
2231 serial8250_release_std_resource(up);
2232}
2233
2234static int
2235serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2236{
2237 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2238 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2239 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2240 ser->type == PORT_STARTECH)
2241 return -EINVAL;
2242 return 0;
2243}
2244
2245static const char *
2246serial8250_type(struct uart_port *port)
2247{
2248 int type = port->type;
2249
2250 if (type >= ARRAY_SIZE(uart_config))
2251 type = 0;
2252 return uart_config[type].name;
2253}
2254
2255static struct uart_ops serial8250_pops = {
2256 .tx_empty = serial8250_tx_empty,
2257 .set_mctrl = serial8250_set_mctrl,
2258 .get_mctrl = serial8250_get_mctrl,
2259 .stop_tx = serial8250_stop_tx,
2260 .start_tx = serial8250_start_tx,
2261 .stop_rx = serial8250_stop_rx,
2262 .enable_ms = serial8250_enable_ms,
2263 .break_ctl = serial8250_break_ctl,
2264 .startup = serial8250_startup,
2265 .shutdown = serial8250_shutdown,
2266 .set_termios = serial8250_set_termios,
2267 .pm = serial8250_pm,
2268 .type = serial8250_type,
2269 .release_port = serial8250_release_port,
2270 .request_port = serial8250_request_port,
2271 .config_port = serial8250_config_port,
2272 .verify_port = serial8250_verify_port,
2273};
2274
2275static struct uart_8250_port serial8250_ports[UART_NR];
2276
2277static void __init serial8250_isa_init_ports(void)
2278{
2279 struct uart_8250_port *up;
2280 static int first = 1;
2281 int i;
2282
2283 if (!first)
2284 return;
2285 first = 0;
2286
a61c2d78 2287 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2288 struct uart_8250_port *up = &serial8250_ports[i];
2289
2290 up->port.line = i;
2291 spin_lock_init(&up->port.lock);
2292
2293 init_timer(&up->timer);
2294 up->timer.function = serial8250_timeout;
2295
2296 /*
2297 * ALPHA_KLUDGE_MCR needs to be killed.
2298 */
2299 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2300 up->mcr_force = ALPHA_KLUDGE_MCR;
2301
2302 up->port.ops = &serial8250_pops;
2303 }
2304
44454bcd 2305 for (i = 0, up = serial8250_ports;
a61c2d78 2306 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2307 i++, up++) {
2308 up->port.iobase = old_serial_port[i].port;
2309 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2310 up->port.uartclk = old_serial_port[i].baud_base * 16;
2311 up->port.flags = old_serial_port[i].flags;
2312 up->port.hub6 = old_serial_port[i].hub6;
2313 up->port.membase = old_serial_port[i].iomem_base;
2314 up->port.iotype = old_serial_port[i].io_type;
2315 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2316 if (share_irqs)
2317 up->port.flags |= UPF_SHARE_IRQ;
2318 }
2319}
2320
2321static void __init
2322serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2323{
2324 int i;
2325
2326 serial8250_isa_init_ports();
2327
a61c2d78 2328 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2329 struct uart_8250_port *up = &serial8250_ports[i];
2330
2331 up->port.dev = dev;
2332 uart_add_one_port(drv, &up->port);
2333 }
2334}
2335
2336#ifdef CONFIG_SERIAL_8250_CONSOLE
2337
d358788f
RK		 2338static void serial8250_console_putchar(struct uart_port *port, int ch)
2339{
2340 struct uart_8250_port *up = (struct uart_8250_port *)port;
2341
2342 wait_for_xmitr(up, UART_LSR_THRE);
2343 serial_out(up, UART_TX, ch);
2344}
2345
1da177e4
LT		 2346/*
2347 * Print a string to the serial port trying not to disturb
2348 * any possible real use of the port...
2349 *
2350 * The console_lock must be held when we get here.
2351 */
2352static void
2353serial8250_console_write(struct console *co, const char *s, unsigned int count)
2354{
2355 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2356 unsigned long flags;
1da177e4 2357 unsigned int ier;
d8a5a8d7 2358 int locked = 1;
1da177e4 2359
78512ece
AM		 2360 touch_nmi_watchdog();
2361
68aa2c0d
AM		 2362 local_irq_save(flags);
2363 if (up->port.sysrq) {
2364 /* serial8250_handle_port() already took the lock */
2365 locked = 0;
2366 } else if (oops_in_progress) {
2367 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2368 } else
68aa2c0d 2369 spin_lock(&up->port.lock);
d8a5a8d7 2370
1da177e4 2371 /*
dc7bf130 2372 * First save the IER then disable the interrupts
1da177e4
LT		 2373 */
2374 ier = serial_in(up, UART_IER);
2375
2376 if (up->capabilities & UART_CAP_UUE)
2377 serial_out(up, UART_IER, UART_IER_UUE);
2378 else
2379 serial_out(up, UART_IER, 0);
2380
d358788f 2381 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2382
2383 /*
2384 * Finally, wait for transmitter to become empty
2385 * and restore the IER
2386 */
f91a3715 2387 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2388 serial_out(up, UART_IER, ier);
d8a5a8d7
RK		 2389
2390 if (locked)
68aa2c0d
AM		 2391 spin_unlock(&up->port.lock);
2392 local_irq_restore(flags);
1da177e4
LT		 2393}
2394
118c0ace 2395static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2396{
2397 struct uart_port *port;
2398 int baud = 9600;
2399 int bits = 8;
2400 int parity = 'n';
2401 int flow = 'n';
2402
2403 /*
2404 * Check whether an invalid uart number has been specified, and
2405 * if so, search for the first available port that does have
2406 * console support.
2407 */
a61c2d78 2408 if (co->index >= nr_uarts)
1da177e4
LT		 2409 co->index = 0;
2410 port = &serial8250_ports[co->index].port;
2411 if (!port->iobase && !port->membase)
2412 return -ENODEV;
2413
2414 if (options)
2415 uart_parse_options(options, &baud, &parity, &bits, &flow);
2416
2417 return uart_set_options(port, co, baud, parity, bits, flow);
2418}
2419
2420static struct uart_driver serial8250_reg;
2421static struct console serial8250_console = {
2422 .name = "ttyS",
2423 .write = serial8250_console_write,
2424 .device = uart_console_device,
2425 .setup = serial8250_console_setup,
2426 .flags = CON_PRINTBUFFER,
2427 .index = -1,
2428 .data = &serial8250_reg,
2429};
2430
2431static int __init serial8250_console_init(void)
2432{
2433 serial8250_isa_init_ports();
2434 register_console(&serial8250_console);
2435 return 0;
2436}
2437console_initcall(serial8250_console_init);
2438
2439static int __init find_port(struct uart_port *p)
2440{
2441 int line;
2442 struct uart_port *port;
2443
a61c2d78 2444 for (line = 0; line < nr_uarts; line++) {
1da177e4 2445 port = &serial8250_ports[line].port;
50aec3b5 2446 if (uart_match_port(p, port))
1da177e4
LT		 2447 return line;
2448 }
2449 return -ENODEV;
2450}
2451
2452int __init serial8250_start_console(struct uart_port *port, char *options)
2453{
2454 int line;
2455
2456 line = find_port(port);
2457 if (line < 0)
2458 return -ENODEV;
2459
2460 add_preferred_console("ttyS", line, options);
2461 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2462 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2463 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2464 (unsigned long) port->iobase, options);
2465 if (!(serial8250_console.flags & CON_ENABLED)) {
2466 serial8250_console.flags &= ~CON_PRINTBUFFER;
2467 register_console(&serial8250_console);
2468 }
2469 return line;
2470}
2471
2472#define SERIAL8250_CONSOLE &serial8250_console
2473#else
2474#define SERIAL8250_CONSOLE NULL
2475#endif
2476
2477static struct uart_driver serial8250_reg = {
2478 .owner = THIS_MODULE,
2479 .driver_name = "serial",
1da177e4
LT		 2480 .dev_name = "ttyS",
2481 .major = TTY_MAJOR,
2482 .minor = 64,
2483 .nr = UART_NR,
2484 .cons = SERIAL8250_CONSOLE,
2485};
2486
d856c666
RK		 2487/*
2488 * early_serial_setup - early registration for 8250 ports
2489 *
2490 * Setup an 8250 port structure prior to console initialisation. Use
2491 * after console initialisation will cause undefined behaviour.
2492 */
1da177e4
LT		 2493int __init early_serial_setup(struct uart_port *port)
2494{
2495 if (port->line >= ARRAY_SIZE(serial8250_ports))
2496 return -ENODEV;
2497
2498 serial8250_isa_init_ports();
2499 serial8250_ports[port->line].port = *port;
2500 serial8250_ports[port->line].port.ops = &serial8250_pops;
2501 return 0;
2502}
2503
2504/**
2505 * serial8250_suspend_port - suspend one serial port
2506 * @line: serial line number
1da177e4
LT		 2507 *
2508 * Suspend one serial port.
2509 */
2510void serial8250_suspend_port(int line)
2511{
2512 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2513}
2514
2515/**
2516 * serial8250_resume_port - resume one serial port
2517 * @line: serial line number
1da177e4
LT		 2518 *
2519 * Resume one serial port.
2520 */
2521void serial8250_resume_port(int line)
2522{
2523 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2524}
2525
2526/*
2527 * Register a set of serial devices attached to a platform device. The
2528 * list is terminated with a zero flags entry, which means we expect
2529 * all entries to have at least UPF_BOOT_AUTOCONF set.
2530 */
3ae5eaec 2531static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2532{
3ae5eaec 2533 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2534 struct uart_port port;
ec9f47cd 2535 int ret, i;
1da177e4
LT		 2536
2537 memset(&port, 0, sizeof(struct uart_port));
2538
ec9f47cd 2539 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2540 port.iobase = p->iobase;
2541 port.membase = p->membase;
2542 port.irq = p->irq;
2543 port.uartclk = p->uartclk;
2544 port.regshift = p->regshift;
2545 port.iotype = p->iotype;
2546 port.flags = p->flags;
2547 port.mapbase = p->mapbase;
ec9f47cd 2548 port.hub6 = p->hub6;
3ae5eaec 2549 port.dev = &dev->dev;
1da177e4
LT		 2550 if (share_irqs)
2551 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2552 ret = serial8250_register_port(&port);
2553 if (ret < 0) {
3ae5eaec 2554 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2555 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2556 p->iobase, p->mapbase, p->irq, ret);
2557 }
1da177e4
LT		 2558 }
2559 return 0;
2560}
2561
2562/*
2563 * Remove serial ports registered against a platform device.
2564 */
3ae5eaec 2565static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2566{
2567 int i;
2568
a61c2d78 2569 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2570 struct uart_8250_port *up = &serial8250_ports[i];
2571
3ae5eaec 2572 if (up->port.dev == &dev->dev)
1da177e4
LT		 2573 serial8250_unregister_port(i);
2574 }
2575 return 0;
2576}
2577
3ae5eaec 2578static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2579{
2580 int i;
2581
1da177e4
LT		 2582 for (i = 0; i < UART_NR; i++) {
2583 struct uart_8250_port *up = &serial8250_ports[i];
2584
3ae5eaec 2585 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2586 uart_suspend_port(&serial8250_reg, &up->port);
2587 }
2588
2589 return 0;
2590}
2591
3ae5eaec 2592static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2593{
2594 int i;
2595
1da177e4
LT		 2596 for (i = 0; i < UART_NR; i++) {
2597 struct uart_8250_port *up = &serial8250_ports[i];
2598
3ae5eaec 2599 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2600 uart_resume_port(&serial8250_reg, &up->port);
2601 }
2602
2603 return 0;
2604}
2605
3ae5eaec 2606static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2607 .probe = serial8250_probe,
2608 .remove = __devexit_p(serial8250_remove),
2609 .suspend = serial8250_suspend,
2610 .resume = serial8250_resume,
3ae5eaec
RK		 2611 .driver = {
2612 .name = "serial8250",
7493a314 2613 .owner = THIS_MODULE,
3ae5eaec 2614 },
1da177e4
LT		 2615};
2616
2617/*
2618 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2619 * in the table in include/asm/serial.h
2620 */
2621static struct platform_device *serial8250_isa_devs;
2622
2623/*
2624 * serial8250_register_port and serial8250_unregister_port allows for
2625 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2626 * modems and PCI multiport cards.
2627 */
f392ecfa 2628static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2629
2630static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2631{
2632 int i;
2633
2634 /*
2635 * First, find a port entry which matches.
2636 */
a61c2d78 2637 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2638 if (uart_match_port(&serial8250_ports[i].port, port))
2639 return &serial8250_ports[i];
2640
2641 /*
2642 * We didn't find a matching entry, so look for the first
2643 * free entry. We look for one which hasn't been previously
2644 * used (indicated by zero iobase).
2645 */
a61c2d78 2646 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2647 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2648 serial8250_ports[i].port.iobase == 0)
2649 return &serial8250_ports[i];
2650
2651 /*
2652 * That also failed. Last resort is to find any entry which
2653 * doesn't have a real port associated with it.
2654 */
a61c2d78 2655 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2656 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2657 return &serial8250_ports[i];
2658
2659 return NULL;
2660}
2661
2662/**
2663 * serial8250_register_port - register a serial port
2664 * @port: serial port template
2665 *
2666 * Configure the serial port specified by the request. If the
2667 * port exists and is in use, it is hung up and unregistered
2668 * first.
2669 *
2670 * The port is then probed and if necessary the IRQ is autodetected
2671 * If this fails an error is returned.
2672 *
2673 * On success the port is ready to use and the line number is returned.
2674 */
2675int serial8250_register_port(struct uart_port *port)
2676{
2677 struct uart_8250_port *uart;
2678 int ret = -ENOSPC;
2679
2680 if (port->uartclk == 0)
2681 return -EINVAL;
2682
f392ecfa 2683 mutex_lock(&serial_mutex);
1da177e4
LT		 2684
2685 uart = serial8250_find_match_or_unused(port);
2686 if (uart) {
2687 uart_remove_one_port(&serial8250_reg, &uart->port);
2688
2689 uart->port.iobase = port->iobase;
2690 uart->port.membase = port->membase;
2691 uart->port.irq = port->irq;
2692 uart->port.uartclk = port->uartclk;
2693 uart->port.fifosize = port->fifosize;
2694 uart->port.regshift = port->regshift;
2695 uart->port.iotype = port->iotype;
2696 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2697 uart->port.mapbase = port->mapbase;
2698 if (port->dev)
2699 uart->port.dev = port->dev;
2700
2701 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2702 if (ret == 0)
2703 ret = uart->port.line;
2704 }
f392ecfa 2705 mutex_unlock(&serial_mutex);
1da177e4
LT		 2706
2707 return ret;
2708}
2709EXPORT_SYMBOL(serial8250_register_port);
2710
2711/**
2712 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2713 * @line: serial line number
2714 *
2715 * Remove one serial port. This may not be called from interrupt
2716 * context. We hand the port back to the our control.
2717 */
2718void serial8250_unregister_port(int line)
2719{
2720 struct uart_8250_port *uart = &serial8250_ports[line];
2721
f392ecfa 2722 mutex_lock(&serial_mutex);
1da177e4
LT		 2723 uart_remove_one_port(&serial8250_reg, &uart->port);
2724 if (serial8250_isa_devs) {
2725 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2726 uart->port.type = PORT_UNKNOWN;
2727 uart->port.dev = &serial8250_isa_devs->dev;
2728 uart_add_one_port(&serial8250_reg, &uart->port);
2729 } else {
2730 uart->port.dev = NULL;
2731 }
f392ecfa 2732 mutex_unlock(&serial_mutex);
1da177e4
LT		 2733}
2734EXPORT_SYMBOL(serial8250_unregister_port);
2735
2736static int __init serial8250_init(void)
2737{
2738 int ret, i;
2739
a61c2d78
DJ		 2740 if (nr_uarts > UART_NR)
2741 nr_uarts = UART_NR;
2742
1da177e4 2743 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2744 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2745 share_irqs ? "en" : "dis");
2746
2747 for (i = 0; i < NR_IRQS; i++)
2748 spin_lock_init(&irq_lists[i].lock);
2749
2750 ret = uart_register_driver(&serial8250_reg);
2751 if (ret)
2752 goto out;
2753
7493a314
DT		 2754 serial8250_isa_devs = platform_device_alloc("serial8250",
2755 PLAT8250_DEV_LEGACY);
2756 if (!serial8250_isa_devs) {
2757 ret = -ENOMEM;
bc965a7f 2758 goto unreg_uart_drv;
1da177e4
LT		 2759 }
2760
7493a314
DT		 2761 ret = platform_device_add(serial8250_isa_devs);
2762 if (ret)
2763 goto put_dev;
2764
1da177e4
LT		 2765 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2766
bc965a7f
RK		 2767 ret = platform_driver_register(&serial8250_isa_driver);
2768 if (ret == 0)
2769 goto out;
1da177e4 2770
bc965a7f 2771 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2772 put_dev:
2773 platform_device_put(serial8250_isa_devs);
7493a314 2774 unreg_uart_drv:
1da177e4
LT		 2775 uart_unregister_driver(&serial8250_reg);
2776 out:
2777 return ret;
2778}
2779
2780static void __exit serial8250_exit(void)
2781{
2782 struct platform_device *isa_dev = serial8250_isa_devs;
2783
2784 /*
2785 * This tells serial8250_unregister_port() not to re-register
2786 * the ports (thereby making serial8250_isa_driver permanently
2787 * in use.)
2788 */
2789 serial8250_isa_devs = NULL;
2790
3ae5eaec 2791 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2792 platform_device_unregister(isa_dev);
2793
2794 uart_unregister_driver(&serial8250_reg);
2795}
2796
2797module_init(serial8250_init);
2798module_exit(serial8250_exit);
2799
2800EXPORT_SYMBOL(serial8250_suspend_port);
2801EXPORT_SYMBOL(serial8250_resume_port);
2802
2803MODULE_LICENSE("GPL");
2804MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2805
2806module_param(share_irqs, uint, 0644);
2807MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2808 " (unsafe)");
2809
a61c2d78
DJ		 2810module_param(nr_uarts, uint, 0644);
2811MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2812
1da177e4
LT		 2813#ifdef CONFIG_SERIAL_8250_RSA
2814module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2815MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2816#endif
2817MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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