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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/8250.c | |
3 | * | |
4 | * Driver for 8250/16550-type serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright (C) 2001 Russell King. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
1da177e4 LT |
15 | * A note about mapbase / membase |
16 | * | |
17 | * mapbase is the physical address of the IO port. | |
18 | * membase is an 'ioremapped' cookie. | |
19 | */ | |
1da177e4 LT |
20 | |
21 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
22 | #define SUPPORT_SYSRQ | |
23 | #endif | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/console.h> | |
30 | #include <linux/sysrq.h> | |
1da177e4 | 31 | #include <linux/delay.h> |
d052d1be | 32 | #include <linux/platform_device.h> |
1da177e4 LT |
33 | #include <linux/tty.h> |
34 | #include <linux/tty_flip.h> | |
35 | #include <linux/serial_reg.h> | |
36 | #include <linux/serial_core.h> | |
37 | #include <linux/serial.h> | |
38 | #include <linux/serial_8250.h> | |
78512ece | 39 | #include <linux/nmi.h> |
f392ecfa | 40 | #include <linux/mutex.h> |
1da177e4 LT |
41 | |
42 | #include <asm/io.h> | |
43 | #include <asm/irq.h> | |
44 | ||
45 | #include "8250.h" | |
46 | ||
b70ac771 DM |
47 | #ifdef CONFIG_SPARC |
48 | #include "suncore.h" | |
49 | #endif | |
50 | ||
1da177e4 LT |
51 | /* |
52 | * Configuration: | |
40663cc7 | 53 | * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option |
1da177e4 LT |
54 | * is unsafe when used on edge-triggered interrupts. |
55 | */ | |
408b664a | 56 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
1da177e4 | 57 | |
a61c2d78 DJ |
58 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; |
59 | ||
8440838b DM |
60 | static struct uart_driver serial8250_reg; |
61 | ||
62 | static int serial_index(struct uart_port *port) | |
63 | { | |
64 | return (serial8250_reg.minor - 64) + port->line; | |
65 | } | |
66 | ||
d41a4b51 CE |
67 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ |
68 | ||
1da177e4 LT |
69 | /* |
70 | * Debugging. | |
71 | */ | |
72 | #if 0 | |
73 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
74 | #else | |
75 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
76 | #endif | |
77 | ||
78 | #if 0 | |
79 | #define DEBUG_INTR(fmt...) printk(fmt) | |
80 | #else | |
81 | #define DEBUG_INTR(fmt...) do { } while (0) | |
82 | #endif | |
83 | ||
84 | #define PASS_LIMIT 256 | |
85 | ||
bca47613 DH |
86 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
87 | ||
88 | ||
1da177e4 LT |
89 | /* |
90 | * We default to IRQ0 for the "no irq" hack. Some | |
91 | * machine types want others as well - they're free | |
92 | * to redefine this in their header file. | |
93 | */ | |
94 | #define is_real_interrupt(irq) ((irq) != 0) | |
95 | ||
1da177e4 LT |
96 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
97 | #define CONFIG_SERIAL_DETECT_IRQ 1 | |
98 | #endif | |
1da177e4 LT |
99 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
100 | #define CONFIG_SERIAL_MANY_PORTS 1 | |
101 | #endif | |
102 | ||
103 | /* | |
104 | * HUB6 is always on. This will be removed once the header | |
105 | * files have been cleaned. | |
106 | */ | |
107 | #define CONFIG_HUB6 1 | |
108 | ||
a4ed1e41 | 109 | #include <asm/serial.h> |
1da177e4 LT |
110 | /* |
111 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
112 | * standard enumeration mechanism. Platforms that can find all | |
113 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
114 | */ | |
115 | #ifndef SERIAL_PORT_DFNS | |
116 | #define SERIAL_PORT_DFNS | |
117 | #endif | |
118 | ||
cb3592be | 119 | static const struct old_serial_port old_serial_port[] = { |
1da177e4 LT |
120 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ |
121 | }; | |
122 | ||
026d02a2 | 123 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
1da177e4 LT |
124 | |
125 | #ifdef CONFIG_SERIAL_8250_RSA | |
126 | ||
127 | #define PORT_RSA_MAX 4 | |
128 | static unsigned long probe_rsa[PORT_RSA_MAX]; | |
129 | static unsigned int probe_rsa_count; | |
130 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
131 | ||
132 | struct uart_8250_port { | |
133 | struct uart_port port; | |
134 | struct timer_list timer; /* "no irq" timer */ | |
135 | struct list_head list; /* ports on this IRQ */ | |
4ba5e35d RK |
136 | unsigned short capabilities; /* port capabilities */ |
137 | unsigned short bugs; /* port bugs */ | |
1da177e4 | 138 | unsigned int tx_loadsz; /* transmit fifo load size */ |
1da177e4 LT |
139 | unsigned char acr; |
140 | unsigned char ier; | |
141 | unsigned char lcr; | |
142 | unsigned char mcr; | |
143 | unsigned char mcr_mask; /* mask of user bits */ | |
144 | unsigned char mcr_force; /* mask of forced bits */ | |
b8e7e40a | 145 | unsigned char cur_iotype; /* Running I/O type */ |
ad4c2aa6 CM |
146 | |
147 | /* | |
148 | * Some bits in registers are cleared on a read, so they must | |
149 | * be saved whenever the register is read but the bits will not | |
150 | * be immediately processed. | |
151 | */ | |
152 | #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS | |
153 | unsigned char lsr_saved_flags; | |
154 | #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA | |
155 | unsigned char msr_saved_flags; | |
1da177e4 LT |
156 | |
157 | /* | |
158 | * We provide a per-port pm hook. | |
159 | */ | |
160 | void (*pm)(struct uart_port *port, | |
161 | unsigned int state, unsigned int old); | |
162 | }; | |
163 | ||
164 | struct irq_info { | |
25db8ad5 AC |
165 | struct hlist_node node; |
166 | int irq; | |
167 | spinlock_t lock; /* Protects list not the hash */ | |
1da177e4 LT |
168 | struct list_head *head; |
169 | }; | |
170 | ||
25db8ad5 AC |
171 | #define NR_IRQ_HASH 32 /* Can be adjusted later */ |
172 | static struct hlist_head irq_lists[NR_IRQ_HASH]; | |
173 | static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ | |
1da177e4 LT |
174 | |
175 | /* | |
176 | * Here we define the default xmit fifo size used for each type of UART. | |
177 | */ | |
178 | static const struct serial8250_config uart_config[] = { | |
179 | [PORT_UNKNOWN] = { | |
180 | .name = "unknown", | |
181 | .fifo_size = 1, | |
182 | .tx_loadsz = 1, | |
183 | }, | |
184 | [PORT_8250] = { | |
185 | .name = "8250", | |
186 | .fifo_size = 1, | |
187 | .tx_loadsz = 1, | |
188 | }, | |
189 | [PORT_16450] = { | |
190 | .name = "16450", | |
191 | .fifo_size = 1, | |
192 | .tx_loadsz = 1, | |
193 | }, | |
194 | [PORT_16550] = { | |
195 | .name = "16550", | |
196 | .fifo_size = 1, | |
197 | .tx_loadsz = 1, | |
198 | }, | |
199 | [PORT_16550A] = { | |
200 | .name = "16550A", | |
201 | .fifo_size = 16, | |
202 | .tx_loadsz = 16, | |
203 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
204 | .flags = UART_CAP_FIFO, | |
205 | }, | |
206 | [PORT_CIRRUS] = { | |
207 | .name = "Cirrus", | |
208 | .fifo_size = 1, | |
209 | .tx_loadsz = 1, | |
210 | }, | |
211 | [PORT_16650] = { | |
212 | .name = "ST16650", | |
213 | .fifo_size = 1, | |
214 | .tx_loadsz = 1, | |
215 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
216 | }, | |
217 | [PORT_16650V2] = { | |
218 | .name = "ST16650V2", | |
219 | .fifo_size = 32, | |
220 | .tx_loadsz = 16, | |
221 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
222 | UART_FCR_T_TRIG_00, | |
223 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
224 | }, | |
225 | [PORT_16750] = { | |
226 | .name = "TI16750", | |
227 | .fifo_size = 64, | |
228 | .tx_loadsz = 64, | |
229 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
230 | UART_FCR7_64BYTE, | |
231 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, | |
232 | }, | |
233 | [PORT_STARTECH] = { | |
234 | .name = "Startech", | |
235 | .fifo_size = 1, | |
236 | .tx_loadsz = 1, | |
237 | }, | |
238 | [PORT_16C950] = { | |
239 | .name = "16C950/954", | |
240 | .fifo_size = 128, | |
241 | .tx_loadsz = 128, | |
242 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
243 | .flags = UART_CAP_FIFO, | |
244 | }, | |
245 | [PORT_16654] = { | |
246 | .name = "ST16654", | |
247 | .fifo_size = 64, | |
248 | .tx_loadsz = 32, | |
249 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
250 | UART_FCR_T_TRIG_10, | |
251 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
252 | }, | |
253 | [PORT_16850] = { | |
254 | .name = "XR16850", | |
255 | .fifo_size = 128, | |
256 | .tx_loadsz = 128, | |
257 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
258 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
259 | }, | |
260 | [PORT_RSA] = { | |
261 | .name = "RSA", | |
262 | .fifo_size = 2048, | |
263 | .tx_loadsz = 2048, | |
264 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |
265 | .flags = UART_CAP_FIFO, | |
266 | }, | |
267 | [PORT_NS16550A] = { | |
268 | .name = "NS16550A", | |
269 | .fifo_size = 16, | |
270 | .tx_loadsz = 16, | |
271 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
272 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |
273 | }, | |
274 | [PORT_XSCALE] = { | |
275 | .name = "XScale", | |
276 | .fifo_size = 32, | |
277 | .tx_loadsz = 32, | |
278 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
279 | .flags = UART_CAP_FIFO | UART_CAP_UUE, | |
280 | }, | |
bd71c182 TK |
281 | [PORT_RM9000] = { |
282 | .name = "RM9000", | |
283 | .fifo_size = 16, | |
284 | .tx_loadsz = 16, | |
285 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
6b06f191 DD |
286 | .flags = UART_CAP_FIFO, |
287 | }, | |
288 | [PORT_OCTEON] = { | |
289 | .name = "OCTEON", | |
290 | .fifo_size = 64, | |
291 | .tx_loadsz = 64, | |
292 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
bd71c182 TK |
293 | .flags = UART_CAP_FIFO, |
294 | }, | |
08e0992f FF |
295 | [PORT_AR7] = { |
296 | .name = "AR7", | |
297 | .fifo_size = 16, | |
298 | .tx_loadsz = 16, | |
299 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, | |
300 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
301 | }, | |
1da177e4 LT |
302 | }; |
303 | ||
bd71c182 | 304 | #if defined (CONFIG_SERIAL_8250_AU1X00) |
21c614a7 PA |
305 | |
306 | /* Au1x00 UART hardware has a weird register layout */ | |
307 | static const u8 au_io_in_map[] = { | |
308 | [UART_RX] = 0, | |
309 | [UART_IER] = 2, | |
310 | [UART_IIR] = 3, | |
311 | [UART_LCR] = 5, | |
312 | [UART_MCR] = 6, | |
313 | [UART_LSR] = 7, | |
314 | [UART_MSR] = 8, | |
315 | }; | |
316 | ||
317 | static const u8 au_io_out_map[] = { | |
318 | [UART_TX] = 1, | |
319 | [UART_IER] = 2, | |
320 | [UART_FCR] = 4, | |
321 | [UART_LCR] = 5, | |
322 | [UART_MCR] = 6, | |
323 | }; | |
324 | ||
325 | /* sane hardware needs no mapping */ | |
7d6a07d1 | 326 | static inline int map_8250_in_reg(struct uart_port *p, int offset) |
21c614a7 | 327 | { |
7d6a07d1 | 328 | if (p->iotype != UPIO_AU) |
21c614a7 PA |
329 | return offset; |
330 | return au_io_in_map[offset]; | |
331 | } | |
332 | ||
7d6a07d1 | 333 | static inline int map_8250_out_reg(struct uart_port *p, int offset) |
21c614a7 | 334 | { |
7d6a07d1 | 335 | if (p->iotype != UPIO_AU) |
21c614a7 PA |
336 | return offset; |
337 | return au_io_out_map[offset]; | |
338 | } | |
339 | ||
6f803cd0 | 340 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
bd71c182 TK |
341 | |
342 | static const u8 | |
343 | regmap_in[8] = { | |
344 | [UART_RX] = 0x00, | |
345 | [UART_IER] = 0x0c, | |
346 | [UART_IIR] = 0x14, | |
347 | [UART_LCR] = 0x1c, | |
348 | [UART_MCR] = 0x20, | |
349 | [UART_LSR] = 0x24, | |
350 | [UART_MSR] = 0x28, | |
351 | [UART_SCR] = 0x2c | |
352 | }, | |
353 | regmap_out[8] = { | |
354 | [UART_TX] = 0x04, | |
355 | [UART_IER] = 0x0c, | |
356 | [UART_FCR] = 0x18, | |
357 | [UART_LCR] = 0x1c, | |
358 | [UART_MCR] = 0x20, | |
359 | [UART_LSR] = 0x24, | |
360 | [UART_MSR] = 0x28, | |
361 | [UART_SCR] = 0x2c | |
362 | }; | |
363 | ||
7d6a07d1 | 364 | static inline int map_8250_in_reg(struct uart_port *p, int offset) |
bd71c182 | 365 | { |
7d6a07d1 | 366 | if (p->iotype != UPIO_RM9000) |
bd71c182 TK |
367 | return offset; |
368 | return regmap_in[offset]; | |
369 | } | |
370 | ||
7d6a07d1 | 371 | static inline int map_8250_out_reg(struct uart_port *p, int offset) |
bd71c182 | 372 | { |
7d6a07d1 | 373 | if (p->iotype != UPIO_RM9000) |
bd71c182 TK |
374 | return offset; |
375 | return regmap_out[offset]; | |
376 | } | |
377 | ||
21c614a7 PA |
378 | #else |
379 | ||
380 | /* sane hardware needs no mapping */ | |
381 | #define map_8250_in_reg(up, offset) (offset) | |
382 | #define map_8250_out_reg(up, offset) (offset) | |
383 | ||
384 | #endif | |
385 | ||
7d6a07d1 | 386 | static unsigned int hub6_serial_in(struct uart_port *p, int offset) |
1da177e4 | 387 | { |
7d6a07d1 DD |
388 | offset = map_8250_in_reg(p, offset) << p->regshift; |
389 | outb(p->hub6 - 1 + offset, p->iobase); | |
390 | return inb(p->iobase + 1); | |
391 | } | |
1da177e4 | 392 | |
7d6a07d1 DD |
393 | static void hub6_serial_out(struct uart_port *p, int offset, int value) |
394 | { | |
395 | offset = map_8250_out_reg(p, offset) << p->regshift; | |
396 | outb(p->hub6 - 1 + offset, p->iobase); | |
397 | outb(value, p->iobase + 1); | |
398 | } | |
1da177e4 | 399 | |
7d6a07d1 DD |
400 | static unsigned int mem_serial_in(struct uart_port *p, int offset) |
401 | { | |
402 | offset = map_8250_in_reg(p, offset) << p->regshift; | |
403 | return readb(p->membase + offset); | |
404 | } | |
1da177e4 | 405 | |
7d6a07d1 DD |
406 | static void mem_serial_out(struct uart_port *p, int offset, int value) |
407 | { | |
408 | offset = map_8250_out_reg(p, offset) << p->regshift; | |
409 | writeb(value, p->membase + offset); | |
410 | } | |
411 | ||
412 | static void mem32_serial_out(struct uart_port *p, int offset, int value) | |
413 | { | |
414 | offset = map_8250_out_reg(p, offset) << p->regshift; | |
415 | writel(value, p->membase + offset); | |
416 | } | |
417 | ||
418 | static unsigned int mem32_serial_in(struct uart_port *p, int offset) | |
419 | { | |
420 | offset = map_8250_in_reg(p, offset) << p->regshift; | |
421 | return readl(p->membase + offset); | |
422 | } | |
1da177e4 | 423 | |
21c614a7 | 424 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
7d6a07d1 DD |
425 | static unsigned int au_serial_in(struct uart_port *p, int offset) |
426 | { | |
427 | offset = map_8250_in_reg(p, offset) << p->regshift; | |
428 | return __raw_readl(p->membase + offset); | |
429 | } | |
430 | ||
431 | static void au_serial_out(struct uart_port *p, int offset, int value) | |
432 | { | |
433 | offset = map_8250_out_reg(p, offset) << p->regshift; | |
434 | __raw_writel(value, p->membase + offset); | |
435 | } | |
21c614a7 PA |
436 | #endif |
437 | ||
7d6a07d1 DD |
438 | static unsigned int tsi_serial_in(struct uart_port *p, int offset) |
439 | { | |
440 | unsigned int tmp; | |
441 | offset = map_8250_in_reg(p, offset) << p->regshift; | |
442 | if (offset == UART_IIR) { | |
443 | tmp = readl(p->membase + (UART_IIR & ~3)); | |
444 | return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */ | |
445 | } else | |
446 | return readb(p->membase + offset); | |
447 | } | |
3be91ec7 | 448 | |
7d6a07d1 DD |
449 | static void tsi_serial_out(struct uart_port *p, int offset, int value) |
450 | { | |
451 | offset = map_8250_out_reg(p, offset) << p->regshift; | |
452 | if (!((offset == UART_IER) && (value & UART_IER_UUE))) | |
453 | writeb(value, p->membase + offset); | |
1da177e4 LT |
454 | } |
455 | ||
7d6a07d1 | 456 | static void dwapb_serial_out(struct uart_port *p, int offset, int value) |
1da177e4 | 457 | { |
beab697a | 458 | int save_offset = offset; |
7d6a07d1 DD |
459 | offset = map_8250_out_reg(p, offset) << p->regshift; |
460 | /* Save the LCR value so it can be re-written when a | |
461 | * Busy Detect interrupt occurs. */ | |
462 | if (save_offset == UART_LCR) { | |
463 | struct uart_8250_port *up = (struct uart_8250_port *)p; | |
464 | up->lcr = value; | |
465 | } | |
466 | writeb(value, p->membase + offset); | |
467 | /* Read the IER to ensure any interrupt is cleared before | |
468 | * returning from ISR. */ | |
469 | if (save_offset == UART_TX || save_offset == UART_IER) | |
470 | value = p->serial_in(p, UART_IER); | |
471 | } | |
1da177e4 | 472 | |
7d6a07d1 DD |
473 | static unsigned int io_serial_in(struct uart_port *p, int offset) |
474 | { | |
475 | offset = map_8250_in_reg(p, offset) << p->regshift; | |
476 | return inb(p->iobase + offset); | |
477 | } | |
478 | ||
479 | static void io_serial_out(struct uart_port *p, int offset, int value) | |
480 | { | |
481 | offset = map_8250_out_reg(p, offset) << p->regshift; | |
482 | outb(value, p->iobase + offset); | |
483 | } | |
484 | ||
485 | static void set_io_from_upio(struct uart_port *p) | |
486 | { | |
b8e7e40a | 487 | struct uart_8250_port *up = (struct uart_8250_port *)p; |
7d6a07d1 | 488 | switch (p->iotype) { |
1da177e4 | 489 | case UPIO_HUB6: |
7d6a07d1 DD |
490 | p->serial_in = hub6_serial_in; |
491 | p->serial_out = hub6_serial_out; | |
1da177e4 LT |
492 | break; |
493 | ||
494 | case UPIO_MEM: | |
7d6a07d1 DD |
495 | p->serial_in = mem_serial_in; |
496 | p->serial_out = mem_serial_out; | |
1da177e4 LT |
497 | break; |
498 | ||
bd71c182 | 499 | case UPIO_RM9000: |
1da177e4 | 500 | case UPIO_MEM32: |
7d6a07d1 DD |
501 | p->serial_in = mem32_serial_in; |
502 | p->serial_out = mem32_serial_out; | |
1da177e4 LT |
503 | break; |
504 | ||
21c614a7 PA |
505 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
506 | case UPIO_AU: | |
7d6a07d1 DD |
507 | p->serial_in = au_serial_in; |
508 | p->serial_out = au_serial_out; | |
21c614a7 PA |
509 | break; |
510 | #endif | |
3be91ec7 | 511 | case UPIO_TSI: |
7d6a07d1 DD |
512 | p->serial_in = tsi_serial_in; |
513 | p->serial_out = tsi_serial_out; | |
3be91ec7 | 514 | break; |
21c614a7 | 515 | |
beab697a | 516 | case UPIO_DWAPB: |
7d6a07d1 DD |
517 | p->serial_in = mem_serial_in; |
518 | p->serial_out = dwapb_serial_out; | |
beab697a MSJ |
519 | break; |
520 | ||
1da177e4 | 521 | default: |
7d6a07d1 DD |
522 | p->serial_in = io_serial_in; |
523 | p->serial_out = io_serial_out; | |
524 | break; | |
1da177e4 | 525 | } |
b8e7e40a AC |
526 | /* Remember loaded iotype */ |
527 | up->cur_iotype = p->iotype; | |
1da177e4 LT |
528 | } |
529 | ||
40b36daa AW |
530 | static void |
531 | serial_out_sync(struct uart_8250_port *up, int offset, int value) | |
532 | { | |
7d6a07d1 DD |
533 | struct uart_port *p = &up->port; |
534 | switch (p->iotype) { | |
40b36daa AW |
535 | case UPIO_MEM: |
536 | case UPIO_MEM32: | |
537 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |
538 | case UPIO_AU: | |
539 | #endif | |
beab697a | 540 | case UPIO_DWAPB: |
7d6a07d1 DD |
541 | p->serial_out(p, offset, value); |
542 | p->serial_in(p, UART_LCR); /* safe, no side-effects */ | |
40b36daa AW |
543 | break; |
544 | default: | |
7d6a07d1 | 545 | p->serial_out(p, offset, value); |
40b36daa AW |
546 | } |
547 | } | |
548 | ||
7d6a07d1 DD |
549 | #define serial_in(up, offset) \ |
550 | (up->port.serial_in(&(up)->port, (offset))) | |
551 | #define serial_out(up, offset, value) \ | |
552 | (up->port.serial_out(&(up)->port, (offset), (value))) | |
1da177e4 LT |
553 | /* |
554 | * We used to support using pause I/O for certain machines. We | |
555 | * haven't supported this for a while, but just in case it's badly | |
556 | * needed for certain old 386 machines, I've left these #define's | |
557 | * in.... | |
558 | */ | |
559 | #define serial_inp(up, offset) serial_in(up, offset) | |
560 | #define serial_outp(up, offset, value) serial_out(up, offset, value) | |
561 | ||
b32b19b8 JAH |
562 | /* Uart divisor latch read */ |
563 | static inline int _serial_dl_read(struct uart_8250_port *up) | |
564 | { | |
565 | return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; | |
566 | } | |
567 | ||
568 | /* Uart divisor latch write */ | |
569 | static inline void _serial_dl_write(struct uart_8250_port *up, int value) | |
570 | { | |
571 | serial_outp(up, UART_DLL, value & 0xff); | |
572 | serial_outp(up, UART_DLM, value >> 8 & 0xff); | |
573 | } | |
574 | ||
6f803cd0 | 575 | #if defined(CONFIG_SERIAL_8250_AU1X00) |
b32b19b8 JAH |
576 | /* Au1x00 haven't got a standard divisor latch */ |
577 | static int serial_dl_read(struct uart_8250_port *up) | |
578 | { | |
579 | if (up->port.iotype == UPIO_AU) | |
580 | return __raw_readl(up->port.membase + 0x28); | |
581 | else | |
582 | return _serial_dl_read(up); | |
583 | } | |
584 | ||
585 | static void serial_dl_write(struct uart_8250_port *up, int value) | |
586 | { | |
587 | if (up->port.iotype == UPIO_AU) | |
588 | __raw_writel(value, up->port.membase + 0x28); | |
589 | else | |
590 | _serial_dl_write(up, value); | |
591 | } | |
6f803cd0 | 592 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
bd71c182 TK |
593 | static int serial_dl_read(struct uart_8250_port *up) |
594 | { | |
595 | return (up->port.iotype == UPIO_RM9000) ? | |
596 | (((__raw_readl(up->port.membase + 0x10) << 8) | | |
597 | (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) : | |
598 | _serial_dl_read(up); | |
599 | } | |
600 | ||
601 | static void serial_dl_write(struct uart_8250_port *up, int value) | |
602 | { | |
603 | if (up->port.iotype == UPIO_RM9000) { | |
604 | __raw_writel(value, up->port.membase + 0x08); | |
605 | __raw_writel(value >> 8, up->port.membase + 0x10); | |
606 | } else { | |
607 | _serial_dl_write(up, value); | |
608 | } | |
609 | } | |
b32b19b8 JAH |
610 | #else |
611 | #define serial_dl_read(up) _serial_dl_read(up) | |
612 | #define serial_dl_write(up, value) _serial_dl_write(up, value) | |
613 | #endif | |
1da177e4 LT |
614 | |
615 | /* | |
616 | * For the 16C950 | |
617 | */ | |
618 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) | |
619 | { | |
620 | serial_out(up, UART_SCR, offset); | |
621 | serial_out(up, UART_ICR, value); | |
622 | } | |
623 | ||
624 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) | |
625 | { | |
626 | unsigned int value; | |
627 | ||
628 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
629 | serial_out(up, UART_SCR, offset); | |
630 | value = serial_in(up, UART_ICR); | |
631 | serial_icr_write(up, UART_ACR, up->acr); | |
632 | ||
633 | return value; | |
634 | } | |
635 | ||
636 | /* | |
637 | * FIFO support. | |
638 | */ | |
b5d674ab | 639 | static void serial8250_clear_fifos(struct uart_8250_port *p) |
1da177e4 LT |
640 | { |
641 | if (p->capabilities & UART_CAP_FIFO) { | |
642 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); | |
643 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |
644 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
645 | serial_outp(p, UART_FCR, 0); | |
646 | } | |
647 | } | |
648 | ||
649 | /* | |
650 | * IER sleep support. UARTs which have EFRs need the "extended | |
651 | * capability" bit enabled. Note that on XR16C850s, we need to | |
652 | * reset LCR to write to IER. | |
653 | */ | |
b5d674ab | 654 | static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) |
1da177e4 LT |
655 | { |
656 | if (p->capabilities & UART_CAP_SLEEP) { | |
657 | if (p->capabilities & UART_CAP_EFR) { | |
658 | serial_outp(p, UART_LCR, 0xBF); | |
659 | serial_outp(p, UART_EFR, UART_EFR_ECB); | |
660 | serial_outp(p, UART_LCR, 0); | |
661 | } | |
662 | serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); | |
663 | if (p->capabilities & UART_CAP_EFR) { | |
664 | serial_outp(p, UART_LCR, 0xBF); | |
665 | serial_outp(p, UART_EFR, 0); | |
666 | serial_outp(p, UART_LCR, 0); | |
667 | } | |
668 | } | |
669 | } | |
670 | ||
671 | #ifdef CONFIG_SERIAL_8250_RSA | |
672 | /* | |
673 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
674 | * We set the port uart clock rate if we succeed. | |
675 | */ | |
676 | static int __enable_rsa(struct uart_8250_port *up) | |
677 | { | |
678 | unsigned char mode; | |
679 | int result; | |
680 | ||
681 | mode = serial_inp(up, UART_RSA_MSR); | |
682 | result = mode & UART_RSA_MSR_FIFO; | |
683 | ||
684 | if (!result) { | |
685 | serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); | |
686 | mode = serial_inp(up, UART_RSA_MSR); | |
687 | result = mode & UART_RSA_MSR_FIFO; | |
688 | } | |
689 | ||
690 | if (result) | |
691 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
692 | ||
693 | return result; | |
694 | } | |
695 | ||
696 | static void enable_rsa(struct uart_8250_port *up) | |
697 | { | |
698 | if (up->port.type == PORT_RSA) { | |
699 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
700 | spin_lock_irq(&up->port.lock); | |
701 | __enable_rsa(up); | |
702 | spin_unlock_irq(&up->port.lock); | |
703 | } | |
704 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
705 | serial_outp(up, UART_RSA_FRR, 0); | |
706 | } | |
707 | } | |
708 | ||
709 | /* | |
710 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
711 | * It is unknown why interrupts were disabled in here. However, | |
712 | * the caller is expected to preserve this behaviour by grabbing | |
713 | * the spinlock before calling this function. | |
714 | */ | |
715 | static void disable_rsa(struct uart_8250_port *up) | |
716 | { | |
717 | unsigned char mode; | |
718 | int result; | |
719 | ||
720 | if (up->port.type == PORT_RSA && | |
721 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
722 | spin_lock_irq(&up->port.lock); | |
723 | ||
724 | mode = serial_inp(up, UART_RSA_MSR); | |
725 | result = !(mode & UART_RSA_MSR_FIFO); | |
726 | ||
727 | if (!result) { | |
728 | serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); | |
729 | mode = serial_inp(up, UART_RSA_MSR); | |
730 | result = !(mode & UART_RSA_MSR_FIFO); | |
731 | } | |
732 | ||
733 | if (result) | |
734 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
735 | spin_unlock_irq(&up->port.lock); | |
736 | } | |
737 | } | |
738 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
739 | ||
740 | /* | |
741 | * This is a quickie test to see how big the FIFO is. | |
742 | * It doesn't work at all the time, more's the pity. | |
743 | */ | |
744 | static int size_fifo(struct uart_8250_port *up) | |
745 | { | |
b32b19b8 JAH |
746 | unsigned char old_fcr, old_mcr, old_lcr; |
747 | unsigned short old_dl; | |
1da177e4 LT |
748 | int count; |
749 | ||
750 | old_lcr = serial_inp(up, UART_LCR); | |
751 | serial_outp(up, UART_LCR, 0); | |
752 | old_fcr = serial_inp(up, UART_FCR); | |
753 | old_mcr = serial_inp(up, UART_MCR); | |
754 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
755 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
756 | serial_outp(up, UART_MCR, UART_MCR_LOOP); | |
757 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
b32b19b8 JAH |
758 | old_dl = serial_dl_read(up); |
759 | serial_dl_write(up, 0x0001); | |
1da177e4 LT |
760 | serial_outp(up, UART_LCR, 0x03); |
761 | for (count = 0; count < 256; count++) | |
762 | serial_outp(up, UART_TX, count); | |
763 | mdelay(20);/* FIXME - schedule_timeout */ | |
764 | for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && | |
765 | (count < 256); count++) | |
766 | serial_inp(up, UART_RX); | |
767 | serial_outp(up, UART_FCR, old_fcr); | |
768 | serial_outp(up, UART_MCR, old_mcr); | |
769 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
b32b19b8 | 770 | serial_dl_write(up, old_dl); |
1da177e4 LT |
771 | serial_outp(up, UART_LCR, old_lcr); |
772 | ||
773 | return count; | |
774 | } | |
775 | ||
776 | /* | |
777 | * Read UART ID using the divisor method - set DLL and DLM to zero | |
778 | * and the revision will be in DLL and device type in DLM. We | |
779 | * preserve the device state across this. | |
780 | */ | |
781 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) | |
782 | { | |
783 | unsigned char old_dll, old_dlm, old_lcr; | |
784 | unsigned int id; | |
785 | ||
786 | old_lcr = serial_inp(p, UART_LCR); | |
787 | serial_outp(p, UART_LCR, UART_LCR_DLAB); | |
788 | ||
789 | old_dll = serial_inp(p, UART_DLL); | |
790 | old_dlm = serial_inp(p, UART_DLM); | |
791 | ||
792 | serial_outp(p, UART_DLL, 0); | |
793 | serial_outp(p, UART_DLM, 0); | |
794 | ||
795 | id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; | |
796 | ||
797 | serial_outp(p, UART_DLL, old_dll); | |
798 | serial_outp(p, UART_DLM, old_dlm); | |
799 | serial_outp(p, UART_LCR, old_lcr); | |
800 | ||
801 | return id; | |
802 | } | |
803 | ||
804 | /* | |
805 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |
806 | * When this function is called we know it is at least a StarTech | |
807 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |
808 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |
809 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |
810 | * existence.) | |
bd71c182 | 811 | * |
1da177e4 LT |
812 | * What evil have men's minds wrought... |
813 | */ | |
814 | static void autoconfig_has_efr(struct uart_8250_port *up) | |
815 | { | |
816 | unsigned int id1, id2, id3, rev; | |
817 | ||
818 | /* | |
819 | * Everything with an EFR has SLEEP | |
820 | */ | |
821 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
822 | ||
823 | /* | |
824 | * First we check to see if it's an Oxford Semiconductor UART. | |
825 | * | |
826 | * If we have to do this here because some non-National | |
827 | * Semiconductor clone chips lock up if you try writing to the | |
828 | * LSR register (which serial_icr_read does) | |
829 | */ | |
830 | ||
831 | /* | |
832 | * Check for Oxford Semiconductor 16C950. | |
833 | * | |
834 | * EFR [4] must be set else this test fails. | |
835 | * | |
836 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |
837 | * claims that it's needed for 952 dual UART's (which are not | |
838 | * recommended for new designs). | |
839 | */ | |
840 | up->acr = 0; | |
841 | serial_out(up, UART_LCR, 0xBF); | |
842 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
843 | serial_out(up, UART_LCR, 0x00); | |
844 | id1 = serial_icr_read(up, UART_ID1); | |
845 | id2 = serial_icr_read(up, UART_ID2); | |
846 | id3 = serial_icr_read(up, UART_ID3); | |
847 | rev = serial_icr_read(up, UART_REV); | |
848 | ||
849 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); | |
850 | ||
851 | if (id1 == 0x16 && id2 == 0xC9 && | |
852 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { | |
853 | up->port.type = PORT_16C950; | |
4ba5e35d RK |
854 | |
855 | /* | |
856 | * Enable work around for the Oxford Semiconductor 952 rev B | |
857 | * chip which causes it to seriously miscalculate baud rates | |
858 | * when DLL is 0. | |
859 | */ | |
860 | if (id3 == 0x52 && rev == 0x01) | |
861 | up->bugs |= UART_BUG_QUOT; | |
1da177e4 LT |
862 | return; |
863 | } | |
bd71c182 | 864 | |
1da177e4 LT |
865 | /* |
866 | * We check for a XR16C850 by setting DLL and DLM to 0, and then | |
867 | * reading back DLL and DLM. The chip type depends on the DLM | |
868 | * value read back: | |
869 | * 0x10 - XR16C850 and the DLL contains the chip revision. | |
870 | * 0x12 - XR16C2850. | |
871 | * 0x14 - XR16C854. | |
872 | */ | |
873 | id1 = autoconfig_read_divisor_id(up); | |
874 | DEBUG_AUTOCONF("850id=%04x ", id1); | |
875 | ||
876 | id2 = id1 >> 8; | |
877 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { | |
1da177e4 LT |
878 | up->port.type = PORT_16850; |
879 | return; | |
880 | } | |
881 | ||
882 | /* | |
883 | * It wasn't an XR16C850. | |
884 | * | |
885 | * We distinguish between the '654 and the '650 by counting | |
886 | * how many bytes are in the FIFO. I'm using this for now, | |
887 | * since that's the technique that was sent to me in the | |
888 | * serial driver update, but I'm not convinced this works. | |
889 | * I've had problems doing this in the past. -TYT | |
890 | */ | |
891 | if (size_fifo(up) == 64) | |
892 | up->port.type = PORT_16654; | |
893 | else | |
894 | up->port.type = PORT_16650V2; | |
895 | } | |
896 | ||
897 | /* | |
898 | * We detected a chip without a FIFO. Only two fall into | |
899 | * this category - the original 8250 and the 16450. The | |
900 | * 16450 has a scratch register (accessible with LCR=0) | |
901 | */ | |
902 | static void autoconfig_8250(struct uart_8250_port *up) | |
903 | { | |
904 | unsigned char scratch, status1, status2; | |
905 | ||
906 | up->port.type = PORT_8250; | |
907 | ||
908 | scratch = serial_in(up, UART_SCR); | |
909 | serial_outp(up, UART_SCR, 0xa5); | |
910 | status1 = serial_in(up, UART_SCR); | |
911 | serial_outp(up, UART_SCR, 0x5a); | |
912 | status2 = serial_in(up, UART_SCR); | |
913 | serial_outp(up, UART_SCR, scratch); | |
914 | ||
915 | if (status1 == 0xa5 && status2 == 0x5a) | |
916 | up->port.type = PORT_16450; | |
917 | } | |
918 | ||
919 | static int broken_efr(struct uart_8250_port *up) | |
920 | { | |
921 | /* | |
922 | * Exar ST16C2550 "A2" devices incorrectly detect as | |
923 | * having an EFR, and report an ID of 0x0201. See | |
924 | * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf | |
925 | */ | |
926 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | |
927 | return 1; | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | /* | |
933 | * We know that the chip has FIFOs. Does it have an EFR? The | |
934 | * EFR is located in the same register position as the IIR and | |
935 | * we know the top two bits of the IIR are currently set. The | |
936 | * EFR should contain zero. Try to read the EFR. | |
937 | */ | |
938 | static void autoconfig_16550a(struct uart_8250_port *up) | |
939 | { | |
940 | unsigned char status1, status2; | |
941 | unsigned int iersave; | |
942 | ||
943 | up->port.type = PORT_16550A; | |
944 | up->capabilities |= UART_CAP_FIFO; | |
945 | ||
946 | /* | |
947 | * Check for presence of the EFR when DLAB is set. | |
948 | * Only ST16C650V1 UARTs pass this test. | |
949 | */ | |
950 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
951 | if (serial_in(up, UART_EFR) == 0) { | |
952 | serial_outp(up, UART_EFR, 0xA8); | |
953 | if (serial_in(up, UART_EFR) != 0) { | |
954 | DEBUG_AUTOCONF("EFRv1 "); | |
955 | up->port.type = PORT_16650; | |
956 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
957 | } else { | |
958 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); | |
959 | } | |
960 | serial_outp(up, UART_EFR, 0); | |
961 | return; | |
962 | } | |
963 | ||
964 | /* | |
965 | * Maybe it requires 0xbf to be written to the LCR. | |
966 | * (other ST16C650V2 UARTs, TI16C752A, etc) | |
967 | */ | |
968 | serial_outp(up, UART_LCR, 0xBF); | |
969 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { | |
970 | DEBUG_AUTOCONF("EFRv2 "); | |
971 | autoconfig_has_efr(up); | |
972 | return; | |
973 | } | |
974 | ||
975 | /* | |
976 | * Check for a National Semiconductor SuperIO chip. | |
977 | * Attempt to switch to bank 2, read the value of the LOOP bit | |
978 | * from EXCR1. Switch back to bank 0, change it in MCR. Then | |
979 | * switch back to bank 2, read it from EXCR1 again and check | |
980 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 | |
1da177e4 LT |
981 | */ |
982 | serial_outp(up, UART_LCR, 0); | |
983 | status1 = serial_in(up, UART_MCR); | |
984 | serial_outp(up, UART_LCR, 0xE0); | |
985 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
986 | ||
987 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { | |
988 | serial_outp(up, UART_LCR, 0); | |
989 | serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP); | |
990 | serial_outp(up, UART_LCR, 0xE0); | |
991 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
992 | serial_outp(up, UART_LCR, 0); | |
993 | serial_outp(up, UART_MCR, status1); | |
994 | ||
995 | if ((status2 ^ status1) & UART_MCR_LOOP) { | |
857dde2e DW |
996 | unsigned short quot; |
997 | ||
1da177e4 | 998 | serial_outp(up, UART_LCR, 0xE0); |
857dde2e | 999 | |
b32b19b8 | 1000 | quot = serial_dl_read(up); |
857dde2e DW |
1001 | quot <<= 3; |
1002 | ||
b5b82df6 | 1003 | status1 = serial_in(up, 0x04); /* EXCR2 */ |
1da177e4 LT |
1004 | status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ |
1005 | status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
1006 | serial_outp(up, 0x04, status1); | |
bd71c182 | 1007 | |
b32b19b8 | 1008 | serial_dl_write(up, quot); |
857dde2e | 1009 | |
1da177e4 | 1010 | serial_outp(up, UART_LCR, 0); |
1da177e4 | 1011 | |
857dde2e | 1012 | up->port.uartclk = 921600*16; |
1da177e4 LT |
1013 | up->port.type = PORT_NS16550A; |
1014 | up->capabilities |= UART_NATSEMI; | |
1015 | return; | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | /* | |
1020 | * No EFR. Try to detect a TI16750, which only sets bit 5 of | |
1021 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. | |
1022 | * Try setting it with and without DLAB set. Cheap clones | |
1023 | * set bit 5 without DLAB set. | |
1024 | */ | |
1025 | serial_outp(up, UART_LCR, 0); | |
1026 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1027 | status1 = serial_in(up, UART_IIR) >> 5; | |
1028 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1029 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
1030 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1031 | status2 = serial_in(up, UART_IIR) >> 5; | |
1032 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1033 | serial_outp(up, UART_LCR, 0); | |
1034 | ||
1035 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); | |
1036 | ||
1037 | if (status1 == 6 && status2 == 7) { | |
1038 | up->port.type = PORT_16750; | |
1039 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; | |
1040 | return; | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Try writing and reading the UART_IER_UUE bit (b6). | |
1045 | * If it works, this is probably one of the Xscale platform's | |
1046 | * internal UARTs. | |
1047 | * We're going to explicitly set the UUE bit to 0 before | |
1048 | * trying to write and read a 1 just to make sure it's not | |
1049 | * already a 1 and maybe locked there before we even start start. | |
1050 | */ | |
1051 | iersave = serial_in(up, UART_IER); | |
1052 | serial_outp(up, UART_IER, iersave & ~UART_IER_UUE); | |
1053 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { | |
1054 | /* | |
1055 | * OK it's in a known zero state, try writing and reading | |
1056 | * without disturbing the current state of the other bits. | |
1057 | */ | |
1058 | serial_outp(up, UART_IER, iersave | UART_IER_UUE); | |
1059 | if (serial_in(up, UART_IER) & UART_IER_UUE) { | |
1060 | /* | |
1061 | * It's an Xscale. | |
1062 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). | |
1063 | */ | |
1064 | DEBUG_AUTOCONF("Xscale "); | |
1065 | up->port.type = PORT_XSCALE; | |
1066 | up->capabilities |= UART_CAP_UUE; | |
1067 | return; | |
1068 | } | |
1069 | } else { | |
1070 | /* | |
1071 | * If we got here we couldn't force the IER_UUE bit to 0. | |
1072 | * Log it and continue. | |
1073 | */ | |
1074 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); | |
1075 | } | |
1076 | serial_outp(up, UART_IER, iersave); | |
1077 | } | |
1078 | ||
1079 | /* | |
1080 | * This routine is called by rs_init() to initialize a specific serial | |
1081 | * port. It determines what type of UART chip this serial port is | |
1082 | * using: 8250, 16450, 16550, 16550A. The important question is | |
1083 | * whether or not this UART is a 16550A or not, since this will | |
1084 | * determine whether or not we can use its FIFO features or not. | |
1085 | */ | |
1086 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | |
1087 | { | |
1088 | unsigned char status1, scratch, scratch2, scratch3; | |
1089 | unsigned char save_lcr, save_mcr; | |
1090 | unsigned long flags; | |
1091 | ||
1092 | if (!up->port.iobase && !up->port.mapbase && !up->port.membase) | |
1093 | return; | |
1094 | ||
80647b95 | 1095 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", |
8440838b | 1096 | serial_index(&up->port), up->port.iobase, up->port.membase); |
1da177e4 LT |
1097 | |
1098 | /* | |
1099 | * We really do need global IRQs disabled here - we're going to | |
1100 | * be frobbing the chips IRQ enable register to see if it exists. | |
1101 | */ | |
1102 | spin_lock_irqsave(&up->port.lock, flags); | |
1da177e4 LT |
1103 | |
1104 | up->capabilities = 0; | |
4ba5e35d | 1105 | up->bugs = 0; |
1da177e4 LT |
1106 | |
1107 | if (!(up->port.flags & UPF_BUGGY_UART)) { | |
1108 | /* | |
1109 | * Do a simple existence test first; if we fail this, | |
1110 | * there's no point trying anything else. | |
bd71c182 | 1111 | * |
1da177e4 LT |
1112 | * 0x80 is used as a nonsense port to prevent against |
1113 | * false positives due to ISA bus float. The | |
1114 | * assumption is that 0x80 is a non-existent port; | |
1115 | * which should be safe since include/asm/io.h also | |
1116 | * makes this assumption. | |
1117 | * | |
1118 | * Note: this is safe as long as MCR bit 4 is clear | |
1119 | * and the device is in "PC" mode. | |
1120 | */ | |
1121 | scratch = serial_inp(up, UART_IER); | |
1122 | serial_outp(up, UART_IER, 0); | |
1123 | #ifdef __i386__ | |
1124 | outb(0xff, 0x080); | |
1125 | #endif | |
48212008 TH |
1126 | /* |
1127 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL | |
1128 | * 16C754B) allow only to modify them if an EFR bit is set. | |
1129 | */ | |
1130 | scratch2 = serial_inp(up, UART_IER) & 0x0f; | |
1da177e4 LT |
1131 | serial_outp(up, UART_IER, 0x0F); |
1132 | #ifdef __i386__ | |
1133 | outb(0, 0x080); | |
1134 | #endif | |
48212008 | 1135 | scratch3 = serial_inp(up, UART_IER) & 0x0f; |
1da177e4 LT |
1136 | serial_outp(up, UART_IER, scratch); |
1137 | if (scratch2 != 0 || scratch3 != 0x0F) { | |
1138 | /* | |
1139 | * We failed; there's nothing here | |
1140 | */ | |
1141 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", | |
1142 | scratch2, scratch3); | |
1143 | goto out; | |
1144 | } | |
1145 | } | |
1146 | ||
1147 | save_mcr = serial_in(up, UART_MCR); | |
1148 | save_lcr = serial_in(up, UART_LCR); | |
1149 | ||
bd71c182 | 1150 | /* |
1da177e4 LT |
1151 | * Check to see if a UART is really there. Certain broken |
1152 | * internal modems based on the Rockwell chipset fail this | |
1153 | * test, because they apparently don't implement the loopback | |
1154 | * test mode. So this test is skipped on the COM 1 through | |
1155 | * COM 4 ports. This *should* be safe, since no board | |
1156 | * manufacturer would be stupid enough to design a board | |
1157 | * that conflicts with COM 1-4 --- we hope! | |
1158 | */ | |
1159 | if (!(up->port.flags & UPF_SKIP_TEST)) { | |
1160 | serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); | |
1161 | status1 = serial_inp(up, UART_MSR) & 0xF0; | |
1162 | serial_outp(up, UART_MCR, save_mcr); | |
1163 | if (status1 != 0x90) { | |
1164 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", | |
1165 | status1); | |
1166 | goto out; | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | /* | |
1171 | * We're pretty sure there's a port here. Lets find out what | |
1172 | * type of port it is. The IIR top two bits allows us to find | |
6f0d618f | 1173 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1da177e4 LT |
1174 | * determines what we test for next. |
1175 | * | |
1176 | * We also initialise the EFR (if any) to zero for later. The | |
1177 | * EFR occupies the same register location as the FCR and IIR. | |
1178 | */ | |
1179 | serial_outp(up, UART_LCR, 0xBF); | |
1180 | serial_outp(up, UART_EFR, 0); | |
1181 | serial_outp(up, UART_LCR, 0); | |
1182 | ||
1183 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1184 | scratch = serial_in(up, UART_IIR) >> 6; | |
1185 | ||
1186 | DEBUG_AUTOCONF("iir=%d ", scratch); | |
1187 | ||
1188 | switch (scratch) { | |
1189 | case 0: | |
1190 | autoconfig_8250(up); | |
1191 | break; | |
1192 | case 1: | |
1193 | up->port.type = PORT_UNKNOWN; | |
1194 | break; | |
1195 | case 2: | |
1196 | up->port.type = PORT_16550; | |
1197 | break; | |
1198 | case 3: | |
1199 | autoconfig_16550a(up); | |
1200 | break; | |
1201 | } | |
1202 | ||
1203 | #ifdef CONFIG_SERIAL_8250_RSA | |
1204 | /* | |
1205 | * Only probe for RSA ports if we got the region. | |
1206 | */ | |
1207 | if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) { | |
1208 | int i; | |
1209 | ||
1210 | for (i = 0 ; i < probe_rsa_count; ++i) { | |
1211 | if (probe_rsa[i] == up->port.iobase && | |
1212 | __enable_rsa(up)) { | |
1213 | up->port.type = PORT_RSA; | |
1214 | break; | |
1215 | } | |
1216 | } | |
1217 | } | |
1218 | #endif | |
21c614a7 | 1219 | |
1da177e4 LT |
1220 | serial_outp(up, UART_LCR, save_lcr); |
1221 | ||
1222 | if (up->capabilities != uart_config[up->port.type].flags) { | |
1223 | printk(KERN_WARNING | |
1224 | "ttyS%d: detected caps %08x should be %08x\n", | |
8440838b DM |
1225 | serial_index(&up->port), up->capabilities, |
1226 | uart_config[up->port.type].flags); | |
1da177e4 LT |
1227 | } |
1228 | ||
1229 | up->port.fifosize = uart_config[up->port.type].fifo_size; | |
1230 | up->capabilities = uart_config[up->port.type].flags; | |
1231 | up->tx_loadsz = uart_config[up->port.type].tx_loadsz; | |
1232 | ||
1233 | if (up->port.type == PORT_UNKNOWN) | |
1234 | goto out; | |
1235 | ||
1236 | /* | |
1237 | * Reset the UART. | |
1238 | */ | |
1239 | #ifdef CONFIG_SERIAL_8250_RSA | |
1240 | if (up->port.type == PORT_RSA) | |
1241 | serial_outp(up, UART_RSA_FRR, 0); | |
1242 | #endif | |
1243 | serial_outp(up, UART_MCR, save_mcr); | |
1244 | serial8250_clear_fifos(up); | |
40b36daa | 1245 | serial_in(up, UART_RX); |
5c8c755c LB |
1246 | if (up->capabilities & UART_CAP_UUE) |
1247 | serial_outp(up, UART_IER, UART_IER_UUE); | |
1248 | else | |
1249 | serial_outp(up, UART_IER, 0); | |
1da177e4 | 1250 | |
bd71c182 | 1251 | out: |
1da177e4 | 1252 | spin_unlock_irqrestore(&up->port.lock, flags); |
1da177e4 LT |
1253 | DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name); |
1254 | } | |
1255 | ||
1256 | static void autoconfig_irq(struct uart_8250_port *up) | |
1257 | { | |
1258 | unsigned char save_mcr, save_ier; | |
1259 | unsigned char save_ICP = 0; | |
1260 | unsigned int ICP = 0; | |
1261 | unsigned long irqs; | |
1262 | int irq; | |
1263 | ||
1264 | if (up->port.flags & UPF_FOURPORT) { | |
1265 | ICP = (up->port.iobase & 0xfe0) | 0x1f; | |
1266 | save_ICP = inb_p(ICP); | |
1267 | outb_p(0x80, ICP); | |
1268 | (void) inb_p(ICP); | |
1269 | } | |
1270 | ||
1271 | /* forget possible initially masked and pending IRQ */ | |
1272 | probe_irq_off(probe_irq_on()); | |
1273 | save_mcr = serial_inp(up, UART_MCR); | |
1274 | save_ier = serial_inp(up, UART_IER); | |
1275 | serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); | |
bd71c182 | 1276 | |
1da177e4 LT |
1277 | irqs = probe_irq_on(); |
1278 | serial_outp(up, UART_MCR, 0); | |
6f803cd0 AC |
1279 | udelay(10); |
1280 | if (up->port.flags & UPF_FOURPORT) { | |
1da177e4 LT |
1281 | serial_outp(up, UART_MCR, |
1282 | UART_MCR_DTR | UART_MCR_RTS); | |
1283 | } else { | |
1284 | serial_outp(up, UART_MCR, | |
1285 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); | |
1286 | } | |
1287 | serial_outp(up, UART_IER, 0x0f); /* enable all intrs */ | |
1288 | (void)serial_inp(up, UART_LSR); | |
1289 | (void)serial_inp(up, UART_RX); | |
1290 | (void)serial_inp(up, UART_IIR); | |
1291 | (void)serial_inp(up, UART_MSR); | |
1292 | serial_outp(up, UART_TX, 0xFF); | |
6f803cd0 | 1293 | udelay(20); |
1da177e4 LT |
1294 | irq = probe_irq_off(irqs); |
1295 | ||
1296 | serial_outp(up, UART_MCR, save_mcr); | |
1297 | serial_outp(up, UART_IER, save_ier); | |
1298 | ||
1299 | if (up->port.flags & UPF_FOURPORT) | |
1300 | outb_p(save_ICP, ICP); | |
1301 | ||
1302 | up->port.irq = (irq > 0) ? irq : 0; | |
1303 | } | |
1304 | ||
e763b90c RK |
1305 | static inline void __stop_tx(struct uart_8250_port *p) |
1306 | { | |
1307 | if (p->ier & UART_IER_THRI) { | |
1308 | p->ier &= ~UART_IER_THRI; | |
1309 | serial_out(p, UART_IER, p->ier); | |
1310 | } | |
1311 | } | |
1312 | ||
b129a8cc | 1313 | static void serial8250_stop_tx(struct uart_port *port) |
1da177e4 LT |
1314 | { |
1315 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1316 | ||
e763b90c | 1317 | __stop_tx(up); |
1da177e4 LT |
1318 | |
1319 | /* | |
e763b90c | 1320 | * We really want to stop the transmitter from sending. |
1da177e4 | 1321 | */ |
e763b90c | 1322 | if (up->port.type == PORT_16C950) { |
1da177e4 LT |
1323 | up->acr |= UART_ACR_TXDIS; |
1324 | serial_icr_write(up, UART_ACR, up->acr); | |
1325 | } | |
1326 | } | |
1327 | ||
55d3b282 RK |
1328 | static void transmit_chars(struct uart_8250_port *up); |
1329 | ||
b129a8cc | 1330 | static void serial8250_start_tx(struct uart_port *port) |
1da177e4 LT |
1331 | { |
1332 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1333 | ||
1334 | if (!(up->ier & UART_IER_THRI)) { | |
1335 | up->ier |= UART_IER_THRI; | |
1336 | serial_out(up, UART_IER, up->ier); | |
55d3b282 | 1337 | |
67f7654e | 1338 | if (up->bugs & UART_BUG_TXEN) { |
68cb4f8e | 1339 | unsigned char lsr; |
55d3b282 | 1340 | lsr = serial_in(up, UART_LSR); |
ad4c2aa6 | 1341 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
bd71c182 | 1342 | if ((up->port.type == PORT_RM9000) ? |
68cb4f8e IJ |
1343 | (lsr & UART_LSR_THRE) : |
1344 | (lsr & UART_LSR_TEMT)) | |
55d3b282 RK |
1345 | transmit_chars(up); |
1346 | } | |
1da177e4 | 1347 | } |
e763b90c | 1348 | |
1da177e4 | 1349 | /* |
e763b90c | 1350 | * Re-enable the transmitter if we disabled it. |
1da177e4 | 1351 | */ |
e763b90c | 1352 | if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1da177e4 LT |
1353 | up->acr &= ~UART_ACR_TXDIS; |
1354 | serial_icr_write(up, UART_ACR, up->acr); | |
1355 | } | |
1356 | } | |
1357 | ||
1358 | static void serial8250_stop_rx(struct uart_port *port) | |
1359 | { | |
1360 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1361 | ||
1362 | up->ier &= ~UART_IER_RLSI; | |
1363 | up->port.read_status_mask &= ~UART_LSR_DR; | |
1364 | serial_out(up, UART_IER, up->ier); | |
1365 | } | |
1366 | ||
1367 | static void serial8250_enable_ms(struct uart_port *port) | |
1368 | { | |
1369 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1370 | ||
21c614a7 PA |
1371 | /* no MSR capabilities */ |
1372 | if (up->bugs & UART_BUG_NOMSR) | |
1373 | return; | |
1374 | ||
1da177e4 LT |
1375 | up->ier |= UART_IER_MSI; |
1376 | serial_out(up, UART_IER, up->ier); | |
1377 | } | |
1378 | ||
ea8874dc | 1379 | static void |
cc79aa9d | 1380 | receive_chars(struct uart_8250_port *up, unsigned int *status) |
1da177e4 | 1381 | { |
ebd2c8f6 | 1382 | struct tty_struct *tty = up->port.state->port.tty; |
1da177e4 LT |
1383 | unsigned char ch, lsr = *status; |
1384 | int max_count = 256; | |
1385 | char flag; | |
1386 | ||
1387 | do { | |
7500b1f6 AR |
1388 | if (likely(lsr & UART_LSR_DR)) |
1389 | ch = serial_inp(up, UART_RX); | |
1390 | else | |
1391 | /* | |
1392 | * Intel 82571 has a Serial Over Lan device that will | |
1393 | * set UART_LSR_BI without setting UART_LSR_DR when | |
1394 | * it receives a break. To avoid reading from the | |
1395 | * receive buffer without UART_LSR_DR bit set, we | |
1396 | * just force the read character to be 0 | |
1397 | */ | |
1398 | ch = 0; | |
1399 | ||
1da177e4 LT |
1400 | flag = TTY_NORMAL; |
1401 | up->port.icount.rx++; | |
1402 | ||
ad4c2aa6 CM |
1403 | lsr |= up->lsr_saved_flags; |
1404 | up->lsr_saved_flags = 0; | |
1da177e4 | 1405 | |
ad4c2aa6 | 1406 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { |
1da177e4 LT |
1407 | /* |
1408 | * For statistics only | |
1409 | */ | |
1410 | if (lsr & UART_LSR_BI) { | |
1411 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
1412 | up->port.icount.brk++; | |
1413 | /* | |
1414 | * We do the SysRQ and SAK checking | |
1415 | * here because otherwise the break | |
1416 | * may get masked by ignore_status_mask | |
1417 | * or read_status_mask. | |
1418 | */ | |
1419 | if (uart_handle_break(&up->port)) | |
1420 | goto ignore_char; | |
1421 | } else if (lsr & UART_LSR_PE) | |
1422 | up->port.icount.parity++; | |
1423 | else if (lsr & UART_LSR_FE) | |
1424 | up->port.icount.frame++; | |
1425 | if (lsr & UART_LSR_OE) | |
1426 | up->port.icount.overrun++; | |
1427 | ||
1428 | /* | |
23907eb8 | 1429 | * Mask off conditions which should be ignored. |
1da177e4 LT |
1430 | */ |
1431 | lsr &= up->port.read_status_mask; | |
1432 | ||
1433 | if (lsr & UART_LSR_BI) { | |
1434 | DEBUG_INTR("handling break...."); | |
1435 | flag = TTY_BREAK; | |
1436 | } else if (lsr & UART_LSR_PE) | |
1437 | flag = TTY_PARITY; | |
1438 | else if (lsr & UART_LSR_FE) | |
1439 | flag = TTY_FRAME; | |
1440 | } | |
7d12e780 | 1441 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 1442 | goto ignore_char; |
05ab3014 RK |
1443 | |
1444 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
1445 | ||
6f803cd0 | 1446 | ignore_char: |
1da177e4 | 1447 | lsr = serial_inp(up, UART_LSR); |
7500b1f6 | 1448 | } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); |
1da177e4 LT |
1449 | spin_unlock(&up->port.lock); |
1450 | tty_flip_buffer_push(tty); | |
1451 | spin_lock(&up->port.lock); | |
1452 | *status = lsr; | |
1453 | } | |
1454 | ||
ea8874dc | 1455 | static void transmit_chars(struct uart_8250_port *up) |
1da177e4 | 1456 | { |
ebd2c8f6 | 1457 | struct circ_buf *xmit = &up->port.state->xmit; |
1da177e4 LT |
1458 | int count; |
1459 | ||
1460 | if (up->port.x_char) { | |
1461 | serial_outp(up, UART_TX, up->port.x_char); | |
1462 | up->port.icount.tx++; | |
1463 | up->port.x_char = 0; | |
1464 | return; | |
1465 | } | |
b129a8cc RK |
1466 | if (uart_tx_stopped(&up->port)) { |
1467 | serial8250_stop_tx(&up->port); | |
1468 | return; | |
1469 | } | |
1470 | if (uart_circ_empty(xmit)) { | |
e763b90c | 1471 | __stop_tx(up); |
1da177e4 LT |
1472 | return; |
1473 | } | |
1474 | ||
1475 | count = up->tx_loadsz; | |
1476 | do { | |
1477 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
1478 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1479 | up->port.icount.tx++; | |
1480 | if (uart_circ_empty(xmit)) | |
1481 | break; | |
1482 | } while (--count > 0); | |
1483 | ||
1484 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1485 | uart_write_wakeup(&up->port); | |
1486 | ||
1487 | DEBUG_INTR("THRE..."); | |
1488 | ||
1489 | if (uart_circ_empty(xmit)) | |
e763b90c | 1490 | __stop_tx(up); |
1da177e4 LT |
1491 | } |
1492 | ||
2af7cd68 | 1493 | static unsigned int check_modem_status(struct uart_8250_port *up) |
1da177e4 | 1494 | { |
2af7cd68 RK |
1495 | unsigned int status = serial_in(up, UART_MSR); |
1496 | ||
ad4c2aa6 CM |
1497 | status |= up->msr_saved_flags; |
1498 | up->msr_saved_flags = 0; | |
fdc30b3d | 1499 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && |
ebd2c8f6 | 1500 | up->port.state != NULL) { |
2af7cd68 RK |
1501 | if (status & UART_MSR_TERI) |
1502 | up->port.icount.rng++; | |
1503 | if (status & UART_MSR_DDSR) | |
1504 | up->port.icount.dsr++; | |
1505 | if (status & UART_MSR_DDCD) | |
1506 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
1507 | if (status & UART_MSR_DCTS) | |
1508 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
1509 | ||
bdc04e31 | 1510 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
2af7cd68 | 1511 | } |
1da177e4 | 1512 | |
2af7cd68 | 1513 | return status; |
1da177e4 LT |
1514 | } |
1515 | ||
1516 | /* | |
1517 | * This handles the interrupt from one port. | |
1518 | */ | |
b5d674ab | 1519 | static void serial8250_handle_port(struct uart_8250_port *up) |
1da177e4 | 1520 | { |
45e24601 | 1521 | unsigned int status; |
4bf3631c | 1522 | unsigned long flags; |
45e24601 | 1523 | |
4bf3631c | 1524 | spin_lock_irqsave(&up->port.lock, flags); |
45e24601 RK |
1525 | |
1526 | status = serial_inp(up, UART_LSR); | |
1da177e4 LT |
1527 | |
1528 | DEBUG_INTR("status = %x...", status); | |
1529 | ||
7500b1f6 | 1530 | if (status & (UART_LSR_DR | UART_LSR_BI)) |
7d12e780 | 1531 | receive_chars(up, &status); |
1da177e4 LT |
1532 | check_modem_status(up); |
1533 | if (status & UART_LSR_THRE) | |
1534 | transmit_chars(up); | |
45e24601 | 1535 | |
4bf3631c | 1536 | spin_unlock_irqrestore(&up->port.lock, flags); |
1da177e4 LT |
1537 | } |
1538 | ||
1539 | /* | |
1540 | * This is the serial driver's interrupt routine. | |
1541 | * | |
1542 | * Arjan thinks the old way was overly complex, so it got simplified. | |
1543 | * Alan disagrees, saying that need the complexity to handle the weird | |
1544 | * nature of ISA shared interrupts. (This is a special exception.) | |
1545 | * | |
1546 | * In order to handle ISA shared interrupts properly, we need to check | |
1547 | * that all ports have been serviced, and therefore the ISA interrupt | |
1548 | * line has been de-asserted. | |
1549 | * | |
1550 | * This means we need to loop through all ports. checking that they | |
1551 | * don't have an interrupt pending. | |
1552 | */ | |
7d12e780 | 1553 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1554 | { |
1555 | struct irq_info *i = dev_id; | |
1556 | struct list_head *l, *end = NULL; | |
1557 | int pass_counter = 0, handled = 0; | |
1558 | ||
1559 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); | |
1560 | ||
1561 | spin_lock(&i->lock); | |
1562 | ||
1563 | l = i->head; | |
1564 | do { | |
1565 | struct uart_8250_port *up; | |
1566 | unsigned int iir; | |
1567 | ||
1568 | up = list_entry(l, struct uart_8250_port, list); | |
1569 | ||
1570 | iir = serial_in(up, UART_IIR); | |
1571 | if (!(iir & UART_IIR_NO_INT)) { | |
7d12e780 | 1572 | serial8250_handle_port(up); |
1da177e4 LT |
1573 | |
1574 | handled = 1; | |
1575 | ||
beab697a MSJ |
1576 | end = NULL; |
1577 | } else if (up->port.iotype == UPIO_DWAPB && | |
1578 | (iir & UART_IIR_BUSY) == UART_IIR_BUSY) { | |
1579 | /* The DesignWare APB UART has an Busy Detect (0x07) | |
1580 | * interrupt meaning an LCR write attempt occured while the | |
1581 | * UART was busy. The interrupt must be cleared by reading | |
1582 | * the UART status register (USR) and the LCR re-written. */ | |
1583 | unsigned int status; | |
1584 | status = *(volatile u32 *)up->port.private_data; | |
1585 | serial_out(up, UART_LCR, up->lcr); | |
1586 | ||
1587 | handled = 1; | |
1588 | ||
1da177e4 LT |
1589 | end = NULL; |
1590 | } else if (end == NULL) | |
1591 | end = l; | |
1592 | ||
1593 | l = l->next; | |
1594 | ||
1595 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
1596 | /* If we hit this, we're dead. */ | |
1597 | printk(KERN_ERR "serial8250: too much work for " | |
1598 | "irq%d\n", irq); | |
1599 | break; | |
1600 | } | |
1601 | } while (l != end); | |
1602 | ||
1603 | spin_unlock(&i->lock); | |
1604 | ||
1605 | DEBUG_INTR("end.\n"); | |
1606 | ||
1607 | return IRQ_RETVAL(handled); | |
1608 | } | |
1609 | ||
1610 | /* | |
1611 | * To support ISA shared interrupts, we need to have one interrupt | |
1612 | * handler that ensures that the IRQ line has been deasserted | |
1613 | * before returning. Failing to do this will result in the IRQ | |
1614 | * line being stuck active, and, since ISA irqs are edge triggered, | |
1615 | * no more IRQs will be seen. | |
1616 | */ | |
1617 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) | |
1618 | { | |
1619 | spin_lock_irq(&i->lock); | |
1620 | ||
1621 | if (!list_empty(i->head)) { | |
1622 | if (i->head == &up->list) | |
1623 | i->head = i->head->next; | |
1624 | list_del(&up->list); | |
1625 | } else { | |
1626 | BUG_ON(i->head != &up->list); | |
1627 | i->head = NULL; | |
1628 | } | |
1da177e4 | 1629 | spin_unlock_irq(&i->lock); |
25db8ad5 AC |
1630 | /* List empty so throw away the hash node */ |
1631 | if (i->head == NULL) { | |
1632 | hlist_del(&i->node); | |
1633 | kfree(i); | |
1634 | } | |
1da177e4 LT |
1635 | } |
1636 | ||
1637 | static int serial_link_irq_chain(struct uart_8250_port *up) | |
1638 | { | |
25db8ad5 AC |
1639 | struct hlist_head *h; |
1640 | struct hlist_node *n; | |
1641 | struct irq_info *i; | |
40663cc7 | 1642 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; |
1da177e4 | 1643 | |
25db8ad5 AC |
1644 | mutex_lock(&hash_mutex); |
1645 | ||
1646 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; | |
1647 | ||
1648 | hlist_for_each(n, h) { | |
1649 | i = hlist_entry(n, struct irq_info, node); | |
1650 | if (i->irq == up->port.irq) | |
1651 | break; | |
1652 | } | |
1653 | ||
1654 | if (n == NULL) { | |
1655 | i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); | |
1656 | if (i == NULL) { | |
1657 | mutex_unlock(&hash_mutex); | |
1658 | return -ENOMEM; | |
1659 | } | |
1660 | spin_lock_init(&i->lock); | |
1661 | i->irq = up->port.irq; | |
1662 | hlist_add_head(&i->node, h); | |
1663 | } | |
1664 | mutex_unlock(&hash_mutex); | |
1665 | ||
1da177e4 LT |
1666 | spin_lock_irq(&i->lock); |
1667 | ||
1668 | if (i->head) { | |
1669 | list_add(&up->list, i->head); | |
1670 | spin_unlock_irq(&i->lock); | |
1671 | ||
1672 | ret = 0; | |
1673 | } else { | |
1674 | INIT_LIST_HEAD(&up->list); | |
1675 | i->head = &up->list; | |
1676 | spin_unlock_irq(&i->lock); | |
1c2f0493 | 1677 | irq_flags |= up->port.irqflags; |
1da177e4 LT |
1678 | ret = request_irq(up->port.irq, serial8250_interrupt, |
1679 | irq_flags, "serial", i); | |
1680 | if (ret < 0) | |
1681 | serial_do_unlink(i, up); | |
1682 | } | |
1683 | ||
1684 | return ret; | |
1685 | } | |
1686 | ||
1687 | static void serial_unlink_irq_chain(struct uart_8250_port *up) | |
1688 | { | |
25db8ad5 AC |
1689 | struct irq_info *i; |
1690 | struct hlist_node *n; | |
1691 | struct hlist_head *h; | |
1da177e4 | 1692 | |
25db8ad5 AC |
1693 | mutex_lock(&hash_mutex); |
1694 | ||
1695 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; | |
1696 | ||
1697 | hlist_for_each(n, h) { | |
1698 | i = hlist_entry(n, struct irq_info, node); | |
1699 | if (i->irq == up->port.irq) | |
1700 | break; | |
1701 | } | |
1702 | ||
1703 | BUG_ON(n == NULL); | |
1da177e4 LT |
1704 | BUG_ON(i->head == NULL); |
1705 | ||
1706 | if (list_empty(i->head)) | |
1707 | free_irq(up->port.irq, i); | |
1708 | ||
1709 | serial_do_unlink(i, up); | |
25db8ad5 | 1710 | mutex_unlock(&hash_mutex); |
1da177e4 LT |
1711 | } |
1712 | ||
40b36daa AW |
1713 | /* Base timer interval for polling */ |
1714 | static inline int poll_timeout(int timeout) | |
1715 | { | |
1716 | return timeout > 6 ? (timeout / 2 - 2) : 1; | |
1717 | } | |
1718 | ||
1da177e4 LT |
1719 | /* |
1720 | * This function is used to handle ports that do not have an | |
1721 | * interrupt. This doesn't work very well for 16450's, but gives | |
1722 | * barely passable results for a 16550A. (Although at the expense | |
1723 | * of much CPU overhead). | |
1724 | */ | |
1725 | static void serial8250_timeout(unsigned long data) | |
1726 | { | |
1727 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
1da177e4 LT |
1728 | unsigned int iir; |
1729 | ||
1730 | iir = serial_in(up, UART_IIR); | |
45e24601 | 1731 | if (!(iir & UART_IIR_NO_INT)) |
7d12e780 | 1732 | serial8250_handle_port(up); |
40b36daa AW |
1733 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
1734 | } | |
1735 | ||
1736 | static void serial8250_backup_timeout(unsigned long data) | |
1737 | { | |
1738 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
ad4c2aa6 CM |
1739 | unsigned int iir, ier = 0, lsr; |
1740 | unsigned long flags; | |
40b36daa AW |
1741 | |
1742 | /* | |
1743 | * Must disable interrupts or else we risk racing with the interrupt | |
1744 | * based handler. | |
1745 | */ | |
1746 | if (is_real_interrupt(up->port.irq)) { | |
1747 | ier = serial_in(up, UART_IER); | |
1748 | serial_out(up, UART_IER, 0); | |
1749 | } | |
1da177e4 | 1750 | |
40b36daa AW |
1751 | iir = serial_in(up, UART_IIR); |
1752 | ||
1753 | /* | |
1754 | * This should be a safe test for anyone who doesn't trust the | |
1755 | * IIR bits on their UART, but it's specifically designed for | |
1756 | * the "Diva" UART used on the management processor on many HP | |
1757 | * ia64 and parisc boxes. | |
1758 | */ | |
ad4c2aa6 CM |
1759 | spin_lock_irqsave(&up->port.lock, flags); |
1760 | lsr = serial_in(up, UART_LSR); | |
1761 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
1762 | spin_unlock_irqrestore(&up->port.lock, flags); | |
40b36daa | 1763 | if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && |
ebd2c8f6 | 1764 | (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && |
ad4c2aa6 | 1765 | (lsr & UART_LSR_THRE)) { |
40b36daa AW |
1766 | iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); |
1767 | iir |= UART_IIR_THRI; | |
1768 | } | |
1769 | ||
1770 | if (!(iir & UART_IIR_NO_INT)) | |
1771 | serial8250_handle_port(up); | |
1772 | ||
1773 | if (is_real_interrupt(up->port.irq)) | |
1774 | serial_out(up, UART_IER, ier); | |
1775 | ||
1776 | /* Standard timer interval plus 0.2s to keep the port running */ | |
6f803cd0 AC |
1777 | mod_timer(&up->timer, |
1778 | jiffies + poll_timeout(up->port.timeout) + HZ / 5); | |
1da177e4 LT |
1779 | } |
1780 | ||
1781 | static unsigned int serial8250_tx_empty(struct uart_port *port) | |
1782 | { | |
1783 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1784 | unsigned long flags; | |
ad4c2aa6 | 1785 | unsigned int lsr; |
1da177e4 LT |
1786 | |
1787 | spin_lock_irqsave(&up->port.lock, flags); | |
ad4c2aa6 CM |
1788 | lsr = serial_in(up, UART_LSR); |
1789 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
1da177e4 LT |
1790 | spin_unlock_irqrestore(&up->port.lock, flags); |
1791 | ||
bca47613 | 1792 | return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; |
1da177e4 LT |
1793 | } |
1794 | ||
1795 | static unsigned int serial8250_get_mctrl(struct uart_port *port) | |
1796 | { | |
1797 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2af7cd68 | 1798 | unsigned int status; |
1da177e4 LT |
1799 | unsigned int ret; |
1800 | ||
2af7cd68 | 1801 | status = check_modem_status(up); |
1da177e4 LT |
1802 | |
1803 | ret = 0; | |
1804 | if (status & UART_MSR_DCD) | |
1805 | ret |= TIOCM_CAR; | |
1806 | if (status & UART_MSR_RI) | |
1807 | ret |= TIOCM_RNG; | |
1808 | if (status & UART_MSR_DSR) | |
1809 | ret |= TIOCM_DSR; | |
1810 | if (status & UART_MSR_CTS) | |
1811 | ret |= TIOCM_CTS; | |
1812 | return ret; | |
1813 | } | |
1814 | ||
1815 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1816 | { | |
1817 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1818 | unsigned char mcr = 0; | |
1819 | ||
1820 | if (mctrl & TIOCM_RTS) | |
1821 | mcr |= UART_MCR_RTS; | |
1822 | if (mctrl & TIOCM_DTR) | |
1823 | mcr |= UART_MCR_DTR; | |
1824 | if (mctrl & TIOCM_OUT1) | |
1825 | mcr |= UART_MCR_OUT1; | |
1826 | if (mctrl & TIOCM_OUT2) | |
1827 | mcr |= UART_MCR_OUT2; | |
1828 | if (mctrl & TIOCM_LOOP) | |
1829 | mcr |= UART_MCR_LOOP; | |
1830 | ||
1831 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; | |
1832 | ||
1833 | serial_out(up, UART_MCR, mcr); | |
1834 | } | |
1835 | ||
1836 | static void serial8250_break_ctl(struct uart_port *port, int break_state) | |
1837 | { | |
1838 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1839 | unsigned long flags; | |
1840 | ||
1841 | spin_lock_irqsave(&up->port.lock, flags); | |
1842 | if (break_state == -1) | |
1843 | up->lcr |= UART_LCR_SBC; | |
1844 | else | |
1845 | up->lcr &= ~UART_LCR_SBC; | |
1846 | serial_out(up, UART_LCR, up->lcr); | |
1847 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1848 | } | |
1849 | ||
40b36daa AW |
1850 | /* |
1851 | * Wait for transmitter & holding register to empty | |
1852 | */ | |
b5d674ab | 1853 | static void wait_for_xmitr(struct uart_8250_port *up, int bits) |
40b36daa AW |
1854 | { |
1855 | unsigned int status, tmout = 10000; | |
1856 | ||
1857 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1858 | do { | |
1859 | status = serial_in(up, UART_LSR); | |
1860 | ||
ad4c2aa6 | 1861 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; |
40b36daa AW |
1862 | |
1863 | if (--tmout == 0) | |
1864 | break; | |
1865 | udelay(1); | |
1866 | } while ((status & bits) != bits); | |
1867 | ||
1868 | /* Wait up to 1s for flow control if necessary */ | |
1869 | if (up->port.flags & UPF_CONS_FLOW) { | |
ad4c2aa6 CM |
1870 | unsigned int tmout; |
1871 | for (tmout = 1000000; tmout; tmout--) { | |
1872 | unsigned int msr = serial_in(up, UART_MSR); | |
1873 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1874 | if (msr & UART_MSR_CTS) | |
1875 | break; | |
40b36daa AW |
1876 | udelay(1); |
1877 | touch_nmi_watchdog(); | |
1878 | } | |
1879 | } | |
1880 | } | |
1881 | ||
f2d937f3 JW |
1882 | #ifdef CONFIG_CONSOLE_POLL |
1883 | /* | |
1884 | * Console polling routines for writing and reading from the uart while | |
1885 | * in an interrupt or debug context. | |
1886 | */ | |
1887 | ||
1888 | static int serial8250_get_poll_char(struct uart_port *port) | |
1889 | { | |
1890 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1891 | unsigned char lsr = serial_inp(up, UART_LSR); | |
1892 | ||
1893 | while (!(lsr & UART_LSR_DR)) | |
1894 | lsr = serial_inp(up, UART_LSR); | |
1895 | ||
1896 | return serial_inp(up, UART_RX); | |
1897 | } | |
1898 | ||
1899 | ||
1900 | static void serial8250_put_poll_char(struct uart_port *port, | |
1901 | unsigned char c) | |
1902 | { | |
1903 | unsigned int ier; | |
1904 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1905 | ||
1906 | /* | |
1907 | * First save the IER then disable the interrupts | |
1908 | */ | |
1909 | ier = serial_in(up, UART_IER); | |
1910 | if (up->capabilities & UART_CAP_UUE) | |
1911 | serial_out(up, UART_IER, UART_IER_UUE); | |
1912 | else | |
1913 | serial_out(up, UART_IER, 0); | |
1914 | ||
1915 | wait_for_xmitr(up, BOTH_EMPTY); | |
1916 | /* | |
1917 | * Send the character out. | |
1918 | * If a LF, also do CR... | |
1919 | */ | |
1920 | serial_out(up, UART_TX, c); | |
1921 | if (c == 10) { | |
1922 | wait_for_xmitr(up, BOTH_EMPTY); | |
1923 | serial_out(up, UART_TX, 13); | |
1924 | } | |
1925 | ||
1926 | /* | |
1927 | * Finally, wait for transmitter to become empty | |
1928 | * and restore the IER | |
1929 | */ | |
1930 | wait_for_xmitr(up, BOTH_EMPTY); | |
1931 | serial_out(up, UART_IER, ier); | |
1932 | } | |
1933 | ||
1934 | #endif /* CONFIG_CONSOLE_POLL */ | |
1935 | ||
1da177e4 LT |
1936 | static int serial8250_startup(struct uart_port *port) |
1937 | { | |
1938 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1939 | unsigned long flags; | |
55d3b282 | 1940 | unsigned char lsr, iir; |
1da177e4 LT |
1941 | int retval; |
1942 | ||
1943 | up->capabilities = uart_config[up->port.type].flags; | |
1944 | up->mcr = 0; | |
1945 | ||
b8e7e40a AC |
1946 | if (up->port.iotype != up->cur_iotype) |
1947 | set_io_from_upio(port); | |
1948 | ||
1da177e4 LT |
1949 | if (up->port.type == PORT_16C950) { |
1950 | /* Wake up and initialize UART */ | |
1951 | up->acr = 0; | |
1952 | serial_outp(up, UART_LCR, 0xBF); | |
1953 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
1954 | serial_outp(up, UART_IER, 0); | |
1955 | serial_outp(up, UART_LCR, 0); | |
1956 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ | |
1957 | serial_outp(up, UART_LCR, 0xBF); | |
1958 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
1959 | serial_outp(up, UART_LCR, 0); | |
1960 | } | |
1961 | ||
1962 | #ifdef CONFIG_SERIAL_8250_RSA | |
1963 | /* | |
1964 | * If this is an RSA port, see if we can kick it up to the | |
1965 | * higher speed clock. | |
1966 | */ | |
1967 | enable_rsa(up); | |
1968 | #endif | |
1969 | ||
1970 | /* | |
1971 | * Clear the FIFO buffers and disable them. | |
7f927fcc | 1972 | * (they will be reenabled in set_termios()) |
1da177e4 LT |
1973 | */ |
1974 | serial8250_clear_fifos(up); | |
1975 | ||
1976 | /* | |
1977 | * Clear the interrupt registers. | |
1978 | */ | |
1979 | (void) serial_inp(up, UART_LSR); | |
1980 | (void) serial_inp(up, UART_RX); | |
1981 | (void) serial_inp(up, UART_IIR); | |
1982 | (void) serial_inp(up, UART_MSR); | |
1983 | ||
1984 | /* | |
1985 | * At this point, there's no way the LSR could still be 0xff; | |
1986 | * if it is, then bail out, because there's likely no UART | |
1987 | * here. | |
1988 | */ | |
1989 | if (!(up->port.flags & UPF_BUGGY_UART) && | |
1990 | (serial_inp(up, UART_LSR) == 0xff)) { | |
8440838b DM |
1991 | printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n", |
1992 | serial_index(&up->port)); | |
1da177e4 LT |
1993 | return -ENODEV; |
1994 | } | |
1995 | ||
1996 | /* | |
1997 | * For a XR16C850, we need to set the trigger levels | |
1998 | */ | |
1999 | if (up->port.type == PORT_16850) { | |
2000 | unsigned char fctr; | |
2001 | ||
2002 | serial_outp(up, UART_LCR, 0xbf); | |
2003 | ||
2004 | fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); | |
2005 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); | |
2006 | serial_outp(up, UART_TRG, UART_TRG_96); | |
2007 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX); | |
2008 | serial_outp(up, UART_TRG, UART_TRG_96); | |
2009 | ||
2010 | serial_outp(up, UART_LCR, 0); | |
2011 | } | |
2012 | ||
40b36daa | 2013 | if (is_real_interrupt(up->port.irq)) { |
01c194d9 | 2014 | unsigned char iir1; |
40b36daa AW |
2015 | /* |
2016 | * Test for UARTs that do not reassert THRE when the | |
2017 | * transmitter is idle and the interrupt has already | |
2018 | * been cleared. Real 16550s should always reassert | |
2019 | * this interrupt whenever the transmitter is idle and | |
2020 | * the interrupt is enabled. Delays are necessary to | |
2021 | * allow register changes to become visible. | |
2022 | */ | |
c389d27b | 2023 | spin_lock_irqsave(&up->port.lock, flags); |
1c2f0493 | 2024 | if (up->port.irqflags & IRQF_SHARED) |
768aec0b | 2025 | disable_irq_nosync(up->port.irq); |
40b36daa AW |
2026 | |
2027 | wait_for_xmitr(up, UART_LSR_THRE); | |
2028 | serial_out_sync(up, UART_IER, UART_IER_THRI); | |
2029 | udelay(1); /* allow THRE to set */ | |
01c194d9 | 2030 | iir1 = serial_in(up, UART_IIR); |
40b36daa AW |
2031 | serial_out(up, UART_IER, 0); |
2032 | serial_out_sync(up, UART_IER, UART_IER_THRI); | |
2033 | udelay(1); /* allow a working UART time to re-assert THRE */ | |
2034 | iir = serial_in(up, UART_IIR); | |
2035 | serial_out(up, UART_IER, 0); | |
2036 | ||
1c2f0493 | 2037 | if (up->port.irqflags & IRQF_SHARED) |
768aec0b | 2038 | enable_irq(up->port.irq); |
c389d27b | 2039 | spin_unlock_irqrestore(&up->port.lock, flags); |
40b36daa AW |
2040 | |
2041 | /* | |
2042 | * If the interrupt is not reasserted, setup a timer to | |
2043 | * kick the UART on a regular basis. | |
2044 | */ | |
01c194d9 | 2045 | if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) { |
363f66fe | 2046 | up->bugs |= UART_BUG_THRE; |
8440838b DM |
2047 | pr_debug("ttyS%d - using backup timer\n", |
2048 | serial_index(port)); | |
40b36daa AW |
2049 | } |
2050 | } | |
2051 | ||
363f66fe WN |
2052 | /* |
2053 | * The above check will only give an accurate result the first time | |
2054 | * the port is opened so this value needs to be preserved. | |
2055 | */ | |
2056 | if (up->bugs & UART_BUG_THRE) { | |
2057 | up->timer.function = serial8250_backup_timeout; | |
2058 | up->timer.data = (unsigned long)up; | |
2059 | mod_timer(&up->timer, jiffies + | |
2060 | poll_timeout(up->port.timeout) + HZ / 5); | |
2061 | } | |
2062 | ||
1da177e4 LT |
2063 | /* |
2064 | * If the "interrupt" for this port doesn't correspond with any | |
2065 | * hardware interrupt, we use a timer-based system. The original | |
2066 | * driver used to do this with IRQ0. | |
2067 | */ | |
2068 | if (!is_real_interrupt(up->port.irq)) { | |
1da177e4 | 2069 | up->timer.data = (unsigned long)up; |
40b36daa | 2070 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
1da177e4 LT |
2071 | } else { |
2072 | retval = serial_link_irq_chain(up); | |
2073 | if (retval) | |
2074 | return retval; | |
2075 | } | |
2076 | ||
2077 | /* | |
2078 | * Now, initialize the UART | |
2079 | */ | |
2080 | serial_outp(up, UART_LCR, UART_LCR_WLEN8); | |
2081 | ||
2082 | spin_lock_irqsave(&up->port.lock, flags); | |
2083 | if (up->port.flags & UPF_FOURPORT) { | |
2084 | if (!is_real_interrupt(up->port.irq)) | |
2085 | up->port.mctrl |= TIOCM_OUT1; | |
2086 | } else | |
2087 | /* | |
2088 | * Most PC uarts need OUT2 raised to enable interrupts. | |
2089 | */ | |
2090 | if (is_real_interrupt(up->port.irq)) | |
2091 | up->port.mctrl |= TIOCM_OUT2; | |
2092 | ||
2093 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
55d3b282 | 2094 | |
b6adea33 MCC |
2095 | /* Serial over Lan (SoL) hack: |
2096 | Intel 8257x Gigabit ethernet chips have a | |
2097 | 16550 emulation, to be used for Serial Over Lan. | |
2098 | Those chips take a longer time than a normal | |
2099 | serial device to signalize that a transmission | |
2100 | data was queued. Due to that, the above test generally | |
2101 | fails. One solution would be to delay the reading of | |
2102 | iir. However, this is not reliable, since the timeout | |
2103 | is variable. So, let's just don't test if we receive | |
2104 | TX irq. This way, we'll never enable UART_BUG_TXEN. | |
2105 | */ | |
d41a4b51 | 2106 | if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) |
b6adea33 MCC |
2107 | goto dont_test_tx_en; |
2108 | ||
55d3b282 RK |
2109 | /* |
2110 | * Do a quick test to see if we receive an | |
2111 | * interrupt when we enable the TX irq. | |
2112 | */ | |
2113 | serial_outp(up, UART_IER, UART_IER_THRI); | |
2114 | lsr = serial_in(up, UART_LSR); | |
2115 | iir = serial_in(up, UART_IIR); | |
2116 | serial_outp(up, UART_IER, 0); | |
2117 | ||
2118 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { | |
67f7654e RK |
2119 | if (!(up->bugs & UART_BUG_TXEN)) { |
2120 | up->bugs |= UART_BUG_TXEN; | |
55d3b282 | 2121 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
8440838b | 2122 | serial_index(port)); |
55d3b282 RK |
2123 | } |
2124 | } else { | |
67f7654e | 2125 | up->bugs &= ~UART_BUG_TXEN; |
55d3b282 RK |
2126 | } |
2127 | ||
b6adea33 | 2128 | dont_test_tx_en: |
1da177e4 LT |
2129 | spin_unlock_irqrestore(&up->port.lock, flags); |
2130 | ||
ad4c2aa6 CM |
2131 | /* |
2132 | * Clear the interrupt registers again for luck, and clear the | |
2133 | * saved flags to avoid getting false values from polling | |
2134 | * routines or the previous session. | |
2135 | */ | |
2136 | serial_inp(up, UART_LSR); | |
2137 | serial_inp(up, UART_RX); | |
2138 | serial_inp(up, UART_IIR); | |
2139 | serial_inp(up, UART_MSR); | |
2140 | up->lsr_saved_flags = 0; | |
2141 | up->msr_saved_flags = 0; | |
2142 | ||
1da177e4 LT |
2143 | /* |
2144 | * Finally, enable interrupts. Note: Modem status interrupts | |
2145 | * are set via set_termios(), which will be occurring imminently | |
2146 | * anyway, so we don't enable them here. | |
2147 | */ | |
2148 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
2149 | serial_outp(up, UART_IER, up->ier); | |
2150 | ||
2151 | if (up->port.flags & UPF_FOURPORT) { | |
2152 | unsigned int icp; | |
2153 | /* | |
2154 | * Enable interrupts on the AST Fourport board | |
2155 | */ | |
2156 | icp = (up->port.iobase & 0xfe0) | 0x01f; | |
2157 | outb_p(0x80, icp); | |
2158 | (void) inb_p(icp); | |
2159 | } | |
2160 | ||
1da177e4 LT |
2161 | return 0; |
2162 | } | |
2163 | ||
2164 | static void serial8250_shutdown(struct uart_port *port) | |
2165 | { | |
2166 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2167 | unsigned long flags; | |
2168 | ||
2169 | /* | |
2170 | * Disable interrupts from this port | |
2171 | */ | |
2172 | up->ier = 0; | |
2173 | serial_outp(up, UART_IER, 0); | |
2174 | ||
2175 | spin_lock_irqsave(&up->port.lock, flags); | |
2176 | if (up->port.flags & UPF_FOURPORT) { | |
2177 | /* reset interrupts on the AST Fourport board */ | |
2178 | inb((up->port.iobase & 0xfe0) | 0x1f); | |
2179 | up->port.mctrl |= TIOCM_OUT1; | |
2180 | } else | |
2181 | up->port.mctrl &= ~TIOCM_OUT2; | |
2182 | ||
2183 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
2184 | spin_unlock_irqrestore(&up->port.lock, flags); | |
2185 | ||
2186 | /* | |
2187 | * Disable break condition and FIFOs | |
2188 | */ | |
2189 | serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); | |
2190 | serial8250_clear_fifos(up); | |
2191 | ||
2192 | #ifdef CONFIG_SERIAL_8250_RSA | |
2193 | /* | |
2194 | * Reset the RSA board back to 115kbps compat mode. | |
2195 | */ | |
2196 | disable_rsa(up); | |
2197 | #endif | |
2198 | ||
2199 | /* | |
2200 | * Read data port to reset things, and then unlink from | |
2201 | * the IRQ chain. | |
2202 | */ | |
2203 | (void) serial_in(up, UART_RX); | |
2204 | ||
40b36daa AW |
2205 | del_timer_sync(&up->timer); |
2206 | up->timer.function = serial8250_timeout; | |
2207 | if (is_real_interrupt(up->port.irq)) | |
1da177e4 LT |
2208 | serial_unlink_irq_chain(up); |
2209 | } | |
2210 | ||
2211 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) | |
2212 | { | |
2213 | unsigned int quot; | |
2214 | ||
2215 | /* | |
2216 | * Handle magic divisors for baud rates above baud_base on | |
2217 | * SMSC SuperIO chips. | |
2218 | */ | |
2219 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2220 | baud == (port->uartclk/4)) | |
2221 | quot = 0x8001; | |
2222 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2223 | baud == (port->uartclk/8)) | |
2224 | quot = 0x8002; | |
2225 | else | |
2226 | quot = uart_get_divisor(port, baud); | |
2227 | ||
2228 | return quot; | |
2229 | } | |
2230 | ||
2231 | static void | |
606d099c AC |
2232 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, |
2233 | struct ktermios *old) | |
1da177e4 LT |
2234 | { |
2235 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2236 | unsigned char cval, fcr = 0; | |
2237 | unsigned long flags; | |
2238 | unsigned int baud, quot; | |
2239 | ||
2240 | switch (termios->c_cflag & CSIZE) { | |
2241 | case CS5: | |
0a8b80c5 | 2242 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
2243 | break; |
2244 | case CS6: | |
0a8b80c5 | 2245 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
2246 | break; |
2247 | case CS7: | |
0a8b80c5 | 2248 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
2249 | break; |
2250 | default: | |
2251 | case CS8: | |
0a8b80c5 | 2252 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
2253 | break; |
2254 | } | |
2255 | ||
2256 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 2257 | cval |= UART_LCR_STOP; |
1da177e4 LT |
2258 | if (termios->c_cflag & PARENB) |
2259 | cval |= UART_LCR_PARITY; | |
2260 | if (!(termios->c_cflag & PARODD)) | |
2261 | cval |= UART_LCR_EPAR; | |
2262 | #ifdef CMSPAR | |
2263 | if (termios->c_cflag & CMSPAR) | |
2264 | cval |= UART_LCR_SPAR; | |
2265 | #endif | |
2266 | ||
2267 | /* | |
2268 | * Ask the core to calculate the divisor for us. | |
2269 | */ | |
24d481ec AV |
2270 | baud = uart_get_baud_rate(port, termios, old, |
2271 | port->uartclk / 16 / 0xffff, | |
2272 | port->uartclk / 16); | |
1da177e4 LT |
2273 | quot = serial8250_get_divisor(port, baud); |
2274 | ||
2275 | /* | |
4ba5e35d | 2276 | * Oxford Semi 952 rev B workaround |
1da177e4 | 2277 | */ |
4ba5e35d | 2278 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
3e8d4e20 | 2279 | quot++; |
1da177e4 LT |
2280 | |
2281 | if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) { | |
2282 | if (baud < 2400) | |
2283 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; | |
2284 | else | |
2285 | fcr = uart_config[up->port.type].fcr; | |
2286 | } | |
2287 | ||
2288 | /* | |
2289 | * MCR-based auto flow control. When AFE is enabled, RTS will be | |
2290 | * deasserted when the receive FIFO contains more characters than | |
2291 | * the trigger, or the MCR RTS bit is cleared. In the case where | |
2292 | * the remote UART is not using CTS auto flow control, we must | |
2293 | * have sufficient FIFO entries for the latency of the remote | |
2294 | * UART to respond. IOW, at least 32 bytes of FIFO. | |
2295 | */ | |
2296 | if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { | |
2297 | up->mcr &= ~UART_MCR_AFE; | |
2298 | if (termios->c_cflag & CRTSCTS) | |
2299 | up->mcr |= UART_MCR_AFE; | |
2300 | } | |
2301 | ||
2302 | /* | |
2303 | * Ok, we're now changing the port state. Do it with | |
2304 | * interrupts disabled. | |
2305 | */ | |
2306 | spin_lock_irqsave(&up->port.lock, flags); | |
2307 | ||
2308 | /* | |
2309 | * Update the per-port timeout. | |
2310 | */ | |
2311 | uart_update_timeout(port, termios->c_cflag, baud); | |
2312 | ||
2313 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
2314 | if (termios->c_iflag & INPCK) | |
2315 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
2316 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
2317 | up->port.read_status_mask |= UART_LSR_BI; | |
2318 | ||
2319 | /* | |
2320 | * Characteres to ignore | |
2321 | */ | |
2322 | up->port.ignore_status_mask = 0; | |
2323 | if (termios->c_iflag & IGNPAR) | |
2324 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
2325 | if (termios->c_iflag & IGNBRK) { | |
2326 | up->port.ignore_status_mask |= UART_LSR_BI; | |
2327 | /* | |
2328 | * If we're ignoring parity and break indicators, | |
2329 | * ignore overruns too (for real raw support). | |
2330 | */ | |
2331 | if (termios->c_iflag & IGNPAR) | |
2332 | up->port.ignore_status_mask |= UART_LSR_OE; | |
2333 | } | |
2334 | ||
2335 | /* | |
2336 | * ignore all characters if CREAD is not set | |
2337 | */ | |
2338 | if ((termios->c_cflag & CREAD) == 0) | |
2339 | up->port.ignore_status_mask |= UART_LSR_DR; | |
2340 | ||
2341 | /* | |
2342 | * CTS flow control flag and modem status interrupts | |
2343 | */ | |
2344 | up->ier &= ~UART_IER_MSI; | |
21c614a7 PA |
2345 | if (!(up->bugs & UART_BUG_NOMSR) && |
2346 | UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
1da177e4 LT |
2347 | up->ier |= UART_IER_MSI; |
2348 | if (up->capabilities & UART_CAP_UUE) | |
2349 | up->ier |= UART_IER_UUE | UART_IER_RTOIE; | |
2350 | ||
2351 | serial_out(up, UART_IER, up->ier); | |
2352 | ||
2353 | if (up->capabilities & UART_CAP_EFR) { | |
2354 | unsigned char efr = 0; | |
2355 | /* | |
2356 | * TI16C752/Startech hardware flow control. FIXME: | |
2357 | * - TI16C752 requires control thresholds to be set. | |
2358 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. | |
2359 | */ | |
2360 | if (termios->c_cflag & CRTSCTS) | |
2361 | efr |= UART_EFR_CTS; | |
2362 | ||
2363 | serial_outp(up, UART_LCR, 0xBF); | |
2364 | serial_outp(up, UART_EFR, efr); | |
2365 | } | |
2366 | ||
f2eda27d | 2367 | #ifdef CONFIG_ARCH_OMAP |
255341c6 | 2368 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ |
5668545a | 2369 | if (cpu_is_omap1510() && is_omap_port(up)) { |
255341c6 JM |
2370 | if (baud == 115200) { |
2371 | quot = 1; | |
2372 | serial_out(up, UART_OMAP_OSC_12M_SEL, 1); | |
2373 | } else | |
2374 | serial_out(up, UART_OMAP_OSC_12M_SEL, 0); | |
2375 | } | |
2376 | #endif | |
2377 | ||
1da177e4 LT |
2378 | if (up->capabilities & UART_NATSEMI) { |
2379 | /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ | |
2380 | serial_outp(up, UART_LCR, 0xe0); | |
2381 | } else { | |
2382 | serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ | |
2383 | } | |
2384 | ||
b32b19b8 | 2385 | serial_dl_write(up, quot); |
1da177e4 LT |
2386 | |
2387 | /* | |
2388 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR | |
2389 | * is written without DLAB set, this mode will be disabled. | |
2390 | */ | |
2391 | if (up->port.type == PORT_16750) | |
2392 | serial_outp(up, UART_FCR, fcr); | |
2393 | ||
2394 | serial_outp(up, UART_LCR, cval); /* reset DLAB */ | |
2395 | up->lcr = cval; /* Save LCR */ | |
2396 | if (up->port.type != PORT_16750) { | |
2397 | if (fcr & UART_FCR_ENABLE_FIFO) { | |
2398 | /* emulated UARTs (Lucent Venus 167x) need two steps */ | |
2399 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
2400 | } | |
2401 | serial_outp(up, UART_FCR, fcr); /* set fcr */ | |
2402 | } | |
2403 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
2404 | spin_unlock_irqrestore(&up->port.lock, flags); | |
e991a2bd AC |
2405 | /* Don't rewrite B0 */ |
2406 | if (tty_termios_baud_rate(termios)) | |
2407 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1da177e4 LT |
2408 | } |
2409 | ||
2410 | static void | |
2411 | serial8250_pm(struct uart_port *port, unsigned int state, | |
2412 | unsigned int oldstate) | |
2413 | { | |
2414 | struct uart_8250_port *p = (struct uart_8250_port *)port; | |
2415 | ||
2416 | serial8250_set_sleep(p, state != 0); | |
2417 | ||
2418 | if (p->pm) | |
2419 | p->pm(port, state, oldstate); | |
2420 | } | |
2421 | ||
f2eda27d RK |
2422 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) |
2423 | { | |
2424 | if (pt->port.iotype == UPIO_AU) | |
b2b13cdf | 2425 | return 0x1000; |
f2eda27d RK |
2426 | #ifdef CONFIG_ARCH_OMAP |
2427 | if (is_omap_port(pt)) | |
2428 | return 0x16 << pt->port.regshift; | |
2429 | #endif | |
2430 | return 8 << pt->port.regshift; | |
2431 | } | |
2432 | ||
1da177e4 LT |
2433 | /* |
2434 | * Resource handling. | |
2435 | */ | |
2436 | static int serial8250_request_std_resource(struct uart_8250_port *up) | |
2437 | { | |
f2eda27d | 2438 | unsigned int size = serial8250_port_size(up); |
1da177e4 LT |
2439 | int ret = 0; |
2440 | ||
2441 | switch (up->port.iotype) { | |
85835f44 | 2442 | case UPIO_AU: |
0b30d668 SS |
2443 | case UPIO_TSI: |
2444 | case UPIO_MEM32: | |
1da177e4 | 2445 | case UPIO_MEM: |
beab697a | 2446 | case UPIO_DWAPB: |
1da177e4 LT |
2447 | if (!up->port.mapbase) |
2448 | break; | |
2449 | ||
2450 | if (!request_mem_region(up->port.mapbase, size, "serial")) { | |
2451 | ret = -EBUSY; | |
2452 | break; | |
2453 | } | |
2454 | ||
2455 | if (up->port.flags & UPF_IOREMAP) { | |
6f441fe9 AC |
2456 | up->port.membase = ioremap_nocache(up->port.mapbase, |
2457 | size); | |
1da177e4 LT |
2458 | if (!up->port.membase) { |
2459 | release_mem_region(up->port.mapbase, size); | |
2460 | ret = -ENOMEM; | |
2461 | } | |
2462 | } | |
2463 | break; | |
2464 | ||
2465 | case UPIO_HUB6: | |
2466 | case UPIO_PORT: | |
2467 | if (!request_region(up->port.iobase, size, "serial")) | |
2468 | ret = -EBUSY; | |
2469 | break; | |
2470 | } | |
2471 | return ret; | |
2472 | } | |
2473 | ||
2474 | static void serial8250_release_std_resource(struct uart_8250_port *up) | |
2475 | { | |
f2eda27d | 2476 | unsigned int size = serial8250_port_size(up); |
1da177e4 LT |
2477 | |
2478 | switch (up->port.iotype) { | |
85835f44 | 2479 | case UPIO_AU: |
0b30d668 SS |
2480 | case UPIO_TSI: |
2481 | case UPIO_MEM32: | |
1da177e4 | 2482 | case UPIO_MEM: |
beab697a | 2483 | case UPIO_DWAPB: |
1da177e4 LT |
2484 | if (!up->port.mapbase) |
2485 | break; | |
2486 | ||
2487 | if (up->port.flags & UPF_IOREMAP) { | |
2488 | iounmap(up->port.membase); | |
2489 | up->port.membase = NULL; | |
2490 | } | |
2491 | ||
2492 | release_mem_region(up->port.mapbase, size); | |
2493 | break; | |
2494 | ||
2495 | case UPIO_HUB6: | |
2496 | case UPIO_PORT: | |
2497 | release_region(up->port.iobase, size); | |
2498 | break; | |
2499 | } | |
2500 | } | |
2501 | ||
2502 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) | |
2503 | { | |
2504 | unsigned long start = UART_RSA_BASE << up->port.regshift; | |
2505 | unsigned int size = 8 << up->port.regshift; | |
0b30d668 | 2506 | int ret = -EINVAL; |
1da177e4 LT |
2507 | |
2508 | switch (up->port.iotype) { | |
1da177e4 LT |
2509 | case UPIO_HUB6: |
2510 | case UPIO_PORT: | |
2511 | start += up->port.iobase; | |
0b30d668 SS |
2512 | if (request_region(start, size, "serial-rsa")) |
2513 | ret = 0; | |
2514 | else | |
1da177e4 LT |
2515 | ret = -EBUSY; |
2516 | break; | |
2517 | } | |
2518 | ||
2519 | return ret; | |
2520 | } | |
2521 | ||
2522 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) | |
2523 | { | |
2524 | unsigned long offset = UART_RSA_BASE << up->port.regshift; | |
2525 | unsigned int size = 8 << up->port.regshift; | |
2526 | ||
2527 | switch (up->port.iotype) { | |
1da177e4 LT |
2528 | case UPIO_HUB6: |
2529 | case UPIO_PORT: | |
2530 | release_region(up->port.iobase + offset, size); | |
2531 | break; | |
2532 | } | |
2533 | } | |
2534 | ||
2535 | static void serial8250_release_port(struct uart_port *port) | |
2536 | { | |
2537 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2538 | ||
2539 | serial8250_release_std_resource(up); | |
2540 | if (up->port.type == PORT_RSA) | |
2541 | serial8250_release_rsa_resource(up); | |
2542 | } | |
2543 | ||
2544 | static int serial8250_request_port(struct uart_port *port) | |
2545 | { | |
2546 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2547 | int ret = 0; | |
2548 | ||
2549 | ret = serial8250_request_std_resource(up); | |
2550 | if (ret == 0 && up->port.type == PORT_RSA) { | |
2551 | ret = serial8250_request_rsa_resource(up); | |
2552 | if (ret < 0) | |
2553 | serial8250_release_std_resource(up); | |
2554 | } | |
2555 | ||
2556 | return ret; | |
2557 | } | |
2558 | ||
2559 | static void serial8250_config_port(struct uart_port *port, int flags) | |
2560 | { | |
2561 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2562 | int probeflags = PROBE_ANY; | |
2563 | int ret; | |
2564 | ||
1da177e4 LT |
2565 | /* |
2566 | * Find the region that we can probe for. This in turn | |
2567 | * tells us whether we can probe for the type of port. | |
2568 | */ | |
2569 | ret = serial8250_request_std_resource(up); | |
2570 | if (ret < 0) | |
2571 | return; | |
2572 | ||
2573 | ret = serial8250_request_rsa_resource(up); | |
2574 | if (ret < 0) | |
2575 | probeflags &= ~PROBE_RSA; | |
2576 | ||
b8e7e40a AC |
2577 | if (up->port.iotype != up->cur_iotype) |
2578 | set_io_from_upio(port); | |
2579 | ||
1da177e4 LT |
2580 | if (flags & UART_CONFIG_TYPE) |
2581 | autoconfig(up, probeflags); | |
b2b13cdf ML |
2582 | |
2583 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |
2584 | /* if access method is AU, it is a 16550 with a quirk */ | |
2585 | if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU) | |
2586 | up->bugs |= UART_BUG_NOMSR; | |
2587 | #endif | |
2588 | ||
1da177e4 LT |
2589 | if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) |
2590 | autoconfig_irq(up); | |
2591 | ||
2592 | if (up->port.type != PORT_RSA && probeflags & PROBE_RSA) | |
2593 | serial8250_release_rsa_resource(up); | |
2594 | if (up->port.type == PORT_UNKNOWN) | |
2595 | serial8250_release_std_resource(up); | |
2596 | } | |
2597 | ||
2598 | static int | |
2599 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2600 | { | |
a62c4133 | 2601 | if (ser->irq >= nr_irqs || ser->irq < 0 || |
1da177e4 LT |
2602 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || |
2603 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || | |
2604 | ser->type == PORT_STARTECH) | |
2605 | return -EINVAL; | |
2606 | return 0; | |
2607 | } | |
2608 | ||
2609 | static const char * | |
2610 | serial8250_type(struct uart_port *port) | |
2611 | { | |
2612 | int type = port->type; | |
2613 | ||
2614 | if (type >= ARRAY_SIZE(uart_config)) | |
2615 | type = 0; | |
2616 | return uart_config[type].name; | |
2617 | } | |
2618 | ||
2619 | static struct uart_ops serial8250_pops = { | |
2620 | .tx_empty = serial8250_tx_empty, | |
2621 | .set_mctrl = serial8250_set_mctrl, | |
2622 | .get_mctrl = serial8250_get_mctrl, | |
2623 | .stop_tx = serial8250_stop_tx, | |
2624 | .start_tx = serial8250_start_tx, | |
2625 | .stop_rx = serial8250_stop_rx, | |
2626 | .enable_ms = serial8250_enable_ms, | |
2627 | .break_ctl = serial8250_break_ctl, | |
2628 | .startup = serial8250_startup, | |
2629 | .shutdown = serial8250_shutdown, | |
2630 | .set_termios = serial8250_set_termios, | |
2631 | .pm = serial8250_pm, | |
2632 | .type = serial8250_type, | |
2633 | .release_port = serial8250_release_port, | |
2634 | .request_port = serial8250_request_port, | |
2635 | .config_port = serial8250_config_port, | |
2636 | .verify_port = serial8250_verify_port, | |
f2d937f3 JW |
2637 | #ifdef CONFIG_CONSOLE_POLL |
2638 | .poll_get_char = serial8250_get_poll_char, | |
2639 | .poll_put_char = serial8250_put_poll_char, | |
2640 | #endif | |
1da177e4 LT |
2641 | }; |
2642 | ||
2643 | static struct uart_8250_port serial8250_ports[UART_NR]; | |
2644 | ||
2645 | static void __init serial8250_isa_init_ports(void) | |
2646 | { | |
2647 | struct uart_8250_port *up; | |
2648 | static int first = 1; | |
4c0ebb80 | 2649 | int i, irqflag = 0; |
1da177e4 LT |
2650 | |
2651 | if (!first) | |
2652 | return; | |
2653 | first = 0; | |
2654 | ||
a61c2d78 | 2655 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2656 | struct uart_8250_port *up = &serial8250_ports[i]; |
2657 | ||
2658 | up->port.line = i; | |
2659 | spin_lock_init(&up->port.lock); | |
2660 | ||
2661 | init_timer(&up->timer); | |
2662 | up->timer.function = serial8250_timeout; | |
2663 | ||
2664 | /* | |
2665 | * ALPHA_KLUDGE_MCR needs to be killed. | |
2666 | */ | |
2667 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | |
2668 | up->mcr_force = ALPHA_KLUDGE_MCR; | |
2669 | ||
2670 | up->port.ops = &serial8250_pops; | |
2671 | } | |
2672 | ||
4c0ebb80 AGR |
2673 | if (share_irqs) |
2674 | irqflag = IRQF_SHARED; | |
2675 | ||
44454bcd | 2676 | for (i = 0, up = serial8250_ports; |
a61c2d78 | 2677 | i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; |
1da177e4 LT |
2678 | i++, up++) { |
2679 | up->port.iobase = old_serial_port[i].port; | |
2680 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); | |
1c2f0493 | 2681 | up->port.irqflags = old_serial_port[i].irqflags; |
1da177e4 LT |
2682 | up->port.uartclk = old_serial_port[i].baud_base * 16; |
2683 | up->port.flags = old_serial_port[i].flags; | |
2684 | up->port.hub6 = old_serial_port[i].hub6; | |
2685 | up->port.membase = old_serial_port[i].iomem_base; | |
2686 | up->port.iotype = old_serial_port[i].io_type; | |
2687 | up->port.regshift = old_serial_port[i].iomem_reg_shift; | |
7d6a07d1 | 2688 | set_io_from_upio(&up->port); |
4c0ebb80 | 2689 | up->port.irqflags |= irqflag; |
1da177e4 LT |
2690 | } |
2691 | } | |
2692 | ||
b5d228cc SL |
2693 | static void |
2694 | serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) | |
2695 | { | |
2696 | up->port.type = type; | |
2697 | up->port.fifosize = uart_config[type].fifo_size; | |
2698 | up->capabilities = uart_config[type].flags; | |
2699 | up->tx_loadsz = uart_config[type].tx_loadsz; | |
2700 | } | |
2701 | ||
1da177e4 LT |
2702 | static void __init |
2703 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) | |
2704 | { | |
2705 | int i; | |
2706 | ||
b8e7e40a AC |
2707 | for (i = 0; i < nr_uarts; i++) { |
2708 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2709 | up->cur_iotype = 0xFF; | |
2710 | } | |
2711 | ||
1da177e4 LT |
2712 | serial8250_isa_init_ports(); |
2713 | ||
a61c2d78 | 2714 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2715 | struct uart_8250_port *up = &serial8250_ports[i]; |
2716 | ||
2717 | up->port.dev = dev; | |
b5d228cc SL |
2718 | |
2719 | if (up->port.flags & UPF_FIXED_TYPE) | |
2720 | serial8250_init_fixed_type_port(up, up->port.type); | |
2721 | ||
1da177e4 LT |
2722 | uart_add_one_port(drv, &up->port); |
2723 | } | |
2724 | } | |
2725 | ||
2726 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
2727 | ||
d358788f RK |
2728 | static void serial8250_console_putchar(struct uart_port *port, int ch) |
2729 | { | |
2730 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2731 | ||
2732 | wait_for_xmitr(up, UART_LSR_THRE); | |
2733 | serial_out(up, UART_TX, ch); | |
2734 | } | |
2735 | ||
1da177e4 LT |
2736 | /* |
2737 | * Print a string to the serial port trying not to disturb | |
2738 | * any possible real use of the port... | |
2739 | * | |
2740 | * The console_lock must be held when we get here. | |
2741 | */ | |
2742 | static void | |
2743 | serial8250_console_write(struct console *co, const char *s, unsigned int count) | |
2744 | { | |
2745 | struct uart_8250_port *up = &serial8250_ports[co->index]; | |
d8a5a8d7 | 2746 | unsigned long flags; |
1da177e4 | 2747 | unsigned int ier; |
d8a5a8d7 | 2748 | int locked = 1; |
1da177e4 | 2749 | |
78512ece AM |
2750 | touch_nmi_watchdog(); |
2751 | ||
68aa2c0d AM |
2752 | local_irq_save(flags); |
2753 | if (up->port.sysrq) { | |
2754 | /* serial8250_handle_port() already took the lock */ | |
2755 | locked = 0; | |
2756 | } else if (oops_in_progress) { | |
2757 | locked = spin_trylock(&up->port.lock); | |
d8a5a8d7 | 2758 | } else |
68aa2c0d | 2759 | spin_lock(&up->port.lock); |
d8a5a8d7 | 2760 | |
1da177e4 | 2761 | /* |
dc7bf130 | 2762 | * First save the IER then disable the interrupts |
1da177e4 LT |
2763 | */ |
2764 | ier = serial_in(up, UART_IER); | |
2765 | ||
2766 | if (up->capabilities & UART_CAP_UUE) | |
2767 | serial_out(up, UART_IER, UART_IER_UUE); | |
2768 | else | |
2769 | serial_out(up, UART_IER, 0); | |
2770 | ||
d358788f | 2771 | uart_console_write(&up->port, s, count, serial8250_console_putchar); |
1da177e4 LT |
2772 | |
2773 | /* | |
2774 | * Finally, wait for transmitter to become empty | |
2775 | * and restore the IER | |
2776 | */ | |
f91a3715 | 2777 | wait_for_xmitr(up, BOTH_EMPTY); |
a88d75b2 | 2778 | serial_out(up, UART_IER, ier); |
d8a5a8d7 | 2779 | |
ad4c2aa6 CM |
2780 | /* |
2781 | * The receive handling will happen properly because the | |
2782 | * receive ready bit will still be set; it is not cleared | |
2783 | * on read. However, modem control will not, we must | |
2784 | * call it if we have saved something in the saved flags | |
2785 | * while processing with interrupts off. | |
2786 | */ | |
2787 | if (up->msr_saved_flags) | |
2788 | check_modem_status(up); | |
2789 | ||
d8a5a8d7 | 2790 | if (locked) |
68aa2c0d AM |
2791 | spin_unlock(&up->port.lock); |
2792 | local_irq_restore(flags); | |
1da177e4 LT |
2793 | } |
2794 | ||
118c0ace | 2795 | static int __init serial8250_console_setup(struct console *co, char *options) |
1da177e4 LT |
2796 | { |
2797 | struct uart_port *port; | |
2798 | int baud = 9600; | |
2799 | int bits = 8; | |
2800 | int parity = 'n'; | |
2801 | int flow = 'n'; | |
2802 | ||
2803 | /* | |
2804 | * Check whether an invalid uart number has been specified, and | |
2805 | * if so, search for the first available port that does have | |
2806 | * console support. | |
2807 | */ | |
a61c2d78 | 2808 | if (co->index >= nr_uarts) |
1da177e4 LT |
2809 | co->index = 0; |
2810 | port = &serial8250_ports[co->index].port; | |
2811 | if (!port->iobase && !port->membase) | |
2812 | return -ENODEV; | |
2813 | ||
2814 | if (options) | |
2815 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2816 | ||
2817 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2818 | } | |
2819 | ||
b6b1d877 | 2820 | static int serial8250_console_early_setup(void) |
18a8bd94 YL |
2821 | { |
2822 | return serial8250_find_port_for_earlycon(); | |
2823 | } | |
2824 | ||
1da177e4 LT |
2825 | static struct console serial8250_console = { |
2826 | .name = "ttyS", | |
2827 | .write = serial8250_console_write, | |
2828 | .device = uart_console_device, | |
2829 | .setup = serial8250_console_setup, | |
18a8bd94 | 2830 | .early_setup = serial8250_console_early_setup, |
1da177e4 LT |
2831 | .flags = CON_PRINTBUFFER, |
2832 | .index = -1, | |
2833 | .data = &serial8250_reg, | |
2834 | }; | |
2835 | ||
2836 | static int __init serial8250_console_init(void) | |
2837 | { | |
05d81d22 EB |
2838 | if (nr_uarts > UART_NR) |
2839 | nr_uarts = UART_NR; | |
2840 | ||
1da177e4 LT |
2841 | serial8250_isa_init_ports(); |
2842 | register_console(&serial8250_console); | |
2843 | return 0; | |
2844 | } | |
2845 | console_initcall(serial8250_console_init); | |
2846 | ||
18a8bd94 | 2847 | int serial8250_find_port(struct uart_port *p) |
1da177e4 LT |
2848 | { |
2849 | int line; | |
2850 | struct uart_port *port; | |
2851 | ||
a61c2d78 | 2852 | for (line = 0; line < nr_uarts; line++) { |
1da177e4 | 2853 | port = &serial8250_ports[line].port; |
50aec3b5 | 2854 | if (uart_match_port(p, port)) |
1da177e4 LT |
2855 | return line; |
2856 | } | |
2857 | return -ENODEV; | |
2858 | } | |
2859 | ||
1da177e4 LT |
2860 | #define SERIAL8250_CONSOLE &serial8250_console |
2861 | #else | |
2862 | #define SERIAL8250_CONSOLE NULL | |
2863 | #endif | |
2864 | ||
2865 | static struct uart_driver serial8250_reg = { | |
2866 | .owner = THIS_MODULE, | |
2867 | .driver_name = "serial", | |
1da177e4 LT |
2868 | .dev_name = "ttyS", |
2869 | .major = TTY_MAJOR, | |
2870 | .minor = 64, | |
1da177e4 LT |
2871 | .cons = SERIAL8250_CONSOLE, |
2872 | }; | |
2873 | ||
d856c666 RK |
2874 | /* |
2875 | * early_serial_setup - early registration for 8250 ports | |
2876 | * | |
2877 | * Setup an 8250 port structure prior to console initialisation. Use | |
2878 | * after console initialisation will cause undefined behaviour. | |
2879 | */ | |
1da177e4 LT |
2880 | int __init early_serial_setup(struct uart_port *port) |
2881 | { | |
b430428a DD |
2882 | struct uart_port *p; |
2883 | ||
1da177e4 LT |
2884 | if (port->line >= ARRAY_SIZE(serial8250_ports)) |
2885 | return -ENODEV; | |
2886 | ||
2887 | serial8250_isa_init_ports(); | |
b430428a DD |
2888 | p = &serial8250_ports[port->line].port; |
2889 | p->iobase = port->iobase; | |
2890 | p->membase = port->membase; | |
2891 | p->irq = port->irq; | |
1c2f0493 | 2892 | p->irqflags = port->irqflags; |
b430428a DD |
2893 | p->uartclk = port->uartclk; |
2894 | p->fifosize = port->fifosize; | |
2895 | p->regshift = port->regshift; | |
2896 | p->iotype = port->iotype; | |
2897 | p->flags = port->flags; | |
2898 | p->mapbase = port->mapbase; | |
2899 | p->private_data = port->private_data; | |
125c97d8 HD |
2900 | p->type = port->type; |
2901 | p->line = port->line; | |
7d6a07d1 DD |
2902 | |
2903 | set_io_from_upio(p); | |
2904 | if (port->serial_in) | |
2905 | p->serial_in = port->serial_in; | |
2906 | if (port->serial_out) | |
2907 | p->serial_out = port->serial_out; | |
2908 | ||
1da177e4 LT |
2909 | return 0; |
2910 | } | |
2911 | ||
2912 | /** | |
2913 | * serial8250_suspend_port - suspend one serial port | |
2914 | * @line: serial line number | |
1da177e4 LT |
2915 | * |
2916 | * Suspend one serial port. | |
2917 | */ | |
2918 | void serial8250_suspend_port(int line) | |
2919 | { | |
2920 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); | |
2921 | } | |
2922 | ||
2923 | /** | |
2924 | * serial8250_resume_port - resume one serial port | |
2925 | * @line: serial line number | |
1da177e4 LT |
2926 | * |
2927 | * Resume one serial port. | |
2928 | */ | |
2929 | void serial8250_resume_port(int line) | |
2930 | { | |
b5b82df6 DW |
2931 | struct uart_8250_port *up = &serial8250_ports[line]; |
2932 | ||
2933 | if (up->capabilities & UART_NATSEMI) { | |
2934 | unsigned char tmp; | |
2935 | ||
2936 | /* Ensure it's still in high speed mode */ | |
2937 | serial_outp(up, UART_LCR, 0xE0); | |
2938 | ||
2939 | tmp = serial_in(up, 0x04); /* EXCR2 */ | |
2940 | tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | |
2941 | tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
2942 | serial_outp(up, 0x04, tmp); | |
2943 | ||
2944 | serial_outp(up, UART_LCR, 0); | |
2945 | } | |
2946 | uart_resume_port(&serial8250_reg, &up->port); | |
1da177e4 LT |
2947 | } |
2948 | ||
2949 | /* | |
2950 | * Register a set of serial devices attached to a platform device. The | |
2951 | * list is terminated with a zero flags entry, which means we expect | |
2952 | * all entries to have at least UPF_BOOT_AUTOCONF set. | |
2953 | */ | |
3ae5eaec | 2954 | static int __devinit serial8250_probe(struct platform_device *dev) |
1da177e4 | 2955 | { |
3ae5eaec | 2956 | struct plat_serial8250_port *p = dev->dev.platform_data; |
1da177e4 | 2957 | struct uart_port port; |
4c0ebb80 | 2958 | int ret, i, irqflag = 0; |
1da177e4 LT |
2959 | |
2960 | memset(&port, 0, sizeof(struct uart_port)); | |
2961 | ||
4c0ebb80 AGR |
2962 | if (share_irqs) |
2963 | irqflag = IRQF_SHARED; | |
2964 | ||
ec9f47cd | 2965 | for (i = 0; p && p->flags != 0; p++, i++) { |
74a19741 WN |
2966 | port.iobase = p->iobase; |
2967 | port.membase = p->membase; | |
2968 | port.irq = p->irq; | |
1c2f0493 | 2969 | port.irqflags = p->irqflags; |
74a19741 WN |
2970 | port.uartclk = p->uartclk; |
2971 | port.regshift = p->regshift; | |
2972 | port.iotype = p->iotype; | |
2973 | port.flags = p->flags; | |
2974 | port.mapbase = p->mapbase; | |
2975 | port.hub6 = p->hub6; | |
2976 | port.private_data = p->private_data; | |
8e23fcc8 | 2977 | port.type = p->type; |
7d6a07d1 DD |
2978 | port.serial_in = p->serial_in; |
2979 | port.serial_out = p->serial_out; | |
74a19741 | 2980 | port.dev = &dev->dev; |
4c0ebb80 | 2981 | port.irqflags |= irqflag; |
ec9f47cd RK |
2982 | ret = serial8250_register_port(&port); |
2983 | if (ret < 0) { | |
3ae5eaec | 2984 | dev_err(&dev->dev, "unable to register port at index %d " |
4f640efb JB |
2985 | "(IO%lx MEM%llx IRQ%d): %d\n", i, |
2986 | p->iobase, (unsigned long long)p->mapbase, | |
2987 | p->irq, ret); | |
ec9f47cd | 2988 | } |
1da177e4 LT |
2989 | } |
2990 | return 0; | |
2991 | } | |
2992 | ||
2993 | /* | |
2994 | * Remove serial ports registered against a platform device. | |
2995 | */ | |
3ae5eaec | 2996 | static int __devexit serial8250_remove(struct platform_device *dev) |
1da177e4 LT |
2997 | { |
2998 | int i; | |
2999 | ||
a61c2d78 | 3000 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
3001 | struct uart_8250_port *up = &serial8250_ports[i]; |
3002 | ||
3ae5eaec | 3003 | if (up->port.dev == &dev->dev) |
1da177e4 LT |
3004 | serial8250_unregister_port(i); |
3005 | } | |
3006 | return 0; | |
3007 | } | |
3008 | ||
3ae5eaec | 3009 | static int serial8250_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 LT |
3010 | { |
3011 | int i; | |
3012 | ||
1da177e4 LT |
3013 | for (i = 0; i < UART_NR; i++) { |
3014 | struct uart_8250_port *up = &serial8250_ports[i]; | |
3015 | ||
3ae5eaec | 3016 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
1da177e4 LT |
3017 | uart_suspend_port(&serial8250_reg, &up->port); |
3018 | } | |
3019 | ||
3020 | return 0; | |
3021 | } | |
3022 | ||
3ae5eaec | 3023 | static int serial8250_resume(struct platform_device *dev) |
1da177e4 LT |
3024 | { |
3025 | int i; | |
3026 | ||
1da177e4 LT |
3027 | for (i = 0; i < UART_NR; i++) { |
3028 | struct uart_8250_port *up = &serial8250_ports[i]; | |
3029 | ||
3ae5eaec | 3030 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
b5b82df6 | 3031 | serial8250_resume_port(i); |
1da177e4 LT |
3032 | } |
3033 | ||
3034 | return 0; | |
3035 | } | |
3036 | ||
3ae5eaec | 3037 | static struct platform_driver serial8250_isa_driver = { |
1da177e4 LT |
3038 | .probe = serial8250_probe, |
3039 | .remove = __devexit_p(serial8250_remove), | |
3040 | .suspend = serial8250_suspend, | |
3041 | .resume = serial8250_resume, | |
3ae5eaec RK |
3042 | .driver = { |
3043 | .name = "serial8250", | |
7493a314 | 3044 | .owner = THIS_MODULE, |
3ae5eaec | 3045 | }, |
1da177e4 LT |
3046 | }; |
3047 | ||
3048 | /* | |
3049 | * This "device" covers _all_ ISA 8250-compatible serial devices listed | |
3050 | * in the table in include/asm/serial.h | |
3051 | */ | |
3052 | static struct platform_device *serial8250_isa_devs; | |
3053 | ||
3054 | /* | |
3055 | * serial8250_register_port and serial8250_unregister_port allows for | |
3056 | * 16x50 serial ports to be configured at run-time, to support PCMCIA | |
3057 | * modems and PCI multiport cards. | |
3058 | */ | |
f392ecfa | 3059 | static DEFINE_MUTEX(serial_mutex); |
1da177e4 LT |
3060 | |
3061 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) | |
3062 | { | |
3063 | int i; | |
3064 | ||
3065 | /* | |
3066 | * First, find a port entry which matches. | |
3067 | */ | |
a61c2d78 | 3068 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3069 | if (uart_match_port(&serial8250_ports[i].port, port)) |
3070 | return &serial8250_ports[i]; | |
3071 | ||
3072 | /* | |
3073 | * We didn't find a matching entry, so look for the first | |
3074 | * free entry. We look for one which hasn't been previously | |
3075 | * used (indicated by zero iobase). | |
3076 | */ | |
a61c2d78 | 3077 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3078 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && |
3079 | serial8250_ports[i].port.iobase == 0) | |
3080 | return &serial8250_ports[i]; | |
3081 | ||
3082 | /* | |
3083 | * That also failed. Last resort is to find any entry which | |
3084 | * doesn't have a real port associated with it. | |
3085 | */ | |
a61c2d78 | 3086 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3087 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) |
3088 | return &serial8250_ports[i]; | |
3089 | ||
3090 | return NULL; | |
3091 | } | |
3092 | ||
3093 | /** | |
3094 | * serial8250_register_port - register a serial port | |
3095 | * @port: serial port template | |
3096 | * | |
3097 | * Configure the serial port specified by the request. If the | |
3098 | * port exists and is in use, it is hung up and unregistered | |
3099 | * first. | |
3100 | * | |
3101 | * The port is then probed and if necessary the IRQ is autodetected | |
3102 | * If this fails an error is returned. | |
3103 | * | |
3104 | * On success the port is ready to use and the line number is returned. | |
3105 | */ | |
3106 | int serial8250_register_port(struct uart_port *port) | |
3107 | { | |
3108 | struct uart_8250_port *uart; | |
3109 | int ret = -ENOSPC; | |
3110 | ||
3111 | if (port->uartclk == 0) | |
3112 | return -EINVAL; | |
3113 | ||
f392ecfa | 3114 | mutex_lock(&serial_mutex); |
1da177e4 LT |
3115 | |
3116 | uart = serial8250_find_match_or_unused(port); | |
3117 | if (uart) { | |
3118 | uart_remove_one_port(&serial8250_reg, &uart->port); | |
3119 | ||
74a19741 WN |
3120 | uart->port.iobase = port->iobase; |
3121 | uart->port.membase = port->membase; | |
3122 | uart->port.irq = port->irq; | |
1c2f0493 | 3123 | uart->port.irqflags = port->irqflags; |
74a19741 WN |
3124 | uart->port.uartclk = port->uartclk; |
3125 | uart->port.fifosize = port->fifosize; | |
3126 | uart->port.regshift = port->regshift; | |
3127 | uart->port.iotype = port->iotype; | |
3128 | uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; | |
3129 | uart->port.mapbase = port->mapbase; | |
3130 | uart->port.private_data = port->private_data; | |
1da177e4 LT |
3131 | if (port->dev) |
3132 | uart->port.dev = port->dev; | |
8e23fcc8 | 3133 | |
b5d228cc SL |
3134 | if (port->flags & UPF_FIXED_TYPE) |
3135 | serial8250_init_fixed_type_port(uart, port->type); | |
8e23fcc8 | 3136 | |
7d6a07d1 DD |
3137 | set_io_from_upio(&uart->port); |
3138 | /* Possibly override default I/O functions. */ | |
3139 | if (port->serial_in) | |
3140 | uart->port.serial_in = port->serial_in; | |
3141 | if (port->serial_out) | |
3142 | uart->port.serial_out = port->serial_out; | |
1da177e4 LT |
3143 | |
3144 | ret = uart_add_one_port(&serial8250_reg, &uart->port); | |
3145 | if (ret == 0) | |
3146 | ret = uart->port.line; | |
3147 | } | |
f392ecfa | 3148 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
3149 | |
3150 | return ret; | |
3151 | } | |
3152 | EXPORT_SYMBOL(serial8250_register_port); | |
3153 | ||
3154 | /** | |
3155 | * serial8250_unregister_port - remove a 16x50 serial port at runtime | |
3156 | * @line: serial line number | |
3157 | * | |
3158 | * Remove one serial port. This may not be called from interrupt | |
3159 | * context. We hand the port back to the our control. | |
3160 | */ | |
3161 | void serial8250_unregister_port(int line) | |
3162 | { | |
3163 | struct uart_8250_port *uart = &serial8250_ports[line]; | |
3164 | ||
f392ecfa | 3165 | mutex_lock(&serial_mutex); |
1da177e4 LT |
3166 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3167 | if (serial8250_isa_devs) { | |
3168 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; | |
3169 | uart->port.type = PORT_UNKNOWN; | |
3170 | uart->port.dev = &serial8250_isa_devs->dev; | |
3171 | uart_add_one_port(&serial8250_reg, &uart->port); | |
3172 | } else { | |
3173 | uart->port.dev = NULL; | |
3174 | } | |
f392ecfa | 3175 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
3176 | } |
3177 | EXPORT_SYMBOL(serial8250_unregister_port); | |
3178 | ||
3179 | static int __init serial8250_init(void) | |
3180 | { | |
25db8ad5 | 3181 | int ret; |
1da177e4 | 3182 | |
a61c2d78 DJ |
3183 | if (nr_uarts > UART_NR) |
3184 | nr_uarts = UART_NR; | |
3185 | ||
f1fb9bb8 | 3186 | printk(KERN_INFO "Serial: 8250/16550 driver, " |
a61c2d78 | 3187 | "%d ports, IRQ sharing %sabled\n", nr_uarts, |
1da177e4 LT |
3188 | share_irqs ? "en" : "dis"); |
3189 | ||
b70ac771 DM |
3190 | #ifdef CONFIG_SPARC |
3191 | ret = sunserial_register_minors(&serial8250_reg, UART_NR); | |
3192 | #else | |
3193 | serial8250_reg.nr = UART_NR; | |
1da177e4 | 3194 | ret = uart_register_driver(&serial8250_reg); |
b70ac771 | 3195 | #endif |
1da177e4 LT |
3196 | if (ret) |
3197 | goto out; | |
3198 | ||
7493a314 DT |
3199 | serial8250_isa_devs = platform_device_alloc("serial8250", |
3200 | PLAT8250_DEV_LEGACY); | |
3201 | if (!serial8250_isa_devs) { | |
3202 | ret = -ENOMEM; | |
bc965a7f | 3203 | goto unreg_uart_drv; |
1da177e4 LT |
3204 | } |
3205 | ||
7493a314 DT |
3206 | ret = platform_device_add(serial8250_isa_devs); |
3207 | if (ret) | |
3208 | goto put_dev; | |
3209 | ||
1da177e4 LT |
3210 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); |
3211 | ||
bc965a7f RK |
3212 | ret = platform_driver_register(&serial8250_isa_driver); |
3213 | if (ret == 0) | |
3214 | goto out; | |
1da177e4 | 3215 | |
bc965a7f | 3216 | platform_device_del(serial8250_isa_devs); |
25db8ad5 | 3217 | put_dev: |
7493a314 | 3218 | platform_device_put(serial8250_isa_devs); |
25db8ad5 | 3219 | unreg_uart_drv: |
b70ac771 DM |
3220 | #ifdef CONFIG_SPARC |
3221 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3222 | #else | |
1da177e4 | 3223 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3224 | #endif |
25db8ad5 | 3225 | out: |
1da177e4 LT |
3226 | return ret; |
3227 | } | |
3228 | ||
3229 | static void __exit serial8250_exit(void) | |
3230 | { | |
3231 | struct platform_device *isa_dev = serial8250_isa_devs; | |
3232 | ||
3233 | /* | |
3234 | * This tells serial8250_unregister_port() not to re-register | |
3235 | * the ports (thereby making serial8250_isa_driver permanently | |
3236 | * in use.) | |
3237 | */ | |
3238 | serial8250_isa_devs = NULL; | |
3239 | ||
3ae5eaec | 3240 | platform_driver_unregister(&serial8250_isa_driver); |
1da177e4 LT |
3241 | platform_device_unregister(isa_dev); |
3242 | ||
b70ac771 DM |
3243 | #ifdef CONFIG_SPARC |
3244 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3245 | #else | |
1da177e4 | 3246 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3247 | #endif |
1da177e4 LT |
3248 | } |
3249 | ||
3250 | module_init(serial8250_init); | |
3251 | module_exit(serial8250_exit); | |
3252 | ||
3253 | EXPORT_SYMBOL(serial8250_suspend_port); | |
3254 | EXPORT_SYMBOL(serial8250_resume_port); | |
3255 | ||
3256 | MODULE_LICENSE("GPL"); | |
d87a6d95 | 3257 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); |
1da177e4 LT |
3258 | |
3259 | module_param(share_irqs, uint, 0644); | |
3260 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" | |
3261 | " (unsafe)"); | |
3262 | ||
a61c2d78 DJ |
3263 | module_param(nr_uarts, uint, 0644); |
3264 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); | |
3265 | ||
d41a4b51 CE |
3266 | module_param(skip_txen_test, uint, 0644); |
3267 | MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); | |
3268 | ||
1da177e4 LT |
3269 | #ifdef CONFIG_SERIAL_8250_RSA |
3270 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); | |
3271 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); | |
3272 | #endif | |
3273 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); |