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[ARM] 3181/1: add PORT_ identifier for Hilscher netx uart
[mirror_ubuntu-artful-kernel.git] / drivers / serial / 8250.c
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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
d052d1be 36#include <linux/platform_device.h>
1da177e4
LT		 37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
78512ece 43#include <linux/nmi.h>
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
52 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4
LT		 56
57/*
58 * Debugging.
59 */
60#if 0
61#define DEBUG_AUTOCONF(fmt...) printk(fmt)
62#else
63#define DEBUG_AUTOCONF(fmt...) do { } while (0)
64#endif
65
66#if 0
67#define DEBUG_INTR(fmt...) printk(fmt)
68#else
69#define DEBUG_INTR(fmt...) do { } while (0)
70#endif
71
72#define PASS_LIMIT 256
73
74/*
75 * We default to IRQ0 for the "no irq" hack. Some
76 * machine types want others as well - they're free
77 * to redefine this in their header file.
78 */
79#define is_real_interrupt(irq) ((irq) != 0)
80
1da177e4
LT		 81#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
82#define CONFIG_SERIAL_DETECT_IRQ 1
83#endif
1da177e4
LT		 84#ifdef CONFIG_SERIAL_8250_MANY_PORTS
85#define CONFIG_SERIAL_MANY_PORTS 1
86#endif
87
88/*
89 * HUB6 is always on. This will be removed once the header
90 * files have been cleaned.
91 */
92#define CONFIG_HUB6 1
93
94#include <asm/serial.h>
95
96/*
97 * SERIAL_PORT_DFNS tells us about built-in ports that have no
98 * standard enumeration mechanism. Platforms that can find all
99 * serial ports via mechanisms like ACPI or PCI need not supply it.
100 */
101#ifndef SERIAL_PORT_DFNS
102#define SERIAL_PORT_DFNS
103#endif
104
105static struct old_serial_port old_serial_port[] = {
106 SERIAL_PORT_DFNS /* defined in asm/serial.h */
107};
108
026d02a2 109#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 110
111#ifdef CONFIG_SERIAL_8250_RSA
112
113#define PORT_RSA_MAX 4
114static unsigned long probe_rsa[PORT_RSA_MAX];
115static unsigned int probe_rsa_count;
116#endif /* CONFIG_SERIAL_8250_RSA */
117
118struct uart_8250_port {
119 struct uart_port port;
120 struct timer_list timer; /* "no irq" timer */
121 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 122 unsigned short capabilities; /* port capabilities */
123 unsigned short bugs; /* port bugs */
1da177e4 124 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 125 unsigned char acr;
126 unsigned char ier;
127 unsigned char lcr;
128 unsigned char mcr;
129 unsigned char mcr_mask; /* mask of user bits */
130 unsigned char mcr_force; /* mask of forced bits */
131 unsigned char lsr_break_flag;
132
133 /*
134 * We provide a per-port pm hook.
135 */
136 void (*pm)(struct uart_port *port,
137 unsigned int state, unsigned int old);
138};
139
140struct irq_info {
141 spinlock_t lock;
142 struct list_head *head;
143};
144
145static struct irq_info irq_lists[NR_IRQS];
146
147/*
148 * Here we define the default xmit fifo size used for each type of UART.
149 */
150static const struct serial8250_config uart_config[] = {
151 [PORT_UNKNOWN] = {
152 .name = "unknown",
153 .fifo_size = 1,
154 .tx_loadsz = 1,
155 },
156 [PORT_8250] = {
157 .name = "8250",
158 .fifo_size = 1,
159 .tx_loadsz = 1,
160 },
161 [PORT_16450] = {
162 .name = "16450",
163 .fifo_size = 1,
164 .tx_loadsz = 1,
165 },
166 [PORT_16550] = {
167 .name = "16550",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16550A] = {
172 .name = "16550A",
173 .fifo_size = 16,
174 .tx_loadsz = 16,
175 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
176 .flags = UART_CAP_FIFO,
177 },
178 [PORT_CIRRUS] = {
179 .name = "Cirrus",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16650] = {
184 .name = "ST16650",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
188 },
189 [PORT_16650V2] = {
190 .name = "ST16650V2",
191 .fifo_size = 32,
192 .tx_loadsz = 16,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 UART_FCR_T_TRIG_00,
195 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
196 },
197 [PORT_16750] = {
198 .name = "TI16750",
199 .fifo_size = 64,
200 .tx_loadsz = 64,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
202 UART_FCR7_64BYTE,
203 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
204 },
205 [PORT_STARTECH] = {
206 .name = "Startech",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 },
210 [PORT_16C950] = {
211 .name = "16C950/954",
212 .fifo_size = 128,
213 .tx_loadsz = 128,
214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
215 .flags = UART_CAP_FIFO,
216 },
217 [PORT_16654] = {
218 .name = "ST16654",
219 .fifo_size = 64,
220 .tx_loadsz = 32,
221 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
222 UART_FCR_T_TRIG_10,
223 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
224 },
225 [PORT_16850] = {
226 .name = "XR16850",
227 .fifo_size = 128,
228 .tx_loadsz = 128,
229 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
230 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
231 },
232 [PORT_RSA] = {
233 .name = "RSA",
234 .fifo_size = 2048,
235 .tx_loadsz = 2048,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
237 .flags = UART_CAP_FIFO,
238 },
239 [PORT_NS16550A] = {
240 .name = "NS16550A",
241 .fifo_size = 16,
242 .tx_loadsz = 16,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_NATSEMI,
245 },
246 [PORT_XSCALE] = {
247 .name = "XScale",
248 .fifo_size = 32,
249 .tx_loadsz = 32,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_UUE,
252 },
253};
254
21c614a7
PA		 255#ifdef CONFIG_SERIAL_8250_AU1X00
256
257/* Au1x00 UART hardware has a weird register layout */
258static const u8 au_io_in_map[] = {
259 [UART_RX] = 0,
260 [UART_IER] = 2,
261 [UART_IIR] = 3,
262 [UART_LCR] = 5,
263 [UART_MCR] = 6,
264 [UART_LSR] = 7,
265 [UART_MSR] = 8,
266};
267
268static const u8 au_io_out_map[] = {
269 [UART_TX] = 1,
270 [UART_IER] = 2,
271 [UART_FCR] = 4,
272 [UART_LCR] = 5,
273 [UART_MCR] = 6,
274};
275
276/* sane hardware needs no mapping */
277static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
278{
279 if (up->port.iotype != UPIO_AU)
280 return offset;
281 return au_io_in_map[offset];
282}
283
284static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
285{
286 if (up->port.iotype != UPIO_AU)
287 return offset;
288 return au_io_out_map[offset];
289}
290
291#else
292
293/* sane hardware needs no mapping */
294#define map_8250_in_reg(up, offset) (offset)
295#define map_8250_out_reg(up, offset) (offset)
296
297#endif
298
1da177e4
LT		 299static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
300{
21c614a7 301 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 302
303 switch (up->port.iotype) {
304 case UPIO_HUB6:
305 outb(up->port.hub6 - 1 + offset, up->port.iobase);
306 return inb(up->port.iobase + 1);
307
308 case UPIO_MEM:
309 return readb(up->port.membase + offset);
310
311 case UPIO_MEM32:
312 return readl(up->port.membase + offset);
313
21c614a7
PA		 314#ifdef CONFIG_SERIAL_8250_AU1X00
315 case UPIO_AU:
316 return __raw_readl(up->port.membase + offset);
317#endif
318
1da177e4
LT		 319 default:
320 return inb(up->port.iobase + offset);
321 }
322}
323
324static _INLINE_ void
325serial_out(struct uart_8250_port *up, int offset, int value)
326{
21c614a7 327 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 328
329 switch (up->port.iotype) {
330 case UPIO_HUB6:
331 outb(up->port.hub6 - 1 + offset, up->port.iobase);
332 outb(value, up->port.iobase + 1);
333 break;
334
335 case UPIO_MEM:
336 writeb(value, up->port.membase + offset);
337 break;
338
339 case UPIO_MEM32:
340 writel(value, up->port.membase + offset);
341 break;
342
21c614a7
PA		 343#ifdef CONFIG_SERIAL_8250_AU1X00
344 case UPIO_AU:
345 __raw_writel(value, up->port.membase + offset);
346 break;
347#endif
348
1da177e4
LT		 349 default:
350 outb(value, up->port.iobase + offset);
351 }
352}
353
354/*
355 * We used to support using pause I/O for certain machines. We
356 * haven't supported this for a while, but just in case it's badly
357 * needed for certain old 386 machines, I've left these #define's
358 * in....
359 */
360#define serial_inp(up, offset) serial_in(up, offset)
361#define serial_outp(up, offset, value) serial_out(up, offset, value)
362
363
364/*
365 * For the 16C950
366 */
367static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
368{
369 serial_out(up, UART_SCR, offset);
370 serial_out(up, UART_ICR, value);
371}
372
373static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
374{
375 unsigned int value;
376
377 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
378 serial_out(up, UART_SCR, offset);
379 value = serial_in(up, UART_ICR);
380 serial_icr_write(up, UART_ACR, up->acr);
381
382 return value;
383}
384
385/*
386 * FIFO support.
387 */
388static inline void serial8250_clear_fifos(struct uart_8250_port *p)
389{
390 if (p->capabilities & UART_CAP_FIFO) {
391 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
392 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
393 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
394 serial_outp(p, UART_FCR, 0);
395 }
396}
397
398/*
399 * IER sleep support. UARTs which have EFRs need the "extended
400 * capability" bit enabled. Note that on XR16C850s, we need to
401 * reset LCR to write to IER.
402 */
403static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
404{
405 if (p->capabilities & UART_CAP_SLEEP) {
406 if (p->capabilities & UART_CAP_EFR) {
407 serial_outp(p, UART_LCR, 0xBF);
408 serial_outp(p, UART_EFR, UART_EFR_ECB);
409 serial_outp(p, UART_LCR, 0);
410 }
411 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
412 if (p->capabilities & UART_CAP_EFR) {
413 serial_outp(p, UART_LCR, 0xBF);
414 serial_outp(p, UART_EFR, 0);
415 serial_outp(p, UART_LCR, 0);
416 }
417 }
418}
419
420#ifdef CONFIG_SERIAL_8250_RSA
421/*
422 * Attempts to turn on the RSA FIFO. Returns zero on failure.
423 * We set the port uart clock rate if we succeed.
424 */
425static int __enable_rsa(struct uart_8250_port *up)
426{
427 unsigned char mode;
428 int result;
429
430 mode = serial_inp(up, UART_RSA_MSR);
431 result = mode & UART_RSA_MSR_FIFO;
432
433 if (!result) {
434 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
435 mode = serial_inp(up, UART_RSA_MSR);
436 result = mode & UART_RSA_MSR_FIFO;
437 }
438
439 if (result)
440 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
441
442 return result;
443}
444
445static void enable_rsa(struct uart_8250_port *up)
446{
447 if (up->port.type == PORT_RSA) {
448 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
449 spin_lock_irq(&up->port.lock);
450 __enable_rsa(up);
451 spin_unlock_irq(&up->port.lock);
452 }
453 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
454 serial_outp(up, UART_RSA_FRR, 0);
455 }
456}
457
458/*
459 * Attempts to turn off the RSA FIFO. Returns zero on failure.
460 * It is unknown why interrupts were disabled in here. However,
461 * the caller is expected to preserve this behaviour by grabbing
462 * the spinlock before calling this function.
463 */
464static void disable_rsa(struct uart_8250_port *up)
465{
466 unsigned char mode;
467 int result;
468
469 if (up->port.type == PORT_RSA &&
470 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
471 spin_lock_irq(&up->port.lock);
472
473 mode = serial_inp(up, UART_RSA_MSR);
474 result = !(mode & UART_RSA_MSR_FIFO);
475
476 if (!result) {
477 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
478 mode = serial_inp(up, UART_RSA_MSR);
479 result = !(mode & UART_RSA_MSR_FIFO);
480 }
481
482 if (result)
483 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
484 spin_unlock_irq(&up->port.lock);
485 }
486}
487#endif /* CONFIG_SERIAL_8250_RSA */
488
489/*
490 * This is a quickie test to see how big the FIFO is.
491 * It doesn't work at all the time, more's the pity.
492 */
493static int size_fifo(struct uart_8250_port *up)
494{
495 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
496 int count;
497
498 old_lcr = serial_inp(up, UART_LCR);
499 serial_outp(up, UART_LCR, 0);
500 old_fcr = serial_inp(up, UART_FCR);
501 old_mcr = serial_inp(up, UART_MCR);
502 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
503 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
504 serial_outp(up, UART_MCR, UART_MCR_LOOP);
505 serial_outp(up, UART_LCR, UART_LCR_DLAB);
506 old_dll = serial_inp(up, UART_DLL);
507 old_dlm = serial_inp(up, UART_DLM);
508 serial_outp(up, UART_DLL, 0x01);
509 serial_outp(up, UART_DLM, 0x00);
510 serial_outp(up, UART_LCR, 0x03);
511 for (count = 0; count < 256; count++)
512 serial_outp(up, UART_TX, count);
513 mdelay(20);/* FIXME - schedule_timeout */
514 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
515 (count < 256); count++)
516 serial_inp(up, UART_RX);
517 serial_outp(up, UART_FCR, old_fcr);
518 serial_outp(up, UART_MCR, old_mcr);
519 serial_outp(up, UART_LCR, UART_LCR_DLAB);
520 serial_outp(up, UART_DLL, old_dll);
521 serial_outp(up, UART_DLM, old_dlm);
522 serial_outp(up, UART_LCR, old_lcr);
523
524 return count;
525}
526
527/*
528 * Read UART ID using the divisor method - set DLL and DLM to zero
529 * and the revision will be in DLL and device type in DLM. We
530 * preserve the device state across this.
531 */
532static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
533{
534 unsigned char old_dll, old_dlm, old_lcr;
535 unsigned int id;
536
537 old_lcr = serial_inp(p, UART_LCR);
538 serial_outp(p, UART_LCR, UART_LCR_DLAB);
539
540 old_dll = serial_inp(p, UART_DLL);
541 old_dlm = serial_inp(p, UART_DLM);
542
543 serial_outp(p, UART_DLL, 0);
544 serial_outp(p, UART_DLM, 0);
545
546 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
547
548 serial_outp(p, UART_DLL, old_dll);
549 serial_outp(p, UART_DLM, old_dlm);
550 serial_outp(p, UART_LCR, old_lcr);
551
552 return id;
553}
554
555/*
556 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
557 * When this function is called we know it is at least a StarTech
558 * 16650 V2, but it might be one of several StarTech UARTs, or one of
559 * its clones. (We treat the broken original StarTech 16650 V1 as a
560 * 16550, and why not? Startech doesn't seem to even acknowledge its
561 * existence.)
562 *
563 * What evil have men's minds wrought...
564 */
565static void autoconfig_has_efr(struct uart_8250_port *up)
566{
567 unsigned int id1, id2, id3, rev;
568
569 /*
570 * Everything with an EFR has SLEEP
571 */
572 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
573
574 /*
575 * First we check to see if it's an Oxford Semiconductor UART.
576 *
577 * If we have to do this here because some non-National
578 * Semiconductor clone chips lock up if you try writing to the
579 * LSR register (which serial_icr_read does)
580 */
581
582 /*
583 * Check for Oxford Semiconductor 16C950.
584 *
585 * EFR [4] must be set else this test fails.
586 *
587 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
588 * claims that it's needed for 952 dual UART's (which are not
589 * recommended for new designs).
590 */
591 up->acr = 0;
592 serial_out(up, UART_LCR, 0xBF);
593 serial_out(up, UART_EFR, UART_EFR_ECB);
594 serial_out(up, UART_LCR, 0x00);
595 id1 = serial_icr_read(up, UART_ID1);
596 id2 = serial_icr_read(up, UART_ID2);
597 id3 = serial_icr_read(up, UART_ID3);
598 rev = serial_icr_read(up, UART_REV);
599
600 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
601
602 if (id1 == 0x16 && id2 == 0xC9 &&
603 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
604 up->port.type = PORT_16C950;
4ba5e35d
RK		 605
606 /*
607 * Enable work around for the Oxford Semiconductor 952 rev B
608 * chip which causes it to seriously miscalculate baud rates
609 * when DLL is 0.
610 */
611 if (id3 == 0x52 && rev == 0x01)
612 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 613 return;
614 }
615
616 /*
617 * We check for a XR16C850 by setting DLL and DLM to 0, and then
618 * reading back DLL and DLM. The chip type depends on the DLM
619 * value read back:
620 * 0x10 - XR16C850 and the DLL contains the chip revision.
621 * 0x12 - XR16C2850.
622 * 0x14 - XR16C854.
623 */
624 id1 = autoconfig_read_divisor_id(up);
625 DEBUG_AUTOCONF("850id=%04x ", id1);
626
627 id2 = id1 >> 8;
628 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 629 up->port.type = PORT_16850;
630 return;
631 }
632
633 /*
634 * It wasn't an XR16C850.
635 *
636 * We distinguish between the '654 and the '650 by counting
637 * how many bytes are in the FIFO. I'm using this for now,
638 * since that's the technique that was sent to me in the
639 * serial driver update, but I'm not convinced this works.
640 * I've had problems doing this in the past. -TYT
641 */
642 if (size_fifo(up) == 64)
643 up->port.type = PORT_16654;
644 else
645 up->port.type = PORT_16650V2;
646}
647
648/*
649 * We detected a chip without a FIFO. Only two fall into
650 * this category - the original 8250 and the 16450. The
651 * 16450 has a scratch register (accessible with LCR=0)
652 */
653static void autoconfig_8250(struct uart_8250_port *up)
654{
655 unsigned char scratch, status1, status2;
656
657 up->port.type = PORT_8250;
658
659 scratch = serial_in(up, UART_SCR);
660 serial_outp(up, UART_SCR, 0xa5);
661 status1 = serial_in(up, UART_SCR);
662 serial_outp(up, UART_SCR, 0x5a);
663 status2 = serial_in(up, UART_SCR);
664 serial_outp(up, UART_SCR, scratch);
665
666 if (status1 == 0xa5 && status2 == 0x5a)
667 up->port.type = PORT_16450;
668}
669
670static int broken_efr(struct uart_8250_port *up)
671{
672 /*
673 * Exar ST16C2550 "A2" devices incorrectly detect as
674 * having an EFR, and report an ID of 0x0201. See
675 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
676 */
677 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
678 return 1;
679
680 return 0;
681}
682
683/*
684 * We know that the chip has FIFOs. Does it have an EFR? The
685 * EFR is located in the same register position as the IIR and
686 * we know the top two bits of the IIR are currently set. The
687 * EFR should contain zero. Try to read the EFR.
688 */
689static void autoconfig_16550a(struct uart_8250_port *up)
690{
691 unsigned char status1, status2;
692 unsigned int iersave;
693
694 up->port.type = PORT_16550A;
695 up->capabilities |= UART_CAP_FIFO;
696
697 /*
698 * Check for presence of the EFR when DLAB is set.
699 * Only ST16C650V1 UARTs pass this test.
700 */
701 serial_outp(up, UART_LCR, UART_LCR_DLAB);
702 if (serial_in(up, UART_EFR) == 0) {
703 serial_outp(up, UART_EFR, 0xA8);
704 if (serial_in(up, UART_EFR) != 0) {
705 DEBUG_AUTOCONF("EFRv1 ");
706 up->port.type = PORT_16650;
707 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
708 } else {
709 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
710 }
711 serial_outp(up, UART_EFR, 0);
712 return;
713 }
714
715 /*
716 * Maybe it requires 0xbf to be written to the LCR.
717 * (other ST16C650V2 UARTs, TI16C752A, etc)
718 */
719 serial_outp(up, UART_LCR, 0xBF);
720 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
721 DEBUG_AUTOCONF("EFRv2 ");
722 autoconfig_has_efr(up);
723 return;
724 }
725
726 /*
727 * Check for a National Semiconductor SuperIO chip.
728 * Attempt to switch to bank 2, read the value of the LOOP bit
729 * from EXCR1. Switch back to bank 0, change it in MCR. Then
730 * switch back to bank 2, read it from EXCR1 again and check
731 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 732 */
733 serial_outp(up, UART_LCR, 0);
734 status1 = serial_in(up, UART_MCR);
735 serial_outp(up, UART_LCR, 0xE0);
736 status2 = serial_in(up, 0x02); /* EXCR1 */
737
738 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
739 serial_outp(up, UART_LCR, 0);
740 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
741 serial_outp(up, UART_LCR, 0xE0);
742 status2 = serial_in(up, 0x02); /* EXCR1 */
743 serial_outp(up, UART_LCR, 0);
744 serial_outp(up, UART_MCR, status1);
745
746 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 747 unsigned short quot;
748
1da177e4 749 serial_outp(up, UART_LCR, 0xE0);
857dde2e
DW		 750
751 quot = serial_inp(up, UART_DLM) << 8;
752 quot += serial_inp(up, UART_DLL);
753 quot <<= 3;
754
1da177e4
LT		 755 status1 = serial_in(up, 0x04); /* EXCR1 */
756 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
757 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
758 serial_outp(up, 0x04, status1);
857dde2e
DW		 759
760 serial_outp(up, UART_DLL, quot & 0xff);
761 serial_outp(up, UART_DLM, quot >> 8);
762
1da177e4 763 serial_outp(up, UART_LCR, 0);
1da177e4 764
857dde2e 765 up->port.uartclk = 921600*16;
1da177e4
LT		 766 up->port.type = PORT_NS16550A;
767 up->capabilities |= UART_NATSEMI;
768 return;
769 }
770 }
771
772 /*
773 * No EFR. Try to detect a TI16750, which only sets bit 5 of
774 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
775 * Try setting it with and without DLAB set. Cheap clones
776 * set bit 5 without DLAB set.
777 */
778 serial_outp(up, UART_LCR, 0);
779 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
780 status1 = serial_in(up, UART_IIR) >> 5;
781 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
782 serial_outp(up, UART_LCR, UART_LCR_DLAB);
783 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
784 status2 = serial_in(up, UART_IIR) >> 5;
785 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
786 serial_outp(up, UART_LCR, 0);
787
788 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
789
790 if (status1 == 6 && status2 == 7) {
791 up->port.type = PORT_16750;
792 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
793 return;
794 }
795
796 /*
797 * Try writing and reading the UART_IER_UUE bit (b6).
798 * If it works, this is probably one of the Xscale platform's
799 * internal UARTs.
800 * We're going to explicitly set the UUE bit to 0 before
801 * trying to write and read a 1 just to make sure it's not
802 * already a 1 and maybe locked there before we even start start.
803 */
804 iersave = serial_in(up, UART_IER);
805 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
806 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
807 /*
808 * OK it's in a known zero state, try writing and reading
809 * without disturbing the current state of the other bits.
810 */
811 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
812 if (serial_in(up, UART_IER) & UART_IER_UUE) {
813 /*
814 * It's an Xscale.
815 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
816 */
817 DEBUG_AUTOCONF("Xscale ");
818 up->port.type = PORT_XSCALE;
819 up->capabilities |= UART_CAP_UUE;
820 return;
821 }
822 } else {
823 /*
824 * If we got here we couldn't force the IER_UUE bit to 0.
825 * Log it and continue.
826 */
827 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
828 }
829 serial_outp(up, UART_IER, iersave);
830}
831
832/*
833 * This routine is called by rs_init() to initialize a specific serial
834 * port. It determines what type of UART chip this serial port is
835 * using: 8250, 16450, 16550, 16550A. The important question is
836 * whether or not this UART is a 16550A or not, since this will
837 * determine whether or not we can use its FIFO features or not.
838 */
839static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
840{
841 unsigned char status1, scratch, scratch2, scratch3;
842 unsigned char save_lcr, save_mcr;
843 unsigned long flags;
844
845 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
846 return;
847
848 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
849 up->port.line, up->port.iobase, up->port.membase);
850
851 /*
852 * We really do need global IRQs disabled here - we're going to
853 * be frobbing the chips IRQ enable register to see if it exists.
854 */
855 spin_lock_irqsave(&up->port.lock, flags);
856// save_flags(flags); cli();
857
858 up->capabilities = 0;
4ba5e35d 859 up->bugs = 0;
1da177e4
LT		 860
861 if (!(up->port.flags & UPF_BUGGY_UART)) {
862 /*
863 * Do a simple existence test first; if we fail this,
864 * there's no point trying anything else.
865 *
866 * 0x80 is used as a nonsense port to prevent against
867 * false positives due to ISA bus float. The
868 * assumption is that 0x80 is a non-existent port;
869 * which should be safe since include/asm/io.h also
870 * makes this assumption.
871 *
872 * Note: this is safe as long as MCR bit 4 is clear
873 * and the device is in "PC" mode.
874 */
875 scratch = serial_inp(up, UART_IER);
876 serial_outp(up, UART_IER, 0);
877#ifdef __i386__
878 outb(0xff, 0x080);
879#endif
880 scratch2 = serial_inp(up, UART_IER);
881 serial_outp(up, UART_IER, 0x0F);
882#ifdef __i386__
883 outb(0, 0x080);
884#endif
885 scratch3 = serial_inp(up, UART_IER);
886 serial_outp(up, UART_IER, scratch);
887 if (scratch2 != 0 || scratch3 != 0x0F) {
888 /*
889 * We failed; there's nothing here
890 */
891 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
892 scratch2, scratch3);
893 goto out;
894 }
895 }
896
897 save_mcr = serial_in(up, UART_MCR);
898 save_lcr = serial_in(up, UART_LCR);
899
900 /*
901 * Check to see if a UART is really there. Certain broken
902 * internal modems based on the Rockwell chipset fail this
903 * test, because they apparently don't implement the loopback
904 * test mode. So this test is skipped on the COM 1 through
905 * COM 4 ports. This *should* be safe, since no board
906 * manufacturer would be stupid enough to design a board
907 * that conflicts with COM 1-4 --- we hope!
908 */
909 if (!(up->port.flags & UPF_SKIP_TEST)) {
910 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
911 status1 = serial_inp(up, UART_MSR) & 0xF0;
912 serial_outp(up, UART_MCR, save_mcr);
913 if (status1 != 0x90) {
914 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
915 status1);
916 goto out;
917 }
918 }
919
920 /*
921 * We're pretty sure there's a port here. Lets find out what
922 * type of port it is. The IIR top two bits allows us to find
6f0d618f 923 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 924 * determines what we test for next.
925 *
926 * We also initialise the EFR (if any) to zero for later. The
927 * EFR occupies the same register location as the FCR and IIR.
928 */
929 serial_outp(up, UART_LCR, 0xBF);
930 serial_outp(up, UART_EFR, 0);
931 serial_outp(up, UART_LCR, 0);
932
933 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
934 scratch = serial_in(up, UART_IIR) >> 6;
935
936 DEBUG_AUTOCONF("iir=%d ", scratch);
937
938 switch (scratch) {
939 case 0:
940 autoconfig_8250(up);
941 break;
942 case 1:
943 up->port.type = PORT_UNKNOWN;
944 break;
945 case 2:
946 up->port.type = PORT_16550;
947 break;
948 case 3:
949 autoconfig_16550a(up);
950 break;
951 }
952
953#ifdef CONFIG_SERIAL_8250_RSA
954 /*
955 * Only probe for RSA ports if we got the region.
956 */
957 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
958 int i;
959
960 for (i = 0 ; i < probe_rsa_count; ++i) {
961 if (probe_rsa[i] == up->port.iobase &&
962 __enable_rsa(up)) {
963 up->port.type = PORT_RSA;
964 break;
965 }
966 }
967 }
968#endif
21c614a7
PA		 969
970#ifdef CONFIG_SERIAL_8250_AU1X00
971 /* if access method is AU, it is a 16550 with a quirk */
972 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
973 up->bugs |= UART_BUG_NOMSR;
974#endif
975
1da177e4
LT		 976 serial_outp(up, UART_LCR, save_lcr);
977
978 if (up->capabilities != uart_config[up->port.type].flags) {
979 printk(KERN_WARNING
980 "ttyS%d: detected caps %08x should be %08x\n",
981 up->port.line, up->capabilities,
982 uart_config[up->port.type].flags);
983 }
984
985 up->port.fifosize = uart_config[up->port.type].fifo_size;
986 up->capabilities = uart_config[up->port.type].flags;
987 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
988
989 if (up->port.type == PORT_UNKNOWN)
990 goto out;
991
992 /*
993 * Reset the UART.
994 */
995#ifdef CONFIG_SERIAL_8250_RSA
996 if (up->port.type == PORT_RSA)
997 serial_outp(up, UART_RSA_FRR, 0);
998#endif
999 serial_outp(up, UART_MCR, save_mcr);
1000 serial8250_clear_fifos(up);
1001 (void)serial_in(up, UART_RX);
5c8c755c
LB		 1002 if (up->capabilities & UART_CAP_UUE)
1003 serial_outp(up, UART_IER, UART_IER_UUE);
1004 else
1005 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1006
1007 out:
1008 spin_unlock_irqrestore(&up->port.lock, flags);
1009// restore_flags(flags);
1010 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1011}
1012
1013static void autoconfig_irq(struct uart_8250_port *up)
1014{
1015 unsigned char save_mcr, save_ier;
1016 unsigned char save_ICP = 0;
1017 unsigned int ICP = 0;
1018 unsigned long irqs;
1019 int irq;
1020
1021 if (up->port.flags & UPF_FOURPORT) {
1022 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1023 save_ICP = inb_p(ICP);
1024 outb_p(0x80, ICP);
1025 (void) inb_p(ICP);
1026 }
1027
1028 /* forget possible initially masked and pending IRQ */
1029 probe_irq_off(probe_irq_on());
1030 save_mcr = serial_inp(up, UART_MCR);
1031 save_ier = serial_inp(up, UART_IER);
1032 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1033
1034 irqs = probe_irq_on();
1035 serial_outp(up, UART_MCR, 0);
1036 udelay (10);
1037 if (up->port.flags & UPF_FOURPORT) {
1038 serial_outp(up, UART_MCR,
1039 UART_MCR_DTR | UART_MCR_RTS);
1040 } else {
1041 serial_outp(up, UART_MCR,
1042 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1043 }
1044 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1045 (void)serial_inp(up, UART_LSR);
1046 (void)serial_inp(up, UART_RX);
1047 (void)serial_inp(up, UART_IIR);
1048 (void)serial_inp(up, UART_MSR);
1049 serial_outp(up, UART_TX, 0xFF);
1050 udelay (20);
1051 irq = probe_irq_off(irqs);
1052
1053 serial_outp(up, UART_MCR, save_mcr);
1054 serial_outp(up, UART_IER, save_ier);
1055
1056 if (up->port.flags & UPF_FOURPORT)
1057 outb_p(save_ICP, ICP);
1058
1059 up->port.irq = (irq > 0) ? irq : 0;
1060}
1061
e763b90c
RK		 1062static inline void __stop_tx(struct uart_8250_port *p)
1063{
1064 if (p->ier & UART_IER_THRI) {
1065 p->ier &= ~UART_IER_THRI;
1066 serial_out(p, UART_IER, p->ier);
1067 }
1068}
1069
b129a8cc 1070static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1071{
1072 struct uart_8250_port *up = (struct uart_8250_port *)port;
1073
e763b90c 1074 __stop_tx(up);
1da177e4
LT		 1075
1076 /*
e763b90c 1077 * We really want to stop the transmitter from sending.
1da177e4 1078 */
e763b90c 1079 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1080 up->acr |= UART_ACR_TXDIS;
1081 serial_icr_write(up, UART_ACR, up->acr);
1082 }
1083}
1084
55d3b282
RK		 1085static void transmit_chars(struct uart_8250_port *up);
1086
b129a8cc 1087static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1088{
1089 struct uart_8250_port *up = (struct uart_8250_port *)port;
1090
1091 if (!(up->ier & UART_IER_THRI)) {
1092 up->ier |= UART_IER_THRI;
1093 serial_out(up, UART_IER, up->ier);
55d3b282 1094
67f7654e 1095 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1096 unsigned char lsr, iir;
1097 lsr = serial_in(up, UART_LSR);
1098 iir = serial_in(up, UART_IIR);
1099 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1100 transmit_chars(up);
1101 }
1da177e4 1102 }
e763b90c 1103
1da177e4 1104 /*
e763b90c 1105 * Re-enable the transmitter if we disabled it.
1da177e4 1106 */
e763b90c 1107 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1108 up->acr &= ~UART_ACR_TXDIS;
1109 serial_icr_write(up, UART_ACR, up->acr);
1110 }
1111}
1112
1113static void serial8250_stop_rx(struct uart_port *port)
1114{
1115 struct uart_8250_port *up = (struct uart_8250_port *)port;
1116
1117 up->ier &= ~UART_IER_RLSI;
1118 up->port.read_status_mask &= ~UART_LSR_DR;
1119 serial_out(up, UART_IER, up->ier);
1120}
1121
1122static void serial8250_enable_ms(struct uart_port *port)
1123{
1124 struct uart_8250_port *up = (struct uart_8250_port *)port;
1125
21c614a7
PA		 1126 /* no MSR capabilities */
1127 if (up->bugs & UART_BUG_NOMSR)
1128 return;
1129
1da177e4
LT		 1130 up->ier |= UART_IER_MSI;
1131 serial_out(up, UART_IER, up->ier);
1132}
1133
1134static _INLINE_ void
1135receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1136{
1137 struct tty_struct *tty = up->port.info->tty;
1138 unsigned char ch, lsr = *status;
1139 int max_count = 256;
1140 char flag;
1141
1142 do {
1143 /* The following is not allowed by the tty layer and
1144 unsafe. It should be fixed ASAP */
1145 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1146 if (tty->low_latency) {
1147 spin_unlock(&up->port.lock);
1148 tty_flip_buffer_push(tty);
1149 spin_lock(&up->port.lock);
1150 }
23907eb8
RK		 1151 /*
1152 * If this failed then we will throw away the
1153 * bytes but must do so to clear interrupts
1154 */
1da177e4
LT		 1155 }
1156 ch = serial_inp(up, UART_RX);
1157 flag = TTY_NORMAL;
1158 up->port.icount.rx++;
1159
1160#ifdef CONFIG_SERIAL_8250_CONSOLE
1161 /*
1162 * Recover the break flag from console xmit
1163 */
1164 if (up->port.line == up->port.cons->index) {
1165 lsr |= up->lsr_break_flag;
1166 up->lsr_break_flag = 0;
1167 }
1168#endif
1169
1170 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1171 UART_LSR_FE | UART_LSR_OE))) {
1172 /*
1173 * For statistics only
1174 */
1175 if (lsr & UART_LSR_BI) {
1176 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1177 up->port.icount.brk++;
1178 /*
1179 * We do the SysRQ and SAK checking
1180 * here because otherwise the break
1181 * may get masked by ignore_status_mask
1182 * or read_status_mask.
1183 */
1184 if (uart_handle_break(&up->port))
1185 goto ignore_char;
1186 } else if (lsr & UART_LSR_PE)
1187 up->port.icount.parity++;
1188 else if (lsr & UART_LSR_FE)
1189 up->port.icount.frame++;
1190 if (lsr & UART_LSR_OE)
1191 up->port.icount.overrun++;
1192
1193 /*
23907eb8 1194 * Mask off conditions which should be ignored.
1da177e4
LT		 1195 */
1196 lsr &= up->port.read_status_mask;
1197
1198 if (lsr & UART_LSR_BI) {
1199 DEBUG_INTR("handling break....");
1200 flag = TTY_BREAK;
1201 } else if (lsr & UART_LSR_PE)
1202 flag = TTY_PARITY;
1203 else if (lsr & UART_LSR_FE)
1204 flag = TTY_FRAME;
1205 }
1206 if (uart_handle_sysrq_char(&up->port, ch, regs))
1207 goto ignore_char;
05ab3014
RK		 1208
1209 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1210
1da177e4
LT		 1211 ignore_char:
1212 lsr = serial_inp(up, UART_LSR);
1213 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1214 spin_unlock(&up->port.lock);
1215 tty_flip_buffer_push(tty);
1216 spin_lock(&up->port.lock);
1217 *status = lsr;
1218}
1219
1220static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1221{
1222 struct circ_buf *xmit = &up->port.info->xmit;
1223 int count;
1224
1225 if (up->port.x_char) {
1226 serial_outp(up, UART_TX, up->port.x_char);
1227 up->port.icount.tx++;
1228 up->port.x_char = 0;
1229 return;
1230 }
b129a8cc
RK		 1231 if (uart_tx_stopped(&up->port)) {
1232 serial8250_stop_tx(&up->port);
1233 return;
1234 }
1235 if (uart_circ_empty(xmit)) {
e763b90c 1236 __stop_tx(up);
1da177e4
LT		 1237 return;
1238 }
1239
1240 count = up->tx_loadsz;
1241 do {
1242 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1243 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1244 up->port.icount.tx++;
1245 if (uart_circ_empty(xmit))
1246 break;
1247 } while (--count > 0);
1248
1249 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1250 uart_write_wakeup(&up->port);
1251
1252 DEBUG_INTR("THRE...");
1253
1254 if (uart_circ_empty(xmit))
e763b90c 1255 __stop_tx(up);
1da177e4
LT		 1256}
1257
1258static _INLINE_ void check_modem_status(struct uart_8250_port *up)
1259{
1260 int status;
1261
1262 status = serial_in(up, UART_MSR);
1263
1264 if ((status & UART_MSR_ANY_DELTA) == 0)
1265 return;
1266
1267 if (status & UART_MSR_TERI)
1268 up->port.icount.rng++;
1269 if (status & UART_MSR_DDSR)
1270 up->port.icount.dsr++;
1271 if (status & UART_MSR_DDCD)
1272 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1273 if (status & UART_MSR_DCTS)
1274 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1275
1276 wake_up_interruptible(&up->port.info->delta_msr_wait);
1277}
1278
1279/*
1280 * This handles the interrupt from one port.
1281 */
1282static inline void
1283serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1284{
1285 unsigned int status = serial_inp(up, UART_LSR);
1286
1287 DEBUG_INTR("status = %x...", status);
1288
1289 if (status & UART_LSR_DR)
1290 receive_chars(up, &status, regs);
1291 check_modem_status(up);
1292 if (status & UART_LSR_THRE)
1293 transmit_chars(up);
1294}
1295
1296/*
1297 * This is the serial driver's interrupt routine.
1298 *
1299 * Arjan thinks the old way was overly complex, so it got simplified.
1300 * Alan disagrees, saying that need the complexity to handle the weird
1301 * nature of ISA shared interrupts. (This is a special exception.)
1302 *
1303 * In order to handle ISA shared interrupts properly, we need to check
1304 * that all ports have been serviced, and therefore the ISA interrupt
1305 * line has been de-asserted.
1306 *
1307 * This means we need to loop through all ports. checking that they
1308 * don't have an interrupt pending.
1309 */
1310static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1311{
1312 struct irq_info *i = dev_id;
1313 struct list_head *l, *end = NULL;
1314 int pass_counter = 0, handled = 0;
1315
1316 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1317
1318 spin_lock(&i->lock);
1319
1320 l = i->head;
1321 do {
1322 struct uart_8250_port *up;
1323 unsigned int iir;
1324
1325 up = list_entry(l, struct uart_8250_port, list);
1326
1327 iir = serial_in(up, UART_IIR);
1328 if (!(iir & UART_IIR_NO_INT)) {
1329 spin_lock(&up->port.lock);
1330 serial8250_handle_port(up, regs);
1331 spin_unlock(&up->port.lock);
1332
1333 handled = 1;
1334
1335 end = NULL;
1336 } else if (end == NULL)
1337 end = l;
1338
1339 l = l->next;
1340
1341 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1342 /* If we hit this, we're dead. */
1343 printk(KERN_ERR "serial8250: too much work for "
1344 "irq%d\n", irq);
1345 break;
1346 }
1347 } while (l != end);
1348
1349 spin_unlock(&i->lock);
1350
1351 DEBUG_INTR("end.\n");
1352
1353 return IRQ_RETVAL(handled);
1354}
1355
1356/*
1357 * To support ISA shared interrupts, we need to have one interrupt
1358 * handler that ensures that the IRQ line has been deasserted
1359 * before returning. Failing to do this will result in the IRQ
1360 * line being stuck active, and, since ISA irqs are edge triggered,
1361 * no more IRQs will be seen.
1362 */
1363static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1364{
1365 spin_lock_irq(&i->lock);
1366
1367 if (!list_empty(i->head)) {
1368 if (i->head == &up->list)
1369 i->head = i->head->next;
1370 list_del(&up->list);
1371 } else {
1372 BUG_ON(i->head != &up->list);
1373 i->head = NULL;
1374 }
1375
1376 spin_unlock_irq(&i->lock);
1377}
1378
1379static int serial_link_irq_chain(struct uart_8250_port *up)
1380{
1381 struct irq_info *i = irq_lists + up->port.irq;
1382 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1383
1384 spin_lock_irq(&i->lock);
1385
1386 if (i->head) {
1387 list_add(&up->list, i->head);
1388 spin_unlock_irq(&i->lock);
1389
1390 ret = 0;
1391 } else {
1392 INIT_LIST_HEAD(&up->list);
1393 i->head = &up->list;
1394 spin_unlock_irq(&i->lock);
1395
1396 ret = request_irq(up->port.irq, serial8250_interrupt,
1397 irq_flags, "serial", i);
1398 if (ret < 0)
1399 serial_do_unlink(i, up);
1400 }
1401
1402 return ret;
1403}
1404
1405static void serial_unlink_irq_chain(struct uart_8250_port *up)
1406{
1407 struct irq_info *i = irq_lists + up->port.irq;
1408
1409 BUG_ON(i->head == NULL);
1410
1411 if (list_empty(i->head))
1412 free_irq(up->port.irq, i);
1413
1414 serial_do_unlink(i, up);
1415}
1416
1417/*
1418 * This function is used to handle ports that do not have an
1419 * interrupt. This doesn't work very well for 16450's, but gives
1420 * barely passable results for a 16550A. (Although at the expense
1421 * of much CPU overhead).
1422 */
1423static void serial8250_timeout(unsigned long data)
1424{
1425 struct uart_8250_port *up = (struct uart_8250_port *)data;
1426 unsigned int timeout;
1427 unsigned int iir;
1428
1429 iir = serial_in(up, UART_IIR);
1430 if (!(iir & UART_IIR_NO_INT)) {
1431 spin_lock(&up->port.lock);
1432 serial8250_handle_port(up, NULL);
1433 spin_unlock(&up->port.lock);
1434 }
1435
1436 timeout = up->port.timeout;
1437 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1438 mod_timer(&up->timer, jiffies + timeout);
1439}
1440
1441static unsigned int serial8250_tx_empty(struct uart_port *port)
1442{
1443 struct uart_8250_port *up = (struct uart_8250_port *)port;
1444 unsigned long flags;
1445 unsigned int ret;
1446
1447 spin_lock_irqsave(&up->port.lock, flags);
1448 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1449 spin_unlock_irqrestore(&up->port.lock, flags);
1450
1451 return ret;
1452}
1453
1454static unsigned int serial8250_get_mctrl(struct uart_port *port)
1455{
1456 struct uart_8250_port *up = (struct uart_8250_port *)port;
1da177e4
LT		 1457 unsigned char status;
1458 unsigned int ret;
1459
1da177e4 1460 status = serial_in(up, UART_MSR);
1da177e4
LT		 1461
1462 ret = 0;
1463 if (status & UART_MSR_DCD)
1464 ret |= TIOCM_CAR;
1465 if (status & UART_MSR_RI)
1466 ret |= TIOCM_RNG;
1467 if (status & UART_MSR_DSR)
1468 ret |= TIOCM_DSR;
1469 if (status & UART_MSR_CTS)
1470 ret |= TIOCM_CTS;
1471 return ret;
1472}
1473
1474static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1475{
1476 struct uart_8250_port *up = (struct uart_8250_port *)port;
1477 unsigned char mcr = 0;
1478
1479 if (mctrl & TIOCM_RTS)
1480 mcr |= UART_MCR_RTS;
1481 if (mctrl & TIOCM_DTR)
1482 mcr |= UART_MCR_DTR;
1483 if (mctrl & TIOCM_OUT1)
1484 mcr |= UART_MCR_OUT1;
1485 if (mctrl & TIOCM_OUT2)
1486 mcr |= UART_MCR_OUT2;
1487 if (mctrl & TIOCM_LOOP)
1488 mcr |= UART_MCR_LOOP;
1489
1490 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1491
1492 serial_out(up, UART_MCR, mcr);
1493}
1494
1495static void serial8250_break_ctl(struct uart_port *port, int break_state)
1496{
1497 struct uart_8250_port *up = (struct uart_8250_port *)port;
1498 unsigned long flags;
1499
1500 spin_lock_irqsave(&up->port.lock, flags);
1501 if (break_state == -1)
1502 up->lcr |= UART_LCR_SBC;
1503 else
1504 up->lcr &= ~UART_LCR_SBC;
1505 serial_out(up, UART_LCR, up->lcr);
1506 spin_unlock_irqrestore(&up->port.lock, flags);
1507}
1508
1509static int serial8250_startup(struct uart_port *port)
1510{
1511 struct uart_8250_port *up = (struct uart_8250_port *)port;
1512 unsigned long flags;
55d3b282 1513 unsigned char lsr, iir;
1da177e4
LT		 1514 int retval;
1515
1516 up->capabilities = uart_config[up->port.type].flags;
1517 up->mcr = 0;
1518
1519 if (up->port.type == PORT_16C950) {
1520 /* Wake up and initialize UART */
1521 up->acr = 0;
1522 serial_outp(up, UART_LCR, 0xBF);
1523 serial_outp(up, UART_EFR, UART_EFR_ECB);
1524 serial_outp(up, UART_IER, 0);
1525 serial_outp(up, UART_LCR, 0);
1526 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1527 serial_outp(up, UART_LCR, 0xBF);
1528 serial_outp(up, UART_EFR, UART_EFR_ECB);
1529 serial_outp(up, UART_LCR, 0);
1530 }
1531
1532#ifdef CONFIG_SERIAL_8250_RSA
1533 /*
1534 * If this is an RSA port, see if we can kick it up to the
1535 * higher speed clock.
1536 */
1537 enable_rsa(up);
1538#endif
1539
1540 /*
1541 * Clear the FIFO buffers and disable them.
1542 * (they will be reeanbled in set_termios())
1543 */
1544 serial8250_clear_fifos(up);
1545
1546 /*
1547 * Clear the interrupt registers.
1548 */
1549 (void) serial_inp(up, UART_LSR);
1550 (void) serial_inp(up, UART_RX);
1551 (void) serial_inp(up, UART_IIR);
1552 (void) serial_inp(up, UART_MSR);
1553
1554 /*
1555 * At this point, there's no way the LSR could still be 0xff;
1556 * if it is, then bail out, because there's likely no UART
1557 * here.
1558 */
1559 if (!(up->port.flags & UPF_BUGGY_UART) &&
1560 (serial_inp(up, UART_LSR) == 0xff)) {
1561 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1562 return -ENODEV;
1563 }
1564
1565 /*
1566 * For a XR16C850, we need to set the trigger levels
1567 */
1568 if (up->port.type == PORT_16850) {
1569 unsigned char fctr;
1570
1571 serial_outp(up, UART_LCR, 0xbf);
1572
1573 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1574 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1575 serial_outp(up, UART_TRG, UART_TRG_96);
1576 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1577 serial_outp(up, UART_TRG, UART_TRG_96);
1578
1579 serial_outp(up, UART_LCR, 0);
1580 }
1581
1582 /*
1583 * If the "interrupt" for this port doesn't correspond with any
1584 * hardware interrupt, we use a timer-based system. The original
1585 * driver used to do this with IRQ0.
1586 */
1587 if (!is_real_interrupt(up->port.irq)) {
1588 unsigned int timeout = up->port.timeout;
1589
1590 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1591
1592 up->timer.data = (unsigned long)up;
1593 mod_timer(&up->timer, jiffies + timeout);
1594 } else {
1595 retval = serial_link_irq_chain(up);
1596 if (retval)
1597 return retval;
1598 }
1599
1600 /*
1601 * Now, initialize the UART
1602 */
1603 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1604
1605 spin_lock_irqsave(&up->port.lock, flags);
1606 if (up->port.flags & UPF_FOURPORT) {
1607 if (!is_real_interrupt(up->port.irq))
1608 up->port.mctrl |= TIOCM_OUT1;
1609 } else
1610 /*
1611 * Most PC uarts need OUT2 raised to enable interrupts.
1612 */
1613 if (is_real_interrupt(up->port.irq))
1614 up->port.mctrl |= TIOCM_OUT2;
1615
1616 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1617
1618 /*
1619 * Do a quick test to see if we receive an
1620 * interrupt when we enable the TX irq.
1621 */
1622 serial_outp(up, UART_IER, UART_IER_THRI);
1623 lsr = serial_in(up, UART_LSR);
1624 iir = serial_in(up, UART_IIR);
1625 serial_outp(up, UART_IER, 0);
1626
1627 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1628 if (!(up->bugs & UART_BUG_TXEN)) {
1629 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1630 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1631 port->line);
1632 }
1633 } else {
67f7654e 1634 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1635 }
1636
1da177e4
LT		 1637 spin_unlock_irqrestore(&up->port.lock, flags);
1638
1639 /*
1640 * Finally, enable interrupts. Note: Modem status interrupts
1641 * are set via set_termios(), which will be occurring imminently
1642 * anyway, so we don't enable them here.
1643 */
1644 up->ier = UART_IER_RLSI | UART_IER_RDI;
1645 serial_outp(up, UART_IER, up->ier);
1646
1647 if (up->port.flags & UPF_FOURPORT) {
1648 unsigned int icp;
1649 /*
1650 * Enable interrupts on the AST Fourport board
1651 */
1652 icp = (up->port.iobase & 0xfe0) | 0x01f;
1653 outb_p(0x80, icp);
1654 (void) inb_p(icp);
1655 }
1656
1657 /*
1658 * And clear the interrupt registers again for luck.
1659 */
1660 (void) serial_inp(up, UART_LSR);
1661 (void) serial_inp(up, UART_RX);
1662 (void) serial_inp(up, UART_IIR);
1663 (void) serial_inp(up, UART_MSR);
1664
1665 return 0;
1666}
1667
1668static void serial8250_shutdown(struct uart_port *port)
1669{
1670 struct uart_8250_port *up = (struct uart_8250_port *)port;
1671 unsigned long flags;
1672
1673 /*
1674 * Disable interrupts from this port
1675 */
1676 up->ier = 0;
1677 serial_outp(up, UART_IER, 0);
1678
1679 spin_lock_irqsave(&up->port.lock, flags);
1680 if (up->port.flags & UPF_FOURPORT) {
1681 /* reset interrupts on the AST Fourport board */
1682 inb((up->port.iobase & 0xfe0) | 0x1f);
1683 up->port.mctrl |= TIOCM_OUT1;
1684 } else
1685 up->port.mctrl &= ~TIOCM_OUT2;
1686
1687 serial8250_set_mctrl(&up->port, up->port.mctrl);
1688 spin_unlock_irqrestore(&up->port.lock, flags);
1689
1690 /*
1691 * Disable break condition and FIFOs
1692 */
1693 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1694 serial8250_clear_fifos(up);
1695
1696#ifdef CONFIG_SERIAL_8250_RSA
1697 /*
1698 * Reset the RSA board back to 115kbps compat mode.
1699 */
1700 disable_rsa(up);
1701#endif
1702
1703 /*
1704 * Read data port to reset things, and then unlink from
1705 * the IRQ chain.
1706 */
1707 (void) serial_in(up, UART_RX);
1708
1709 if (!is_real_interrupt(up->port.irq))
1710 del_timer_sync(&up->timer);
1711 else
1712 serial_unlink_irq_chain(up);
1713}
1714
1715static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1716{
1717 unsigned int quot;
1718
1719 /*
1720 * Handle magic divisors for baud rates above baud_base on
1721 * SMSC SuperIO chips.
1722 */
1723 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1724 baud == (port->uartclk/4))
1725 quot = 0x8001;
1726 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1727 baud == (port->uartclk/8))
1728 quot = 0x8002;
1729 else
1730 quot = uart_get_divisor(port, baud);
1731
1732 return quot;
1733}
1734
1735static void
1736serial8250_set_termios(struct uart_port *port, struct termios *termios,
1737 struct termios *old)
1738{
1739 struct uart_8250_port *up = (struct uart_8250_port *)port;
1740 unsigned char cval, fcr = 0;
1741 unsigned long flags;
1742 unsigned int baud, quot;
1743
1744 switch (termios->c_cflag & CSIZE) {
1745 case CS5:
0a8b80c5 1746 cval = UART_LCR_WLEN5;
1da177e4
LT		 1747 break;
1748 case CS6:
0a8b80c5 1749 cval = UART_LCR_WLEN6;
1da177e4
LT		 1750 break;
1751 case CS7:
0a8b80c5 1752 cval = UART_LCR_WLEN7;
1da177e4
LT		 1753 break;
1754 default:
1755 case CS8:
0a8b80c5 1756 cval = UART_LCR_WLEN8;
1da177e4
LT		 1757 break;
1758 }
1759
1760 if (termios->c_cflag & CSTOPB)
0a8b80c5 1761 cval |= UART_LCR_STOP;
1da177e4
LT		 1762 if (termios->c_cflag & PARENB)
1763 cval |= UART_LCR_PARITY;
1764 if (!(termios->c_cflag & PARODD))
1765 cval |= UART_LCR_EPAR;
1766#ifdef CMSPAR
1767 if (termios->c_cflag & CMSPAR)
1768 cval |= UART_LCR_SPAR;
1769#endif
1770
1771 /*
1772 * Ask the core to calculate the divisor for us.
1773 */
1774 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1775 quot = serial8250_get_divisor(port, baud);
1776
1777 /*
4ba5e35d 1778 * Oxford Semi 952 rev B workaround
1da177e4 1779 */
4ba5e35d 1780 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1781 quot ++;
1782
1783 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1784 if (baud < 2400)
1785 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1786 else
1787 fcr = uart_config[up->port.type].fcr;
1788 }
1789
1790 /*
1791 * MCR-based auto flow control. When AFE is enabled, RTS will be
1792 * deasserted when the receive FIFO contains more characters than
1793 * the trigger, or the MCR RTS bit is cleared. In the case where
1794 * the remote UART is not using CTS auto flow control, we must
1795 * have sufficient FIFO entries for the latency of the remote
1796 * UART to respond. IOW, at least 32 bytes of FIFO.
1797 */
1798 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1799 up->mcr &= ~UART_MCR_AFE;
1800 if (termios->c_cflag & CRTSCTS)
1801 up->mcr |= UART_MCR_AFE;
1802 }
1803
1804 /*
1805 * Ok, we're now changing the port state. Do it with
1806 * interrupts disabled.
1807 */
1808 spin_lock_irqsave(&up->port.lock, flags);
1809
1810 /*
1811 * Update the per-port timeout.
1812 */
1813 uart_update_timeout(port, termios->c_cflag, baud);
1814
1815 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1816 if (termios->c_iflag & INPCK)
1817 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1818 if (termios->c_iflag & (BRKINT | PARMRK))
1819 up->port.read_status_mask |= UART_LSR_BI;
1820
1821 /*
1822 * Characteres to ignore
1823 */
1824 up->port.ignore_status_mask = 0;
1825 if (termios->c_iflag & IGNPAR)
1826 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1827 if (termios->c_iflag & IGNBRK) {
1828 up->port.ignore_status_mask |= UART_LSR_BI;
1829 /*
1830 * If we're ignoring parity and break indicators,
1831 * ignore overruns too (for real raw support).
1832 */
1833 if (termios->c_iflag & IGNPAR)
1834 up->port.ignore_status_mask |= UART_LSR_OE;
1835 }
1836
1837 /*
1838 * ignore all characters if CREAD is not set
1839 */
1840 if ((termios->c_cflag & CREAD) == 0)
1841 up->port.ignore_status_mask |= UART_LSR_DR;
1842
1843 /*
1844 * CTS flow control flag and modem status interrupts
1845 */
1846 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1847 if (!(up->bugs & UART_BUG_NOMSR) &&
1848 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1849 up->ier |= UART_IER_MSI;
1850 if (up->capabilities & UART_CAP_UUE)
1851 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1852
1853 serial_out(up, UART_IER, up->ier);
1854
1855 if (up->capabilities & UART_CAP_EFR) {
1856 unsigned char efr = 0;
1857 /*
1858 * TI16C752/Startech hardware flow control. FIXME:
1859 * - TI16C752 requires control thresholds to be set.
1860 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1861 */
1862 if (termios->c_cflag & CRTSCTS)
1863 efr |= UART_EFR_CTS;
1864
1865 serial_outp(up, UART_LCR, 0xBF);
1866 serial_outp(up, UART_EFR, efr);
1867 }
1868
1869 if (up->capabilities & UART_NATSEMI) {
1870 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1871 serial_outp(up, UART_LCR, 0xe0);
1872 } else {
1873 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1874 }
1875
1876 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1877 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1878
1879 /*
1880 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1881 * is written without DLAB set, this mode will be disabled.
1882 */
1883 if (up->port.type == PORT_16750)
1884 serial_outp(up, UART_FCR, fcr);
1885
1886 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1887 up->lcr = cval; /* Save LCR */
1888 if (up->port.type != PORT_16750) {
1889 if (fcr & UART_FCR_ENABLE_FIFO) {
1890 /* emulated UARTs (Lucent Venus 167x) need two steps */
1891 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1892 }
1893 serial_outp(up, UART_FCR, fcr); /* set fcr */
1894 }
1895 serial8250_set_mctrl(&up->port, up->port.mctrl);
1896 spin_unlock_irqrestore(&up->port.lock, flags);
1897}
1898
1899static void
1900serial8250_pm(struct uart_port *port, unsigned int state,
1901 unsigned int oldstate)
1902{
1903 struct uart_8250_port *p = (struct uart_8250_port *)port;
1904
1905 serial8250_set_sleep(p, state != 0);
1906
1907 if (p->pm)
1908 p->pm(port, state, oldstate);
1909}
1910
1911/*
1912 * Resource handling.
1913 */
1914static int serial8250_request_std_resource(struct uart_8250_port *up)
1915{
1916 unsigned int size = 8 << up->port.regshift;
1917 int ret = 0;
1918
1919 switch (up->port.iotype) {
1920 case UPIO_MEM:
1921 if (!up->port.mapbase)
1922 break;
1923
1924 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1925 ret = -EBUSY;
1926 break;
1927 }
1928
1929 if (up->port.flags & UPF_IOREMAP) {
1930 up->port.membase = ioremap(up->port.mapbase, size);
1931 if (!up->port.membase) {
1932 release_mem_region(up->port.mapbase, size);
1933 ret = -ENOMEM;
1934 }
1935 }
1936 break;
1937
1938 case UPIO_HUB6:
1939 case UPIO_PORT:
1940 if (!request_region(up->port.iobase, size, "serial"))
1941 ret = -EBUSY;
1942 break;
1943 }
1944 return ret;
1945}
1946
1947static void serial8250_release_std_resource(struct uart_8250_port *up)
1948{
1949 unsigned int size = 8 << up->port.regshift;
1950
1951 switch (up->port.iotype) {
1952 case UPIO_MEM:
1953 if (!up->port.mapbase)
1954 break;
1955
1956 if (up->port.flags & UPF_IOREMAP) {
1957 iounmap(up->port.membase);
1958 up->port.membase = NULL;
1959 }
1960
1961 release_mem_region(up->port.mapbase, size);
1962 break;
1963
1964 case UPIO_HUB6:
1965 case UPIO_PORT:
1966 release_region(up->port.iobase, size);
1967 break;
1968 }
1969}
1970
1971static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1972{
1973 unsigned long start = UART_RSA_BASE << up->port.regshift;
1974 unsigned int size = 8 << up->port.regshift;
1975 int ret = 0;
1976
1977 switch (up->port.iotype) {
1978 case UPIO_MEM:
1979 ret = -EINVAL;
1980 break;
1981
1982 case UPIO_HUB6:
1983 case UPIO_PORT:
1984 start += up->port.iobase;
1985 if (!request_region(start, size, "serial-rsa"))
1986 ret = -EBUSY;
1987 break;
1988 }
1989
1990 return ret;
1991}
1992
1993static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1994{
1995 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1996 unsigned int size = 8 << up->port.regshift;
1997
1998 switch (up->port.iotype) {
1999 case UPIO_MEM:
2000 break;
2001
2002 case UPIO_HUB6:
2003 case UPIO_PORT:
2004 release_region(up->port.iobase + offset, size);
2005 break;
2006 }
2007}
2008
2009static void serial8250_release_port(struct uart_port *port)
2010{
2011 struct uart_8250_port *up = (struct uart_8250_port *)port;
2012
2013 serial8250_release_std_resource(up);
2014 if (up->port.type == PORT_RSA)
2015 serial8250_release_rsa_resource(up);
2016}
2017
2018static int serial8250_request_port(struct uart_port *port)
2019{
2020 struct uart_8250_port *up = (struct uart_8250_port *)port;
2021 int ret = 0;
2022
2023 ret = serial8250_request_std_resource(up);
2024 if (ret == 0 && up->port.type == PORT_RSA) {
2025 ret = serial8250_request_rsa_resource(up);
2026 if (ret < 0)
2027 serial8250_release_std_resource(up);
2028 }
2029
2030 return ret;
2031}
2032
2033static void serial8250_config_port(struct uart_port *port, int flags)
2034{
2035 struct uart_8250_port *up = (struct uart_8250_port *)port;
2036 int probeflags = PROBE_ANY;
2037 int ret;
2038
2039 /*
2040 * Don't probe for MCA ports on non-MCA machines.
2041 */
2042 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
2043 return;
2044
2045 /*
2046 * Find the region that we can probe for. This in turn
2047 * tells us whether we can probe for the type of port.
2048 */
2049 ret = serial8250_request_std_resource(up);
2050 if (ret < 0)
2051 return;
2052
2053 ret = serial8250_request_rsa_resource(up);
2054 if (ret < 0)
2055 probeflags &= ~PROBE_RSA;
2056
2057 if (flags & UART_CONFIG_TYPE)
2058 autoconfig(up, probeflags);
2059 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2060 autoconfig_irq(up);
2061
2062 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2063 serial8250_release_rsa_resource(up);
2064 if (up->port.type == PORT_UNKNOWN)
2065 serial8250_release_std_resource(up);
2066}
2067
2068static int
2069serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2070{
2071 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2072 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2073 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2074 ser->type == PORT_STARTECH)
2075 return -EINVAL;
2076 return 0;
2077}
2078
2079static const char *
2080serial8250_type(struct uart_port *port)
2081{
2082 int type = port->type;
2083
2084 if (type >= ARRAY_SIZE(uart_config))
2085 type = 0;
2086 return uart_config[type].name;
2087}
2088
2089static struct uart_ops serial8250_pops = {
2090 .tx_empty = serial8250_tx_empty,
2091 .set_mctrl = serial8250_set_mctrl,
2092 .get_mctrl = serial8250_get_mctrl,
2093 .stop_tx = serial8250_stop_tx,
2094 .start_tx = serial8250_start_tx,
2095 .stop_rx = serial8250_stop_rx,
2096 .enable_ms = serial8250_enable_ms,
2097 .break_ctl = serial8250_break_ctl,
2098 .startup = serial8250_startup,
2099 .shutdown = serial8250_shutdown,
2100 .set_termios = serial8250_set_termios,
2101 .pm = serial8250_pm,
2102 .type = serial8250_type,
2103 .release_port = serial8250_release_port,
2104 .request_port = serial8250_request_port,
2105 .config_port = serial8250_config_port,
2106 .verify_port = serial8250_verify_port,
2107};
2108
2109static struct uart_8250_port serial8250_ports[UART_NR];
2110
2111static void __init serial8250_isa_init_ports(void)
2112{
2113 struct uart_8250_port *up;
2114 static int first = 1;
2115 int i;
2116
2117 if (!first)
2118 return;
2119 first = 0;
2120
2121 for (i = 0; i < UART_NR; i++) {
2122 struct uart_8250_port *up = &serial8250_ports[i];
2123
2124 up->port.line = i;
2125 spin_lock_init(&up->port.lock);
2126
2127 init_timer(&up->timer);
2128 up->timer.function = serial8250_timeout;
2129
2130 /*
2131 * ALPHA_KLUDGE_MCR needs to be killed.
2132 */
2133 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2134 up->mcr_force = ALPHA_KLUDGE_MCR;
2135
2136 up->port.ops = &serial8250_pops;
2137 }
2138
44454bcd
RK		 2139 for (i = 0, up = serial8250_ports;
2140 i < ARRAY_SIZE(old_serial_port) && i < UART_NR;
1da177e4
LT		 2141 i++, up++) {
2142 up->port.iobase = old_serial_port[i].port;
2143 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2144 up->port.uartclk = old_serial_port[i].baud_base * 16;
2145 up->port.flags = old_serial_port[i].flags;
2146 up->port.hub6 = old_serial_port[i].hub6;
2147 up->port.membase = old_serial_port[i].iomem_base;
2148 up->port.iotype = old_serial_port[i].io_type;
2149 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2150 if (share_irqs)
2151 up->port.flags |= UPF_SHARE_IRQ;
2152 }
2153}
2154
2155static void __init
2156serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2157{
2158 int i;
2159
2160 serial8250_isa_init_ports();
2161
2162 for (i = 0; i < UART_NR; i++) {
2163 struct uart_8250_port *up = &serial8250_ports[i];
2164
2165 up->port.dev = dev;
2166 uart_add_one_port(drv, &up->port);
2167 }
2168}
2169
2170#ifdef CONFIG_SERIAL_8250_CONSOLE
2171
2172#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2173
2174/*
2175 * Wait for transmitter & holding register to empty
2176 */
2177static inline void wait_for_xmitr(struct uart_8250_port *up)
2178{
2179 unsigned int status, tmout = 10000;
2180
2181 /* Wait up to 10ms for the character(s) to be sent. */
2182 do {
2183 status = serial_in(up, UART_LSR);
2184
2185 if (status & UART_LSR_BI)
2186 up->lsr_break_flag = UART_LSR_BI;
2187
2188 if (--tmout == 0)
2189 break;
2190 udelay(1);
2191 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2192
2193 /* Wait up to 1s for flow control if necessary */
2194 if (up->port.flags & UPF_CONS_FLOW) {
2195 tmout = 1000000;
2196 while (--tmout &&
2197 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2198 udelay(1);
2199 }
2200}
2201
2202/*
2203 * Print a string to the serial port trying not to disturb
2204 * any possible real use of the port...
2205 *
2206 * The console_lock must be held when we get here.
2207 */
2208static void
2209serial8250_console_write(struct console *co, const char *s, unsigned int count)
2210{
2211 struct uart_8250_port *up = &serial8250_ports[co->index];
2212 unsigned int ier;
2213 int i;
2214
78512ece
AM		 2215 touch_nmi_watchdog();
2216
1da177e4
LT		 2217 /*
2218 * First save the UER then disable the interrupts
2219 */
2220 ier = serial_in(up, UART_IER);
2221
2222 if (up->capabilities & UART_CAP_UUE)
2223 serial_out(up, UART_IER, UART_IER_UUE);
2224 else
2225 serial_out(up, UART_IER, 0);
2226
2227 /*
2228 * Now, do each character
2229 */
2230 for (i = 0; i < count; i++, s++) {
2231 wait_for_xmitr(up);
2232
2233 /*
2234 * Send the character out.
2235 * If a LF, also do CR...
2236 */
2237 serial_out(up, UART_TX, *s);
2238 if (*s == 10) {
2239 wait_for_xmitr(up);
2240 serial_out(up, UART_TX, 13);
2241 }
2242 }
2243
2244 /*
2245 * Finally, wait for transmitter to become empty
2246 * and restore the IER
2247 */
2248 wait_for_xmitr(up);
2249 serial_out(up, UART_IER, ier);
2250}
2251
2252static int serial8250_console_setup(struct console *co, char *options)
2253{
2254 struct uart_port *port;
2255 int baud = 9600;
2256 int bits = 8;
2257 int parity = 'n';
2258 int flow = 'n';
2259
2260 /*
2261 * Check whether an invalid uart number has been specified, and
2262 * if so, search for the first available port that does have
2263 * console support.
2264 */
2265 if (co->index >= UART_NR)
2266 co->index = 0;
2267 port = &serial8250_ports[co->index].port;
2268 if (!port->iobase && !port->membase)
2269 return -ENODEV;
2270
2271 if (options)
2272 uart_parse_options(options, &baud, &parity, &bits, &flow);
2273
2274 return uart_set_options(port, co, baud, parity, bits, flow);
2275}
2276
2277static struct uart_driver serial8250_reg;
2278static struct console serial8250_console = {
2279 .name = "ttyS",
2280 .write = serial8250_console_write,
2281 .device = uart_console_device,
2282 .setup = serial8250_console_setup,
2283 .flags = CON_PRINTBUFFER,
2284 .index = -1,
2285 .data = &serial8250_reg,
2286};
2287
2288static int __init serial8250_console_init(void)
2289{
2290 serial8250_isa_init_ports();
2291 register_console(&serial8250_console);
2292 return 0;
2293}
2294console_initcall(serial8250_console_init);
2295
2296static int __init find_port(struct uart_port *p)
2297{
2298 int line;
2299 struct uart_port *port;
2300
2301 for (line = 0; line < UART_NR; line++) {
2302 port = &serial8250_ports[line].port;
2303 if (p->iotype == port->iotype &&
2304 p->iobase == port->iobase &&
2305 p->membase == port->membase)
2306 return line;
2307 }
2308 return -ENODEV;
2309}
2310
2311int __init serial8250_start_console(struct uart_port *port, char *options)
2312{
2313 int line;
2314
2315 line = find_port(port);
2316 if (line < 0)
2317 return -ENODEV;
2318
2319 add_preferred_console("ttyS", line, options);
2320 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2321 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2322 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2323 (unsigned long) port->iobase, options);
2324 if (!(serial8250_console.flags & CON_ENABLED)) {
2325 serial8250_console.flags &= ~CON_PRINTBUFFER;
2326 register_console(&serial8250_console);
2327 }
2328 return line;
2329}
2330
2331#define SERIAL8250_CONSOLE &serial8250_console
2332#else
2333#define SERIAL8250_CONSOLE NULL
2334#endif
2335
2336static struct uart_driver serial8250_reg = {
2337 .owner = THIS_MODULE,
2338 .driver_name = "serial",
2339 .devfs_name = "tts/",
2340 .dev_name = "ttyS",
2341 .major = TTY_MAJOR,
2342 .minor = 64,
2343 .nr = UART_NR,
2344 .cons = SERIAL8250_CONSOLE,
2345};
2346
2347int __init early_serial_setup(struct uart_port *port)
2348{
2349 if (port->line >= ARRAY_SIZE(serial8250_ports))
2350 return -ENODEV;
2351
2352 serial8250_isa_init_ports();
2353 serial8250_ports[port->line].port = *port;
2354 serial8250_ports[port->line].port.ops = &serial8250_pops;
2355 return 0;
2356}
2357
2358/**
2359 * serial8250_suspend_port - suspend one serial port
2360 * @line: serial line number
2361 * @level: the level of port suspension, as per uart_suspend_port
2362 *
2363 * Suspend one serial port.
2364 */
2365void serial8250_suspend_port(int line)
2366{
2367 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2368}
2369
2370/**
2371 * serial8250_resume_port - resume one serial port
2372 * @line: serial line number
2373 * @level: the level of port resumption, as per uart_resume_port
2374 *
2375 * Resume one serial port.
2376 */
2377void serial8250_resume_port(int line)
2378{
2379 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2380}
2381
2382/*
2383 * Register a set of serial devices attached to a platform device. The
2384 * list is terminated with a zero flags entry, which means we expect
2385 * all entries to have at least UPF_BOOT_AUTOCONF set.
2386 */
3ae5eaec 2387static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2388{
3ae5eaec 2389 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2390 struct uart_port port;
ec9f47cd 2391 int ret, i;
1da177e4
LT		 2392
2393 memset(&port, 0, sizeof(struct uart_port));
2394
ec9f47cd 2395 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2396 port.iobase = p->iobase;
2397 port.membase = p->membase;
2398 port.irq = p->irq;
2399 port.uartclk = p->uartclk;
2400 port.regshift = p->regshift;
2401 port.iotype = p->iotype;
2402 port.flags = p->flags;
2403 port.mapbase = p->mapbase;
ec9f47cd 2404 port.hub6 = p->hub6;
3ae5eaec 2405 port.dev = &dev->dev;
1da177e4
LT		 2406 if (share_irqs)
2407 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2408 ret = serial8250_register_port(&port);
2409 if (ret < 0) {
3ae5eaec 2410 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2411 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2412 p->iobase, p->mapbase, p->irq, ret);
2413 }
1da177e4
LT		 2414 }
2415 return 0;
2416}
2417
2418/*
2419 * Remove serial ports registered against a platform device.
2420 */
3ae5eaec 2421static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2422{
2423 int i;
2424
2425 for (i = 0; i < UART_NR; i++) {
2426 struct uart_8250_port *up = &serial8250_ports[i];
2427
3ae5eaec 2428 if (up->port.dev == &dev->dev)
1da177e4
LT		 2429 serial8250_unregister_port(i);
2430 }
2431 return 0;
2432}
2433
3ae5eaec 2434static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2435{
2436 int i;
2437
1da177e4
LT		 2438 for (i = 0; i < UART_NR; i++) {
2439 struct uart_8250_port *up = &serial8250_ports[i];
2440
3ae5eaec 2441 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2442 uart_suspend_port(&serial8250_reg, &up->port);
2443 }
2444
2445 return 0;
2446}
2447
3ae5eaec 2448static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2449{
2450 int i;
2451
1da177e4
LT		 2452 for (i = 0; i < UART_NR; i++) {
2453 struct uart_8250_port *up = &serial8250_ports[i];
2454
3ae5eaec 2455 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2456 uart_resume_port(&serial8250_reg, &up->port);
2457 }
2458
2459 return 0;
2460}
2461
3ae5eaec 2462static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2463 .probe = serial8250_probe,
2464 .remove = __devexit_p(serial8250_remove),
2465 .suspend = serial8250_suspend,
2466 .resume = serial8250_resume,
3ae5eaec
RK		 2467 .driver = {
2468 .name = "serial8250",
2469 },
1da177e4
LT		 2470};
2471
2472/*
2473 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2474 * in the table in include/asm/serial.h
2475 */
2476static struct platform_device *serial8250_isa_devs;
2477
2478/*
2479 * serial8250_register_port and serial8250_unregister_port allows for
2480 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2481 * modems and PCI multiport cards.
2482 */
2483static DECLARE_MUTEX(serial_sem);
2484
2485static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2486{
2487 int i;
2488
2489 /*
2490 * First, find a port entry which matches.
2491 */
2492 for (i = 0; i < UART_NR; i++)
2493 if (uart_match_port(&serial8250_ports[i].port, port))
2494 return &serial8250_ports[i];
2495
2496 /*
2497 * We didn't find a matching entry, so look for the first
2498 * free entry. We look for one which hasn't been previously
2499 * used (indicated by zero iobase).
2500 */
2501 for (i = 0; i < UART_NR; i++)
2502 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2503 serial8250_ports[i].port.iobase == 0)
2504 return &serial8250_ports[i];
2505
2506 /*
2507 * That also failed. Last resort is to find any entry which
2508 * doesn't have a real port associated with it.
2509 */
2510 for (i = 0; i < UART_NR; i++)
2511 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2512 return &serial8250_ports[i];
2513
2514 return NULL;
2515}
2516
2517/**
2518 * serial8250_register_port - register a serial port
2519 * @port: serial port template
2520 *
2521 * Configure the serial port specified by the request. If the
2522 * port exists and is in use, it is hung up and unregistered
2523 * first.
2524 *
2525 * The port is then probed and if necessary the IRQ is autodetected
2526 * If this fails an error is returned.
2527 *
2528 * On success the port is ready to use and the line number is returned.
2529 */
2530int serial8250_register_port(struct uart_port *port)
2531{
2532 struct uart_8250_port *uart;
2533 int ret = -ENOSPC;
2534
2535 if (port->uartclk == 0)
2536 return -EINVAL;
2537
2538 down(&serial_sem);
2539
2540 uart = serial8250_find_match_or_unused(port);
2541 if (uart) {
2542 uart_remove_one_port(&serial8250_reg, &uart->port);
2543
2544 uart->port.iobase = port->iobase;
2545 uart->port.membase = port->membase;
2546 uart->port.irq = port->irq;
2547 uart->port.uartclk = port->uartclk;
2548 uart->port.fifosize = port->fifosize;
2549 uart->port.regshift = port->regshift;
2550 uart->port.iotype = port->iotype;
2551 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2552 uart->port.mapbase = port->mapbase;
2553 if (port->dev)
2554 uart->port.dev = port->dev;
2555
2556 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2557 if (ret == 0)
2558 ret = uart->port.line;
2559 }
2560 up(&serial_sem);
2561
2562 return ret;
2563}
2564EXPORT_SYMBOL(serial8250_register_port);
2565
2566/**
2567 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2568 * @line: serial line number
2569 *
2570 * Remove one serial port. This may not be called from interrupt
2571 * context. We hand the port back to the our control.
2572 */
2573void serial8250_unregister_port(int line)
2574{
2575 struct uart_8250_port *uart = &serial8250_ports[line];
2576
2577 down(&serial_sem);
2578 uart_remove_one_port(&serial8250_reg, &uart->port);
2579 if (serial8250_isa_devs) {
2580 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2581 uart->port.type = PORT_UNKNOWN;
2582 uart->port.dev = &serial8250_isa_devs->dev;
2583 uart_add_one_port(&serial8250_reg, &uart->port);
2584 } else {
2585 uart->port.dev = NULL;
2586 }
2587 up(&serial_sem);
2588}
2589EXPORT_SYMBOL(serial8250_unregister_port);
2590
2591static int __init serial8250_init(void)
2592{
2593 int ret, i;
2594
2595 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2596 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2597 share_irqs ? "en" : "dis");
2598
2599 for (i = 0; i < NR_IRQS; i++)
2600 spin_lock_init(&irq_lists[i].lock);
2601
2602 ret = uart_register_driver(&serial8250_reg);
2603 if (ret)
2604 goto out;
2605
2606 serial8250_isa_devs = platform_device_register_simple("serial8250",
6df29deb 2607 PLAT8250_DEV_LEGACY, NULL, 0);
1da177e4
LT		 2608 if (IS_ERR(serial8250_isa_devs)) {
2609 ret = PTR_ERR(serial8250_isa_devs);
2610 goto unreg;
2611 }
2612
2613 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2614
3ae5eaec 2615 ret = platform_driver_register(&serial8250_isa_driver);
1da177e4
LT		 2616 if (ret == 0)
2617 goto out;
2618
2619 platform_device_unregister(serial8250_isa_devs);
2620 unreg:
2621 uart_unregister_driver(&serial8250_reg);
2622 out:
2623 return ret;
2624}
2625
2626static void __exit serial8250_exit(void)
2627{
2628 struct platform_device *isa_dev = serial8250_isa_devs;
2629
2630 /*
2631 * This tells serial8250_unregister_port() not to re-register
2632 * the ports (thereby making serial8250_isa_driver permanently
2633 * in use.)
2634 */
2635 serial8250_isa_devs = NULL;
2636
3ae5eaec 2637 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2638 platform_device_unregister(isa_dev);
2639
2640 uart_unregister_driver(&serial8250_reg);
2641}
2642
2643module_init(serial8250_init);
2644module_exit(serial8250_exit);
2645
2646EXPORT_SYMBOL(serial8250_suspend_port);
2647EXPORT_SYMBOL(serial8250_resume_port);
2648
2649MODULE_LICENSE("GPL");
2650MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2651
2652module_param(share_irqs, uint, 0644);
2653MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2654 " (unsafe)");
2655
2656#ifdef CONFIG_SERIAL_8250_RSA
2657module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2658MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2659#endif
2660MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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