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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/8250_pci.c | |
3 | * | |
4 | * Probe module for 8250/16550-type PCI serial ports. | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License. | |
13 | * | |
14 | * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $ | |
15 | */ | |
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/string.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/tty.h> | |
25 | #include <linux/serial_core.h> | |
26 | #include <linux/8250_pci.h> | |
27 | #include <linux/bitops.h> | |
28 | ||
29 | #include <asm/byteorder.h> | |
30 | #include <asm/io.h> | |
31 | ||
32 | #include "8250.h" | |
33 | ||
34 | #undef SERIAL_DEBUG_PCI | |
35 | ||
36 | /* | |
37 | * Definitions for PCI support. | |
38 | */ | |
39 | #define FL_BASE_MASK 0x0007 | |
40 | #define FL_BASE0 0x0000 | |
41 | #define FL_BASE1 0x0001 | |
42 | #define FL_BASE2 0x0002 | |
43 | #define FL_BASE3 0x0003 | |
44 | #define FL_BASE4 0x0004 | |
45 | #define FL_GET_BASE(x) (x & FL_BASE_MASK) | |
46 | ||
47 | /* Use successive BARs (PCI base address registers), | |
48 | else use offset into some specified BAR */ | |
49 | #define FL_BASE_BARS 0x0008 | |
50 | ||
51 | /* do not assign an irq */ | |
52 | #define FL_NOIRQ 0x0080 | |
53 | ||
54 | /* Use the Base address register size to cap number of ports */ | |
55 | #define FL_REGION_SZ_CAP 0x0100 | |
56 | ||
57 | struct pci_board { | |
58 | unsigned int flags; | |
59 | unsigned int num_ports; | |
60 | unsigned int base_baud; | |
61 | unsigned int uart_offset; | |
62 | unsigned int reg_shift; | |
63 | unsigned int first_offset; | |
64 | }; | |
65 | ||
66 | /* | |
67 | * init function returns: | |
68 | * > 0 - number of ports | |
69 | * = 0 - use board->num_ports | |
70 | * < 0 - error | |
71 | */ | |
72 | struct pci_serial_quirk { | |
73 | u32 vendor; | |
74 | u32 device; | |
75 | u32 subvendor; | |
76 | u32 subdevice; | |
77 | int (*init)(struct pci_dev *dev); | |
78 | int (*setup)(struct pci_dev *dev, struct pci_board *board, | |
79 | struct uart_port *port, int idx); | |
80 | void (*exit)(struct pci_dev *dev); | |
81 | }; | |
82 | ||
83 | #define PCI_NUM_BAR_RESOURCES 6 | |
84 | ||
85 | struct serial_private { | |
86 | unsigned int nr; | |
87 | void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; | |
88 | struct pci_serial_quirk *quirk; | |
89 | int line[0]; | |
90 | }; | |
91 | ||
92 | static void moan_device(const char *str, struct pci_dev *dev) | |
93 | { | |
94 | printk(KERN_WARNING "%s: %s\n" | |
95 | KERN_WARNING "Please send the output of lspci -vv, this\n" | |
96 | KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" | |
97 | KERN_WARNING "manufacturer and name of serial board or\n" | |
98 | KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n", | |
99 | pci_name(dev), str, dev->vendor, dev->device, | |
100 | dev->subsystem_vendor, dev->subsystem_device); | |
101 | } | |
102 | ||
103 | static int | |
104 | setup_port(struct pci_dev *dev, struct uart_port *port, | |
105 | int bar, int offset, int regshift) | |
106 | { | |
107 | struct serial_private *priv = pci_get_drvdata(dev); | |
108 | unsigned long base, len; | |
109 | ||
110 | if (bar >= PCI_NUM_BAR_RESOURCES) | |
111 | return -EINVAL; | |
112 | ||
113 | if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { | |
114 | base = pci_resource_start(dev, bar); | |
115 | len = pci_resource_len(dev, bar); | |
116 | ||
117 | if (!priv->remapped_bar[bar]) | |
118 | priv->remapped_bar[bar] = ioremap(base, len); | |
119 | if (!priv->remapped_bar[bar]) | |
120 | return -ENOMEM; | |
121 | ||
122 | port->iotype = UPIO_MEM; | |
123 | port->mapbase = base + offset; | |
124 | port->membase = priv->remapped_bar[bar] + offset; | |
125 | port->regshift = regshift; | |
126 | } else { | |
127 | base = pci_resource_start(dev, bar) + offset; | |
128 | port->iotype = UPIO_PORT; | |
129 | port->iobase = base; | |
130 | } | |
131 | return 0; | |
132 | } | |
133 | ||
134 | /* | |
135 | * AFAVLAB uses a different mixture of BARs and offsets | |
136 | * Not that ugly ;) -- HW | |
137 | */ | |
138 | static int | |
139 | afavlab_setup(struct pci_dev *dev, struct pci_board *board, | |
140 | struct uart_port *port, int idx) | |
141 | { | |
142 | unsigned int bar, offset = board->first_offset; | |
143 | ||
144 | bar = FL_GET_BASE(board->flags); | |
145 | if (idx < 4) | |
146 | bar += idx; | |
147 | else { | |
148 | bar = 4; | |
149 | offset += (idx - 4) * board->uart_offset; | |
150 | } | |
151 | ||
152 | return setup_port(dev, port, bar, offset, board->reg_shift); | |
153 | } | |
154 | ||
155 | /* | |
156 | * HP's Remote Management Console. The Diva chip came in several | |
157 | * different versions. N-class, L2000 and A500 have two Diva chips, each | |
158 | * with 3 UARTs (the third UART on the second chip is unused). Superdome | |
159 | * and Keystone have one Diva chip with 3 UARTs. Some later machines have | |
160 | * one Diva chip, but it has been expanded to 5 UARTs. | |
161 | */ | |
162 | static int __devinit pci_hp_diva_init(struct pci_dev *dev) | |
163 | { | |
164 | int rc = 0; | |
165 | ||
166 | switch (dev->subsystem_device) { | |
167 | case PCI_DEVICE_ID_HP_DIVA_TOSCA1: | |
168 | case PCI_DEVICE_ID_HP_DIVA_HALFDOME: | |
169 | case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: | |
170 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | |
171 | rc = 3; | |
172 | break; | |
173 | case PCI_DEVICE_ID_HP_DIVA_TOSCA2: | |
174 | rc = 2; | |
175 | break; | |
176 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: | |
177 | rc = 4; | |
178 | break; | |
179 | case PCI_DEVICE_ID_HP_DIVA_POWERBAR: | |
180 | rc = 1; | |
181 | break; | |
182 | } | |
183 | ||
184 | return rc; | |
185 | } | |
186 | ||
187 | /* | |
188 | * HP's Diva chip puts the 4th/5th serial port further out, and | |
189 | * some serial ports are supposed to be hidden on certain models. | |
190 | */ | |
191 | static int | |
192 | pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board, | |
193 | struct uart_port *port, int idx) | |
194 | { | |
195 | unsigned int offset = board->first_offset; | |
196 | unsigned int bar = FL_GET_BASE(board->flags); | |
197 | ||
198 | switch (dev->subsystem_device) { | |
199 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: | |
200 | if (idx == 3) | |
201 | idx++; | |
202 | break; | |
203 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | |
204 | if (idx > 0) | |
205 | idx++; | |
206 | if (idx > 2) | |
207 | idx++; | |
208 | break; | |
209 | } | |
210 | if (idx > 2) | |
211 | offset = 0x18; | |
212 | ||
213 | offset += idx * board->uart_offset; | |
214 | ||
215 | return setup_port(dev, port, bar, offset, board->reg_shift); | |
216 | } | |
217 | ||
218 | /* | |
219 | * Added for EKF Intel i960 serial boards | |
220 | */ | |
221 | static int __devinit pci_inteli960ni_init(struct pci_dev *dev) | |
222 | { | |
223 | unsigned long oldval; | |
224 | ||
225 | if (!(dev->subsystem_device & 0x1000)) | |
226 | return -ENODEV; | |
227 | ||
228 | /* is firmware started? */ | |
229 | pci_read_config_dword(dev, 0x44, (void*) &oldval); | |
230 | if (oldval == 0x00001000L) { /* RESET value */ | |
231 | printk(KERN_DEBUG "Local i960 firmware missing"); | |
232 | return -ENODEV; | |
233 | } | |
234 | return 0; | |
235 | } | |
236 | ||
237 | /* | |
238 | * Some PCI serial cards using the PLX 9050 PCI interface chip require | |
239 | * that the card interrupt be explicitly enabled or disabled. This | |
240 | * seems to be mainly needed on card using the PLX which also use I/O | |
241 | * mapped memory. | |
242 | */ | |
243 | static int __devinit pci_plx9050_init(struct pci_dev *dev) | |
244 | { | |
245 | u8 irq_config; | |
246 | void __iomem *p; | |
247 | ||
248 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { | |
249 | moan_device("no memory in bar 0", dev); | |
250 | return 0; | |
251 | } | |
252 | ||
253 | irq_config = 0x41; | |
254 | if (dev->vendor == PCI_VENDOR_ID_PANACOM) | |
255 | irq_config = 0x43; | |
256 | if ((dev->vendor == PCI_VENDOR_ID_PLX) && | |
257 | (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) { | |
258 | /* | |
259 | * As the megawolf cards have the int pins active | |
260 | * high, and have 2 UART chips, both ints must be | |
261 | * enabled on the 9050. Also, the UARTS are set in | |
262 | * 16450 mode by default, so we have to enable the | |
263 | * 16C950 'enhanced' mode so that we can use the | |
264 | * deep FIFOs | |
265 | */ | |
266 | irq_config = 0x5b; | |
267 | } | |
268 | ||
269 | /* | |
270 | * enable/disable interrupts | |
271 | */ | |
272 | p = ioremap(pci_resource_start(dev, 0), 0x80); | |
273 | if (p == NULL) | |
274 | return -ENOMEM; | |
275 | writel(irq_config, p + 0x4c); | |
276 | ||
277 | /* | |
278 | * Read the register back to ensure that it took effect. | |
279 | */ | |
280 | readl(p + 0x4c); | |
281 | iounmap(p); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | static void __devexit pci_plx9050_exit(struct pci_dev *dev) | |
287 | { | |
288 | u8 __iomem *p; | |
289 | ||
290 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) | |
291 | return; | |
292 | ||
293 | /* | |
294 | * disable interrupts | |
295 | */ | |
296 | p = ioremap(pci_resource_start(dev, 0), 0x80); | |
297 | if (p != NULL) { | |
298 | writel(0, p + 0x4c); | |
299 | ||
300 | /* | |
301 | * Read the register back to ensure that it took effect. | |
302 | */ | |
303 | readl(p + 0x4c); | |
304 | iounmap(p); | |
305 | } | |
306 | } | |
307 | ||
308 | /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ | |
309 | static int | |
310 | sbs_setup(struct pci_dev *dev, struct pci_board *board, | |
311 | struct uart_port *port, int idx) | |
312 | { | |
313 | unsigned int bar, offset = board->first_offset; | |
314 | ||
315 | bar = 0; | |
316 | ||
317 | if (idx < 4) { | |
318 | /* first four channels map to 0, 0x100, 0x200, 0x300 */ | |
319 | offset += idx * board->uart_offset; | |
320 | } else if (idx < 8) { | |
321 | /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ | |
322 | offset += idx * board->uart_offset + 0xC00; | |
323 | } else /* we have only 8 ports on PMC-OCTALPRO */ | |
324 | return 1; | |
325 | ||
326 | return setup_port(dev, port, bar, offset, board->reg_shift); | |
327 | } | |
328 | ||
329 | /* | |
330 | * This does initialization for PMC OCTALPRO cards: | |
331 | * maps the device memory, resets the UARTs (needed, bc | |
332 | * if the module is removed and inserted again, the card | |
333 | * is in the sleep mode) and enables global interrupt. | |
334 | */ | |
335 | ||
336 | /* global control register offset for SBS PMC-OctalPro */ | |
337 | #define OCT_REG_CR_OFF 0x500 | |
338 | ||
339 | static int __devinit sbs_init(struct pci_dev *dev) | |
340 | { | |
341 | u8 __iomem *p; | |
342 | ||
343 | p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0)); | |
344 | ||
345 | if (p == NULL) | |
346 | return -ENOMEM; | |
347 | /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ | |
348 | writeb(0x10,p + OCT_REG_CR_OFF); | |
349 | udelay(50); | |
350 | writeb(0x0,p + OCT_REG_CR_OFF); | |
351 | ||
352 | /* Set bit-2 (INTENABLE) of Control Register */ | |
353 | writeb(0x4, p + OCT_REG_CR_OFF); | |
354 | iounmap(p); | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | /* | |
360 | * Disables the global interrupt of PMC-OctalPro | |
361 | */ | |
362 | ||
363 | static void __devexit sbs_exit(struct pci_dev *dev) | |
364 | { | |
365 | u8 __iomem *p; | |
366 | ||
367 | p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0)); | |
368 | if (p != NULL) { | |
369 | writeb(0, p + OCT_REG_CR_OFF); | |
370 | } | |
371 | iounmap(p); | |
372 | } | |
373 | ||
374 | /* | |
375 | * SIIG serial cards have an PCI interface chip which also controls | |
376 | * the UART clocking frequency. Each UART can be clocked independently | |
377 | * (except cards equiped with 4 UARTs) and initial clocking settings | |
378 | * are stored in the EEPROM chip. It can cause problems because this | |
379 | * version of serial driver doesn't support differently clocked UART's | |
380 | * on single PCI card. To prevent this, initialization functions set | |
381 | * high frequency clocking for all UART's on given card. It is safe (I | |
382 | * hope) because it doesn't touch EEPROM settings to prevent conflicts | |
383 | * with other OSes (like M$ DOS). | |
384 | * | |
385 | * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 | |
386 | * | |
387 | * There is two family of SIIG serial cards with different PCI | |
388 | * interface chip and different configuration methods: | |
389 | * - 10x cards have control registers in IO and/or memory space; | |
390 | * - 20x cards have control registers in standard PCI configuration space. | |
391 | * | |
392 | * Note: some SIIG cards are probed by the parport_serial object. | |
393 | */ | |
394 | ||
395 | #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) | |
396 | #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) | |
397 | ||
398 | static int pci_siig10x_init(struct pci_dev *dev) | |
399 | { | |
400 | u16 data; | |
401 | void __iomem *p; | |
402 | ||
403 | switch (dev->device & 0xfff8) { | |
404 | case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ | |
405 | data = 0xffdf; | |
406 | break; | |
407 | case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ | |
408 | data = 0xf7ff; | |
409 | break; | |
410 | default: /* 1S1P, 4S */ | |
411 | data = 0xfffb; | |
412 | break; | |
413 | } | |
414 | ||
415 | p = ioremap(pci_resource_start(dev, 0), 0x80); | |
416 | if (p == NULL) | |
417 | return -ENOMEM; | |
418 | ||
419 | writew(readw(p + 0x28) & data, p + 0x28); | |
420 | readw(p + 0x28); | |
421 | iounmap(p); | |
422 | return 0; | |
423 | } | |
424 | ||
425 | #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) | |
426 | #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) | |
427 | ||
428 | static int pci_siig20x_init(struct pci_dev *dev) | |
429 | { | |
430 | u8 data; | |
431 | ||
432 | /* Change clock frequency for the first UART. */ | |
433 | pci_read_config_byte(dev, 0x6f, &data); | |
434 | pci_write_config_byte(dev, 0x6f, data & 0xef); | |
435 | ||
436 | /* If this card has 2 UART, we have to do the same with second UART. */ | |
437 | if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || | |
438 | ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { | |
439 | pci_read_config_byte(dev, 0x73, &data); | |
440 | pci_write_config_byte(dev, 0x73, data & 0xef); | |
441 | } | |
442 | return 0; | |
443 | } | |
444 | ||
445 | int pci_siig10x_fn(struct pci_dev *dev, int enable) | |
446 | { | |
447 | int ret = 0; | |
448 | if (enable) | |
449 | ret = pci_siig10x_init(dev); | |
450 | return ret; | |
451 | } | |
452 | ||
453 | int pci_siig20x_fn(struct pci_dev *dev, int enable) | |
454 | { | |
455 | int ret = 0; | |
456 | if (enable) | |
457 | ret = pci_siig20x_init(dev); | |
458 | return ret; | |
459 | } | |
460 | ||
461 | EXPORT_SYMBOL(pci_siig10x_fn); | |
462 | EXPORT_SYMBOL(pci_siig20x_fn); | |
463 | ||
464 | /* | |
465 | * Timedia has an explosion of boards, and to avoid the PCI table from | |
466 | * growing *huge*, we use this function to collapse some 70 entries | |
467 | * in the PCI table into one, for sanity's and compactness's sake. | |
468 | */ | |
469 | static unsigned short timedia_single_port[] = { | |
470 | 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 | |
471 | }; | |
472 | ||
473 | static unsigned short timedia_dual_port[] = { | |
474 | 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, | |
475 | 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, | |
476 | 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, | |
477 | 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, | |
478 | 0xD079, 0 | |
479 | }; | |
480 | ||
481 | static unsigned short timedia_quad_port[] = { | |
482 | 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, | |
483 | 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, | |
484 | 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, | |
485 | 0xB157, 0 | |
486 | }; | |
487 | ||
488 | static unsigned short timedia_eight_port[] = { | |
489 | 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, | |
490 | 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 | |
491 | }; | |
492 | ||
493 | static struct timedia_struct { | |
494 | int num; | |
495 | unsigned short *ids; | |
496 | } timedia_data[] = { | |
497 | { 1, timedia_single_port }, | |
498 | { 2, timedia_dual_port }, | |
499 | { 4, timedia_quad_port }, | |
500 | { 8, timedia_eight_port }, | |
501 | { 0, NULL } | |
502 | }; | |
503 | ||
504 | static int __devinit pci_timedia_init(struct pci_dev *dev) | |
505 | { | |
506 | unsigned short *ids; | |
507 | int i, j; | |
508 | ||
509 | for (i = 0; timedia_data[i].num; i++) { | |
510 | ids = timedia_data[i].ids; | |
511 | for (j = 0; ids[j]; j++) | |
512 | if (dev->subsystem_device == ids[j]) | |
513 | return timedia_data[i].num; | |
514 | } | |
515 | return 0; | |
516 | } | |
517 | ||
518 | /* | |
519 | * Timedia/SUNIX uses a mixture of BARs and offsets | |
520 | * Ugh, this is ugly as all hell --- TYT | |
521 | */ | |
522 | static int | |
523 | pci_timedia_setup(struct pci_dev *dev, struct pci_board *board, | |
524 | struct uart_port *port, int idx) | |
525 | { | |
526 | unsigned int bar = 0, offset = board->first_offset; | |
527 | ||
528 | switch (idx) { | |
529 | case 0: | |
530 | bar = 0; | |
531 | break; | |
532 | case 1: | |
533 | offset = board->uart_offset; | |
534 | bar = 0; | |
535 | break; | |
536 | case 2: | |
537 | bar = 1; | |
538 | break; | |
539 | case 3: | |
540 | offset = board->uart_offset; | |
541 | bar = 1; | |
542 | case 4: /* BAR 2 */ | |
543 | case 5: /* BAR 3 */ | |
544 | case 6: /* BAR 4 */ | |
545 | case 7: /* BAR 5 */ | |
546 | bar = idx - 2; | |
547 | } | |
548 | ||
549 | return setup_port(dev, port, bar, offset, board->reg_shift); | |
550 | } | |
551 | ||
552 | /* | |
553 | * Some Titan cards are also a little weird | |
554 | */ | |
555 | static int | |
556 | titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board, | |
557 | struct uart_port *port, int idx) | |
558 | { | |
559 | unsigned int bar, offset = board->first_offset; | |
560 | ||
561 | switch (idx) { | |
562 | case 0: | |
563 | bar = 1; | |
564 | break; | |
565 | case 1: | |
566 | bar = 2; | |
567 | break; | |
568 | default: | |
569 | bar = 4; | |
570 | offset = (idx - 2) * board->uart_offset; | |
571 | } | |
572 | ||
573 | return setup_port(dev, port, bar, offset, board->reg_shift); | |
574 | } | |
575 | ||
576 | static int __devinit pci_xircom_init(struct pci_dev *dev) | |
577 | { | |
578 | msleep(100); | |
579 | return 0; | |
580 | } | |
581 | ||
582 | static int __devinit pci_netmos_init(struct pci_dev *dev) | |
583 | { | |
584 | /* subdevice 0x00PS means <P> parallel, <S> serial */ | |
585 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
586 | ||
587 | if (num_serial == 0) | |
588 | return -ENODEV; | |
589 | return num_serial; | |
590 | } | |
591 | ||
592 | static int | |
593 | pci_default_setup(struct pci_dev *dev, struct pci_board *board, | |
594 | struct uart_port *port, int idx) | |
595 | { | |
596 | unsigned int bar, offset = board->first_offset, maxnr; | |
597 | ||
598 | bar = FL_GET_BASE(board->flags); | |
599 | if (board->flags & FL_BASE_BARS) | |
600 | bar += idx; | |
601 | else | |
602 | offset += idx * board->uart_offset; | |
603 | ||
604 | maxnr = (pci_resource_len(dev, bar) - board->first_offset) / | |
605 | (8 << board->reg_shift); | |
606 | ||
607 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) | |
608 | return 1; | |
609 | ||
610 | return setup_port(dev, port, bar, offset, board->reg_shift); | |
611 | } | |
612 | ||
613 | /* This should be in linux/pci_ids.h */ | |
614 | #define PCI_VENDOR_ID_SBSMODULARIO 0x124B | |
615 | #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B | |
616 | #define PCI_DEVICE_ID_OCTPRO 0x0001 | |
617 | #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 | |
618 | #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 | |
619 | #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 | |
620 | #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 | |
621 | ||
622 | /* | |
623 | * Master list of serial port init/setup/exit quirks. | |
624 | * This does not describe the general nature of the port. | |
625 | * (ie, baud base, number and location of ports, etc) | |
626 | * | |
627 | * This list is ordered alphabetically by vendor then device. | |
628 | * Specific entries must come before more generic entries. | |
629 | */ | |
630 | static struct pci_serial_quirk pci_serial_quirks[] = { | |
631 | /* | |
632 | * AFAVLAB cards. | |
633 | * It is not clear whether this applies to all products. | |
634 | */ | |
635 | { | |
636 | .vendor = PCI_VENDOR_ID_AFAVLAB, | |
637 | .device = PCI_ANY_ID, | |
638 | .subvendor = PCI_ANY_ID, | |
639 | .subdevice = PCI_ANY_ID, | |
640 | .setup = afavlab_setup, | |
641 | }, | |
642 | /* | |
643 | * HP Diva | |
644 | */ | |
645 | { | |
646 | .vendor = PCI_VENDOR_ID_HP, | |
647 | .device = PCI_DEVICE_ID_HP_DIVA, | |
648 | .subvendor = PCI_ANY_ID, | |
649 | .subdevice = PCI_ANY_ID, | |
650 | .init = pci_hp_diva_init, | |
651 | .setup = pci_hp_diva_setup, | |
652 | }, | |
653 | /* | |
654 | * Intel | |
655 | */ | |
656 | { | |
657 | .vendor = PCI_VENDOR_ID_INTEL, | |
658 | .device = PCI_DEVICE_ID_INTEL_80960_RP, | |
659 | .subvendor = 0xe4bf, | |
660 | .subdevice = PCI_ANY_ID, | |
661 | .init = pci_inteli960ni_init, | |
662 | .setup = pci_default_setup, | |
663 | }, | |
664 | /* | |
665 | * Panacom | |
666 | */ | |
667 | { | |
668 | .vendor = PCI_VENDOR_ID_PANACOM, | |
669 | .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, | |
670 | .subvendor = PCI_ANY_ID, | |
671 | .subdevice = PCI_ANY_ID, | |
672 | .init = pci_plx9050_init, | |
673 | .setup = pci_default_setup, | |
674 | .exit = __devexit_p(pci_plx9050_exit), | |
675 | }, | |
676 | { | |
677 | .vendor = PCI_VENDOR_ID_PANACOM, | |
678 | .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, | |
679 | .subvendor = PCI_ANY_ID, | |
680 | .subdevice = PCI_ANY_ID, | |
681 | .init = pci_plx9050_init, | |
682 | .setup = pci_default_setup, | |
683 | .exit = __devexit_p(pci_plx9050_exit), | |
684 | }, | |
685 | /* | |
686 | * PLX | |
687 | */ | |
688 | { | |
689 | .vendor = PCI_VENDOR_ID_PLX, | |
690 | .device = PCI_DEVICE_ID_PLX_9050, | |
691 | .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, | |
692 | .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, | |
693 | .init = pci_plx9050_init, | |
694 | .setup = pci_default_setup, | |
695 | .exit = __devexit_p(pci_plx9050_exit), | |
696 | }, | |
697 | { | |
698 | .vendor = PCI_VENDOR_ID_PLX, | |
699 | .device = PCI_DEVICE_ID_PLX_ROMULUS, | |
700 | .subvendor = PCI_VENDOR_ID_PLX, | |
701 | .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, | |
702 | .init = pci_plx9050_init, | |
703 | .setup = pci_default_setup, | |
704 | .exit = __devexit_p(pci_plx9050_exit), | |
705 | }, | |
706 | /* | |
707 | * SBS Technologies, Inc., PMC-OCTALPRO 232 | |
708 | */ | |
709 | { | |
710 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
711 | .device = PCI_DEVICE_ID_OCTPRO, | |
712 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
713 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, | |
714 | .init = sbs_init, | |
715 | .setup = sbs_setup, | |
716 | .exit = __devexit_p(sbs_exit), | |
717 | }, | |
718 | /* | |
719 | * SBS Technologies, Inc., PMC-OCTALPRO 422 | |
720 | */ | |
721 | { | |
722 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
723 | .device = PCI_DEVICE_ID_OCTPRO, | |
724 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
725 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, | |
726 | .init = sbs_init, | |
727 | .setup = sbs_setup, | |
728 | .exit = __devexit_p(sbs_exit), | |
729 | }, | |
730 | /* | |
731 | * SBS Technologies, Inc., P-Octal 232 | |
732 | */ | |
733 | { | |
734 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
735 | .device = PCI_DEVICE_ID_OCTPRO, | |
736 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
737 | .subdevice = PCI_SUBDEVICE_ID_POCTAL232, | |
738 | .init = sbs_init, | |
739 | .setup = sbs_setup, | |
740 | .exit = __devexit_p(sbs_exit), | |
741 | }, | |
742 | /* | |
743 | * SBS Technologies, Inc., P-Octal 422 | |
744 | */ | |
745 | { | |
746 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
747 | .device = PCI_DEVICE_ID_OCTPRO, | |
748 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
749 | .subdevice = PCI_SUBDEVICE_ID_POCTAL422, | |
750 | .init = sbs_init, | |
751 | .setup = sbs_setup, | |
752 | .exit = __devexit_p(sbs_exit), | |
753 | }, | |
754 | ||
755 | /* | |
756 | * SIIG cards. | |
757 | * It is not clear whether these could be collapsed. | |
758 | */ | |
759 | { | |
760 | .vendor = PCI_VENDOR_ID_SIIG, | |
761 | .device = PCI_DEVICE_ID_SIIG_1S_10x_550, | |
762 | .subvendor = PCI_ANY_ID, | |
763 | .subdevice = PCI_ANY_ID, | |
764 | .init = pci_siig10x_init, | |
765 | .setup = pci_default_setup, | |
766 | }, | |
767 | { | |
768 | .vendor = PCI_VENDOR_ID_SIIG, | |
769 | .device = PCI_DEVICE_ID_SIIG_1S_10x_650, | |
770 | .subvendor = PCI_ANY_ID, | |
771 | .subdevice = PCI_ANY_ID, | |
772 | .init = pci_siig10x_init, | |
773 | .setup = pci_default_setup, | |
774 | }, | |
775 | { | |
776 | .vendor = PCI_VENDOR_ID_SIIG, | |
777 | .device = PCI_DEVICE_ID_SIIG_1S_10x_850, | |
778 | .subvendor = PCI_ANY_ID, | |
779 | .subdevice = PCI_ANY_ID, | |
780 | .init = pci_siig10x_init, | |
781 | .setup = pci_default_setup, | |
782 | }, | |
783 | { | |
784 | .vendor = PCI_VENDOR_ID_SIIG, | |
785 | .device = PCI_DEVICE_ID_SIIG_2S_10x_550, | |
786 | .subvendor = PCI_ANY_ID, | |
787 | .subdevice = PCI_ANY_ID, | |
788 | .init = pci_siig10x_init, | |
789 | .setup = pci_default_setup, | |
790 | }, | |
791 | { | |
792 | .vendor = PCI_VENDOR_ID_SIIG, | |
793 | .device = PCI_DEVICE_ID_SIIG_2S_10x_650, | |
794 | .subvendor = PCI_ANY_ID, | |
795 | .subdevice = PCI_ANY_ID, | |
796 | .init = pci_siig10x_init, | |
797 | .setup = pci_default_setup, | |
798 | }, | |
799 | { | |
800 | .vendor = PCI_VENDOR_ID_SIIG, | |
801 | .device = PCI_DEVICE_ID_SIIG_2S_10x_850, | |
802 | .subvendor = PCI_ANY_ID, | |
803 | .subdevice = PCI_ANY_ID, | |
804 | .init = pci_siig10x_init, | |
805 | .setup = pci_default_setup, | |
806 | }, | |
807 | { | |
808 | .vendor = PCI_VENDOR_ID_SIIG, | |
809 | .device = PCI_DEVICE_ID_SIIG_4S_10x_550, | |
810 | .subvendor = PCI_ANY_ID, | |
811 | .subdevice = PCI_ANY_ID, | |
812 | .init = pci_siig10x_init, | |
813 | .setup = pci_default_setup, | |
814 | }, | |
815 | { | |
816 | .vendor = PCI_VENDOR_ID_SIIG, | |
817 | .device = PCI_DEVICE_ID_SIIG_4S_10x_650, | |
818 | .subvendor = PCI_ANY_ID, | |
819 | .subdevice = PCI_ANY_ID, | |
820 | .init = pci_siig10x_init, | |
821 | .setup = pci_default_setup, | |
822 | }, | |
823 | { | |
824 | .vendor = PCI_VENDOR_ID_SIIG, | |
825 | .device = PCI_DEVICE_ID_SIIG_4S_10x_850, | |
826 | .subvendor = PCI_ANY_ID, | |
827 | .subdevice = PCI_ANY_ID, | |
828 | .init = pci_siig10x_init, | |
829 | .setup = pci_default_setup, | |
830 | }, | |
831 | { | |
832 | .vendor = PCI_VENDOR_ID_SIIG, | |
833 | .device = PCI_DEVICE_ID_SIIG_1S_20x_550, | |
834 | .subvendor = PCI_ANY_ID, | |
835 | .subdevice = PCI_ANY_ID, | |
836 | .init = pci_siig20x_init, | |
837 | .setup = pci_default_setup, | |
838 | }, | |
839 | { | |
840 | .vendor = PCI_VENDOR_ID_SIIG, | |
841 | .device = PCI_DEVICE_ID_SIIG_1S_20x_650, | |
842 | .subvendor = PCI_ANY_ID, | |
843 | .subdevice = PCI_ANY_ID, | |
844 | .init = pci_siig20x_init, | |
845 | .setup = pci_default_setup, | |
846 | }, | |
847 | { | |
848 | .vendor = PCI_VENDOR_ID_SIIG, | |
849 | .device = PCI_DEVICE_ID_SIIG_1S_20x_850, | |
850 | .subvendor = PCI_ANY_ID, | |
851 | .subdevice = PCI_ANY_ID, | |
852 | .init = pci_siig20x_init, | |
853 | .setup = pci_default_setup, | |
854 | }, | |
855 | { | |
856 | .vendor = PCI_VENDOR_ID_SIIG, | |
857 | .device = PCI_DEVICE_ID_SIIG_2S_20x_550, | |
858 | .subvendor = PCI_ANY_ID, | |
859 | .subdevice = PCI_ANY_ID, | |
860 | .init = pci_siig20x_init, | |
861 | .setup = pci_default_setup, | |
862 | }, | |
863 | { .vendor = PCI_VENDOR_ID_SIIG, | |
864 | .device = PCI_DEVICE_ID_SIIG_2S_20x_650, | |
865 | .subvendor = PCI_ANY_ID, | |
866 | .subdevice = PCI_ANY_ID, | |
867 | .init = pci_siig20x_init, | |
868 | .setup = pci_default_setup, | |
869 | }, | |
870 | { | |
871 | .vendor = PCI_VENDOR_ID_SIIG, | |
872 | .device = PCI_DEVICE_ID_SIIG_2S_20x_850, | |
873 | .subvendor = PCI_ANY_ID, | |
874 | .subdevice = PCI_ANY_ID, | |
875 | .init = pci_siig20x_init, | |
876 | .setup = pci_default_setup, | |
877 | }, | |
878 | { | |
879 | .vendor = PCI_VENDOR_ID_SIIG, | |
880 | .device = PCI_DEVICE_ID_SIIG_4S_20x_550, | |
881 | .subvendor = PCI_ANY_ID, | |
882 | .subdevice = PCI_ANY_ID, | |
883 | .init = pci_siig20x_init, | |
884 | .setup = pci_default_setup, | |
885 | }, | |
886 | { | |
887 | .vendor = PCI_VENDOR_ID_SIIG, | |
888 | .device = PCI_DEVICE_ID_SIIG_4S_20x_650, | |
889 | .subvendor = PCI_ANY_ID, | |
890 | .subdevice = PCI_ANY_ID, | |
891 | .init = pci_siig20x_init, | |
892 | .setup = pci_default_setup, | |
893 | }, | |
894 | { | |
895 | .vendor = PCI_VENDOR_ID_SIIG, | |
896 | .device = PCI_DEVICE_ID_SIIG_4S_20x_850, | |
897 | .subvendor = PCI_ANY_ID, | |
898 | .subdevice = PCI_ANY_ID, | |
899 | .init = pci_siig20x_init, | |
900 | .setup = pci_default_setup, | |
901 | }, | |
902 | /* | |
903 | * Titan cards | |
904 | */ | |
905 | { | |
906 | .vendor = PCI_VENDOR_ID_TITAN, | |
907 | .device = PCI_DEVICE_ID_TITAN_400L, | |
908 | .subvendor = PCI_ANY_ID, | |
909 | .subdevice = PCI_ANY_ID, | |
910 | .setup = titan_400l_800l_setup, | |
911 | }, | |
912 | { | |
913 | .vendor = PCI_VENDOR_ID_TITAN, | |
914 | .device = PCI_DEVICE_ID_TITAN_800L, | |
915 | .subvendor = PCI_ANY_ID, | |
916 | .subdevice = PCI_ANY_ID, | |
917 | .setup = titan_400l_800l_setup, | |
918 | }, | |
919 | /* | |
920 | * Timedia cards | |
921 | */ | |
922 | { | |
923 | .vendor = PCI_VENDOR_ID_TIMEDIA, | |
924 | .device = PCI_DEVICE_ID_TIMEDIA_1889, | |
925 | .subvendor = PCI_VENDOR_ID_TIMEDIA, | |
926 | .subdevice = PCI_ANY_ID, | |
927 | .init = pci_timedia_init, | |
928 | .setup = pci_timedia_setup, | |
929 | }, | |
930 | { | |
931 | .vendor = PCI_VENDOR_ID_TIMEDIA, | |
932 | .device = PCI_ANY_ID, | |
933 | .subvendor = PCI_ANY_ID, | |
934 | .subdevice = PCI_ANY_ID, | |
935 | .setup = pci_timedia_setup, | |
936 | }, | |
937 | /* | |
938 | * Xircom cards | |
939 | */ | |
940 | { | |
941 | .vendor = PCI_VENDOR_ID_XIRCOM, | |
942 | .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, | |
943 | .subvendor = PCI_ANY_ID, | |
944 | .subdevice = PCI_ANY_ID, | |
945 | .init = pci_xircom_init, | |
946 | .setup = pci_default_setup, | |
947 | }, | |
948 | /* | |
949 | * Netmos cards | |
950 | */ | |
951 | { | |
952 | .vendor = PCI_VENDOR_ID_NETMOS, | |
953 | .device = PCI_ANY_ID, | |
954 | .subvendor = PCI_ANY_ID, | |
955 | .subdevice = PCI_ANY_ID, | |
956 | .init = pci_netmos_init, | |
957 | .setup = pci_default_setup, | |
958 | }, | |
959 | /* | |
960 | * Default "match everything" terminator entry | |
961 | */ | |
962 | { | |
963 | .vendor = PCI_ANY_ID, | |
964 | .device = PCI_ANY_ID, | |
965 | .subvendor = PCI_ANY_ID, | |
966 | .subdevice = PCI_ANY_ID, | |
967 | .setup = pci_default_setup, | |
968 | } | |
969 | }; | |
970 | ||
971 | static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) | |
972 | { | |
973 | return quirk_id == PCI_ANY_ID || quirk_id == dev_id; | |
974 | } | |
975 | ||
976 | static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) | |
977 | { | |
978 | struct pci_serial_quirk *quirk; | |
979 | ||
980 | for (quirk = pci_serial_quirks; ; quirk++) | |
981 | if (quirk_id_matches(quirk->vendor, dev->vendor) && | |
982 | quirk_id_matches(quirk->device, dev->device) && | |
983 | quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && | |
984 | quirk_id_matches(quirk->subdevice, dev->subsystem_device)) | |
985 | break; | |
986 | return quirk; | |
987 | } | |
988 | ||
989 | static _INLINE_ int | |
990 | get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx) | |
991 | { | |
992 | if (board->flags & FL_NOIRQ) | |
993 | return 0; | |
994 | else | |
995 | return dev->irq; | |
996 | } | |
997 | ||
998 | /* | |
999 | * This is the configuration table for all of the PCI serial boards | |
1000 | * which we support. It is directly indexed by the pci_board_num_t enum | |
1001 | * value, which is encoded in the pci_device_id PCI probe table's | |
1002 | * driver_data member. | |
1003 | * | |
1004 | * The makeup of these names are: | |
1005 | * pbn_bn{_bt}_n_baud | |
1006 | * | |
1007 | * bn = PCI BAR number | |
1008 | * bt = Index using PCI BARs | |
1009 | * n = number of serial ports | |
1010 | * baud = baud rate | |
1011 | * | |
1012 | * Please note: in theory if n = 1, _bt infix should make no difference. | |
1013 | * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 | |
1014 | */ | |
1015 | enum pci_board_num_t { | |
1016 | pbn_default = 0, | |
1017 | ||
1018 | pbn_b0_1_115200, | |
1019 | pbn_b0_2_115200, | |
1020 | pbn_b0_4_115200, | |
1021 | pbn_b0_5_115200, | |
1022 | ||
1023 | pbn_b0_1_921600, | |
1024 | pbn_b0_2_921600, | |
1025 | pbn_b0_4_921600, | |
1026 | ||
1027 | pbn_b0_bt_1_115200, | |
1028 | pbn_b0_bt_2_115200, | |
1029 | pbn_b0_bt_8_115200, | |
1030 | ||
1031 | pbn_b0_bt_1_460800, | |
1032 | pbn_b0_bt_2_460800, | |
1033 | pbn_b0_bt_4_460800, | |
1034 | ||
1035 | pbn_b0_bt_1_921600, | |
1036 | pbn_b0_bt_2_921600, | |
1037 | pbn_b0_bt_4_921600, | |
1038 | pbn_b0_bt_8_921600, | |
1039 | ||
1040 | pbn_b1_1_115200, | |
1041 | pbn_b1_2_115200, | |
1042 | pbn_b1_4_115200, | |
1043 | pbn_b1_8_115200, | |
1044 | ||
1045 | pbn_b1_1_921600, | |
1046 | pbn_b1_2_921600, | |
1047 | pbn_b1_4_921600, | |
1048 | pbn_b1_8_921600, | |
1049 | ||
1050 | pbn_b1_bt_2_921600, | |
1051 | ||
1052 | pbn_b1_1_1382400, | |
1053 | pbn_b1_2_1382400, | |
1054 | pbn_b1_4_1382400, | |
1055 | pbn_b1_8_1382400, | |
1056 | ||
1057 | pbn_b2_1_115200, | |
1058 | pbn_b2_8_115200, | |
1059 | ||
1060 | pbn_b2_1_460800, | |
1061 | pbn_b2_4_460800, | |
1062 | pbn_b2_8_460800, | |
1063 | pbn_b2_16_460800, | |
1064 | ||
1065 | pbn_b2_1_921600, | |
1066 | pbn_b2_4_921600, | |
1067 | pbn_b2_8_921600, | |
1068 | ||
1069 | pbn_b2_bt_1_115200, | |
1070 | pbn_b2_bt_2_115200, | |
1071 | pbn_b2_bt_4_115200, | |
1072 | ||
1073 | pbn_b2_bt_2_921600, | |
1074 | pbn_b2_bt_4_921600, | |
1075 | ||
1076 | pbn_b3_4_115200, | |
1077 | pbn_b3_8_115200, | |
1078 | ||
1079 | /* | |
1080 | * Board-specific versions. | |
1081 | */ | |
1082 | pbn_panacom, | |
1083 | pbn_panacom2, | |
1084 | pbn_panacom4, | |
1085 | pbn_plx_romulus, | |
1086 | pbn_oxsemi, | |
1087 | pbn_intel_i960, | |
1088 | pbn_sgi_ioc3, | |
1089 | pbn_nec_nile4, | |
1090 | pbn_computone_4, | |
1091 | pbn_computone_6, | |
1092 | pbn_computone_8, | |
1093 | pbn_sbsxrsio, | |
1094 | pbn_exar_XR17C152, | |
1095 | pbn_exar_XR17C154, | |
1096 | pbn_exar_XR17C158, | |
1097 | }; | |
1098 | ||
1099 | /* | |
1100 | * uart_offset - the space between channels | |
1101 | * reg_shift - describes how the UART registers are mapped | |
1102 | * to PCI memory by the card. | |
1103 | * For example IER register on SBS, Inc. PMC-OctPro is located at | |
1104 | * offset 0x10 from the UART base, while UART_IER is defined as 1 | |
1105 | * in include/linux/serial_reg.h, | |
1106 | * see first lines of serial_in() and serial_out() in 8250.c | |
1107 | */ | |
1108 | ||
1109 | static struct pci_board pci_boards[] __devinitdata = { | |
1110 | [pbn_default] = { | |
1111 | .flags = FL_BASE0, | |
1112 | .num_ports = 1, | |
1113 | .base_baud = 115200, | |
1114 | .uart_offset = 8, | |
1115 | }, | |
1116 | [pbn_b0_1_115200] = { | |
1117 | .flags = FL_BASE0, | |
1118 | .num_ports = 1, | |
1119 | .base_baud = 115200, | |
1120 | .uart_offset = 8, | |
1121 | }, | |
1122 | [pbn_b0_2_115200] = { | |
1123 | .flags = FL_BASE0, | |
1124 | .num_ports = 2, | |
1125 | .base_baud = 115200, | |
1126 | .uart_offset = 8, | |
1127 | }, | |
1128 | [pbn_b0_4_115200] = { | |
1129 | .flags = FL_BASE0, | |
1130 | .num_ports = 4, | |
1131 | .base_baud = 115200, | |
1132 | .uart_offset = 8, | |
1133 | }, | |
1134 | [pbn_b0_5_115200] = { | |
1135 | .flags = FL_BASE0, | |
1136 | .num_ports = 5, | |
1137 | .base_baud = 115200, | |
1138 | .uart_offset = 8, | |
1139 | }, | |
1140 | ||
1141 | [pbn_b0_1_921600] = { | |
1142 | .flags = FL_BASE0, | |
1143 | .num_ports = 1, | |
1144 | .base_baud = 921600, | |
1145 | .uart_offset = 8, | |
1146 | }, | |
1147 | [pbn_b0_2_921600] = { | |
1148 | .flags = FL_BASE0, | |
1149 | .num_ports = 2, | |
1150 | .base_baud = 921600, | |
1151 | .uart_offset = 8, | |
1152 | }, | |
1153 | [pbn_b0_4_921600] = { | |
1154 | .flags = FL_BASE0, | |
1155 | .num_ports = 4, | |
1156 | .base_baud = 921600, | |
1157 | .uart_offset = 8, | |
1158 | }, | |
1159 | ||
1160 | [pbn_b0_bt_1_115200] = { | |
1161 | .flags = FL_BASE0|FL_BASE_BARS, | |
1162 | .num_ports = 1, | |
1163 | .base_baud = 115200, | |
1164 | .uart_offset = 8, | |
1165 | }, | |
1166 | [pbn_b0_bt_2_115200] = { | |
1167 | .flags = FL_BASE0|FL_BASE_BARS, | |
1168 | .num_ports = 2, | |
1169 | .base_baud = 115200, | |
1170 | .uart_offset = 8, | |
1171 | }, | |
1172 | [pbn_b0_bt_8_115200] = { | |
1173 | .flags = FL_BASE0|FL_BASE_BARS, | |
1174 | .num_ports = 8, | |
1175 | .base_baud = 115200, | |
1176 | .uart_offset = 8, | |
1177 | }, | |
1178 | ||
1179 | [pbn_b0_bt_1_460800] = { | |
1180 | .flags = FL_BASE0|FL_BASE_BARS, | |
1181 | .num_ports = 1, | |
1182 | .base_baud = 460800, | |
1183 | .uart_offset = 8, | |
1184 | }, | |
1185 | [pbn_b0_bt_2_460800] = { | |
1186 | .flags = FL_BASE0|FL_BASE_BARS, | |
1187 | .num_ports = 2, | |
1188 | .base_baud = 460800, | |
1189 | .uart_offset = 8, | |
1190 | }, | |
1191 | [pbn_b0_bt_4_460800] = { | |
1192 | .flags = FL_BASE0|FL_BASE_BARS, | |
1193 | .num_ports = 4, | |
1194 | .base_baud = 460800, | |
1195 | .uart_offset = 8, | |
1196 | }, | |
1197 | ||
1198 | [pbn_b0_bt_1_921600] = { | |
1199 | .flags = FL_BASE0|FL_BASE_BARS, | |
1200 | .num_ports = 1, | |
1201 | .base_baud = 921600, | |
1202 | .uart_offset = 8, | |
1203 | }, | |
1204 | [pbn_b0_bt_2_921600] = { | |
1205 | .flags = FL_BASE0|FL_BASE_BARS, | |
1206 | .num_ports = 2, | |
1207 | .base_baud = 921600, | |
1208 | .uart_offset = 8, | |
1209 | }, | |
1210 | [pbn_b0_bt_4_921600] = { | |
1211 | .flags = FL_BASE0|FL_BASE_BARS, | |
1212 | .num_ports = 4, | |
1213 | .base_baud = 921600, | |
1214 | .uart_offset = 8, | |
1215 | }, | |
1216 | [pbn_b0_bt_8_921600] = { | |
1217 | .flags = FL_BASE0|FL_BASE_BARS, | |
1218 | .num_ports = 8, | |
1219 | .base_baud = 921600, | |
1220 | .uart_offset = 8, | |
1221 | }, | |
1222 | ||
1223 | [pbn_b1_1_115200] = { | |
1224 | .flags = FL_BASE1, | |
1225 | .num_ports = 1, | |
1226 | .base_baud = 115200, | |
1227 | .uart_offset = 8, | |
1228 | }, | |
1229 | [pbn_b1_2_115200] = { | |
1230 | .flags = FL_BASE1, | |
1231 | .num_ports = 2, | |
1232 | .base_baud = 115200, | |
1233 | .uart_offset = 8, | |
1234 | }, | |
1235 | [pbn_b1_4_115200] = { | |
1236 | .flags = FL_BASE1, | |
1237 | .num_ports = 4, | |
1238 | .base_baud = 115200, | |
1239 | .uart_offset = 8, | |
1240 | }, | |
1241 | [pbn_b1_8_115200] = { | |
1242 | .flags = FL_BASE1, | |
1243 | .num_ports = 8, | |
1244 | .base_baud = 115200, | |
1245 | .uart_offset = 8, | |
1246 | }, | |
1247 | ||
1248 | [pbn_b1_1_921600] = { | |
1249 | .flags = FL_BASE1, | |
1250 | .num_ports = 1, | |
1251 | .base_baud = 921600, | |
1252 | .uart_offset = 8, | |
1253 | }, | |
1254 | [pbn_b1_2_921600] = { | |
1255 | .flags = FL_BASE1, | |
1256 | .num_ports = 2, | |
1257 | .base_baud = 921600, | |
1258 | .uart_offset = 8, | |
1259 | }, | |
1260 | [pbn_b1_4_921600] = { | |
1261 | .flags = FL_BASE1, | |
1262 | .num_ports = 4, | |
1263 | .base_baud = 921600, | |
1264 | .uart_offset = 8, | |
1265 | }, | |
1266 | [pbn_b1_8_921600] = { | |
1267 | .flags = FL_BASE1, | |
1268 | .num_ports = 8, | |
1269 | .base_baud = 921600, | |
1270 | .uart_offset = 8, | |
1271 | }, | |
1272 | ||
1273 | [pbn_b1_bt_2_921600] = { | |
1274 | .flags = FL_BASE1|FL_BASE_BARS, | |
1275 | .num_ports = 2, | |
1276 | .base_baud = 921600, | |
1277 | .uart_offset = 8, | |
1278 | }, | |
1279 | ||
1280 | [pbn_b1_1_1382400] = { | |
1281 | .flags = FL_BASE1, | |
1282 | .num_ports = 1, | |
1283 | .base_baud = 1382400, | |
1284 | .uart_offset = 8, | |
1285 | }, | |
1286 | [pbn_b1_2_1382400] = { | |
1287 | .flags = FL_BASE1, | |
1288 | .num_ports = 2, | |
1289 | .base_baud = 1382400, | |
1290 | .uart_offset = 8, | |
1291 | }, | |
1292 | [pbn_b1_4_1382400] = { | |
1293 | .flags = FL_BASE1, | |
1294 | .num_ports = 4, | |
1295 | .base_baud = 1382400, | |
1296 | .uart_offset = 8, | |
1297 | }, | |
1298 | [pbn_b1_8_1382400] = { | |
1299 | .flags = FL_BASE1, | |
1300 | .num_ports = 8, | |
1301 | .base_baud = 1382400, | |
1302 | .uart_offset = 8, | |
1303 | }, | |
1304 | ||
1305 | [pbn_b2_1_115200] = { | |
1306 | .flags = FL_BASE2, | |
1307 | .num_ports = 1, | |
1308 | .base_baud = 115200, | |
1309 | .uart_offset = 8, | |
1310 | }, | |
1311 | [pbn_b2_8_115200] = { | |
1312 | .flags = FL_BASE2, | |
1313 | .num_ports = 8, | |
1314 | .base_baud = 115200, | |
1315 | .uart_offset = 8, | |
1316 | }, | |
1317 | ||
1318 | [pbn_b2_1_460800] = { | |
1319 | .flags = FL_BASE2, | |
1320 | .num_ports = 1, | |
1321 | .base_baud = 460800, | |
1322 | .uart_offset = 8, | |
1323 | }, | |
1324 | [pbn_b2_4_460800] = { | |
1325 | .flags = FL_BASE2, | |
1326 | .num_ports = 4, | |
1327 | .base_baud = 460800, | |
1328 | .uart_offset = 8, | |
1329 | }, | |
1330 | [pbn_b2_8_460800] = { | |
1331 | .flags = FL_BASE2, | |
1332 | .num_ports = 8, | |
1333 | .base_baud = 460800, | |
1334 | .uart_offset = 8, | |
1335 | }, | |
1336 | [pbn_b2_16_460800] = { | |
1337 | .flags = FL_BASE2, | |
1338 | .num_ports = 16, | |
1339 | .base_baud = 460800, | |
1340 | .uart_offset = 8, | |
1341 | }, | |
1342 | ||
1343 | [pbn_b2_1_921600] = { | |
1344 | .flags = FL_BASE2, | |
1345 | .num_ports = 1, | |
1346 | .base_baud = 921600, | |
1347 | .uart_offset = 8, | |
1348 | }, | |
1349 | [pbn_b2_4_921600] = { | |
1350 | .flags = FL_BASE2, | |
1351 | .num_ports = 4, | |
1352 | .base_baud = 921600, | |
1353 | .uart_offset = 8, | |
1354 | }, | |
1355 | [pbn_b2_8_921600] = { | |
1356 | .flags = FL_BASE2, | |
1357 | .num_ports = 8, | |
1358 | .base_baud = 921600, | |
1359 | .uart_offset = 8, | |
1360 | }, | |
1361 | ||
1362 | [pbn_b2_bt_1_115200] = { | |
1363 | .flags = FL_BASE2|FL_BASE_BARS, | |
1364 | .num_ports = 1, | |
1365 | .base_baud = 115200, | |
1366 | .uart_offset = 8, | |
1367 | }, | |
1368 | [pbn_b2_bt_2_115200] = { | |
1369 | .flags = FL_BASE2|FL_BASE_BARS, | |
1370 | .num_ports = 2, | |
1371 | .base_baud = 115200, | |
1372 | .uart_offset = 8, | |
1373 | }, | |
1374 | [pbn_b2_bt_4_115200] = { | |
1375 | .flags = FL_BASE2|FL_BASE_BARS, | |
1376 | .num_ports = 4, | |
1377 | .base_baud = 115200, | |
1378 | .uart_offset = 8, | |
1379 | }, | |
1380 | ||
1381 | [pbn_b2_bt_2_921600] = { | |
1382 | .flags = FL_BASE2|FL_BASE_BARS, | |
1383 | .num_ports = 2, | |
1384 | .base_baud = 921600, | |
1385 | .uart_offset = 8, | |
1386 | }, | |
1387 | [pbn_b2_bt_4_921600] = { | |
1388 | .flags = FL_BASE2|FL_BASE_BARS, | |
1389 | .num_ports = 4, | |
1390 | .base_baud = 921600, | |
1391 | .uart_offset = 8, | |
1392 | }, | |
1393 | ||
1394 | [pbn_b3_4_115200] = { | |
1395 | .flags = FL_BASE3, | |
1396 | .num_ports = 4, | |
1397 | .base_baud = 115200, | |
1398 | .uart_offset = 8, | |
1399 | }, | |
1400 | [pbn_b3_8_115200] = { | |
1401 | .flags = FL_BASE3, | |
1402 | .num_ports = 8, | |
1403 | .base_baud = 115200, | |
1404 | .uart_offset = 8, | |
1405 | }, | |
1406 | ||
1407 | /* | |
1408 | * Entries following this are board-specific. | |
1409 | */ | |
1410 | ||
1411 | /* | |
1412 | * Panacom - IOMEM | |
1413 | */ | |
1414 | [pbn_panacom] = { | |
1415 | .flags = FL_BASE2, | |
1416 | .num_ports = 2, | |
1417 | .base_baud = 921600, | |
1418 | .uart_offset = 0x400, | |
1419 | .reg_shift = 7, | |
1420 | }, | |
1421 | [pbn_panacom2] = { | |
1422 | .flags = FL_BASE2|FL_BASE_BARS, | |
1423 | .num_ports = 2, | |
1424 | .base_baud = 921600, | |
1425 | .uart_offset = 0x400, | |
1426 | .reg_shift = 7, | |
1427 | }, | |
1428 | [pbn_panacom4] = { | |
1429 | .flags = FL_BASE2|FL_BASE_BARS, | |
1430 | .num_ports = 4, | |
1431 | .base_baud = 921600, | |
1432 | .uart_offset = 0x400, | |
1433 | .reg_shift = 7, | |
1434 | }, | |
1435 | ||
1436 | /* I think this entry is broken - the first_offset looks wrong --rmk */ | |
1437 | [pbn_plx_romulus] = { | |
1438 | .flags = FL_BASE2, | |
1439 | .num_ports = 4, | |
1440 | .base_baud = 921600, | |
1441 | .uart_offset = 8 << 2, | |
1442 | .reg_shift = 2, | |
1443 | .first_offset = 0x03, | |
1444 | }, | |
1445 | ||
1446 | /* | |
1447 | * This board uses the size of PCI Base region 0 to | |
1448 | * signal now many ports are available | |
1449 | */ | |
1450 | [pbn_oxsemi] = { | |
1451 | .flags = FL_BASE0|FL_REGION_SZ_CAP, | |
1452 | .num_ports = 32, | |
1453 | .base_baud = 115200, | |
1454 | .uart_offset = 8, | |
1455 | }, | |
1456 | ||
1457 | /* | |
1458 | * EKF addition for i960 Boards form EKF with serial port. | |
1459 | * Max 256 ports. | |
1460 | */ | |
1461 | [pbn_intel_i960] = { | |
1462 | .flags = FL_BASE0, | |
1463 | .num_ports = 32, | |
1464 | .base_baud = 921600, | |
1465 | .uart_offset = 8 << 2, | |
1466 | .reg_shift = 2, | |
1467 | .first_offset = 0x10000, | |
1468 | }, | |
1469 | [pbn_sgi_ioc3] = { | |
1470 | .flags = FL_BASE0|FL_NOIRQ, | |
1471 | .num_ports = 1, | |
1472 | .base_baud = 458333, | |
1473 | .uart_offset = 8, | |
1474 | .reg_shift = 0, | |
1475 | .first_offset = 0x20178, | |
1476 | }, | |
1477 | ||
1478 | /* | |
1479 | * NEC Vrc-5074 (Nile 4) builtin UART. | |
1480 | */ | |
1481 | [pbn_nec_nile4] = { | |
1482 | .flags = FL_BASE0, | |
1483 | .num_ports = 1, | |
1484 | .base_baud = 520833, | |
1485 | .uart_offset = 8 << 3, | |
1486 | .reg_shift = 3, | |
1487 | .first_offset = 0x300, | |
1488 | }, | |
1489 | ||
1490 | /* | |
1491 | * Computone - uses IOMEM. | |
1492 | */ | |
1493 | [pbn_computone_4] = { | |
1494 | .flags = FL_BASE0, | |
1495 | .num_ports = 4, | |
1496 | .base_baud = 921600, | |
1497 | .uart_offset = 0x40, | |
1498 | .reg_shift = 2, | |
1499 | .first_offset = 0x200, | |
1500 | }, | |
1501 | [pbn_computone_6] = { | |
1502 | .flags = FL_BASE0, | |
1503 | .num_ports = 6, | |
1504 | .base_baud = 921600, | |
1505 | .uart_offset = 0x40, | |
1506 | .reg_shift = 2, | |
1507 | .first_offset = 0x200, | |
1508 | }, | |
1509 | [pbn_computone_8] = { | |
1510 | .flags = FL_BASE0, | |
1511 | .num_ports = 8, | |
1512 | .base_baud = 921600, | |
1513 | .uart_offset = 0x40, | |
1514 | .reg_shift = 2, | |
1515 | .first_offset = 0x200, | |
1516 | }, | |
1517 | [pbn_sbsxrsio] = { | |
1518 | .flags = FL_BASE0, | |
1519 | .num_ports = 8, | |
1520 | .base_baud = 460800, | |
1521 | .uart_offset = 256, | |
1522 | .reg_shift = 4, | |
1523 | }, | |
1524 | /* | |
1525 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART | |
1526 | * Only basic 16550A support. | |
1527 | * XR17C15[24] are not tested, but they should work. | |
1528 | */ | |
1529 | [pbn_exar_XR17C152] = { | |
1530 | .flags = FL_BASE0, | |
1531 | .num_ports = 2, | |
1532 | .base_baud = 921600, | |
1533 | .uart_offset = 0x200, | |
1534 | }, | |
1535 | [pbn_exar_XR17C154] = { | |
1536 | .flags = FL_BASE0, | |
1537 | .num_ports = 4, | |
1538 | .base_baud = 921600, | |
1539 | .uart_offset = 0x200, | |
1540 | }, | |
1541 | [pbn_exar_XR17C158] = { | |
1542 | .flags = FL_BASE0, | |
1543 | .num_ports = 8, | |
1544 | .base_baud = 921600, | |
1545 | .uart_offset = 0x200, | |
1546 | }, | |
1547 | }; | |
1548 | ||
1549 | /* | |
1550 | * Given a complete unknown PCI device, try to use some heuristics to | |
1551 | * guess what the configuration might be, based on the pitiful PCI | |
1552 | * serial specs. Returns 0 on success, 1 on failure. | |
1553 | */ | |
1554 | static int __devinit | |
1555 | serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board) | |
1556 | { | |
1557 | int num_iomem, num_port, first_port = -1, i; | |
1558 | ||
1559 | /* | |
1560 | * If it is not a communications device or the programming | |
1561 | * interface is greater than 6, give up. | |
1562 | * | |
1563 | * (Should we try to make guesses for multiport serial devices | |
1564 | * later?) | |
1565 | */ | |
1566 | if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && | |
1567 | ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || | |
1568 | (dev->class & 0xff) > 6) | |
1569 | return -ENODEV; | |
1570 | ||
1571 | num_iomem = num_port = 0; | |
1572 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | |
1573 | if (pci_resource_flags(dev, i) & IORESOURCE_IO) { | |
1574 | num_port++; | |
1575 | if (first_port == -1) | |
1576 | first_port = i; | |
1577 | } | |
1578 | if (pci_resource_flags(dev, i) & IORESOURCE_MEM) | |
1579 | num_iomem++; | |
1580 | } | |
1581 | ||
1582 | /* | |
1583 | * If there is 1 or 0 iomem regions, and exactly one port, | |
1584 | * use it. We guess the number of ports based on the IO | |
1585 | * region size. | |
1586 | */ | |
1587 | if (num_iomem <= 1 && num_port == 1) { | |
1588 | board->flags = first_port; | |
1589 | board->num_ports = pci_resource_len(dev, first_port) / 8; | |
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | /* | |
1594 | * Now guess if we've got a board which indexes by BARs. | |
1595 | * Each IO BAR should be 8 bytes, and they should follow | |
1596 | * consecutively. | |
1597 | */ | |
1598 | first_port = -1; | |
1599 | num_port = 0; | |
1600 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | |
1601 | if (pci_resource_flags(dev, i) & IORESOURCE_IO && | |
1602 | pci_resource_len(dev, i) == 8 && | |
1603 | (first_port == -1 || (first_port + num_port) == i)) { | |
1604 | num_port++; | |
1605 | if (first_port == -1) | |
1606 | first_port = i; | |
1607 | } | |
1608 | } | |
1609 | ||
1610 | if (num_port > 1) { | |
1611 | board->flags = first_port | FL_BASE_BARS; | |
1612 | board->num_ports = num_port; | |
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | return -ENODEV; | |
1617 | } | |
1618 | ||
1619 | static inline int | |
1620 | serial_pci_matches(struct pci_board *board, struct pci_board *guessed) | |
1621 | { | |
1622 | return | |
1623 | board->num_ports == guessed->num_ports && | |
1624 | board->base_baud == guessed->base_baud && | |
1625 | board->uart_offset == guessed->uart_offset && | |
1626 | board->reg_shift == guessed->reg_shift && | |
1627 | board->first_offset == guessed->first_offset; | |
1628 | } | |
1629 | ||
1630 | /* | |
1631 | * Probe one serial board. Unfortunately, there is no rhyme nor reason | |
1632 | * to the arrangement of serial ports on a PCI card. | |
1633 | */ | |
1634 | static int __devinit | |
1635 | pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) | |
1636 | { | |
1637 | struct serial_private *priv; | |
1638 | struct pci_board *board, tmp; | |
1639 | struct pci_serial_quirk *quirk; | |
1640 | int rc, nr_ports, i; | |
1641 | ||
1642 | if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { | |
1643 | printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n", | |
1644 | ent->driver_data); | |
1645 | return -EINVAL; | |
1646 | } | |
1647 | ||
1648 | board = &pci_boards[ent->driver_data]; | |
1649 | ||
1650 | rc = pci_enable_device(dev); | |
1651 | if (rc) | |
1652 | return rc; | |
1653 | ||
1654 | if (ent->driver_data == pbn_default) { | |
1655 | /* | |
1656 | * Use a copy of the pci_board entry for this; | |
1657 | * avoid changing entries in the table. | |
1658 | */ | |
1659 | memcpy(&tmp, board, sizeof(struct pci_board)); | |
1660 | board = &tmp; | |
1661 | ||
1662 | /* | |
1663 | * We matched one of our class entries. Try to | |
1664 | * determine the parameters of this board. | |
1665 | */ | |
1666 | rc = serial_pci_guess_board(dev, board); | |
1667 | if (rc) | |
1668 | goto disable; | |
1669 | } else { | |
1670 | /* | |
1671 | * We matched an explicit entry. If we are able to | |
1672 | * detect this boards settings with our heuristic, | |
1673 | * then we no longer need this entry. | |
1674 | */ | |
1675 | memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board)); | |
1676 | rc = serial_pci_guess_board(dev, &tmp); | |
1677 | if (rc == 0 && serial_pci_matches(board, &tmp)) | |
1678 | moan_device("Redundant entry in serial pci_table.", | |
1679 | dev); | |
1680 | } | |
1681 | ||
1682 | nr_ports = board->num_ports; | |
1683 | ||
1684 | /* | |
1685 | * Find an init and setup quirks. | |
1686 | */ | |
1687 | quirk = find_quirk(dev); | |
1688 | ||
1689 | /* | |
1690 | * Run the new-style initialization function. | |
1691 | * The initialization function returns: | |
1692 | * <0 - error | |
1693 | * 0 - use board->num_ports | |
1694 | * >0 - number of ports | |
1695 | */ | |
1696 | if (quirk->init) { | |
1697 | rc = quirk->init(dev); | |
1698 | if (rc < 0) | |
1699 | goto disable; | |
1700 | if (rc) | |
1701 | nr_ports = rc; | |
1702 | } | |
1703 | ||
1704 | priv = kmalloc(sizeof(struct serial_private) + | |
1705 | sizeof(unsigned int) * nr_ports, | |
1706 | GFP_KERNEL); | |
1707 | if (!priv) { | |
1708 | rc = -ENOMEM; | |
1709 | goto deinit; | |
1710 | } | |
1711 | ||
1712 | memset(priv, 0, sizeof(struct serial_private) + | |
1713 | sizeof(unsigned int) * nr_ports); | |
1714 | ||
1715 | priv->quirk = quirk; | |
1716 | pci_set_drvdata(dev, priv); | |
1717 | ||
1718 | for (i = 0; i < nr_ports; i++) { | |
1719 | struct uart_port serial_port; | |
1720 | memset(&serial_port, 0, sizeof(struct uart_port)); | |
1721 | ||
1722 | serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | | |
1723 | UPF_SHARE_IRQ; | |
1724 | serial_port.uartclk = board->base_baud * 16; | |
1725 | serial_port.irq = get_pci_irq(dev, board, i); | |
1726 | serial_port.dev = &dev->dev; | |
1727 | if (quirk->setup(dev, board, &serial_port, i)) | |
1728 | break; | |
1729 | #ifdef SERIAL_DEBUG_PCI | |
1730 | printk("Setup PCI port: port %x, irq %d, type %d\n", | |
1731 | serial_port.iobase, serial_port.irq, serial_port.iotype); | |
1732 | #endif | |
1733 | ||
1734 | priv->line[i] = serial8250_register_port(&serial_port); | |
1735 | if (priv->line[i] < 0) { | |
1736 | printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]); | |
1737 | break; | |
1738 | } | |
1739 | } | |
1740 | ||
1741 | priv->nr = i; | |
1742 | ||
1743 | return 0; | |
1744 | ||
1745 | deinit: | |
1746 | if (quirk->exit) | |
1747 | quirk->exit(dev); | |
1748 | disable: | |
1749 | pci_disable_device(dev); | |
1750 | return rc; | |
1751 | } | |
1752 | ||
1753 | static void __devexit pciserial_remove_one(struct pci_dev *dev) | |
1754 | { | |
1755 | struct serial_private *priv = pci_get_drvdata(dev); | |
1756 | ||
1757 | pci_set_drvdata(dev, NULL); | |
1758 | ||
1759 | if (priv) { | |
1760 | struct pci_serial_quirk *quirk; | |
1761 | int i; | |
1762 | ||
1763 | for (i = 0; i < priv->nr; i++) | |
1764 | serial8250_unregister_port(priv->line[i]); | |
1765 | ||
1766 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | |
1767 | if (priv->remapped_bar[i]) | |
1768 | iounmap(priv->remapped_bar[i]); | |
1769 | priv->remapped_bar[i] = NULL; | |
1770 | } | |
1771 | ||
1772 | /* | |
1773 | * Find the exit quirks. | |
1774 | */ | |
1775 | quirk = find_quirk(dev); | |
1776 | if (quirk->exit) | |
1777 | quirk->exit(dev); | |
1778 | ||
1779 | pci_disable_device(dev); | |
1780 | ||
1781 | kfree(priv); | |
1782 | } | |
1783 | } | |
1784 | ||
1785 | static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) | |
1786 | { | |
1787 | struct serial_private *priv = pci_get_drvdata(dev); | |
1788 | ||
1789 | if (priv) { | |
1790 | int i; | |
1791 | ||
1792 | for (i = 0; i < priv->nr; i++) | |
1793 | serial8250_suspend_port(priv->line[i]); | |
1794 | } | |
1795 | pci_save_state(dev); | |
1796 | pci_set_power_state(dev, pci_choose_state(dev, state)); | |
1797 | return 0; | |
1798 | } | |
1799 | ||
1800 | static int pciserial_resume_one(struct pci_dev *dev) | |
1801 | { | |
1802 | struct serial_private *priv = pci_get_drvdata(dev); | |
1803 | ||
1804 | pci_set_power_state(dev, PCI_D0); | |
1805 | pci_restore_state(dev); | |
1806 | ||
1807 | if (priv) { | |
1808 | int i; | |
1809 | ||
1810 | /* | |
1811 | * The device may have been disabled. Re-enable it. | |
1812 | */ | |
1813 | pci_enable_device(dev); | |
1814 | ||
1815 | /* | |
1816 | * Ensure that the board is correctly configured. | |
1817 | */ | |
1818 | if (priv->quirk->init) | |
1819 | priv->quirk->init(dev); | |
1820 | ||
1821 | for (i = 0; i < priv->nr; i++) | |
1822 | serial8250_resume_port(priv->line[i]); | |
1823 | } | |
1824 | return 0; | |
1825 | } | |
1826 | ||
1827 | static struct pci_device_id serial_pci_tbl[] = { | |
1828 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | |
1829 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1830 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | |
1831 | pbn_b1_8_1382400 }, | |
1832 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | |
1833 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1834 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | |
1835 | pbn_b1_4_1382400 }, | |
1836 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | |
1837 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1838 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | |
1839 | pbn_b1_2_1382400 }, | |
1840 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1841 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1842 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | |
1843 | pbn_b1_8_1382400 }, | |
1844 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1845 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1846 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | |
1847 | pbn_b1_4_1382400 }, | |
1848 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1849 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1850 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | |
1851 | pbn_b1_2_1382400 }, | |
1852 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1853 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1854 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, | |
1855 | pbn_b1_8_921600 }, | |
1856 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1857 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1858 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, | |
1859 | pbn_b1_8_921600 }, | |
1860 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1861 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1862 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, | |
1863 | pbn_b1_4_921600 }, | |
1864 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1865 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1866 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, | |
1867 | pbn_b1_4_921600 }, | |
1868 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1869 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1870 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, | |
1871 | pbn_b1_2_921600 }, | |
1872 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1873 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1874 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, | |
1875 | pbn_b1_8_921600 }, | |
1876 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1877 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1878 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, | |
1879 | pbn_b1_8_921600 }, | |
1880 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
1881 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
1882 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, | |
1883 | pbn_b1_4_921600 }, | |
1884 | ||
1885 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, | |
1886 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1887 | pbn_b2_bt_1_115200 }, | |
1888 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, | |
1889 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1890 | pbn_b2_bt_2_115200 }, | |
1891 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, | |
1892 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1893 | pbn_b2_bt_4_115200 }, | |
1894 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, | |
1895 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1896 | pbn_b2_bt_2_115200 }, | |
1897 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, | |
1898 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1899 | pbn_b2_bt_4_115200 }, | |
1900 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, | |
1901 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1902 | pbn_b2_8_115200 }, | |
1903 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, | |
1904 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1905 | pbn_b2_8_115200 }, | |
1906 | ||
1907 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, | |
1908 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1909 | pbn_b2_bt_2_115200 }, | |
1910 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, | |
1911 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1912 | pbn_b2_bt_2_921600 }, | |
1913 | /* | |
1914 | * VScom SPCOM800, from sl@s.pl | |
1915 | */ | |
1916 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, | |
1917 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1918 | pbn_b2_8_921600 }, | |
1919 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, | |
1920 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1921 | pbn_b2_4_921600 }, | |
1922 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1923 | PCI_SUBVENDOR_ID_KEYSPAN, | |
1924 | PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, | |
1925 | pbn_panacom }, | |
1926 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, | |
1927 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1928 | pbn_panacom4 }, | |
1929 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, | |
1930 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1931 | pbn_panacom2 }, | |
1932 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1933 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
1934 | PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, | |
1935 | pbn_b2_4_460800 }, | |
1936 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1937 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
1938 | PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, | |
1939 | pbn_b2_8_460800 }, | |
1940 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1941 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
1942 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, | |
1943 | pbn_b2_16_460800 }, | |
1944 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1945 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
1946 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, | |
1947 | pbn_b2_16_460800 }, | |
1948 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1949 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | |
1950 | PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, | |
1951 | pbn_b2_4_460800 }, | |
1952 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1953 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | |
1954 | PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, | |
1955 | pbn_b2_8_460800 }, | |
1956 | /* | |
1957 | * Megawolf Romulus PCI Serial Card, from Mike Hudson | |
1958 | * (Exoray@isys.ca) | |
1959 | */ | |
1960 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, | |
1961 | 0x10b5, 0x106a, 0, 0, | |
1962 | pbn_plx_romulus }, | |
1963 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, | |
1964 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1965 | pbn_b1_4_115200 }, | |
1966 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, | |
1967 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1968 | pbn_b1_2_115200 }, | |
1969 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, | |
1970 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1971 | pbn_b1_8_115200 }, | |
1972 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, | |
1973 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1974 | pbn_b1_8_115200 }, | |
1975 | { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, | |
1976 | PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0, | |
1977 | pbn_b0_4_921600 }, | |
1978 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | |
1979 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1980 | pbn_b0_4_115200 }, | |
1981 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, | |
1982 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1983 | pbn_b0_bt_2_921600 }, | |
1984 | ||
1985 | /* | |
1986 | * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, | |
1987 | * from skokodyn@yahoo.com | |
1988 | */ | |
1989 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
1990 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, | |
1991 | pbn_sbsxrsio }, | |
1992 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
1993 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, | |
1994 | pbn_sbsxrsio }, | |
1995 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
1996 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, | |
1997 | pbn_sbsxrsio }, | |
1998 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
1999 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, | |
2000 | pbn_sbsxrsio }, | |
2001 | ||
2002 | /* | |
2003 | * Digitan DS560-558, from jimd@esoft.com | |
2004 | */ | |
2005 | { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, | |
2006 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2007 | pbn_b1_1_115200 }, | |
2008 | ||
2009 | /* | |
2010 | * Titan Electronic cards | |
2011 | * The 400L and 800L have a custom setup quirk. | |
2012 | */ | |
2013 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, | |
2014 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2015 | pbn_b0_1_921600 }, | |
2016 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, | |
2017 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2018 | pbn_b0_2_921600 }, | |
2019 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, | |
2020 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2021 | pbn_b0_4_921600 }, | |
2022 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, | |
2023 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2024 | pbn_b0_4_921600 }, | |
2025 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, | |
2026 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2027 | pbn_b1_1_921600 }, | |
2028 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, | |
2029 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2030 | pbn_b1_bt_2_921600 }, | |
2031 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, | |
2032 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2033 | pbn_b0_bt_4_921600 }, | |
2034 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, | |
2035 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2036 | pbn_b0_bt_8_921600 }, | |
2037 | ||
2038 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, | |
2039 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2040 | pbn_b2_1_460800 }, | |
2041 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, | |
2042 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2043 | pbn_b2_1_460800 }, | |
2044 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, | |
2045 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2046 | pbn_b2_1_460800 }, | |
2047 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, | |
2048 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2049 | pbn_b2_bt_2_921600 }, | |
2050 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, | |
2051 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2052 | pbn_b2_bt_2_921600 }, | |
2053 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, | |
2054 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2055 | pbn_b2_bt_2_921600 }, | |
2056 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, | |
2057 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2058 | pbn_b2_bt_4_921600 }, | |
2059 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, | |
2060 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2061 | pbn_b2_bt_4_921600 }, | |
2062 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, | |
2063 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2064 | pbn_b2_bt_4_921600 }, | |
2065 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, | |
2066 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2067 | pbn_b0_1_921600 }, | |
2068 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, | |
2069 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2070 | pbn_b0_1_921600 }, | |
2071 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, | |
2072 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2073 | pbn_b0_1_921600 }, | |
2074 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, | |
2075 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2076 | pbn_b0_bt_2_921600 }, | |
2077 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, | |
2078 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2079 | pbn_b0_bt_2_921600 }, | |
2080 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, | |
2081 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2082 | pbn_b0_bt_2_921600 }, | |
2083 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, | |
2084 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2085 | pbn_b0_bt_4_921600 }, | |
2086 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, | |
2087 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2088 | pbn_b0_bt_4_921600 }, | |
2089 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, | |
2090 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2091 | pbn_b0_bt_4_921600 }, | |
2092 | ||
2093 | /* | |
2094 | * Computone devices submitted by Doug McNash dmcnash@computone.com | |
2095 | */ | |
2096 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
2097 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, | |
2098 | 0, 0, pbn_computone_4 }, | |
2099 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
2100 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, | |
2101 | 0, 0, pbn_computone_8 }, | |
2102 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
2103 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, | |
2104 | 0, 0, pbn_computone_6 }, | |
2105 | ||
2106 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, | |
2107 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2108 | pbn_oxsemi }, | |
2109 | { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, | |
2110 | PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, | |
2111 | pbn_b0_bt_1_921600 }, | |
2112 | ||
2113 | /* | |
2114 | * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> | |
2115 | */ | |
2116 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, | |
2117 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2118 | pbn_b0_bt_8_115200 }, | |
2119 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, | |
2120 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2121 | pbn_b0_bt_8_115200 }, | |
2122 | ||
2123 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, | |
2124 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2125 | pbn_b0_bt_2_115200 }, | |
2126 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, | |
2127 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2128 | pbn_b0_bt_2_115200 }, | |
2129 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, | |
2130 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2131 | pbn_b0_bt_2_115200 }, | |
2132 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, | |
2133 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2134 | pbn_b0_bt_4_460800 }, | |
2135 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, | |
2136 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2137 | pbn_b0_bt_4_460800 }, | |
2138 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, | |
2139 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2140 | pbn_b0_bt_2_460800 }, | |
2141 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, | |
2142 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2143 | pbn_b0_bt_2_460800 }, | |
2144 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, | |
2145 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2146 | pbn_b0_bt_2_460800 }, | |
2147 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, | |
2148 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2149 | pbn_b0_bt_1_115200 }, | |
2150 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, | |
2151 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2152 | pbn_b0_bt_1_460800 }, | |
2153 | ||
2154 | /* | |
2155 | * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com | |
2156 | */ | |
2157 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, | |
2158 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2159 | pbn_b1_1_1382400 }, | |
2160 | ||
2161 | /* | |
2162 | * Dell Remote Access Card III - Tim_T_Murphy@Dell.com | |
2163 | */ | |
2164 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, | |
2165 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2166 | pbn_b1_1_1382400 }, | |
2167 | ||
2168 | /* | |
2169 | * RAStel 2 port modem, gerg@moreton.com.au | |
2170 | */ | |
2171 | { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, | |
2172 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2173 | pbn_b2_bt_2_115200 }, | |
2174 | ||
2175 | /* | |
2176 | * EKF addition for i960 Boards form EKF with serial port | |
2177 | */ | |
2178 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, | |
2179 | 0xE4BF, PCI_ANY_ID, 0, 0, | |
2180 | pbn_intel_i960 }, | |
2181 | ||
2182 | /* | |
2183 | * Xircom Cardbus/Ethernet combos | |
2184 | */ | |
2185 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, | |
2186 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2187 | pbn_b0_1_115200 }, | |
2188 | /* | |
2189 | * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) | |
2190 | */ | |
2191 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, | |
2192 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2193 | pbn_b0_1_115200 }, | |
2194 | ||
2195 | /* | |
2196 | * Untested PCI modems, sent in from various folks... | |
2197 | */ | |
2198 | ||
2199 | /* | |
2200 | * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> | |
2201 | */ | |
2202 | { PCI_VENDOR_ID_ROCKWELL, 0x1004, | |
2203 | 0x1048, 0x1500, 0, 0, | |
2204 | pbn_b1_1_115200 }, | |
2205 | ||
2206 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, | |
2207 | 0xFF00, 0, 0, 0, | |
2208 | pbn_sgi_ioc3 }, | |
2209 | ||
2210 | /* | |
2211 | * HP Diva card | |
2212 | */ | |
2213 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | |
2214 | PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, | |
2215 | pbn_b1_1_115200 }, | |
2216 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | |
2217 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2218 | pbn_b0_5_115200 }, | |
2219 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, | |
2220 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2221 | pbn_b2_1_115200 }, | |
2222 | ||
2223 | /* | |
2224 | * NEC Vrc-5074 (Nile 4) builtin UART. | |
2225 | */ | |
2226 | { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4, | |
2227 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2228 | pbn_nec_nile4 }, | |
2229 | ||
2230 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, | |
2231 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2232 | pbn_b3_4_115200 }, | |
2233 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, | |
2234 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2235 | pbn_b3_8_115200 }, | |
2236 | ||
2237 | /* | |
2238 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART | |
2239 | */ | |
2240 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | |
2241 | PCI_ANY_ID, PCI_ANY_ID, | |
2242 | 0, | |
2243 | 0, pbn_exar_XR17C152 }, | |
2244 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | |
2245 | PCI_ANY_ID, PCI_ANY_ID, | |
2246 | 0, | |
2247 | 0, pbn_exar_XR17C154 }, | |
2248 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | |
2249 | PCI_ANY_ID, PCI_ANY_ID, | |
2250 | 0, | |
2251 | 0, pbn_exar_XR17C158 }, | |
2252 | ||
2253 | /* | |
2254 | * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) | |
2255 | */ | |
2256 | { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, | |
2257 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
2258 | pbn_b0_1_115200 }, | |
2259 | ||
2260 | /* | |
2261 | * These entries match devices with class COMMUNICATION_SERIAL, | |
2262 | * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL | |
2263 | */ | |
2264 | { PCI_ANY_ID, PCI_ANY_ID, | |
2265 | PCI_ANY_ID, PCI_ANY_ID, | |
2266 | PCI_CLASS_COMMUNICATION_SERIAL << 8, | |
2267 | 0xffff00, pbn_default }, | |
2268 | { PCI_ANY_ID, PCI_ANY_ID, | |
2269 | PCI_ANY_ID, PCI_ANY_ID, | |
2270 | PCI_CLASS_COMMUNICATION_MODEM << 8, | |
2271 | 0xffff00, pbn_default }, | |
2272 | { PCI_ANY_ID, PCI_ANY_ID, | |
2273 | PCI_ANY_ID, PCI_ANY_ID, | |
2274 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, | |
2275 | 0xffff00, pbn_default }, | |
2276 | { 0, } | |
2277 | }; | |
2278 | ||
2279 | static struct pci_driver serial_pci_driver = { | |
2280 | .name = "serial", | |
2281 | .probe = pciserial_init_one, | |
2282 | .remove = __devexit_p(pciserial_remove_one), | |
2283 | .suspend = pciserial_suspend_one, | |
2284 | .resume = pciserial_resume_one, | |
2285 | .id_table = serial_pci_tbl, | |
2286 | }; | |
2287 | ||
2288 | static int __init serial8250_pci_init(void) | |
2289 | { | |
2290 | return pci_register_driver(&serial_pci_driver); | |
2291 | } | |
2292 | ||
2293 | static void __exit serial8250_pci_exit(void) | |
2294 | { | |
2295 | pci_unregister_driver(&serial_pci_driver); | |
2296 | } | |
2297 | ||
2298 | module_init(serial8250_pci_init); | |
2299 | module_exit(serial8250_pci_exit); | |
2300 | ||
2301 | MODULE_LICENSE("GPL"); | |
2302 | MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); | |
2303 | MODULE_DEVICE_TABLE(pci, serial_pci_tbl); |