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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/amba.c | |
3 | * | |
4 | * Driver for AMBA serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright 1999 ARM Limited | |
9 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 10 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
1da177e4 LT |
26 | * This is a generic driver for ARM AMBA-type serial ports. They |
27 | * have a lot of 16550-like features, but are not register compatible. | |
28 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
29 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
30 | * required, these have to be supplied via some other means (eg, GPIO) | |
31 | * and hooked into this driver. | |
32 | */ | |
1da177e4 LT |
33 | |
34 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
35 | #define SUPPORT_SYSRQ | |
36 | #endif | |
37 | ||
38 | #include <linux/module.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/console.h> | |
42 | #include <linux/sysrq.h> | |
43 | #include <linux/device.h> | |
44 | #include <linux/tty.h> | |
45 | #include <linux/tty_flip.h> | |
46 | #include <linux/serial_core.h> | |
47 | #include <linux/serial.h> | |
a62c80e5 RK |
48 | #include <linux/amba/bus.h> |
49 | #include <linux/amba/serial.h> | |
f8ce2547 | 50 | #include <linux/clk.h> |
5a0e3ad6 | 51 | #include <linux/slab.h> |
68b65f73 RK |
52 | #include <linux/dmaengine.h> |
53 | #include <linux/dma-mapping.h> | |
54 | #include <linux/scatterlist.h> | |
1da177e4 LT |
55 | |
56 | #include <asm/io.h> | |
c6b8fdad | 57 | #include <asm/sizes.h> |
1da177e4 LT |
58 | |
59 | #define UART_NR 14 | |
60 | ||
61 | #define SERIAL_AMBA_MAJOR 204 | |
62 | #define SERIAL_AMBA_MINOR 64 | |
63 | #define SERIAL_AMBA_NR UART_NR | |
64 | ||
65 | #define AMBA_ISR_PASS_LIMIT 256 | |
66 | ||
b63d4f0f RK |
67 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
68 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 69 | |
5926a295 AR |
70 | /* There is by now at least one vendor with differing details, so handle it */ |
71 | struct vendor_data { | |
72 | unsigned int ifls; | |
73 | unsigned int fifosize; | |
ec489aa8 LW |
74 | unsigned int lcrh_tx; |
75 | unsigned int lcrh_rx; | |
ac3e3fb4 | 76 | bool oversampling; |
5926a295 AR |
77 | }; |
78 | ||
79 | static struct vendor_data vendor_arm = { | |
80 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
81 | .fifosize = 16, | |
ec489aa8 LW |
82 | .lcrh_tx = UART011_LCRH, |
83 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 84 | .oversampling = false, |
5926a295 AR |
85 | }; |
86 | ||
87 | static struct vendor_data vendor_st = { | |
88 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
89 | .fifosize = 64, | |
ec489aa8 LW |
90 | .lcrh_tx = ST_UART011_LCRH_TX, |
91 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 92 | .oversampling = true, |
1da177e4 LT |
93 | }; |
94 | ||
68b65f73 RK |
95 | /* Deals with DMA transactions */ |
96 | struct pl011_dmatx_data { | |
97 | struct dma_chan *chan; | |
98 | struct scatterlist sg; | |
99 | char *buf; | |
100 | bool queued; | |
101 | }; | |
102 | ||
c19f12b5 RK |
103 | /* |
104 | * We wrap our port structure around the generic uart_port. | |
105 | */ | |
106 | struct uart_amba_port { | |
107 | struct uart_port port; | |
108 | struct clk *clk; | |
109 | const struct vendor_data *vendor; | |
68b65f73 | 110 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
111 | unsigned int im; /* interrupt mask */ |
112 | unsigned int old_status; | |
ffca2b11 | 113 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
114 | unsigned int lcrh_tx; /* vendor-specific */ |
115 | unsigned int lcrh_rx; /* vendor-specific */ | |
116 | bool autorts; | |
117 | char type[12]; | |
68b65f73 RK |
118 | #ifdef CONFIG_DMA_ENGINE |
119 | /* DMA stuff */ | |
120 | bool using_dma; | |
121 | struct pl011_dmatx_data dmatx; | |
122 | #endif | |
123 | }; | |
124 | ||
125 | /* | |
126 | * All the DMA operation mode stuff goes inside this ifdef. | |
127 | * This assumes that you have a generic DMA device interface, | |
128 | * no custom DMA interfaces are supported. | |
129 | */ | |
130 | #ifdef CONFIG_DMA_ENGINE | |
131 | ||
132 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
133 | ||
134 | static void pl011_dma_probe_initcall(struct uart_amba_port *uap) | |
135 | { | |
136 | /* DMA is the sole user of the platform data right now */ | |
137 | struct amba_pl011_data *plat = uap->port.dev->platform_data; | |
138 | struct dma_slave_config tx_conf = { | |
139 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
140 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
141 | .direction = DMA_TO_DEVICE, | |
142 | .dst_maxburst = uap->fifosize >> 1, | |
143 | }; | |
144 | struct dma_chan *chan; | |
145 | dma_cap_mask_t mask; | |
146 | ||
147 | /* We need platform data */ | |
148 | if (!plat || !plat->dma_filter) { | |
149 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
150 | return; | |
151 | } | |
152 | ||
153 | /* Try to acquire a generic DMA engine slave channel */ | |
154 | dma_cap_zero(mask); | |
155 | dma_cap_set(DMA_SLAVE, mask); | |
156 | ||
157 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param); | |
158 | if (!chan) { | |
159 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
160 | return; | |
161 | } | |
162 | ||
163 | dmaengine_slave_config(chan, &tx_conf); | |
164 | uap->dmatx.chan = chan; | |
165 | ||
166 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
167 | dma_chan_name(uap->dmatx.chan)); | |
168 | } | |
169 | ||
170 | #ifndef MODULE | |
171 | /* | |
172 | * Stack up the UARTs and let the above initcall be done at device | |
173 | * initcall time, because the serial driver is called as an arch | |
174 | * initcall, and at this time the DMA subsystem is not yet registered. | |
175 | * At this point the driver will switch over to using DMA where desired. | |
176 | */ | |
177 | struct dma_uap { | |
178 | struct list_head node; | |
179 | struct uart_amba_port *uap; | |
c19f12b5 RK |
180 | }; |
181 | ||
68b65f73 RK |
182 | static LIST_HEAD(pl011_dma_uarts); |
183 | ||
184 | static int __init pl011_dma_initcall(void) | |
185 | { | |
186 | struct list_head *node, *tmp; | |
187 | ||
188 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
189 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
190 | pl011_dma_probe_initcall(dmau->uap); | |
191 | list_del(node); | |
192 | kfree(dmau); | |
193 | } | |
194 | return 0; | |
195 | } | |
196 | ||
197 | device_initcall(pl011_dma_initcall); | |
198 | ||
199 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
200 | { | |
201 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
202 | if (dmau) { | |
203 | dmau->uap = uap; | |
204 | list_add_tail(&dmau->node, &pl011_dma_uarts); | |
205 | } | |
206 | } | |
207 | #else | |
208 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
209 | { | |
210 | pl011_dma_probe_initcall(uap); | |
211 | } | |
212 | #endif | |
213 | ||
214 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
215 | { | |
216 | /* TODO: remove the initcall if it has not yet executed */ | |
217 | if (uap->dmatx.chan) | |
218 | dma_release_channel(uap->dmatx.chan); | |
219 | } | |
220 | ||
221 | ||
222 | /* Forward declare this for the refill routine */ | |
223 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | |
224 | ||
225 | /* | |
226 | * The current DMA TX buffer has been sent. | |
227 | * Try to queue up another DMA buffer. | |
228 | */ | |
229 | static void pl011_dma_tx_callback(void *data) | |
230 | { | |
231 | struct uart_amba_port *uap = data; | |
232 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
233 | unsigned long flags; | |
234 | u16 dmacr; | |
235 | ||
236 | spin_lock_irqsave(&uap->port.lock, flags); | |
237 | if (uap->dmatx.queued) | |
238 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
239 | DMA_TO_DEVICE); | |
240 | ||
241 | dmacr = uap->dmacr; | |
242 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
243 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
244 | ||
245 | /* | |
246 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
247 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
248 | * | |
249 | * Note: we need to be careful here of a potential race between DMA | |
250 | * and the rest of the driver - if the driver disables TX DMA while | |
251 | * a TX buffer completing, we must update the tx queued status to | |
252 | * get further refills (hence we check dmacr). | |
253 | */ | |
254 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
255 | uart_circ_empty(&uap->port.state->xmit)) { | |
256 | uap->dmatx.queued = false; | |
257 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
258 | return; | |
259 | } | |
260 | ||
261 | if (pl011_dma_tx_refill(uap) <= 0) { | |
262 | /* | |
263 | * We didn't queue a DMA buffer for some reason, but we | |
264 | * have data pending to be sent. Re-enable the TX IRQ. | |
265 | */ | |
266 | uap->im |= UART011_TXIM; | |
267 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
268 | } | |
269 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
270 | } | |
271 | ||
272 | /* | |
273 | * Try to refill the TX DMA buffer. | |
274 | * Locking: called with port lock held and IRQs disabled. | |
275 | * Returns: | |
276 | * 1 if we queued up a TX DMA buffer. | |
277 | * 0 if we didn't want to handle this by DMA | |
278 | * <0 on error | |
279 | */ | |
280 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
281 | { | |
282 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
283 | struct dma_chan *chan = dmatx->chan; | |
284 | struct dma_device *dma_dev = chan->device; | |
285 | struct dma_async_tx_descriptor *desc; | |
286 | struct circ_buf *xmit = &uap->port.state->xmit; | |
287 | unsigned int count; | |
288 | ||
289 | /* | |
290 | * Try to avoid the overhead involved in using DMA if the | |
291 | * transaction fits in the first half of the FIFO, by using | |
292 | * the standard interrupt handling. This ensures that we | |
293 | * issue a uart_write_wakeup() at the appropriate time. | |
294 | */ | |
295 | count = uart_circ_chars_pending(xmit); | |
296 | if (count < (uap->fifosize >> 1)) { | |
297 | uap->dmatx.queued = false; | |
298 | return 0; | |
299 | } | |
300 | ||
301 | /* | |
302 | * Bodge: don't send the last character by DMA, as this | |
303 | * will prevent XON from notifying us to restart DMA. | |
304 | */ | |
305 | count -= 1; | |
306 | ||
307 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
308 | if (count > PL011_DMA_BUFFER_SIZE) | |
309 | count = PL011_DMA_BUFFER_SIZE; | |
310 | ||
311 | if (xmit->tail < xmit->head) | |
312 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
313 | else { | |
314 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
315 | size_t second = xmit->head; | |
316 | ||
317 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
318 | if (second) | |
319 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
320 | } | |
321 | ||
322 | dmatx->sg.length = count; | |
323 | ||
324 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
325 | uap->dmatx.queued = false; | |
326 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
327 | return -EBUSY; | |
328 | } | |
329 | ||
330 | desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE, | |
331 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
332 | if (!desc) { | |
333 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
334 | uap->dmatx.queued = false; | |
335 | /* | |
336 | * If DMA cannot be used right now, we complete this | |
337 | * transaction via IRQ and let the TTY layer retry. | |
338 | */ | |
339 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
340 | return -EBUSY; | |
341 | } | |
342 | ||
343 | /* Some data to go along to the callback */ | |
344 | desc->callback = pl011_dma_tx_callback; | |
345 | desc->callback_param = uap; | |
346 | ||
347 | /* All errors should happen at prepare time */ | |
348 | dmaengine_submit(desc); | |
349 | ||
350 | /* Fire the DMA transaction */ | |
351 | dma_dev->device_issue_pending(chan); | |
352 | ||
353 | uap->dmacr |= UART011_TXDMAE; | |
354 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
355 | uap->dmatx.queued = true; | |
356 | ||
357 | /* | |
358 | * Now we know that DMA will fire, so advance the ring buffer | |
359 | * with the stuff we just dispatched. | |
360 | */ | |
361 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
362 | uap->port.icount.tx += count; | |
363 | ||
364 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
365 | uart_write_wakeup(&uap->port); | |
366 | ||
367 | return 1; | |
368 | } | |
369 | ||
370 | /* | |
371 | * We received a transmit interrupt without a pending X-char but with | |
372 | * pending characters. | |
373 | * Locking: called with port lock held and IRQs disabled. | |
374 | * Returns: | |
375 | * false if we want to use PIO to transmit | |
376 | * true if we queued a DMA buffer | |
377 | */ | |
378 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
379 | { | |
380 | if (!uap->using_dma) | |
381 | return false; | |
382 | ||
383 | /* | |
384 | * If we already have a TX buffer queued, but received a | |
385 | * TX interrupt, it will be because we've just sent an X-char. | |
386 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
387 | */ | |
388 | if (uap->dmatx.queued) { | |
389 | uap->dmacr |= UART011_TXDMAE; | |
390 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
391 | uap->im &= ~UART011_TXIM; | |
392 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
393 | return true; | |
394 | } | |
395 | ||
396 | /* | |
397 | * We don't have a TX buffer queued, so try to queue one. | |
398 | * If we succesfully queued a buffer, mask the TX IRQ. | |
399 | */ | |
400 | if (pl011_dma_tx_refill(uap) > 0) { | |
401 | uap->im &= ~UART011_TXIM; | |
402 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
403 | return true; | |
404 | } | |
405 | return false; | |
406 | } | |
407 | ||
408 | /* | |
409 | * Stop the DMA transmit (eg, due to received XOFF). | |
410 | * Locking: called with port lock held and IRQs disabled. | |
411 | */ | |
412 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
413 | { | |
414 | if (uap->dmatx.queued) { | |
415 | uap->dmacr &= ~UART011_TXDMAE; | |
416 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
417 | } | |
418 | } | |
419 | ||
420 | /* | |
421 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
422 | * character queued for send, try to get that character out ASAP. | |
423 | * Locking: called with port lock held and IRQs disabled. | |
424 | * Returns: | |
425 | * false if we want the TX IRQ to be enabled | |
426 | * true if we have a buffer queued | |
427 | */ | |
428 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
429 | { | |
430 | u16 dmacr; | |
431 | ||
432 | if (!uap->using_dma) | |
433 | return false; | |
434 | ||
435 | if (!uap->port.x_char) { | |
436 | /* no X-char, try to push chars out in DMA mode */ | |
437 | bool ret = true; | |
438 | ||
439 | if (!uap->dmatx.queued) { | |
440 | if (pl011_dma_tx_refill(uap) > 0) { | |
441 | uap->im &= ~UART011_TXIM; | |
442 | ret = true; | |
443 | } else { | |
444 | uap->im |= UART011_TXIM; | |
445 | ret = false; | |
446 | } | |
447 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
448 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | |
449 | uap->dmacr |= UART011_TXDMAE; | |
450 | writew(uap->dmacr, | |
451 | uap->port.membase + UART011_DMACR); | |
452 | } | |
453 | return ret; | |
454 | } | |
455 | ||
456 | /* | |
457 | * We have an X-char to send. Disable DMA to prevent it loading | |
458 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
459 | */ | |
460 | dmacr = uap->dmacr; | |
461 | uap->dmacr &= ~UART011_TXDMAE; | |
462 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
463 | ||
464 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
465 | /* | |
466 | * No space in the FIFO, so enable the transmit interrupt | |
467 | * so we know when there is space. Note that once we've | |
468 | * loaded the character, we should just re-enable DMA. | |
469 | */ | |
470 | return false; | |
471 | } | |
472 | ||
473 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
474 | uap->port.icount.tx++; | |
475 | uap->port.x_char = 0; | |
476 | ||
477 | /* Success - restore the DMA state */ | |
478 | uap->dmacr = dmacr; | |
479 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
480 | ||
481 | return true; | |
482 | } | |
483 | ||
484 | /* | |
485 | * Flush the transmit buffer. | |
486 | * Locking: called with port lock held and IRQs disabled. | |
487 | */ | |
488 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
489 | { | |
490 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
491 | ||
492 | if (!uap->using_dma) | |
493 | return; | |
494 | ||
495 | /* Avoid deadlock with the DMA engine callback */ | |
496 | spin_unlock(&uap->port.lock); | |
497 | dmaengine_terminate_all(uap->dmatx.chan); | |
498 | spin_lock(&uap->port.lock); | |
499 | if (uap->dmatx.queued) { | |
500 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
501 | DMA_TO_DEVICE); | |
502 | uap->dmatx.queued = false; | |
503 | uap->dmacr &= ~UART011_TXDMAE; | |
504 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
505 | } | |
506 | } | |
507 | ||
508 | ||
509 | static void pl011_dma_startup(struct uart_amba_port *uap) | |
510 | { | |
511 | if (!uap->dmatx.chan) | |
512 | return; | |
513 | ||
514 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
515 | if (!uap->dmatx.buf) { | |
516 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
517 | uap->port.fifosize = uap->fifosize; | |
518 | return; | |
519 | } | |
520 | ||
521 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
522 | ||
523 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
524 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
525 | uap->using_dma = true; | |
526 | ||
527 | /* Turn on DMA error (RX/TX will be enabled on demand) */ | |
528 | uap->dmacr |= UART011_DMAONERR; | |
529 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
530 | } | |
531 | ||
532 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
533 | { | |
534 | if (!uap->using_dma) | |
535 | return; | |
536 | ||
537 | /* Disable RX and TX DMA */ | |
538 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
539 | barrier(); | |
540 | ||
541 | spin_lock_irq(&uap->port.lock); | |
542 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
543 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
544 | spin_unlock_irq(&uap->port.lock); | |
545 | ||
546 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
547 | dmaengine_terminate_all(uap->dmatx.chan); | |
548 | if (uap->dmatx.queued) { | |
549 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
550 | DMA_TO_DEVICE); | |
551 | uap->dmatx.queued = false; | |
552 | } | |
553 | ||
554 | kfree(uap->dmatx.buf); | |
555 | ||
556 | uap->using_dma = false; | |
557 | } | |
558 | ||
559 | #else | |
560 | /* Blank functions if the DMA engine is not available */ | |
561 | static inline void pl011_dma_probe(struct uart_amba_port *uap) | |
562 | { | |
563 | } | |
564 | ||
565 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
566 | { | |
567 | } | |
568 | ||
569 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
570 | { | |
571 | } | |
572 | ||
573 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
574 | { | |
575 | } | |
576 | ||
577 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
578 | { | |
579 | return false; | |
580 | } | |
581 | ||
582 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
583 | { | |
584 | } | |
585 | ||
586 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
587 | { | |
588 | return false; | |
589 | } | |
590 | ||
591 | #define pl011_dma_flush_buffer NULL | |
592 | #endif | |
593 | ||
594 | ||
b129a8cc | 595 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 LT |
596 | { |
597 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
598 | ||
599 | uap->im &= ~UART011_TXIM; | |
600 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 601 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
602 | } |
603 | ||
b129a8cc | 604 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 LT |
605 | { |
606 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
607 | ||
68b65f73 RK |
608 | if (!pl011_dma_tx_start(uap)) { |
609 | uap->im |= UART011_TXIM; | |
610 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
611 | } | |
1da177e4 LT |
612 | } |
613 | ||
614 | static void pl011_stop_rx(struct uart_port *port) | |
615 | { | |
616 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
617 | ||
618 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
619 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
620 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
621 | } | |
622 | ||
623 | static void pl011_enable_ms(struct uart_port *port) | |
624 | { | |
625 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
626 | ||
627 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
628 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
629 | } | |
630 | ||
7d12e780 | 631 | static void pl011_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 632 | { |
ebd2c8f6 | 633 | struct tty_struct *tty = uap->port.state->port.tty; |
b63d4f0f | 634 | unsigned int status, ch, flag, max_count = 256; |
1da177e4 LT |
635 | |
636 | status = readw(uap->port.membase + UART01x_FR); | |
637 | while ((status & UART01x_FR_RXFE) == 0 && max_count--) { | |
b63d4f0f | 638 | ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX; |
1da177e4 LT |
639 | flag = TTY_NORMAL; |
640 | uap->port.icount.rx++; | |
641 | ||
642 | /* | |
643 | * Note that the error handling code is | |
644 | * out of the main execution path | |
645 | */ | |
b63d4f0f RK |
646 | if (unlikely(ch & UART_DR_ERROR)) { |
647 | if (ch & UART011_DR_BE) { | |
648 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
1da177e4 LT |
649 | uap->port.icount.brk++; |
650 | if (uart_handle_break(&uap->port)) | |
651 | goto ignore_char; | |
b63d4f0f | 652 | } else if (ch & UART011_DR_PE) |
1da177e4 | 653 | uap->port.icount.parity++; |
b63d4f0f | 654 | else if (ch & UART011_DR_FE) |
1da177e4 | 655 | uap->port.icount.frame++; |
b63d4f0f | 656 | if (ch & UART011_DR_OE) |
1da177e4 LT |
657 | uap->port.icount.overrun++; |
658 | ||
b63d4f0f | 659 | ch &= uap->port.read_status_mask; |
1da177e4 | 660 | |
b63d4f0f | 661 | if (ch & UART011_DR_BE) |
1da177e4 | 662 | flag = TTY_BREAK; |
b63d4f0f | 663 | else if (ch & UART011_DR_PE) |
1da177e4 | 664 | flag = TTY_PARITY; |
b63d4f0f | 665 | else if (ch & UART011_DR_FE) |
1da177e4 LT |
666 | flag = TTY_FRAME; |
667 | } | |
668 | ||
7d12e780 | 669 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) |
1da177e4 LT |
670 | goto ignore_char; |
671 | ||
b63d4f0f | 672 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); |
05ab3014 | 673 | |
1da177e4 LT |
674 | ignore_char: |
675 | status = readw(uap->port.membase + UART01x_FR); | |
676 | } | |
2389b272 | 677 | spin_unlock(&uap->port.lock); |
1da177e4 | 678 | tty_flip_buffer_push(tty); |
2389b272 | 679 | spin_lock(&uap->port.lock); |
1da177e4 LT |
680 | } |
681 | ||
682 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
683 | { | |
ebd2c8f6 | 684 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
685 | int count; |
686 | ||
687 | if (uap->port.x_char) { | |
688 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
689 | uap->port.icount.tx++; | |
690 | uap->port.x_char = 0; | |
691 | return; | |
692 | } | |
693 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 694 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
695 | return; |
696 | } | |
697 | ||
68b65f73 RK |
698 | /* If we are using DMA mode, try to send some characters. */ |
699 | if (pl011_dma_tx_irq(uap)) | |
700 | return; | |
701 | ||
ffca2b11 | 702 | count = uap->fifosize >> 1; |
1da177e4 LT |
703 | do { |
704 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
705 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
706 | uap->port.icount.tx++; | |
707 | if (uart_circ_empty(xmit)) | |
708 | break; | |
709 | } while (--count > 0); | |
710 | ||
711 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
712 | uart_write_wakeup(&uap->port); | |
713 | ||
714 | if (uart_circ_empty(xmit)) | |
b129a8cc | 715 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
716 | } |
717 | ||
718 | static void pl011_modem_status(struct uart_amba_port *uap) | |
719 | { | |
720 | unsigned int status, delta; | |
721 | ||
722 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
723 | ||
724 | delta = status ^ uap->old_status; | |
725 | uap->old_status = status; | |
726 | ||
727 | if (!delta) | |
728 | return; | |
729 | ||
730 | if (delta & UART01x_FR_DCD) | |
731 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
732 | ||
733 | if (delta & UART01x_FR_DSR) | |
734 | uap->port.icount.dsr++; | |
735 | ||
736 | if (delta & UART01x_FR_CTS) | |
737 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
738 | ||
bdc04e31 | 739 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
740 | } |
741 | ||
7d12e780 | 742 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
743 | { |
744 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 745 | unsigned long flags; |
1da177e4 LT |
746 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
747 | int handled = 0; | |
748 | ||
963cc981 | 749 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
750 | |
751 | status = readw(uap->port.membase + UART011_MIS); | |
752 | if (status) { | |
753 | do { | |
754 | writew(status & ~(UART011_TXIS|UART011_RTIS| | |
755 | UART011_RXIS), | |
756 | uap->port.membase + UART011_ICR); | |
757 | ||
758 | if (status & (UART011_RTIS|UART011_RXIS)) | |
1da177e4 | 759 | pl011_rx_chars(uap); |
1da177e4 LT |
760 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
761 | UART011_CTSMIS|UART011_RIMIS)) | |
762 | pl011_modem_status(uap); | |
763 | if (status & UART011_TXIS) | |
764 | pl011_tx_chars(uap); | |
765 | ||
766 | if (pass_counter-- == 0) | |
767 | break; | |
768 | ||
769 | status = readw(uap->port.membase + UART011_MIS); | |
770 | } while (status != 0); | |
771 | handled = 1; | |
772 | } | |
773 | ||
963cc981 | 774 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
775 | |
776 | return IRQ_RETVAL(handled); | |
777 | } | |
778 | ||
779 | static unsigned int pl01x_tx_empty(struct uart_port *port) | |
780 | { | |
781 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
782 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
783 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
784 | } | |
785 | ||
786 | static unsigned int pl01x_get_mctrl(struct uart_port *port) | |
787 | { | |
788 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
789 | unsigned int result = 0; | |
790 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
791 | ||
5159f407 | 792 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
793 | if (status & uartbit) \ |
794 | result |= tiocmbit | |
795 | ||
5159f407 JS |
796 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
797 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
798 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
799 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
800 | #undef TIOCMBIT | |
1da177e4 LT |
801 | return result; |
802 | } | |
803 | ||
804 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
805 | { | |
806 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
807 | unsigned int cr; | |
808 | ||
809 | cr = readw(uap->port.membase + UART011_CR); | |
810 | ||
5159f407 | 811 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
812 | if (mctrl & tiocmbit) \ |
813 | cr |= uartbit; \ | |
814 | else \ | |
815 | cr &= ~uartbit | |
816 | ||
5159f407 JS |
817 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
818 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
819 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
820 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
821 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
822 | |
823 | if (uap->autorts) { | |
824 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
825 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
826 | } | |
5159f407 | 827 | #undef TIOCMBIT |
1da177e4 LT |
828 | |
829 | writew(cr, uap->port.membase + UART011_CR); | |
830 | } | |
831 | ||
832 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
833 | { | |
834 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
835 | unsigned long flags; | |
836 | unsigned int lcr_h; | |
837 | ||
838 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 839 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
840 | if (break_state == -1) |
841 | lcr_h |= UART01x_LCRH_BRK; | |
842 | else | |
843 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 844 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
845 | spin_unlock_irqrestore(&uap->port.lock, flags); |
846 | } | |
847 | ||
84b5ae15 JW |
848 | #ifdef CONFIG_CONSOLE_POLL |
849 | static int pl010_get_poll_char(struct uart_port *port) | |
850 | { | |
851 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
852 | unsigned int status; | |
853 | ||
f5316b4a JW |
854 | status = readw(uap->port.membase + UART01x_FR); |
855 | if (status & UART01x_FR_RXFE) | |
856 | return NO_POLL_CHAR; | |
84b5ae15 JW |
857 | |
858 | return readw(uap->port.membase + UART01x_DR); | |
859 | } | |
860 | ||
861 | static void pl010_put_poll_char(struct uart_port *port, | |
862 | unsigned char ch) | |
863 | { | |
864 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
865 | ||
866 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
867 | barrier(); | |
868 | ||
869 | writew(ch, uap->port.membase + UART01x_DR); | |
870 | } | |
871 | ||
872 | #endif /* CONFIG_CONSOLE_POLL */ | |
873 | ||
1da177e4 LT |
874 | static int pl011_startup(struct uart_port *port) |
875 | { | |
876 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
877 | unsigned int cr; | |
878 | int retval; | |
879 | ||
880 | /* | |
881 | * Try to enable the clock producer. | |
882 | */ | |
883 | retval = clk_enable(uap->clk); | |
884 | if (retval) | |
885 | goto out; | |
886 | ||
887 | uap->port.uartclk = clk_get_rate(uap->clk); | |
888 | ||
889 | /* | |
890 | * Allocate the IRQ | |
891 | */ | |
892 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
893 | if (retval) | |
894 | goto clk_dis; | |
895 | ||
c19f12b5 | 896 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
897 | |
898 | /* | |
899 | * Provoke TX FIFO interrupt into asserting. | |
900 | */ | |
901 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | |
902 | writew(cr, uap->port.membase + UART011_CR); | |
903 | writew(0, uap->port.membase + UART011_FBRD); | |
904 | writew(1, uap->port.membase + UART011_IBRD); | |
ec489aa8 LW |
905 | writew(0, uap->port.membase + uap->lcrh_rx); |
906 | if (uap->lcrh_tx != uap->lcrh_rx) { | |
907 | int i; | |
908 | /* | |
909 | * Wait 10 PCLKs before writing LCRH_TX register, | |
910 | * to get this delay write read only register 10 times | |
911 | */ | |
912 | for (i = 0; i < 10; ++i) | |
913 | writew(0xff, uap->port.membase + UART011_MIS); | |
914 | writew(0, uap->port.membase + uap->lcrh_tx); | |
915 | } | |
1da177e4 LT |
916 | writew(0, uap->port.membase + UART01x_DR); |
917 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
918 | barrier(); | |
919 | ||
920 | cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
921 | writew(cr, uap->port.membase + UART011_CR); | |
922 | ||
5063e2c5 RK |
923 | /* Clear pending error interrupts */ |
924 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
925 | uap->port.membase + UART011_ICR); | |
926 | ||
1da177e4 LT |
927 | /* |
928 | * initialise the old status of the modem signals | |
929 | */ | |
930 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
931 | ||
68b65f73 RK |
932 | /* Startup DMA */ |
933 | pl011_dma_startup(uap); | |
934 | ||
1da177e4 LT |
935 | /* |
936 | * Finally, enable interrupts | |
937 | */ | |
938 | spin_lock_irq(&uap->port.lock); | |
939 | uap->im = UART011_RXIM | UART011_RTIM; | |
940 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
941 | spin_unlock_irq(&uap->port.lock); | |
942 | ||
943 | return 0; | |
944 | ||
945 | clk_dis: | |
946 | clk_disable(uap->clk); | |
947 | out: | |
948 | return retval; | |
949 | } | |
950 | ||
ec489aa8 LW |
951 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
952 | unsigned int lcrh) | |
953 | { | |
954 | unsigned long val; | |
955 | ||
956 | val = readw(uap->port.membase + lcrh); | |
957 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
958 | writew(val, uap->port.membase + lcrh); | |
959 | } | |
960 | ||
1da177e4 LT |
961 | static void pl011_shutdown(struct uart_port *port) |
962 | { | |
963 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1da177e4 LT |
964 | |
965 | /* | |
966 | * disable all interrupts | |
967 | */ | |
968 | spin_lock_irq(&uap->port.lock); | |
969 | uap->im = 0; | |
970 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
971 | writew(0xffff, uap->port.membase + UART011_ICR); | |
972 | spin_unlock_irq(&uap->port.lock); | |
973 | ||
68b65f73 RK |
974 | pl011_dma_shutdown(uap); |
975 | ||
1da177e4 LT |
976 | /* |
977 | * Free the interrupt | |
978 | */ | |
979 | free_irq(uap->port.irq, uap); | |
980 | ||
981 | /* | |
982 | * disable the port | |
983 | */ | |
3b43816f | 984 | uap->autorts = false; |
1da177e4 LT |
985 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); |
986 | ||
987 | /* | |
988 | * disable break condition and fifos | |
989 | */ | |
ec489aa8 LW |
990 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
991 | if (uap->lcrh_rx != uap->lcrh_tx) | |
992 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
993 | |
994 | /* | |
995 | * Shut down the clock producer | |
996 | */ | |
997 | clk_disable(uap->clk); | |
998 | } | |
999 | ||
1000 | static void | |
606d099c AC |
1001 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1002 | struct ktermios *old) | |
1da177e4 | 1003 | { |
3b43816f | 1004 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 LT |
1005 | unsigned int lcr_h, old_cr; |
1006 | unsigned long flags; | |
c19f12b5 RK |
1007 | unsigned int baud, quot, clkdiv; |
1008 | ||
1009 | if (uap->vendor->oversampling) | |
1010 | clkdiv = 8; | |
1011 | else | |
1012 | clkdiv = 16; | |
1da177e4 LT |
1013 | |
1014 | /* | |
1015 | * Ask the core to calculate the divisor for us. | |
1016 | */ | |
ac3e3fb4 | 1017 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1018 | port->uartclk / clkdiv); |
ac3e3fb4 LW |
1019 | |
1020 | if (baud > port->uartclk/16) | |
1021 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1022 | else | |
1023 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1024 | |
1025 | switch (termios->c_cflag & CSIZE) { | |
1026 | case CS5: | |
1027 | lcr_h = UART01x_LCRH_WLEN_5; | |
1028 | break; | |
1029 | case CS6: | |
1030 | lcr_h = UART01x_LCRH_WLEN_6; | |
1031 | break; | |
1032 | case CS7: | |
1033 | lcr_h = UART01x_LCRH_WLEN_7; | |
1034 | break; | |
1035 | default: // CS8 | |
1036 | lcr_h = UART01x_LCRH_WLEN_8; | |
1037 | break; | |
1038 | } | |
1039 | if (termios->c_cflag & CSTOPB) | |
1040 | lcr_h |= UART01x_LCRH_STP2; | |
1041 | if (termios->c_cflag & PARENB) { | |
1042 | lcr_h |= UART01x_LCRH_PEN; | |
1043 | if (!(termios->c_cflag & PARODD)) | |
1044 | lcr_h |= UART01x_LCRH_EPS; | |
1045 | } | |
ffca2b11 | 1046 | if (uap->fifosize > 1) |
1da177e4 LT |
1047 | lcr_h |= UART01x_LCRH_FEN; |
1048 | ||
1049 | spin_lock_irqsave(&port->lock, flags); | |
1050 | ||
1051 | /* | |
1052 | * Update the per-port timeout. | |
1053 | */ | |
1054 | uart_update_timeout(port, termios->c_cflag, baud); | |
1055 | ||
b63d4f0f | 1056 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1057 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1058 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1059 | if (termios->c_iflag & (BRKINT | PARMRK)) |
b63d4f0f | 1060 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1061 | |
1062 | /* | |
1063 | * Characters to ignore | |
1064 | */ | |
1065 | port->ignore_status_mask = 0; | |
1066 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1067 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1068 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1069 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1070 | /* |
1071 | * If we're ignoring parity and break indicators, | |
1072 | * ignore overruns too (for real raw support). | |
1073 | */ | |
1074 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1075 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1076 | } |
1077 | ||
1078 | /* | |
1079 | * Ignore all characters if CREAD is not set. | |
1080 | */ | |
1081 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1082 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1083 | |
1084 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1085 | pl011_enable_ms(port); | |
1086 | ||
1087 | /* first, disable everything */ | |
1088 | old_cr = readw(port->membase + UART011_CR); | |
1089 | writew(0, port->membase + UART011_CR); | |
1090 | ||
3b43816f RV |
1091 | if (termios->c_cflag & CRTSCTS) { |
1092 | if (old_cr & UART011_CR_RTS) | |
1093 | old_cr |= UART011_CR_RTSEN; | |
1094 | ||
1095 | old_cr |= UART011_CR_CTSEN; | |
1096 | uap->autorts = true; | |
1097 | } else { | |
1098 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1099 | uap->autorts = false; | |
1100 | } | |
1101 | ||
c19f12b5 RK |
1102 | if (uap->vendor->oversampling) { |
1103 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1104 | old_cr |= ST_UART011_CR_OVSFACT; |
1105 | else | |
1106 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1107 | } | |
1108 | ||
1da177e4 LT |
1109 | /* Set baud rate */ |
1110 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1111 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1112 | ||
1113 | /* | |
1114 | * ----------v----------v----------v----------v----- | |
1115 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
1116 | * ----------^----------^----------^----------^----- | |
1117 | */ | |
ec489aa8 LW |
1118 | writew(lcr_h, port->membase + uap->lcrh_rx); |
1119 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1120 | int i; | |
1121 | /* | |
1122 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1123 | * to get this delay write read only register 10 times | |
1124 | */ | |
1125 | for (i = 0; i < 10; ++i) | |
1126 | writew(0xff, uap->port.membase + UART011_MIS); | |
1127 | writew(lcr_h, port->membase + uap->lcrh_tx); | |
1128 | } | |
1da177e4 LT |
1129 | writew(old_cr, port->membase + UART011_CR); |
1130 | ||
1131 | spin_unlock_irqrestore(&port->lock, flags); | |
1132 | } | |
1133 | ||
1134 | static const char *pl011_type(struct uart_port *port) | |
1135 | { | |
e8a7ba86 RK |
1136 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1137 | return uap->port.type == PORT_AMBA ? uap->type : NULL; | |
1da177e4 LT |
1138 | } |
1139 | ||
1140 | /* | |
1141 | * Release the memory region(s) being used by 'port' | |
1142 | */ | |
1143 | static void pl010_release_port(struct uart_port *port) | |
1144 | { | |
1145 | release_mem_region(port->mapbase, SZ_4K); | |
1146 | } | |
1147 | ||
1148 | /* | |
1149 | * Request the memory region(s) being used by 'port' | |
1150 | */ | |
1151 | static int pl010_request_port(struct uart_port *port) | |
1152 | { | |
1153 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1154 | != NULL ? 0 : -EBUSY; | |
1155 | } | |
1156 | ||
1157 | /* | |
1158 | * Configure/autoconfigure the port. | |
1159 | */ | |
1160 | static void pl010_config_port(struct uart_port *port, int flags) | |
1161 | { | |
1162 | if (flags & UART_CONFIG_TYPE) { | |
1163 | port->type = PORT_AMBA; | |
1164 | pl010_request_port(port); | |
1165 | } | |
1166 | } | |
1167 | ||
1168 | /* | |
1169 | * verify the new serial_struct (for TIOCSSERIAL). | |
1170 | */ | |
1171 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1172 | { | |
1173 | int ret = 0; | |
1174 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1175 | ret = -EINVAL; | |
a62c4133 | 1176 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1177 | ret = -EINVAL; |
1178 | if (ser->baud_base < 9600) | |
1179 | ret = -EINVAL; | |
1180 | return ret; | |
1181 | } | |
1182 | ||
1183 | static struct uart_ops amba_pl011_pops = { | |
1184 | .tx_empty = pl01x_tx_empty, | |
1185 | .set_mctrl = pl011_set_mctrl, | |
1186 | .get_mctrl = pl01x_get_mctrl, | |
1187 | .stop_tx = pl011_stop_tx, | |
1188 | .start_tx = pl011_start_tx, | |
1189 | .stop_rx = pl011_stop_rx, | |
1190 | .enable_ms = pl011_enable_ms, | |
1191 | .break_ctl = pl011_break_ctl, | |
1192 | .startup = pl011_startup, | |
1193 | .shutdown = pl011_shutdown, | |
68b65f73 | 1194 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
1195 | .set_termios = pl011_set_termios, |
1196 | .type = pl011_type, | |
1197 | .release_port = pl010_release_port, | |
1198 | .request_port = pl010_request_port, | |
1199 | .config_port = pl010_config_port, | |
1200 | .verify_port = pl010_verify_port, | |
84b5ae15 JW |
1201 | #ifdef CONFIG_CONSOLE_POLL |
1202 | .poll_get_char = pl010_get_poll_char, | |
1203 | .poll_put_char = pl010_put_poll_char, | |
1204 | #endif | |
1da177e4 LT |
1205 | }; |
1206 | ||
1207 | static struct uart_amba_port *amba_ports[UART_NR]; | |
1208 | ||
1209 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
1210 | ||
d358788f | 1211 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 1212 | { |
d358788f | 1213 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 | 1214 | |
d358788f RK |
1215 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
1216 | barrier(); | |
1da177e4 LT |
1217 | writew(ch, uap->port.membase + UART01x_DR); |
1218 | } | |
1219 | ||
1220 | static void | |
1221 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
1222 | { | |
1223 | struct uart_amba_port *uap = amba_ports[co->index]; | |
1224 | unsigned int status, old_cr, new_cr; | |
1da177e4 LT |
1225 | |
1226 | clk_enable(uap->clk); | |
1227 | ||
1228 | /* | |
1229 | * First save the CR then disable the interrupts | |
1230 | */ | |
1231 | old_cr = readw(uap->port.membase + UART011_CR); | |
1232 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
1233 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1234 | writew(new_cr, uap->port.membase + UART011_CR); | |
1235 | ||
d358788f | 1236 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
1237 | |
1238 | /* | |
1239 | * Finally, wait for transmitter to become empty | |
1240 | * and restore the TCR | |
1241 | */ | |
1242 | do { | |
1243 | status = readw(uap->port.membase + UART01x_FR); | |
1244 | } while (status & UART01x_FR_BUSY); | |
1245 | writew(old_cr, uap->port.membase + UART011_CR); | |
1246 | ||
1247 | clk_disable(uap->clk); | |
1248 | } | |
1249 | ||
1250 | static void __init | |
1251 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
1252 | int *parity, int *bits) | |
1253 | { | |
1254 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
1255 | unsigned int lcr_h, ibrd, fbrd; | |
1256 | ||
ec489aa8 | 1257 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1258 | |
1259 | *parity = 'n'; | |
1260 | if (lcr_h & UART01x_LCRH_PEN) { | |
1261 | if (lcr_h & UART01x_LCRH_EPS) | |
1262 | *parity = 'e'; | |
1263 | else | |
1264 | *parity = 'o'; | |
1265 | } | |
1266 | ||
1267 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
1268 | *bits = 7; | |
1269 | else | |
1270 | *bits = 8; | |
1271 | ||
1272 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1273 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
1274 | ||
1275 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 1276 | |
c19f12b5 | 1277 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
1278 | if (readw(uap->port.membase + UART011_CR) |
1279 | & ST_UART011_CR_OVSFACT) | |
1280 | *baud *= 2; | |
1281 | } | |
1da177e4 LT |
1282 | } |
1283 | } | |
1284 | ||
1285 | static int __init pl011_console_setup(struct console *co, char *options) | |
1286 | { | |
1287 | struct uart_amba_port *uap; | |
1288 | int baud = 38400; | |
1289 | int bits = 8; | |
1290 | int parity = 'n'; | |
1291 | int flow = 'n'; | |
1292 | ||
1293 | /* | |
1294 | * Check whether an invalid uart number has been specified, and | |
1295 | * if so, search for the first available port that does have | |
1296 | * console support. | |
1297 | */ | |
1298 | if (co->index >= UART_NR) | |
1299 | co->index = 0; | |
1300 | uap = amba_ports[co->index]; | |
d28122a5 RK |
1301 | if (!uap) |
1302 | return -ENODEV; | |
1da177e4 LT |
1303 | |
1304 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1305 | ||
1306 | if (options) | |
1307 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1308 | else | |
1309 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
1310 | ||
1311 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
1312 | } | |
1313 | ||
2d93486c | 1314 | static struct uart_driver amba_reg; |
1da177e4 LT |
1315 | static struct console amba_console = { |
1316 | .name = "ttyAMA", | |
1317 | .write = pl011_console_write, | |
1318 | .device = uart_console_device, | |
1319 | .setup = pl011_console_setup, | |
1320 | .flags = CON_PRINTBUFFER, | |
1321 | .index = -1, | |
1322 | .data = &amba_reg, | |
1323 | }; | |
1324 | ||
1325 | #define AMBA_CONSOLE (&amba_console) | |
1326 | #else | |
1327 | #define AMBA_CONSOLE NULL | |
1328 | #endif | |
1329 | ||
1330 | static struct uart_driver amba_reg = { | |
1331 | .owner = THIS_MODULE, | |
1332 | .driver_name = "ttyAMA", | |
1333 | .dev_name = "ttyAMA", | |
1334 | .major = SERIAL_AMBA_MAJOR, | |
1335 | .minor = SERIAL_AMBA_MINOR, | |
1336 | .nr = UART_NR, | |
1337 | .cons = AMBA_CONSOLE, | |
1338 | }; | |
1339 | ||
03fbdb15 | 1340 | static int pl011_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 LT |
1341 | { |
1342 | struct uart_amba_port *uap; | |
5926a295 | 1343 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
1344 | void __iomem *base; |
1345 | int i, ret; | |
1346 | ||
1347 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1348 | if (amba_ports[i] == NULL) | |
1349 | break; | |
1350 | ||
1351 | if (i == ARRAY_SIZE(amba_ports)) { | |
1352 | ret = -EBUSY; | |
1353 | goto out; | |
1354 | } | |
1355 | ||
dd00cc48 | 1356 | uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); |
1da177e4 LT |
1357 | if (uap == NULL) { |
1358 | ret = -ENOMEM; | |
1359 | goto out; | |
1360 | } | |
1361 | ||
dc890c2d | 1362 | base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1363 | if (!base) { |
1364 | ret = -ENOMEM; | |
1365 | goto free; | |
1366 | } | |
1367 | ||
ee569c43 | 1368 | uap->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1369 | if (IS_ERR(uap->clk)) { |
1370 | ret = PTR_ERR(uap->clk); | |
1371 | goto unmap; | |
1372 | } | |
1373 | ||
c19f12b5 | 1374 | uap->vendor = vendor; |
ec489aa8 LW |
1375 | uap->lcrh_rx = vendor->lcrh_rx; |
1376 | uap->lcrh_tx = vendor->lcrh_tx; | |
ffca2b11 | 1377 | uap->fifosize = vendor->fifosize; |
1da177e4 LT |
1378 | uap->port.dev = &dev->dev; |
1379 | uap->port.mapbase = dev->res.start; | |
1380 | uap->port.membase = base; | |
1381 | uap->port.iotype = UPIO_MEM; | |
1382 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 1383 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
1384 | uap->port.ops = &amba_pl011_pops; |
1385 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
1386 | uap->port.line = i; | |
68b65f73 | 1387 | pl011_dma_probe(uap); |
1da177e4 | 1388 | |
e8a7ba86 RK |
1389 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
1390 | ||
1da177e4 LT |
1391 | amba_ports[i] = uap; |
1392 | ||
1393 | amba_set_drvdata(dev, uap); | |
1394 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
1395 | if (ret) { | |
1396 | amba_set_drvdata(dev, NULL); | |
1397 | amba_ports[i] = NULL; | |
68b65f73 | 1398 | pl011_dma_remove(uap); |
1da177e4 LT |
1399 | clk_put(uap->clk); |
1400 | unmap: | |
1401 | iounmap(base); | |
1402 | free: | |
1403 | kfree(uap); | |
1404 | } | |
1405 | out: | |
1406 | return ret; | |
1407 | } | |
1408 | ||
1409 | static int pl011_remove(struct amba_device *dev) | |
1410 | { | |
1411 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1412 | int i; | |
1413 | ||
1414 | amba_set_drvdata(dev, NULL); | |
1415 | ||
1416 | uart_remove_one_port(&amba_reg, &uap->port); | |
1417 | ||
1418 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1419 | if (amba_ports[i] == uap) | |
1420 | amba_ports[i] = NULL; | |
1421 | ||
68b65f73 | 1422 | pl011_dma_remove(uap); |
1da177e4 | 1423 | iounmap(uap->port.membase); |
1da177e4 LT |
1424 | clk_put(uap->clk); |
1425 | kfree(uap); | |
1426 | return 0; | |
1427 | } | |
1428 | ||
b736b89f LC |
1429 | #ifdef CONFIG_PM |
1430 | static int pl011_suspend(struct amba_device *dev, pm_message_t state) | |
1431 | { | |
1432 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1433 | ||
1434 | if (!uap) | |
1435 | return -EINVAL; | |
1436 | ||
1437 | return uart_suspend_port(&amba_reg, &uap->port); | |
1438 | } | |
1439 | ||
1440 | static int pl011_resume(struct amba_device *dev) | |
1441 | { | |
1442 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1443 | ||
1444 | if (!uap) | |
1445 | return -EINVAL; | |
1446 | ||
1447 | return uart_resume_port(&amba_reg, &uap->port); | |
1448 | } | |
1449 | #endif | |
1450 | ||
2c39c9e1 | 1451 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
1452 | { |
1453 | .id = 0x00041011, | |
1454 | .mask = 0x000fffff, | |
5926a295 AR |
1455 | .data = &vendor_arm, |
1456 | }, | |
1457 | { | |
1458 | .id = 0x00380802, | |
1459 | .mask = 0x00ffffff, | |
1460 | .data = &vendor_st, | |
1da177e4 LT |
1461 | }, |
1462 | { 0, 0 }, | |
1463 | }; | |
1464 | ||
1465 | static struct amba_driver pl011_driver = { | |
1466 | .drv = { | |
1467 | .name = "uart-pl011", | |
1468 | }, | |
1469 | .id_table = pl011_ids, | |
1470 | .probe = pl011_probe, | |
1471 | .remove = pl011_remove, | |
b736b89f LC |
1472 | #ifdef CONFIG_PM |
1473 | .suspend = pl011_suspend, | |
1474 | .resume = pl011_resume, | |
1475 | #endif | |
1da177e4 LT |
1476 | }; |
1477 | ||
1478 | static int __init pl011_init(void) | |
1479 | { | |
1480 | int ret; | |
1481 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
1482 | ||
1483 | ret = uart_register_driver(&amba_reg); | |
1484 | if (ret == 0) { | |
1485 | ret = amba_driver_register(&pl011_driver); | |
1486 | if (ret) | |
1487 | uart_unregister_driver(&amba_reg); | |
1488 | } | |
1489 | return ret; | |
1490 | } | |
1491 | ||
1492 | static void __exit pl011_exit(void) | |
1493 | { | |
1494 | amba_driver_unregister(&pl011_driver); | |
1495 | uart_unregister_driver(&amba_reg); | |
1496 | } | |
1497 | ||
4dd9e742 AR |
1498 | /* |
1499 | * While this can be a module, if builtin it's most likely the console | |
1500 | * So let's leave module_exit but move module_init to an earlier place | |
1501 | */ | |
1502 | arch_initcall(pl011_init); | |
1da177e4 LT |
1503 | module_exit(pl011_exit); |
1504 | ||
1505 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
1506 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
1507 | MODULE_LICENSE("GPL"); |