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ARM: PL011: include revision number in boot-time port printk
[mirror_ubuntu-bionic-kernel.git] / drivers / serial / amba-pl011.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
1da177e4
LT		 25 * This is a generic driver for ARM AMBA-type serial ports. They
26 * have a lot of 16550-like features, but are not register compatible.
27 * Note that although they do have CTS, DCD and DSR inputs, they do
28 * not have an RI input, nor do they have DTR or RTS outputs. If
29 * required, these have to be supplied via some other means (eg, GPIO)
30 * and hooked into this driver.
31 */
1da177e4
LT		 32
33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
a62c80e5
RK		 47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
f8ce2547 49#include <linux/clk.h>
5a0e3ad6 50#include <linux/slab.h>
1da177e4
LT		 51
52#include <asm/io.h>
c6b8fdad 53#include <asm/sizes.h>
1da177e4
LT		 54
55#define UART_NR 14
56
57#define SERIAL_AMBA_MAJOR 204
58#define SERIAL_AMBA_MINOR 64
59#define SERIAL_AMBA_NR UART_NR
60
61#define AMBA_ISR_PASS_LIMIT 256
62
b63d4f0f
RK		 63#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
64#define UART_DUMMY_DR_RX (1 << 16)
1da177e4
LT		 65
66/*
67 * We wrap our port structure around the generic uart_port.
68 */
69struct uart_amba_port {
70 struct uart_port port;
71 struct clk *clk;
ec489aa8 72 unsigned int im; /* interrupt mask */
1da177e4 73 unsigned int old_status;
ec489aa8
LW		 74 unsigned int ifls; /* vendor-specific */
75 unsigned int lcrh_tx; /* vendor-specific */
76 unsigned int lcrh_rx; /* vendor-specific */
ac3e3fb4 77 bool oversampling; /* vendor-specific */
3b43816f 78 bool autorts;
e8a7ba86 79 char type[12];
5926a295
AR		 80};
81
82/* There is by now at least one vendor with differing details, so handle it */
83struct vendor_data {
84 unsigned int ifls;
85 unsigned int fifosize;
ec489aa8
LW		 86 unsigned int lcrh_tx;
87 unsigned int lcrh_rx;
ac3e3fb4 88 bool oversampling;
5926a295
AR		 89};
90
91static struct vendor_data vendor_arm = {
92 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
93 .fifosize = 16,
ec489aa8
LW		 94 .lcrh_tx = UART011_LCRH,
95 .lcrh_rx = UART011_LCRH,
ac3e3fb4 96 .oversampling = false,
5926a295
AR		 97};
98
99static struct vendor_data vendor_st = {
100 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
101 .fifosize = 64,
ec489aa8
LW		 102 .lcrh_tx = ST_UART011_LCRH_TX,
103 .lcrh_rx = ST_UART011_LCRH_RX,
ac3e3fb4 104 .oversampling = true,
1da177e4
LT		 105};
106
b129a8cc 107static void pl011_stop_tx(struct uart_port *port)
1da177e4
LT		 108{
109 struct uart_amba_port *uap = (struct uart_amba_port *)port;
110
111 uap->im &= ~UART011_TXIM;
112 writew(uap->im, uap->port.membase + UART011_IMSC);
113}
114
b129a8cc 115static void pl011_start_tx(struct uart_port *port)
1da177e4
LT		 116{
117 struct uart_amba_port *uap = (struct uart_amba_port *)port;
118
119 uap->im |= UART011_TXIM;
120 writew(uap->im, uap->port.membase + UART011_IMSC);
121}
122
123static void pl011_stop_rx(struct uart_port *port)
124{
125 struct uart_amba_port *uap = (struct uart_amba_port *)port;
126
127 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
128 UART011_PEIM|UART011_BEIM|UART011_OEIM);
129 writew(uap->im, uap->port.membase + UART011_IMSC);
130}
131
132static void pl011_enable_ms(struct uart_port *port)
133{
134 struct uart_amba_port *uap = (struct uart_amba_port *)port;
135
136 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
137 writew(uap->im, uap->port.membase + UART011_IMSC);
138}
139
7d12e780 140static void pl011_rx_chars(struct uart_amba_port *uap)
1da177e4 141{
ebd2c8f6 142 struct tty_struct *tty = uap->port.state->port.tty;
b63d4f0f 143 unsigned int status, ch, flag, max_count = 256;
1da177e4
LT		 144
145 status = readw(uap->port.membase + UART01x_FR);
146 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
b63d4f0f 147 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
1da177e4
LT		 148 flag = TTY_NORMAL;
149 uap->port.icount.rx++;
150
151 /*
152 * Note that the error handling code is
153 * out of the main execution path
154 */
b63d4f0f
RK		 155 if (unlikely(ch & UART_DR_ERROR)) {
156 if (ch & UART011_DR_BE) {
157 ch &= ~(UART011_DR_FE | UART011_DR_PE);
1da177e4
LT		 158 uap->port.icount.brk++;
159 if (uart_handle_break(&uap->port))
160 goto ignore_char;
b63d4f0f 161 } else if (ch & UART011_DR_PE)
1da177e4 162 uap->port.icount.parity++;
b63d4f0f 163 else if (ch & UART011_DR_FE)
1da177e4 164 uap->port.icount.frame++;
b63d4f0f 165 if (ch & UART011_DR_OE)
1da177e4
LT		 166 uap->port.icount.overrun++;
167
b63d4f0f 168 ch &= uap->port.read_status_mask;
1da177e4 169
b63d4f0f 170 if (ch & UART011_DR_BE)
1da177e4 171 flag = TTY_BREAK;
b63d4f0f 172 else if (ch & UART011_DR_PE)
1da177e4 173 flag = TTY_PARITY;
b63d4f0f 174 else if (ch & UART011_DR_FE)
1da177e4
LT		 175 flag = TTY_FRAME;
176 }
177
7d12e780 178 if (uart_handle_sysrq_char(&uap->port, ch & 255))
1da177e4
LT		 179 goto ignore_char;
180
b63d4f0f 181 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
05ab3014 182
1da177e4
LT		 183 ignore_char:
184 status = readw(uap->port.membase + UART01x_FR);
185 }
2389b272 186 spin_unlock(&uap->port.lock);
1da177e4 187 tty_flip_buffer_push(tty);
2389b272 188 spin_lock(&uap->port.lock);
1da177e4
LT		 189}
190
191static void pl011_tx_chars(struct uart_amba_port *uap)
192{
ebd2c8f6 193 struct circ_buf *xmit = &uap->port.state->xmit;
1da177e4
LT		 194 int count;
195
196 if (uap->port.x_char) {
197 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
198 uap->port.icount.tx++;
199 uap->port.x_char = 0;
200 return;
201 }
202 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 203 pl011_stop_tx(&uap->port);
1da177e4
LT		 204 return;
205 }
206
207 count = uap->port.fifosize >> 1;
208 do {
209 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
210 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
211 uap->port.icount.tx++;
212 if (uart_circ_empty(xmit))
213 break;
214 } while (--count > 0);
215
216 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
217 uart_write_wakeup(&uap->port);
218
219 if (uart_circ_empty(xmit))
b129a8cc 220 pl011_stop_tx(&uap->port);
1da177e4
LT		 221}
222
223static void pl011_modem_status(struct uart_amba_port *uap)
224{
225 unsigned int status, delta;
226
227 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
228
229 delta = status ^ uap->old_status;
230 uap->old_status = status;
231
232 if (!delta)
233 return;
234
235 if (delta & UART01x_FR_DCD)
236 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
237
238 if (delta & UART01x_FR_DSR)
239 uap->port.icount.dsr++;
240
241 if (delta & UART01x_FR_CTS)
242 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
243
bdc04e31 244 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 245}
246
7d12e780 247static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 248{
249 struct uart_amba_port *uap = dev_id;
250 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
251 int handled = 0;
252
253 spin_lock(&uap->port.lock);
254
255 status = readw(uap->port.membase + UART011_MIS);
256 if (status) {
257 do {
258 writew(status & ~(UART011_TXIS|UART011_RTIS|
259 UART011_RXIS),
260 uap->port.membase + UART011_ICR);
261
262 if (status & (UART011_RTIS|UART011_RXIS))
1da177e4 263 pl011_rx_chars(uap);
1da177e4
LT		 264 if (status & (UART011_DSRMIS|UART011_DCDMIS|
265 UART011_CTSMIS|UART011_RIMIS))
266 pl011_modem_status(uap);
267 if (status & UART011_TXIS)
268 pl011_tx_chars(uap);
269
270 if (pass_counter-- == 0)
271 break;
272
273 status = readw(uap->port.membase + UART011_MIS);
274 } while (status != 0);
275 handled = 1;
276 }
277
278 spin_unlock(&uap->port.lock);
279
280 return IRQ_RETVAL(handled);
281}
282
283static unsigned int pl01x_tx_empty(struct uart_port *port)
284{
285 struct uart_amba_port *uap = (struct uart_amba_port *)port;
286 unsigned int status = readw(uap->port.membase + UART01x_FR);
287 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
288}
289
290static unsigned int pl01x_get_mctrl(struct uart_port *port)
291{
292 struct uart_amba_port *uap = (struct uart_amba_port *)port;
293 unsigned int result = 0;
294 unsigned int status = readw(uap->port.membase + UART01x_FR);
295
5159f407 296#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 297 if (status & uartbit) \
298 result |= tiocmbit
299
5159f407
JS		 300 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
301 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
302 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
303 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
304#undef TIOCMBIT
1da177e4
LT		 305 return result;
306}
307
308static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
309{
310 struct uart_amba_port *uap = (struct uart_amba_port *)port;
311 unsigned int cr;
312
313 cr = readw(uap->port.membase + UART011_CR);
314
5159f407 315#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 316 if (mctrl & tiocmbit) \
317 cr |= uartbit; \
318 else \
319 cr &= ~uartbit
320
5159f407
JS		 321 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
322 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
323 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
324 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
325 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f
RV		 326
327 if (uap->autorts) {
328 /* We need to disable auto-RTS if we want to turn RTS off */
329 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
330 }
5159f407 331#undef TIOCMBIT
1da177e4
LT		 332
333 writew(cr, uap->port.membase + UART011_CR);
334}
335
336static void pl011_break_ctl(struct uart_port *port, int break_state)
337{
338 struct uart_amba_port *uap = (struct uart_amba_port *)port;
339 unsigned long flags;
340 unsigned int lcr_h;
341
342 spin_lock_irqsave(&uap->port.lock, flags);
ec489aa8 343 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 344 if (break_state == -1)
345 lcr_h |= UART01x_LCRH_BRK;
346 else
347 lcr_h &= ~UART01x_LCRH_BRK;
ec489aa8 348 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 349 spin_unlock_irqrestore(&uap->port.lock, flags);
350}
351
84b5ae15
JW		 352#ifdef CONFIG_CONSOLE_POLL
353static int pl010_get_poll_char(struct uart_port *port)
354{
355 struct uart_amba_port *uap = (struct uart_amba_port *)port;
356 unsigned int status;
357
f5316b4a
JW		 358 status = readw(uap->port.membase + UART01x_FR);
359 if (status & UART01x_FR_RXFE)
360 return NO_POLL_CHAR;
84b5ae15
JW		 361
362 return readw(uap->port.membase + UART01x_DR);
363}
364
365static void pl010_put_poll_char(struct uart_port *port,
366 unsigned char ch)
367{
368 struct uart_amba_port *uap = (struct uart_amba_port *)port;
369
370 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
371 barrier();
372
373 writew(ch, uap->port.membase + UART01x_DR);
374}
375
376#endif /* CONFIG_CONSOLE_POLL */
377
1da177e4
LT		 378static int pl011_startup(struct uart_port *port)
379{
380 struct uart_amba_port *uap = (struct uart_amba_port *)port;
381 unsigned int cr;
382 int retval;
383
384 /*
385 * Try to enable the clock producer.
386 */
387 retval = clk_enable(uap->clk);
388 if (retval)
389 goto out;
390
391 uap->port.uartclk = clk_get_rate(uap->clk);
392
393 /*
394 * Allocate the IRQ
395 */
396 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
397 if (retval)
398 goto clk_dis;
399
5926a295 400 writew(uap->ifls, uap->port.membase + UART011_IFLS);
1da177e4
LT		 401
402 /*
403 * Provoke TX FIFO interrupt into asserting.
404 */
405 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
406 writew(cr, uap->port.membase + UART011_CR);
407 writew(0, uap->port.membase + UART011_FBRD);
408 writew(1, uap->port.membase + UART011_IBRD);
ec489aa8
LW		 409 writew(0, uap->port.membase + uap->lcrh_rx);
410 if (uap->lcrh_tx != uap->lcrh_rx) {
411 int i;
412 /*
413 * Wait 10 PCLKs before writing LCRH_TX register,
414 * to get this delay write read only register 10 times
415 */
416 for (i = 0; i < 10; ++i)
417 writew(0xff, uap->port.membase + UART011_MIS);
418 writew(0, uap->port.membase + uap->lcrh_tx);
419 }
1da177e4
LT		 420 writew(0, uap->port.membase + UART01x_DR);
421 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
422 barrier();
423
424 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
425 writew(cr, uap->port.membase + UART011_CR);
426
427 /*
428 * initialise the old status of the modem signals
429 */
430 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
431
432 /*
433 * Finally, enable interrupts
434 */
435 spin_lock_irq(&uap->port.lock);
436 uap->im = UART011_RXIM | UART011_RTIM;
437 writew(uap->im, uap->port.membase + UART011_IMSC);
438 spin_unlock_irq(&uap->port.lock);
439
440 return 0;
441
442 clk_dis:
443 clk_disable(uap->clk);
444 out:
445 return retval;
446}
447
ec489aa8
LW		 448static void pl011_shutdown_channel(struct uart_amba_port *uap,
449 unsigned int lcrh)
450{
451 unsigned long val;
452
453 val = readw(uap->port.membase + lcrh);
454 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
455 writew(val, uap->port.membase + lcrh);
456}
457
1da177e4
LT		 458static void pl011_shutdown(struct uart_port *port)
459{
460 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 461
462 /*
463 * disable all interrupts
464 */
465 spin_lock_irq(&uap->port.lock);
466 uap->im = 0;
467 writew(uap->im, uap->port.membase + UART011_IMSC);
468 writew(0xffff, uap->port.membase + UART011_ICR);
469 spin_unlock_irq(&uap->port.lock);
470
471 /*
472 * Free the interrupt
473 */
474 free_irq(uap->port.irq, uap);
475
476 /*
477 * disable the port
478 */
3b43816f 479 uap->autorts = false;
1da177e4
LT		 480 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
481
482 /*
483 * disable break condition and fifos
484 */
ec489aa8
LW		 485 pl011_shutdown_channel(uap, uap->lcrh_rx);
486 if (uap->lcrh_rx != uap->lcrh_tx)
487 pl011_shutdown_channel(uap, uap->lcrh_tx);
1da177e4
LT		 488
489 /*
490 * Shut down the clock producer
491 */
492 clk_disable(uap->clk);
493}
494
495static void
606d099c
AC		 496pl011_set_termios(struct uart_port *port, struct ktermios *termios,
497 struct ktermios *old)
1da177e4 498{
3b43816f 499 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 500 unsigned int lcr_h, old_cr;
501 unsigned long flags;
502 unsigned int baud, quot;
503
504 /*
505 * Ask the core to calculate the divisor for us.
506 */
ac3e3fb4
LW		 507 baud = uart_get_baud_rate(port, termios, old, 0,
508 port->uartclk/(uap->oversampling ? 8 : 16));
509
510 if (baud > port->uartclk/16)
511 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
512 else
513 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 514
515 switch (termios->c_cflag & CSIZE) {
516 case CS5:
517 lcr_h = UART01x_LCRH_WLEN_5;
518 break;
519 case CS6:
520 lcr_h = UART01x_LCRH_WLEN_6;
521 break;
522 case CS7:
523 lcr_h = UART01x_LCRH_WLEN_7;
524 break;
525 default: // CS8
526 lcr_h = UART01x_LCRH_WLEN_8;
527 break;
528 }
529 if (termios->c_cflag & CSTOPB)
530 lcr_h |= UART01x_LCRH_STP2;
531 if (termios->c_cflag & PARENB) {
532 lcr_h |= UART01x_LCRH_PEN;
533 if (!(termios->c_cflag & PARODD))
534 lcr_h |= UART01x_LCRH_EPS;
535 }
536 if (port->fifosize > 1)
537 lcr_h |= UART01x_LCRH_FEN;
538
539 spin_lock_irqsave(&port->lock, flags);
540
541 /*
542 * Update the per-port timeout.
543 */
544 uart_update_timeout(port, termios->c_cflag, baud);
545
b63d4f0f 546 port->read_status_mask = UART011_DR_OE | 255;
1da177e4 547 if (termios->c_iflag & INPCK)
b63d4f0f 548 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1da177e4 549 if (termios->c_iflag & (BRKINT | PARMRK))
b63d4f0f 550 port->read_status_mask |= UART011_DR_BE;
1da177e4
LT		 551
552 /*
553 * Characters to ignore
554 */
555 port->ignore_status_mask = 0;
556 if (termios->c_iflag & IGNPAR)
b63d4f0f 557 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1da177e4 558 if (termios->c_iflag & IGNBRK) {
b63d4f0f 559 port->ignore_status_mask |= UART011_DR_BE;
1da177e4
LT		 560 /*
561 * If we're ignoring parity and break indicators,
562 * ignore overruns too (for real raw support).
563 */
564 if (termios->c_iflag & IGNPAR)
b63d4f0f 565 port->ignore_status_mask |= UART011_DR_OE;
1da177e4
LT		 566 }
567
568 /*
569 * Ignore all characters if CREAD is not set.
570 */
571 if ((termios->c_cflag & CREAD) == 0)
b63d4f0f 572 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1da177e4
LT		 573
574 if (UART_ENABLE_MS(port, termios->c_cflag))
575 pl011_enable_ms(port);
576
577 /* first, disable everything */
578 old_cr = readw(port->membase + UART011_CR);
579 writew(0, port->membase + UART011_CR);
580
3b43816f
RV		 581 if (termios->c_cflag & CRTSCTS) {
582 if (old_cr & UART011_CR_RTS)
583 old_cr |= UART011_CR_RTSEN;
584
585 old_cr |= UART011_CR_CTSEN;
586 uap->autorts = true;
587 } else {
588 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
589 uap->autorts = false;
590 }
591
ac3e3fb4
LW		 592 if (uap->oversampling) {
593 if (baud > port->uartclk/16)
594 old_cr |= ST_UART011_CR_OVSFACT;
595 else
596 old_cr &= ~ST_UART011_CR_OVSFACT;
597 }
598
1da177e4
LT		 599 /* Set baud rate */
600 writew(quot & 0x3f, port->membase + UART011_FBRD);
601 writew(quot >> 6, port->membase + UART011_IBRD);
602
603 /*
604 * ----------v----------v----------v----------v-----
605 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
606 * ----------^----------^----------^----------^-----
607 */
ec489aa8
LW		 608 writew(lcr_h, port->membase + uap->lcrh_rx);
609 if (uap->lcrh_rx != uap->lcrh_tx) {
610 int i;
611 /*
612 * Wait 10 PCLKs before writing LCRH_TX register,
613 * to get this delay write read only register 10 times
614 */
615 for (i = 0; i < 10; ++i)
616 writew(0xff, uap->port.membase + UART011_MIS);
617 writew(lcr_h, port->membase + uap->lcrh_tx);
618 }
1da177e4
LT		 619 writew(old_cr, port->membase + UART011_CR);
620
621 spin_unlock_irqrestore(&port->lock, flags);
622}
623
624static const char *pl011_type(struct uart_port *port)
625{
e8a7ba86
RK		 626 struct uart_amba_port *uap = (struct uart_amba_port *)port;
627 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 628}
629
630/*
631 * Release the memory region(s) being used by 'port'
632 */
633static void pl010_release_port(struct uart_port *port)
634{
635 release_mem_region(port->mapbase, SZ_4K);
636}
637
638/*
639 * Request the memory region(s) being used by 'port'
640 */
641static int pl010_request_port(struct uart_port *port)
642{
643 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
644 != NULL ? 0 : -EBUSY;
645}
646
647/*
648 * Configure/autoconfigure the port.
649 */
650static void pl010_config_port(struct uart_port *port, int flags)
651{
652 if (flags & UART_CONFIG_TYPE) {
653 port->type = PORT_AMBA;
654 pl010_request_port(port);
655 }
656}
657
658/*
659 * verify the new serial_struct (for TIOCSSERIAL).
660 */
661static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
662{
663 int ret = 0;
664 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
665 ret = -EINVAL;
a62c4133 666 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 667 ret = -EINVAL;
668 if (ser->baud_base < 9600)
669 ret = -EINVAL;
670 return ret;
671}
672
673static struct uart_ops amba_pl011_pops = {
674 .tx_empty = pl01x_tx_empty,
675 .set_mctrl = pl011_set_mctrl,
676 .get_mctrl = pl01x_get_mctrl,
677 .stop_tx = pl011_stop_tx,
678 .start_tx = pl011_start_tx,
679 .stop_rx = pl011_stop_rx,
680 .enable_ms = pl011_enable_ms,
681 .break_ctl = pl011_break_ctl,
682 .startup = pl011_startup,
683 .shutdown = pl011_shutdown,
684 .set_termios = pl011_set_termios,
685 .type = pl011_type,
686 .release_port = pl010_release_port,
687 .request_port = pl010_request_port,
688 .config_port = pl010_config_port,
689 .verify_port = pl010_verify_port,
84b5ae15
JW		 690#ifdef CONFIG_CONSOLE_POLL
691 .poll_get_char = pl010_get_poll_char,
692 .poll_put_char = pl010_put_poll_char,
693#endif
1da177e4
LT		 694};
695
696static struct uart_amba_port *amba_ports[UART_NR];
697
698#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
699
d358788f 700static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 701{
d358788f 702 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4 703
d358788f
RK		 704 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
705 barrier();
1da177e4
LT		 706 writew(ch, uap->port.membase + UART01x_DR);
707}
708
709static void
710pl011_console_write(struct console *co, const char *s, unsigned int count)
711{
712 struct uart_amba_port *uap = amba_ports[co->index];
713 unsigned int status, old_cr, new_cr;
1da177e4
LT		 714
715 clk_enable(uap->clk);
716
717 /*
718 * First save the CR then disable the interrupts
719 */
720 old_cr = readw(uap->port.membase + UART011_CR);
721 new_cr = old_cr & ~UART011_CR_CTSEN;
722 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
723 writew(new_cr, uap->port.membase + UART011_CR);
724
d358788f 725 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 726
727 /*
728 * Finally, wait for transmitter to become empty
729 * and restore the TCR
730 */
731 do {
732 status = readw(uap->port.membase + UART01x_FR);
733 } while (status & UART01x_FR_BUSY);
734 writew(old_cr, uap->port.membase + UART011_CR);
735
736 clk_disable(uap->clk);
737}
738
739static void __init
740pl011_console_get_options(struct uart_amba_port *uap, int *baud,
741 int *parity, int *bits)
742{
743 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
744 unsigned int lcr_h, ibrd, fbrd;
745
ec489aa8 746 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 747
748 *parity = 'n';
749 if (lcr_h & UART01x_LCRH_PEN) {
750 if (lcr_h & UART01x_LCRH_EPS)
751 *parity = 'e';
752 else
753 *parity = 'o';
754 }
755
756 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
757 *bits = 7;
758 else
759 *bits = 8;
760
761 ibrd = readw(uap->port.membase + UART011_IBRD);
762 fbrd = readw(uap->port.membase + UART011_FBRD);
763
764 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4
LW		 765
766 if (uap->oversampling) {
767 if (readw(uap->port.membase + UART011_CR)
768 & ST_UART011_CR_OVSFACT)
769 *baud *= 2;
770 }
1da177e4
LT		 771 }
772}
773
774static int __init pl011_console_setup(struct console *co, char *options)
775{
776 struct uart_amba_port *uap;
777 int baud = 38400;
778 int bits = 8;
779 int parity = 'n';
780 int flow = 'n';
781
782 /*
783 * Check whether an invalid uart number has been specified, and
784 * if so, search for the first available port that does have
785 * console support.
786 */
787 if (co->index >= UART_NR)
788 co->index = 0;
789 uap = amba_ports[co->index];
d28122a5
RK		 790 if (!uap)
791 return -ENODEV;
1da177e4
LT		 792
793 uap->port.uartclk = clk_get_rate(uap->clk);
794
795 if (options)
796 uart_parse_options(options, &baud, &parity, &bits, &flow);
797 else
798 pl011_console_get_options(uap, &baud, &parity, &bits);
799
800 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
801}
802
2d93486c 803static struct uart_driver amba_reg;
1da177e4
LT		 804static struct console amba_console = {
805 .name = "ttyAMA",
806 .write = pl011_console_write,
807 .device = uart_console_device,
808 .setup = pl011_console_setup,
809 .flags = CON_PRINTBUFFER,
810 .index = -1,
811 .data = &amba_reg,
812};
813
814#define AMBA_CONSOLE (&amba_console)
815#else
816#define AMBA_CONSOLE NULL
817#endif
818
819static struct uart_driver amba_reg = {
820 .owner = THIS_MODULE,
821 .driver_name = "ttyAMA",
822 .dev_name = "ttyAMA",
823 .major = SERIAL_AMBA_MAJOR,
824 .minor = SERIAL_AMBA_MINOR,
825 .nr = UART_NR,
826 .cons = AMBA_CONSOLE,
827};
828
03fbdb15 829static int pl011_probe(struct amba_device *dev, struct amba_id *id)
1da177e4
LT		 830{
831 struct uart_amba_port *uap;
5926a295 832 struct vendor_data *vendor = id->data;
1da177e4
LT		 833 void __iomem *base;
834 int i, ret;
835
836 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
837 if (amba_ports[i] == NULL)
838 break;
839
840 if (i == ARRAY_SIZE(amba_ports)) {
841 ret = -EBUSY;
842 goto out;
843 }
844
dd00cc48 845 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1da177e4
LT		 846 if (uap == NULL) {
847 ret = -ENOMEM;
848 goto out;
849 }
850
dc890c2d 851 base = ioremap(dev->res.start, resource_size(&dev->res));
1da177e4
LT		 852 if (!base) {
853 ret = -ENOMEM;
854 goto free;
855 }
856
ee569c43 857 uap->clk = clk_get(&dev->dev, NULL);
1da177e4
LT		 858 if (IS_ERR(uap->clk)) {
859 ret = PTR_ERR(uap->clk);
860 goto unmap;
861 }
862
5926a295 863 uap->ifls = vendor->ifls;
ec489aa8
LW		 864 uap->lcrh_rx = vendor->lcrh_rx;
865 uap->lcrh_tx = vendor->lcrh_tx;
ac3e3fb4 866 uap->oversampling = vendor->oversampling;
1da177e4
LT		 867 uap->port.dev = &dev->dev;
868 uap->port.mapbase = dev->res.start;
869 uap->port.membase = base;
870 uap->port.iotype = UPIO_MEM;
871 uap->port.irq = dev->irq[0];
5926a295 872 uap->port.fifosize = vendor->fifosize;
1da177e4
LT		 873 uap->port.ops = &amba_pl011_pops;
874 uap->port.flags = UPF_BOOT_AUTOCONF;
875 uap->port.line = i;
876
e8a7ba86
RK		 877 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
878
1da177e4
LT		 879 amba_ports[i] = uap;
880
881 amba_set_drvdata(dev, uap);
882 ret = uart_add_one_port(&amba_reg, &uap->port);
883 if (ret) {
884 amba_set_drvdata(dev, NULL);
885 amba_ports[i] = NULL;
1da177e4
LT		 886 clk_put(uap->clk);
887 unmap:
888 iounmap(base);
889 free:
890 kfree(uap);
891 }
892 out:
893 return ret;
894}
895
896static int pl011_remove(struct amba_device *dev)
897{
898 struct uart_amba_port *uap = amba_get_drvdata(dev);
899 int i;
900
901 amba_set_drvdata(dev, NULL);
902
903 uart_remove_one_port(&amba_reg, &uap->port);
904
905 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
906 if (amba_ports[i] == uap)
907 amba_ports[i] = NULL;
908
909 iounmap(uap->port.membase);
1da177e4
LT		 910 clk_put(uap->clk);
911 kfree(uap);
912 return 0;
913}
914
b736b89f
LC		 915#ifdef CONFIG_PM
916static int pl011_suspend(struct amba_device *dev, pm_message_t state)
917{
918 struct uart_amba_port *uap = amba_get_drvdata(dev);
919
920 if (!uap)
921 return -EINVAL;
922
923 return uart_suspend_port(&amba_reg, &uap->port);
924}
925
926static int pl011_resume(struct amba_device *dev)
927{
928 struct uart_amba_port *uap = amba_get_drvdata(dev);
929
930 if (!uap)
931 return -EINVAL;
932
933 return uart_resume_port(&amba_reg, &uap->port);
934}
935#endif
936
2c39c9e1 937static struct amba_id pl011_ids[] = {
1da177e4
LT		 938 {
939 .id = 0x00041011,
940 .mask = 0x000fffff,
5926a295
AR		 941 .data = &vendor_arm,
942 },
943 {
944 .id = 0x00380802,
945 .mask = 0x00ffffff,
946 .data = &vendor_st,
1da177e4
LT		 947 },
948 { 0, 0 },
949};
950
951static struct amba_driver pl011_driver = {
952 .drv = {
953 .name = "uart-pl011",
954 },
955 .id_table = pl011_ids,
956 .probe = pl011_probe,
957 .remove = pl011_remove,
b736b89f
LC		 958#ifdef CONFIG_PM
959 .suspend = pl011_suspend,
960 .resume = pl011_resume,
961#endif
1da177e4
LT		 962};
963
964static int __init pl011_init(void)
965{
966 int ret;
967 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
968
969 ret = uart_register_driver(&amba_reg);
970 if (ret == 0) {
971 ret = amba_driver_register(&pl011_driver);
972 if (ret)
973 uart_unregister_driver(&amba_reg);
974 }
975 return ret;
976}
977
978static void __exit pl011_exit(void)
979{
980 amba_driver_unregister(&pl011_driver);
981 uart_unregister_driver(&amba_reg);
982}
983
4dd9e742
AR		 984/*
985 * While this can be a module, if builtin it's most likely the console
986 * So let's leave module_exit but move module_init to an earlier place
987 */
988arch_initcall(pl011_init);
1da177e4
LT		 989module_exit(pl011_exit);
990
991MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
992MODULE_DESCRIPTION("ARM AMBA serial port driver");
993MODULE_LICENSE("GPL");
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