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ARM: PL011: Separate hardware FIFO size from TTY FIFO size
[mirror_ubuntu-artful-kernel.git] / drivers / serial / amba-pl011.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
1da177e4
LT		 25 * This is a generic driver for ARM AMBA-type serial ports. They
26 * have a lot of 16550-like features, but are not register compatible.
27 * Note that although they do have CTS, DCD and DSR inputs, they do
28 * not have an RI input, nor do they have DTR or RTS outputs. If
29 * required, these have to be supplied via some other means (eg, GPIO)
30 * and hooked into this driver.
31 */
1da177e4
LT		 32
33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
a62c80e5
RK		 47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
f8ce2547 49#include <linux/clk.h>
5a0e3ad6 50#include <linux/slab.h>
1da177e4
LT		 51
52#include <asm/io.h>
c6b8fdad 53#include <asm/sizes.h>
1da177e4
LT		 54
55#define UART_NR 14
56
57#define SERIAL_AMBA_MAJOR 204
58#define SERIAL_AMBA_MINOR 64
59#define SERIAL_AMBA_NR UART_NR
60
61#define AMBA_ISR_PASS_LIMIT 256
62
b63d4f0f
RK		 63#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
64#define UART_DUMMY_DR_RX (1 << 16)
1da177e4 65
5926a295
AR		 66/* There is by now at least one vendor with differing details, so handle it */
67struct vendor_data {
68 unsigned int ifls;
69 unsigned int fifosize;
ec489aa8
LW		 70 unsigned int lcrh_tx;
71 unsigned int lcrh_rx;
ac3e3fb4 72 bool oversampling;
5926a295
AR		 73};
74
75static struct vendor_data vendor_arm = {
76 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
77 .fifosize = 16,
ec489aa8
LW		 78 .lcrh_tx = UART011_LCRH,
79 .lcrh_rx = UART011_LCRH,
ac3e3fb4 80 .oversampling = false,
5926a295
AR		 81};
82
83static struct vendor_data vendor_st = {
84 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
85 .fifosize = 64,
ec489aa8
LW		 86 .lcrh_tx = ST_UART011_LCRH_TX,
87 .lcrh_rx = ST_UART011_LCRH_RX,
ac3e3fb4 88 .oversampling = true,
1da177e4
LT		 89};
90
c19f12b5
RK		 91/*
92 * We wrap our port structure around the generic uart_port.
93 */
94struct uart_amba_port {
95 struct uart_port port;
96 struct clk *clk;
97 const struct vendor_data *vendor;
98 unsigned int im; /* interrupt mask */
99 unsigned int old_status;
ffca2b11 100 unsigned int fifosize; /* vendor-specific */
c19f12b5
RK		 101 unsigned int lcrh_tx; /* vendor-specific */
102 unsigned int lcrh_rx; /* vendor-specific */
103 bool autorts;
104 char type[12];
105};
106
b129a8cc 107static void pl011_stop_tx(struct uart_port *port)
1da177e4
LT		 108{
109 struct uart_amba_port *uap = (struct uart_amba_port *)port;
110
111 uap->im &= ~UART011_TXIM;
112 writew(uap->im, uap->port.membase + UART011_IMSC);
113}
114
b129a8cc 115static void pl011_start_tx(struct uart_port *port)
1da177e4
LT		 116{
117 struct uart_amba_port *uap = (struct uart_amba_port *)port;
118
119 uap->im |= UART011_TXIM;
120 writew(uap->im, uap->port.membase + UART011_IMSC);
121}
122
123static void pl011_stop_rx(struct uart_port *port)
124{
125 struct uart_amba_port *uap = (struct uart_amba_port *)port;
126
127 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
128 UART011_PEIM|UART011_BEIM|UART011_OEIM);
129 writew(uap->im, uap->port.membase + UART011_IMSC);
130}
131
132static void pl011_enable_ms(struct uart_port *port)
133{
134 struct uart_amba_port *uap = (struct uart_amba_port *)port;
135
136 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
137 writew(uap->im, uap->port.membase + UART011_IMSC);
138}
139
7d12e780 140static void pl011_rx_chars(struct uart_amba_port *uap)
1da177e4 141{
ebd2c8f6 142 struct tty_struct *tty = uap->port.state->port.tty;
b63d4f0f 143 unsigned int status, ch, flag, max_count = 256;
1da177e4
LT		 144
145 status = readw(uap->port.membase + UART01x_FR);
146 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
b63d4f0f 147 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
1da177e4
LT		 148 flag = TTY_NORMAL;
149 uap->port.icount.rx++;
150
151 /*
152 * Note that the error handling code is
153 * out of the main execution path
154 */
b63d4f0f
RK		 155 if (unlikely(ch & UART_DR_ERROR)) {
156 if (ch & UART011_DR_BE) {
157 ch &= ~(UART011_DR_FE | UART011_DR_PE);
1da177e4
LT		 158 uap->port.icount.brk++;
159 if (uart_handle_break(&uap->port))
160 goto ignore_char;
b63d4f0f 161 } else if (ch & UART011_DR_PE)
1da177e4 162 uap->port.icount.parity++;
b63d4f0f 163 else if (ch & UART011_DR_FE)
1da177e4 164 uap->port.icount.frame++;
b63d4f0f 165 if (ch & UART011_DR_OE)
1da177e4
LT		 166 uap->port.icount.overrun++;
167
b63d4f0f 168 ch &= uap->port.read_status_mask;
1da177e4 169
b63d4f0f 170 if (ch & UART011_DR_BE)
1da177e4 171 flag = TTY_BREAK;
b63d4f0f 172 else if (ch & UART011_DR_PE)
1da177e4 173 flag = TTY_PARITY;
b63d4f0f 174 else if (ch & UART011_DR_FE)
1da177e4
LT		 175 flag = TTY_FRAME;
176 }
177
7d12e780 178 if (uart_handle_sysrq_char(&uap->port, ch & 255))
1da177e4
LT		 179 goto ignore_char;
180
b63d4f0f 181 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
05ab3014 182
1da177e4
LT		 183 ignore_char:
184 status = readw(uap->port.membase + UART01x_FR);
185 }
2389b272 186 spin_unlock(&uap->port.lock);
1da177e4 187 tty_flip_buffer_push(tty);
2389b272 188 spin_lock(&uap->port.lock);
1da177e4
LT		 189}
190
191static void pl011_tx_chars(struct uart_amba_port *uap)
192{
ebd2c8f6 193 struct circ_buf *xmit = &uap->port.state->xmit;
1da177e4
LT		 194 int count;
195
196 if (uap->port.x_char) {
197 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
198 uap->port.icount.tx++;
199 uap->port.x_char = 0;
200 return;
201 }
202 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 203 pl011_stop_tx(&uap->port);
1da177e4
LT		 204 return;
205 }
206
ffca2b11 207 count = uap->fifosize >> 1;
1da177e4
LT		 208 do {
209 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
210 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
211 uap->port.icount.tx++;
212 if (uart_circ_empty(xmit))
213 break;
214 } while (--count > 0);
215
216 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
217 uart_write_wakeup(&uap->port);
218
219 if (uart_circ_empty(xmit))
b129a8cc 220 pl011_stop_tx(&uap->port);
1da177e4
LT		 221}
222
223static void pl011_modem_status(struct uart_amba_port *uap)
224{
225 unsigned int status, delta;
226
227 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
228
229 delta = status ^ uap->old_status;
230 uap->old_status = status;
231
232 if (!delta)
233 return;
234
235 if (delta & UART01x_FR_DCD)
236 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
237
238 if (delta & UART01x_FR_DSR)
239 uap->port.icount.dsr++;
240
241 if (delta & UART01x_FR_CTS)
242 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
243
bdc04e31 244 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 245}
246
7d12e780 247static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 248{
249 struct uart_amba_port *uap = dev_id;
250 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
251 int handled = 0;
252
253 spin_lock(&uap->port.lock);
254
255 status = readw(uap->port.membase + UART011_MIS);
256 if (status) {
257 do {
258 writew(status & ~(UART011_TXIS|UART011_RTIS|
259 UART011_RXIS),
260 uap->port.membase + UART011_ICR);
261
262 if (status & (UART011_RTIS|UART011_RXIS))
1da177e4 263 pl011_rx_chars(uap);
1da177e4
LT		 264 if (status & (UART011_DSRMIS|UART011_DCDMIS|
265 UART011_CTSMIS|UART011_RIMIS))
266 pl011_modem_status(uap);
267 if (status & UART011_TXIS)
268 pl011_tx_chars(uap);
269
270 if (pass_counter-- == 0)
271 break;
272
273 status = readw(uap->port.membase + UART011_MIS);
274 } while (status != 0);
275 handled = 1;
276 }
277
278 spin_unlock(&uap->port.lock);
279
280 return IRQ_RETVAL(handled);
281}
282
283static unsigned int pl01x_tx_empty(struct uart_port *port)
284{
285 struct uart_amba_port *uap = (struct uart_amba_port *)port;
286 unsigned int status = readw(uap->port.membase + UART01x_FR);
287 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
288}
289
290static unsigned int pl01x_get_mctrl(struct uart_port *port)
291{
292 struct uart_amba_port *uap = (struct uart_amba_port *)port;
293 unsigned int result = 0;
294 unsigned int status = readw(uap->port.membase + UART01x_FR);
295
5159f407 296#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 297 if (status & uartbit) \
298 result |= tiocmbit
299
5159f407
JS		 300 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
301 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
302 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
303 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
304#undef TIOCMBIT
1da177e4
LT		 305 return result;
306}
307
308static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
309{
310 struct uart_amba_port *uap = (struct uart_amba_port *)port;
311 unsigned int cr;
312
313 cr = readw(uap->port.membase + UART011_CR);
314
5159f407 315#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 316 if (mctrl & tiocmbit) \
317 cr |= uartbit; \
318 else \
319 cr &= ~uartbit
320
5159f407
JS		 321 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
322 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
323 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
324 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
325 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f
RV		 326
327 if (uap->autorts) {
328 /* We need to disable auto-RTS if we want to turn RTS off */
329 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
330 }
5159f407 331#undef TIOCMBIT
1da177e4
LT		 332
333 writew(cr, uap->port.membase + UART011_CR);
334}
335
336static void pl011_break_ctl(struct uart_port *port, int break_state)
337{
338 struct uart_amba_port *uap = (struct uart_amba_port *)port;
339 unsigned long flags;
340 unsigned int lcr_h;
341
342 spin_lock_irqsave(&uap->port.lock, flags);
ec489aa8 343 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 344 if (break_state == -1)
345 lcr_h |= UART01x_LCRH_BRK;
346 else
347 lcr_h &= ~UART01x_LCRH_BRK;
ec489aa8 348 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 349 spin_unlock_irqrestore(&uap->port.lock, flags);
350}
351
84b5ae15
JW		 352#ifdef CONFIG_CONSOLE_POLL
353static int pl010_get_poll_char(struct uart_port *port)
354{
355 struct uart_amba_port *uap = (struct uart_amba_port *)port;
356 unsigned int status;
357
f5316b4a
JW		 358 status = readw(uap->port.membase + UART01x_FR);
359 if (status & UART01x_FR_RXFE)
360 return NO_POLL_CHAR;
84b5ae15
JW		 361
362 return readw(uap->port.membase + UART01x_DR);
363}
364
365static void pl010_put_poll_char(struct uart_port *port,
366 unsigned char ch)
367{
368 struct uart_amba_port *uap = (struct uart_amba_port *)port;
369
370 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
371 barrier();
372
373 writew(ch, uap->port.membase + UART01x_DR);
374}
375
376#endif /* CONFIG_CONSOLE_POLL */
377
1da177e4
LT		 378static int pl011_startup(struct uart_port *port)
379{
380 struct uart_amba_port *uap = (struct uart_amba_port *)port;
381 unsigned int cr;
382 int retval;
383
384 /*
385 * Try to enable the clock producer.
386 */
387 retval = clk_enable(uap->clk);
388 if (retval)
389 goto out;
390
391 uap->port.uartclk = clk_get_rate(uap->clk);
392
393 /*
394 * Allocate the IRQ
395 */
396 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
397 if (retval)
398 goto clk_dis;
399
c19f12b5 400 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1da177e4
LT		 401
402 /*
403 * Provoke TX FIFO interrupt into asserting.
404 */
405 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
406 writew(cr, uap->port.membase + UART011_CR);
407 writew(0, uap->port.membase + UART011_FBRD);
408 writew(1, uap->port.membase + UART011_IBRD);
ec489aa8
LW		 409 writew(0, uap->port.membase + uap->lcrh_rx);
410 if (uap->lcrh_tx != uap->lcrh_rx) {
411 int i;
412 /*
413 * Wait 10 PCLKs before writing LCRH_TX register,
414 * to get this delay write read only register 10 times
415 */
416 for (i = 0; i < 10; ++i)
417 writew(0xff, uap->port.membase + UART011_MIS);
418 writew(0, uap->port.membase + uap->lcrh_tx);
419 }
1da177e4
LT		 420 writew(0, uap->port.membase + UART01x_DR);
421 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
422 barrier();
423
424 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
425 writew(cr, uap->port.membase + UART011_CR);
426
5063e2c5
RK		 427 /* Clear pending error interrupts */
428 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
429 uap->port.membase + UART011_ICR);
430
1da177e4
LT		 431 /*
432 * initialise the old status of the modem signals
433 */
434 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
435
436 /*
437 * Finally, enable interrupts
438 */
439 spin_lock_irq(&uap->port.lock);
440 uap->im = UART011_RXIM | UART011_RTIM;
441 writew(uap->im, uap->port.membase + UART011_IMSC);
442 spin_unlock_irq(&uap->port.lock);
443
444 return 0;
445
446 clk_dis:
447 clk_disable(uap->clk);
448 out:
449 return retval;
450}
451
ec489aa8
LW		 452static void pl011_shutdown_channel(struct uart_amba_port *uap,
453 unsigned int lcrh)
454{
455 unsigned long val;
456
457 val = readw(uap->port.membase + lcrh);
458 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
459 writew(val, uap->port.membase + lcrh);
460}
461
1da177e4
LT		 462static void pl011_shutdown(struct uart_port *port)
463{
464 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 465
466 /*
467 * disable all interrupts
468 */
469 spin_lock_irq(&uap->port.lock);
470 uap->im = 0;
471 writew(uap->im, uap->port.membase + UART011_IMSC);
472 writew(0xffff, uap->port.membase + UART011_ICR);
473 spin_unlock_irq(&uap->port.lock);
474
475 /*
476 * Free the interrupt
477 */
478 free_irq(uap->port.irq, uap);
479
480 /*
481 * disable the port
482 */
3b43816f 483 uap->autorts = false;
1da177e4
LT		 484 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
485
486 /*
487 * disable break condition and fifos
488 */
ec489aa8
LW		 489 pl011_shutdown_channel(uap, uap->lcrh_rx);
490 if (uap->lcrh_rx != uap->lcrh_tx)
491 pl011_shutdown_channel(uap, uap->lcrh_tx);
1da177e4
LT		 492
493 /*
494 * Shut down the clock producer
495 */
496 clk_disable(uap->clk);
497}
498
499static void
606d099c
AC		 500pl011_set_termios(struct uart_port *port, struct ktermios *termios,
501 struct ktermios *old)
1da177e4 502{
3b43816f 503 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 504 unsigned int lcr_h, old_cr;
505 unsigned long flags;
c19f12b5
RK		 506 unsigned int baud, quot, clkdiv;
507
508 if (uap->vendor->oversampling)
509 clkdiv = 8;
510 else
511 clkdiv = 16;
1da177e4
LT		 512
513 /*
514 * Ask the core to calculate the divisor for us.
515 */
ac3e3fb4 516 baud = uart_get_baud_rate(port, termios, old, 0,
c19f12b5 517 port->uartclk / clkdiv);
ac3e3fb4
LW		 518
519 if (baud > port->uartclk/16)
520 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
521 else
522 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 523
524 switch (termios->c_cflag & CSIZE) {
525 case CS5:
526 lcr_h = UART01x_LCRH_WLEN_5;
527 break;
528 case CS6:
529 lcr_h = UART01x_LCRH_WLEN_6;
530 break;
531 case CS7:
532 lcr_h = UART01x_LCRH_WLEN_7;
533 break;
534 default: // CS8
535 lcr_h = UART01x_LCRH_WLEN_8;
536 break;
537 }
538 if (termios->c_cflag & CSTOPB)
539 lcr_h |= UART01x_LCRH_STP2;
540 if (termios->c_cflag & PARENB) {
541 lcr_h |= UART01x_LCRH_PEN;
542 if (!(termios->c_cflag & PARODD))
543 lcr_h |= UART01x_LCRH_EPS;
544 }
ffca2b11 545 if (uap->fifosize > 1)
1da177e4
LT		 546 lcr_h |= UART01x_LCRH_FEN;
547
548 spin_lock_irqsave(&port->lock, flags);
549
550 /*
551 * Update the per-port timeout.
552 */
553 uart_update_timeout(port, termios->c_cflag, baud);
554
b63d4f0f 555 port->read_status_mask = UART011_DR_OE | 255;
1da177e4 556 if (termios->c_iflag & INPCK)
b63d4f0f 557 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1da177e4 558 if (termios->c_iflag & (BRKINT | PARMRK))
b63d4f0f 559 port->read_status_mask |= UART011_DR_BE;
1da177e4
LT		 560
561 /*
562 * Characters to ignore
563 */
564 port->ignore_status_mask = 0;
565 if (termios->c_iflag & IGNPAR)
b63d4f0f 566 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1da177e4 567 if (termios->c_iflag & IGNBRK) {
b63d4f0f 568 port->ignore_status_mask |= UART011_DR_BE;
1da177e4
LT		 569 /*
570 * If we're ignoring parity and break indicators,
571 * ignore overruns too (for real raw support).
572 */
573 if (termios->c_iflag & IGNPAR)
b63d4f0f 574 port->ignore_status_mask |= UART011_DR_OE;
1da177e4
LT		 575 }
576
577 /*
578 * Ignore all characters if CREAD is not set.
579 */
580 if ((termios->c_cflag & CREAD) == 0)
b63d4f0f 581 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1da177e4
LT		 582
583 if (UART_ENABLE_MS(port, termios->c_cflag))
584 pl011_enable_ms(port);
585
586 /* first, disable everything */
587 old_cr = readw(port->membase + UART011_CR);
588 writew(0, port->membase + UART011_CR);
589
3b43816f
RV		 590 if (termios->c_cflag & CRTSCTS) {
591 if (old_cr & UART011_CR_RTS)
592 old_cr |= UART011_CR_RTSEN;
593
594 old_cr |= UART011_CR_CTSEN;
595 uap->autorts = true;
596 } else {
597 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
598 uap->autorts = false;
599 }
600
c19f12b5
RK		 601 if (uap->vendor->oversampling) {
602 if (baud > port->uartclk / 16)
ac3e3fb4
LW		 603 old_cr |= ST_UART011_CR_OVSFACT;
604 else
605 old_cr &= ~ST_UART011_CR_OVSFACT;
606 }
607
1da177e4
LT		 608 /* Set baud rate */
609 writew(quot & 0x3f, port->membase + UART011_FBRD);
610 writew(quot >> 6, port->membase + UART011_IBRD);
611
612 /*
613 * ----------v----------v----------v----------v-----
614 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
615 * ----------^----------^----------^----------^-----
616 */
ec489aa8
LW		 617 writew(lcr_h, port->membase + uap->lcrh_rx);
618 if (uap->lcrh_rx != uap->lcrh_tx) {
619 int i;
620 /*
621 * Wait 10 PCLKs before writing LCRH_TX register,
622 * to get this delay write read only register 10 times
623 */
624 for (i = 0; i < 10; ++i)
625 writew(0xff, uap->port.membase + UART011_MIS);
626 writew(lcr_h, port->membase + uap->lcrh_tx);
627 }
1da177e4
LT		 628 writew(old_cr, port->membase + UART011_CR);
629
630 spin_unlock_irqrestore(&port->lock, flags);
631}
632
633static const char *pl011_type(struct uart_port *port)
634{
e8a7ba86
RK		 635 struct uart_amba_port *uap = (struct uart_amba_port *)port;
636 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 637}
638
639/*
640 * Release the memory region(s) being used by 'port'
641 */
642static void pl010_release_port(struct uart_port *port)
643{
644 release_mem_region(port->mapbase, SZ_4K);
645}
646
647/*
648 * Request the memory region(s) being used by 'port'
649 */
650static int pl010_request_port(struct uart_port *port)
651{
652 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
653 != NULL ? 0 : -EBUSY;
654}
655
656/*
657 * Configure/autoconfigure the port.
658 */
659static void pl010_config_port(struct uart_port *port, int flags)
660{
661 if (flags & UART_CONFIG_TYPE) {
662 port->type = PORT_AMBA;
663 pl010_request_port(port);
664 }
665}
666
667/*
668 * verify the new serial_struct (for TIOCSSERIAL).
669 */
670static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
671{
672 int ret = 0;
673 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
674 ret = -EINVAL;
a62c4133 675 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 676 ret = -EINVAL;
677 if (ser->baud_base < 9600)
678 ret = -EINVAL;
679 return ret;
680}
681
682static struct uart_ops amba_pl011_pops = {
683 .tx_empty = pl01x_tx_empty,
684 .set_mctrl = pl011_set_mctrl,
685 .get_mctrl = pl01x_get_mctrl,
686 .stop_tx = pl011_stop_tx,
687 .start_tx = pl011_start_tx,
688 .stop_rx = pl011_stop_rx,
689 .enable_ms = pl011_enable_ms,
690 .break_ctl = pl011_break_ctl,
691 .startup = pl011_startup,
692 .shutdown = pl011_shutdown,
693 .set_termios = pl011_set_termios,
694 .type = pl011_type,
695 .release_port = pl010_release_port,
696 .request_port = pl010_request_port,
697 .config_port = pl010_config_port,
698 .verify_port = pl010_verify_port,
84b5ae15
JW		 699#ifdef CONFIG_CONSOLE_POLL
700 .poll_get_char = pl010_get_poll_char,
701 .poll_put_char = pl010_put_poll_char,
702#endif
1da177e4
LT		 703};
704
705static struct uart_amba_port *amba_ports[UART_NR];
706
707#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
708
d358788f 709static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 710{
d358788f 711 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4 712
d358788f
RK		 713 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
714 barrier();
1da177e4
LT		 715 writew(ch, uap->port.membase + UART01x_DR);
716}
717
718static void
719pl011_console_write(struct console *co, const char *s, unsigned int count)
720{
721 struct uart_amba_port *uap = amba_ports[co->index];
722 unsigned int status, old_cr, new_cr;
1da177e4
LT		 723
724 clk_enable(uap->clk);
725
726 /*
727 * First save the CR then disable the interrupts
728 */
729 old_cr = readw(uap->port.membase + UART011_CR);
730 new_cr = old_cr & ~UART011_CR_CTSEN;
731 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
732 writew(new_cr, uap->port.membase + UART011_CR);
733
d358788f 734 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 735
736 /*
737 * Finally, wait for transmitter to become empty
738 * and restore the TCR
739 */
740 do {
741 status = readw(uap->port.membase + UART01x_FR);
742 } while (status & UART01x_FR_BUSY);
743 writew(old_cr, uap->port.membase + UART011_CR);
744
745 clk_disable(uap->clk);
746}
747
748static void __init
749pl011_console_get_options(struct uart_amba_port *uap, int *baud,
750 int *parity, int *bits)
751{
752 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
753 unsigned int lcr_h, ibrd, fbrd;
754
ec489aa8 755 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1da177e4
LT		 756
757 *parity = 'n';
758 if (lcr_h & UART01x_LCRH_PEN) {
759 if (lcr_h & UART01x_LCRH_EPS)
760 *parity = 'e';
761 else
762 *parity = 'o';
763 }
764
765 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
766 *bits = 7;
767 else
768 *bits = 8;
769
770 ibrd = readw(uap->port.membase + UART011_IBRD);
771 fbrd = readw(uap->port.membase + UART011_FBRD);
772
773 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4 774
c19f12b5 775 if (uap->vendor->oversampling) {
ac3e3fb4
LW		 776 if (readw(uap->port.membase + UART011_CR)
777 & ST_UART011_CR_OVSFACT)
778 *baud *= 2;
779 }
1da177e4
LT		 780 }
781}
782
783static int __init pl011_console_setup(struct console *co, char *options)
784{
785 struct uart_amba_port *uap;
786 int baud = 38400;
787 int bits = 8;
788 int parity = 'n';
789 int flow = 'n';
790
791 /*
792 * Check whether an invalid uart number has been specified, and
793 * if so, search for the first available port that does have
794 * console support.
795 */
796 if (co->index >= UART_NR)
797 co->index = 0;
798 uap = amba_ports[co->index];
d28122a5
RK		 799 if (!uap)
800 return -ENODEV;
1da177e4
LT		 801
802 uap->port.uartclk = clk_get_rate(uap->clk);
803
804 if (options)
805 uart_parse_options(options, &baud, &parity, &bits, &flow);
806 else
807 pl011_console_get_options(uap, &baud, &parity, &bits);
808
809 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
810}
811
2d93486c 812static struct uart_driver amba_reg;
1da177e4
LT		 813static struct console amba_console = {
814 .name = "ttyAMA",
815 .write = pl011_console_write,
816 .device = uart_console_device,
817 .setup = pl011_console_setup,
818 .flags = CON_PRINTBUFFER,
819 .index = -1,
820 .data = &amba_reg,
821};
822
823#define AMBA_CONSOLE (&amba_console)
824#else
825#define AMBA_CONSOLE NULL
826#endif
827
828static struct uart_driver amba_reg = {
829 .owner = THIS_MODULE,
830 .driver_name = "ttyAMA",
831 .dev_name = "ttyAMA",
832 .major = SERIAL_AMBA_MAJOR,
833 .minor = SERIAL_AMBA_MINOR,
834 .nr = UART_NR,
835 .cons = AMBA_CONSOLE,
836};
837
03fbdb15 838static int pl011_probe(struct amba_device *dev, struct amba_id *id)
1da177e4
LT		 839{
840 struct uart_amba_port *uap;
5926a295 841 struct vendor_data *vendor = id->data;
1da177e4
LT		 842 void __iomem *base;
843 int i, ret;
844
845 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
846 if (amba_ports[i] == NULL)
847 break;
848
849 if (i == ARRAY_SIZE(amba_ports)) {
850 ret = -EBUSY;
851 goto out;
852 }
853
dd00cc48 854 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1da177e4
LT		 855 if (uap == NULL) {
856 ret = -ENOMEM;
857 goto out;
858 }
859
dc890c2d 860 base = ioremap(dev->res.start, resource_size(&dev->res));
1da177e4
LT		 861 if (!base) {
862 ret = -ENOMEM;
863 goto free;
864 }
865
ee569c43 866 uap->clk = clk_get(&dev->dev, NULL);
1da177e4
LT		 867 if (IS_ERR(uap->clk)) {
868 ret = PTR_ERR(uap->clk);
869 goto unmap;
870 }
871
c19f12b5 872 uap->vendor = vendor;
ec489aa8
LW		 873 uap->lcrh_rx = vendor->lcrh_rx;
874 uap->lcrh_tx = vendor->lcrh_tx;
ffca2b11 875 uap->fifosize = vendor->fifosize;
1da177e4
LT		 876 uap->port.dev = &dev->dev;
877 uap->port.mapbase = dev->res.start;
878 uap->port.membase = base;
879 uap->port.iotype = UPIO_MEM;
880 uap->port.irq = dev->irq[0];
ffca2b11 881 uap->port.fifosize = uap->fifosize;
1da177e4
LT		 882 uap->port.ops = &amba_pl011_pops;
883 uap->port.flags = UPF_BOOT_AUTOCONF;
884 uap->port.line = i;
885
e8a7ba86
RK		 886 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
887
1da177e4
LT		 888 amba_ports[i] = uap;
889
890 amba_set_drvdata(dev, uap);
891 ret = uart_add_one_port(&amba_reg, &uap->port);
892 if (ret) {
893 amba_set_drvdata(dev, NULL);
894 amba_ports[i] = NULL;
1da177e4
LT		 895 clk_put(uap->clk);
896 unmap:
897 iounmap(base);
898 free:
899 kfree(uap);
900 }
901 out:
902 return ret;
903}
904
905static int pl011_remove(struct amba_device *dev)
906{
907 struct uart_amba_port *uap = amba_get_drvdata(dev);
908 int i;
909
910 amba_set_drvdata(dev, NULL);
911
912 uart_remove_one_port(&amba_reg, &uap->port);
913
914 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
915 if (amba_ports[i] == uap)
916 amba_ports[i] = NULL;
917
918 iounmap(uap->port.membase);
1da177e4
LT		 919 clk_put(uap->clk);
920 kfree(uap);
921 return 0;
922}
923
b736b89f
LC		 924#ifdef CONFIG_PM
925static int pl011_suspend(struct amba_device *dev, pm_message_t state)
926{
927 struct uart_amba_port *uap = amba_get_drvdata(dev);
928
929 if (!uap)
930 return -EINVAL;
931
932 return uart_suspend_port(&amba_reg, &uap->port);
933}
934
935static int pl011_resume(struct amba_device *dev)
936{
937 struct uart_amba_port *uap = amba_get_drvdata(dev);
938
939 if (!uap)
940 return -EINVAL;
941
942 return uart_resume_port(&amba_reg, &uap->port);
943}
944#endif
945
2c39c9e1 946static struct amba_id pl011_ids[] = {
1da177e4
LT		 947 {
948 .id = 0x00041011,
949 .mask = 0x000fffff,
5926a295
AR		 950 .data = &vendor_arm,
951 },
952 {
953 .id = 0x00380802,
954 .mask = 0x00ffffff,
955 .data = &vendor_st,
1da177e4
LT		 956 },
957 { 0, 0 },
958};
959
960static struct amba_driver pl011_driver = {
961 .drv = {
962 .name = "uart-pl011",
963 },
964 .id_table = pl011_ids,
965 .probe = pl011_probe,
966 .remove = pl011_remove,
b736b89f
LC		 967#ifdef CONFIG_PM
968 .suspend = pl011_suspend,
969 .resume = pl011_resume,
970#endif
1da177e4
LT		 971};
972
973static int __init pl011_init(void)
974{
975 int ret;
976 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
977
978 ret = uart_register_driver(&amba_reg);
979 if (ret == 0) {
980 ret = amba_driver_register(&pl011_driver);
981 if (ret)
982 uart_unregister_driver(&amba_reg);
983 }
984 return ret;
985}
986
987static void __exit pl011_exit(void)
988{
989 amba_driver_unregister(&pl011_driver);
990 uart_unregister_driver(&amba_reg);
991}
992
4dd9e742
AR		 993/*
994 * While this can be a module, if builtin it's most likely the console
995 * So let's leave module_exit but move module_init to an earlier place
996 */
997arch_initcall(pl011_init);
1da177e4
LT		 998module_exit(pl011_exit);
999
1000MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
1001MODULE_DESCRIPTION("ARM AMBA serial port driver");
1002MODULE_LICENSE("GPL");
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