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Commit | Line | Data |
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1e6c9c28 | 1 | /* |
c2f5ccfb | 2 | * linux/drivers/char/atmel_serial.c |
1e6c9c28 | 3 | * |
7192f92c | 4 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
5 | * Copyright (C) 2003 Rick Bronson |
6 | * | |
7 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
8 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
93a3ddc2 | 36 | #include <linux/atmel_pdc.h> |
1e6c9c28 AV |
37 | |
38 | #include <asm/io.h> | |
39 | ||
afefc415 | 40 | #include <asm/mach/serial_at91.h> |
1e6c9c28 | 41 | #include <asm/arch/board.h> |
93a3ddc2 | 42 | |
acca9b83 | 43 | #ifdef CONFIG_ARM |
c2f5ccfb | 44 | #include <asm/arch/cpu.h> |
20e65276 | 45 | #include <asm/arch/gpio.h> |
acca9b83 | 46 | #endif |
1e6c9c28 | 47 | |
5b34821a HS |
48 | #include "atmel_serial.h" |
49 | ||
749c4e60 | 50 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
51 | #define SUPPORT_SYSRQ |
52 | #endif | |
53 | ||
54 | #include <linux/serial_core.h> | |
55 | ||
749c4e60 | 56 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
57 | |
58 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
59 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
60 | * UART. */ | |
7192f92c | 61 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 62 | #define MINOR_START 154 |
7192f92c | 63 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
64 | |
65 | #else | |
66 | ||
67 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
68 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 69 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 70 | #define MINOR_START 64 |
7192f92c | 71 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
72 | |
73 | #endif | |
74 | ||
7192f92c | 75 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 76 | |
544fc728 HS |
77 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
78 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
79 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
80 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
81 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
82 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
83 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
84 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
85 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
86 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
87 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
88 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
89 | ||
90 | // #define UART_GET_CR(port) __raw_readl((port)->membase + ATMEL_US_CR) // is write-only | |
1e6c9c28 AV |
91 | |
92 | /* PDC registers */ | |
544fc728 HS |
93 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
94 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
95 | ||
96 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
97 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
98 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
99 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
100 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
101 | ||
102 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
103 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
104 | //#define UART_PUT_TNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNPR) | |
105 | //#define UART_PUT_TNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNCR) | |
1e6c9c28 | 106 | |
71f2e2b8 HS |
107 | static int (*atmel_open_hook)(struct uart_port *); |
108 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 109 | |
afefc415 AV |
110 | /* |
111 | * We wrap our port structure around the generic uart_port. | |
112 | */ | |
7192f92c | 113 | struct atmel_uart_port { |
afefc415 AV |
114 | struct uart_port uart; /* uart */ |
115 | struct clk *clk; /* uart clock */ | |
116 | unsigned short suspended; /* is port suspended? */ | |
9e6077bd | 117 | int break_active; /* break being received */ |
afefc415 AV |
118 | }; |
119 | ||
7192f92c | 120 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
afefc415 | 121 | |
1e6c9c28 | 122 | #ifdef SUPPORT_SYSRQ |
7192f92c | 123 | static struct console atmel_console; |
1e6c9c28 AV |
124 | #endif |
125 | ||
126 | /* | |
127 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
128 | */ | |
7192f92c | 129 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 130 | { |
7192f92c | 131 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
132 | } |
133 | ||
134 | /* | |
135 | * Set state of the modem control output lines | |
136 | */ | |
7192f92c | 137 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
138 | { |
139 | unsigned int control = 0; | |
afefc415 | 140 | unsigned int mode; |
1e6c9c28 | 141 | |
c2f5ccfb | 142 | #ifdef CONFIG_ARCH_AT91RM9200 |
79da7a61 | 143 | if (cpu_is_at91rm9200()) { |
afefc415 AV |
144 | /* |
145 | * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21. | |
146 | * We need to drive the pin manually. | |
147 | */ | |
72729910 | 148 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 149 | if (mctrl & TIOCM_RTS) |
20e65276 | 150 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 151 | else |
20e65276 | 152 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 153 | } |
1e6c9c28 | 154 | } |
acca9b83 | 155 | #endif |
1e6c9c28 AV |
156 | |
157 | if (mctrl & TIOCM_RTS) | |
7192f92c | 158 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 159 | else |
7192f92c | 160 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
161 | |
162 | if (mctrl & TIOCM_DTR) | |
7192f92c | 163 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 164 | else |
7192f92c | 165 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 166 | |
afefc415 AV |
167 | UART_PUT_CR(port, control); |
168 | ||
169 | /* Local loopback mode? */ | |
7192f92c | 170 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 171 | if (mctrl & TIOCM_LOOP) |
7192f92c | 172 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 173 | else |
7192f92c | 174 | mode |= ATMEL_US_CHMODE_NORMAL; |
afefc415 | 175 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
176 | } |
177 | ||
178 | /* | |
179 | * Get state of the modem control input lines | |
180 | */ | |
7192f92c | 181 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
182 | { |
183 | unsigned int status, ret = 0; | |
184 | ||
185 | status = UART_GET_CSR(port); | |
186 | ||
187 | /* | |
188 | * The control signals are active low. | |
189 | */ | |
7192f92c | 190 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 191 | ret |= TIOCM_CD; |
7192f92c | 192 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 193 | ret |= TIOCM_CTS; |
7192f92c | 194 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 195 | ret |= TIOCM_DSR; |
7192f92c | 196 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
197 | ret |= TIOCM_RI; |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
202 | /* | |
203 | * Stop transmitting. | |
204 | */ | |
7192f92c | 205 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 206 | { |
7192f92c | 207 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 208 | |
7192f92c | 209 | UART_PUT_IDR(port, ATMEL_US_TXRDY); |
1e6c9c28 AV |
210 | } |
211 | ||
212 | /* | |
213 | * Start transmitting. | |
214 | */ | |
7192f92c | 215 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 216 | { |
7192f92c | 217 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 218 | |
7192f92c | 219 | UART_PUT_IER(port, ATMEL_US_TXRDY); |
1e6c9c28 AV |
220 | } |
221 | ||
222 | /* | |
223 | * Stop receiving - port is in process of being closed. | |
224 | */ | |
7192f92c | 225 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 226 | { |
7192f92c | 227 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 228 | |
7192f92c | 229 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
1e6c9c28 AV |
230 | } |
231 | ||
232 | /* | |
233 | * Enable modem status interrupts | |
234 | */ | |
7192f92c | 235 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 236 | { |
7192f92c | 237 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC); |
1e6c9c28 AV |
238 | } |
239 | ||
240 | /* | |
241 | * Control the transmission of a break signal | |
242 | */ | |
7192f92c | 243 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
244 | { |
245 | if (break_state != 0) | |
7192f92c | 246 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 247 | else |
7192f92c | 248 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
249 | } |
250 | ||
251 | /* | |
252 | * Characters received (called from interrupt handler) | |
253 | */ | |
7d12e780 | 254 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 255 | { |
9e6077bd | 256 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 AV |
257 | struct tty_struct *tty = port->info->tty; |
258 | unsigned int status, ch, flg; | |
259 | ||
afefc415 | 260 | status = UART_GET_CSR(port); |
7192f92c | 261 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
262 | ch = UART_GET_CHAR(port); |
263 | ||
1e6c9c28 AV |
264 | port->icount.rx++; |
265 | ||
266 | flg = TTY_NORMAL; | |
267 | ||
268 | /* | |
269 | * note that the error handling code is | |
270 | * out of the main execution path | |
271 | */ | |
9e6077bd HS |
272 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
273 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
274 | || atmel_port->break_active)) { | |
7192f92c | 275 | UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */ |
9e6077bd HS |
276 | if (status & ATMEL_US_RXBRK |
277 | && !atmel_port->break_active) { | |
7192f92c | 278 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */ |
afefc415 | 279 | port->icount.brk++; |
9e6077bd HS |
280 | atmel_port->break_active = 1; |
281 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
afefc415 AV |
282 | if (uart_handle_break(port)) |
283 | goto ignore_char; | |
9e6077bd HS |
284 | } else { |
285 | /* | |
286 | * This is either the end-of-break | |
287 | * condition or we've received at | |
288 | * least one character without RXBRK | |
289 | * being set. In both cases, the next | |
290 | * RXBRK will indicate start-of-break. | |
291 | */ | |
292 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
293 | status &= ~ATMEL_US_RXBRK; | |
294 | atmel_port->break_active = 0; | |
afefc415 | 295 | } |
7192f92c | 296 | if (status & ATMEL_US_PARE) |
1e6c9c28 | 297 | port->icount.parity++; |
7192f92c | 298 | if (status & ATMEL_US_FRAME) |
1e6c9c28 | 299 | port->icount.frame++; |
7192f92c | 300 | if (status & ATMEL_US_OVRE) |
1e6c9c28 AV |
301 | port->icount.overrun++; |
302 | ||
afefc415 AV |
303 | status &= port->read_status_mask; |
304 | ||
7192f92c | 305 | if (status & ATMEL_US_RXBRK) |
afefc415 | 306 | flg = TTY_BREAK; |
7192f92c | 307 | else if (status & ATMEL_US_PARE) |
1e6c9c28 | 308 | flg = TTY_PARITY; |
7192f92c | 309 | else if (status & ATMEL_US_FRAME) |
1e6c9c28 | 310 | flg = TTY_FRAME; |
1e6c9c28 AV |
311 | } |
312 | ||
7d12e780 | 313 | if (uart_handle_sysrq_char(port, ch)) |
1e6c9c28 AV |
314 | goto ignore_char; |
315 | ||
7192f92c | 316 | uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg); |
1e6c9c28 AV |
317 | |
318 | ignore_char: | |
afefc415 | 319 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
320 | } |
321 | ||
322 | tty_flip_buffer_push(tty); | |
323 | } | |
324 | ||
325 | /* | |
326 | * Transmit characters (called from interrupt handler) | |
327 | */ | |
7192f92c | 328 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 AV |
329 | { |
330 | struct circ_buf *xmit = &port->info->xmit; | |
331 | ||
332 | if (port->x_char) { | |
333 | UART_PUT_CHAR(port, port->x_char); | |
334 | port->icount.tx++; | |
335 | port->x_char = 0; | |
336 | return; | |
337 | } | |
338 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
7192f92c | 339 | atmel_stop_tx(port); |
1e6c9c28 AV |
340 | return; |
341 | } | |
342 | ||
7192f92c | 343 | while (UART_GET_CSR(port) & ATMEL_US_TXRDY) { |
1e6c9c28 AV |
344 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
345 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
346 | port->icount.tx++; | |
347 | if (uart_circ_empty(xmit)) | |
348 | break; | |
349 | } | |
350 | ||
351 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
352 | uart_write_wakeup(port); | |
353 | ||
354 | if (uart_circ_empty(xmit)) | |
7192f92c | 355 | atmel_stop_tx(port); |
1e6c9c28 AV |
356 | } |
357 | ||
358 | /* | |
359 | * Interrupt handler | |
360 | */ | |
7d12e780 | 361 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
362 | { |
363 | struct uart_port *port = dev_id; | |
7192f92c | 364 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 AV |
365 | unsigned int status, pending, pass_counter = 0; |
366 | ||
367 | status = UART_GET_CSR(port); | |
afefc415 AV |
368 | pending = status & UART_GET_IMR(port); |
369 | while (pending) { | |
370 | /* Interrupt receive */ | |
7192f92c | 371 | if (pending & ATMEL_US_RXRDY) |
7d12e780 | 372 | atmel_rx_chars(port); |
9e6077bd HS |
373 | else if (pending & ATMEL_US_RXBRK) { |
374 | /* | |
375 | * End of break detected. If it came along | |
376 | * with a character, atmel_rx_chars will | |
377 | * handle it. | |
378 | */ | |
379 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
380 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
381 | atmel_port->break_active = 0; | |
382 | } | |
afefc415 AV |
383 | |
384 | // TODO: All reads to CSR will clear these interrupts! | |
7192f92c HS |
385 | if (pending & ATMEL_US_RIIC) port->icount.rng++; |
386 | if (pending & ATMEL_US_DSRIC) port->icount.dsr++; | |
387 | if (pending & ATMEL_US_DCDIC) | |
388 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
389 | if (pending & ATMEL_US_CTSIC) | |
390 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
391 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC)) | |
afefc415 AV |
392 | wake_up_interruptible(&port->info->delta_msr_wait); |
393 | ||
394 | /* Interrupt transmit */ | |
7192f92c HS |
395 | if (pending & ATMEL_US_TXRDY) |
396 | atmel_tx_chars(port); | |
afefc415 | 397 | |
7192f92c | 398 | if (pass_counter++ > ATMEL_ISR_PASS_LIMIT) |
afefc415 | 399 | break; |
1e6c9c28 | 400 | |
afefc415 AV |
401 | status = UART_GET_CSR(port); |
402 | pending = status & UART_GET_IMR(port); | |
1e6c9c28 AV |
403 | } |
404 | return IRQ_HANDLED; | |
405 | } | |
406 | ||
407 | /* | |
408 | * Perform initialization and enable port for reception | |
409 | */ | |
7192f92c | 410 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 411 | { |
7192f92c | 412 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 AV |
413 | int retval; |
414 | ||
415 | /* | |
416 | * Ensure that no interrupts are enabled otherwise when | |
417 | * request_irq() is called we could get stuck trying to | |
418 | * handle an unexpected interrupt | |
419 | */ | |
420 | UART_PUT_IDR(port, -1); | |
421 | ||
422 | /* | |
423 | * Allocate the IRQ | |
424 | */ | |
7192f92c | 425 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, "atmel_serial", port); |
1e6c9c28 | 426 | if (retval) { |
7192f92c | 427 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
428 | return retval; |
429 | } | |
430 | ||
431 | /* | |
432 | * If there is a specific "open" function (to register | |
433 | * control line interrupts) | |
434 | */ | |
71f2e2b8 HS |
435 | if (atmel_open_hook) { |
436 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
437 | if (retval) { |
438 | free_irq(port->irq, port); | |
439 | return retval; | |
440 | } | |
441 | } | |
442 | ||
1e6c9c28 AV |
443 | /* |
444 | * Finally, enable the serial port | |
445 | */ | |
7192f92c HS |
446 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
447 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */ | |
afefc415 | 448 | |
7192f92c | 449 | UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */ |
afefc415 | 450 | |
1e6c9c28 AV |
451 | return 0; |
452 | } | |
453 | ||
454 | /* | |
455 | * Disable the port | |
456 | */ | |
7192f92c | 457 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 458 | { |
7192f92c | 459 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 460 | |
1e6c9c28 AV |
461 | /* |
462 | * Disable all interrupts, port and break condition. | |
463 | */ | |
7192f92c | 464 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
465 | UART_PUT_IDR(port, -1); |
466 | ||
467 | /* | |
468 | * Free the interrupt | |
469 | */ | |
470 | free_irq(port->irq, port); | |
471 | ||
472 | /* | |
473 | * If there is a specific "close" function (to unregister | |
474 | * control line interrupts) | |
475 | */ | |
71f2e2b8 HS |
476 | if (atmel_close_hook) |
477 | atmel_close_hook(port); | |
1e6c9c28 AV |
478 | } |
479 | ||
480 | /* | |
481 | * Power / Clock management. | |
482 | */ | |
7192f92c | 483 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) |
1e6c9c28 | 484 | { |
7192f92c | 485 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 486 | |
1e6c9c28 AV |
487 | switch (state) { |
488 | case 0: | |
489 | /* | |
490 | * Enable the peripheral clock for this serial port. | |
491 | * This is called on uart_open() or a resume event. | |
492 | */ | |
7192f92c | 493 | clk_enable(atmel_port->clk); |
1e6c9c28 AV |
494 | break; |
495 | case 3: | |
496 | /* | |
497 | * Disable the peripheral clock for this serial port. | |
498 | * This is called on uart_close() or a suspend event. | |
499 | */ | |
7192f92c | 500 | clk_disable(atmel_port->clk); |
1e6c9c28 AV |
501 | break; |
502 | default: | |
7192f92c | 503 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); |
1e6c9c28 AV |
504 | } |
505 | } | |
506 | ||
507 | /* | |
508 | * Change the port parameters | |
509 | */ | |
606d099c | 510 | static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old) |
1e6c9c28 AV |
511 | { |
512 | unsigned long flags; | |
513 | unsigned int mode, imr, quot, baud; | |
514 | ||
03abeac0 AV |
515 | /* Get current mode register */ |
516 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR); | |
517 | ||
1e6c9c28 AV |
518 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); |
519 | quot = uart_get_divisor(port, baud); | |
520 | ||
03abeac0 AV |
521 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
522 | quot /= 8; | |
523 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
524 | } | |
1e6c9c28 AV |
525 | |
526 | /* byte size */ | |
527 | switch (termios->c_cflag & CSIZE) { | |
528 | case CS5: | |
7192f92c | 529 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
530 | break; |
531 | case CS6: | |
7192f92c | 532 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
533 | break; |
534 | case CS7: | |
7192f92c | 535 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
536 | break; |
537 | default: | |
7192f92c | 538 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
539 | break; |
540 | } | |
541 | ||
542 | /* stop bits */ | |
543 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 544 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
545 | |
546 | /* parity */ | |
547 | if (termios->c_cflag & PARENB) { | |
548 | if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */ | |
549 | if (termios->c_cflag & PARODD) | |
7192f92c | 550 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 551 | else |
7192f92c | 552 | mode |= ATMEL_US_PAR_SPACE; |
1e6c9c28 AV |
553 | } |
554 | else if (termios->c_cflag & PARODD) | |
7192f92c | 555 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 556 | else |
7192f92c | 557 | mode |= ATMEL_US_PAR_EVEN; |
1e6c9c28 AV |
558 | } |
559 | else | |
7192f92c | 560 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
561 | |
562 | spin_lock_irqsave(&port->lock, flags); | |
563 | ||
7192f92c | 564 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 565 | if (termios->c_iflag & INPCK) |
7192f92c | 566 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 567 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 568 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
569 | |
570 | /* | |
571 | * Characters to ignore | |
572 | */ | |
573 | port->ignore_status_mask = 0; | |
574 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 575 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 576 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 577 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
578 | /* |
579 | * If we're ignoring parity and break indicators, | |
580 | * ignore overruns too (for real raw support). | |
581 | */ | |
582 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 583 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 AV |
584 | } |
585 | ||
586 | // TODO: Ignore all characters if CREAD is set. | |
587 | ||
588 | /* update the per-port timeout */ | |
589 | uart_update_timeout(port, termios->c_cflag, baud); | |
590 | ||
591 | /* disable interrupts and drain transmitter */ | |
592 | imr = UART_GET_IMR(port); /* get interrupt mask */ | |
593 | UART_PUT_IDR(port, -1); /* disable all interrupts */ | |
7192f92c | 594 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) { barrier(); } |
1e6c9c28 AV |
595 | |
596 | /* disable receiver and transmitter */ | |
7192f92c | 597 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 AV |
598 | |
599 | /* set the parity, stop bits and data size */ | |
600 | UART_PUT_MR(port, mode); | |
601 | ||
602 | /* set the baud rate */ | |
603 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
604 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
605 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
606 | |
607 | /* restore interrupts */ | |
608 | UART_PUT_IER(port, imr); | |
609 | ||
610 | /* CTS flow-control and modem-status interrupts */ | |
611 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
612 | port->ops->enable_ms(port); | |
613 | ||
614 | spin_unlock_irqrestore(&port->lock, flags); | |
615 | } | |
616 | ||
617 | /* | |
618 | * Return string describing the specified port | |
619 | */ | |
7192f92c | 620 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 621 | { |
9ab4f88b | 622 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
623 | } |
624 | ||
625 | /* | |
626 | * Release the memory region(s) being used by 'port'. | |
627 | */ | |
7192f92c | 628 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 629 | { |
afefc415 AV |
630 | struct platform_device *pdev = to_platform_device(port->dev); |
631 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
632 | ||
633 | release_mem_region(port->mapbase, size); | |
634 | ||
635 | if (port->flags & UPF_IOREMAP) { | |
636 | iounmap(port->membase); | |
637 | port->membase = NULL; | |
638 | } | |
1e6c9c28 AV |
639 | } |
640 | ||
641 | /* | |
642 | * Request the memory region(s) being used by 'port'. | |
643 | */ | |
7192f92c | 644 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 645 | { |
afefc415 AV |
646 | struct platform_device *pdev = to_platform_device(port->dev); |
647 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
648 | ||
7192f92c | 649 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
650 | return -EBUSY; |
651 | ||
652 | if (port->flags & UPF_IOREMAP) { | |
653 | port->membase = ioremap(port->mapbase, size); | |
654 | if (port->membase == NULL) { | |
655 | release_mem_region(port->mapbase, size); | |
656 | return -ENOMEM; | |
657 | } | |
658 | } | |
1e6c9c28 | 659 | |
afefc415 | 660 | return 0; |
1e6c9c28 AV |
661 | } |
662 | ||
663 | /* | |
664 | * Configure/autoconfigure the port. | |
665 | */ | |
7192f92c | 666 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
667 | { |
668 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 669 | port->type = PORT_ATMEL; |
7192f92c | 670 | atmel_request_port(port); |
1e6c9c28 AV |
671 | } |
672 | } | |
673 | ||
674 | /* | |
675 | * Verify the new serial_struct (for TIOCSSERIAL). | |
676 | */ | |
7192f92c | 677 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
678 | { |
679 | int ret = 0; | |
9ab4f88b | 680 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
681 | ret = -EINVAL; |
682 | if (port->irq != ser->irq) | |
683 | ret = -EINVAL; | |
684 | if (ser->io_type != SERIAL_IO_MEM) | |
685 | ret = -EINVAL; | |
686 | if (port->uartclk / 16 != ser->baud_base) | |
687 | ret = -EINVAL; | |
688 | if ((void *)port->mapbase != ser->iomem_base) | |
689 | ret = -EINVAL; | |
690 | if (port->iobase != ser->port) | |
691 | ret = -EINVAL; | |
692 | if (ser->hub6 != 0) | |
693 | ret = -EINVAL; | |
694 | return ret; | |
695 | } | |
696 | ||
7192f92c HS |
697 | static struct uart_ops atmel_pops = { |
698 | .tx_empty = atmel_tx_empty, | |
699 | .set_mctrl = atmel_set_mctrl, | |
700 | .get_mctrl = atmel_get_mctrl, | |
701 | .stop_tx = atmel_stop_tx, | |
702 | .start_tx = atmel_start_tx, | |
703 | .stop_rx = atmel_stop_rx, | |
704 | .enable_ms = atmel_enable_ms, | |
705 | .break_ctl = atmel_break_ctl, | |
706 | .startup = atmel_startup, | |
707 | .shutdown = atmel_shutdown, | |
708 | .set_termios = atmel_set_termios, | |
709 | .type = atmel_type, | |
710 | .release_port = atmel_release_port, | |
711 | .request_port = atmel_request_port, | |
712 | .config_port = atmel_config_port, | |
713 | .verify_port = atmel_verify_port, | |
714 | .pm = atmel_serial_pm, | |
1e6c9c28 AV |
715 | }; |
716 | ||
afefc415 AV |
717 | /* |
718 | * Configure the port from the platform device resource info. | |
719 | */ | |
7192f92c | 720 | static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct platform_device *pdev) |
1e6c9c28 | 721 | { |
7192f92c | 722 | struct uart_port *port = &atmel_port->uart; |
73e2798b | 723 | struct atmel_uart_data *data = pdev->dev.platform_data; |
afefc415 AV |
724 | |
725 | port->iotype = UPIO_MEM; | |
a14d5273 | 726 | port->flags = UPF_BOOT_AUTOCONF; |
7192f92c | 727 | port->ops = &atmel_pops; |
a14d5273 | 728 | port->fifosize = 1; |
afefc415 AV |
729 | port->line = pdev->id; |
730 | port->dev = &pdev->dev; | |
731 | ||
732 | port->mapbase = pdev->resource[0].start; | |
733 | port->irq = pdev->resource[1].start; | |
734 | ||
75d35213 HS |
735 | if (data->regs) |
736 | /* Already mapped by setup code */ | |
737 | port->membase = data->regs; | |
afefc415 AV |
738 | else { |
739 | port->flags |= UPF_IOREMAP; | |
740 | port->membase = NULL; | |
741 | } | |
1e6c9c28 | 742 | |
7192f92c HS |
743 | if (!atmel_port->clk) { /* for console, the clock could already be configured */ |
744 | atmel_port->clk = clk_get(&pdev->dev, "usart"); | |
745 | clk_enable(atmel_port->clk); | |
746 | port->uartclk = clk_get_rate(atmel_port->clk); | |
afefc415 | 747 | } |
1e6c9c28 AV |
748 | } |
749 | ||
afefc415 AV |
750 | /* |
751 | * Register board-specific modem-control line handlers. | |
752 | */ | |
71f2e2b8 | 753 | void __init atmel_register_uart_fns(struct atmel_port_fns *fns) |
1e6c9c28 AV |
754 | { |
755 | if (fns->enable_ms) | |
7192f92c | 756 | atmel_pops.enable_ms = fns->enable_ms; |
1e6c9c28 | 757 | if (fns->get_mctrl) |
7192f92c | 758 | atmel_pops.get_mctrl = fns->get_mctrl; |
1e6c9c28 | 759 | if (fns->set_mctrl) |
7192f92c | 760 | atmel_pops.set_mctrl = fns->set_mctrl; |
71f2e2b8 HS |
761 | atmel_open_hook = fns->open; |
762 | atmel_close_hook = fns->close; | |
7192f92c HS |
763 | atmel_pops.pm = fns->pm; |
764 | atmel_pops.set_wake = fns->set_wake; | |
1e6c9c28 AV |
765 | } |
766 | ||
1e6c9c28 | 767 | |
749c4e60 | 768 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 769 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 770 | { |
7192f92c | 771 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
d358788f RK |
772 | barrier(); |
773 | UART_PUT_CHAR(port, ch); | |
774 | } | |
1e6c9c28 AV |
775 | |
776 | /* | |
777 | * Interrupts are disabled on entering | |
778 | */ | |
7192f92c | 779 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 780 | { |
7192f92c | 781 | struct uart_port *port = &atmel_ports[co->index].uart; |
d358788f | 782 | unsigned int status, imr; |
1e6c9c28 AV |
783 | |
784 | /* | |
785 | * First, save IMR and then disable interrupts | |
786 | */ | |
787 | imr = UART_GET_IMR(port); /* get interrupt mask */ | |
7192f92c | 788 | UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY); |
1e6c9c28 | 789 | |
7192f92c | 790 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
791 | |
792 | /* | |
793 | * Finally, wait for transmitter to become empty | |
794 | * and restore IMR | |
795 | */ | |
796 | do { | |
797 | status = UART_GET_CSR(port); | |
7192f92c | 798 | } while (!(status & ATMEL_US_TXRDY)); |
1e6c9c28 AV |
799 | UART_PUT_IER(port, imr); /* set interrupts back the way they were */ |
800 | } | |
801 | ||
802 | /* | |
803 | * If the port was already initialised (eg, by a boot loader), try to determine | |
804 | * the current setup. | |
805 | */ | |
7192f92c | 806 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits) |
1e6c9c28 AV |
807 | { |
808 | unsigned int mr, quot; | |
809 | ||
810 | // TODO: CR is a write-only register | |
811 | // unsigned int cr; | |
812 | // | |
7192f92c HS |
813 | // cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN); |
814 | // if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) { | |
1e6c9c28 AV |
815 | // /* ok, the port was enabled */ |
816 | // } | |
817 | ||
7192f92c HS |
818 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
819 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
820 | *bits = 8; |
821 | else | |
822 | *bits = 7; | |
823 | ||
7192f92c HS |
824 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
825 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 826 | *parity = 'e'; |
7192f92c | 827 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
828 | *parity = 'o'; |
829 | ||
4d5e392c HS |
830 | /* |
831 | * The serial core only rounds down when matching this to a | |
832 | * supported baud rate. Make sure we don't end up slightly | |
833 | * lower than one of those, as it would make us fall through | |
834 | * to a much lower baud rate than we really want. | |
835 | */ | |
1e6c9c28 | 836 | quot = UART_GET_BRGR(port); |
4d5e392c | 837 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
838 | } |
839 | ||
7192f92c | 840 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 841 | { |
7192f92c | 842 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
843 | int baud = 115200; |
844 | int bits = 8; | |
845 | int parity = 'n'; | |
846 | int flow = 'n'; | |
847 | ||
afefc415 AV |
848 | if (port->membase == 0) /* Port not initialized yet - delay setup */ |
849 | return -ENODEV; | |
1e6c9c28 | 850 | |
1e6c9c28 | 851 | UART_PUT_IDR(port, -1); /* disable interrupts */ |
7192f92c HS |
852 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
853 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
854 | |
855 | if (options) | |
856 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
857 | else | |
7192f92c | 858 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
859 | |
860 | return uart_set_options(port, co, baud, parity, bits, flow); | |
861 | } | |
862 | ||
7192f92c | 863 | static struct uart_driver atmel_uart; |
1e6c9c28 | 864 | |
7192f92c HS |
865 | static struct console atmel_console = { |
866 | .name = ATMEL_DEVICENAME, | |
867 | .write = atmel_console_write, | |
1e6c9c28 | 868 | .device = uart_console_device, |
7192f92c | 869 | .setup = atmel_console_setup, |
1e6c9c28 AV |
870 | .flags = CON_PRINTBUFFER, |
871 | .index = -1, | |
7192f92c | 872 | .data = &atmel_uart, |
1e6c9c28 AV |
873 | }; |
874 | ||
7192f92c | 875 | #define ATMEL_CONSOLE_DEVICE &atmel_console |
1e6c9c28 | 876 | |
afefc415 AV |
877 | /* |
878 | * Early console initialization (before VM subsystem initialized). | |
879 | */ | |
7192f92c | 880 | static int __init atmel_console_init(void) |
1e6c9c28 | 881 | { |
73e2798b | 882 | if (atmel_default_console_device) { |
7192f92c HS |
883 | add_preferred_console(ATMEL_DEVICENAME, atmel_default_console_device->id, NULL); |
884 | atmel_init_port(&(atmel_ports[atmel_default_console_device->id]), atmel_default_console_device); | |
885 | register_console(&atmel_console); | |
afefc415 | 886 | } |
1e6c9c28 | 887 | |
1e6c9c28 AV |
888 | return 0; |
889 | } | |
7192f92c | 890 | console_initcall(atmel_console_init); |
1e6c9c28 | 891 | |
afefc415 AV |
892 | /* |
893 | * Late console initialization. | |
894 | */ | |
7192f92c | 895 | static int __init atmel_late_console_init(void) |
afefc415 | 896 | { |
7192f92c HS |
897 | if (atmel_default_console_device && !(atmel_console.flags & CON_ENABLED)) |
898 | register_console(&atmel_console); | |
afefc415 AV |
899 | |
900 | return 0; | |
901 | } | |
7192f92c | 902 | core_initcall(atmel_late_console_init); |
afefc415 | 903 | |
1e6c9c28 | 904 | #else |
7192f92c | 905 | #define ATMEL_CONSOLE_DEVICE NULL |
1e6c9c28 AV |
906 | #endif |
907 | ||
7192f92c | 908 | static struct uart_driver atmel_uart = { |
1e6c9c28 | 909 | .owner = THIS_MODULE, |
7192f92c HS |
910 | .driver_name = "atmel_serial", |
911 | .dev_name = ATMEL_DEVICENAME, | |
912 | .major = SERIAL_ATMEL_MAJOR, | |
1e6c9c28 | 913 | .minor = MINOR_START, |
73e2798b | 914 | .nr = ATMEL_MAX_UART, |
7192f92c | 915 | .cons = ATMEL_CONSOLE_DEVICE, |
1e6c9c28 AV |
916 | }; |
917 | ||
afefc415 | 918 | #ifdef CONFIG_PM |
7192f92c | 919 | static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state) |
1e6c9c28 | 920 | { |
afefc415 | 921 | struct uart_port *port = platform_get_drvdata(pdev); |
7192f92c | 922 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 AV |
923 | |
924 | if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock()) | |
925 | enable_irq_wake(port->irq); | |
926 | else { | |
7192f92c HS |
927 | uart_suspend_port(&atmel_uart, port); |
928 | atmel_port->suspended = 1; | |
afefc415 | 929 | } |
1e6c9c28 | 930 | |
afefc415 AV |
931 | return 0; |
932 | } | |
1e6c9c28 | 933 | |
7192f92c | 934 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
935 | { |
936 | struct uart_port *port = platform_get_drvdata(pdev); | |
7192f92c | 937 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 | 938 | |
7192f92c HS |
939 | if (atmel_port->suspended) { |
940 | uart_resume_port(&atmel_uart, port); | |
941 | atmel_port->suspended = 0; | |
1e6c9c28 | 942 | } |
9b938166 AV |
943 | else |
944 | disable_irq_wake(port->irq); | |
1e6c9c28 AV |
945 | |
946 | return 0; | |
947 | } | |
afefc415 | 948 | #else |
7192f92c HS |
949 | #define atmel_serial_suspend NULL |
950 | #define atmel_serial_resume NULL | |
afefc415 | 951 | #endif |
1e6c9c28 | 952 | |
7192f92c | 953 | static int __devinit atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 954 | { |
7192f92c | 955 | struct atmel_uart_port *port; |
afefc415 | 956 | int ret; |
1e6c9c28 | 957 | |
7192f92c HS |
958 | port = &atmel_ports[pdev->id]; |
959 | atmel_init_port(port, pdev); | |
1e6c9c28 | 960 | |
7192f92c | 961 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
afefc415 AV |
962 | if (!ret) { |
963 | device_init_wakeup(&pdev->dev, 1); | |
964 | platform_set_drvdata(pdev, port); | |
965 | } | |
966 | ||
967 | return ret; | |
968 | } | |
969 | ||
7192f92c | 970 | static int __devexit atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
971 | { |
972 | struct uart_port *port = platform_get_drvdata(pdev); | |
7192f92c | 973 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 AV |
974 | int ret = 0; |
975 | ||
7192f92c HS |
976 | clk_disable(atmel_port->clk); |
977 | clk_put(atmel_port->clk); | |
afefc415 AV |
978 | |
979 | device_init_wakeup(&pdev->dev, 0); | |
980 | platform_set_drvdata(pdev, NULL); | |
981 | ||
982 | if (port) { | |
7192f92c | 983 | ret = uart_remove_one_port(&atmel_uart, port); |
afefc415 AV |
984 | kfree(port); |
985 | } | |
986 | ||
987 | return ret; | |
988 | } | |
989 | ||
7192f92c HS |
990 | static struct platform_driver atmel_serial_driver = { |
991 | .probe = atmel_serial_probe, | |
992 | .remove = __devexit_p(atmel_serial_remove), | |
993 | .suspend = atmel_serial_suspend, | |
994 | .resume = atmel_serial_resume, | |
afefc415 | 995 | .driver = { |
1e8ea802 | 996 | .name = "atmel_usart", |
afefc415 AV |
997 | .owner = THIS_MODULE, |
998 | }, | |
999 | }; | |
1000 | ||
7192f92c | 1001 | static int __init atmel_serial_init(void) |
afefc415 AV |
1002 | { |
1003 | int ret; | |
1004 | ||
7192f92c | 1005 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
1006 | if (ret) |
1007 | return ret; | |
1008 | ||
7192f92c | 1009 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 1010 | if (ret) |
7192f92c | 1011 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
1012 | |
1013 | return ret; | |
1014 | } | |
1015 | ||
7192f92c | 1016 | static void __exit atmel_serial_exit(void) |
afefc415 | 1017 | { |
7192f92c HS |
1018 | platform_driver_unregister(&atmel_serial_driver); |
1019 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
1020 | } |
1021 | ||
7192f92c HS |
1022 | module_init(atmel_serial_init); |
1023 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
1024 | |
1025 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 1026 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 1027 | MODULE_LICENSE("GPL"); |