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atmel_serial: fix broken RX buffer allocation
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1e6c9c28 1/*
c2f5ccfb 2 * linux/drivers/char/atmel_serial.c
1e6c9c28 3 *
7192f92c 4 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV
5 * Copyright (C) 2003 Rick Bronson
6 *
7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 *
a6670615
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10 * DMA support added by Chip Coldwell.
11 *
1e6c9c28
AV
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
1e6c9c28
AV
27#include <linux/module.h>
28#include <linux/tty.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/init.h>
32#include <linux/serial.h>
afefc415 33#include <linux/clk.h>
1e6c9c28
AV
34#include <linux/console.h>
35#include <linux/sysrq.h>
36#include <linux/tty_flip.h>
afefc415 37#include <linux/platform_device.h>
a6670615 38#include <linux/dma-mapping.h>
93a3ddc2 39#include <linux/atmel_pdc.h>
fa3218d8 40#include <linux/atmel_serial.h>
1e6c9c28
AV
41
42#include <asm/io.h>
43
afefc415 44#include <asm/mach/serial_at91.h>
1e6c9c28 45#include <asm/arch/board.h>
93a3ddc2 46
acca9b83 47#ifdef CONFIG_ARM
c2f5ccfb 48#include <asm/arch/cpu.h>
20e65276 49#include <asm/arch/gpio.h>
acca9b83 50#endif
1e6c9c28 51
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52#define PDC_BUFFER_SIZE 512
53/* Revisit: We should calculate this based on the actual port settings */
54#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
55
749c4e60 56#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV
57#define SUPPORT_SYSRQ
58#endif
59
60#include <linux/serial_core.h>
61
749c4e60 62#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV
63
64/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
65 * should coexist with the 8250 driver, such as if we have an external 16C550
66 * UART. */
7192f92c 67#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 68#define MINOR_START 154
7192f92c 69#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV
70
71#else
72
73/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
74 * name, but it is legally reserved for the 8250 driver. */
7192f92c 75#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 76#define MINOR_START 64
7192f92c 77#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV
78
79#endif
80
7192f92c 81#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 82
b843aa21 83/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS
84#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
85#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
86#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
87#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
88#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
89#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
90#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
91#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
92#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
93#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
94#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
95#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
96
1e6c9c28 97 /* PDC registers */
544fc728
HS
98#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
99#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
100
101#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
102#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
103#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
104#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
105#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
106
107#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
108#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
1e6c9c28 109
71f2e2b8
HS
110static int (*atmel_open_hook)(struct uart_port *);
111static void (*atmel_close_hook)(struct uart_port *);
1e6c9c28 112
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113struct atmel_dma_buffer {
114 unsigned char *buf;
115 dma_addr_t dma_addr;
116 unsigned int dma_size;
117 unsigned int ofs;
118};
119
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120struct atmel_uart_char {
121 u16 status;
122 u16 ch;
123};
124
125#define ATMEL_SERIAL_RINGSIZE 1024
126
afefc415
AV
127/*
128 * We wrap our port structure around the generic uart_port.
129 */
7192f92c 130struct atmel_uart_port {
afefc415
AV
131 struct uart_port uart; /* uart */
132 struct clk *clk; /* uart clock */
133 unsigned short suspended; /* is port suspended? */
9e6077bd 134 int break_active; /* break being received */
1ecc26bd 135
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136 short use_dma_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
139
140 short use_dma_tx; /* enable PDC transmitter */
141 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
142
1ecc26bd
RB
143 struct tasklet_struct tasklet;
144 unsigned int irq_status;
145 unsigned int irq_status_prev;
146
147 struct circ_buf rx_ring;
afefc415
AV
148};
149
7192f92c 150static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
afefc415 151
1e6c9c28 152#ifdef SUPPORT_SYSRQ
7192f92c 153static struct console atmel_console;
1e6c9c28
AV
154#endif
155
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156#ifdef CONFIG_SERIAL_ATMEL_PDC
157static bool atmel_use_dma_rx(struct uart_port *port)
158{
159 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
160
161 return atmel_port->use_dma_rx;
162}
163
164static bool atmel_use_dma_tx(struct uart_port *port)
165{
166 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
167
168 return atmel_port->use_dma_tx;
169}
170#else
171static bool atmel_use_dma_rx(struct uart_port *port)
172{
173 return false;
174}
175
176static bool atmel_use_dma_tx(struct uart_port *port)
177{
178 return false;
179}
180#endif
181
1e6c9c28
AV
182/*
183 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
184 */
7192f92c 185static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 186{
7192f92c 187 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV
188}
189
190/*
191 * Set state of the modem control output lines
192 */
7192f92c 193static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV
194{
195 unsigned int control = 0;
afefc415 196 unsigned int mode;
1e6c9c28 197
c2f5ccfb 198#ifdef CONFIG_ARCH_AT91RM9200
79da7a61 199 if (cpu_is_at91rm9200()) {
afefc415 200 /*
b843aa21
RB
201 * AT91RM9200 Errata #39: RTS0 is not internally connected
202 * to PA21. We need to drive the pin manually.
afefc415 203 */
72729910 204 if (port->mapbase == AT91RM9200_BASE_US0) {
afefc415 205 if (mctrl & TIOCM_RTS)
20e65276 206 at91_set_gpio_value(AT91_PIN_PA21, 0);
afefc415 207 else
20e65276 208 at91_set_gpio_value(AT91_PIN_PA21, 1);
afefc415 209 }
1e6c9c28 210 }
acca9b83 211#endif
1e6c9c28
AV
212
213 if (mctrl & TIOCM_RTS)
7192f92c 214 control |= ATMEL_US_RTSEN;
1e6c9c28 215 else
7192f92c 216 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV
217
218 if (mctrl & TIOCM_DTR)
7192f92c 219 control |= ATMEL_US_DTREN;
1e6c9c28 220 else
7192f92c 221 control |= ATMEL_US_DTRDIS;
1e6c9c28 222
afefc415
AV
223 UART_PUT_CR(port, control);
224
225 /* Local loopback mode? */
7192f92c 226 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 227 if (mctrl & TIOCM_LOOP)
7192f92c 228 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 229 else
7192f92c 230 mode |= ATMEL_US_CHMODE_NORMAL;
afefc415 231 UART_PUT_MR(port, mode);
1e6c9c28
AV
232}
233
234/*
235 * Get state of the modem control input lines
236 */
7192f92c 237static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28
AV
238{
239 unsigned int status, ret = 0;
240
241 status = UART_GET_CSR(port);
242
243 /*
244 * The control signals are active low.
245 */
7192f92c 246 if (!(status & ATMEL_US_DCD))
1e6c9c28 247 ret |= TIOCM_CD;
7192f92c 248 if (!(status & ATMEL_US_CTS))
1e6c9c28 249 ret |= TIOCM_CTS;
7192f92c 250 if (!(status & ATMEL_US_DSR))
1e6c9c28 251 ret |= TIOCM_DSR;
7192f92c 252 if (!(status & ATMEL_US_RI))
1e6c9c28
AV
253 ret |= TIOCM_RI;
254
255 return ret;
256}
257
258/*
259 * Stop transmitting.
260 */
7192f92c 261static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 262{
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263 if (atmel_use_dma_tx(port)) {
264 /* disable PDC transmit */
265 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
266 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
267 } else
268 UART_PUT_IDR(port, ATMEL_US_TXRDY);
1e6c9c28
AV
269}
270
271/*
272 * Start transmitting.
273 */
7192f92c 274static void atmel_start_tx(struct uart_port *port)
1e6c9c28 275{
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276 if (atmel_use_dma_tx(port)) {
277 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
278 /* The transmitter is already running. Yes, we
279 really need this.*/
280 return;
281
282 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
283 /* re-enable PDC transmit */
284 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
285 } else
286 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
287}
288
289/*
290 * Stop receiving - port is in process of being closed.
291 */
7192f92c 292static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 293{
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294 if (atmel_use_dma_rx(port)) {
295 /* disable PDC receive */
296 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
297 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
298 } else
299 UART_PUT_IDR(port, ATMEL_US_RXRDY);
1e6c9c28
AV
300}
301
302/*
303 * Enable modem status interrupts
304 */
7192f92c 305static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 306{
b843aa21
RB
307 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
308 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
1e6c9c28
AV
309}
310
311/*
312 * Control the transmission of a break signal
313 */
7192f92c 314static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV
315{
316 if (break_state != 0)
7192f92c 317 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 318 else
7192f92c 319 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV
320}
321
1ecc26bd
RB
322/*
323 * Stores the incoming character in the ring buffer
324 */
325static void
326atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
327 unsigned int ch)
328{
329 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
330 struct circ_buf *ring = &atmel_port->rx_ring;
331 struct atmel_uart_char *c;
332
333 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
334 /* Buffer overflow, ignore char */
335 return;
336
337 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
338 c->status = status;
339 c->ch = ch;
340
341 /* Make sure the character is stored before we update head. */
342 smp_wmb();
343
344 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
345}
346
a6670615
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347/*
348 * Deal with parity, framing and overrun errors.
349 */
350static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
351{
352 /* clear error */
353 UART_PUT_CR(port, ATMEL_US_RSTSTA);
354
355 if (status & ATMEL_US_RXBRK) {
356 /* ignore side-effect */
357 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
358 port->icount.brk++;
359 }
360 if (status & ATMEL_US_PARE)
361 port->icount.parity++;
362 if (status & ATMEL_US_FRAME)
363 port->icount.frame++;
364 if (status & ATMEL_US_OVRE)
365 port->icount.overrun++;
366}
367
1e6c9c28
AV
368/*
369 * Characters received (called from interrupt handler)
370 */
7d12e780 371static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 372{
b843aa21 373 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
1ecc26bd 374 unsigned int status, ch;
1e6c9c28 375
afefc415 376 status = UART_GET_CSR(port);
7192f92c 377 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV
378 ch = UART_GET_CHAR(port);
379
1e6c9c28
AV
380 /*
381 * note that the error handling code is
382 * out of the main execution path
383 */
9e6077bd
HS
384 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
385 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
386 || atmel_port->break_active)) {
1ecc26bd 387
b843aa21
RB
388 /* clear error */
389 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 390
9e6077bd
HS
391 if (status & ATMEL_US_RXBRK
392 && !atmel_port->break_active) {
9e6077bd
HS
393 atmel_port->break_active = 1;
394 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS
395 } else {
396 /*
397 * This is either the end-of-break
398 * condition or we've received at
399 * least one character without RXBRK
400 * being set. In both cases, the next
401 * RXBRK will indicate start-of-break.
402 */
403 UART_PUT_IDR(port, ATMEL_US_RXBRK);
404 status &= ~ATMEL_US_RXBRK;
405 atmel_port->break_active = 0;
afefc415 406 }
1e6c9c28
AV
407 }
408
1ecc26bd 409 atmel_buffer_rx_char(port, status, ch);
afefc415 410 status = UART_GET_CSR(port);
1e6c9c28
AV
411 }
412
1ecc26bd 413 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV
414}
415
416/*
1ecc26bd
RB
417 * Transmit characters (called from tasklet with TXRDY interrupt
418 * disabled)
1e6c9c28 419 */
7192f92c 420static void atmel_tx_chars(struct uart_port *port)
1e6c9c28
AV
421{
422 struct circ_buf *xmit = &port->info->xmit;
423
1ecc26bd 424 if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
425 UART_PUT_CHAR(port, port->x_char);
426 port->icount.tx++;
427 port->x_char = 0;
1e6c9c28 428 }
1ecc26bd 429 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 430 return;
1e6c9c28 431
7192f92c 432 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
433 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
435 port->icount.tx++;
436 if (uart_circ_empty(xmit))
437 break;
438 }
439
440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
441 uart_write_wakeup(port);
442
1ecc26bd
RB
443 if (!uart_circ_empty(xmit))
444 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
445}
446
b843aa21
RB
447/*
448 * receive interrupt handler.
449 */
450static void
451atmel_handle_receive(struct uart_port *port, unsigned int pending)
452{
453 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
454
a6670615
CC
455 if (atmel_use_dma_rx(port)) {
456 /*
457 * PDC receive. Just schedule the tasklet and let it
458 * figure out the details.
459 *
460 * TODO: We're not handling error flags correctly at
461 * the moment.
462 */
463 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
464 UART_PUT_IDR(port, (ATMEL_US_ENDRX
465 | ATMEL_US_TIMEOUT));
466 tasklet_schedule(&atmel_port->tasklet);
467 }
468
469 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
470 ATMEL_US_FRAME | ATMEL_US_PARE))
471 atmel_pdc_rxerr(port, pending);
472 }
473
b843aa21
RB
474 /* Interrupt receive */
475 if (pending & ATMEL_US_RXRDY)
476 atmel_rx_chars(port);
477 else if (pending & ATMEL_US_RXBRK) {
478 /*
479 * End of break detected. If it came along with a
480 * character, atmel_rx_chars will handle it.
481 */
482 UART_PUT_CR(port, ATMEL_US_RSTSTA);
483 UART_PUT_IDR(port, ATMEL_US_RXBRK);
484 atmel_port->break_active = 0;
485 }
486}
487
488/*
1ecc26bd 489 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB
490 */
491static void
492atmel_handle_transmit(struct uart_port *port, unsigned int pending)
493{
1ecc26bd
RB
494 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
495
a6670615
CC
496 if (atmel_use_dma_tx(port)) {
497 /* PDC transmit */
498 if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) {
499 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
500 tasklet_schedule(&atmel_port->tasklet);
501 }
502 } else {
503 /* Interrupt transmit */
504 if (pending & ATMEL_US_TXRDY) {
505 UART_PUT_IDR(port, ATMEL_US_TXRDY);
506 tasklet_schedule(&atmel_port->tasklet);
507 }
1ecc26bd 508 }
b843aa21
RB
509}
510
511/*
512 * status flags interrupt handler.
513 */
514static void
515atmel_handle_status(struct uart_port *port, unsigned int pending,
516 unsigned int status)
517{
1ecc26bd
RB
518 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
519
b843aa21 520 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB
521 | ATMEL_US_CTSIC)) {
522 atmel_port->irq_status = status;
523 tasklet_schedule(&atmel_port->tasklet);
524 }
b843aa21
RB
525}
526
1e6c9c28
AV
527/*
528 * Interrupt handler
529 */
7d12e780 530static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV
531{
532 struct uart_port *port = dev_id;
533 unsigned int status, pending, pass_counter = 0;
534
a6670615
CC
535 do {
536 status = UART_GET_CSR(port);
537 pending = status & UART_GET_IMR(port);
538 if (!pending)
539 break;
540
b843aa21
RB
541 atmel_handle_receive(port, pending);
542 atmel_handle_status(port, pending, status);
543 atmel_handle_transmit(port, pending);
a6670615 544 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 545
a6670615
CC
546 return IRQ_HANDLED;
547}
1e6c9c28 548
a6670615
CC
549/*
550 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
551 */
552static void atmel_tx_dma(struct uart_port *port)
553{
554 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
555 struct circ_buf *xmit = &port->info->xmit;
556 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
557 int count;
558
559 xmit->tail += pdc->ofs;
560 xmit->tail &= UART_XMIT_SIZE - 1;
561
562 port->icount.tx += pdc->ofs;
563 pdc->ofs = 0;
564
565 if (!uart_circ_empty(xmit)) {
566 /* more to transmit - setup next transfer */
567
568 /* disable PDC transmit */
569 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
570 dma_sync_single_for_device(port->dev,
571 pdc->dma_addr,
572 pdc->dma_size,
573 DMA_TO_DEVICE);
574
575 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
576 pdc->ofs = count;
577
578 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
579 UART_PUT_TCR(port, count);
580 /* re-enable PDC transmit and interrupts */
581 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
582 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
583 } else {
584 /* nothing left to transmit - disable the transmitter */
585
586 /* disable PDC transmit */
587 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1e6c9c28 588 }
a6670615
CC
589
590 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
591 uart_write_wakeup(port);
1e6c9c28
AV
592}
593
1ecc26bd
RB
594static void atmel_rx_from_ring(struct uart_port *port)
595{
596 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
597 struct circ_buf *ring = &atmel_port->rx_ring;
598 unsigned int flg;
599 unsigned int status;
600
601 while (ring->head != ring->tail) {
602 struct atmel_uart_char c;
603
604 /* Make sure c is loaded after head. */
605 smp_rmb();
606
607 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
608
609 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
610
611 port->icount.rx++;
612 status = c.status;
613 flg = TTY_NORMAL;
614
615 /*
616 * note that the error handling code is
617 * out of the main execution path
618 */
619 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
620 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
621 if (status & ATMEL_US_RXBRK) {
622 /* ignore side-effect */
623 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
624
625 port->icount.brk++;
626 if (uart_handle_break(port))
627 continue;
628 }
629 if (status & ATMEL_US_PARE)
630 port->icount.parity++;
631 if (status & ATMEL_US_FRAME)
632 port->icount.frame++;
633 if (status & ATMEL_US_OVRE)
634 port->icount.overrun++;
635
636 status &= port->read_status_mask;
637
638 if (status & ATMEL_US_RXBRK)
639 flg = TTY_BREAK;
640 else if (status & ATMEL_US_PARE)
641 flg = TTY_PARITY;
642 else if (status & ATMEL_US_FRAME)
643 flg = TTY_FRAME;
644 }
645
646
647 if (uart_handle_sysrq_char(port, c.ch))
648 continue;
649
650 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
651 }
652
653 /*
654 * Drop the lock here since it might end up calling
655 * uart_start(), which takes the lock.
656 */
657 spin_unlock(&port->lock);
658 tty_flip_buffer_push(port->info->tty);
659 spin_lock(&port->lock);
660}
661
a6670615
CC
662static void atmel_rx_from_dma(struct uart_port *port)
663{
664 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
665 struct tty_struct *tty = port->info->tty;
666 struct atmel_dma_buffer *pdc;
667 int rx_idx = atmel_port->pdc_rx_idx;
668 unsigned int head;
669 unsigned int tail;
670 unsigned int count;
671
672 do {
673 /* Reset the UART timeout early so that we don't miss one */
674 UART_PUT_CR(port, ATMEL_US_STTTO);
675
676 pdc = &atmel_port->pdc_rx[rx_idx];
677 head = UART_GET_RPR(port) - pdc->dma_addr;
678 tail = pdc->ofs;
679
680 /* If the PDC has switched buffers, RPR won't contain
681 * any address within the current buffer. Since head
682 * is unsigned, we just need a one-way comparison to
683 * find out.
684 *
685 * In this case, we just need to consume the entire
686 * buffer and resubmit it for DMA. This will clear the
687 * ENDRX bit as well, so that we can safely re-enable
688 * all interrupts below.
689 */
690 head = min(head, pdc->dma_size);
691
692 if (likely(head != tail)) {
693 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
694 pdc->dma_size, DMA_FROM_DEVICE);
695
696 /*
697 * head will only wrap around when we recycle
698 * the DMA buffer, and when that happens, we
699 * explicitly set tail to 0. So head will
700 * always be greater than tail.
701 */
702 count = head - tail;
703
704 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
705
706 dma_sync_single_for_device(port->dev, pdc->dma_addr,
707 pdc->dma_size, DMA_FROM_DEVICE);
708
709 port->icount.rx += count;
710 pdc->ofs = head;
711 }
712
713 /*
714 * If the current buffer is full, we need to check if
715 * the next one contains any additional data.
716 */
717 if (head >= pdc->dma_size) {
718 pdc->ofs = 0;
719 UART_PUT_RNPR(port, pdc->dma_addr);
720 UART_PUT_RNCR(port, pdc->dma_size);
721
722 rx_idx = !rx_idx;
723 atmel_port->pdc_rx_idx = rx_idx;
724 }
725 } while (head >= pdc->dma_size);
726
727 /*
728 * Drop the lock here since it might end up calling
729 * uart_start(), which takes the lock.
730 */
731 spin_unlock(&port->lock);
732 tty_flip_buffer_push(tty);
733 spin_lock(&port->lock);
734
735 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
736}
737
1ecc26bd
RB
738/*
739 * tasklet handling tty stuff outside the interrupt handler.
740 */
741static void atmel_tasklet_func(unsigned long data)
742{
743 struct uart_port *port = (struct uart_port *)data;
744 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
745 unsigned int status;
746 unsigned int status_change;
747
748 /* The interrupt handler does not take the lock */
749 spin_lock(&port->lock);
750
a6670615
CC
751 if (atmel_use_dma_tx(port))
752 atmel_tx_dma(port);
753 else
754 atmel_tx_chars(port);
1ecc26bd
RB
755
756 status = atmel_port->irq_status;
757 status_change = status ^ atmel_port->irq_status_prev;
758
759 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
760 | ATMEL_US_DCD | ATMEL_US_CTS)) {
761 /* TODO: All reads to CSR will clear these interrupts! */
762 if (status_change & ATMEL_US_RI)
763 port->icount.rng++;
764 if (status_change & ATMEL_US_DSR)
765 port->icount.dsr++;
766 if (status_change & ATMEL_US_DCD)
767 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
768 if (status_change & ATMEL_US_CTS)
769 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
770
771 wake_up_interruptible(&port->info->delta_msr_wait);
772
773 atmel_port->irq_status_prev = status;
774 }
775
a6670615
CC
776 if (atmel_use_dma_rx(port))
777 atmel_rx_from_dma(port);
778 else
779 atmel_rx_from_ring(port);
1ecc26bd
RB
780
781 spin_unlock(&port->lock);
782}
783
1e6c9c28
AV
784/*
785 * Perform initialization and enable port for reception
786 */
7192f92c 787static int atmel_startup(struct uart_port *port)
1e6c9c28 788{
a6670615 789 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
1e6c9c28
AV
790 int retval;
791
792 /*
793 * Ensure that no interrupts are enabled otherwise when
794 * request_irq() is called we could get stuck trying to
795 * handle an unexpected interrupt
796 */
797 UART_PUT_IDR(port, -1);
798
799 /*
800 * Allocate the IRQ
801 */
b843aa21
RB
802 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
803 "atmel_serial", port);
1e6c9c28 804 if (retval) {
7192f92c 805 printk("atmel_serial: atmel_startup - Can't get irq\n");
1e6c9c28
AV
806 return retval;
807 }
808
a6670615
CC
809 /*
810 * Initialize DMA (if necessary)
811 */
812 if (atmel_use_dma_rx(port)) {
813 int i;
814
815 for (i = 0; i < 2; i++) {
816 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
817
818 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
819 if (pdc->buf == NULL) {
820 if (i != 0) {
821 dma_unmap_single(port->dev,
822 atmel_port->pdc_rx[0].dma_addr,
823 PDC_BUFFER_SIZE,
824 DMA_FROM_DEVICE);
825 kfree(atmel_port->pdc_rx[0].buf);
826 }
827 free_irq(port->irq, port);
828 return -ENOMEM;
829 }
830 pdc->dma_addr = dma_map_single(port->dev,
831 pdc->buf,
832 PDC_BUFFER_SIZE,
833 DMA_FROM_DEVICE);
834 pdc->dma_size = PDC_BUFFER_SIZE;
835 pdc->ofs = 0;
836 }
837
838 atmel_port->pdc_rx_idx = 0;
839
840 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
841 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
842
843 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
844 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
845 }
846 if (atmel_use_dma_tx(port)) {
847 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
848 struct circ_buf *xmit = &port->info->xmit;
849
850 pdc->buf = xmit->buf;
851 pdc->dma_addr = dma_map_single(port->dev,
852 pdc->buf,
853 UART_XMIT_SIZE,
854 DMA_TO_DEVICE);
855 pdc->dma_size = UART_XMIT_SIZE;
856 pdc->ofs = 0;
857 }
858
1e6c9c28
AV
859 /*
860 * If there is a specific "open" function (to register
861 * control line interrupts)
862 */
71f2e2b8
HS
863 if (atmel_open_hook) {
864 retval = atmel_open_hook(port);
1e6c9c28
AV
865 if (retval) {
866 free_irq(port->irq, port);
867 return retval;
868 }
869 }
870
1e6c9c28
AV
871 /*
872 * Finally, enable the serial port
873 */
7192f92c 874 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB
875 /* enable xmit & rcvr */
876 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 877
a6670615
CC
878 if (atmel_use_dma_rx(port)) {
879 /* set UART timeout */
880 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
881 UART_PUT_CR(port, ATMEL_US_STTTO);
882
883 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
884 /* enable PDC controller */
885 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
886 } else {
887 /* enable receive only */
888 UART_PUT_IER(port, ATMEL_US_RXRDY);
889 }
afefc415 890
1e6c9c28
AV
891 return 0;
892}
893
894/*
895 * Disable the port
896 */
7192f92c 897static void atmel_shutdown(struct uart_port *port)
1e6c9c28 898{
a6670615
CC
899 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
900 /*
901 * Ensure everything is stopped.
902 */
903 atmel_stop_rx(port);
904 atmel_stop_tx(port);
905
906 /*
907 * Shut-down the DMA.
908 */
909 if (atmel_use_dma_rx(port)) {
910 int i;
911
912 for (i = 0; i < 2; i++) {
913 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
914
915 dma_unmap_single(port->dev,
916 pdc->dma_addr,
917 pdc->dma_size,
918 DMA_FROM_DEVICE);
919 kfree(pdc->buf);
920 }
921 }
922 if (atmel_use_dma_tx(port)) {
923 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
924
925 dma_unmap_single(port->dev,
926 pdc->dma_addr,
927 pdc->dma_size,
928 DMA_TO_DEVICE);
929 }
930
1e6c9c28
AV
931 /*
932 * Disable all interrupts, port and break condition.
933 */
7192f92c 934 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1e6c9c28
AV
935 UART_PUT_IDR(port, -1);
936
937 /*
938 * Free the interrupt
939 */
940 free_irq(port->irq, port);
941
942 /*
943 * If there is a specific "close" function (to unregister
944 * control line interrupts)
945 */
71f2e2b8
HS
946 if (atmel_close_hook)
947 atmel_close_hook(port);
1e6c9c28
AV
948}
949
950/*
951 * Power / Clock management.
952 */
b843aa21
RB
953static void atmel_serial_pm(struct uart_port *port, unsigned int state,
954 unsigned int oldstate)
1e6c9c28 955{
b843aa21 956 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
afefc415 957
1e6c9c28 958 switch (state) {
b843aa21
RB
959 case 0:
960 /*
961 * Enable the peripheral clock for this serial port.
962 * This is called on uart_open() or a resume event.
963 */
964 clk_enable(atmel_port->clk);
965 break;
966 case 3:
967 /*
968 * Disable the peripheral clock for this serial port.
969 * This is called on uart_close() or a suspend event.
970 */
971 clk_disable(atmel_port->clk);
972 break;
973 default:
974 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV
975 }
976}
977
978/*
979 * Change the port parameters
980 */
b843aa21
RB
981static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
982 struct ktermios *old)
1e6c9c28
AV
983{
984 unsigned long flags;
985 unsigned int mode, imr, quot, baud;
986
03abeac0 987 /* Get current mode register */
b843aa21
RB
988 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
989 | ATMEL_US_NBSTOP | ATMEL_US_PAR);
03abeac0 990
b843aa21 991 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV
992 quot = uart_get_divisor(port, baud);
993
b843aa21 994 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV
995 quot /= 8;
996 mode |= ATMEL_US_USCLKS_MCK_DIV8;
997 }
1e6c9c28
AV
998
999 /* byte size */
1000 switch (termios->c_cflag & CSIZE) {
1001 case CS5:
7192f92c 1002 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV
1003 break;
1004 case CS6:
7192f92c 1005 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV
1006 break;
1007 case CS7:
7192f92c 1008 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV
1009 break;
1010 default:
7192f92c 1011 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV
1012 break;
1013 }
1014
1015 /* stop bits */
1016 if (termios->c_cflag & CSTOPB)
7192f92c 1017 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV
1018
1019 /* parity */
1020 if (termios->c_cflag & PARENB) {
b843aa21
RB
1021 /* Mark or Space parity */
1022 if (termios->c_cflag & CMSPAR) {
1e6c9c28 1023 if (termios->c_cflag & PARODD)
7192f92c 1024 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 1025 else
7192f92c 1026 mode |= ATMEL_US_PAR_SPACE;
b843aa21 1027 } else if (termios->c_cflag & PARODD)
7192f92c 1028 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 1029 else
7192f92c 1030 mode |= ATMEL_US_PAR_EVEN;
b843aa21 1031 } else
7192f92c 1032 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV
1033
1034 spin_lock_irqsave(&port->lock, flags);
1035
7192f92c 1036 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 1037 if (termios->c_iflag & INPCK)
7192f92c 1038 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1039 if (termios->c_iflag & (BRKINT | PARMRK))
7192f92c 1040 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 1041
a6670615
CC
1042 if (atmel_use_dma_rx(port))
1043 /* need to enable error interrupts */
1044 UART_PUT_IER(port, port->read_status_mask);
1045
1e6c9c28
AV
1046 /*
1047 * Characters to ignore
1048 */
1049 port->ignore_status_mask = 0;
1050 if (termios->c_iflag & IGNPAR)
7192f92c 1051 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 1052 if (termios->c_iflag & IGNBRK) {
7192f92c 1053 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
1054 /*
1055 * If we're ignoring parity and break indicators,
1056 * ignore overruns too (for real raw support).
1057 */
1058 if (termios->c_iflag & IGNPAR)
7192f92c 1059 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 1060 }
b843aa21 1061 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV
1062
1063 /* update the per-port timeout */
1064 uart_update_timeout(port, termios->c_cflag, baud);
1065
b843aa21
RB
1066 /* save/disable interrupts and drain transmitter */
1067 imr = UART_GET_IMR(port);
1068 UART_PUT_IDR(port, -1);
1069 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
829dd811 1070 cpu_relax();
1e6c9c28
AV
1071
1072 /* disable receiver and transmitter */
7192f92c 1073 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28
AV
1074
1075 /* set the parity, stop bits and data size */
1076 UART_PUT_MR(port, mode);
1077
1078 /* set the baud rate */
1079 UART_PUT_BRGR(port, quot);
7192f92c
HS
1080 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1081 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1082
1083 /* restore interrupts */
1084 UART_PUT_IER(port, imr);
1085
1086 /* CTS flow-control and modem-status interrupts */
1087 if (UART_ENABLE_MS(port, termios->c_cflag))
1088 port->ops->enable_ms(port);
1089
1090 spin_unlock_irqrestore(&port->lock, flags);
1091}
1092
1093/*
1094 * Return string describing the specified port
1095 */
7192f92c 1096static const char *atmel_type(struct uart_port *port)
1e6c9c28 1097{
9ab4f88b 1098 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV
1099}
1100
1101/*
1102 * Release the memory region(s) being used by 'port'.
1103 */
7192f92c 1104static void atmel_release_port(struct uart_port *port)
1e6c9c28 1105{
afefc415
AV
1106 struct platform_device *pdev = to_platform_device(port->dev);
1107 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1108
1109 release_mem_region(port->mapbase, size);
1110
1111 if (port->flags & UPF_IOREMAP) {
1112 iounmap(port->membase);
1113 port->membase = NULL;
1114 }
1e6c9c28
AV
1115}
1116
1117/*
1118 * Request the memory region(s) being used by 'port'.
1119 */
7192f92c 1120static int atmel_request_port(struct uart_port *port)
1e6c9c28 1121{
afefc415
AV
1122 struct platform_device *pdev = to_platform_device(port->dev);
1123 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1124
7192f92c 1125 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV
1126 return -EBUSY;
1127
1128 if (port->flags & UPF_IOREMAP) {
1129 port->membase = ioremap(port->mapbase, size);
1130 if (port->membase == NULL) {
1131 release_mem_region(port->mapbase, size);
1132 return -ENOMEM;
1133 }
1134 }
1e6c9c28 1135
afefc415 1136 return 0;
1e6c9c28
AV
1137}
1138
1139/*
1140 * Configure/autoconfigure the port.
1141 */
7192f92c 1142static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV
1143{
1144 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 1145 port->type = PORT_ATMEL;
7192f92c 1146 atmel_request_port(port);
1e6c9c28
AV
1147 }
1148}
1149
1150/*
1151 * Verify the new serial_struct (for TIOCSSERIAL).
1152 */
7192f92c 1153static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV
1154{
1155 int ret = 0;
9ab4f88b 1156 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV
1157 ret = -EINVAL;
1158 if (port->irq != ser->irq)
1159 ret = -EINVAL;
1160 if (ser->io_type != SERIAL_IO_MEM)
1161 ret = -EINVAL;
1162 if (port->uartclk / 16 != ser->baud_base)
1163 ret = -EINVAL;
1164 if ((void *)port->mapbase != ser->iomem_base)
1165 ret = -EINVAL;
1166 if (port->iobase != ser->port)
1167 ret = -EINVAL;
1168 if (ser->hub6 != 0)
1169 ret = -EINVAL;
1170 return ret;
1171}
1172
7192f92c
HS
1173static struct uart_ops atmel_pops = {
1174 .tx_empty = atmel_tx_empty,
1175 .set_mctrl = atmel_set_mctrl,
1176 .get_mctrl = atmel_get_mctrl,
1177 .stop_tx = atmel_stop_tx,
1178 .start_tx = atmel_start_tx,
1179 .stop_rx = atmel_stop_rx,
1180 .enable_ms = atmel_enable_ms,
1181 .break_ctl = atmel_break_ctl,
1182 .startup = atmel_startup,
1183 .shutdown = atmel_shutdown,
1184 .set_termios = atmel_set_termios,
1185 .type = atmel_type,
1186 .release_port = atmel_release_port,
1187 .request_port = atmel_request_port,
1188 .config_port = atmel_config_port,
1189 .verify_port = atmel_verify_port,
1190 .pm = atmel_serial_pm,
1e6c9c28
AV
1191};
1192
afefc415
AV
1193/*
1194 * Configure the port from the platform device resource info.
1195 */
b843aa21
RB
1196static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1197 struct platform_device *pdev)
1e6c9c28 1198{
7192f92c 1199 struct uart_port *port = &atmel_port->uart;
73e2798b 1200 struct atmel_uart_data *data = pdev->dev.platform_data;
afefc415
AV
1201
1202 port->iotype = UPIO_MEM;
a14d5273 1203 port->flags = UPF_BOOT_AUTOCONF;
7192f92c 1204 port->ops = &atmel_pops;
a14d5273 1205 port->fifosize = 1;
afefc415
AV
1206 port->line = pdev->id;
1207 port->dev = &pdev->dev;
1208
1209 port->mapbase = pdev->resource[0].start;
1210 port->irq = pdev->resource[1].start;
1211
1ecc26bd
RB
1212 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
1213 (unsigned long)port);
1214
1215 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
1216
75d35213
HS
1217 if (data->regs)
1218 /* Already mapped by setup code */
1219 port->membase = data->regs;
afefc415
AV
1220 else {
1221 port->flags |= UPF_IOREMAP;
1222 port->membase = NULL;
1223 }
1e6c9c28 1224
b843aa21
RB
1225 /* for console, the clock could already be configured */
1226 if (!atmel_port->clk) {
7192f92c
HS
1227 atmel_port->clk = clk_get(&pdev->dev, "usart");
1228 clk_enable(atmel_port->clk);
1229 port->uartclk = clk_get_rate(atmel_port->clk);
afefc415 1230 }
a6670615
CC
1231
1232 atmel_port->use_dma_rx = data->use_dma_rx;
1233 atmel_port->use_dma_tx = data->use_dma_tx;
1234 if (atmel_use_dma_tx(port))
1235 port->fifosize = PDC_BUFFER_SIZE;
1e6c9c28
AV
1236}
1237
afefc415
AV
1238/*
1239 * Register board-specific modem-control line handlers.
1240 */
71f2e2b8 1241void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1e6c9c28
AV
1242{
1243 if (fns->enable_ms)
7192f92c 1244 atmel_pops.enable_ms = fns->enable_ms;
1e6c9c28 1245 if (fns->get_mctrl)
7192f92c 1246 atmel_pops.get_mctrl = fns->get_mctrl;
1e6c9c28 1247 if (fns->set_mctrl)
7192f92c 1248 atmel_pops.set_mctrl = fns->set_mctrl;
71f2e2b8
HS
1249 atmel_open_hook = fns->open;
1250 atmel_close_hook = fns->close;
7192f92c
HS
1251 atmel_pops.pm = fns->pm;
1252 atmel_pops.set_wake = fns->set_wake;
1e6c9c28
AV
1253}
1254
749c4e60 1255#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 1256static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 1257{
7192f92c 1258 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 1259 cpu_relax();
d358788f
RK
1260 UART_PUT_CHAR(port, ch);
1261}
1e6c9c28
AV
1262
1263/*
1264 * Interrupts are disabled on entering
1265 */
7192f92c 1266static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 1267{
7192f92c 1268 struct uart_port *port = &atmel_ports[co->index].uart;
d358788f 1269 unsigned int status, imr;
1e6c9c28
AV
1270
1271 /*
b843aa21 1272 * First, save IMR and then disable interrupts
1e6c9c28 1273 */
b843aa21 1274 imr = UART_GET_IMR(port);
7192f92c 1275 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
1e6c9c28 1276
7192f92c 1277 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV
1278
1279 /*
b843aa21
RB
1280 * Finally, wait for transmitter to become empty
1281 * and restore IMR
1e6c9c28
AV
1282 */
1283 do {
1284 status = UART_GET_CSR(port);
7192f92c 1285 } while (!(status & ATMEL_US_TXRDY));
b843aa21
RB
1286 /* set interrupts back the way they were */
1287 UART_PUT_IER(port, imr);
1e6c9c28
AV
1288}
1289
1290/*
b843aa21
RB
1291 * If the port was already initialised (eg, by a boot loader),
1292 * try to determine the current setup.
1e6c9c28 1293 */
b843aa21
RB
1294static void __init atmel_console_get_options(struct uart_port *port, int *baud,
1295 int *parity, int *bits)
1e6c9c28
AV
1296{
1297 unsigned int mr, quot;
1298
1c0fd82f
HS
1299 /*
1300 * If the baud rate generator isn't running, the port wasn't
1301 * initialized by the boot loader.
1302 */
1303 quot = UART_GET_BRGR(port);
1304 if (!quot)
1305 return;
1e6c9c28 1306
7192f92c
HS
1307 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
1308 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV
1309 *bits = 8;
1310 else
1311 *bits = 7;
1312
7192f92c
HS
1313 mr = UART_GET_MR(port) & ATMEL_US_PAR;
1314 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 1315 *parity = 'e';
7192f92c 1316 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV
1317 *parity = 'o';
1318
4d5e392c
HS
1319 /*
1320 * The serial core only rounds down when matching this to a
1321 * supported baud rate. Make sure we don't end up slightly
1322 * lower than one of those, as it would make us fall through
1323 * to a much lower baud rate than we really want.
1324 */
4d5e392c 1325 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV
1326}
1327
7192f92c 1328static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 1329{
7192f92c 1330 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV
1331 int baud = 115200;
1332 int bits = 8;
1333 int parity = 'n';
1334 int flow = 'n';
1335
b843aa21
RB
1336 if (port->membase == NULL) {
1337 /* Port not initialized yet - delay setup */
afefc415 1338 return -ENODEV;
b843aa21 1339 }
1e6c9c28 1340
b843aa21 1341 UART_PUT_IDR(port, -1);
7192f92c
HS
1342 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1343 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
1344
1345 if (options)
1346 uart_parse_options(options, &baud, &parity, &bits, &flow);
1347 else
7192f92c 1348 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV
1349
1350 return uart_set_options(port, co, baud, parity, bits, flow);
1351}
1352
7192f92c 1353static struct uart_driver atmel_uart;
1e6c9c28 1354
7192f92c
HS
1355static struct console atmel_console = {
1356 .name = ATMEL_DEVICENAME,
1357 .write = atmel_console_write,
1e6c9c28 1358 .device = uart_console_device,
7192f92c 1359 .setup = atmel_console_setup,
1e6c9c28
AV
1360 .flags = CON_PRINTBUFFER,
1361 .index = -1,
7192f92c 1362 .data = &atmel_uart,
1e6c9c28
AV
1363};
1364
7192f92c 1365#define ATMEL_CONSOLE_DEVICE &atmel_console
1e6c9c28 1366
afefc415
AV
1367/*
1368 * Early console initialization (before VM subsystem initialized).
1369 */
7192f92c 1370static int __init atmel_console_init(void)
1e6c9c28 1371{
73e2798b 1372 if (atmel_default_console_device) {
b843aa21
RB
1373 add_preferred_console(ATMEL_DEVICENAME,
1374 atmel_default_console_device->id, NULL);
1375 atmel_init_port(&atmel_ports[atmel_default_console_device->id],
1376 atmel_default_console_device);
7192f92c 1377 register_console(&atmel_console);
afefc415 1378 }
1e6c9c28 1379
1e6c9c28
AV
1380 return 0;
1381}
b843aa21 1382
7192f92c 1383console_initcall(atmel_console_init);
1e6c9c28 1384
afefc415
AV
1385/*
1386 * Late console initialization.
1387 */
7192f92c 1388static int __init atmel_late_console_init(void)
afefc415 1389{
b843aa21
RB
1390 if (atmel_default_console_device
1391 && !(atmel_console.flags & CON_ENABLED))
7192f92c 1392 register_console(&atmel_console);
afefc415
AV
1393
1394 return 0;
1395}
b843aa21 1396
7192f92c 1397core_initcall(atmel_late_console_init);
afefc415 1398
dfa7f343
HS
1399static inline bool atmel_is_console_port(struct uart_port *port)
1400{
1401 return port->cons && port->cons->index == port->line;
1402}
1403
1e6c9c28 1404#else
7192f92c 1405#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS
1406
1407static inline bool atmel_is_console_port(struct uart_port *port)
1408{
1409 return false;
1410}
1e6c9c28
AV
1411#endif
1412
7192f92c 1413static struct uart_driver atmel_uart = {
b843aa21
RB
1414 .owner = THIS_MODULE,
1415 .driver_name = "atmel_serial",
1416 .dev_name = ATMEL_DEVICENAME,
1417 .major = SERIAL_ATMEL_MAJOR,
1418 .minor = MINOR_START,
1419 .nr = ATMEL_MAX_UART,
1420 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV
1421};
1422
afefc415 1423#ifdef CONFIG_PM
b843aa21
RB
1424static int atmel_serial_suspend(struct platform_device *pdev,
1425 pm_message_t state)
1e6c9c28 1426{
afefc415 1427 struct uart_port *port = platform_get_drvdata(pdev);
b843aa21 1428 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
afefc415 1429
b843aa21
RB
1430 if (device_may_wakeup(&pdev->dev)
1431 && !at91_suspend_entering_slow_clock())
afefc415
AV
1432 enable_irq_wake(port->irq);
1433 else {
7192f92c
HS
1434 uart_suspend_port(&atmel_uart, port);
1435 atmel_port->suspended = 1;
afefc415 1436 }
1e6c9c28 1437
afefc415
AV
1438 return 0;
1439}
1e6c9c28 1440
7192f92c 1441static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV
1442{
1443 struct uart_port *port = platform_get_drvdata(pdev);
b843aa21 1444 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
1e6c9c28 1445
7192f92c
HS
1446 if (atmel_port->suspended) {
1447 uart_resume_port(&atmel_uart, port);
1448 atmel_port->suspended = 0;
b843aa21 1449 } else
9b938166 1450 disable_irq_wake(port->irq);
1e6c9c28
AV
1451
1452 return 0;
1453}
afefc415 1454#else
7192f92c
HS
1455#define atmel_serial_suspend NULL
1456#define atmel_serial_resume NULL
afefc415 1457#endif
1e6c9c28 1458
7192f92c 1459static int __devinit atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 1460{
7192f92c 1461 struct atmel_uart_port *port;
1ecc26bd 1462 void *data;
afefc415 1463 int ret;
1e6c9c28 1464
1ecc26bd
RB
1465 BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE));
1466
7192f92c
HS
1467 port = &atmel_ports[pdev->id];
1468 atmel_init_port(port, pdev);
1e6c9c28 1469
a6670615
CC
1470 if (!atmel_use_dma_rx(&port->uart)) {
1471 ret = -ENOMEM;
6433471d
HS
1472 data = kmalloc(sizeof(struct atmel_uart_char)
1473 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC
1474 if (!data)
1475 goto err_alloc_ring;
1476 port->rx_ring.buf = data;
1477 }
1ecc26bd 1478
7192f92c 1479 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS
1480 if (ret)
1481 goto err_add_port;
1482
1483 device_init_wakeup(&pdev->dev, 1);
1484 platform_set_drvdata(pdev, port);
1485
1486 return 0;
1487
1488err_add_port:
1ecc26bd
RB
1489 kfree(port->rx_ring.buf);
1490 port->rx_ring.buf = NULL;
1491err_alloc_ring:
dfa7f343
HS
1492 if (!atmel_is_console_port(&port->uart)) {
1493 clk_disable(port->clk);
1494 clk_put(port->clk);
1495 port->clk = NULL;
afefc415
AV
1496 }
1497
1498 return ret;
1499}
1500
7192f92c 1501static int __devexit atmel_serial_remove(struct platform_device *pdev)
afefc415
AV
1502{
1503 struct uart_port *port = platform_get_drvdata(pdev);
b843aa21 1504 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port;
afefc415
AV
1505 int ret = 0;
1506
afefc415
AV
1507 device_init_wakeup(&pdev->dev, 0);
1508 platform_set_drvdata(pdev, NULL);
1509
dfa7f343
HS
1510 ret = uart_remove_one_port(&atmel_uart, port);
1511
1ecc26bd
RB
1512 tasklet_kill(&atmel_port->tasklet);
1513 kfree(atmel_port->rx_ring.buf);
1514
dfa7f343
HS
1515 /* "port" is allocated statically, so we shouldn't free it */
1516
1517 clk_disable(atmel_port->clk);
1518 clk_put(atmel_port->clk);
afefc415
AV
1519
1520 return ret;
1521}
1522
7192f92c
HS
1523static struct platform_driver atmel_serial_driver = {
1524 .probe = atmel_serial_probe,
1525 .remove = __devexit_p(atmel_serial_remove),
1526 .suspend = atmel_serial_suspend,
1527 .resume = atmel_serial_resume,
afefc415 1528 .driver = {
1e8ea802 1529 .name = "atmel_usart",
afefc415
AV
1530 .owner = THIS_MODULE,
1531 },
1532};
1533
7192f92c 1534static int __init atmel_serial_init(void)
afefc415
AV
1535{
1536 int ret;
1537
7192f92c 1538 ret = uart_register_driver(&atmel_uart);
afefc415
AV
1539 if (ret)
1540 return ret;
1541
7192f92c 1542 ret = platform_driver_register(&atmel_serial_driver);
afefc415 1543 if (ret)
7192f92c 1544 uart_unregister_driver(&atmel_uart);
afefc415
AV
1545
1546 return ret;
1547}
1548
7192f92c 1549static void __exit atmel_serial_exit(void)
afefc415 1550{
7192f92c
HS
1551 platform_driver_unregister(&atmel_serial_driver);
1552 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV
1553}
1554
7192f92c
HS
1555module_init(atmel_serial_init);
1556module_exit(atmel_serial_exit);
1e6c9c28
AV
1557
1558MODULE_AUTHOR("Rick Bronson");
7192f92c 1559MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 1560MODULE_LICENSE("GPL");