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1e6c9c28 AV |
1 | /* |
2 | * linux/drivers/char/at91_serial.c | |
3 | * | |
7192f92c | 4 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
5 | * Copyright (C) 2003 Rick Bronson |
6 | * | |
7 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
8 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
1e6c9c28 AV |
36 | |
37 | #include <asm/io.h> | |
38 | ||
afefc415 AV |
39 | #include <asm/arch/at91rm9200_pdc.h> |
40 | #include <asm/mach/serial_at91.h> | |
1e6c9c28 | 41 | #include <asm/arch/board.h> |
afefc415 | 42 | #include <asm/arch/system.h> |
20e65276 | 43 | #include <asm/arch/gpio.h> |
1e6c9c28 | 44 | |
5b34821a HS |
45 | #include "atmel_serial.h" |
46 | ||
749c4e60 | 47 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
48 | #define SUPPORT_SYSRQ |
49 | #endif | |
50 | ||
51 | #include <linux/serial_core.h> | |
52 | ||
749c4e60 | 53 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
54 | |
55 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
56 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
57 | * UART. */ | |
7192f92c | 58 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 59 | #define MINOR_START 154 |
7192f92c | 60 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
61 | |
62 | #else | |
63 | ||
64 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
65 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 66 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 67 | #define MINOR_START 64 |
7192f92c | 68 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
69 | |
70 | #endif | |
71 | ||
7192f92c | 72 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 73 | |
7192f92c HS |
74 | #define UART_PUT_CR(port,v) writel(v, (port)->membase + ATMEL_US_CR) |
75 | #define UART_GET_MR(port) readl((port)->membase + ATMEL_US_MR) | |
76 | #define UART_PUT_MR(port,v) writel(v, (port)->membase + ATMEL_US_MR) | |
77 | #define UART_PUT_IER(port,v) writel(v, (port)->membase + ATMEL_US_IER) | |
78 | #define UART_PUT_IDR(port,v) writel(v, (port)->membase + ATMEL_US_IDR) | |
79 | #define UART_GET_IMR(port) readl((port)->membase + ATMEL_US_IMR) | |
80 | #define UART_GET_CSR(port) readl((port)->membase + ATMEL_US_CSR) | |
81 | #define UART_GET_CHAR(port) readl((port)->membase + ATMEL_US_RHR) | |
82 | #define UART_PUT_CHAR(port,v) writel(v, (port)->membase + ATMEL_US_THR) | |
83 | #define UART_GET_BRGR(port) readl((port)->membase + ATMEL_US_BRGR) | |
84 | #define UART_PUT_BRGR(port,v) writel(v, (port)->membase + ATMEL_US_BRGR) | |
85 | #define UART_PUT_RTOR(port,v) writel(v, (port)->membase + ATMEL_US_RTOR) | |
1e6c9c28 | 86 | |
7192f92c | 87 | // #define UART_GET_CR(port) readl((port)->membase + ATMEL_US_CR) // is write-only |
1e6c9c28 AV |
88 | |
89 | /* PDC registers */ | |
7192f92c HS |
90 | #define UART_PUT_PTCR(port,v) writel(v, (port)->membase + ATMEL_PDC_PTCR) |
91 | #define UART_GET_PTSR(port) readl((port)->membase + ATMEL_PDC_PTSR) | |
afefc415 | 92 | |
7192f92c HS |
93 | #define UART_PUT_RPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RPR) |
94 | #define UART_GET_RPR(port) readl((port)->membase + ATMEL_PDC_RPR) | |
95 | #define UART_PUT_RCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RCR) | |
96 | #define UART_PUT_RNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
97 | #define UART_PUT_RNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
1e6c9c28 | 98 | |
7192f92c HS |
99 | #define UART_PUT_TPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TPR) |
100 | #define UART_PUT_TCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TCR) | |
101 | //#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNPR) | |
102 | //#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNCR) | |
1e6c9c28 | 103 | |
71f2e2b8 HS |
104 | static int (*atmel_open_hook)(struct uart_port *); |
105 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 106 | |
afefc415 AV |
107 | /* |
108 | * We wrap our port structure around the generic uart_port. | |
109 | */ | |
7192f92c | 110 | struct atmel_uart_port { |
afefc415 AV |
111 | struct uart_port uart; /* uart */ |
112 | struct clk *clk; /* uart clock */ | |
113 | unsigned short suspended; /* is port suspended? */ | |
114 | }; | |
115 | ||
7192f92c | 116 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
afefc415 | 117 | |
1e6c9c28 | 118 | #ifdef SUPPORT_SYSRQ |
7192f92c | 119 | static struct console atmel_console; |
1e6c9c28 AV |
120 | #endif |
121 | ||
122 | /* | |
123 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
124 | */ | |
7192f92c | 125 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 126 | { |
7192f92c | 127 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
128 | } |
129 | ||
130 | /* | |
131 | * Set state of the modem control output lines | |
132 | */ | |
7192f92c | 133 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
134 | { |
135 | unsigned int control = 0; | |
afefc415 | 136 | unsigned int mode; |
1e6c9c28 | 137 | |
afefc415 AV |
138 | if (arch_identify() == ARCH_ID_AT91RM9200) { |
139 | /* | |
140 | * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21. | |
141 | * We need to drive the pin manually. | |
142 | */ | |
72729910 | 143 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 144 | if (mctrl & TIOCM_RTS) |
20e65276 | 145 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 146 | else |
20e65276 | 147 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 148 | } |
1e6c9c28 AV |
149 | } |
150 | ||
151 | if (mctrl & TIOCM_RTS) | |
7192f92c | 152 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 153 | else |
7192f92c | 154 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
155 | |
156 | if (mctrl & TIOCM_DTR) | |
7192f92c | 157 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 158 | else |
7192f92c | 159 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 160 | |
afefc415 AV |
161 | UART_PUT_CR(port, control); |
162 | ||
163 | /* Local loopback mode? */ | |
7192f92c | 164 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 165 | if (mctrl & TIOCM_LOOP) |
7192f92c | 166 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 167 | else |
7192f92c | 168 | mode |= ATMEL_US_CHMODE_NORMAL; |
afefc415 | 169 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
170 | } |
171 | ||
172 | /* | |
173 | * Get state of the modem control input lines | |
174 | */ | |
7192f92c | 175 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
176 | { |
177 | unsigned int status, ret = 0; | |
178 | ||
179 | status = UART_GET_CSR(port); | |
180 | ||
181 | /* | |
182 | * The control signals are active low. | |
183 | */ | |
7192f92c | 184 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 185 | ret |= TIOCM_CD; |
7192f92c | 186 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 187 | ret |= TIOCM_CTS; |
7192f92c | 188 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 189 | ret |= TIOCM_DSR; |
7192f92c | 190 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
191 | ret |= TIOCM_RI; |
192 | ||
193 | return ret; | |
194 | } | |
195 | ||
196 | /* | |
197 | * Stop transmitting. | |
198 | */ | |
7192f92c | 199 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 200 | { |
7192f92c | 201 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 202 | |
7192f92c | 203 | UART_PUT_IDR(port, ATMEL_US_TXRDY); |
1e6c9c28 AV |
204 | } |
205 | ||
206 | /* | |
207 | * Start transmitting. | |
208 | */ | |
7192f92c | 209 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 210 | { |
7192f92c | 211 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 212 | |
7192f92c | 213 | UART_PUT_IER(port, ATMEL_US_TXRDY); |
1e6c9c28 AV |
214 | } |
215 | ||
216 | /* | |
217 | * Stop receiving - port is in process of being closed. | |
218 | */ | |
7192f92c | 219 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 220 | { |
7192f92c | 221 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 222 | |
7192f92c | 223 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
1e6c9c28 AV |
224 | } |
225 | ||
226 | /* | |
227 | * Enable modem status interrupts | |
228 | */ | |
7192f92c | 229 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 230 | { |
7192f92c | 231 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC); |
1e6c9c28 AV |
232 | } |
233 | ||
234 | /* | |
235 | * Control the transmission of a break signal | |
236 | */ | |
7192f92c | 237 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
238 | { |
239 | if (break_state != 0) | |
7192f92c | 240 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 241 | else |
7192f92c | 242 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
243 | } |
244 | ||
245 | /* | |
246 | * Characters received (called from interrupt handler) | |
247 | */ | |
7192f92c | 248 | static void atmel_rx_chars(struct uart_port *port, struct pt_regs *regs) |
1e6c9c28 AV |
249 | { |
250 | struct tty_struct *tty = port->info->tty; | |
251 | unsigned int status, ch, flg; | |
252 | ||
afefc415 | 253 | status = UART_GET_CSR(port); |
7192f92c | 254 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
255 | ch = UART_GET_CHAR(port); |
256 | ||
1e6c9c28 AV |
257 | port->icount.rx++; |
258 | ||
259 | flg = TTY_NORMAL; | |
260 | ||
261 | /* | |
262 | * note that the error handling code is | |
263 | * out of the main execution path | |
264 | */ | |
7192f92c HS |
265 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { |
266 | UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */ | |
267 | if (status & ATMEL_US_RXBRK) { | |
268 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */ | |
afefc415 AV |
269 | port->icount.brk++; |
270 | if (uart_handle_break(port)) | |
271 | goto ignore_char; | |
272 | } | |
7192f92c | 273 | if (status & ATMEL_US_PARE) |
1e6c9c28 | 274 | port->icount.parity++; |
7192f92c | 275 | if (status & ATMEL_US_FRAME) |
1e6c9c28 | 276 | port->icount.frame++; |
7192f92c | 277 | if (status & ATMEL_US_OVRE) |
1e6c9c28 AV |
278 | port->icount.overrun++; |
279 | ||
afefc415 AV |
280 | status &= port->read_status_mask; |
281 | ||
7192f92c | 282 | if (status & ATMEL_US_RXBRK) |
afefc415 | 283 | flg = TTY_BREAK; |
7192f92c | 284 | else if (status & ATMEL_US_PARE) |
1e6c9c28 | 285 | flg = TTY_PARITY; |
7192f92c | 286 | else if (status & ATMEL_US_FRAME) |
1e6c9c28 | 287 | flg = TTY_FRAME; |
1e6c9c28 AV |
288 | } |
289 | ||
290 | if (uart_handle_sysrq_char(port, ch, regs)) | |
291 | goto ignore_char; | |
292 | ||
7192f92c | 293 | uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg); |
1e6c9c28 AV |
294 | |
295 | ignore_char: | |
afefc415 | 296 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
297 | } |
298 | ||
299 | tty_flip_buffer_push(tty); | |
300 | } | |
301 | ||
302 | /* | |
303 | * Transmit characters (called from interrupt handler) | |
304 | */ | |
7192f92c | 305 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 AV |
306 | { |
307 | struct circ_buf *xmit = &port->info->xmit; | |
308 | ||
309 | if (port->x_char) { | |
310 | UART_PUT_CHAR(port, port->x_char); | |
311 | port->icount.tx++; | |
312 | port->x_char = 0; | |
313 | return; | |
314 | } | |
315 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
7192f92c | 316 | atmel_stop_tx(port); |
1e6c9c28 AV |
317 | return; |
318 | } | |
319 | ||
7192f92c | 320 | while (UART_GET_CSR(port) & ATMEL_US_TXRDY) { |
1e6c9c28 AV |
321 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
322 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
323 | port->icount.tx++; | |
324 | if (uart_circ_empty(xmit)) | |
325 | break; | |
326 | } | |
327 | ||
328 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
329 | uart_write_wakeup(port); | |
330 | ||
331 | if (uart_circ_empty(xmit)) | |
7192f92c | 332 | atmel_stop_tx(port); |
1e6c9c28 AV |
333 | } |
334 | ||
335 | /* | |
336 | * Interrupt handler | |
337 | */ | |
7192f92c | 338 | static irqreturn_t atmel_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
1e6c9c28 AV |
339 | { |
340 | struct uart_port *port = dev_id; | |
7192f92c | 341 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 AV |
342 | unsigned int status, pending, pass_counter = 0; |
343 | ||
344 | status = UART_GET_CSR(port); | |
afefc415 AV |
345 | pending = status & UART_GET_IMR(port); |
346 | while (pending) { | |
347 | /* Interrupt receive */ | |
7192f92c HS |
348 | if (pending & ATMEL_US_RXRDY) |
349 | atmel_rx_chars(port, regs); | |
afefc415 AV |
350 | |
351 | // TODO: All reads to CSR will clear these interrupts! | |
7192f92c HS |
352 | if (pending & ATMEL_US_RIIC) port->icount.rng++; |
353 | if (pending & ATMEL_US_DSRIC) port->icount.dsr++; | |
354 | if (pending & ATMEL_US_DCDIC) | |
355 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
356 | if (pending & ATMEL_US_CTSIC) | |
357 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
358 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC)) | |
afefc415 AV |
359 | wake_up_interruptible(&port->info->delta_msr_wait); |
360 | ||
361 | /* Interrupt transmit */ | |
7192f92c HS |
362 | if (pending & ATMEL_US_TXRDY) |
363 | atmel_tx_chars(port); | |
afefc415 | 364 | |
7192f92c | 365 | if (pass_counter++ > ATMEL_ISR_PASS_LIMIT) |
afefc415 | 366 | break; |
1e6c9c28 | 367 | |
afefc415 AV |
368 | status = UART_GET_CSR(port); |
369 | pending = status & UART_GET_IMR(port); | |
1e6c9c28 AV |
370 | } |
371 | return IRQ_HANDLED; | |
372 | } | |
373 | ||
374 | /* | |
375 | * Perform initialization and enable port for reception | |
376 | */ | |
7192f92c | 377 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 378 | { |
7192f92c | 379 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 AV |
380 | int retval; |
381 | ||
382 | /* | |
383 | * Ensure that no interrupts are enabled otherwise when | |
384 | * request_irq() is called we could get stuck trying to | |
385 | * handle an unexpected interrupt | |
386 | */ | |
387 | UART_PUT_IDR(port, -1); | |
388 | ||
389 | /* | |
390 | * Allocate the IRQ | |
391 | */ | |
7192f92c | 392 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, "atmel_serial", port); |
1e6c9c28 | 393 | if (retval) { |
7192f92c | 394 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
395 | return retval; |
396 | } | |
397 | ||
398 | /* | |
399 | * If there is a specific "open" function (to register | |
400 | * control line interrupts) | |
401 | */ | |
71f2e2b8 HS |
402 | if (atmel_open_hook) { |
403 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
404 | if (retval) { |
405 | free_irq(port->irq, port); | |
406 | return retval; | |
407 | } | |
408 | } | |
409 | ||
1e6c9c28 AV |
410 | /* |
411 | * Finally, enable the serial port | |
412 | */ | |
7192f92c HS |
413 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
414 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */ | |
afefc415 | 415 | |
7192f92c | 416 | UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */ |
afefc415 | 417 | |
1e6c9c28 AV |
418 | return 0; |
419 | } | |
420 | ||
421 | /* | |
422 | * Disable the port | |
423 | */ | |
7192f92c | 424 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 425 | { |
7192f92c | 426 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 427 | |
1e6c9c28 AV |
428 | /* |
429 | * Disable all interrupts, port and break condition. | |
430 | */ | |
7192f92c | 431 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
432 | UART_PUT_IDR(port, -1); |
433 | ||
434 | /* | |
435 | * Free the interrupt | |
436 | */ | |
437 | free_irq(port->irq, port); | |
438 | ||
439 | /* | |
440 | * If there is a specific "close" function (to unregister | |
441 | * control line interrupts) | |
442 | */ | |
71f2e2b8 HS |
443 | if (atmel_close_hook) |
444 | atmel_close_hook(port); | |
1e6c9c28 AV |
445 | } |
446 | ||
447 | /* | |
448 | * Power / Clock management. | |
449 | */ | |
7192f92c | 450 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) |
1e6c9c28 | 451 | { |
7192f92c | 452 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 453 | |
1e6c9c28 AV |
454 | switch (state) { |
455 | case 0: | |
456 | /* | |
457 | * Enable the peripheral clock for this serial port. | |
458 | * This is called on uart_open() or a resume event. | |
459 | */ | |
7192f92c | 460 | clk_enable(atmel_port->clk); |
1e6c9c28 AV |
461 | break; |
462 | case 3: | |
463 | /* | |
464 | * Disable the peripheral clock for this serial port. | |
465 | * This is called on uart_close() or a suspend event. | |
466 | */ | |
7192f92c | 467 | clk_disable(atmel_port->clk); |
1e6c9c28 AV |
468 | break; |
469 | default: | |
7192f92c | 470 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); |
1e6c9c28 AV |
471 | } |
472 | } | |
473 | ||
474 | /* | |
475 | * Change the port parameters | |
476 | */ | |
7192f92c | 477 | static void atmel_set_termios(struct uart_port *port, struct termios * termios, struct termios * old) |
1e6c9c28 AV |
478 | { |
479 | unsigned long flags; | |
480 | unsigned int mode, imr, quot, baud; | |
481 | ||
482 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
483 | quot = uart_get_divisor(port, baud); | |
484 | ||
485 | /* Get current mode register */ | |
7192f92c | 486 | mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR); |
1e6c9c28 AV |
487 | |
488 | /* byte size */ | |
489 | switch (termios->c_cflag & CSIZE) { | |
490 | case CS5: | |
7192f92c | 491 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
492 | break; |
493 | case CS6: | |
7192f92c | 494 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
495 | break; |
496 | case CS7: | |
7192f92c | 497 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
498 | break; |
499 | default: | |
7192f92c | 500 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
501 | break; |
502 | } | |
503 | ||
504 | /* stop bits */ | |
505 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 506 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
507 | |
508 | /* parity */ | |
509 | if (termios->c_cflag & PARENB) { | |
510 | if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */ | |
511 | if (termios->c_cflag & PARODD) | |
7192f92c | 512 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 513 | else |
7192f92c | 514 | mode |= ATMEL_US_PAR_SPACE; |
1e6c9c28 AV |
515 | } |
516 | else if (termios->c_cflag & PARODD) | |
7192f92c | 517 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 518 | else |
7192f92c | 519 | mode |= ATMEL_US_PAR_EVEN; |
1e6c9c28 AV |
520 | } |
521 | else | |
7192f92c | 522 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
523 | |
524 | spin_lock_irqsave(&port->lock, flags); | |
525 | ||
7192f92c | 526 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 527 | if (termios->c_iflag & INPCK) |
7192f92c | 528 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 529 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 530 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
531 | |
532 | /* | |
533 | * Characters to ignore | |
534 | */ | |
535 | port->ignore_status_mask = 0; | |
536 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 537 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 538 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 539 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
540 | /* |
541 | * If we're ignoring parity and break indicators, | |
542 | * ignore overruns too (for real raw support). | |
543 | */ | |
544 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 545 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 AV |
546 | } |
547 | ||
548 | // TODO: Ignore all characters if CREAD is set. | |
549 | ||
550 | /* update the per-port timeout */ | |
551 | uart_update_timeout(port, termios->c_cflag, baud); | |
552 | ||
553 | /* disable interrupts and drain transmitter */ | |
554 | imr = UART_GET_IMR(port); /* get interrupt mask */ | |
555 | UART_PUT_IDR(port, -1); /* disable all interrupts */ | |
7192f92c | 556 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) { barrier(); } |
1e6c9c28 AV |
557 | |
558 | /* disable receiver and transmitter */ | |
7192f92c | 559 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 AV |
560 | |
561 | /* set the parity, stop bits and data size */ | |
562 | UART_PUT_MR(port, mode); | |
563 | ||
564 | /* set the baud rate */ | |
565 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
566 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
567 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
568 | |
569 | /* restore interrupts */ | |
570 | UART_PUT_IER(port, imr); | |
571 | ||
572 | /* CTS flow-control and modem-status interrupts */ | |
573 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
574 | port->ops->enable_ms(port); | |
575 | ||
576 | spin_unlock_irqrestore(&port->lock, flags); | |
577 | } | |
578 | ||
579 | /* | |
580 | * Return string describing the specified port | |
581 | */ | |
7192f92c | 582 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 583 | { |
9ab4f88b | 584 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
585 | } |
586 | ||
587 | /* | |
588 | * Release the memory region(s) being used by 'port'. | |
589 | */ | |
7192f92c | 590 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 591 | { |
afefc415 AV |
592 | struct platform_device *pdev = to_platform_device(port->dev); |
593 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
594 | ||
595 | release_mem_region(port->mapbase, size); | |
596 | ||
597 | if (port->flags & UPF_IOREMAP) { | |
598 | iounmap(port->membase); | |
599 | port->membase = NULL; | |
600 | } | |
1e6c9c28 AV |
601 | } |
602 | ||
603 | /* | |
604 | * Request the memory region(s) being used by 'port'. | |
605 | */ | |
7192f92c | 606 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 607 | { |
afefc415 AV |
608 | struct platform_device *pdev = to_platform_device(port->dev); |
609 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
610 | ||
7192f92c | 611 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
612 | return -EBUSY; |
613 | ||
614 | if (port->flags & UPF_IOREMAP) { | |
615 | port->membase = ioremap(port->mapbase, size); | |
616 | if (port->membase == NULL) { | |
617 | release_mem_region(port->mapbase, size); | |
618 | return -ENOMEM; | |
619 | } | |
620 | } | |
1e6c9c28 | 621 | |
afefc415 | 622 | return 0; |
1e6c9c28 AV |
623 | } |
624 | ||
625 | /* | |
626 | * Configure/autoconfigure the port. | |
627 | */ | |
7192f92c | 628 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
629 | { |
630 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 631 | port->type = PORT_ATMEL; |
7192f92c | 632 | atmel_request_port(port); |
1e6c9c28 AV |
633 | } |
634 | } | |
635 | ||
636 | /* | |
637 | * Verify the new serial_struct (for TIOCSSERIAL). | |
638 | */ | |
7192f92c | 639 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
640 | { |
641 | int ret = 0; | |
9ab4f88b | 642 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
643 | ret = -EINVAL; |
644 | if (port->irq != ser->irq) | |
645 | ret = -EINVAL; | |
646 | if (ser->io_type != SERIAL_IO_MEM) | |
647 | ret = -EINVAL; | |
648 | if (port->uartclk / 16 != ser->baud_base) | |
649 | ret = -EINVAL; | |
650 | if ((void *)port->mapbase != ser->iomem_base) | |
651 | ret = -EINVAL; | |
652 | if (port->iobase != ser->port) | |
653 | ret = -EINVAL; | |
654 | if (ser->hub6 != 0) | |
655 | ret = -EINVAL; | |
656 | return ret; | |
657 | } | |
658 | ||
7192f92c HS |
659 | static struct uart_ops atmel_pops = { |
660 | .tx_empty = atmel_tx_empty, | |
661 | .set_mctrl = atmel_set_mctrl, | |
662 | .get_mctrl = atmel_get_mctrl, | |
663 | .stop_tx = atmel_stop_tx, | |
664 | .start_tx = atmel_start_tx, | |
665 | .stop_rx = atmel_stop_rx, | |
666 | .enable_ms = atmel_enable_ms, | |
667 | .break_ctl = atmel_break_ctl, | |
668 | .startup = atmel_startup, | |
669 | .shutdown = atmel_shutdown, | |
670 | .set_termios = atmel_set_termios, | |
671 | .type = atmel_type, | |
672 | .release_port = atmel_release_port, | |
673 | .request_port = atmel_request_port, | |
674 | .config_port = atmel_config_port, | |
675 | .verify_port = atmel_verify_port, | |
676 | .pm = atmel_serial_pm, | |
1e6c9c28 AV |
677 | }; |
678 | ||
afefc415 AV |
679 | /* |
680 | * Configure the port from the platform device resource info. | |
681 | */ | |
7192f92c | 682 | static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct platform_device *pdev) |
1e6c9c28 | 683 | { |
7192f92c | 684 | struct uart_port *port = &atmel_port->uart; |
73e2798b | 685 | struct atmel_uart_data *data = pdev->dev.platform_data; |
afefc415 AV |
686 | |
687 | port->iotype = UPIO_MEM; | |
688 | port->flags = UPF_BOOT_AUTOCONF; | |
7192f92c | 689 | port->ops = &atmel_pops; |
afefc415 AV |
690 | port->fifosize = 1; |
691 | port->line = pdev->id; | |
692 | port->dev = &pdev->dev; | |
693 | ||
694 | port->mapbase = pdev->resource[0].start; | |
695 | port->irq = pdev->resource[1].start; | |
696 | ||
697 | if (port->mapbase == AT91_VA_BASE_SYS + AT91_DBGU) /* Part of system perpherals - already mapped */ | |
698 | port->membase = (void __iomem *) port->mapbase; | |
699 | else { | |
700 | port->flags |= UPF_IOREMAP; | |
701 | port->membase = NULL; | |
702 | } | |
1e6c9c28 | 703 | |
7192f92c HS |
704 | if (!atmel_port->clk) { /* for console, the clock could already be configured */ |
705 | atmel_port->clk = clk_get(&pdev->dev, "usart"); | |
706 | clk_enable(atmel_port->clk); | |
707 | port->uartclk = clk_get_rate(atmel_port->clk); | |
afefc415 | 708 | } |
1e6c9c28 AV |
709 | } |
710 | ||
afefc415 AV |
711 | /* |
712 | * Register board-specific modem-control line handlers. | |
713 | */ | |
71f2e2b8 | 714 | void __init atmel_register_uart_fns(struct atmel_port_fns *fns) |
1e6c9c28 AV |
715 | { |
716 | if (fns->enable_ms) | |
7192f92c | 717 | atmel_pops.enable_ms = fns->enable_ms; |
1e6c9c28 | 718 | if (fns->get_mctrl) |
7192f92c | 719 | atmel_pops.get_mctrl = fns->get_mctrl; |
1e6c9c28 | 720 | if (fns->set_mctrl) |
7192f92c | 721 | atmel_pops.set_mctrl = fns->set_mctrl; |
71f2e2b8 HS |
722 | atmel_open_hook = fns->open; |
723 | atmel_close_hook = fns->close; | |
7192f92c HS |
724 | atmel_pops.pm = fns->pm; |
725 | atmel_pops.set_wake = fns->set_wake; | |
1e6c9c28 AV |
726 | } |
727 | ||
1e6c9c28 | 728 | |
749c4e60 | 729 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 730 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 731 | { |
7192f92c | 732 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
d358788f RK |
733 | barrier(); |
734 | UART_PUT_CHAR(port, ch); | |
735 | } | |
1e6c9c28 AV |
736 | |
737 | /* | |
738 | * Interrupts are disabled on entering | |
739 | */ | |
7192f92c | 740 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 741 | { |
7192f92c | 742 | struct uart_port *port = &atmel_ports[co->index].uart; |
d358788f | 743 | unsigned int status, imr; |
1e6c9c28 AV |
744 | |
745 | /* | |
746 | * First, save IMR and then disable interrupts | |
747 | */ | |
748 | imr = UART_GET_IMR(port); /* get interrupt mask */ | |
7192f92c | 749 | UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY); |
1e6c9c28 | 750 | |
7192f92c | 751 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
752 | |
753 | /* | |
754 | * Finally, wait for transmitter to become empty | |
755 | * and restore IMR | |
756 | */ | |
757 | do { | |
758 | status = UART_GET_CSR(port); | |
7192f92c | 759 | } while (!(status & ATMEL_US_TXRDY)); |
1e6c9c28 AV |
760 | UART_PUT_IER(port, imr); /* set interrupts back the way they were */ |
761 | } | |
762 | ||
763 | /* | |
764 | * If the port was already initialised (eg, by a boot loader), try to determine | |
765 | * the current setup. | |
766 | */ | |
7192f92c | 767 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits) |
1e6c9c28 AV |
768 | { |
769 | unsigned int mr, quot; | |
770 | ||
771 | // TODO: CR is a write-only register | |
772 | // unsigned int cr; | |
773 | // | |
7192f92c HS |
774 | // cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN); |
775 | // if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) { | |
1e6c9c28 AV |
776 | // /* ok, the port was enabled */ |
777 | // } | |
778 | ||
7192f92c HS |
779 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
780 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
781 | *bits = 8; |
782 | else | |
783 | *bits = 7; | |
784 | ||
7192f92c HS |
785 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
786 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 787 | *parity = 'e'; |
7192f92c | 788 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
789 | *parity = 'o'; |
790 | ||
791 | quot = UART_GET_BRGR(port); | |
792 | *baud = port->uartclk / (16 * (quot)); | |
793 | } | |
794 | ||
7192f92c | 795 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 796 | { |
7192f92c | 797 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
798 | int baud = 115200; |
799 | int bits = 8; | |
800 | int parity = 'n'; | |
801 | int flow = 'n'; | |
802 | ||
afefc415 AV |
803 | if (port->membase == 0) /* Port not initialized yet - delay setup */ |
804 | return -ENODEV; | |
1e6c9c28 | 805 | |
1e6c9c28 | 806 | UART_PUT_IDR(port, -1); /* disable interrupts */ |
7192f92c HS |
807 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
808 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
809 | |
810 | if (options) | |
811 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
812 | else | |
7192f92c | 813 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
814 | |
815 | return uart_set_options(port, co, baud, parity, bits, flow); | |
816 | } | |
817 | ||
7192f92c | 818 | static struct uart_driver atmel_uart; |
1e6c9c28 | 819 | |
7192f92c HS |
820 | static struct console atmel_console = { |
821 | .name = ATMEL_DEVICENAME, | |
822 | .write = atmel_console_write, | |
1e6c9c28 | 823 | .device = uart_console_device, |
7192f92c | 824 | .setup = atmel_console_setup, |
1e6c9c28 AV |
825 | .flags = CON_PRINTBUFFER, |
826 | .index = -1, | |
7192f92c | 827 | .data = &atmel_uart, |
1e6c9c28 AV |
828 | }; |
829 | ||
7192f92c | 830 | #define ATMEL_CONSOLE_DEVICE &atmel_console |
1e6c9c28 | 831 | |
afefc415 AV |
832 | /* |
833 | * Early console initialization (before VM subsystem initialized). | |
834 | */ | |
7192f92c | 835 | static int __init atmel_console_init(void) |
1e6c9c28 | 836 | { |
73e2798b | 837 | if (atmel_default_console_device) { |
7192f92c HS |
838 | add_preferred_console(ATMEL_DEVICENAME, atmel_default_console_device->id, NULL); |
839 | atmel_init_port(&(atmel_ports[atmel_default_console_device->id]), atmel_default_console_device); | |
840 | register_console(&atmel_console); | |
afefc415 | 841 | } |
1e6c9c28 | 842 | |
1e6c9c28 AV |
843 | return 0; |
844 | } | |
7192f92c | 845 | console_initcall(atmel_console_init); |
1e6c9c28 | 846 | |
afefc415 AV |
847 | /* |
848 | * Late console initialization. | |
849 | */ | |
7192f92c | 850 | static int __init atmel_late_console_init(void) |
afefc415 | 851 | { |
7192f92c HS |
852 | if (atmel_default_console_device && !(atmel_console.flags & CON_ENABLED)) |
853 | register_console(&atmel_console); | |
afefc415 AV |
854 | |
855 | return 0; | |
856 | } | |
7192f92c | 857 | core_initcall(atmel_late_console_init); |
afefc415 | 858 | |
1e6c9c28 | 859 | #else |
7192f92c | 860 | #define ATMEL_CONSOLE_DEVICE NULL |
1e6c9c28 AV |
861 | #endif |
862 | ||
7192f92c | 863 | static struct uart_driver atmel_uart = { |
1e6c9c28 | 864 | .owner = THIS_MODULE, |
7192f92c HS |
865 | .driver_name = "atmel_serial", |
866 | .dev_name = ATMEL_DEVICENAME, | |
867 | .major = SERIAL_ATMEL_MAJOR, | |
1e6c9c28 | 868 | .minor = MINOR_START, |
73e2798b | 869 | .nr = ATMEL_MAX_UART, |
7192f92c | 870 | .cons = ATMEL_CONSOLE_DEVICE, |
1e6c9c28 AV |
871 | }; |
872 | ||
afefc415 | 873 | #ifdef CONFIG_PM |
7192f92c | 874 | static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state) |
1e6c9c28 | 875 | { |
afefc415 | 876 | struct uart_port *port = platform_get_drvdata(pdev); |
7192f92c | 877 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 AV |
878 | |
879 | if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock()) | |
880 | enable_irq_wake(port->irq); | |
881 | else { | |
882 | disable_irq_wake(port->irq); | |
7192f92c HS |
883 | uart_suspend_port(&atmel_uart, port); |
884 | atmel_port->suspended = 1; | |
afefc415 | 885 | } |
1e6c9c28 | 886 | |
afefc415 AV |
887 | return 0; |
888 | } | |
1e6c9c28 | 889 | |
7192f92c | 890 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
891 | { |
892 | struct uart_port *port = platform_get_drvdata(pdev); | |
7192f92c | 893 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 | 894 | |
7192f92c HS |
895 | if (atmel_port->suspended) { |
896 | uart_resume_port(&atmel_uart, port); | |
897 | atmel_port->suspended = 0; | |
1e6c9c28 AV |
898 | } |
899 | ||
900 | return 0; | |
901 | } | |
afefc415 | 902 | #else |
7192f92c HS |
903 | #define atmel_serial_suspend NULL |
904 | #define atmel_serial_resume NULL | |
afefc415 | 905 | #endif |
1e6c9c28 | 906 | |
7192f92c | 907 | static int __devinit atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 908 | { |
7192f92c | 909 | struct atmel_uart_port *port; |
afefc415 | 910 | int ret; |
1e6c9c28 | 911 | |
7192f92c HS |
912 | port = &atmel_ports[pdev->id]; |
913 | atmel_init_port(port, pdev); | |
1e6c9c28 | 914 | |
7192f92c | 915 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
afefc415 AV |
916 | if (!ret) { |
917 | device_init_wakeup(&pdev->dev, 1); | |
918 | platform_set_drvdata(pdev, port); | |
919 | } | |
920 | ||
921 | return ret; | |
922 | } | |
923 | ||
7192f92c | 924 | static int __devexit atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
925 | { |
926 | struct uart_port *port = platform_get_drvdata(pdev); | |
7192f92c | 927 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 AV |
928 | int ret = 0; |
929 | ||
7192f92c HS |
930 | clk_disable(atmel_port->clk); |
931 | clk_put(atmel_port->clk); | |
afefc415 AV |
932 | |
933 | device_init_wakeup(&pdev->dev, 0); | |
934 | platform_set_drvdata(pdev, NULL); | |
935 | ||
936 | if (port) { | |
7192f92c | 937 | ret = uart_remove_one_port(&atmel_uart, port); |
afefc415 AV |
938 | kfree(port); |
939 | } | |
940 | ||
941 | return ret; | |
942 | } | |
943 | ||
7192f92c HS |
944 | static struct platform_driver atmel_serial_driver = { |
945 | .probe = atmel_serial_probe, | |
946 | .remove = __devexit_p(atmel_serial_remove), | |
947 | .suspend = atmel_serial_suspend, | |
948 | .resume = atmel_serial_resume, | |
afefc415 | 949 | .driver = { |
1e8ea802 | 950 | .name = "atmel_usart", |
afefc415 AV |
951 | .owner = THIS_MODULE, |
952 | }, | |
953 | }; | |
954 | ||
7192f92c | 955 | static int __init atmel_serial_init(void) |
afefc415 AV |
956 | { |
957 | int ret; | |
958 | ||
7192f92c | 959 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
960 | if (ret) |
961 | return ret; | |
962 | ||
7192f92c | 963 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 964 | if (ret) |
7192f92c | 965 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
966 | |
967 | return ret; | |
968 | } | |
969 | ||
7192f92c | 970 | static void __exit atmel_serial_exit(void) |
afefc415 | 971 | { |
7192f92c HS |
972 | platform_driver_unregister(&atmel_serial_driver); |
973 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
974 | } |
975 | ||
7192f92c HS |
976 | module_init(atmel_serial_init); |
977 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
978 | |
979 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 980 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 981 | MODULE_LICENSE("GPL"); |