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1e6c9c28
AV
1/*
2 * linux/drivers/char/at91_serial.c
3 *
7192f92c 4 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV
5 * Copyright (C) 2003 Rick Bronson
6 *
7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV
25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
afefc415 31#include <linux/clk.h>
1e6c9c28
AV
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
afefc415 35#include <linux/platform_device.h>
1e6c9c28
AV
36
37#include <asm/io.h>
38
afefc415
AV
39#include <asm/arch/at91rm9200_pdc.h>
40#include <asm/mach/serial_at91.h>
1e6c9c28 41#include <asm/arch/board.h>
acca9b83 42#ifdef CONFIG_ARM
afefc415 43#include <asm/arch/system.h>
20e65276 44#include <asm/arch/gpio.h>
acca9b83 45#endif
1e6c9c28 46
5b34821a
HS
47#include "atmel_serial.h"
48
749c4e60 49#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV
50#define SUPPORT_SYSRQ
51#endif
52
53#include <linux/serial_core.h>
54
749c4e60 55#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV
56
57/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
58 * should coexist with the 8250 driver, such as if we have an external 16C550
59 * UART. */
7192f92c 60#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 61#define MINOR_START 154
7192f92c 62#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV
63
64#else
65
66/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
67 * name, but it is legally reserved for the 8250 driver. */
7192f92c 68#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 69#define MINOR_START 64
7192f92c 70#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV
71
72#endif
73
7192f92c 74#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 75
7192f92c
HS
76#define UART_PUT_CR(port,v) writel(v, (port)->membase + ATMEL_US_CR)
77#define UART_GET_MR(port) readl((port)->membase + ATMEL_US_MR)
78#define UART_PUT_MR(port,v) writel(v, (port)->membase + ATMEL_US_MR)
79#define UART_PUT_IER(port,v) writel(v, (port)->membase + ATMEL_US_IER)
80#define UART_PUT_IDR(port,v) writel(v, (port)->membase + ATMEL_US_IDR)
81#define UART_GET_IMR(port) readl((port)->membase + ATMEL_US_IMR)
82#define UART_GET_CSR(port) readl((port)->membase + ATMEL_US_CSR)
83#define UART_GET_CHAR(port) readl((port)->membase + ATMEL_US_RHR)
84#define UART_PUT_CHAR(port,v) writel(v, (port)->membase + ATMEL_US_THR)
85#define UART_GET_BRGR(port) readl((port)->membase + ATMEL_US_BRGR)
86#define UART_PUT_BRGR(port,v) writel(v, (port)->membase + ATMEL_US_BRGR)
87#define UART_PUT_RTOR(port,v) writel(v, (port)->membase + ATMEL_US_RTOR)
1e6c9c28 88
7192f92c 89// #define UART_GET_CR(port) readl((port)->membase + ATMEL_US_CR) // is write-only
1e6c9c28
AV
90
91 /* PDC registers */
7192f92c
HS
92#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + ATMEL_PDC_PTCR)
93#define UART_GET_PTSR(port) readl((port)->membase + ATMEL_PDC_PTSR)
afefc415 94
7192f92c
HS
95#define UART_PUT_RPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RPR)
96#define UART_GET_RPR(port) readl((port)->membase + ATMEL_PDC_RPR)
97#define UART_PUT_RCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RCR)
98#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNPR)
99#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNCR)
1e6c9c28 100
7192f92c
HS
101#define UART_PUT_TPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TPR)
102#define UART_PUT_TCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TCR)
103//#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNPR)
104//#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNCR)
1e6c9c28 105
71f2e2b8
HS
106static int (*atmel_open_hook)(struct uart_port *);
107static void (*atmel_close_hook)(struct uart_port *);
1e6c9c28 108
afefc415
AV
109/*
110 * We wrap our port structure around the generic uart_port.
111 */
7192f92c 112struct atmel_uart_port {
afefc415
AV
113 struct uart_port uart; /* uart */
114 struct clk *clk; /* uart clock */
115 unsigned short suspended; /* is port suspended? */
116};
117
7192f92c 118static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
afefc415 119
1e6c9c28 120#ifdef SUPPORT_SYSRQ
7192f92c 121static struct console atmel_console;
1e6c9c28
AV
122#endif
123
124/*
125 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
126 */
7192f92c 127static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 128{
7192f92c 129 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV
130}
131
132/*
133 * Set state of the modem control output lines
134 */
7192f92c 135static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV
136{
137 unsigned int control = 0;
afefc415 138 unsigned int mode;
1e6c9c28 139
acca9b83 140#ifdef CONFIG_ARM
afefc415
AV
141 if (arch_identify() == ARCH_ID_AT91RM9200) {
142 /*
143 * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
144 * We need to drive the pin manually.
145 */
72729910 146 if (port->mapbase == AT91RM9200_BASE_US0) {
afefc415 147 if (mctrl & TIOCM_RTS)
20e65276 148 at91_set_gpio_value(AT91_PIN_PA21, 0);
afefc415 149 else
20e65276 150 at91_set_gpio_value(AT91_PIN_PA21, 1);
afefc415 151 }
1e6c9c28 152 }
acca9b83 153#endif
1e6c9c28
AV
154
155 if (mctrl & TIOCM_RTS)
7192f92c 156 control |= ATMEL_US_RTSEN;
1e6c9c28 157 else
7192f92c 158 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV
159
160 if (mctrl & TIOCM_DTR)
7192f92c 161 control |= ATMEL_US_DTREN;
1e6c9c28 162 else
7192f92c 163 control |= ATMEL_US_DTRDIS;
1e6c9c28 164
afefc415
AV
165 UART_PUT_CR(port, control);
166
167 /* Local loopback mode? */
7192f92c 168 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 169 if (mctrl & TIOCM_LOOP)
7192f92c 170 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 171 else
7192f92c 172 mode |= ATMEL_US_CHMODE_NORMAL;
afefc415 173 UART_PUT_MR(port, mode);
1e6c9c28
AV
174}
175
176/*
177 * Get state of the modem control input lines
178 */
7192f92c 179static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28
AV
180{
181 unsigned int status, ret = 0;
182
183 status = UART_GET_CSR(port);
184
185 /*
186 * The control signals are active low.
187 */
7192f92c 188 if (!(status & ATMEL_US_DCD))
1e6c9c28 189 ret |= TIOCM_CD;
7192f92c 190 if (!(status & ATMEL_US_CTS))
1e6c9c28 191 ret |= TIOCM_CTS;
7192f92c 192 if (!(status & ATMEL_US_DSR))
1e6c9c28 193 ret |= TIOCM_DSR;
7192f92c 194 if (!(status & ATMEL_US_RI))
1e6c9c28
AV
195 ret |= TIOCM_RI;
196
197 return ret;
198}
199
200/*
201 * Stop transmitting.
202 */
7192f92c 203static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 204{
7192f92c 205 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 206
7192f92c 207 UART_PUT_IDR(port, ATMEL_US_TXRDY);
1e6c9c28
AV
208}
209
210/*
211 * Start transmitting.
212 */
7192f92c 213static void atmel_start_tx(struct uart_port *port)
1e6c9c28 214{
7192f92c 215 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 216
7192f92c 217 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
218}
219
220/*
221 * Stop receiving - port is in process of being closed.
222 */
7192f92c 223static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 224{
7192f92c 225 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 226
7192f92c 227 UART_PUT_IDR(port, ATMEL_US_RXRDY);
1e6c9c28
AV
228}
229
230/*
231 * Enable modem status interrupts
232 */
7192f92c 233static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 234{
7192f92c 235 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
1e6c9c28
AV
236}
237
238/*
239 * Control the transmission of a break signal
240 */
7192f92c 241static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV
242{
243 if (break_state != 0)
7192f92c 244 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 245 else
7192f92c 246 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV
247}
248
249/*
250 * Characters received (called from interrupt handler)
251 */
7d12e780 252static void atmel_rx_chars(struct uart_port *port)
1e6c9c28
AV
253{
254 struct tty_struct *tty = port->info->tty;
255 unsigned int status, ch, flg;
256
afefc415 257 status = UART_GET_CSR(port);
7192f92c 258 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV
259 ch = UART_GET_CHAR(port);
260
1e6c9c28
AV
261 port->icount.rx++;
262
263 flg = TTY_NORMAL;
264
265 /*
266 * note that the error handling code is
267 * out of the main execution path
268 */
7192f92c
HS
269 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
270 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */
271 if (status & ATMEL_US_RXBRK) {
272 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
afefc415
AV
273 port->icount.brk++;
274 if (uart_handle_break(port))
275 goto ignore_char;
276 }
7192f92c 277 if (status & ATMEL_US_PARE)
1e6c9c28 278 port->icount.parity++;
7192f92c 279 if (status & ATMEL_US_FRAME)
1e6c9c28 280 port->icount.frame++;
7192f92c 281 if (status & ATMEL_US_OVRE)
1e6c9c28
AV
282 port->icount.overrun++;
283
afefc415
AV
284 status &= port->read_status_mask;
285
7192f92c 286 if (status & ATMEL_US_RXBRK)
afefc415 287 flg = TTY_BREAK;
7192f92c 288 else if (status & ATMEL_US_PARE)
1e6c9c28 289 flg = TTY_PARITY;
7192f92c 290 else if (status & ATMEL_US_FRAME)
1e6c9c28 291 flg = TTY_FRAME;
1e6c9c28
AV
292 }
293
7d12e780 294 if (uart_handle_sysrq_char(port, ch))
1e6c9c28
AV
295 goto ignore_char;
296
7192f92c 297 uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg);
1e6c9c28
AV
298
299 ignore_char:
afefc415 300 status = UART_GET_CSR(port);
1e6c9c28
AV
301 }
302
303 tty_flip_buffer_push(tty);
304}
305
306/*
307 * Transmit characters (called from interrupt handler)
308 */
7192f92c 309static void atmel_tx_chars(struct uart_port *port)
1e6c9c28
AV
310{
311 struct circ_buf *xmit = &port->info->xmit;
312
313 if (port->x_char) {
314 UART_PUT_CHAR(port, port->x_char);
315 port->icount.tx++;
316 port->x_char = 0;
317 return;
318 }
319 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
7192f92c 320 atmel_stop_tx(port);
1e6c9c28
AV
321 return;
322 }
323
7192f92c 324 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
325 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
326 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
327 port->icount.tx++;
328 if (uart_circ_empty(xmit))
329 break;
330 }
331
332 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
333 uart_write_wakeup(port);
334
335 if (uart_circ_empty(xmit))
7192f92c 336 atmel_stop_tx(port);
1e6c9c28
AV
337}
338
339/*
340 * Interrupt handler
341 */
7d12e780 342static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV
343{
344 struct uart_port *port = dev_id;
7192f92c 345 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
1e6c9c28
AV
346 unsigned int status, pending, pass_counter = 0;
347
348 status = UART_GET_CSR(port);
afefc415
AV
349 pending = status & UART_GET_IMR(port);
350 while (pending) {
351 /* Interrupt receive */
7192f92c 352 if (pending & ATMEL_US_RXRDY)
7d12e780 353 atmel_rx_chars(port);
afefc415
AV
354
355 // TODO: All reads to CSR will clear these interrupts!
7192f92c
HS
356 if (pending & ATMEL_US_RIIC) port->icount.rng++;
357 if (pending & ATMEL_US_DSRIC) port->icount.dsr++;
358 if (pending & ATMEL_US_DCDIC)
359 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
360 if (pending & ATMEL_US_CTSIC)
361 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
362 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
afefc415
AV
363 wake_up_interruptible(&port->info->delta_msr_wait);
364
365 /* Interrupt transmit */
7192f92c
HS
366 if (pending & ATMEL_US_TXRDY)
367 atmel_tx_chars(port);
afefc415 368
7192f92c 369 if (pass_counter++ > ATMEL_ISR_PASS_LIMIT)
afefc415 370 break;
1e6c9c28 371
afefc415
AV
372 status = UART_GET_CSR(port);
373 pending = status & UART_GET_IMR(port);
1e6c9c28
AV
374 }
375 return IRQ_HANDLED;
376}
377
378/*
379 * Perform initialization and enable port for reception
380 */
7192f92c 381static int atmel_startup(struct uart_port *port)
1e6c9c28 382{
7192f92c 383 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
1e6c9c28
AV
384 int retval;
385
386 /*
387 * Ensure that no interrupts are enabled otherwise when
388 * request_irq() is called we could get stuck trying to
389 * handle an unexpected interrupt
390 */
391 UART_PUT_IDR(port, -1);
392
393 /*
394 * Allocate the IRQ
395 */
7192f92c 396 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, "atmel_serial", port);
1e6c9c28 397 if (retval) {
7192f92c 398 printk("atmel_serial: atmel_startup - Can't get irq\n");
1e6c9c28
AV
399 return retval;
400 }
401
402 /*
403 * If there is a specific "open" function (to register
404 * control line interrupts)
405 */
71f2e2b8
HS
406 if (atmel_open_hook) {
407 retval = atmel_open_hook(port);
1e6c9c28
AV
408 if (retval) {
409 free_irq(port->irq, port);
410 return retval;
411 }
412 }
413
1e6c9c28
AV
414 /*
415 * Finally, enable the serial port
416 */
7192f92c
HS
417 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
418 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */
afefc415 419
7192f92c 420 UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
afefc415 421
1e6c9c28
AV
422 return 0;
423}
424
425/*
426 * Disable the port
427 */
7192f92c 428static void atmel_shutdown(struct uart_port *port)
1e6c9c28 429{
7192f92c 430 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 431
1e6c9c28
AV
432 /*
433 * Disable all interrupts, port and break condition.
434 */
7192f92c 435 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1e6c9c28
AV
436 UART_PUT_IDR(port, -1);
437
438 /*
439 * Free the interrupt
440 */
441 free_irq(port->irq, port);
442
443 /*
444 * If there is a specific "close" function (to unregister
445 * control line interrupts)
446 */
71f2e2b8
HS
447 if (atmel_close_hook)
448 atmel_close_hook(port);
1e6c9c28
AV
449}
450
451/*
452 * Power / Clock management.
453 */
7192f92c 454static void atmel_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
1e6c9c28 455{
7192f92c 456 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 457
1e6c9c28
AV
458 switch (state) {
459 case 0:
460 /*
461 * Enable the peripheral clock for this serial port.
462 * This is called on uart_open() or a resume event.
463 */
7192f92c 464 clk_enable(atmel_port->clk);
1e6c9c28
AV
465 break;
466 case 3:
467 /*
468 * Disable the peripheral clock for this serial port.
469 * This is called on uart_close() or a suspend event.
470 */
7192f92c 471 clk_disable(atmel_port->clk);
1e6c9c28
AV
472 break;
473 default:
7192f92c 474 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV
475 }
476}
477
478/*
479 * Change the port parameters
480 */
7192f92c 481static void atmel_set_termios(struct uart_port *port, struct termios * termios, struct termios * old)
1e6c9c28
AV
482{
483 unsigned long flags;
484 unsigned int mode, imr, quot, baud;
485
486 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
487 quot = uart_get_divisor(port, baud);
488
489 /* Get current mode register */
7192f92c 490 mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
1e6c9c28
AV
491
492 /* byte size */
493 switch (termios->c_cflag & CSIZE) {
494 case CS5:
7192f92c 495 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV
496 break;
497 case CS6:
7192f92c 498 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV
499 break;
500 case CS7:
7192f92c 501 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV
502 break;
503 default:
7192f92c 504 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV
505 break;
506 }
507
508 /* stop bits */
509 if (termios->c_cflag & CSTOPB)
7192f92c 510 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV
511
512 /* parity */
513 if (termios->c_cflag & PARENB) {
514 if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */
515 if (termios->c_cflag & PARODD)
7192f92c 516 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 517 else
7192f92c 518 mode |= ATMEL_US_PAR_SPACE;
1e6c9c28
AV
519 }
520 else if (termios->c_cflag & PARODD)
7192f92c 521 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 522 else
7192f92c 523 mode |= ATMEL_US_PAR_EVEN;
1e6c9c28
AV
524 }
525 else
7192f92c 526 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV
527
528 spin_lock_irqsave(&port->lock, flags);
529
7192f92c 530 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 531 if (termios->c_iflag & INPCK)
7192f92c 532 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 533 if (termios->c_iflag & (BRKINT | PARMRK))
7192f92c 534 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
535
536 /*
537 * Characters to ignore
538 */
539 port->ignore_status_mask = 0;
540 if (termios->c_iflag & IGNPAR)
7192f92c 541 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 542 if (termios->c_iflag & IGNBRK) {
7192f92c 543 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
544 /*
545 * If we're ignoring parity and break indicators,
546 * ignore overruns too (for real raw support).
547 */
548 if (termios->c_iflag & IGNPAR)
7192f92c 549 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28
AV
550 }
551
552 // TODO: Ignore all characters if CREAD is set.
553
554 /* update the per-port timeout */
555 uart_update_timeout(port, termios->c_cflag, baud);
556
557 /* disable interrupts and drain transmitter */
558 imr = UART_GET_IMR(port); /* get interrupt mask */
559 UART_PUT_IDR(port, -1); /* disable all interrupts */
7192f92c 560 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) { barrier(); }
1e6c9c28
AV
561
562 /* disable receiver and transmitter */
7192f92c 563 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28
AV
564
565 /* set the parity, stop bits and data size */
566 UART_PUT_MR(port, mode);
567
568 /* set the baud rate */
569 UART_PUT_BRGR(port, quot);
7192f92c
HS
570 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
571 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
572
573 /* restore interrupts */
574 UART_PUT_IER(port, imr);
575
576 /* CTS flow-control and modem-status interrupts */
577 if (UART_ENABLE_MS(port, termios->c_cflag))
578 port->ops->enable_ms(port);
579
580 spin_unlock_irqrestore(&port->lock, flags);
581}
582
583/*
584 * Return string describing the specified port
585 */
7192f92c 586static const char *atmel_type(struct uart_port *port)
1e6c9c28 587{
9ab4f88b 588 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV
589}
590
591/*
592 * Release the memory region(s) being used by 'port'.
593 */
7192f92c 594static void atmel_release_port(struct uart_port *port)
1e6c9c28 595{
afefc415
AV
596 struct platform_device *pdev = to_platform_device(port->dev);
597 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
598
599 release_mem_region(port->mapbase, size);
600
601 if (port->flags & UPF_IOREMAP) {
602 iounmap(port->membase);
603 port->membase = NULL;
604 }
1e6c9c28
AV
605}
606
607/*
608 * Request the memory region(s) being used by 'port'.
609 */
7192f92c 610static int atmel_request_port(struct uart_port *port)
1e6c9c28 611{
afefc415
AV
612 struct platform_device *pdev = to_platform_device(port->dev);
613 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
614
7192f92c 615 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV
616 return -EBUSY;
617
618 if (port->flags & UPF_IOREMAP) {
619 port->membase = ioremap(port->mapbase, size);
620 if (port->membase == NULL) {
621 release_mem_region(port->mapbase, size);
622 return -ENOMEM;
623 }
624 }
1e6c9c28 625
afefc415 626 return 0;
1e6c9c28
AV
627}
628
629/*
630 * Configure/autoconfigure the port.
631 */
7192f92c 632static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV
633{
634 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 635 port->type = PORT_ATMEL;
7192f92c 636 atmel_request_port(port);
1e6c9c28
AV
637 }
638}
639
640/*
641 * Verify the new serial_struct (for TIOCSSERIAL).
642 */
7192f92c 643static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV
644{
645 int ret = 0;
9ab4f88b 646 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV
647 ret = -EINVAL;
648 if (port->irq != ser->irq)
649 ret = -EINVAL;
650 if (ser->io_type != SERIAL_IO_MEM)
651 ret = -EINVAL;
652 if (port->uartclk / 16 != ser->baud_base)
653 ret = -EINVAL;
654 if ((void *)port->mapbase != ser->iomem_base)
655 ret = -EINVAL;
656 if (port->iobase != ser->port)
657 ret = -EINVAL;
658 if (ser->hub6 != 0)
659 ret = -EINVAL;
660 return ret;
661}
662
7192f92c
HS
663static struct uart_ops atmel_pops = {
664 .tx_empty = atmel_tx_empty,
665 .set_mctrl = atmel_set_mctrl,
666 .get_mctrl = atmel_get_mctrl,
667 .stop_tx = atmel_stop_tx,
668 .start_tx = atmel_start_tx,
669 .stop_rx = atmel_stop_rx,
670 .enable_ms = atmel_enable_ms,
671 .break_ctl = atmel_break_ctl,
672 .startup = atmel_startup,
673 .shutdown = atmel_shutdown,
674 .set_termios = atmel_set_termios,
675 .type = atmel_type,
676 .release_port = atmel_release_port,
677 .request_port = atmel_request_port,
678 .config_port = atmel_config_port,
679 .verify_port = atmel_verify_port,
680 .pm = atmel_serial_pm,
1e6c9c28
AV
681};
682
afefc415
AV
683/*
684 * Configure the port from the platform device resource info.
685 */
7192f92c 686static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct platform_device *pdev)
1e6c9c28 687{
7192f92c 688 struct uart_port *port = &atmel_port->uart;
73e2798b 689 struct atmel_uart_data *data = pdev->dev.platform_data;
afefc415
AV
690
691 port->iotype = UPIO_MEM;
692 port->flags = UPF_BOOT_AUTOCONF;
7192f92c 693 port->ops = &atmel_pops;
afefc415
AV
694 port->fifosize = 1;
695 port->line = pdev->id;
696 port->dev = &pdev->dev;
697
698 port->mapbase = pdev->resource[0].start;
699 port->irq = pdev->resource[1].start;
700
75d35213
HS
701 if (data->regs)
702 /* Already mapped by setup code */
703 port->membase = data->regs;
afefc415
AV
704 else {
705 port->flags |= UPF_IOREMAP;
706 port->membase = NULL;
707 }
1e6c9c28 708
7192f92c
HS
709 if (!atmel_port->clk) { /* for console, the clock could already be configured */
710 atmel_port->clk = clk_get(&pdev->dev, "usart");
711 clk_enable(atmel_port->clk);
712 port->uartclk = clk_get_rate(atmel_port->clk);
afefc415 713 }
1e6c9c28
AV
714}
715
afefc415
AV
716/*
717 * Register board-specific modem-control line handlers.
718 */
71f2e2b8 719void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1e6c9c28
AV
720{
721 if (fns->enable_ms)
7192f92c 722 atmel_pops.enable_ms = fns->enable_ms;
1e6c9c28 723 if (fns->get_mctrl)
7192f92c 724 atmel_pops.get_mctrl = fns->get_mctrl;
1e6c9c28 725 if (fns->set_mctrl)
7192f92c 726 atmel_pops.set_mctrl = fns->set_mctrl;
71f2e2b8
HS
727 atmel_open_hook = fns->open;
728 atmel_close_hook = fns->close;
7192f92c
HS
729 atmel_pops.pm = fns->pm;
730 atmel_pops.set_wake = fns->set_wake;
1e6c9c28
AV
731}
732
1e6c9c28 733
749c4e60 734#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 735static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 736{
7192f92c 737 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
d358788f
RK
738 barrier();
739 UART_PUT_CHAR(port, ch);
740}
1e6c9c28
AV
741
742/*
743 * Interrupts are disabled on entering
744 */
7192f92c 745static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 746{
7192f92c 747 struct uart_port *port = &atmel_ports[co->index].uart;
d358788f 748 unsigned int status, imr;
1e6c9c28
AV
749
750 /*
751 * First, save IMR and then disable interrupts
752 */
753 imr = UART_GET_IMR(port); /* get interrupt mask */
7192f92c 754 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
1e6c9c28 755
7192f92c 756 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV
757
758 /*
759 * Finally, wait for transmitter to become empty
760 * and restore IMR
761 */
762 do {
763 status = UART_GET_CSR(port);
7192f92c 764 } while (!(status & ATMEL_US_TXRDY));
1e6c9c28
AV
765 UART_PUT_IER(port, imr); /* set interrupts back the way they were */
766}
767
768/*
769 * If the port was already initialised (eg, by a boot loader), try to determine
770 * the current setup.
771 */
7192f92c 772static void __init atmel_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
1e6c9c28
AV
773{
774 unsigned int mr, quot;
775
776// TODO: CR is a write-only register
777// unsigned int cr;
778//
7192f92c
HS
779// cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN);
780// if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) {
1e6c9c28
AV
781// /* ok, the port was enabled */
782// }
783
7192f92c
HS
784 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
785 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV
786 *bits = 8;
787 else
788 *bits = 7;
789
7192f92c
HS
790 mr = UART_GET_MR(port) & ATMEL_US_PAR;
791 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 792 *parity = 'e';
7192f92c 793 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV
794 *parity = 'o';
795
4d5e392c
HS
796 /*
797 * The serial core only rounds down when matching this to a
798 * supported baud rate. Make sure we don't end up slightly
799 * lower than one of those, as it would make us fall through
800 * to a much lower baud rate than we really want.
801 */
1e6c9c28 802 quot = UART_GET_BRGR(port);
4d5e392c 803 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV
804}
805
7192f92c 806static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 807{
7192f92c 808 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV
809 int baud = 115200;
810 int bits = 8;
811 int parity = 'n';
812 int flow = 'n';
813
afefc415
AV
814 if (port->membase == 0) /* Port not initialized yet - delay setup */
815 return -ENODEV;
1e6c9c28 816
1e6c9c28 817 UART_PUT_IDR(port, -1); /* disable interrupts */
7192f92c
HS
818 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
819 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
820
821 if (options)
822 uart_parse_options(options, &baud, &parity, &bits, &flow);
823 else
7192f92c 824 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV
825
826 return uart_set_options(port, co, baud, parity, bits, flow);
827}
828
7192f92c 829static struct uart_driver atmel_uart;
1e6c9c28 830
7192f92c
HS
831static struct console atmel_console = {
832 .name = ATMEL_DEVICENAME,
833 .write = atmel_console_write,
1e6c9c28 834 .device = uart_console_device,
7192f92c 835 .setup = atmel_console_setup,
1e6c9c28
AV
836 .flags = CON_PRINTBUFFER,
837 .index = -1,
7192f92c 838 .data = &atmel_uart,
1e6c9c28
AV
839};
840
7192f92c 841#define ATMEL_CONSOLE_DEVICE &atmel_console
1e6c9c28 842
afefc415
AV
843/*
844 * Early console initialization (before VM subsystem initialized).
845 */
7192f92c 846static int __init atmel_console_init(void)
1e6c9c28 847{
73e2798b 848 if (atmel_default_console_device) {
7192f92c
HS
849 add_preferred_console(ATMEL_DEVICENAME, atmel_default_console_device->id, NULL);
850 atmel_init_port(&(atmel_ports[atmel_default_console_device->id]), atmel_default_console_device);
851 register_console(&atmel_console);
afefc415 852 }
1e6c9c28 853
1e6c9c28
AV
854 return 0;
855}
7192f92c 856console_initcall(atmel_console_init);
1e6c9c28 857
afefc415
AV
858/*
859 * Late console initialization.
860 */
7192f92c 861static int __init atmel_late_console_init(void)
afefc415 862{
7192f92c
HS
863 if (atmel_default_console_device && !(atmel_console.flags & CON_ENABLED))
864 register_console(&atmel_console);
afefc415
AV
865
866 return 0;
867}
7192f92c 868core_initcall(atmel_late_console_init);
afefc415 869
1e6c9c28 870#else
7192f92c 871#define ATMEL_CONSOLE_DEVICE NULL
1e6c9c28
AV
872#endif
873
7192f92c 874static struct uart_driver atmel_uart = {
1e6c9c28 875 .owner = THIS_MODULE,
7192f92c
HS
876 .driver_name = "atmel_serial",
877 .dev_name = ATMEL_DEVICENAME,
878 .major = SERIAL_ATMEL_MAJOR,
1e6c9c28 879 .minor = MINOR_START,
73e2798b 880 .nr = ATMEL_MAX_UART,
7192f92c 881 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV
882};
883
afefc415 884#ifdef CONFIG_PM
7192f92c 885static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state)
1e6c9c28 886{
afefc415 887 struct uart_port *port = platform_get_drvdata(pdev);
7192f92c 888 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415
AV
889
890 if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
891 enable_irq_wake(port->irq);
892 else {
893 disable_irq_wake(port->irq);
7192f92c
HS
894 uart_suspend_port(&atmel_uart, port);
895 atmel_port->suspended = 1;
afefc415 896 }
1e6c9c28 897
afefc415
AV
898 return 0;
899}
1e6c9c28 900
7192f92c 901static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV
902{
903 struct uart_port *port = platform_get_drvdata(pdev);
7192f92c 904 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
1e6c9c28 905
7192f92c
HS
906 if (atmel_port->suspended) {
907 uart_resume_port(&atmel_uart, port);
908 atmel_port->suspended = 0;
1e6c9c28
AV
909 }
910
911 return 0;
912}
afefc415 913#else
7192f92c
HS
914#define atmel_serial_suspend NULL
915#define atmel_serial_resume NULL
afefc415 916#endif
1e6c9c28 917
7192f92c 918static int __devinit atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 919{
7192f92c 920 struct atmel_uart_port *port;
afefc415 921 int ret;
1e6c9c28 922
7192f92c
HS
923 port = &atmel_ports[pdev->id];
924 atmel_init_port(port, pdev);
1e6c9c28 925
7192f92c 926 ret = uart_add_one_port(&atmel_uart, &port->uart);
afefc415
AV
927 if (!ret) {
928 device_init_wakeup(&pdev->dev, 1);
929 platform_set_drvdata(pdev, port);
930 }
931
932 return ret;
933}
934
7192f92c 935static int __devexit atmel_serial_remove(struct platform_device *pdev)
afefc415
AV
936{
937 struct uart_port *port = platform_get_drvdata(pdev);
7192f92c 938 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415
AV
939 int ret = 0;
940
7192f92c
HS
941 clk_disable(atmel_port->clk);
942 clk_put(atmel_port->clk);
afefc415
AV
943
944 device_init_wakeup(&pdev->dev, 0);
945 platform_set_drvdata(pdev, NULL);
946
947 if (port) {
7192f92c 948 ret = uart_remove_one_port(&atmel_uart, port);
afefc415
AV
949 kfree(port);
950 }
951
952 return ret;
953}
954
7192f92c
HS
955static struct platform_driver atmel_serial_driver = {
956 .probe = atmel_serial_probe,
957 .remove = __devexit_p(atmel_serial_remove),
958 .suspend = atmel_serial_suspend,
959 .resume = atmel_serial_resume,
afefc415 960 .driver = {
1e8ea802 961 .name = "atmel_usart",
afefc415
AV
962 .owner = THIS_MODULE,
963 },
964};
965
7192f92c 966static int __init atmel_serial_init(void)
afefc415
AV
967{
968 int ret;
969
7192f92c 970 ret = uart_register_driver(&atmel_uart);
afefc415
AV
971 if (ret)
972 return ret;
973
7192f92c 974 ret = platform_driver_register(&atmel_serial_driver);
afefc415 975 if (ret)
7192f92c 976 uart_unregister_driver(&atmel_uart);
afefc415
AV
977
978 return ret;
979}
980
7192f92c 981static void __exit atmel_serial_exit(void)
afefc415 982{
7192f92c
HS
983 platform_driver_unregister(&atmel_serial_driver);
984 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV
985}
986
7192f92c
HS
987module_init(atmel_serial_init);
988module_exit(atmel_serial_exit);
1e6c9c28
AV
989
990MODULE_AUTHOR("Rick Bronson");
7192f92c 991MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 992MODULE_LICENSE("GPL");