]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/serial/atmel_serial.c
[ARM] 4151/1: AT91 / AVR32: Move at91_pdc.h to linux/atmel_pdc.h
[mirror_ubuntu-artful-kernel.git] / drivers / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
c2f5ccfb 2 * linux/drivers/char/atmel_serial.c
1e6c9c28 3 *
7192f92c 4 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV
5 * Copyright (C) 2003 Rick Bronson
6 *
7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV
25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
afefc415 31#include <linux/clk.h>
1e6c9c28
AV
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
afefc415 35#include <linux/platform_device.h>
93a3ddc2 36#include <linux/atmel_pdc.h>
1e6c9c28
AV
37
38#include <asm/io.h>
39
afefc415 40#include <asm/mach/serial_at91.h>
1e6c9c28 41#include <asm/arch/board.h>
93a3ddc2 42
acca9b83 43#ifdef CONFIG_ARM
c2f5ccfb 44#include <asm/arch/cpu.h>
20e65276 45#include <asm/arch/gpio.h>
acca9b83 46#endif
1e6c9c28 47
5b34821a
HS
48#include "atmel_serial.h"
49
749c4e60 50#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV
51#define SUPPORT_SYSRQ
52#endif
53
54#include <linux/serial_core.h>
55
749c4e60 56#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV
57
58/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
59 * should coexist with the 8250 driver, such as if we have an external 16C550
60 * UART. */
7192f92c 61#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 62#define MINOR_START 154
7192f92c 63#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV
64
65#else
66
67/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
68 * name, but it is legally reserved for the 8250 driver. */
7192f92c 69#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 70#define MINOR_START 64
7192f92c 71#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV
72
73#endif
74
7192f92c 75#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 76
7192f92c
HS
77#define UART_PUT_CR(port,v) writel(v, (port)->membase + ATMEL_US_CR)
78#define UART_GET_MR(port) readl((port)->membase + ATMEL_US_MR)
79#define UART_PUT_MR(port,v) writel(v, (port)->membase + ATMEL_US_MR)
80#define UART_PUT_IER(port,v) writel(v, (port)->membase + ATMEL_US_IER)
81#define UART_PUT_IDR(port,v) writel(v, (port)->membase + ATMEL_US_IDR)
82#define UART_GET_IMR(port) readl((port)->membase + ATMEL_US_IMR)
83#define UART_GET_CSR(port) readl((port)->membase + ATMEL_US_CSR)
84#define UART_GET_CHAR(port) readl((port)->membase + ATMEL_US_RHR)
85#define UART_PUT_CHAR(port,v) writel(v, (port)->membase + ATMEL_US_THR)
86#define UART_GET_BRGR(port) readl((port)->membase + ATMEL_US_BRGR)
87#define UART_PUT_BRGR(port,v) writel(v, (port)->membase + ATMEL_US_BRGR)
88#define UART_PUT_RTOR(port,v) writel(v, (port)->membase + ATMEL_US_RTOR)
1e6c9c28 89
7192f92c 90// #define UART_GET_CR(port) readl((port)->membase + ATMEL_US_CR) // is write-only
1e6c9c28
AV
91
92 /* PDC registers */
7192f92c
HS
93#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + ATMEL_PDC_PTCR)
94#define UART_GET_PTSR(port) readl((port)->membase + ATMEL_PDC_PTSR)
afefc415 95
7192f92c
HS
96#define UART_PUT_RPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RPR)
97#define UART_GET_RPR(port) readl((port)->membase + ATMEL_PDC_RPR)
98#define UART_PUT_RCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RCR)
99#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNPR)
100#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNCR)
1e6c9c28 101
7192f92c
HS
102#define UART_PUT_TPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TPR)
103#define UART_PUT_TCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TCR)
104//#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNPR)
105//#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNCR)
1e6c9c28 106
71f2e2b8
HS
107static int (*atmel_open_hook)(struct uart_port *);
108static void (*atmel_close_hook)(struct uart_port *);
1e6c9c28 109
afefc415
AV
110/*
111 * We wrap our port structure around the generic uart_port.
112 */
7192f92c 113struct atmel_uart_port {
afefc415
AV
114 struct uart_port uart; /* uart */
115 struct clk *clk; /* uart clock */
116 unsigned short suspended; /* is port suspended? */
117};
118
7192f92c 119static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
afefc415 120
1e6c9c28 121#ifdef SUPPORT_SYSRQ
7192f92c 122static struct console atmel_console;
1e6c9c28
AV
123#endif
124
125/*
126 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
127 */
7192f92c 128static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 129{
7192f92c 130 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV
131}
132
133/*
134 * Set state of the modem control output lines
135 */
7192f92c 136static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV
137{
138 unsigned int control = 0;
afefc415 139 unsigned int mode;
1e6c9c28 140
c2f5ccfb 141#ifdef CONFIG_ARCH_AT91RM9200
79da7a61 142 if (cpu_is_at91rm9200()) {
afefc415
AV
143 /*
144 * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
145 * We need to drive the pin manually.
146 */
72729910 147 if (port->mapbase == AT91RM9200_BASE_US0) {
afefc415 148 if (mctrl & TIOCM_RTS)
20e65276 149 at91_set_gpio_value(AT91_PIN_PA21, 0);
afefc415 150 else
20e65276 151 at91_set_gpio_value(AT91_PIN_PA21, 1);
afefc415 152 }
1e6c9c28 153 }
acca9b83 154#endif
1e6c9c28
AV
155
156 if (mctrl & TIOCM_RTS)
7192f92c 157 control |= ATMEL_US_RTSEN;
1e6c9c28 158 else
7192f92c 159 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV
160
161 if (mctrl & TIOCM_DTR)
7192f92c 162 control |= ATMEL_US_DTREN;
1e6c9c28 163 else
7192f92c 164 control |= ATMEL_US_DTRDIS;
1e6c9c28 165
afefc415
AV
166 UART_PUT_CR(port, control);
167
168 /* Local loopback mode? */
7192f92c 169 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 170 if (mctrl & TIOCM_LOOP)
7192f92c 171 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 172 else
7192f92c 173 mode |= ATMEL_US_CHMODE_NORMAL;
afefc415 174 UART_PUT_MR(port, mode);
1e6c9c28
AV
175}
176
177/*
178 * Get state of the modem control input lines
179 */
7192f92c 180static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28
AV
181{
182 unsigned int status, ret = 0;
183
184 status = UART_GET_CSR(port);
185
186 /*
187 * The control signals are active low.
188 */
7192f92c 189 if (!(status & ATMEL_US_DCD))
1e6c9c28 190 ret |= TIOCM_CD;
7192f92c 191 if (!(status & ATMEL_US_CTS))
1e6c9c28 192 ret |= TIOCM_CTS;
7192f92c 193 if (!(status & ATMEL_US_DSR))
1e6c9c28 194 ret |= TIOCM_DSR;
7192f92c 195 if (!(status & ATMEL_US_RI))
1e6c9c28
AV
196 ret |= TIOCM_RI;
197
198 return ret;
199}
200
201/*
202 * Stop transmitting.
203 */
7192f92c 204static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 205{
7192f92c 206 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 207
7192f92c 208 UART_PUT_IDR(port, ATMEL_US_TXRDY);
1e6c9c28
AV
209}
210
211/*
212 * Start transmitting.
213 */
7192f92c 214static void atmel_start_tx(struct uart_port *port)
1e6c9c28 215{
7192f92c 216 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 217
7192f92c 218 UART_PUT_IER(port, ATMEL_US_TXRDY);
1e6c9c28
AV
219}
220
221/*
222 * Stop receiving - port is in process of being closed.
223 */
7192f92c 224static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 225{
7192f92c 226 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 227
7192f92c 228 UART_PUT_IDR(port, ATMEL_US_RXRDY);
1e6c9c28
AV
229}
230
231/*
232 * Enable modem status interrupts
233 */
7192f92c 234static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 235{
7192f92c 236 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
1e6c9c28
AV
237}
238
239/*
240 * Control the transmission of a break signal
241 */
7192f92c 242static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV
243{
244 if (break_state != 0)
7192f92c 245 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 246 else
7192f92c 247 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV
248}
249
250/*
251 * Characters received (called from interrupt handler)
252 */
7d12e780 253static void atmel_rx_chars(struct uart_port *port)
1e6c9c28
AV
254{
255 struct tty_struct *tty = port->info->tty;
256 unsigned int status, ch, flg;
257
afefc415 258 status = UART_GET_CSR(port);
7192f92c 259 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV
260 ch = UART_GET_CHAR(port);
261
1e6c9c28
AV
262 port->icount.rx++;
263
264 flg = TTY_NORMAL;
265
266 /*
267 * note that the error handling code is
268 * out of the main execution path
269 */
7192f92c
HS
270 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
271 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */
272 if (status & ATMEL_US_RXBRK) {
273 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
afefc415
AV
274 port->icount.brk++;
275 if (uart_handle_break(port))
276 goto ignore_char;
277 }
7192f92c 278 if (status & ATMEL_US_PARE)
1e6c9c28 279 port->icount.parity++;
7192f92c 280 if (status & ATMEL_US_FRAME)
1e6c9c28 281 port->icount.frame++;
7192f92c 282 if (status & ATMEL_US_OVRE)
1e6c9c28
AV
283 port->icount.overrun++;
284
afefc415
AV
285 status &= port->read_status_mask;
286
7192f92c 287 if (status & ATMEL_US_RXBRK)
afefc415 288 flg = TTY_BREAK;
7192f92c 289 else if (status & ATMEL_US_PARE)
1e6c9c28 290 flg = TTY_PARITY;
7192f92c 291 else if (status & ATMEL_US_FRAME)
1e6c9c28 292 flg = TTY_FRAME;
1e6c9c28
AV
293 }
294
7d12e780 295 if (uart_handle_sysrq_char(port, ch))
1e6c9c28
AV
296 goto ignore_char;
297
7192f92c 298 uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg);
1e6c9c28
AV
299
300 ignore_char:
afefc415 301 status = UART_GET_CSR(port);
1e6c9c28
AV
302 }
303
304 tty_flip_buffer_push(tty);
305}
306
307/*
308 * Transmit characters (called from interrupt handler)
309 */
7192f92c 310static void atmel_tx_chars(struct uart_port *port)
1e6c9c28
AV
311{
312 struct circ_buf *xmit = &port->info->xmit;
313
314 if (port->x_char) {
315 UART_PUT_CHAR(port, port->x_char);
316 port->icount.tx++;
317 port->x_char = 0;
318 return;
319 }
320 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
7192f92c 321 atmel_stop_tx(port);
1e6c9c28
AV
322 return;
323 }
324
7192f92c 325 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
1e6c9c28
AV
326 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
327 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
328 port->icount.tx++;
329 if (uart_circ_empty(xmit))
330 break;
331 }
332
333 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
334 uart_write_wakeup(port);
335
336 if (uart_circ_empty(xmit))
7192f92c 337 atmel_stop_tx(port);
1e6c9c28
AV
338}
339
340/*
341 * Interrupt handler
342 */
7d12e780 343static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV
344{
345 struct uart_port *port = dev_id;
7192f92c 346 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
1e6c9c28
AV
347 unsigned int status, pending, pass_counter = 0;
348
349 status = UART_GET_CSR(port);
afefc415
AV
350 pending = status & UART_GET_IMR(port);
351 while (pending) {
352 /* Interrupt receive */
7192f92c 353 if (pending & ATMEL_US_RXRDY)
7d12e780 354 atmel_rx_chars(port);
afefc415
AV
355
356 // TODO: All reads to CSR will clear these interrupts!
7192f92c
HS
357 if (pending & ATMEL_US_RIIC) port->icount.rng++;
358 if (pending & ATMEL_US_DSRIC) port->icount.dsr++;
359 if (pending & ATMEL_US_DCDIC)
360 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
361 if (pending & ATMEL_US_CTSIC)
362 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
363 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
afefc415
AV
364 wake_up_interruptible(&port->info->delta_msr_wait);
365
366 /* Interrupt transmit */
7192f92c
HS
367 if (pending & ATMEL_US_TXRDY)
368 atmel_tx_chars(port);
afefc415 369
7192f92c 370 if (pass_counter++ > ATMEL_ISR_PASS_LIMIT)
afefc415 371 break;
1e6c9c28 372
afefc415
AV
373 status = UART_GET_CSR(port);
374 pending = status & UART_GET_IMR(port);
1e6c9c28
AV
375 }
376 return IRQ_HANDLED;
377}
378
379/*
380 * Perform initialization and enable port for reception
381 */
7192f92c 382static int atmel_startup(struct uart_port *port)
1e6c9c28 383{
7192f92c 384 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
1e6c9c28
AV
385 int retval;
386
387 /*
388 * Ensure that no interrupts are enabled otherwise when
389 * request_irq() is called we could get stuck trying to
390 * handle an unexpected interrupt
391 */
392 UART_PUT_IDR(port, -1);
393
394 /*
395 * Allocate the IRQ
396 */
7192f92c 397 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, "atmel_serial", port);
1e6c9c28 398 if (retval) {
7192f92c 399 printk("atmel_serial: atmel_startup - Can't get irq\n");
1e6c9c28
AV
400 return retval;
401 }
402
403 /*
404 * If there is a specific "open" function (to register
405 * control line interrupts)
406 */
71f2e2b8
HS
407 if (atmel_open_hook) {
408 retval = atmel_open_hook(port);
1e6c9c28
AV
409 if (retval) {
410 free_irq(port->irq, port);
411 return retval;
412 }
413 }
414
1e6c9c28
AV
415 /*
416 * Finally, enable the serial port
417 */
7192f92c
HS
418 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
419 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */
afefc415 420
7192f92c 421 UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
afefc415 422
1e6c9c28
AV
423 return 0;
424}
425
426/*
427 * Disable the port
428 */
7192f92c 429static void atmel_shutdown(struct uart_port *port)
1e6c9c28 430{
7192f92c 431 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 432
1e6c9c28
AV
433 /*
434 * Disable all interrupts, port and break condition.
435 */
7192f92c 436 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1e6c9c28
AV
437 UART_PUT_IDR(port, -1);
438
439 /*
440 * Free the interrupt
441 */
442 free_irq(port->irq, port);
443
444 /*
445 * If there is a specific "close" function (to unregister
446 * control line interrupts)
447 */
71f2e2b8
HS
448 if (atmel_close_hook)
449 atmel_close_hook(port);
1e6c9c28
AV
450}
451
452/*
453 * Power / Clock management.
454 */
7192f92c 455static void atmel_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
1e6c9c28 456{
7192f92c 457 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415 458
1e6c9c28
AV
459 switch (state) {
460 case 0:
461 /*
462 * Enable the peripheral clock for this serial port.
463 * This is called on uart_open() or a resume event.
464 */
7192f92c 465 clk_enable(atmel_port->clk);
1e6c9c28
AV
466 break;
467 case 3:
468 /*
469 * Disable the peripheral clock for this serial port.
470 * This is called on uart_close() or a suspend event.
471 */
7192f92c 472 clk_disable(atmel_port->clk);
1e6c9c28
AV
473 break;
474 default:
7192f92c 475 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV
476 }
477}
478
479/*
480 * Change the port parameters
481 */
606d099c 482static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old)
1e6c9c28
AV
483{
484 unsigned long flags;
485 unsigned int mode, imr, quot, baud;
486
487 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
488 quot = uart_get_divisor(port, baud);
489
490 /* Get current mode register */
7192f92c 491 mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
1e6c9c28
AV
492
493 /* byte size */
494 switch (termios->c_cflag & CSIZE) {
495 case CS5:
7192f92c 496 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV
497 break;
498 case CS6:
7192f92c 499 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV
500 break;
501 case CS7:
7192f92c 502 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV
503 break;
504 default:
7192f92c 505 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV
506 break;
507 }
508
509 /* stop bits */
510 if (termios->c_cflag & CSTOPB)
7192f92c 511 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV
512
513 /* parity */
514 if (termios->c_cflag & PARENB) {
515 if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */
516 if (termios->c_cflag & PARODD)
7192f92c 517 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 518 else
7192f92c 519 mode |= ATMEL_US_PAR_SPACE;
1e6c9c28
AV
520 }
521 else if (termios->c_cflag & PARODD)
7192f92c 522 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 523 else
7192f92c 524 mode |= ATMEL_US_PAR_EVEN;
1e6c9c28
AV
525 }
526 else
7192f92c 527 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV
528
529 spin_lock_irqsave(&port->lock, flags);
530
7192f92c 531 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 532 if (termios->c_iflag & INPCK)
7192f92c 533 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 534 if (termios->c_iflag & (BRKINT | PARMRK))
7192f92c 535 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
536
537 /*
538 * Characters to ignore
539 */
540 port->ignore_status_mask = 0;
541 if (termios->c_iflag & IGNPAR)
7192f92c 542 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 543 if (termios->c_iflag & IGNBRK) {
7192f92c 544 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV
545 /*
546 * If we're ignoring parity and break indicators,
547 * ignore overruns too (for real raw support).
548 */
549 if (termios->c_iflag & IGNPAR)
7192f92c 550 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28
AV
551 }
552
553 // TODO: Ignore all characters if CREAD is set.
554
555 /* update the per-port timeout */
556 uart_update_timeout(port, termios->c_cflag, baud);
557
558 /* disable interrupts and drain transmitter */
559 imr = UART_GET_IMR(port); /* get interrupt mask */
560 UART_PUT_IDR(port, -1); /* disable all interrupts */
7192f92c 561 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) { barrier(); }
1e6c9c28
AV
562
563 /* disable receiver and transmitter */
7192f92c 564 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28
AV
565
566 /* set the parity, stop bits and data size */
567 UART_PUT_MR(port, mode);
568
569 /* set the baud rate */
570 UART_PUT_BRGR(port, quot);
7192f92c
HS
571 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
572 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
573
574 /* restore interrupts */
575 UART_PUT_IER(port, imr);
576
577 /* CTS flow-control and modem-status interrupts */
578 if (UART_ENABLE_MS(port, termios->c_cflag))
579 port->ops->enable_ms(port);
580
581 spin_unlock_irqrestore(&port->lock, flags);
582}
583
584/*
585 * Return string describing the specified port
586 */
7192f92c 587static const char *atmel_type(struct uart_port *port)
1e6c9c28 588{
9ab4f88b 589 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV
590}
591
592/*
593 * Release the memory region(s) being used by 'port'.
594 */
7192f92c 595static void atmel_release_port(struct uart_port *port)
1e6c9c28 596{
afefc415
AV
597 struct platform_device *pdev = to_platform_device(port->dev);
598 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
599
600 release_mem_region(port->mapbase, size);
601
602 if (port->flags & UPF_IOREMAP) {
603 iounmap(port->membase);
604 port->membase = NULL;
605 }
1e6c9c28
AV
606}
607
608/*
609 * Request the memory region(s) being used by 'port'.
610 */
7192f92c 611static int atmel_request_port(struct uart_port *port)
1e6c9c28 612{
afefc415
AV
613 struct platform_device *pdev = to_platform_device(port->dev);
614 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
615
7192f92c 616 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV
617 return -EBUSY;
618
619 if (port->flags & UPF_IOREMAP) {
620 port->membase = ioremap(port->mapbase, size);
621 if (port->membase == NULL) {
622 release_mem_region(port->mapbase, size);
623 return -ENOMEM;
624 }
625 }
1e6c9c28 626
afefc415 627 return 0;
1e6c9c28
AV
628}
629
630/*
631 * Configure/autoconfigure the port.
632 */
7192f92c 633static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV
634{
635 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 636 port->type = PORT_ATMEL;
7192f92c 637 atmel_request_port(port);
1e6c9c28
AV
638 }
639}
640
641/*
642 * Verify the new serial_struct (for TIOCSSERIAL).
643 */
7192f92c 644static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV
645{
646 int ret = 0;
9ab4f88b 647 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV
648 ret = -EINVAL;
649 if (port->irq != ser->irq)
650 ret = -EINVAL;
651 if (ser->io_type != SERIAL_IO_MEM)
652 ret = -EINVAL;
653 if (port->uartclk / 16 != ser->baud_base)
654 ret = -EINVAL;
655 if ((void *)port->mapbase != ser->iomem_base)
656 ret = -EINVAL;
657 if (port->iobase != ser->port)
658 ret = -EINVAL;
659 if (ser->hub6 != 0)
660 ret = -EINVAL;
661 return ret;
662}
663
7192f92c
HS
664static struct uart_ops atmel_pops = {
665 .tx_empty = atmel_tx_empty,
666 .set_mctrl = atmel_set_mctrl,
667 .get_mctrl = atmel_get_mctrl,
668 .stop_tx = atmel_stop_tx,
669 .start_tx = atmel_start_tx,
670 .stop_rx = atmel_stop_rx,
671 .enable_ms = atmel_enable_ms,
672 .break_ctl = atmel_break_ctl,
673 .startup = atmel_startup,
674 .shutdown = atmel_shutdown,
675 .set_termios = atmel_set_termios,
676 .type = atmel_type,
677 .release_port = atmel_release_port,
678 .request_port = atmel_request_port,
679 .config_port = atmel_config_port,
680 .verify_port = atmel_verify_port,
681 .pm = atmel_serial_pm,
1e6c9c28
AV
682};
683
afefc415
AV
684/*
685 * Configure the port from the platform device resource info.
686 */
7192f92c 687static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct platform_device *pdev)
1e6c9c28 688{
7192f92c 689 struct uart_port *port = &atmel_port->uart;
73e2798b 690 struct atmel_uart_data *data = pdev->dev.platform_data;
afefc415
AV
691
692 port->iotype = UPIO_MEM;
a14d5273 693 port->flags = UPF_BOOT_AUTOCONF;
7192f92c 694 port->ops = &atmel_pops;
a14d5273 695 port->fifosize = 1;
afefc415
AV
696 port->line = pdev->id;
697 port->dev = &pdev->dev;
698
699 port->mapbase = pdev->resource[0].start;
700 port->irq = pdev->resource[1].start;
701
75d35213
HS
702 if (data->regs)
703 /* Already mapped by setup code */
704 port->membase = data->regs;
afefc415
AV
705 else {
706 port->flags |= UPF_IOREMAP;
707 port->membase = NULL;
708 }
1e6c9c28 709
7192f92c
HS
710 if (!atmel_port->clk) { /* for console, the clock could already be configured */
711 atmel_port->clk = clk_get(&pdev->dev, "usart");
712 clk_enable(atmel_port->clk);
713 port->uartclk = clk_get_rate(atmel_port->clk);
afefc415 714 }
1e6c9c28
AV
715}
716
afefc415
AV
717/*
718 * Register board-specific modem-control line handlers.
719 */
71f2e2b8 720void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1e6c9c28
AV
721{
722 if (fns->enable_ms)
7192f92c 723 atmel_pops.enable_ms = fns->enable_ms;
1e6c9c28 724 if (fns->get_mctrl)
7192f92c 725 atmel_pops.get_mctrl = fns->get_mctrl;
1e6c9c28 726 if (fns->set_mctrl)
7192f92c 727 atmel_pops.set_mctrl = fns->set_mctrl;
71f2e2b8
HS
728 atmel_open_hook = fns->open;
729 atmel_close_hook = fns->close;
7192f92c
HS
730 atmel_pops.pm = fns->pm;
731 atmel_pops.set_wake = fns->set_wake;
1e6c9c28
AV
732}
733
1e6c9c28 734
749c4e60 735#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 736static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 737{
7192f92c 738 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
d358788f
RK
739 barrier();
740 UART_PUT_CHAR(port, ch);
741}
1e6c9c28
AV
742
743/*
744 * Interrupts are disabled on entering
745 */
7192f92c 746static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 747{
7192f92c 748 struct uart_port *port = &atmel_ports[co->index].uart;
d358788f 749 unsigned int status, imr;
1e6c9c28
AV
750
751 /*
752 * First, save IMR and then disable interrupts
753 */
754 imr = UART_GET_IMR(port); /* get interrupt mask */
7192f92c 755 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
1e6c9c28 756
7192f92c 757 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV
758
759 /*
760 * Finally, wait for transmitter to become empty
761 * and restore IMR
762 */
763 do {
764 status = UART_GET_CSR(port);
7192f92c 765 } while (!(status & ATMEL_US_TXRDY));
1e6c9c28
AV
766 UART_PUT_IER(port, imr); /* set interrupts back the way they were */
767}
768
769/*
770 * If the port was already initialised (eg, by a boot loader), try to determine
771 * the current setup.
772 */
7192f92c 773static void __init atmel_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
1e6c9c28
AV
774{
775 unsigned int mr, quot;
776
777// TODO: CR is a write-only register
778// unsigned int cr;
779//
7192f92c
HS
780// cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN);
781// if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) {
1e6c9c28
AV
782// /* ok, the port was enabled */
783// }
784
7192f92c
HS
785 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
786 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV
787 *bits = 8;
788 else
789 *bits = 7;
790
7192f92c
HS
791 mr = UART_GET_MR(port) & ATMEL_US_PAR;
792 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 793 *parity = 'e';
7192f92c 794 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV
795 *parity = 'o';
796
4d5e392c
HS
797 /*
798 * The serial core only rounds down when matching this to a
799 * supported baud rate. Make sure we don't end up slightly
800 * lower than one of those, as it would make us fall through
801 * to a much lower baud rate than we really want.
802 */
1e6c9c28 803 quot = UART_GET_BRGR(port);
4d5e392c 804 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV
805}
806
7192f92c 807static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 808{
7192f92c 809 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV
810 int baud = 115200;
811 int bits = 8;
812 int parity = 'n';
813 int flow = 'n';
814
afefc415
AV
815 if (port->membase == 0) /* Port not initialized yet - delay setup */
816 return -ENODEV;
1e6c9c28 817
1e6c9c28 818 UART_PUT_IDR(port, -1); /* disable interrupts */
7192f92c
HS
819 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
820 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV
821
822 if (options)
823 uart_parse_options(options, &baud, &parity, &bits, &flow);
824 else
7192f92c 825 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV
826
827 return uart_set_options(port, co, baud, parity, bits, flow);
828}
829
7192f92c 830static struct uart_driver atmel_uart;
1e6c9c28 831
7192f92c
HS
832static struct console atmel_console = {
833 .name = ATMEL_DEVICENAME,
834 .write = atmel_console_write,
1e6c9c28 835 .device = uart_console_device,
7192f92c 836 .setup = atmel_console_setup,
1e6c9c28
AV
837 .flags = CON_PRINTBUFFER,
838 .index = -1,
7192f92c 839 .data = &atmel_uart,
1e6c9c28
AV
840};
841
7192f92c 842#define ATMEL_CONSOLE_DEVICE &atmel_console
1e6c9c28 843
afefc415
AV
844/*
845 * Early console initialization (before VM subsystem initialized).
846 */
7192f92c 847static int __init atmel_console_init(void)
1e6c9c28 848{
73e2798b 849 if (atmel_default_console_device) {
7192f92c
HS
850 add_preferred_console(ATMEL_DEVICENAME, atmel_default_console_device->id, NULL);
851 atmel_init_port(&(atmel_ports[atmel_default_console_device->id]), atmel_default_console_device);
852 register_console(&atmel_console);
afefc415 853 }
1e6c9c28 854
1e6c9c28
AV
855 return 0;
856}
7192f92c 857console_initcall(atmel_console_init);
1e6c9c28 858
afefc415
AV
859/*
860 * Late console initialization.
861 */
7192f92c 862static int __init atmel_late_console_init(void)
afefc415 863{
7192f92c
HS
864 if (atmel_default_console_device && !(atmel_console.flags & CON_ENABLED))
865 register_console(&atmel_console);
afefc415
AV
866
867 return 0;
868}
7192f92c 869core_initcall(atmel_late_console_init);
afefc415 870
1e6c9c28 871#else
7192f92c 872#define ATMEL_CONSOLE_DEVICE NULL
1e6c9c28
AV
873#endif
874
7192f92c 875static struct uart_driver atmel_uart = {
1e6c9c28 876 .owner = THIS_MODULE,
7192f92c
HS
877 .driver_name = "atmel_serial",
878 .dev_name = ATMEL_DEVICENAME,
879 .major = SERIAL_ATMEL_MAJOR,
1e6c9c28 880 .minor = MINOR_START,
73e2798b 881 .nr = ATMEL_MAX_UART,
7192f92c 882 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV
883};
884
afefc415 885#ifdef CONFIG_PM
7192f92c 886static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state)
1e6c9c28 887{
afefc415 888 struct uart_port *port = platform_get_drvdata(pdev);
7192f92c 889 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415
AV
890
891 if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
892 enable_irq_wake(port->irq);
893 else {
7192f92c
HS
894 uart_suspend_port(&atmel_uart, port);
895 atmel_port->suspended = 1;
afefc415 896 }
1e6c9c28 897
afefc415
AV
898 return 0;
899}
1e6c9c28 900
7192f92c 901static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV
902{
903 struct uart_port *port = platform_get_drvdata(pdev);
7192f92c 904 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
1e6c9c28 905
7192f92c
HS
906 if (atmel_port->suspended) {
907 uart_resume_port(&atmel_uart, port);
908 atmel_port->suspended = 0;
1e6c9c28 909 }
9b938166
AV
910 else
911 disable_irq_wake(port->irq);
1e6c9c28
AV
912
913 return 0;
914}
afefc415 915#else
7192f92c
HS
916#define atmel_serial_suspend NULL
917#define atmel_serial_resume NULL
afefc415 918#endif
1e6c9c28 919
7192f92c 920static int __devinit atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 921{
7192f92c 922 struct atmel_uart_port *port;
afefc415 923 int ret;
1e6c9c28 924
7192f92c
HS
925 port = &atmel_ports[pdev->id];
926 atmel_init_port(port, pdev);
1e6c9c28 927
7192f92c 928 ret = uart_add_one_port(&atmel_uart, &port->uart);
afefc415
AV
929 if (!ret) {
930 device_init_wakeup(&pdev->dev, 1);
931 platform_set_drvdata(pdev, port);
932 }
933
934 return ret;
935}
936
7192f92c 937static int __devexit atmel_serial_remove(struct platform_device *pdev)
afefc415
AV
938{
939 struct uart_port *port = platform_get_drvdata(pdev);
7192f92c 940 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
afefc415
AV
941 int ret = 0;
942
7192f92c
HS
943 clk_disable(atmel_port->clk);
944 clk_put(atmel_port->clk);
afefc415
AV
945
946 device_init_wakeup(&pdev->dev, 0);
947 platform_set_drvdata(pdev, NULL);
948
949 if (port) {
7192f92c 950 ret = uart_remove_one_port(&atmel_uart, port);
afefc415
AV
951 kfree(port);
952 }
953
954 return ret;
955}
956
7192f92c
HS
957static struct platform_driver atmel_serial_driver = {
958 .probe = atmel_serial_probe,
959 .remove = __devexit_p(atmel_serial_remove),
960 .suspend = atmel_serial_suspend,
961 .resume = atmel_serial_resume,
afefc415 962 .driver = {
1e8ea802 963 .name = "atmel_usart",
afefc415
AV
964 .owner = THIS_MODULE,
965 },
966};
967
7192f92c 968static int __init atmel_serial_init(void)
afefc415
AV
969{
970 int ret;
971
7192f92c 972 ret = uart_register_driver(&atmel_uart);
afefc415
AV
973 if (ret)
974 return ret;
975
7192f92c 976 ret = platform_driver_register(&atmel_serial_driver);
afefc415 977 if (ret)
7192f92c 978 uart_unregister_driver(&atmel_uart);
afefc415
AV
979
980 return ret;
981}
982
7192f92c 983static void __exit atmel_serial_exit(void)
afefc415 984{
7192f92c
HS
985 platform_driver_unregister(&atmel_serial_driver);
986 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV
987}
988
7192f92c
HS
989module_init(atmel_serial_init);
990module_exit(atmel_serial_exit);
1e6c9c28
AV
991
992MODULE_AUTHOR("Rick Bronson");
7192f92c 993MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 994MODULE_LICENSE("GPL");