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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / serial / bfin_5xx.c
CommitLineData
194de561 1/*
1ba7a3ee 2 * Blackfin On-Chip Serial Driver
194de561 3 *
d273e201 4 * Copyright 2006-2008 Analog Devices Inc.
194de561 5 *
1ba7a3ee 6 * Enter bugs at http://blackfin.uclinux.org/
194de561 7 *
1ba7a3ee 8 * Licensed under the GPL-2 or later.
194de561
BW		 9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
20#include <linux/platform_device.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24
52e15f0e
SZ		 25#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
26 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
474f1a66
SZ		 27#include <linux/kgdb.h>
28#include <asm/irq_regs.h>
29#endif
30
194de561 31#include <asm/gpio.h>
639f6571 32#include <mach/bfin_serial_5xx.h>
194de561
BW		 33
34#ifdef CONFIG_SERIAL_BFIN_DMA
35#include <linux/dma-mapping.h>
36#include <asm/io.h>
37#include <asm/irq.h>
38#include <asm/cacheflush.h>
39#endif
40
41/* UART name and device definitions */
42#define BFIN_SERIAL_NAME "ttyBF"
43#define BFIN_SERIAL_MAJOR 204
44#define BFIN_SERIAL_MINOR 64
45
c9607ecc
MF		 46static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
47static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
48
52e15f0e
SZ		 49#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
50 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
51
52# ifndef CONFIG_SERIAL_BFIN_PIO
53# error KGDB only support UART in PIO mode.
54# endif
55
56static int kgdboc_port_line;
57static int kgdboc_break_enabled;
58#endif
194de561
BW		 59/*
60 * Setup for console. Argument comes from the menuconfig
61 */
62#define DMA_RX_XCOUNT 512
63#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
64
0aef4564 65#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
194de561
BW		 66
67#ifdef CONFIG_SERIAL_BFIN_DMA
68static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
69#else
194de561 70static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
BW		 71#endif
72
80d5c474
GY		 73static void bfin_serial_reset_irda(struct uart_port *port);
74
d307d36a
SZ		 75#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
76 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
77static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
78{
79 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
80 if (uart->cts_pin < 0)
81 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
82
83 /* CTS PIN is negative assertive. */
84 if (UART_GET_CTS(uart))
85 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
86 else
87 return TIOCM_DSR | TIOCM_CAR;
88}
89
90static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
91{
92 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
93 if (uart->rts_pin < 0)
94 return;
95
96 /* RTS PIN is negative assertive. */
97 if (mctrl & TIOCM_RTS)
98 UART_ENABLE_RTS(uart);
99 else
100 UART_DISABLE_RTS(uart);
101}
102
103/*
104 * Handle any change of modem status signal.
105 */
106static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
107{
108 struct bfin_serial_port *uart = dev_id;
109 unsigned int status;
110
111 status = bfin_serial_get_mctrl(&uart->port);
112 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
113#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
114 uart->scts = 1;
115 UART_CLEAR_SCTS(uart);
116 UART_CLEAR_IER(uart, EDSSI);
117#endif
118
119 return IRQ_HANDLED;
120}
121#else
122static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
123{
124 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
125}
126
127static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
128{
129}
130#endif
131
194de561
BW		 132/*
133 * interrupts are disabled on entry
134 */
135static void bfin_serial_stop_tx(struct uart_port *port)
136{
137 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
68a784cb 138#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857 139 struct circ_buf *xmit = &uart->port.info->xmit;
68a784cb 140#endif
194de561 141
f4d640c9 142 while (!(UART_GET_LSR(uart) & TEMT))
0711d857 143 cpu_relax();
f4d640c9 144
194de561
BW		 145#ifdef CONFIG_SERIAL_BFIN_DMA
146 disable_dma(uart->tx_dma_channel);
0711d857
SZ		 147 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
148 uart->port.icount.tx += uart->tx_count;
149 uart->tx_count = 0;
150 uart->tx_done = 1;
f4d640c9
RH		 151#else
152#ifdef CONFIG_BF54x
f4d640c9
RH		 153 /* Clear TFI bit */
154 UART_PUT_LSR(uart, TFI);
194de561 155#endif
89bf6dc5 156 UART_CLEAR_IER(uart, ETBEI);
f4d640c9 157#endif
194de561
BW		 158}
159
160/*
161 * port is locked and interrupts are disabled
162 */
163static void bfin_serial_start_tx(struct uart_port *port)
164{
165 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
80d5c474
GY		 166 struct tty_struct *tty = uart->port.info->port.tty;
167
d307d36a
SZ		 168#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
169 if (uart->scts && (!bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
170 uart->scts = 0;
171 uart_handle_cts_change(&uart->port, uart->scts);
172 }
173#endif
174
80d5c474
GY		 175 /*
176 * To avoid losting RX interrupt, we reset IR function
177 * before sending data.
178 */
179 if (tty->termios->c_line == N_IRDA)
180 bfin_serial_reset_irda(port);
194de561
BW		 181
182#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857
SZ		 183 if (uart->tx_done)
184 bfin_serial_dma_tx_chars(uart);
f4d640c9 185#else
f4d640c9 186 UART_SET_IER(uart, ETBEI);
a359cca7 187 bfin_serial_tx_chars(uart);
f4d640c9 188#endif
194de561
BW		 189}
190
191/*
192 * Interrupts are enabled
193 */
194static void bfin_serial_stop_rx(struct uart_port *port)
195{
196 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
52e15f0e 197
f4d640c9 198 UART_CLEAR_IER(uart, ERBFI);
194de561
BW		 199}
200
201/*
202 * Set the modem control timer to fire immediately.
203 */
204static void bfin_serial_enable_ms(struct uart_port *port)
205{
206}
207
474f1a66 208
50e2e15a 209#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
8851c71e
MF		 210# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
211# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
212#else
213# define UART_GET_ANOMALY_THRESHOLD(uart) 0
214# define UART_SET_ANOMALY_THRESHOLD(uart, v)
215#endif
216
194de561 217#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
BW		 218static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
219{
52e15f0e 220 struct tty_struct *tty = NULL;
194de561 221 unsigned int status, ch, flg;
8851c71e 222 static struct timeval anomaly_start = { .tv_sec = 0 };
194de561 223
759eb040 224 status = UART_GET_LSR(uart);
0bcfd70e
MF		 225 UART_CLEAR_LSR(uart);
226
227 ch = UART_GET_CHAR(uart);
194de561
BW		 228 uart->port.icount.rx++;
229
52e15f0e
SZ		 230#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
231 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
232 if (kgdb_connected && kgdboc_port_line == uart->port.line)
233 if (ch == 0x3) {/* Ctrl + C */
234 kgdb_breakpoint();
474f1a66 235 return;
474f1a66 236 }
52e15f0e 237
df04baf1 238 if (!uart->port.info || !uart->port.info->port.tty)
52e15f0e 239 return;
474f1a66 240#endif
df04baf1 241 tty = uart->port.info->port.tty;
bbf275f0 242
50e2e15a 243 if (ANOMALY_05000363) {
8851c71e
MF		 244 /* The BF533 (and BF561) family of processors have a nice anomaly
245 * where they continuously generate characters for a "single" break.
bbf275f0 246 * We have to basically ignore this flood until the "next" valid
8851c71e
MF		 247 * character comes across. Due to the nature of the flood, it is
248 * not possible to reliably catch bytes that are sent too quickly
249 * after this break. So application code talking to the Blackfin
250 * which sends a break signal must allow at least 1.5 character
251 * times after the end of the break for things to stabilize. This
252 * timeout was picked as it must absolutely be larger than 1
253 * character time +/- some percent. So 1.5 sounds good. All other
254 * Blackfin families operate properly. Woo.
bbf275f0 255 */
8851c71e
MF		 256 if (anomaly_start.tv_sec) {
257 struct timeval curr;
258 suseconds_t usecs;
259
260 if ((~ch & (~ch + 1)) & 0xff)
261 goto known_good_char;
262
263 do_gettimeofday(&curr);
264 if (curr.tv_sec - anomaly_start.tv_sec > 1)
265 goto known_good_char;
266
267 usecs = 0;
268 if (curr.tv_sec != anomaly_start.tv_sec)
269 usecs += USEC_PER_SEC;
270 usecs += curr.tv_usec - anomaly_start.tv_usec;
271
272 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
273 goto known_good_char;
274
275 if (ch)
276 anomaly_start.tv_sec = 0;
277 else
278 anomaly_start = curr;
279
280 return;
281
282 known_good_char:
e482a237 283 status &= ~BI;
8851c71e 284 anomaly_start.tv_sec = 0;
bbf275f0 285 }
194de561 286 }
194de561
BW		 287
288 if (status & BI) {
50e2e15a 289 if (ANOMALY_05000363)
8851c71e
MF		 290 if (bfin_revid() < 5)
291 do_gettimeofday(&anomaly_start);
194de561
BW		 292 uart->port.icount.brk++;
293 if (uart_handle_break(&uart->port))
294 goto ignore_char;
9808901b 295 status &= ~(PE | FE);
2ac5ee47
MF		 296 }
297 if (status & PE)
194de561 298 uart->port.icount.parity++;
2ac5ee47 299 if (status & OE)
194de561 300 uart->port.icount.overrun++;
2ac5ee47 301 if (status & FE)
194de561 302 uart->port.icount.frame++;
2ac5ee47
MF		 303
304 status &= uart->port.read_status_mask;
305
306 if (status & BI)
307 flg = TTY_BREAK;
308 else if (status & PE)
309 flg = TTY_PARITY;
310 else if (status & FE)
311 flg = TTY_FRAME;
312 else
194de561
BW		 313 flg = TTY_NORMAL;
314
315 if (uart_handle_sysrq_char(&uart->port, ch))
316 goto ignore_char;
194de561 317
2ac5ee47
MF		 318 uart_insert_char(&uart->port, status, OE, ch, flg);
319
320 ignore_char:
321 tty_flip_buffer_push(tty);
194de561
BW		 322}
323
324static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
325{
326 struct circ_buf *xmit = &uart->port.info->xmit;
327
194de561 328 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
5ffdeea2
SZ		 329#ifdef CONFIG_BF54x
330 /* Clear TFI bit */
331 UART_PUT_LSR(uart, TFI);
332#endif
333 UART_CLEAR_IER(uart, ETBEI);
194de561
BW		 334 return;
335 }
336
f30ac0ce
SZ		 337 if (uart->port.x_char) {
338 UART_PUT_CHAR(uart, uart->port.x_char);
339 uart->port.icount.tx++;
340 uart->port.x_char = 0;
341 }
342
759eb040
SZ		 343 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
344 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
345 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
346 uart->port.icount.tx++;
347 SSYNC();
348 }
194de561
BW		 349
350 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
351 uart_write_wakeup(&uart->port);
194de561
BW		 352}
353
5c4e472b
AL		 354static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
355{
356 struct bfin_serial_port *uart = dev_id;
357
f4d640c9 358 spin_lock(&uart->port.lock);
0bcfd70e 359 while (UART_GET_LSR(uart) & DR)
f4d640c9 360 bfin_serial_rx_chars(uart);
f4d640c9 361 spin_unlock(&uart->port.lock);
759eb040 362
5c4e472b
AL		 363 return IRQ_HANDLED;
364}
365
366static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW		 367{
368 struct bfin_serial_port *uart = dev_id;
194de561 369
d307d36a
SZ		 370#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
371 if (uart->scts && (!bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
372 uart->scts = 0;
373 uart_handle_cts_change(&uart->port, uart->scts);
374 }
375#endif
f4d640c9 376 spin_lock(&uart->port.lock);
0bcfd70e 377 if (UART_GET_LSR(uart) & THRE)
f4d640c9 378 bfin_serial_tx_chars(uart);
f4d640c9 379 spin_unlock(&uart->port.lock);
759eb040 380
194de561
BW		 381 return IRQ_HANDLED;
382}
4cb4f22b 383#endif
194de561 384
194de561
BW		 385#ifdef CONFIG_SERIAL_BFIN_DMA
386static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
387{
388 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 389
194de561
BW		 390 uart->tx_done = 0;
391
1b73351c 392 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
0711d857 393 uart->tx_count = 0;
1b73351c
SZ		 394 uart->tx_done = 1;
395 return;
396 }
397
194de561
BW		 398 if (uart->port.x_char) {
399 UART_PUT_CHAR(uart, uart->port.x_char);
400 uart->port.icount.tx++;
401 uart->port.x_char = 0;
194de561 402 }
1b73351c 403
194de561
BW		 404 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
405 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
406 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
407 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
408 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
409 set_dma_config(uart->tx_dma_channel,
410 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
411 INTR_ON_BUF,
412 DIMENSION_LINEAR,
2047e40d
MH		 413 DATA_SIZE_8,
414 DMA_SYNC_RESTART));
194de561
BW		 415 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
416 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
417 set_dma_x_modify(uart->tx_dma_channel, 1);
418 enable_dma(uart->tx_dma_channel);
99ee7b5f 419
f4d640c9 420 UART_SET_IER(uart, ETBEI);
194de561
BW		 421}
422
2ac5ee47 423static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561 424{
a88487c7 425 struct tty_struct *tty = uart->port.info->port.tty;
194de561
BW		 426 int i, flg, status;
427
428 status = UART_GET_LSR(uart);
0bcfd70e
MF		 429 UART_CLEAR_LSR(uart);
430
56f5de8f
SZ		 431 uart->port.icount.rx +=
432 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
433 UART_XMIT_SIZE);
194de561
BW		 434
435 if (status & BI) {
436 uart->port.icount.brk++;
437 if (uart_handle_break(&uart->port))
438 goto dma_ignore_char;
9808901b 439 status &= ~(PE | FE);
2ac5ee47
MF		 440 }
441 if (status & PE)
194de561 442 uart->port.icount.parity++;
2ac5ee47 443 if (status & OE)
194de561 444 uart->port.icount.overrun++;
2ac5ee47 445 if (status & FE)
194de561 446 uart->port.icount.frame++;
2ac5ee47
MF		 447
448 status &= uart->port.read_status_mask;
449
450 if (status & BI)
451 flg = TTY_BREAK;
452 else if (status & PE)
453 flg = TTY_PARITY;
454 else if (status & FE)
455 flg = TTY_FRAME;
456 else
194de561
BW		 457 flg = TTY_NORMAL;
458
8c4210e3 459 for (i = uart->rx_dma_buf.tail; ; i++) {
56f5de8f
SZ		 460 if (i >= UART_XMIT_SIZE)
461 i = 0;
8c4210e3
SZ		 462 if (i == uart->rx_dma_buf.head)
463 break;
56f5de8f
SZ		 464 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
465 uart_insert_char(&uart->port, status, OE,
466 uart->rx_dma_buf.buf[i], flg);
194de561 467 }
2ac5ee47
MF		 468
469 dma_ignore_char:
194de561
BW		 470 tty_flip_buffer_push(tty);
471}
472
473void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
474{
59e4e3e6
MF		 475 int x_pos, pos;
476 unsigned long flags;
68a784cb
SZ		 477
478 spin_lock_irqsave(&uart->port.lock, flags);
194de561 479
56f5de8f
SZ		 480 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
481 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
482 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
483 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
484 uart->rx_dma_nrows = 0;
485 x_pos = DMA_RX_XCOUNT - x_pos;
194de561
BW		 486 if (x_pos == DMA_RX_XCOUNT)
487 x_pos = 0;
488
489 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
56f5de8f
SZ		 490 if (pos != uart->rx_dma_buf.tail) {
491 uart->rx_dma_buf.head = pos;
194de561 492 bfin_serial_dma_rx_chars(uart);
56f5de8f 493 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
194de561 494 }
0aef4564 495
68a784cb
SZ		 496 spin_unlock_irqrestore(&uart->port.lock, flags);
497
0a278423 498 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
194de561
BW		 499}
500
501static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
502{
503 struct bfin_serial_port *uart = dev_id;
504 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 505
d307d36a
SZ		 506#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
507 if (uart->scts && (!bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
508 uart->scts = 0;
509 uart_handle_cts_change(&uart->port, uart->scts);
510 }
511#endif
512
194de561
BW		 513 spin_lock(&uart->port.lock);
514 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
194de561 515 disable_dma(uart->tx_dma_channel);
0711d857 516 clear_dma_irqstat(uart->tx_dma_channel);
f4d640c9 517 UART_CLEAR_IER(uart, ETBEI);
0711d857
SZ		 518 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
519 uart->port.icount.tx += uart->tx_count;
1b73351c 520
56f5de8f
SZ		 521 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
522 uart_write_wakeup(&uart->port);
523
1b73351c 524 bfin_serial_dma_tx_chars(uart);
194de561
BW		 525 }
526
527 spin_unlock(&uart->port.lock);
528 return IRQ_HANDLED;
529}
530
531static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
532{
533 struct bfin_serial_port *uart = dev_id;
534 unsigned short irqstat;
0711d857 535
194de561
BW		 536 spin_lock(&uart->port.lock);
537 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
538 clear_dma_irqstat(uart->rx_dma_channel);
68a784cb 539 bfin_serial_dma_rx_chars(uart);
194de561 540 spin_unlock(&uart->port.lock);
0aef4564 541
194de561
BW		 542 return IRQ_HANDLED;
543}
544#endif
545
546/*
547 * Return TIOCSER_TEMT when transmitter is not busy.
548 */
549static unsigned int bfin_serial_tx_empty(struct uart_port *port)
550{
551 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
552 unsigned short lsr;
553
554 lsr = UART_GET_LSR(uart);
555 if (lsr & TEMT)
556 return TIOCSER_TEMT;
557 else
558 return 0;
559}
560
194de561
BW		 561static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
562{
cf686762
MF		 563 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
564 u16 lcr = UART_GET_LCR(uart);
565 if (break_state)
566 lcr |= SB;
567 else
568 lcr &= ~SB;
569 UART_PUT_LCR(uart, lcr);
570 SSYNC();
194de561
BW		 571}
572
573static int bfin_serial_startup(struct uart_port *port)
574{
575 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
576
577#ifdef CONFIG_SERIAL_BFIN_DMA
578 dma_addr_t dma_handle;
579
580 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
581 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
582 return -EBUSY;
583 }
584
585 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
586 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
587 free_dma(uart->rx_dma_channel);
588 return -EBUSY;
589 }
590
591 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
592 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
593
594 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
595 uart->rx_dma_buf.head = 0;
596 uart->rx_dma_buf.tail = 0;
597 uart->rx_dma_nrows = 0;
598
599 set_dma_config(uart->rx_dma_channel,
600 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
601 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH		 602 DATA_SIZE_8,
603 DMA_SYNC_RESTART));
194de561
BW		 604 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
605 set_dma_x_modify(uart->rx_dma_channel, 1);
606 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
607 set_dma_y_modify(uart->rx_dma_channel, 1);
608 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
609 enable_dma(uart->rx_dma_channel);
610
611 uart->rx_dma_timer.data = (unsigned long)(uart);
612 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
613 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
614 add_timer(&(uart->rx_dma_timer));
615#else
6f95570e 616# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52e15f0e
SZ		 617 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
618 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
619 kgdboc_break_enabled = 0;
620 else {
621# endif
a359cca7
SZ		 622 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
623 "BFIN_UART_RX", uart)) {
194de561
BW		 624 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
625 return -EBUSY;
626 }
627
628 if (request_irq
5c4e472b 629 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW		 630 "BFIN_UART_TX", uart)) {
631 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
632 free_irq(uart->port.irq, uart);
633 return -EBUSY;
634 }
ab2375f2
SZ		 635
636# ifdef CONFIG_BF54x
637 {
638 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
639
640 switch (uart->port.irq) {
641 case IRQ_UART3_RX:
642 uart_dma_ch_rx = CH_UART3_RX;
643 uart_dma_ch_tx = CH_UART3_TX;
644 break;
645 case IRQ_UART2_RX:
646 uart_dma_ch_rx = CH_UART2_RX;
647 uart_dma_ch_tx = CH_UART2_TX;
648 break;
649 default:
650 uart_dma_ch_rx = uart_dma_ch_tx = 0;
651 break;
652 };
653
654 if (uart_dma_ch_rx &&
655 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
656 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
657 free_irq(uart->port.irq, uart);
658 free_irq(uart->port.irq + 1, uart);
659 return -EBUSY;
660 }
661 if (uart_dma_ch_tx &&
662 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
663 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
664 free_dma(uart_dma_ch_rx);
665 free_irq(uart->port.irq, uart);
666 free_irq(uart->port.irq + 1, uart);
667 return -EBUSY;
668 }
669 }
670# endif
6f95570e 671# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52e15f0e
SZ		 672 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
673 }
674# endif
6f95570e
SZ		 675#endif
676
677#ifdef CONFIG_SERIAL_BFIN_CTSRTS
678 if (uart->cts_pin >= 0) {
679 if (request_irq(gpio_to_irq(uart->cts_pin),
680 bfin_serial_mctrl_cts_int,
681 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
682 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
683 uart->cts_pin = -1;
684 pr_info("Unable to attach BlackFin UART CTS interrupt.\
685 So, disable it.\n");
686 }
687 }
688 if (uart->rts_pin >= 0) {
689 gpio_request(uart->rts_pin, DRIVER_NAME);
690 gpio_direction_output(uart->rts_pin, 0);
691 }
194de561 692#endif
d307d36a
SZ		 693#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
694 if (request_irq(uart->status_irq,
695 bfin_serial_mctrl_cts_int,
696 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
697 pr_info("Unable to attach BlackFin UART Modem \
698 Status interrupt.\n");
699 }
700
701 if (uart->cts_pin >= 0) {
702 gpio_request(uart->cts_pin, DRIVER_NAME);
703 gpio_direction_output(uart->cts_pin, 1);
704 }
705 if (uart->rts_pin >= 0) {
706 gpio_request(uart->rts_pin, DRIVER_NAME);
707 gpio_direction_output(uart->rts_pin, 0);
708 }
709
710 /* CTS RTS PINs are negative assertive. */
711 UART_PUT_MCR(uart, ACTS);
712 UART_SET_IER(uart, EDSSI);
713#endif
714
f4d640c9 715 UART_SET_IER(uart, ERBFI);
194de561
BW		 716 return 0;
717}
718
719static void bfin_serial_shutdown(struct uart_port *port)
720{
721 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
722
723#ifdef CONFIG_SERIAL_BFIN_DMA
724 disable_dma(uart->tx_dma_channel);
725 free_dma(uart->tx_dma_channel);
726 disable_dma(uart->rx_dma_channel);
727 free_dma(uart->rx_dma_channel);
728 del_timer(&(uart->rx_dma_timer));
75b780bd 729 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 730#else
ab2375f2
SZ		 731#ifdef CONFIG_BF54x
732 switch (uart->port.irq) {
733 case IRQ_UART3_RX:
734 free_dma(CH_UART3_RX);
735 free_dma(CH_UART3_TX);
736 break;
737 case IRQ_UART2_RX:
738 free_dma(CH_UART2_RX);
739 free_dma(CH_UART2_TX);
740 break;
741 default:
742 break;
743 };
474f1a66 744#endif
194de561
BW		 745 free_irq(uart->port.irq, uart);
746 free_irq(uart->port.irq+1, uart);
747#endif
6f95570e 748
d307d36a 749#ifdef CONFIG_SERIAL_BFIN_CTSRTS
6f95570e
SZ		 750 if (uart->cts_pin >= 0)
751 free_irq(gpio_to_irq(uart->cts_pin), uart);
752 if (uart->rts_pin >= 0)
753 gpio_free(uart->rts_pin);
d307d36a
SZ		 754#endif
755#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
756 if (uart->cts_pin >= 0)
757 gpio_free(uart->cts_pin);
758 if (uart->rts_pin >= 0)
759 gpio_free(uart->rts_pin);
760 if (UART_GET_IER(uart) && EDSSI)
761 free_irq(uart->status_irq, uart);
762#endif
194de561
BW		 763}
764
765static void
766bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
767 struct ktermios *old)
768{
769 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
770 unsigned long flags;
771 unsigned int baud, quot;
0c44a86d 772 unsigned short val, ier, lcr = 0;
194de561
BW		 773
774 switch (termios->c_cflag & CSIZE) {
775 case CS8:
776 lcr = WLS(8);
777 break;
778 case CS7:
779 lcr = WLS(7);
780 break;
781 case CS6:
782 lcr = WLS(6);
783 break;
784 case CS5:
785 lcr = WLS(5);
786 break;
787 default:
788 printk(KERN_ERR "%s: word lengh not supported\n",
71cc2c21 789 __func__);
194de561
BW		 790 }
791
792 if (termios->c_cflag & CSTOPB)
793 lcr |= STB;
19aa6382 794 if (termios->c_cflag & PARENB)
194de561 795 lcr |= PEN;
19aa6382
MF		 796 if (!(termios->c_cflag & PARODD))
797 lcr |= EPS;
798 if (termios->c_cflag & CMSPAR)
799 lcr |= STP;
194de561 800
2ac5ee47
MF		 801 port->read_status_mask = OE;
802 if (termios->c_iflag & INPCK)
803 port->read_status_mask |= (FE | PE);
804 if (termios->c_iflag & (BRKINT | PARMRK))
805 port->read_status_mask |= BI;
194de561 806
2ac5ee47
MF		 807 /*
808 * Characters to ignore
809 */
810 port->ignore_status_mask = 0;
811 if (termios->c_iflag & IGNPAR)
812 port->ignore_status_mask |= FE | PE;
813 if (termios->c_iflag & IGNBRK) {
814 port->ignore_status_mask |= BI;
815 /*
816 * If we're ignoring parity and break indicators,
817 * ignore overruns too (for real raw support).
818 */
819 if (termios->c_iflag & IGNPAR)
820 port->ignore_status_mask |= OE;
821 }
194de561
BW		 822
823 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
f4487101 824 quot = uart_get_divisor(port, baud) - ANOMALY_05000230;
194de561
BW		 825 spin_lock_irqsave(&uart->port.lock, flags);
826
8851c71e
MF		 827 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
828
194de561
BW		 829 /* Disable UART */
830 ier = UART_GET_IER(uart);
1feaa51d 831 UART_DISABLE_INTS(uart);
194de561
BW		 832
833 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 834 UART_SET_DLAB(uart);
194de561
BW		 835
836 UART_PUT_DLL(uart, quot & 0xFF);
194de561
BW		 837 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
838 SSYNC();
839
840 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 841 UART_CLEAR_DLAB(uart);
194de561
BW		 842
843 UART_PUT_LCR(uart, lcr);
844
845 /* Enable UART */
1feaa51d 846 UART_ENABLE_INTS(uart, ier);
194de561
BW		 847
848 val = UART_GET_GCTL(uart);
849 val |= UCEN;
850 UART_PUT_GCTL(uart, val);
851
b3ef5aba
GY		 852 /* Port speed changed, update the per-port timeout. */
853 uart_update_timeout(port, termios->c_cflag, baud);
854
194de561
BW		 855 spin_unlock_irqrestore(&uart->port.lock, flags);
856}
857
858static const char *bfin_serial_type(struct uart_port *port)
859{
860 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
861
862 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
863}
864
865/*
866 * Release the memory region(s) being used by 'port'.
867 */
868static void bfin_serial_release_port(struct uart_port *port)
869{
870}
871
872/*
873 * Request the memory region(s) being used by 'port'.
874 */
875static int bfin_serial_request_port(struct uart_port *port)
876{
877 return 0;
878}
879
880/*
881 * Configure/autoconfigure the port.
882 */
883static void bfin_serial_config_port(struct uart_port *port, int flags)
884{
885 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
886
887 if (flags & UART_CONFIG_TYPE &&
888 bfin_serial_request_port(&uart->port) == 0)
889 uart->port.type = PORT_BFIN;
890}
891
892/*
893 * Verify the new serial_struct (for TIOCSSERIAL).
894 * The only change we allow are to the flags and type, and
895 * even then only between PORT_BFIN and PORT_UNKNOWN
896 */
897static int
898bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
899{
900 return 0;
901}
902
7d01b475
GY		 903/*
904 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
905 * In other cases, disable IrDA function.
906 */
3b8458a9 907static void bfin_serial_set_ldisc(struct uart_port *port)
7d01b475 908{
3b8458a9 909 int line = port->line;
7d01b475
GY		 910 unsigned short val;
911
a88487c7 912 if (line >= port->info->port.tty->driver->num)
7d01b475
GY		 913 return;
914
b1cbefe5 915 switch (port->info->port.tty->termios->c_line) {
7d01b475
GY		 916 case N_IRDA:
917 val = UART_GET_GCTL(&bfin_serial_ports[line]);
918 val |= (IREN | RPOLC);
919 UART_PUT_GCTL(&bfin_serial_ports[line], val);
920 break;
921 default:
922 val = UART_GET_GCTL(&bfin_serial_ports[line]);
923 val &= ~(IREN | RPOLC);
924 UART_PUT_GCTL(&bfin_serial_ports[line], val);
925 }
926}
927
6f95570e
SZ		 928static void bfin_serial_reset_irda(struct uart_port *port)
929{
930 int line = port->line;
931 unsigned short val;
932
933 val = UART_GET_GCTL(&bfin_serial_ports[line]);
934 val &= ~(IREN | RPOLC);
935 UART_PUT_GCTL(&bfin_serial_ports[line], val);
936 SSYNC();
937 val |= (IREN | RPOLC);
938 UART_PUT_GCTL(&bfin_serial_ports[line], val);
939 SSYNC();
940}
941
52e15f0e
SZ		 942#ifdef CONFIG_CONSOLE_POLL
943static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
944{
945 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
946
947 while (!(UART_GET_LSR(uart) & THRE))
948 cpu_relax();
949
950 UART_CLEAR_DLAB(uart);
951 UART_PUT_CHAR(uart, (unsigned char)chr);
952}
953
954static int bfin_serial_poll_get_char(struct uart_port *port)
955{
956 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
957 unsigned char chr;
958
959 while (!(UART_GET_LSR(uart) & DR))
960 cpu_relax();
961
962 UART_CLEAR_DLAB(uart);
963 chr = UART_GET_CHAR(uart);
964
965 return chr;
966}
967#endif
968
969#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
970 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
971static void bfin_kgdboc_port_shutdown(struct uart_port *port)
972{
973 if (kgdboc_break_enabled) {
974 kgdboc_break_enabled = 0;
975 bfin_serial_shutdown(port);
976 }
977}
978
979static int bfin_kgdboc_port_startup(struct uart_port *port)
980{
981 kgdboc_port_line = port->line;
982 kgdboc_break_enabled = !bfin_serial_startup(port);
983 return 0;
984}
985#endif
986
194de561
BW		 987static struct uart_ops bfin_serial_pops = {
988 .tx_empty = bfin_serial_tx_empty,
989 .set_mctrl = bfin_serial_set_mctrl,
990 .get_mctrl = bfin_serial_get_mctrl,
991 .stop_tx = bfin_serial_stop_tx,
992 .start_tx = bfin_serial_start_tx,
993 .stop_rx = bfin_serial_stop_rx,
994 .enable_ms = bfin_serial_enable_ms,
995 .break_ctl = bfin_serial_break_ctl,
996 .startup = bfin_serial_startup,
997 .shutdown = bfin_serial_shutdown,
998 .set_termios = bfin_serial_set_termios,
3b8458a9 999 .set_ldisc = bfin_serial_set_ldisc,
194de561
BW		 1000 .type = bfin_serial_type,
1001 .release_port = bfin_serial_release_port,
1002 .request_port = bfin_serial_request_port,
1003 .config_port = bfin_serial_config_port,
1004 .verify_port = bfin_serial_verify_port,
52e15f0e
SZ		 1005#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1006 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1007 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1008 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1009#endif
1010#ifdef CONFIG_CONSOLE_POLL
1011 .poll_put_char = bfin_serial_poll_put_char,
1012 .poll_get_char = bfin_serial_poll_get_char,
1013#endif
194de561
BW		 1014};
1015
6f95570e
SZ		 1016static void __init bfin_serial_hw_init(void)
1017{
1018#ifdef CONFIG_SERIAL_BFIN_UART0
1019 peripheral_request(P_UART0_TX, DRIVER_NAME);
1020 peripheral_request(P_UART0_RX, DRIVER_NAME);
1021#endif
1022
1023#ifdef CONFIG_SERIAL_BFIN_UART1
1024 peripheral_request(P_UART1_TX, DRIVER_NAME);
1025 peripheral_request(P_UART1_RX, DRIVER_NAME);
1026
1027# if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1028 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1029 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1030# endif
1031#endif
1032
1033#ifdef CONFIG_SERIAL_BFIN_UART2
1034 peripheral_request(P_UART2_TX, DRIVER_NAME);
1035 peripheral_request(P_UART2_RX, DRIVER_NAME);
1036#endif
1037
1038#ifdef CONFIG_SERIAL_BFIN_UART3
1039 peripheral_request(P_UART3_TX, DRIVER_NAME);
1040 peripheral_request(P_UART3_RX, DRIVER_NAME);
1041
1042# if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1043 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1044 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1045# endif
1046#endif
1047}
1048
194de561
BW		 1049static void __init bfin_serial_init_ports(void)
1050{
1051 static int first = 1;
1052 int i;
1053
1054 if (!first)
1055 return;
1056 first = 0;
1057
6f95570e
SZ		 1058 bfin_serial_hw_init();
1059
c9607ecc 1060 for (i = 0; i < nr_active_ports; i++) {
194de561 1061 bfin_serial_ports[i].port.uartclk = get_sclk();
b3ef5aba 1062 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
194de561
BW		 1063 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
1064 bfin_serial_ports[i].port.line = i;
1065 bfin_serial_ports[i].port.iotype = UPIO_MEM;
1066 bfin_serial_ports[i].port.membase =
1067 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1068 bfin_serial_ports[i].port.mapbase =
1069 bfin_serial_resource[i].uart_base_addr;
1070 bfin_serial_ports[i].port.irq =
1071 bfin_serial_resource[i].uart_irq;
d307d36a
SZ		 1072 bfin_serial_ports[i].status_irq =
1073 bfin_serial_resource[i].uart_status_irq;
194de561
BW		 1074 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
1075#ifdef CONFIG_SERIAL_BFIN_DMA
1076 bfin_serial_ports[i].tx_done = 1;
1077 bfin_serial_ports[i].tx_count = 0;
1078 bfin_serial_ports[i].tx_dma_channel =
1079 bfin_serial_resource[i].uart_tx_dma_channel;
1080 bfin_serial_ports[i].rx_dma_channel =
1081 bfin_serial_resource[i].uart_rx_dma_channel;
1082 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
194de561 1083#endif
d307d36a
SZ		 1084#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1085 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
194de561
BW		 1086 bfin_serial_ports[i].cts_pin =
1087 bfin_serial_resource[i].uart_cts_pin;
1088 bfin_serial_ports[i].rts_pin =
1089 bfin_serial_resource[i].uart_rts_pin;
1090#endif
194de561
BW		 1091 }
1092}
1093
b6efa1ea 1094#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
194de561
BW		 1095/*
1096 * If the port was already initialised (eg, by a boot loader),
1097 * try to determine the current setup.
1098 */
1099static void __init
1100bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1101 int *parity, int *bits)
1102{
1103 unsigned short status;
1104
1105 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1106 if (status == (ERBFI | ETBEI)) {
1107 /* ok, the port was enabled */
45828b81 1108 u16 lcr, dlh, dll;
194de561
BW		 1109
1110 lcr = UART_GET_LCR(uart);
1111
1112 *parity = 'n';
1113 if (lcr & PEN) {
1114 if (lcr & EPS)
1115 *parity = 'e';
1116 else
1117 *parity = 'o';
1118 }
1119 switch (lcr & 0x03) {
1120 case 0: *bits = 5; break;
1121 case 1: *bits = 6; break;
1122 case 2: *bits = 7; break;
1123 case 3: *bits = 8; break;
1124 }
1125 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 1126 UART_SET_DLAB(uart);
194de561
BW		 1127
1128 dll = UART_GET_DLL(uart);
1129 dlh = UART_GET_DLH(uart);
1130
1131 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 1132 UART_CLEAR_DLAB(uart);
194de561
BW		 1133
1134 *baud = get_sclk() / (16*(dll | dlh << 8));
1135 }
71cc2c21 1136 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
194de561 1137}
0ae53640 1138
0ae53640 1139static struct uart_driver bfin_serial_reg;
194de561
BW		 1140
1141static int __init
1142bfin_serial_console_setup(struct console *co, char *options)
1143{
1144 struct bfin_serial_port *uart;
1145 int baud = 57600;
1146 int bits = 8;
1147 int parity = 'n';
d307d36a
SZ		 1148# if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1149 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
194de561 1150 int flow = 'r';
b6efa1ea 1151# else
194de561 1152 int flow = 'n';
0ae53640 1153# endif
194de561
BW		 1154
1155 /*
1156 * Check whether an invalid uart number has been specified, and
1157 * if so, search for the first available port that does have
1158 * console support.
1159 */
c9607ecc 1160 if (co->index == -1 || co->index >= nr_active_ports)
194de561
BW		 1161 co->index = 0;
1162 uart = &bfin_serial_ports[co->index];
1163
1164 if (options)
1165 uart_parse_options(options, &baud, &parity, &bits, &flow);
1166 else
1167 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1168
1169 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG		 1170}
1171#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1172 defined (CONFIG_EARLY_PRINTK) */
1173
1174#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1175static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1176{
1177 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1178 while (!(UART_GET_LSR(uart) & THRE))
1179 barrier();
1180 UART_PUT_CHAR(uart, ch);
1181 SSYNC();
1182}
1183
1184/*
1185 * Interrupts are disabled on entering
1186 */
1187static void
1188bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1189{
1190 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
59e4e3e6 1191 unsigned long flags;
0ae53640
RG		 1192
1193 spin_lock_irqsave(&uart->port.lock, flags);
1194 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1195 spin_unlock_irqrestore(&uart->port.lock, flags);
1196
194de561
BW		 1197}
1198
194de561
BW		 1199static struct console bfin_serial_console = {
1200 .name = BFIN_SERIAL_NAME,
1201 .write = bfin_serial_console_write,
1202 .device = uart_console_device,
1203 .setup = bfin_serial_console_setup,
1204 .flags = CON_PRINTBUFFER,
1205 .index = -1,
1206 .data = &bfin_serial_reg,
1207};
1208
1209static int __init bfin_serial_rs_console_init(void)
1210{
1211 bfin_serial_init_ports();
1212 register_console(&bfin_serial_console);
52e15f0e 1213
194de561
BW		 1214 return 0;
1215}
1216console_initcall(bfin_serial_rs_console_init);
1217
1218#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1219#else
1220#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG		 1221#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1222
1223
1224#ifdef CONFIG_EARLY_PRINTK
1225static __init void early_serial_putc(struct uart_port *port, int ch)
1226{
1227 unsigned timeout = 0xffff;
1228 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1229
1230 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1231 cpu_relax();
1232 UART_PUT_CHAR(uart, ch);
1233}
1234
1235static __init void early_serial_write(struct console *con, const char *s,
1236 unsigned int n)
1237{
1238 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1239 unsigned int i;
1240
1241 for (i = 0; i < n; i++, s++) {
1242 if (*s == '\n')
1243 early_serial_putc(&uart->port, '\r');
1244 early_serial_putc(&uart->port, *s);
1245 }
1246}
1247
c1113400 1248static struct __initdata console bfin_early_serial_console = {
0ae53640
RG		 1249 .name = "early_BFuart",
1250 .write = early_serial_write,
1251 .device = uart_console_device,
1252 .flags = CON_PRINTBUFFER,
1253 .setup = bfin_serial_console_setup,
1254 .index = -1,
1255 .data = &bfin_serial_reg,
1256};
1257
1258struct console __init *bfin_earlyserial_init(unsigned int port,
1259 unsigned int cflag)
1260{
1261 struct bfin_serial_port *uart;
1262 struct ktermios t;
1263
c9607ecc 1264 if (port == -1 || port >= nr_active_ports)
0ae53640
RG		 1265 port = 0;
1266 bfin_serial_init_ports();
1267 bfin_early_serial_console.index = port;
0ae53640
RG		 1268 uart = &bfin_serial_ports[port];
1269 t.c_cflag = cflag;
1270 t.c_iflag = 0;
1271 t.c_oflag = 0;
1272 t.c_lflag = ICANON;
1273 t.c_line = port;
1274 bfin_serial_set_termios(&uart->port, &t, &t);
1275 return &bfin_early_serial_console;
1276}
1277
b6efa1ea 1278#endif /* CONFIG_EARLY_PRINTK */
194de561
BW		 1279
1280static struct uart_driver bfin_serial_reg = {
1281 .owner = THIS_MODULE,
1282 .driver_name = "bfin-uart",
1283 .dev_name = BFIN_SERIAL_NAME,
1284 .major = BFIN_SERIAL_MAJOR,
1285 .minor = BFIN_SERIAL_MINOR,
2ade9729 1286 .nr = BFIN_UART_NR_PORTS,
194de561
BW		 1287 .cons = BFIN_SERIAL_CONSOLE,
1288};
1289
1290static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1291{
ccfbc3e1 1292 int i;
194de561 1293
c9607ecc 1294 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1295 if (bfin_serial_ports[i].port.dev != &dev->dev)
1296 continue;
1297 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1298 }
194de561
BW		 1299
1300 return 0;
1301}
1302
1303static int bfin_serial_resume(struct platform_device *dev)
1304{
ccfbc3e1 1305 int i;
194de561 1306
c9607ecc 1307 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1308 if (bfin_serial_ports[i].port.dev != &dev->dev)
1309 continue;
1310 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1311 }
194de561
BW		 1312
1313 return 0;
1314}
1315
1316static int bfin_serial_probe(struct platform_device *dev)
1317{
1318 struct resource *res = dev->resource;
1319 int i;
1320
1321 for (i = 0; i < dev->num_resources; i++, res++)
1322 if (res->flags & IORESOURCE_MEM)
1323 break;
1324
1325 if (i < dev->num_resources) {
c9607ecc 1326 for (i = 0; i < nr_active_ports; i++, res++) {
194de561
BW		 1327 if (bfin_serial_ports[i].port.mapbase != res->start)
1328 continue;
1329 bfin_serial_ports[i].port.dev = &dev->dev;
1330 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
194de561
BW		 1331 }
1332 }
1333
1334 return 0;
1335}
1336
ccfbc3e1 1337static int bfin_serial_remove(struct platform_device *dev)
194de561 1338{
ccfbc3e1 1339 int i;
194de561 1340
c9607ecc 1341 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1342 if (bfin_serial_ports[i].port.dev != &dev->dev)
1343 continue;
1344 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1345 bfin_serial_ports[i].port.dev = NULL;
d307d36a
SZ		 1346#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1347 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
ccfbc3e1
SZ		 1348 gpio_free(bfin_serial_ports[i].cts_pin);
1349 gpio_free(bfin_serial_ports[i].rts_pin);
194de561 1350#endif
ccfbc3e1 1351 }
194de561
BW		 1352
1353 return 0;
1354}
1355
1356static struct platform_driver bfin_serial_driver = {
1357 .probe = bfin_serial_probe,
1358 .remove = bfin_serial_remove,
1359 .suspend = bfin_serial_suspend,
1360 .resume = bfin_serial_resume,
1361 .driver = {
1362 .name = "bfin-uart",
e169c139 1363 .owner = THIS_MODULE,
194de561
BW		 1364 },
1365};
1366
1367static int __init bfin_serial_init(void)
1368{
1369 int ret;
1370
1371 pr_info("Serial: Blackfin serial driver\n");
1372
1373 bfin_serial_init_ports();
1374
1375 ret = uart_register_driver(&bfin_serial_reg);
1376 if (ret == 0) {
1377 ret = platform_driver_register(&bfin_serial_driver);
1378 if (ret) {
1379 pr_debug("uart register failed\n");
1380 uart_unregister_driver(&bfin_serial_reg);
1381 }
1382 }
1383 return ret;
1384}
1385
1386static void __exit bfin_serial_exit(void)
1387{
1388 platform_driver_unregister(&bfin_serial_driver);
1389 uart_unregister_driver(&bfin_serial_reg);
1390}
1391
52e15f0e 1392
194de561
BW		 1393module_init(bfin_serial_init);
1394module_exit(bfin_serial_exit);
1395
1396MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1397MODULE_DESCRIPTION("Blackfin generic serial port driver");
1398MODULE_LICENSE("GPL");
1399MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
e169c139 1400MODULE_ALIAS("platform:bfin-uart");
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