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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/cpm_uart.c | |
3 | * | |
4 | * Driver for CPM (SCC/SMC) serial ports; core driver | |
5 | * | |
6 | * Based on arch/ppc/cpm2_io/uart.c by Dan Malek | |
7 | * Based on ppc8xx.c by Thomas Gleixner | |
8 | * Based on drivers/serial/amba.c by Russell King | |
9 | * | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) |
1da177e4 | 11 | * Pantelis Antoniou (panto@intracom.gr) (CPM1) |
311c4627 | 12 | * |
1da177e4 LT |
13 | * Copyright (C) 2004 Freescale Semiconductor, Inc. |
14 | * (C) 2004 Intracom, S.A. | |
6e197696 VB |
15 | * (C) 2005-2006 MontaVista Software, Inc. |
16 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
32 | */ | |
33 | ||
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/tty.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/serial.h> | |
39 | #include <linux/console.h> | |
40 | #include <linux/sysrq.h> | |
41 | #include <linux/device.h> | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dma-mapping.h> | |
e27987cd | 44 | #include <linux/fs_uart_pd.h> |
1da177e4 LT |
45 | |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
48 | #include <asm/delay.h> | |
3dd0dcbe | 49 | #include <asm/fs_pd.h> |
1da177e4 LT |
50 | |
51 | #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
52 | #define SUPPORT_SYSRQ | |
53 | #endif | |
54 | ||
55 | #include <linux/serial_core.h> | |
56 | #include <linux/kernel.h> | |
57 | ||
58 | #include "cpm_uart.h" | |
59 | ||
60 | /***********************************************************************/ | |
61 | ||
62 | /* Track which ports are configured as uarts */ | |
63 | int cpm_uart_port_map[UART_NR]; | |
64 | /* How many ports did we config as uarts */ | |
e27987cd | 65 | int cpm_uart_nr = 0; |
1da177e4 LT |
66 | |
67 | /**************************************************************/ | |
68 | ||
69 | static int cpm_uart_tx_pump(struct uart_port *port); | |
70 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); | |
71 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); | |
72 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo); | |
73 | ||
74 | /**************************************************************/ | |
75 | ||
311c4627 | 76 | |
e27987cd VB |
77 | /* Place-holder for board-specific stuff */ |
78 | struct platform_device* __attribute__ ((weak)) __init | |
79 | early_uart_get_pdev(int index) | |
80 | { | |
81 | return NULL; | |
82 | } | |
83 | ||
84 | ||
6e197696 | 85 | static void cpm_uart_count(void) |
e27987cd VB |
86 | { |
87 | cpm_uart_nr = 0; | |
88 | #ifdef CONFIG_SERIAL_CPM_SMC1 | |
89 | cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1; | |
90 | #endif | |
91 | #ifdef CONFIG_SERIAL_CPM_SMC2 | |
92 | cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2; | |
93 | #endif | |
94 | #ifdef CONFIG_SERIAL_CPM_SCC1 | |
95 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1; | |
96 | #endif | |
97 | #ifdef CONFIG_SERIAL_CPM_SCC2 | |
98 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2; | |
99 | #endif | |
100 | #ifdef CONFIG_SERIAL_CPM_SCC3 | |
101 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3; | |
102 | #endif | |
103 | #ifdef CONFIG_SERIAL_CPM_SCC4 | |
104 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4; | |
105 | #endif | |
106 | } | |
107 | ||
6e197696 VB |
108 | /* Get UART number by its id */ |
109 | static int cpm_uart_id2nr(int id) | |
110 | { | |
111 | int i; | |
112 | if (id < UART_NR) { | |
113 | for (i=0; i<UART_NR; i++) { | |
114 | if (cpm_uart_port_map[i] == id) | |
115 | return i; | |
116 | } | |
117 | } | |
118 | ||
119 | /* not found or invalid argument */ | |
120 | return -1; | |
121 | } | |
122 | ||
1da177e4 | 123 | /* |
311c4627 | 124 | * Check, if transmit buffers are processed |
1da177e4 LT |
125 | */ |
126 | static unsigned int cpm_uart_tx_empty(struct uart_port *port) | |
127 | { | |
128 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
129 | volatile cbd_t *bdp = pinfo->tx_bd_base; | |
130 | int ret = 0; | |
131 | ||
132 | while (1) { | |
133 | if (bdp->cbd_sc & BD_SC_READY) | |
134 | break; | |
135 | ||
136 | if (bdp->cbd_sc & BD_SC_WRAP) { | |
137 | ret = TIOCSER_TEMT; | |
138 | break; | |
139 | } | |
140 | bdp++; | |
141 | } | |
142 | ||
143 | pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); | |
144 | ||
145 | return ret; | |
146 | } | |
147 | ||
148 | static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
149 | { | |
150 | /* Whee. Do nothing. */ | |
151 | } | |
152 | ||
153 | static unsigned int cpm_uart_get_mctrl(struct uart_port *port) | |
154 | { | |
155 | /* Whee. Do nothing. */ | |
156 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
157 | } | |
158 | ||
159 | /* | |
160 | * Stop transmitter | |
161 | */ | |
b129a8cc | 162 | static void cpm_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
163 | { |
164 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
165 | volatile smc_t *smcp = pinfo->smcp; | |
166 | volatile scc_t *sccp = pinfo->sccp; | |
167 | ||
168 | pr_debug("CPM uart[%d]:stop tx\n", port->line); | |
169 | ||
170 | if (IS_SMC(pinfo)) | |
171 | smcp->smc_smcm &= ~SMCM_TX; | |
172 | else | |
173 | sccp->scc_sccm &= ~UART_SCCM_TX; | |
174 | } | |
175 | ||
176 | /* | |
177 | * Start transmitter | |
178 | */ | |
b129a8cc | 179 | static void cpm_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
180 | { |
181 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
182 | volatile smc_t *smcp = pinfo->smcp; | |
183 | volatile scc_t *sccp = pinfo->sccp; | |
184 | ||
185 | pr_debug("CPM uart[%d]:start tx\n", port->line); | |
186 | ||
187 | if (IS_SMC(pinfo)) { | |
188 | if (smcp->smc_smcm & SMCM_TX) | |
189 | return; | |
190 | } else { | |
191 | if (sccp->scc_sccm & UART_SCCM_TX) | |
192 | return; | |
193 | } | |
194 | ||
195 | if (cpm_uart_tx_pump(port) != 0) { | |
311c4627 | 196 | if (IS_SMC(pinfo)) { |
1da177e4 | 197 | smcp->smc_smcm |= SMCM_TX; |
311c4627 | 198 | } else { |
1da177e4 | 199 | sccp->scc_sccm |= UART_SCCM_TX; |
311c4627 | 200 | } |
1da177e4 LT |
201 | } |
202 | } | |
203 | ||
204 | /* | |
311c4627 | 205 | * Stop receiver |
1da177e4 LT |
206 | */ |
207 | static void cpm_uart_stop_rx(struct uart_port *port) | |
208 | { | |
209 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
210 | volatile smc_t *smcp = pinfo->smcp; | |
211 | volatile scc_t *sccp = pinfo->sccp; | |
212 | ||
213 | pr_debug("CPM uart[%d]:stop rx\n", port->line); | |
214 | ||
215 | if (IS_SMC(pinfo)) | |
216 | smcp->smc_smcm &= ~SMCM_RX; | |
217 | else | |
218 | sccp->scc_sccm &= ~UART_SCCM_RX; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Enable Modem status interrupts | |
223 | */ | |
224 | static void cpm_uart_enable_ms(struct uart_port *port) | |
225 | { | |
226 | pr_debug("CPM uart[%d]:enable ms\n", port->line); | |
227 | } | |
228 | ||
229 | /* | |
311c4627 | 230 | * Generate a break. |
1da177e4 LT |
231 | */ |
232 | static void cpm_uart_break_ctl(struct uart_port *port, int break_state) | |
233 | { | |
234 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
235 | int line = pinfo - cpm_uart_ports; | |
236 | ||
237 | pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, | |
238 | break_state); | |
239 | ||
240 | if (break_state) | |
241 | cpm_line_cr_cmd(line, CPM_CR_STOP_TX); | |
242 | else | |
243 | cpm_line_cr_cmd(line, CPM_CR_RESTART_TX); | |
244 | } | |
245 | ||
246 | /* | |
247 | * Transmit characters, refill buffer descriptor, if possible | |
248 | */ | |
7d12e780 | 249 | static void cpm_uart_int_tx(struct uart_port *port) |
1da177e4 LT |
250 | { |
251 | pr_debug("CPM uart[%d]:TX INT\n", port->line); | |
252 | ||
253 | cpm_uart_tx_pump(port); | |
254 | } | |
255 | ||
256 | /* | |
257 | * Receive characters | |
258 | */ | |
7d12e780 | 259 | static void cpm_uart_int_rx(struct uart_port *port) |
1da177e4 LT |
260 | { |
261 | int i; | |
262 | unsigned char ch, *cp; | |
263 | struct tty_struct *tty = port->info->tty; | |
264 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
265 | volatile cbd_t *bdp; | |
266 | u16 status; | |
267 | unsigned int flg; | |
268 | ||
269 | pr_debug("CPM uart[%d]:RX INT\n", port->line); | |
270 | ||
271 | /* Just loop through the closed BDs and copy the characters into | |
272 | * the buffer. | |
273 | */ | |
274 | bdp = pinfo->rx_cur; | |
275 | for (;;) { | |
276 | /* get status */ | |
277 | status = bdp->cbd_sc; | |
278 | /* If this one is empty, return happy */ | |
279 | if (status & BD_SC_EMPTY) | |
280 | break; | |
281 | ||
282 | /* get number of characters, and check spce in flip-buffer */ | |
283 | i = bdp->cbd_datlen; | |
284 | ||
311c4627 | 285 | /* If we have not enough room in tty flip buffer, then we try |
1da177e4 LT |
286 | * later, which will be the next rx-interrupt or a timeout |
287 | */ | |
76a55431 VB |
288 | if(tty_buffer_request_room(tty, i) < i) { |
289 | printk(KERN_WARNING "No room in flip buffer\n"); | |
290 | return; | |
1da177e4 LT |
291 | } |
292 | ||
293 | /* get pointer */ | |
09b03b6c | 294 | cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); |
1da177e4 LT |
295 | |
296 | /* loop through the buffer */ | |
297 | while (i-- > 0) { | |
298 | ch = *cp++; | |
299 | port->icount.rx++; | |
300 | flg = TTY_NORMAL; | |
301 | ||
302 | if (status & | |
303 | (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) | |
304 | goto handle_error; | |
7d12e780 | 305 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 LT |
306 | continue; |
307 | ||
308 | error_return: | |
76a55431 | 309 | tty_insert_flip_char(tty, ch, flg); |
1da177e4 LT |
310 | |
311 | } /* End while (i--) */ | |
312 | ||
313 | /* This BD is ready to be used again. Clear status. get next */ | |
311c4627 | 314 | bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); |
1da177e4 LT |
315 | bdp->cbd_sc |= BD_SC_EMPTY; |
316 | ||
317 | if (bdp->cbd_sc & BD_SC_WRAP) | |
318 | bdp = pinfo->rx_bd_base; | |
319 | else | |
320 | bdp++; | |
311c4627 | 321 | |
1da177e4 LT |
322 | } /* End for (;;) */ |
323 | ||
324 | /* Write back buffer pointer */ | |
325 | pinfo->rx_cur = (volatile cbd_t *) bdp; | |
326 | ||
327 | /* activate BH processing */ | |
328 | tty_flip_buffer_push(tty); | |
329 | ||
330 | return; | |
331 | ||
332 | /* Error processing */ | |
333 | ||
334 | handle_error: | |
335 | /* Statistics */ | |
336 | if (status & BD_SC_BR) | |
337 | port->icount.brk++; | |
338 | if (status & BD_SC_PR) | |
339 | port->icount.parity++; | |
340 | if (status & BD_SC_FR) | |
341 | port->icount.frame++; | |
342 | if (status & BD_SC_OV) | |
343 | port->icount.overrun++; | |
344 | ||
345 | /* Mask out ignored conditions */ | |
346 | status &= port->read_status_mask; | |
347 | ||
348 | /* Handle the remaining ones */ | |
349 | if (status & BD_SC_BR) | |
350 | flg = TTY_BREAK; | |
351 | else if (status & BD_SC_PR) | |
352 | flg = TTY_PARITY; | |
353 | else if (status & BD_SC_FR) | |
354 | flg = TTY_FRAME; | |
355 | ||
356 | /* overrun does not affect the current character ! */ | |
357 | if (status & BD_SC_OV) { | |
358 | ch = 0; | |
359 | flg = TTY_OVERRUN; | |
360 | /* We skip this buffer */ | |
361 | /* CHECK: Is really nothing senseful there */ | |
362 | /* ASSUMPTION: it contains nothing valid */ | |
363 | i = 0; | |
364 | } | |
365 | #ifdef SUPPORT_SYSRQ | |
366 | port->sysrq = 0; | |
367 | #endif | |
368 | goto error_return; | |
369 | } | |
370 | ||
371 | /* | |
372 | * Asynchron mode interrupt handler | |
373 | */ | |
7d12e780 | 374 | static irqreturn_t cpm_uart_int(int irq, void *data) |
1da177e4 LT |
375 | { |
376 | u8 events; | |
377 | struct uart_port *port = (struct uart_port *)data; | |
378 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
379 | volatile smc_t *smcp = pinfo->smcp; | |
380 | volatile scc_t *sccp = pinfo->sccp; | |
381 | ||
382 | pr_debug("CPM uart[%d]:IRQ\n", port->line); | |
383 | ||
384 | if (IS_SMC(pinfo)) { | |
385 | events = smcp->smc_smce; | |
311c4627 | 386 | smcp->smc_smce = events; |
1da177e4 LT |
387 | if (events & SMCM_BRKE) |
388 | uart_handle_break(port); | |
389 | if (events & SMCM_RX) | |
7d12e780 | 390 | cpm_uart_int_rx(port); |
1da177e4 | 391 | if (events & SMCM_TX) |
7d12e780 | 392 | cpm_uart_int_tx(port); |
1da177e4 LT |
393 | } else { |
394 | events = sccp->scc_scce; | |
311c4627 | 395 | sccp->scc_scce = events; |
1da177e4 LT |
396 | if (events & UART_SCCM_BRKE) |
397 | uart_handle_break(port); | |
398 | if (events & UART_SCCM_RX) | |
7d12e780 | 399 | cpm_uart_int_rx(port); |
1da177e4 | 400 | if (events & UART_SCCM_TX) |
7d12e780 | 401 | cpm_uart_int_tx(port); |
1da177e4 LT |
402 | } |
403 | return (events) ? IRQ_HANDLED : IRQ_NONE; | |
404 | } | |
405 | ||
406 | static int cpm_uart_startup(struct uart_port *port) | |
407 | { | |
408 | int retval; | |
409 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
311c4627 | 410 | int line = pinfo - cpm_uart_ports; |
1da177e4 LT |
411 | |
412 | pr_debug("CPM uart[%d]:startup\n", port->line); | |
413 | ||
414 | /* Install interrupt handler. */ | |
415 | retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); | |
416 | if (retval) | |
417 | return retval; | |
418 | ||
419 | /* Startup rx-int */ | |
420 | if (IS_SMC(pinfo)) { | |
421 | pinfo->smcp->smc_smcm |= SMCM_RX; | |
599540a8 | 422 | pinfo->smcp->smc_smcmr |= (SMCMR_REN | SMCMR_TEN); |
1da177e4 LT |
423 | } else { |
424 | pinfo->sccp->scc_sccm |= UART_SCCM_RX; | |
599540a8 | 425 | pinfo->sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
1da177e4 LT |
426 | } |
427 | ||
311c4627 KG |
428 | if (!(pinfo->flags & FLAG_CONSOLE)) |
429 | cpm_line_cr_cmd(line,CPM_CR_INIT_TRX); | |
1da177e4 LT |
430 | return 0; |
431 | } | |
432 | ||
311c4627 KG |
433 | inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) |
434 | { | |
638861d5 KG |
435 | set_current_state(TASK_UNINTERRUPTIBLE); |
436 | schedule_timeout(pinfo->wait_closing); | |
311c4627 KG |
437 | } |
438 | ||
1da177e4 LT |
439 | /* |
440 | * Shutdown the uart | |
441 | */ | |
442 | static void cpm_uart_shutdown(struct uart_port *port) | |
443 | { | |
444 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
445 | int line = pinfo - cpm_uart_ports; | |
446 | ||
447 | pr_debug("CPM uart[%d]:shutdown\n", port->line); | |
448 | ||
449 | /* free interrupt handler */ | |
450 | free_irq(port->irq, port); | |
451 | ||
452 | /* If the port is not the console, disable Rx and Tx. */ | |
453 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
311c4627 | 454 | /* Wait for all the BDs marked sent */ |
638861d5 KG |
455 | while(!cpm_uart_tx_empty(port)) { |
456 | set_current_state(TASK_UNINTERRUPTIBLE); | |
311c4627 | 457 | schedule_timeout(2); |
638861d5 KG |
458 | } |
459 | ||
460 | if (pinfo->wait_closing) | |
311c4627 KG |
461 | cpm_uart_wait_until_send(pinfo); |
462 | ||
1da177e4 LT |
463 | /* Stop uarts */ |
464 | if (IS_SMC(pinfo)) { | |
465 | volatile smc_t *smcp = pinfo->smcp; | |
466 | smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); | |
467 | smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX); | |
468 | } else { | |
469 | volatile scc_t *sccp = pinfo->sccp; | |
470 | sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
471 | sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX); | |
472 | } | |
473 | ||
474 | /* Shut them really down and reinit buffer descriptors */ | |
61f5657c VB |
475 | if (IS_SMC(pinfo)) |
476 | cpm_line_cr_cmd(line, CPM_CR_STOP_TX); | |
477 | else | |
478 | cpm_line_cr_cmd(line, CPM_CR_GRA_STOP_TX); | |
479 | ||
1da177e4 LT |
480 | cpm_uart_initbd(pinfo); |
481 | } | |
482 | } | |
483 | ||
484 | static void cpm_uart_set_termios(struct uart_port *port, | |
485 | struct termios *termios, struct termios *old) | |
486 | { | |
487 | int baud; | |
488 | unsigned long flags; | |
489 | u16 cval, scval, prev_mode; | |
490 | int bits, sbits; | |
491 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
492 | volatile smc_t *smcp = pinfo->smcp; | |
493 | volatile scc_t *sccp = pinfo->sccp; | |
494 | ||
495 | pr_debug("CPM uart[%d]:set_termios\n", port->line); | |
496 | ||
497 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
498 | ||
499 | /* Character length programmed into the mode register is the | |
500 | * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, | |
501 | * 1 or 2 stop bits, minus 1. | |
502 | * The value 'bits' counts this for us. | |
503 | */ | |
504 | cval = 0; | |
505 | scval = 0; | |
506 | ||
507 | /* byte size */ | |
508 | switch (termios->c_cflag & CSIZE) { | |
509 | case CS5: | |
510 | bits = 5; | |
511 | break; | |
512 | case CS6: | |
513 | bits = 6; | |
514 | break; | |
515 | case CS7: | |
516 | bits = 7; | |
517 | break; | |
518 | case CS8: | |
519 | bits = 8; | |
520 | break; | |
521 | /* Never happens, but GCC is too dumb to figure it out */ | |
522 | default: | |
523 | bits = 8; | |
524 | break; | |
525 | } | |
526 | sbits = bits - 5; | |
527 | ||
528 | if (termios->c_cflag & CSTOPB) { | |
529 | cval |= SMCMR_SL; /* Two stops */ | |
530 | scval |= SCU_PSMR_SL; | |
531 | bits++; | |
532 | } | |
533 | ||
534 | if (termios->c_cflag & PARENB) { | |
535 | cval |= SMCMR_PEN; | |
536 | scval |= SCU_PSMR_PEN; | |
537 | bits++; | |
538 | if (!(termios->c_cflag & PARODD)) { | |
539 | cval |= SMCMR_PM_EVEN; | |
540 | scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); | |
541 | } | |
542 | } | |
543 | ||
544 | /* | |
545 | * Set up parity check flag | |
546 | */ | |
547 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) | |
548 | ||
549 | port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); | |
550 | if (termios->c_iflag & INPCK) | |
551 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; | |
552 | if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) | |
553 | port->read_status_mask |= BD_SC_BR; | |
554 | ||
555 | /* | |
556 | * Characters to ignore | |
557 | */ | |
558 | port->ignore_status_mask = 0; | |
559 | if (termios->c_iflag & IGNPAR) | |
560 | port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; | |
561 | if (termios->c_iflag & IGNBRK) { | |
562 | port->ignore_status_mask |= BD_SC_BR; | |
563 | /* | |
564 | * If we're ignore parity and break indicators, ignore | |
565 | * overruns too. (For real raw support). | |
566 | */ | |
567 | if (termios->c_iflag & IGNPAR) | |
568 | port->ignore_status_mask |= BD_SC_OV; | |
569 | } | |
570 | /* | |
571 | * !!! ignore all characters if CREAD is not set | |
572 | */ | |
573 | if ((termios->c_cflag & CREAD) == 0) | |
574 | port->read_status_mask &= ~BD_SC_EMPTY; | |
311c4627 | 575 | |
1da177e4 LT |
576 | spin_lock_irqsave(&port->lock, flags); |
577 | ||
578 | /* Start bit has not been added (so don't, because we would just | |
579 | * subtract it later), and we need to add one for the number of | |
580 | * stops bits (there is always at least one). | |
581 | */ | |
582 | bits++; | |
583 | if (IS_SMC(pinfo)) { | |
584 | /* Set the mode register. We want to keep a copy of the | |
585 | * enables, because we want to put them back if they were | |
586 | * present. | |
587 | */ | |
588 | prev_mode = smcp->smc_smcmr; | |
589 | smcp->smc_smcmr = smcr_mk_clen(bits) | cval | SMCMR_SM_UART; | |
590 | smcp->smc_smcmr |= (prev_mode & (SMCMR_REN | SMCMR_TEN)); | |
591 | } else { | |
592 | sccp->scc_psmr = (sbits << 12) | scval; | |
593 | } | |
594 | ||
595 | cpm_set_brg(pinfo->brg - 1, baud); | |
596 | spin_unlock_irqrestore(&port->lock, flags); | |
597 | ||
598 | } | |
599 | ||
600 | static const char *cpm_uart_type(struct uart_port *port) | |
601 | { | |
602 | pr_debug("CPM uart[%d]:uart_type\n", port->line); | |
603 | ||
604 | return port->type == PORT_CPM ? "CPM UART" : NULL; | |
605 | } | |
606 | ||
607 | /* | |
608 | * verify the new serial_struct (for TIOCSSERIAL). | |
609 | */ | |
610 | static int cpm_uart_verify_port(struct uart_port *port, | |
611 | struct serial_struct *ser) | |
612 | { | |
613 | int ret = 0; | |
614 | ||
615 | pr_debug("CPM uart[%d]:verify_port\n", port->line); | |
616 | ||
617 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) | |
618 | ret = -EINVAL; | |
619 | if (ser->irq < 0 || ser->irq >= NR_IRQS) | |
620 | ret = -EINVAL; | |
621 | if (ser->baud_base < 9600) | |
622 | ret = -EINVAL; | |
623 | return ret; | |
624 | } | |
625 | ||
626 | /* | |
627 | * Transmit characters, refill buffer descriptor, if possible | |
628 | */ | |
629 | static int cpm_uart_tx_pump(struct uart_port *port) | |
630 | { | |
631 | volatile cbd_t *bdp; | |
632 | unsigned char *p; | |
633 | int count; | |
634 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
635 | struct circ_buf *xmit = &port->info->xmit; | |
636 | ||
637 | /* Handle xon/xoff */ | |
638 | if (port->x_char) { | |
639 | /* Pick next descriptor and fill from buffer */ | |
640 | bdp = pinfo->tx_cur; | |
641 | ||
09b03b6c | 642 | p = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); |
311c4627 | 643 | |
03929c76 | 644 | *p++ = port->x_char; |
1da177e4 LT |
645 | bdp->cbd_datlen = 1; |
646 | bdp->cbd_sc |= BD_SC_READY; | |
647 | /* Get next BD. */ | |
648 | if (bdp->cbd_sc & BD_SC_WRAP) | |
649 | bdp = pinfo->tx_bd_base; | |
650 | else | |
651 | bdp++; | |
652 | pinfo->tx_cur = bdp; | |
653 | ||
654 | port->icount.tx++; | |
655 | port->x_char = 0; | |
656 | return 1; | |
657 | } | |
658 | ||
659 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 660 | cpm_uart_stop_tx(port); |
1da177e4 LT |
661 | return 0; |
662 | } | |
663 | ||
664 | /* Pick next descriptor and fill from buffer */ | |
665 | bdp = pinfo->tx_cur; | |
666 | ||
667 | while (!(bdp->cbd_sc & BD_SC_READY) && (xmit->tail != xmit->head)) { | |
668 | count = 0; | |
09b03b6c | 669 | p = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); |
1da177e4 LT |
670 | while (count < pinfo->tx_fifosize) { |
671 | *p++ = xmit->buf[xmit->tail]; | |
672 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
673 | port->icount.tx++; | |
674 | count++; | |
675 | if (xmit->head == xmit->tail) | |
676 | break; | |
677 | } | |
678 | bdp->cbd_datlen = count; | |
679 | bdp->cbd_sc |= BD_SC_READY; | |
311c4627 | 680 | __asm__("eieio"); |
1da177e4 LT |
681 | /* Get next BD. */ |
682 | if (bdp->cbd_sc & BD_SC_WRAP) | |
683 | bdp = pinfo->tx_bd_base; | |
684 | else | |
685 | bdp++; | |
686 | } | |
687 | pinfo->tx_cur = bdp; | |
688 | ||
689 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
690 | uart_write_wakeup(port); | |
691 | ||
692 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 693 | cpm_uart_stop_tx(port); |
1da177e4 LT |
694 | return 0; |
695 | } | |
696 | ||
697 | return 1; | |
698 | } | |
699 | ||
700 | /* | |
701 | * init buffer descriptors | |
702 | */ | |
703 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo) | |
704 | { | |
705 | int i; | |
706 | u8 *mem_addr; | |
707 | volatile cbd_t *bdp; | |
708 | ||
709 | pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); | |
710 | ||
711 | /* Set the physical address of the host memory | |
712 | * buffers in the buffer descriptors, and the | |
713 | * virtual address for us to work with. | |
714 | */ | |
715 | mem_addr = pinfo->mem_addr; | |
716 | bdp = pinfo->rx_cur = pinfo->rx_bd_base; | |
717 | for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { | |
09b03b6c | 718 | bdp->cbd_bufaddr = cpu2cpm_addr(mem_addr, pinfo); |
1da177e4 LT |
719 | bdp->cbd_sc = BD_SC_EMPTY | BD_SC_INTRPT; |
720 | mem_addr += pinfo->rx_fifosize; | |
721 | } | |
311c4627 | 722 | |
09b03b6c | 723 | bdp->cbd_bufaddr = cpu2cpm_addr(mem_addr, pinfo); |
1da177e4 LT |
724 | bdp->cbd_sc = BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT; |
725 | ||
726 | /* Set the physical address of the host memory | |
727 | * buffers in the buffer descriptors, and the | |
728 | * virtual address for us to work with. | |
729 | */ | |
730 | mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); | |
731 | bdp = pinfo->tx_cur = pinfo->tx_bd_base; | |
732 | for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { | |
09b03b6c | 733 | bdp->cbd_bufaddr = cpu2cpm_addr(mem_addr, pinfo); |
1da177e4 LT |
734 | bdp->cbd_sc = BD_SC_INTRPT; |
735 | mem_addr += pinfo->tx_fifosize; | |
736 | } | |
311c4627 | 737 | |
09b03b6c | 738 | bdp->cbd_bufaddr = cpu2cpm_addr(mem_addr, pinfo); |
1da177e4 LT |
739 | bdp->cbd_sc = BD_SC_WRAP | BD_SC_INTRPT; |
740 | } | |
741 | ||
742 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) | |
743 | { | |
744 | int line = pinfo - cpm_uart_ports; | |
745 | volatile scc_t *scp; | |
746 | volatile scc_uart_t *sup; | |
747 | ||
748 | pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); | |
749 | ||
750 | scp = pinfo->sccp; | |
751 | sup = pinfo->sccup; | |
752 | ||
753 | /* Store address */ | |
754 | pinfo->sccup->scc_genscc.scc_rbase = (unsigned char *)pinfo->rx_bd_base - DPRAM_BASE; | |
755 | pinfo->sccup->scc_genscc.scc_tbase = (unsigned char *)pinfo->tx_bd_base - DPRAM_BASE; | |
756 | ||
757 | /* Set up the uart parameters in the | |
758 | * parameter ram. | |
759 | */ | |
760 | ||
761 | cpm_set_scc_fcr(sup); | |
762 | ||
763 | sup->scc_genscc.scc_mrblr = pinfo->rx_fifosize; | |
764 | sup->scc_maxidl = pinfo->rx_fifosize; | |
765 | sup->scc_brkcr = 1; | |
766 | sup->scc_parec = 0; | |
767 | sup->scc_frmec = 0; | |
768 | sup->scc_nosec = 0; | |
769 | sup->scc_brkec = 0; | |
770 | sup->scc_uaddr1 = 0; | |
771 | sup->scc_uaddr2 = 0; | |
772 | sup->scc_toseq = 0; | |
773 | sup->scc_char1 = 0x8000; | |
774 | sup->scc_char2 = 0x8000; | |
775 | sup->scc_char3 = 0x8000; | |
776 | sup->scc_char4 = 0x8000; | |
777 | sup->scc_char5 = 0x8000; | |
778 | sup->scc_char6 = 0x8000; | |
779 | sup->scc_char7 = 0x8000; | |
780 | sup->scc_char8 = 0x8000; | |
781 | sup->scc_rccm = 0xc0ff; | |
782 | ||
783 | /* Send the CPM an initialize command. | |
784 | */ | |
785 | cpm_line_cr_cmd(line, CPM_CR_INIT_TRX); | |
786 | ||
787 | /* Set UART mode, 8 bit, no parity, one stop. | |
788 | * Enable receive and transmit. | |
789 | */ | |
790 | scp->scc_gsmrh = 0; | |
791 | scp->scc_gsmrl = | |
792 | (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
793 | ||
794 | /* Enable rx interrupts and clear all pending events. */ | |
795 | scp->scc_sccm = 0; | |
796 | scp->scc_scce = 0xffff; | |
797 | scp->scc_dsr = 0x7e7e; | |
798 | scp->scc_psmr = 0x3000; | |
799 | ||
800 | scp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
801 | } | |
802 | ||
803 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) | |
804 | { | |
805 | int line = pinfo - cpm_uart_ports; | |
806 | volatile smc_t *sp; | |
807 | volatile smc_uart_t *up; | |
808 | ||
809 | pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); | |
810 | ||
811 | sp = pinfo->smcp; | |
812 | up = pinfo->smcup; | |
813 | ||
814 | /* Store address */ | |
815 | pinfo->smcup->smc_rbase = (u_char *)pinfo->rx_bd_base - DPRAM_BASE; | |
816 | pinfo->smcup->smc_tbase = (u_char *)pinfo->tx_bd_base - DPRAM_BASE; | |
817 | ||
818 | /* | |
819 | * In case SMC1 is being relocated... | |
820 | */ | |
821 | #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) | |
822 | up->smc_rbptr = pinfo->smcup->smc_rbase; | |
823 | up->smc_tbptr = pinfo->smcup->smc_tbase; | |
824 | up->smc_rstate = 0; | |
825 | up->smc_tstate = 0; | |
826 | up->smc_brkcr = 1; /* number of break chars */ | |
827 | up->smc_brkec = 0; | |
828 | #endif | |
829 | ||
830 | /* Set up the uart parameters in the | |
831 | * parameter ram. | |
832 | */ | |
833 | cpm_set_smc_fcr(up); | |
834 | ||
835 | /* Using idle charater time requires some additional tuning. */ | |
836 | up->smc_mrblr = pinfo->rx_fifosize; | |
837 | up->smc_maxidl = pinfo->rx_fifosize; | |
311c4627 KG |
838 | up->smc_brklen = 0; |
839 | up->smc_brkec = 0; | |
1da177e4 LT |
840 | up->smc_brkcr = 1; |
841 | ||
842 | cpm_line_cr_cmd(line, CPM_CR_INIT_TRX); | |
843 | ||
844 | /* Set UART mode, 8 bit, no parity, one stop. | |
845 | * Enable receive and transmit. | |
846 | */ | |
847 | sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; | |
848 | ||
849 | /* Enable only rx interrupts clear all pending events. */ | |
850 | sp->smc_smcm = 0; | |
851 | sp->smc_smce = 0xff; | |
852 | ||
853 | sp->smc_smcmr |= (SMCMR_REN | SMCMR_TEN); | |
854 | } | |
855 | ||
856 | /* | |
857 | * Initialize port. This is called from early_console stuff | |
858 | * so we have to be careful here ! | |
859 | */ | |
860 | static int cpm_uart_request_port(struct uart_port *port) | |
861 | { | |
862 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
863 | int ret; | |
864 | ||
865 | pr_debug("CPM uart[%d]:request port\n", port->line); | |
866 | ||
867 | if (pinfo->flags & FLAG_CONSOLE) | |
868 | return 0; | |
869 | ||
1da177e4 LT |
870 | if (IS_SMC(pinfo)) { |
871 | pinfo->smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX); | |
872 | pinfo->smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); | |
873 | } else { | |
874 | pinfo->sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX); | |
875 | pinfo->sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
876 | } | |
877 | ||
878 | ret = cpm_uart_allocbuf(pinfo, 0); | |
879 | ||
880 | if (ret) | |
881 | return ret; | |
882 | ||
883 | cpm_uart_initbd(pinfo); | |
311c4627 KG |
884 | if (IS_SMC(pinfo)) |
885 | cpm_uart_init_smc(pinfo); | |
886 | else | |
887 | cpm_uart_init_scc(pinfo); | |
1da177e4 LT |
888 | |
889 | return 0; | |
890 | } | |
891 | ||
892 | static void cpm_uart_release_port(struct uart_port *port) | |
893 | { | |
894 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
895 | ||
896 | if (!(pinfo->flags & FLAG_CONSOLE)) | |
897 | cpm_uart_freebuf(pinfo); | |
898 | } | |
899 | ||
900 | /* | |
901 | * Configure/autoconfigure the port. | |
902 | */ | |
903 | static void cpm_uart_config_port(struct uart_port *port, int flags) | |
904 | { | |
905 | pr_debug("CPM uart[%d]:config_port\n", port->line); | |
906 | ||
907 | if (flags & UART_CONFIG_TYPE) { | |
908 | port->type = PORT_CPM; | |
909 | cpm_uart_request_port(port); | |
910 | } | |
911 | } | |
912 | static struct uart_ops cpm_uart_pops = { | |
913 | .tx_empty = cpm_uart_tx_empty, | |
914 | .set_mctrl = cpm_uart_set_mctrl, | |
915 | .get_mctrl = cpm_uart_get_mctrl, | |
916 | .stop_tx = cpm_uart_stop_tx, | |
917 | .start_tx = cpm_uart_start_tx, | |
918 | .stop_rx = cpm_uart_stop_rx, | |
919 | .enable_ms = cpm_uart_enable_ms, | |
920 | .break_ctl = cpm_uart_break_ctl, | |
921 | .startup = cpm_uart_startup, | |
922 | .shutdown = cpm_uart_shutdown, | |
923 | .set_termios = cpm_uart_set_termios, | |
924 | .type = cpm_uart_type, | |
925 | .release_port = cpm_uart_release_port, | |
926 | .request_port = cpm_uart_request_port, | |
927 | .config_port = cpm_uart_config_port, | |
928 | .verify_port = cpm_uart_verify_port, | |
929 | }; | |
930 | ||
931 | struct uart_cpm_port cpm_uart_ports[UART_NR] = { | |
932 | [UART_SMC1] = { | |
933 | .port = { | |
934 | .irq = SMC1_IRQ, | |
935 | .ops = &cpm_uart_pops, | |
9b4a1617 | 936 | .iotype = UPIO_MEM, |
076fa0fa | 937 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SMC1].port.lock), |
1da177e4 LT |
938 | }, |
939 | .flags = FLAG_SMC, | |
940 | .tx_nrfifos = TX_NUM_FIFO, | |
941 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 942 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
943 | .rx_fifosize = RX_BUF_SIZE, |
944 | .set_lineif = smc1_lineif, | |
945 | }, | |
946 | [UART_SMC2] = { | |
947 | .port = { | |
948 | .irq = SMC2_IRQ, | |
949 | .ops = &cpm_uart_pops, | |
9b4a1617 | 950 | .iotype = UPIO_MEM, |
076fa0fa | 951 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SMC2].port.lock), |
1da177e4 LT |
952 | }, |
953 | .flags = FLAG_SMC, | |
954 | .tx_nrfifos = TX_NUM_FIFO, | |
955 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 956 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
957 | .rx_fifosize = RX_BUF_SIZE, |
958 | .set_lineif = smc2_lineif, | |
959 | #ifdef CONFIG_SERIAL_CPM_ALT_SMC2 | |
960 | .is_portb = 1, | |
961 | #endif | |
962 | }, | |
963 | [UART_SCC1] = { | |
964 | .port = { | |
965 | .irq = SCC1_IRQ, | |
966 | .ops = &cpm_uart_pops, | |
9b4a1617 | 967 | .iotype = UPIO_MEM, |
076fa0fa | 968 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SCC1].port.lock), |
1da177e4 LT |
969 | }, |
970 | .tx_nrfifos = TX_NUM_FIFO, | |
971 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 972 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
973 | .rx_fifosize = RX_BUF_SIZE, |
974 | .set_lineif = scc1_lineif, | |
311c4627 | 975 | .wait_closing = SCC_WAIT_CLOSING, |
1da177e4 LT |
976 | }, |
977 | [UART_SCC2] = { | |
978 | .port = { | |
979 | .irq = SCC2_IRQ, | |
980 | .ops = &cpm_uart_pops, | |
9b4a1617 | 981 | .iotype = UPIO_MEM, |
076fa0fa | 982 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SCC2].port.lock), |
1da177e4 LT |
983 | }, |
984 | .tx_nrfifos = TX_NUM_FIFO, | |
985 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 986 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
987 | .rx_fifosize = RX_BUF_SIZE, |
988 | .set_lineif = scc2_lineif, | |
311c4627 | 989 | .wait_closing = SCC_WAIT_CLOSING, |
1da177e4 LT |
990 | }, |
991 | [UART_SCC3] = { | |
992 | .port = { | |
993 | .irq = SCC3_IRQ, | |
994 | .ops = &cpm_uart_pops, | |
9b4a1617 | 995 | .iotype = UPIO_MEM, |
076fa0fa | 996 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SCC3].port.lock), |
1da177e4 LT |
997 | }, |
998 | .tx_nrfifos = TX_NUM_FIFO, | |
999 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 1000 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
1001 | .rx_fifosize = RX_BUF_SIZE, |
1002 | .set_lineif = scc3_lineif, | |
311c4627 | 1003 | .wait_closing = SCC_WAIT_CLOSING, |
1da177e4 LT |
1004 | }, |
1005 | [UART_SCC4] = { | |
1006 | .port = { | |
1007 | .irq = SCC4_IRQ, | |
1008 | .ops = &cpm_uart_pops, | |
9b4a1617 | 1009 | .iotype = UPIO_MEM, |
076fa0fa | 1010 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SCC4].port.lock), |
1da177e4 LT |
1011 | }, |
1012 | .tx_nrfifos = TX_NUM_FIFO, | |
1013 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 1014 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
1015 | .rx_fifosize = RX_BUF_SIZE, |
1016 | .set_lineif = scc4_lineif, | |
311c4627 | 1017 | .wait_closing = SCC_WAIT_CLOSING, |
1da177e4 LT |
1018 | }, |
1019 | }; | |
1020 | ||
e27987cd VB |
1021 | int cpm_uart_drv_get_platform_data(struct platform_device *pdev, int is_con) |
1022 | { | |
1023 | struct resource *r; | |
1024 | struct fs_uart_platform_info *pdata = pdev->dev.platform_data; | |
611a15af | 1025 | int idx; /* It is UART_SMCx or UART_SCCx index */ |
e27987cd VB |
1026 | struct uart_cpm_port *pinfo; |
1027 | int line; | |
1028 | u32 mem, pram; | |
1029 | ||
611a15af VB |
1030 | idx = pdata->fs_no = fs_uart_get_id(pdata); |
1031 | ||
6e197696 VB |
1032 | line = cpm_uart_id2nr(idx); |
1033 | if(line < 0) { | |
1034 | printk(KERN_ERR"%s(): port %d is not registered", __FUNCTION__, idx); | |
611a15af | 1035 | return -EINVAL; |
6e197696 | 1036 | } |
e27987cd VB |
1037 | |
1038 | pinfo = (struct uart_cpm_port *) &cpm_uart_ports[idx]; | |
1039 | ||
1040 | pinfo->brg = pdata->brg; | |
1041 | ||
1042 | if (!is_con) { | |
1043 | pinfo->port.line = line; | |
1044 | pinfo->port.flags = UPF_BOOT_AUTOCONF; | |
1045 | } | |
1046 | ||
1047 | if (!(r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"))) | |
1048 | return -EINVAL; | |
3dd0dcbe | 1049 | mem = (u32)ioremap(r->start, r->end - r->start + 1); |
e27987cd VB |
1050 | |
1051 | if (!(r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pram"))) | |
1052 | return -EINVAL; | |
3dd0dcbe | 1053 | pram = (u32)ioremap(r->start, r->end - r->start + 1); |
e27987cd VB |
1054 | |
1055 | if(idx > fsid_smc2_uart) { | |
1056 | pinfo->sccp = (scc_t *)mem; | |
1057 | pinfo->sccup = (scc_uart_t *)pram; | |
1058 | } else { | |
1059 | pinfo->smcp = (smc_t *)mem; | |
1060 | pinfo->smcup = (smc_uart_t *)pram; | |
1061 | } | |
1062 | pinfo->tx_nrfifos = pdata->tx_num_fifo; | |
1063 | pinfo->tx_fifosize = pdata->tx_buf_size; | |
1064 | ||
1065 | pinfo->rx_nrfifos = pdata->rx_num_fifo; | |
1066 | pinfo->rx_fifosize = pdata->rx_buf_size; | |
1067 | ||
1068 | pinfo->port.uartclk = pdata->uart_clk; | |
1069 | pinfo->port.mapbase = (unsigned long)mem; | |
1070 | pinfo->port.irq = platform_get_irq(pdev, 0); | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
1da177e4 LT |
1075 | #ifdef CONFIG_SERIAL_CPM_CONSOLE |
1076 | /* | |
1077 | * Print a string to the serial port trying not to disturb | |
1078 | * any possible real use of the port... | |
1079 | * | |
1080 | * Note that this is called with interrupts already disabled | |
1081 | */ | |
1082 | static void cpm_uart_console_write(struct console *co, const char *s, | |
1083 | u_int count) | |
1084 | { | |
1085 | struct uart_cpm_port *pinfo = | |
1086 | &cpm_uart_ports[cpm_uart_port_map[co->index]]; | |
1087 | unsigned int i; | |
1088 | volatile cbd_t *bdp, *bdbase; | |
1089 | volatile unsigned char *cp; | |
1090 | ||
1091 | /* Get the address of the host memory buffer. | |
1092 | */ | |
1093 | bdp = pinfo->tx_cur; | |
1094 | bdbase = pinfo->tx_bd_base; | |
1095 | ||
1096 | /* | |
1097 | * Now, do each character. This is not as bad as it looks | |
1098 | * since this is a holding FIFO and not a transmitting FIFO. | |
1099 | * We could add the complexity of filling the entire transmit | |
1100 | * buffer, but we would just wait longer between accesses...... | |
1101 | */ | |
1102 | for (i = 0; i < count; i++, s++) { | |
1103 | /* Wait for transmitter fifo to empty. | |
1104 | * Ready indicates output is ready, and xmt is doing | |
1105 | * that, not that it is ready for us to send. | |
1106 | */ | |
1107 | while ((bdp->cbd_sc & BD_SC_READY) != 0) | |
1108 | ; | |
1109 | ||
1110 | /* Send the character out. | |
1111 | * If the buffer address is in the CPM DPRAM, don't | |
1112 | * convert it. | |
1113 | */ | |
09b03b6c | 1114 | cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); |
311c4627 | 1115 | |
1da177e4 LT |
1116 | *cp = *s; |
1117 | ||
1118 | bdp->cbd_datlen = 1; | |
1119 | bdp->cbd_sc |= BD_SC_READY; | |
1120 | ||
1121 | if (bdp->cbd_sc & BD_SC_WRAP) | |
1122 | bdp = bdbase; | |
1123 | else | |
1124 | bdp++; | |
1125 | ||
1126 | /* if a LF, also do CR... */ | |
1127 | if (*s == 10) { | |
1128 | while ((bdp->cbd_sc & BD_SC_READY) != 0) | |
1129 | ; | |
1130 | ||
09b03b6c | 1131 | cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); |
1da177e4 LT |
1132 | |
1133 | *cp = 13; | |
1134 | bdp->cbd_datlen = 1; | |
1135 | bdp->cbd_sc |= BD_SC_READY; | |
1136 | ||
1137 | if (bdp->cbd_sc & BD_SC_WRAP) | |
1138 | bdp = bdbase; | |
1139 | else | |
1140 | bdp++; | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | /* | |
1145 | * Finally, Wait for transmitter & holding register to empty | |
1146 | * and restore the IER | |
1147 | */ | |
1148 | while ((bdp->cbd_sc & BD_SC_READY) != 0) | |
1149 | ; | |
1150 | ||
1151 | pinfo->tx_cur = (volatile cbd_t *) bdp; | |
1152 | } | |
1153 | ||
e27987cd | 1154 | |
1da177e4 LT |
1155 | static int __init cpm_uart_console_setup(struct console *co, char *options) |
1156 | { | |
1157 | struct uart_port *port; | |
1158 | struct uart_cpm_port *pinfo; | |
1159 | int baud = 38400; | |
1160 | int bits = 8; | |
1161 | int parity = 'n'; | |
1162 | int flow = 'n'; | |
1163 | int ret; | |
1164 | ||
e27987cd VB |
1165 | struct fs_uart_platform_info *pdata; |
1166 | struct platform_device* pdev = early_uart_get_pdev(co->index); | |
1167 | ||
e27987cd VB |
1168 | if (!pdev) { |
1169 | pr_info("cpm_uart: console: compat mode\n"); | |
1170 | /* compatibility - will be cleaned up */ | |
1171 | cpm_uart_init_portdesc(); | |
8e30a9a2 | 1172 | } |
e27987cd | 1173 | |
8e30a9a2 VB |
1174 | port = |
1175 | (struct uart_port *)&cpm_uart_ports[cpm_uart_port_map[co->index]]; | |
1176 | pinfo = (struct uart_cpm_port *)port; | |
1177 | if (!pdev) { | |
e27987cd VB |
1178 | if (pinfo->set_lineif) |
1179 | pinfo->set_lineif(pinfo); | |
1180 | } else { | |
1181 | pdata = pdev->dev.platform_data; | |
1182 | if (pdata) | |
1183 | if (pdata->init_ioports) | |
d3465c92 | 1184 | pdata->init_ioports(pdata); |
e27987cd VB |
1185 | |
1186 | cpm_uart_drv_get_platform_data(pdev, 1); | |
1187 | } | |
311c4627 | 1188 | |
1da177e4 LT |
1189 | pinfo->flags |= FLAG_CONSOLE; |
1190 | ||
1191 | if (options) { | |
1192 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1193 | } else { | |
3dd0dcbe | 1194 | if ((baud = uart_baudrate()) == -1) |
1da177e4 LT |
1195 | baud = 9600; |
1196 | } | |
1197 | ||
1da177e4 LT |
1198 | if (IS_SMC(pinfo)) { |
1199 | pinfo->smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX); | |
1200 | pinfo->smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); | |
1201 | } else { | |
1202 | pinfo->sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX); | |
1203 | pinfo->sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1204 | } | |
1205 | ||
1206 | ret = cpm_uart_allocbuf(pinfo, 1); | |
1207 | ||
1208 | if (ret) | |
1209 | return ret; | |
1210 | ||
1211 | cpm_uart_initbd(pinfo); | |
1212 | ||
1213 | if (IS_SMC(pinfo)) | |
1214 | cpm_uart_init_smc(pinfo); | |
1215 | else | |
1216 | cpm_uart_init_scc(pinfo); | |
1217 | ||
1218 | uart_set_options(port, co, baud, parity, bits, flow); | |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
36d2f5a1 | 1223 | static struct uart_driver cpm_reg; |
1da177e4 | 1224 | static struct console cpm_scc_uart_console = { |
36d2f5a1 KG |
1225 | .name = "ttyCPM", |
1226 | .write = cpm_uart_console_write, | |
1227 | .device = uart_console_device, | |
1228 | .setup = cpm_uart_console_setup, | |
1229 | .flags = CON_PRINTBUFFER, | |
1230 | .index = -1, | |
1da177e4 LT |
1231 | .data = &cpm_reg, |
1232 | }; | |
1233 | ||
1234 | int __init cpm_uart_console_init(void) | |
1235 | { | |
e27987cd VB |
1236 | register_console(&cpm_scc_uart_console); |
1237 | return 0; | |
1da177e4 LT |
1238 | } |
1239 | ||
1240 | console_initcall(cpm_uart_console_init); | |
1241 | ||
1242 | #define CPM_UART_CONSOLE &cpm_scc_uart_console | |
1243 | #else | |
1244 | #define CPM_UART_CONSOLE NULL | |
1245 | #endif | |
1246 | ||
1247 | static struct uart_driver cpm_reg = { | |
1248 | .owner = THIS_MODULE, | |
1249 | .driver_name = "ttyCPM", | |
1250 | .dev_name = "ttyCPM", | |
1251 | .major = SERIAL_CPM_MAJOR, | |
1252 | .minor = SERIAL_CPM_MINOR, | |
1253 | .cons = CPM_UART_CONSOLE, | |
1254 | }; | |
e27987cd | 1255 | static int cpm_uart_drv_probe(struct device *dev) |
1da177e4 | 1256 | { |
e27987cd VB |
1257 | struct platform_device *pdev = to_platform_device(dev); |
1258 | struct fs_uart_platform_info *pdata; | |
1259 | int ret = -ENODEV; | |
1da177e4 | 1260 | |
e27987cd VB |
1261 | if(!pdev) { |
1262 | printk(KERN_ERR"CPM UART: platform data missing!\n"); | |
1da177e4 | 1263 | return ret; |
e27987cd | 1264 | } |
1da177e4 | 1265 | |
e27987cd | 1266 | pdata = pdev->dev.platform_data; |
1da177e4 | 1267 | |
e27987cd | 1268 | if ((ret = cpm_uart_drv_get_platform_data(pdev, 0))) |
1da177e4 LT |
1269 | return ret; |
1270 | ||
611a15af VB |
1271 | pr_debug("cpm_uart_drv_probe: Adding CPM UART %d\n", cpm_uart_id2nr(pdata->fs_no)); |
1272 | ||
e27987cd | 1273 | if (pdata->init_ioports) |
d3465c92 | 1274 | pdata->init_ioports(pdata); |
1da177e4 | 1275 | |
e27987cd VB |
1276 | ret = uart_add_one_port(&cpm_reg, &cpm_uart_ports[pdata->fs_no].port); |
1277 | ||
1278 | return ret; | |
1da177e4 LT |
1279 | } |
1280 | ||
e27987cd VB |
1281 | static int cpm_uart_drv_remove(struct device *dev) |
1282 | { | |
1283 | struct platform_device *pdev = to_platform_device(dev); | |
1284 | struct fs_uart_platform_info *pdata = pdev->dev.platform_data; | |
1285 | ||
1286 | pr_debug("cpm_uart_drv_remove: Removing CPM UART %d\n", | |
6e197696 | 1287 | cpm_uart_id2nr(pdata->fs_no)); |
e27987cd VB |
1288 | |
1289 | uart_remove_one_port(&cpm_reg, &cpm_uart_ports[pdata->fs_no].port); | |
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | static struct device_driver cpm_smc_uart_driver = { | |
1294 | .name = "fsl-cpm-smc:uart", | |
1295 | .bus = &platform_bus_type, | |
1296 | .probe = cpm_uart_drv_probe, | |
1297 | .remove = cpm_uart_drv_remove, | |
1298 | }; | |
1299 | ||
1300 | static struct device_driver cpm_scc_uart_driver = { | |
1301 | .name = "fsl-cpm-scc:uart", | |
1302 | .bus = &platform_bus_type, | |
1303 | .probe = cpm_uart_drv_probe, | |
1304 | .remove = cpm_uart_drv_remove, | |
1305 | }; | |
1306 | ||
1307 | /* | |
1308 | This is supposed to match uart devices on platform bus, | |
1309 | */ | |
1310 | static int match_is_uart (struct device* dev, void* data) | |
1da177e4 | 1311 | { |
e27987cd VB |
1312 | struct platform_device* pdev = container_of(dev, struct platform_device, dev); |
1313 | int ret = 0; | |
1314 | /* this was setfunc as uart */ | |
1315 | if(strstr(pdev->name,":uart")) { | |
1316 | ret = 1; | |
1317 | } | |
1318 | return ret; | |
1319 | } | |
1320 | ||
1321 | ||
1322 | static int cpm_uart_init(void) { | |
1323 | ||
1324 | int ret; | |
1da177e4 | 1325 | int i; |
e27987cd VB |
1326 | struct device *dev; |
1327 | printk(KERN_INFO "Serial: CPM driver $Revision: 0.02 $\n"); | |
1328 | ||
1329 | /* lookup the bus for uart devices */ | |
1330 | dev = bus_find_device(&platform_bus_type, NULL, 0, match_is_uart); | |
1331 | ||
1332 | /* There are devices on the bus - all should be OK */ | |
1333 | if (dev) { | |
1334 | cpm_uart_count(); | |
1335 | cpm_reg.nr = cpm_uart_nr; | |
1336 | ||
1337 | if (!(ret = uart_register_driver(&cpm_reg))) { | |
1338 | if ((ret = driver_register(&cpm_smc_uart_driver))) { | |
1339 | uart_unregister_driver(&cpm_reg); | |
1340 | return ret; | |
1341 | } | |
1342 | if ((ret = driver_register(&cpm_scc_uart_driver))) { | |
1343 | driver_unregister(&cpm_scc_uart_driver); | |
1344 | uart_unregister_driver(&cpm_reg); | |
1345 | } | |
1346 | } | |
1347 | } else { | |
1348 | /* No capable platform devices found - falling back to legacy mode */ | |
1349 | pr_info("cpm_uart: WARNING: no UART devices found on platform bus!\n"); | |
1350 | pr_info( | |
1351 | "cpm_uart: the driver will guess configuration, but this mode is no longer supported.\n"); | |
0091cf5a KP |
1352 | |
1353 | /* Don't run this again, if the console driver did it already */ | |
1354 | if (cpm_uart_nr == 0) | |
1355 | cpm_uart_init_portdesc(); | |
e27987cd VB |
1356 | |
1357 | cpm_reg.nr = cpm_uart_nr; | |
1358 | ret = uart_register_driver(&cpm_reg); | |
1359 | ||
1360 | if (ret) | |
1361 | return ret; | |
1362 | ||
1363 | for (i = 0; i < cpm_uart_nr; i++) { | |
1364 | int con = cpm_uart_port_map[i]; | |
1365 | cpm_uart_ports[con].port.line = i; | |
1366 | cpm_uart_ports[con].port.flags = UPF_BOOT_AUTOCONF; | |
0091cf5a KP |
1367 | if (cpm_uart_ports[con].set_lineif) |
1368 | cpm_uart_ports[con].set_lineif(&cpm_uart_ports[con]); | |
e27987cd VB |
1369 | uart_add_one_port(&cpm_reg, &cpm_uart_ports[con].port); |
1370 | } | |
1da177e4 | 1371 | |
1da177e4 | 1372 | } |
e27987cd VB |
1373 | return ret; |
1374 | } | |
1da177e4 | 1375 | |
e27987cd VB |
1376 | static void __exit cpm_uart_exit(void) |
1377 | { | |
1378 | driver_unregister(&cpm_scc_uart_driver); | |
1379 | driver_unregister(&cpm_smc_uart_driver); | |
1da177e4 LT |
1380 | uart_unregister_driver(&cpm_reg); |
1381 | } | |
1382 | ||
1383 | module_init(cpm_uart_init); | |
1384 | module_exit(cpm_uart_exit); | |
1385 | ||
1386 | MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); | |
1387 | MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); | |
1388 | MODULE_LICENSE("GPL"); | |
1389 | MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); |