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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/cpm_uart.c | |
3 | * | |
4 | * Driver for CPM (SCC/SMC) serial ports; core driver | |
5 | * | |
6 | * Based on arch/ppc/cpm2_io/uart.c by Dan Malek | |
7 | * Based on ppc8xx.c by Thomas Gleixner | |
8 | * Based on drivers/serial/amba.c by Russell King | |
9 | * | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) |
1da177e4 | 11 | * Pantelis Antoniou (panto@intracom.gr) (CPM1) |
311c4627 | 12 | * |
7ae87036 | 13 | * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. |
1da177e4 | 14 | * (C) 2004 Intracom, S.A. |
6e197696 | 15 | * (C) 2005-2006 MontaVista Software, Inc. |
0d844065 | 16 | * Vitaly Bordug <vbordug@ru.mvista.com> |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
32 | */ | |
33 | ||
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/tty.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/serial.h> | |
39 | #include <linux/console.h> | |
40 | #include <linux/sysrq.h> | |
41 | #include <linux/device.h> | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dma-mapping.h> | |
e27987cd | 44 | #include <linux/fs_uart_pd.h> |
0b2a2e5b | 45 | #include <linux/of_platform.h> |
7485d26b LP |
46 | #include <linux/gpio.h> |
47 | #include <linux/of_gpio.h> | |
1da177e4 LT |
48 | |
49 | #include <asm/io.h> | |
50 | #include <asm/irq.h> | |
51 | #include <asm/delay.h> | |
3dd0dcbe | 52 | #include <asm/fs_pd.h> |
7ae87036 SW |
53 | #include <asm/udbg.h> |
54 | ||
1da177e4 LT |
55 | #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
56 | #define SUPPORT_SYSRQ | |
57 | #endif | |
58 | ||
59 | #include <linux/serial_core.h> | |
60 | #include <linux/kernel.h> | |
61 | ||
62 | #include "cpm_uart.h" | |
63 | ||
1da177e4 LT |
64 | |
65 | /**************************************************************/ | |
66 | ||
67 | static int cpm_uart_tx_pump(struct uart_port *port); | |
68 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); | |
69 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); | |
70 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo); | |
71 | ||
72 | /**************************************************************/ | |
73 | ||
74 | /* | |
311c4627 | 75 | * Check, if transmit buffers are processed |
1da177e4 LT |
76 | */ |
77 | static unsigned int cpm_uart_tx_empty(struct uart_port *port) | |
78 | { | |
79 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d | 80 | cbd_t __iomem *bdp = pinfo->tx_bd_base; |
1da177e4 LT |
81 | int ret = 0; |
82 | ||
83 | while (1) { | |
c1dcfd9d | 84 | if (in_be16(&bdp->cbd_sc) & BD_SC_READY) |
1da177e4 LT |
85 | break; |
86 | ||
c1dcfd9d | 87 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { |
1da177e4 LT |
88 | ret = TIOCSER_TEMT; |
89 | break; | |
90 | } | |
91 | bdp++; | |
92 | } | |
93 | ||
94 | pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); | |
95 | ||
96 | return ret; | |
97 | } | |
98 | ||
99 | static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
100 | { | |
7485d26b LP |
101 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
102 | ||
103 | if (pinfo->gpios[GPIO_RTS] >= 0) | |
104 | gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); | |
105 | ||
106 | if (pinfo->gpios[GPIO_DTR] >= 0) | |
107 | gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); | |
1da177e4 LT |
108 | } |
109 | ||
110 | static unsigned int cpm_uart_get_mctrl(struct uart_port *port) | |
111 | { | |
7485d26b LP |
112 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
113 | unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
114 | ||
115 | if (pinfo->gpios[GPIO_CTS] >= 0) { | |
116 | if (gpio_get_value(pinfo->gpios[GPIO_CTS])) | |
117 | mctrl &= ~TIOCM_CTS; | |
118 | } | |
119 | ||
120 | if (pinfo->gpios[GPIO_DSR] >= 0) { | |
121 | if (gpio_get_value(pinfo->gpios[GPIO_DSR])) | |
122 | mctrl &= ~TIOCM_DSR; | |
123 | } | |
124 | ||
125 | if (pinfo->gpios[GPIO_DCD] >= 0) { | |
126 | if (gpio_get_value(pinfo->gpios[GPIO_DCD])) | |
127 | mctrl &= ~TIOCM_CAR; | |
128 | } | |
129 | ||
130 | if (pinfo->gpios[GPIO_RI] >= 0) { | |
131 | if (!gpio_get_value(pinfo->gpios[GPIO_RI])) | |
132 | mctrl |= TIOCM_RNG; | |
133 | } | |
134 | ||
135 | return mctrl; | |
1da177e4 LT |
136 | } |
137 | ||
138 | /* | |
139 | * Stop transmitter | |
140 | */ | |
b129a8cc | 141 | static void cpm_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
142 | { |
143 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
144 | smc_t __iomem *smcp = pinfo->smcp; |
145 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
146 | |
147 | pr_debug("CPM uart[%d]:stop tx\n", port->line); | |
148 | ||
149 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 150 | clrbits8(&smcp->smc_smcm, SMCM_TX); |
1da177e4 | 151 | else |
c1dcfd9d | 152 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX); |
1da177e4 LT |
153 | } |
154 | ||
155 | /* | |
156 | * Start transmitter | |
157 | */ | |
b129a8cc | 158 | static void cpm_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
159 | { |
160 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
161 | smc_t __iomem *smcp = pinfo->smcp; |
162 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
163 | |
164 | pr_debug("CPM uart[%d]:start tx\n", port->line); | |
165 | ||
166 | if (IS_SMC(pinfo)) { | |
c1dcfd9d | 167 | if (in_8(&smcp->smc_smcm) & SMCM_TX) |
1da177e4 LT |
168 | return; |
169 | } else { | |
c1dcfd9d | 170 | if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) |
1da177e4 LT |
171 | return; |
172 | } | |
173 | ||
174 | if (cpm_uart_tx_pump(port) != 0) { | |
311c4627 | 175 | if (IS_SMC(pinfo)) { |
c1dcfd9d | 176 | setbits8(&smcp->smc_smcm, SMCM_TX); |
311c4627 | 177 | } else { |
c1dcfd9d | 178 | setbits16(&sccp->scc_sccm, UART_SCCM_TX); |
311c4627 | 179 | } |
1da177e4 LT |
180 | } |
181 | } | |
182 | ||
183 | /* | |
311c4627 | 184 | * Stop receiver |
1da177e4 LT |
185 | */ |
186 | static void cpm_uart_stop_rx(struct uart_port *port) | |
187 | { | |
188 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
189 | smc_t __iomem *smcp = pinfo->smcp; |
190 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
191 | |
192 | pr_debug("CPM uart[%d]:stop rx\n", port->line); | |
193 | ||
194 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 195 | clrbits8(&smcp->smc_smcm, SMCM_RX); |
1da177e4 | 196 | else |
c1dcfd9d | 197 | clrbits16(&sccp->scc_sccm, UART_SCCM_RX); |
1da177e4 LT |
198 | } |
199 | ||
200 | /* | |
201 | * Enable Modem status interrupts | |
202 | */ | |
203 | static void cpm_uart_enable_ms(struct uart_port *port) | |
204 | { | |
205 | pr_debug("CPM uart[%d]:enable ms\n", port->line); | |
206 | } | |
207 | ||
208 | /* | |
311c4627 | 209 | * Generate a break. |
1da177e4 LT |
210 | */ |
211 | static void cpm_uart_break_ctl(struct uart_port *port, int break_state) | |
212 | { | |
213 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1da177e4 LT |
214 | |
215 | pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, | |
216 | break_state); | |
217 | ||
218 | if (break_state) | |
7ae87036 | 219 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
1da177e4 | 220 | else |
7ae87036 | 221 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
222 | } |
223 | ||
224 | /* | |
225 | * Transmit characters, refill buffer descriptor, if possible | |
226 | */ | |
7d12e780 | 227 | static void cpm_uart_int_tx(struct uart_port *port) |
1da177e4 LT |
228 | { |
229 | pr_debug("CPM uart[%d]:TX INT\n", port->line); | |
230 | ||
231 | cpm_uart_tx_pump(port); | |
232 | } | |
233 | ||
8e21d04c JW |
234 | #ifdef CONFIG_CONSOLE_POLL |
235 | static int serial_polled; | |
236 | #endif | |
237 | ||
1da177e4 LT |
238 | /* |
239 | * Receive characters | |
240 | */ | |
7d12e780 | 241 | static void cpm_uart_int_rx(struct uart_port *port) |
1da177e4 LT |
242 | { |
243 | int i; | |
c1dcfd9d SW |
244 | unsigned char ch; |
245 | u8 *cp; | |
f10140fb | 246 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 | 247 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
c1dcfd9d | 248 | cbd_t __iomem *bdp; |
1da177e4 LT |
249 | u16 status; |
250 | unsigned int flg; | |
251 | ||
252 | pr_debug("CPM uart[%d]:RX INT\n", port->line); | |
253 | ||
254 | /* Just loop through the closed BDs and copy the characters into | |
255 | * the buffer. | |
256 | */ | |
257 | bdp = pinfo->rx_cur; | |
258 | for (;;) { | |
8e21d04c JW |
259 | #ifdef CONFIG_CONSOLE_POLL |
260 | if (unlikely(serial_polled)) { | |
261 | serial_polled = 0; | |
262 | return; | |
263 | } | |
264 | #endif | |
1da177e4 | 265 | /* get status */ |
c1dcfd9d | 266 | status = in_be16(&bdp->cbd_sc); |
1da177e4 LT |
267 | /* If this one is empty, return happy */ |
268 | if (status & BD_SC_EMPTY) | |
269 | break; | |
270 | ||
271 | /* get number of characters, and check spce in flip-buffer */ | |
c1dcfd9d | 272 | i = in_be16(&bdp->cbd_datlen); |
1da177e4 | 273 | |
311c4627 | 274 | /* If we have not enough room in tty flip buffer, then we try |
1da177e4 LT |
275 | * later, which will be the next rx-interrupt or a timeout |
276 | */ | |
76a55431 VB |
277 | if(tty_buffer_request_room(tty, i) < i) { |
278 | printk(KERN_WARNING "No room in flip buffer\n"); | |
279 | return; | |
1da177e4 LT |
280 | } |
281 | ||
282 | /* get pointer */ | |
c1dcfd9d | 283 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
284 | |
285 | /* loop through the buffer */ | |
286 | while (i-- > 0) { | |
287 | ch = *cp++; | |
288 | port->icount.rx++; | |
289 | flg = TTY_NORMAL; | |
290 | ||
291 | if (status & | |
292 | (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) | |
293 | goto handle_error; | |
7d12e780 | 294 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 295 | continue; |
8e21d04c JW |
296 | #ifdef CONFIG_CONSOLE_POLL |
297 | if (unlikely(serial_polled)) { | |
298 | serial_polled = 0; | |
299 | return; | |
300 | } | |
301 | #endif | |
1da177e4 | 302 | error_return: |
76a55431 | 303 | tty_insert_flip_char(tty, ch, flg); |
1da177e4 LT |
304 | |
305 | } /* End while (i--) */ | |
306 | ||
307 | /* This BD is ready to be used again. Clear status. get next */ | |
c1dcfd9d SW |
308 | clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | |
309 | BD_SC_OV | BD_SC_ID); | |
310 | setbits16(&bdp->cbd_sc, BD_SC_EMPTY); | |
1da177e4 | 311 | |
c1dcfd9d | 312 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
313 | bdp = pinfo->rx_bd_base; |
314 | else | |
315 | bdp++; | |
311c4627 | 316 | |
1da177e4 LT |
317 | } /* End for (;;) */ |
318 | ||
319 | /* Write back buffer pointer */ | |
c1dcfd9d | 320 | pinfo->rx_cur = bdp; |
1da177e4 LT |
321 | |
322 | /* activate BH processing */ | |
323 | tty_flip_buffer_push(tty); | |
324 | ||
325 | return; | |
326 | ||
327 | /* Error processing */ | |
328 | ||
329 | handle_error: | |
330 | /* Statistics */ | |
331 | if (status & BD_SC_BR) | |
332 | port->icount.brk++; | |
333 | if (status & BD_SC_PR) | |
334 | port->icount.parity++; | |
335 | if (status & BD_SC_FR) | |
336 | port->icount.frame++; | |
337 | if (status & BD_SC_OV) | |
338 | port->icount.overrun++; | |
339 | ||
340 | /* Mask out ignored conditions */ | |
341 | status &= port->read_status_mask; | |
342 | ||
343 | /* Handle the remaining ones */ | |
344 | if (status & BD_SC_BR) | |
345 | flg = TTY_BREAK; | |
346 | else if (status & BD_SC_PR) | |
347 | flg = TTY_PARITY; | |
348 | else if (status & BD_SC_FR) | |
349 | flg = TTY_FRAME; | |
350 | ||
351 | /* overrun does not affect the current character ! */ | |
352 | if (status & BD_SC_OV) { | |
353 | ch = 0; | |
354 | flg = TTY_OVERRUN; | |
355 | /* We skip this buffer */ | |
356 | /* CHECK: Is really nothing senseful there */ | |
357 | /* ASSUMPTION: it contains nothing valid */ | |
358 | i = 0; | |
359 | } | |
360 | #ifdef SUPPORT_SYSRQ | |
361 | port->sysrq = 0; | |
362 | #endif | |
363 | goto error_return; | |
364 | } | |
365 | ||
366 | /* | |
367 | * Asynchron mode interrupt handler | |
368 | */ | |
7d12e780 | 369 | static irqreturn_t cpm_uart_int(int irq, void *data) |
1da177e4 LT |
370 | { |
371 | u8 events; | |
15aafa2f | 372 | struct uart_port *port = data; |
1da177e4 | 373 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
c1dcfd9d SW |
374 | smc_t __iomem *smcp = pinfo->smcp; |
375 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
376 | |
377 | pr_debug("CPM uart[%d]:IRQ\n", port->line); | |
378 | ||
379 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
380 | events = in_8(&smcp->smc_smce); |
381 | out_8(&smcp->smc_smce, events); | |
1da177e4 LT |
382 | if (events & SMCM_BRKE) |
383 | uart_handle_break(port); | |
384 | if (events & SMCM_RX) | |
7d12e780 | 385 | cpm_uart_int_rx(port); |
1da177e4 | 386 | if (events & SMCM_TX) |
7d12e780 | 387 | cpm_uart_int_tx(port); |
1da177e4 | 388 | } else { |
c1dcfd9d SW |
389 | events = in_be16(&sccp->scc_scce); |
390 | out_be16(&sccp->scc_scce, events); | |
1da177e4 LT |
391 | if (events & UART_SCCM_BRKE) |
392 | uart_handle_break(port); | |
393 | if (events & UART_SCCM_RX) | |
7d12e780 | 394 | cpm_uart_int_rx(port); |
1da177e4 | 395 | if (events & UART_SCCM_TX) |
7d12e780 | 396 | cpm_uart_int_tx(port); |
1da177e4 LT |
397 | } |
398 | return (events) ? IRQ_HANDLED : IRQ_NONE; | |
399 | } | |
400 | ||
401 | static int cpm_uart_startup(struct uart_port *port) | |
402 | { | |
403 | int retval; | |
404 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
405 | ||
406 | pr_debug("CPM uart[%d]:startup\n", port->line); | |
407 | ||
408 | /* Install interrupt handler. */ | |
409 | retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); | |
410 | if (retval) | |
411 | return retval; | |
412 | ||
413 | /* Startup rx-int */ | |
414 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
415 | setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); |
416 | setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); | |
1da177e4 | 417 | } else { |
c1dcfd9d SW |
418 | setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); |
419 | setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); | |
1da177e4 LT |
420 | } |
421 | ||
311c4627 | 422 | if (!(pinfo->flags & FLAG_CONSOLE)) |
7ae87036 | 423 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
424 | return 0; |
425 | } | |
426 | ||
311c4627 KG |
427 | inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) |
428 | { | |
638861d5 KG |
429 | set_current_state(TASK_UNINTERRUPTIBLE); |
430 | schedule_timeout(pinfo->wait_closing); | |
311c4627 KG |
431 | } |
432 | ||
1da177e4 LT |
433 | /* |
434 | * Shutdown the uart | |
435 | */ | |
436 | static void cpm_uart_shutdown(struct uart_port *port) | |
437 | { | |
438 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1da177e4 LT |
439 | |
440 | pr_debug("CPM uart[%d]:shutdown\n", port->line); | |
441 | ||
442 | /* free interrupt handler */ | |
443 | free_irq(port->irq, port); | |
444 | ||
445 | /* If the port is not the console, disable Rx and Tx. */ | |
446 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
311c4627 | 447 | /* Wait for all the BDs marked sent */ |
638861d5 KG |
448 | while(!cpm_uart_tx_empty(port)) { |
449 | set_current_state(TASK_UNINTERRUPTIBLE); | |
311c4627 | 450 | schedule_timeout(2); |
638861d5 KG |
451 | } |
452 | ||
453 | if (pinfo->wait_closing) | |
311c4627 KG |
454 | cpm_uart_wait_until_send(pinfo); |
455 | ||
1da177e4 LT |
456 | /* Stop uarts */ |
457 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
458 | smc_t __iomem *smcp = pinfo->smcp; |
459 | clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
460 | clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); | |
1da177e4 | 461 | } else { |
c1dcfd9d SW |
462 | scc_t __iomem *sccp = pinfo->sccp; |
463 | clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
464 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); | |
1da177e4 LT |
465 | } |
466 | ||
467 | /* Shut them really down and reinit buffer descriptors */ | |
ae2d4c39 NL |
468 | if (IS_SMC(pinfo)) { |
469 | out_be16(&pinfo->smcup->smc_brkcr, 0); | |
7ae87036 | 470 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
ae2d4c39 NL |
471 | } else { |
472 | out_be16(&pinfo->sccup->scc_brkcr, 0); | |
7ae87036 | 473 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); |
ae2d4c39 | 474 | } |
61f5657c | 475 | |
1da177e4 LT |
476 | cpm_uart_initbd(pinfo); |
477 | } | |
478 | } | |
479 | ||
480 | static void cpm_uart_set_termios(struct uart_port *port, | |
1bda8f30 SW |
481 | struct ktermios *termios, |
482 | struct ktermios *old) | |
1da177e4 LT |
483 | { |
484 | int baud; | |
485 | unsigned long flags; | |
486 | u16 cval, scval, prev_mode; | |
487 | int bits, sbits; | |
488 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
489 | smc_t __iomem *smcp = pinfo->smcp; |
490 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
491 | |
492 | pr_debug("CPM uart[%d]:set_termios\n", port->line); | |
493 | ||
494 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
495 | ||
496 | /* Character length programmed into the mode register is the | |
497 | * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, | |
498 | * 1 or 2 stop bits, minus 1. | |
499 | * The value 'bits' counts this for us. | |
500 | */ | |
501 | cval = 0; | |
502 | scval = 0; | |
503 | ||
504 | /* byte size */ | |
505 | switch (termios->c_cflag & CSIZE) { | |
506 | case CS5: | |
507 | bits = 5; | |
508 | break; | |
509 | case CS6: | |
510 | bits = 6; | |
511 | break; | |
512 | case CS7: | |
513 | bits = 7; | |
514 | break; | |
515 | case CS8: | |
516 | bits = 8; | |
517 | break; | |
518 | /* Never happens, but GCC is too dumb to figure it out */ | |
519 | default: | |
520 | bits = 8; | |
521 | break; | |
522 | } | |
523 | sbits = bits - 5; | |
524 | ||
525 | if (termios->c_cflag & CSTOPB) { | |
526 | cval |= SMCMR_SL; /* Two stops */ | |
527 | scval |= SCU_PSMR_SL; | |
528 | bits++; | |
529 | } | |
530 | ||
531 | if (termios->c_cflag & PARENB) { | |
532 | cval |= SMCMR_PEN; | |
533 | scval |= SCU_PSMR_PEN; | |
534 | bits++; | |
535 | if (!(termios->c_cflag & PARODD)) { | |
536 | cval |= SMCMR_PM_EVEN; | |
537 | scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); | |
538 | } | |
539 | } | |
540 | ||
dc320815 LP |
541 | /* |
542 | * Update the timeout | |
543 | */ | |
544 | uart_update_timeout(port, termios->c_cflag, baud); | |
545 | ||
1da177e4 LT |
546 | /* |
547 | * Set up parity check flag | |
548 | */ | |
549 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) | |
550 | ||
551 | port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); | |
552 | if (termios->c_iflag & INPCK) | |
553 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; | |
554 | if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) | |
555 | port->read_status_mask |= BD_SC_BR; | |
556 | ||
557 | /* | |
558 | * Characters to ignore | |
559 | */ | |
560 | port->ignore_status_mask = 0; | |
561 | if (termios->c_iflag & IGNPAR) | |
562 | port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; | |
563 | if (termios->c_iflag & IGNBRK) { | |
564 | port->ignore_status_mask |= BD_SC_BR; | |
565 | /* | |
566 | * If we're ignore parity and break indicators, ignore | |
567 | * overruns too. (For real raw support). | |
568 | */ | |
569 | if (termios->c_iflag & IGNPAR) | |
570 | port->ignore_status_mask |= BD_SC_OV; | |
571 | } | |
572 | /* | |
573 | * !!! ignore all characters if CREAD is not set | |
574 | */ | |
575 | if ((termios->c_cflag & CREAD) == 0) | |
576 | port->read_status_mask &= ~BD_SC_EMPTY; | |
311c4627 | 577 | |
1da177e4 LT |
578 | spin_lock_irqsave(&port->lock, flags); |
579 | ||
580 | /* Start bit has not been added (so don't, because we would just | |
581 | * subtract it later), and we need to add one for the number of | |
582 | * stops bits (there is always at least one). | |
583 | */ | |
584 | bits++; | |
585 | if (IS_SMC(pinfo)) { | |
586 | /* Set the mode register. We want to keep a copy of the | |
587 | * enables, because we want to put them back if they were | |
588 | * present. | |
589 | */ | |
ae2d4c39 NL |
590 | prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); |
591 | /* Output in *one* operation, so we don't interrupt RX/TX if they | |
592 | * were already enabled. */ | |
593 | out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | | |
594 | SMCMR_SM_UART | prev_mode); | |
1da177e4 | 595 | } else { |
c1dcfd9d | 596 | out_be16(&sccp->scc_psmr, (sbits << 12) | scval); |
1da177e4 LT |
597 | } |
598 | ||
599 | cpm_set_brg(pinfo->brg - 1, baud); | |
600 | spin_unlock_irqrestore(&port->lock, flags); | |
1da177e4 LT |
601 | } |
602 | ||
603 | static const char *cpm_uart_type(struct uart_port *port) | |
604 | { | |
605 | pr_debug("CPM uart[%d]:uart_type\n", port->line); | |
606 | ||
607 | return port->type == PORT_CPM ? "CPM UART" : NULL; | |
608 | } | |
609 | ||
610 | /* | |
611 | * verify the new serial_struct (for TIOCSSERIAL). | |
612 | */ | |
613 | static int cpm_uart_verify_port(struct uart_port *port, | |
614 | struct serial_struct *ser) | |
615 | { | |
616 | int ret = 0; | |
617 | ||
618 | pr_debug("CPM uart[%d]:verify_port\n", port->line); | |
619 | ||
620 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) | |
621 | ret = -EINVAL; | |
622 | if (ser->irq < 0 || ser->irq >= NR_IRQS) | |
623 | ret = -EINVAL; | |
624 | if (ser->baud_base < 9600) | |
625 | ret = -EINVAL; | |
626 | return ret; | |
627 | } | |
628 | ||
629 | /* | |
630 | * Transmit characters, refill buffer descriptor, if possible | |
631 | */ | |
632 | static int cpm_uart_tx_pump(struct uart_port *port) | |
633 | { | |
c1dcfd9d SW |
634 | cbd_t __iomem *bdp; |
635 | u8 *p; | |
1da177e4 LT |
636 | int count; |
637 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
638 | struct circ_buf *xmit = &port->info->xmit; | |
639 | ||
640 | /* Handle xon/xoff */ | |
641 | if (port->x_char) { | |
642 | /* Pick next descriptor and fill from buffer */ | |
643 | bdp = pinfo->tx_cur; | |
644 | ||
c1dcfd9d | 645 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
311c4627 | 646 | |
03929c76 | 647 | *p++ = port->x_char; |
c1dcfd9d SW |
648 | |
649 | out_be16(&bdp->cbd_datlen, 1); | |
650 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 651 | /* Get next BD. */ |
c1dcfd9d | 652 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
653 | bdp = pinfo->tx_bd_base; |
654 | else | |
655 | bdp++; | |
656 | pinfo->tx_cur = bdp; | |
657 | ||
658 | port->icount.tx++; | |
659 | port->x_char = 0; | |
660 | return 1; | |
661 | } | |
662 | ||
663 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 664 | cpm_uart_stop_tx(port); |
1da177e4 LT |
665 | return 0; |
666 | } | |
667 | ||
668 | /* Pick next descriptor and fill from buffer */ | |
669 | bdp = pinfo->tx_cur; | |
670 | ||
c1dcfd9d SW |
671 | while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && |
672 | xmit->tail != xmit->head) { | |
1da177e4 | 673 | count = 0; |
c1dcfd9d | 674 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
675 | while (count < pinfo->tx_fifosize) { |
676 | *p++ = xmit->buf[xmit->tail]; | |
677 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
678 | port->icount.tx++; | |
679 | count++; | |
680 | if (xmit->head == xmit->tail) | |
681 | break; | |
682 | } | |
c1dcfd9d SW |
683 | out_be16(&bdp->cbd_datlen, count); |
684 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 685 | /* Get next BD. */ |
c1dcfd9d | 686 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
687 | bdp = pinfo->tx_bd_base; |
688 | else | |
689 | bdp++; | |
690 | } | |
691 | pinfo->tx_cur = bdp; | |
692 | ||
693 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
694 | uart_write_wakeup(port); | |
695 | ||
696 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 697 | cpm_uart_stop_tx(port); |
1da177e4 LT |
698 | return 0; |
699 | } | |
700 | ||
701 | return 1; | |
702 | } | |
703 | ||
704 | /* | |
705 | * init buffer descriptors | |
706 | */ | |
707 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo) | |
708 | { | |
709 | int i; | |
710 | u8 *mem_addr; | |
c1dcfd9d | 711 | cbd_t __iomem *bdp; |
1da177e4 LT |
712 | |
713 | pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); | |
714 | ||
715 | /* Set the physical address of the host memory | |
716 | * buffers in the buffer descriptors, and the | |
717 | * virtual address for us to work with. | |
718 | */ | |
719 | mem_addr = pinfo->mem_addr; | |
720 | bdp = pinfo->rx_cur = pinfo->rx_bd_base; | |
721 | for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
722 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
723 | out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
724 | mem_addr += pinfo->rx_fifosize; |
725 | } | |
311c4627 | 726 | |
c1dcfd9d SW |
727 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
728 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
729 | |
730 | /* Set the physical address of the host memory | |
731 | * buffers in the buffer descriptors, and the | |
732 | * virtual address for us to work with. | |
733 | */ | |
734 | mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); | |
735 | bdp = pinfo->tx_cur = pinfo->tx_bd_base; | |
736 | for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
737 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
738 | out_be16(&bdp->cbd_sc, BD_SC_INTRPT); | |
1da177e4 LT |
739 | mem_addr += pinfo->tx_fifosize; |
740 | } | |
311c4627 | 741 | |
c1dcfd9d SW |
742 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
743 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); | |
1da177e4 LT |
744 | } |
745 | ||
746 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) | |
747 | { | |
c1dcfd9d SW |
748 | scc_t __iomem *scp; |
749 | scc_uart_t __iomem *sup; | |
1da177e4 LT |
750 | |
751 | pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); | |
752 | ||
753 | scp = pinfo->sccp; | |
754 | sup = pinfo->sccup; | |
755 | ||
756 | /* Store address */ | |
c1dcfd9d SW |
757 | out_be16(&pinfo->sccup->scc_genscc.scc_rbase, |
758 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
759 | out_be16(&pinfo->sccup->scc_genscc.scc_tbase, | |
760 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
761 | |
762 | /* Set up the uart parameters in the | |
763 | * parameter ram. | |
764 | */ | |
765 | ||
766 | cpm_set_scc_fcr(sup); | |
767 | ||
c1dcfd9d SW |
768 | out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); |
769 | out_be16(&sup->scc_maxidl, pinfo->rx_fifosize); | |
770 | out_be16(&sup->scc_brkcr, 1); | |
771 | out_be16(&sup->scc_parec, 0); | |
772 | out_be16(&sup->scc_frmec, 0); | |
773 | out_be16(&sup->scc_nosec, 0); | |
774 | out_be16(&sup->scc_brkec, 0); | |
775 | out_be16(&sup->scc_uaddr1, 0); | |
776 | out_be16(&sup->scc_uaddr2, 0); | |
777 | out_be16(&sup->scc_toseq, 0); | |
778 | out_be16(&sup->scc_char1, 0x8000); | |
779 | out_be16(&sup->scc_char2, 0x8000); | |
780 | out_be16(&sup->scc_char3, 0x8000); | |
781 | out_be16(&sup->scc_char4, 0x8000); | |
782 | out_be16(&sup->scc_char5, 0x8000); | |
783 | out_be16(&sup->scc_char6, 0x8000); | |
784 | out_be16(&sup->scc_char7, 0x8000); | |
785 | out_be16(&sup->scc_char8, 0x8000); | |
786 | out_be16(&sup->scc_rccm, 0xc0ff); | |
1da177e4 LT |
787 | |
788 | /* Send the CPM an initialize command. | |
789 | */ | |
7ae87036 | 790 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
791 | |
792 | /* Set UART mode, 8 bit, no parity, one stop. | |
793 | * Enable receive and transmit. | |
794 | */ | |
c1dcfd9d SW |
795 | out_be32(&scp->scc_gsmrh, 0); |
796 | out_be32(&scp->scc_gsmrl, | |
797 | SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
1da177e4 LT |
798 | |
799 | /* Enable rx interrupts and clear all pending events. */ | |
c1dcfd9d SW |
800 | out_be16(&scp->scc_sccm, 0); |
801 | out_be16(&scp->scc_scce, 0xffff); | |
802 | out_be16(&scp->scc_dsr, 0x7e7e); | |
803 | out_be16(&scp->scc_psmr, 0x3000); | |
1da177e4 | 804 | |
c1dcfd9d | 805 | setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
1da177e4 LT |
806 | } |
807 | ||
808 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) | |
809 | { | |
c1dcfd9d SW |
810 | smc_t __iomem *sp; |
811 | smc_uart_t __iomem *up; | |
1da177e4 LT |
812 | |
813 | pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); | |
814 | ||
815 | sp = pinfo->smcp; | |
816 | up = pinfo->smcup; | |
817 | ||
818 | /* Store address */ | |
c1dcfd9d SW |
819 | out_be16(&pinfo->smcup->smc_rbase, |
820 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
821 | out_be16(&pinfo->smcup->smc_tbase, | |
822 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
823 | |
824 | /* | |
825 | * In case SMC1 is being relocated... | |
826 | */ | |
827 | #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) | |
c1dcfd9d SW |
828 | out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); |
829 | out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); | |
830 | out_be32(&up->smc_rstate, 0); | |
831 | out_be32(&up->smc_tstate, 0); | |
832 | out_be16(&up->smc_brkcr, 1); /* number of break chars */ | |
833 | out_be16(&up->smc_brkec, 0); | |
1da177e4 LT |
834 | #endif |
835 | ||
836 | /* Set up the uart parameters in the | |
837 | * parameter ram. | |
838 | */ | |
839 | cpm_set_smc_fcr(up); | |
840 | ||
841 | /* Using idle charater time requires some additional tuning. */ | |
c1dcfd9d SW |
842 | out_be16(&up->smc_mrblr, pinfo->rx_fifosize); |
843 | out_be16(&up->smc_maxidl, pinfo->rx_fifosize); | |
844 | out_be16(&up->smc_brklen, 0); | |
845 | out_be16(&up->smc_brkec, 0); | |
846 | out_be16(&up->smc_brkcr, 1); | |
1da177e4 | 847 | |
7ae87036 | 848 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
849 | |
850 | /* Set UART mode, 8 bit, no parity, one stop. | |
851 | * Enable receive and transmit. | |
852 | */ | |
c1dcfd9d | 853 | out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); |
1da177e4 LT |
854 | |
855 | /* Enable only rx interrupts clear all pending events. */ | |
c1dcfd9d SW |
856 | out_8(&sp->smc_smcm, 0); |
857 | out_8(&sp->smc_smce, 0xff); | |
1da177e4 | 858 | |
c1dcfd9d | 859 | setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); |
1da177e4 LT |
860 | } |
861 | ||
862 | /* | |
863 | * Initialize port. This is called from early_console stuff | |
864 | * so we have to be careful here ! | |
865 | */ | |
866 | static int cpm_uart_request_port(struct uart_port *port) | |
867 | { | |
868 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
869 | int ret; | |
870 | ||
871 | pr_debug("CPM uart[%d]:request port\n", port->line); | |
872 | ||
873 | if (pinfo->flags & FLAG_CONSOLE) | |
874 | return 0; | |
875 | ||
1da177e4 | 876 | if (IS_SMC(pinfo)) { |
c1dcfd9d SW |
877 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
878 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 879 | } else { |
c1dcfd9d SW |
880 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
881 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
882 | } |
883 | ||
884 | ret = cpm_uart_allocbuf(pinfo, 0); | |
885 | ||
886 | if (ret) | |
887 | return ret; | |
888 | ||
889 | cpm_uart_initbd(pinfo); | |
311c4627 KG |
890 | if (IS_SMC(pinfo)) |
891 | cpm_uart_init_smc(pinfo); | |
892 | else | |
893 | cpm_uart_init_scc(pinfo); | |
1da177e4 LT |
894 | |
895 | return 0; | |
896 | } | |
897 | ||
898 | static void cpm_uart_release_port(struct uart_port *port) | |
899 | { | |
900 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
901 | ||
902 | if (!(pinfo->flags & FLAG_CONSOLE)) | |
903 | cpm_uart_freebuf(pinfo); | |
904 | } | |
905 | ||
906 | /* | |
907 | * Configure/autoconfigure the port. | |
908 | */ | |
909 | static void cpm_uart_config_port(struct uart_port *port, int flags) | |
910 | { | |
911 | pr_debug("CPM uart[%d]:config_port\n", port->line); | |
912 | ||
913 | if (flags & UART_CONFIG_TYPE) { | |
914 | port->type = PORT_CPM; | |
915 | cpm_uart_request_port(port); | |
916 | } | |
917 | } | |
8e21d04c JW |
918 | |
919 | #ifdef CONFIG_CONSOLE_POLL | |
920 | /* Serial polling routines for writing and reading from the uart while | |
921 | * in an interrupt or debug context. | |
922 | */ | |
923 | ||
924 | #define GDB_BUF_SIZE 512 /* power of 2, please */ | |
925 | ||
926 | static char poll_buf[GDB_BUF_SIZE]; | |
927 | static char *pollp; | |
928 | static int poll_chars; | |
929 | ||
930 | static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) | |
931 | { | |
932 | u_char c, *cp; | |
933 | volatile cbd_t *bdp; | |
934 | int i; | |
935 | ||
936 | /* Get the address of the host memory buffer. | |
937 | */ | |
938 | bdp = pinfo->rx_cur; | |
939 | while (bdp->cbd_sc & BD_SC_EMPTY) | |
940 | ; | |
941 | ||
942 | /* If the buffer address is in the CPM DPRAM, don't | |
943 | * convert it. | |
944 | */ | |
945 | cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); | |
946 | ||
947 | if (obuf) { | |
948 | i = c = bdp->cbd_datlen; | |
949 | while (i-- > 0) | |
950 | *obuf++ = *cp++; | |
951 | } else | |
952 | c = *cp; | |
953 | bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); | |
954 | bdp->cbd_sc |= BD_SC_EMPTY; | |
955 | ||
956 | if (bdp->cbd_sc & BD_SC_WRAP) | |
957 | bdp = pinfo->rx_bd_base; | |
958 | else | |
959 | bdp++; | |
960 | pinfo->rx_cur = (cbd_t *)bdp; | |
961 | ||
962 | return (int)c; | |
963 | } | |
964 | ||
965 | static int cpm_get_poll_char(struct uart_port *port) | |
966 | { | |
967 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
968 | ||
969 | if (!serial_polled) { | |
970 | serial_polled = 1; | |
971 | poll_chars = 0; | |
972 | } | |
973 | if (poll_chars <= 0) { | |
974 | poll_chars = poll_wait_key(poll_buf, pinfo); | |
975 | pollp = poll_buf; | |
976 | } | |
977 | poll_chars--; | |
978 | return *pollp++; | |
979 | } | |
980 | ||
981 | static void cpm_put_poll_char(struct uart_port *port, | |
982 | unsigned char c) | |
983 | { | |
984 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
985 | static char ch[2]; | |
986 | ||
987 | ch[0] = (char)c; | |
988 | cpm_uart_early_write(pinfo->port.line, ch, 1); | |
989 | } | |
990 | #endif /* CONFIG_CONSOLE_POLL */ | |
991 | ||
1da177e4 LT |
992 | static struct uart_ops cpm_uart_pops = { |
993 | .tx_empty = cpm_uart_tx_empty, | |
994 | .set_mctrl = cpm_uart_set_mctrl, | |
995 | .get_mctrl = cpm_uart_get_mctrl, | |
996 | .stop_tx = cpm_uart_stop_tx, | |
997 | .start_tx = cpm_uart_start_tx, | |
998 | .stop_rx = cpm_uart_stop_rx, | |
999 | .enable_ms = cpm_uart_enable_ms, | |
1000 | .break_ctl = cpm_uart_break_ctl, | |
1001 | .startup = cpm_uart_startup, | |
1002 | .shutdown = cpm_uart_shutdown, | |
1003 | .set_termios = cpm_uart_set_termios, | |
1004 | .type = cpm_uart_type, | |
1005 | .release_port = cpm_uart_release_port, | |
1006 | .request_port = cpm_uart_request_port, | |
1007 | .config_port = cpm_uart_config_port, | |
1008 | .verify_port = cpm_uart_verify_port, | |
8e21d04c JW |
1009 | #ifdef CONFIG_CONSOLE_POLL |
1010 | .poll_get_char = cpm_get_poll_char, | |
1011 | .poll_put_char = cpm_put_poll_char, | |
1012 | #endif | |
1da177e4 LT |
1013 | }; |
1014 | ||
7ae87036 SW |
1015 | struct uart_cpm_port cpm_uart_ports[UART_NR]; |
1016 | ||
c1dcfd9d SW |
1017 | static int cpm_uart_init_port(struct device_node *np, |
1018 | struct uart_cpm_port *pinfo) | |
7ae87036 SW |
1019 | { |
1020 | const u32 *data; | |
c1dcfd9d | 1021 | void __iomem *mem, *pram; |
7ae87036 SW |
1022 | int len; |
1023 | int ret; | |
7485d26b | 1024 | int i; |
7ae87036 SW |
1025 | |
1026 | data = of_get_property(np, "fsl,cpm-brg", &len); | |
1027 | if (!data || len != 4) { | |
1028 | printk(KERN_ERR "CPM UART %s has no/invalid " | |
1029 | "fsl,cpm-brg property.\n", np->name); | |
1030 | return -EINVAL; | |
1031 | } | |
1032 | pinfo->brg = *data; | |
1033 | ||
1034 | data = of_get_property(np, "fsl,cpm-command", &len); | |
1035 | if (!data || len != 4) { | |
1036 | printk(KERN_ERR "CPM UART %s has no/invalid " | |
1037 | "fsl,cpm-command property.\n", np->name); | |
1038 | return -EINVAL; | |
1039 | } | |
1040 | pinfo->command = *data; | |
1041 | ||
1042 | mem = of_iomap(np, 0); | |
1043 | if (!mem) | |
1044 | return -ENOMEM; | |
1045 | ||
7ae87036 SW |
1046 | if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || |
1047 | of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { | |
1048 | pinfo->sccp = mem; | |
d464df26 | 1049 | pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); |
7ae87036 SW |
1050 | } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || |
1051 | of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { | |
1052 | pinfo->flags |= FLAG_SMC; | |
1053 | pinfo->smcp = mem; | |
d464df26 | 1054 | pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); |
7ae87036 SW |
1055 | } else { |
1056 | ret = -ENODEV; | |
d464df26 LP |
1057 | goto out_mem; |
1058 | } | |
1059 | ||
1060 | if (!pram) { | |
1061 | ret = -ENOMEM; | |
1062 | goto out_mem; | |
7ae87036 SW |
1063 | } |
1064 | ||
1065 | pinfo->tx_nrfifos = TX_NUM_FIFO; | |
1066 | pinfo->tx_fifosize = TX_BUF_SIZE; | |
1067 | pinfo->rx_nrfifos = RX_NUM_FIFO; | |
1068 | pinfo->rx_fifosize = RX_BUF_SIZE; | |
1069 | ||
1070 | pinfo->port.uartclk = ppc_proc_freq; | |
1071 | pinfo->port.mapbase = (unsigned long)mem; | |
1072 | pinfo->port.type = PORT_CPM; | |
1073 | pinfo->port.ops = &cpm_uart_pops, | |
1074 | pinfo->port.iotype = UPIO_MEM; | |
dc320815 | 1075 | pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; |
7ae87036 SW |
1076 | spin_lock_init(&pinfo->port.lock); |
1077 | ||
1078 | pinfo->port.irq = of_irq_to_resource(np, 0, NULL); | |
1079 | if (pinfo->port.irq == NO_IRQ) { | |
1080 | ret = -EINVAL; | |
1081 | goto out_pram; | |
1082 | } | |
1083 | ||
7485d26b LP |
1084 | for (i = 0; i < NUM_GPIOS; i++) |
1085 | pinfo->gpios[i] = of_get_gpio(np, i); | |
1086 | ||
7ae87036 SW |
1087 | return cpm_uart_request_port(&pinfo->port); |
1088 | ||
1089 | out_pram: | |
d464df26 | 1090 | cpm_uart_unmap_pram(pinfo, pram); |
7ae87036 SW |
1091 | out_mem: |
1092 | iounmap(mem); | |
1093 | return ret; | |
1094 | } | |
1095 | ||
1da177e4 LT |
1096 | #ifdef CONFIG_SERIAL_CPM_CONSOLE |
1097 | /* | |
1098 | * Print a string to the serial port trying not to disturb | |
1099 | * any possible real use of the port... | |
1100 | * | |
1101 | * Note that this is called with interrupts already disabled | |
1102 | */ | |
1103 | static void cpm_uart_console_write(struct console *co, const char *s, | |
1104 | u_int count) | |
1105 | { | |
7ae87036 | 1106 | struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; |
1da177e4 | 1107 | unsigned int i; |
c1dcfd9d SW |
1108 | cbd_t __iomem *bdp, *bdbase; |
1109 | unsigned char *cp; | |
491a7a43 RT |
1110 | unsigned long flags; |
1111 | int nolock = oops_in_progress; | |
1112 | ||
1113 | if (unlikely(nolock)) { | |
1114 | local_irq_save(flags); | |
1115 | } else { | |
1116 | spin_lock_irqsave(&pinfo->port.lock, flags); | |
1117 | } | |
1da177e4 LT |
1118 | |
1119 | /* Get the address of the host memory buffer. | |
1120 | */ | |
1121 | bdp = pinfo->tx_cur; | |
1122 | bdbase = pinfo->tx_bd_base; | |
1123 | ||
1124 | /* | |
1125 | * Now, do each character. This is not as bad as it looks | |
1126 | * since this is a holding FIFO and not a transmitting FIFO. | |
1127 | * We could add the complexity of filling the entire transmit | |
1128 | * buffer, but we would just wait longer between accesses...... | |
1129 | */ | |
1130 | for (i = 0; i < count; i++, s++) { | |
1131 | /* Wait for transmitter fifo to empty. | |
1132 | * Ready indicates output is ready, and xmt is doing | |
1133 | * that, not that it is ready for us to send. | |
1134 | */ | |
c1dcfd9d | 1135 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) |
1da177e4 LT |
1136 | ; |
1137 | ||
1138 | /* Send the character out. | |
1139 | * If the buffer address is in the CPM DPRAM, don't | |
1140 | * convert it. | |
1141 | */ | |
c1dcfd9d | 1142 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
1143 | *cp = *s; |
1144 | ||
c1dcfd9d SW |
1145 | out_be16(&bdp->cbd_datlen, 1); |
1146 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 1147 | |
c1dcfd9d | 1148 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
1149 | bdp = bdbase; |
1150 | else | |
1151 | bdp++; | |
1152 | ||
1153 | /* if a LF, also do CR... */ | |
1154 | if (*s == 10) { | |
c1dcfd9d | 1155 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) |
1da177e4 LT |
1156 | ; |
1157 | ||
c1dcfd9d | 1158 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 | 1159 | *cp = 13; |
1da177e4 | 1160 | |
c1dcfd9d SW |
1161 | out_be16(&bdp->cbd_datlen, 1); |
1162 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1163 | ||
1164 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) | |
1da177e4 LT |
1165 | bdp = bdbase; |
1166 | else | |
1167 | bdp++; | |
1168 | } | |
1169 | } | |
1170 | ||
1171 | /* | |
1172 | * Finally, Wait for transmitter & holding register to empty | |
1173 | * and restore the IER | |
1174 | */ | |
c1dcfd9d | 1175 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) |
1da177e4 LT |
1176 | ; |
1177 | ||
c1dcfd9d | 1178 | pinfo->tx_cur = bdp; |
491a7a43 RT |
1179 | |
1180 | if (unlikely(nolock)) { | |
1181 | local_irq_restore(flags); | |
1182 | } else { | |
1183 | spin_unlock_irqrestore(&pinfo->port.lock, flags); | |
1184 | } | |
1da177e4 LT |
1185 | } |
1186 | ||
e27987cd | 1187 | |
1da177e4 LT |
1188 | static int __init cpm_uart_console_setup(struct console *co, char *options) |
1189 | { | |
1da177e4 LT |
1190 | int baud = 38400; |
1191 | int bits = 8; | |
1192 | int parity = 'n'; | |
1193 | int flow = 'n'; | |
1194 | int ret; | |
7ae87036 SW |
1195 | struct uart_cpm_port *pinfo; |
1196 | struct uart_port *port; | |
1197 | ||
7ae87036 SW |
1198 | struct device_node *np = NULL; |
1199 | int i = 0; | |
1200 | ||
1201 | if (co->index >= UART_NR) { | |
1202 | printk(KERN_ERR "cpm_uart: console index %d too high\n", | |
1203 | co->index); | |
1204 | return -ENODEV; | |
1205 | } | |
1206 | ||
1207 | do { | |
1208 | np = of_find_node_by_type(np, "serial"); | |
1209 | if (!np) | |
1210 | return -ENODEV; | |
1211 | ||
1212 | if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && | |
1213 | !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && | |
1214 | !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && | |
1215 | !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) | |
1216 | i--; | |
1217 | } while (i++ != co->index); | |
1218 | ||
1219 | pinfo = &cpm_uart_ports[co->index]; | |
1220 | ||
1221 | pinfo->flags |= FLAG_CONSOLE; | |
1222 | port = &pinfo->port; | |
1223 | ||
1224 | ret = cpm_uart_init_port(np, pinfo); | |
1225 | of_node_put(np); | |
1226 | if (ret) | |
1227 | return ret; | |
1228 | ||
1da177e4 LT |
1229 | if (options) { |
1230 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1231 | } else { | |
3dd0dcbe | 1232 | if ((baud = uart_baudrate()) == -1) |
1da177e4 LT |
1233 | baud = 9600; |
1234 | } | |
1235 | ||
7ae87036 SW |
1236 | #ifdef CONFIG_PPC_EARLY_DEBUG_CPM |
1237 | udbg_putc = NULL; | |
1238 | #endif | |
1239 | ||
1da177e4 | 1240 | if (IS_SMC(pinfo)) { |
ae2d4c39 NL |
1241 | out_be16(&pinfo->smcup->smc_brkcr, 0); |
1242 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); | |
c1dcfd9d SW |
1243 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
1244 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 1245 | } else { |
ae2d4c39 NL |
1246 | out_be16(&pinfo->sccup->scc_brkcr, 0); |
1247 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); | |
c1dcfd9d SW |
1248 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
1249 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
1250 | } |
1251 | ||
1252 | ret = cpm_uart_allocbuf(pinfo, 1); | |
1253 | ||
1254 | if (ret) | |
1255 | return ret; | |
1256 | ||
1257 | cpm_uart_initbd(pinfo); | |
1258 | ||
1259 | if (IS_SMC(pinfo)) | |
1260 | cpm_uart_init_smc(pinfo); | |
1261 | else | |
1262 | cpm_uart_init_scc(pinfo); | |
1263 | ||
1264 | uart_set_options(port, co, baud, parity, bits, flow); | |
d948a29e | 1265 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
1266 | |
1267 | return 0; | |
1268 | } | |
1269 | ||
36d2f5a1 | 1270 | static struct uart_driver cpm_reg; |
1da177e4 | 1271 | static struct console cpm_scc_uart_console = { |
36d2f5a1 KG |
1272 | .name = "ttyCPM", |
1273 | .write = cpm_uart_console_write, | |
1274 | .device = uart_console_device, | |
1275 | .setup = cpm_uart_console_setup, | |
1276 | .flags = CON_PRINTBUFFER, | |
1277 | .index = -1, | |
1da177e4 LT |
1278 | .data = &cpm_reg, |
1279 | }; | |
1280 | ||
c1dcfd9d | 1281 | static int __init cpm_uart_console_init(void) |
1da177e4 | 1282 | { |
e27987cd VB |
1283 | register_console(&cpm_scc_uart_console); |
1284 | return 0; | |
1da177e4 LT |
1285 | } |
1286 | ||
1287 | console_initcall(cpm_uart_console_init); | |
1288 | ||
1289 | #define CPM_UART_CONSOLE &cpm_scc_uart_console | |
1290 | #else | |
1291 | #define CPM_UART_CONSOLE NULL | |
1292 | #endif | |
1293 | ||
1294 | static struct uart_driver cpm_reg = { | |
1295 | .owner = THIS_MODULE, | |
1296 | .driver_name = "ttyCPM", | |
1297 | .dev_name = "ttyCPM", | |
1298 | .major = SERIAL_CPM_MAJOR, | |
1299 | .minor = SERIAL_CPM_MINOR, | |
1300 | .cons = CPM_UART_CONSOLE, | |
7ae87036 SW |
1301 | .nr = UART_NR, |
1302 | }; | |
1303 | ||
7ae87036 SW |
1304 | static int probe_index; |
1305 | ||
1306 | static int __devinit cpm_uart_probe(struct of_device *ofdev, | |
1307 | const struct of_device_id *match) | |
1308 | { | |
1309 | int index = probe_index++; | |
1310 | struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; | |
1311 | int ret; | |
1312 | ||
1313 | pinfo->port.line = index; | |
1314 | ||
1315 | if (index >= UART_NR) | |
1316 | return -ENODEV; | |
1317 | ||
1318 | dev_set_drvdata(&ofdev->dev, pinfo); | |
1319 | ||
1320 | ret = cpm_uart_init_port(ofdev->node, pinfo); | |
1321 | if (ret) | |
1322 | return ret; | |
1323 | ||
1324 | return uart_add_one_port(&cpm_reg, &pinfo->port); | |
1325 | } | |
1326 | ||
1327 | static int __devexit cpm_uart_remove(struct of_device *ofdev) | |
1328 | { | |
1329 | struct uart_cpm_port *pinfo = dev_get_drvdata(&ofdev->dev); | |
1330 | return uart_remove_one_port(&cpm_reg, &pinfo->port); | |
1331 | } | |
1332 | ||
1333 | static struct of_device_id cpm_uart_match[] = { | |
1334 | { | |
1335 | .compatible = "fsl,cpm1-smc-uart", | |
1336 | }, | |
1337 | { | |
1338 | .compatible = "fsl,cpm1-scc-uart", | |
1339 | }, | |
1340 | { | |
1341 | .compatible = "fsl,cpm2-smc-uart", | |
1342 | }, | |
1343 | { | |
1344 | .compatible = "fsl,cpm2-scc-uart", | |
1345 | }, | |
1346 | {} | |
1da177e4 | 1347 | }; |
7ae87036 SW |
1348 | |
1349 | static struct of_platform_driver cpm_uart_driver = { | |
1350 | .name = "cpm_uart", | |
1351 | .match_table = cpm_uart_match, | |
1352 | .probe = cpm_uart_probe, | |
1353 | .remove = cpm_uart_remove, | |
1354 | }; | |
1355 | ||
1356 | static int __init cpm_uart_init(void) | |
1357 | { | |
1358 | int ret = uart_register_driver(&cpm_reg); | |
1359 | if (ret) | |
1360 | return ret; | |
1361 | ||
1362 | ret = of_register_platform_driver(&cpm_uart_driver); | |
1363 | if (ret) | |
1364 | uart_unregister_driver(&cpm_reg); | |
1365 | ||
1366 | return ret; | |
1367 | } | |
1368 | ||
1369 | static void __exit cpm_uart_exit(void) | |
1370 | { | |
1371 | of_unregister_platform_driver(&cpm_uart_driver); | |
1372 | uart_unregister_driver(&cpm_reg); | |
1373 | } | |
1da177e4 LT |
1374 | |
1375 | module_init(cpm_uart_init); | |
1376 | module_exit(cpm_uart_exit); | |
1377 | ||
1378 | MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); | |
1379 | MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); | |
1380 | MODULE_LICENSE("GPL"); | |
1381 | MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); |