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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/cpm_uart.c | |
3 | * | |
4 | * Driver for CPM (SCC/SMC) serial ports; core driver | |
5 | * | |
6 | * Based on arch/ppc/cpm2_io/uart.c by Dan Malek | |
7 | * Based on ppc8xx.c by Thomas Gleixner | |
8 | * Based on drivers/serial/amba.c by Russell King | |
9 | * | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) |
1da177e4 | 11 | * Pantelis Antoniou (panto@intracom.gr) (CPM1) |
311c4627 | 12 | * |
7ae87036 | 13 | * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. |
1da177e4 | 14 | * (C) 2004 Intracom, S.A. |
6e197696 VB |
15 | * (C) 2005-2006 MontaVista Software, Inc. |
16 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
32 | */ | |
33 | ||
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/tty.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/serial.h> | |
39 | #include <linux/console.h> | |
40 | #include <linux/sysrq.h> | |
41 | #include <linux/device.h> | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dma-mapping.h> | |
e27987cd | 44 | #include <linux/fs_uart_pd.h> |
1da177e4 LT |
45 | |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
48 | #include <asm/delay.h> | |
3dd0dcbe | 49 | #include <asm/fs_pd.h> |
7ae87036 SW |
50 | #include <asm/udbg.h> |
51 | ||
52 | #ifdef CONFIG_PPC_CPM_NEW_BINDING | |
53 | #include <linux/of_platform.h> | |
54 | #endif | |
1da177e4 LT |
55 | |
56 | #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
57 | #define SUPPORT_SYSRQ | |
58 | #endif | |
59 | ||
60 | #include <linux/serial_core.h> | |
61 | #include <linux/kernel.h> | |
62 | ||
63 | #include "cpm_uart.h" | |
64 | ||
1da177e4 LT |
65 | |
66 | /**************************************************************/ | |
67 | ||
68 | static int cpm_uart_tx_pump(struct uart_port *port); | |
69 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); | |
70 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); | |
71 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo); | |
72 | ||
73 | /**************************************************************/ | |
74 | ||
7ae87036 SW |
75 | #ifndef CONFIG_PPC_CPM_NEW_BINDING |
76 | /* Track which ports are configured as uarts */ | |
77 | int cpm_uart_port_map[UART_NR]; | |
78 | /* How many ports did we config as uarts */ | |
79 | int cpm_uart_nr; | |
311c4627 | 80 | |
e27987cd VB |
81 | /* Place-holder for board-specific stuff */ |
82 | struct platform_device* __attribute__ ((weak)) __init | |
83 | early_uart_get_pdev(int index) | |
84 | { | |
85 | return NULL; | |
86 | } | |
87 | ||
88 | ||
6e197696 | 89 | static void cpm_uart_count(void) |
e27987cd VB |
90 | { |
91 | cpm_uart_nr = 0; | |
92 | #ifdef CONFIG_SERIAL_CPM_SMC1 | |
93 | cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1; | |
94 | #endif | |
95 | #ifdef CONFIG_SERIAL_CPM_SMC2 | |
96 | cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2; | |
97 | #endif | |
98 | #ifdef CONFIG_SERIAL_CPM_SCC1 | |
99 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1; | |
100 | #endif | |
101 | #ifdef CONFIG_SERIAL_CPM_SCC2 | |
102 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2; | |
103 | #endif | |
104 | #ifdef CONFIG_SERIAL_CPM_SCC3 | |
105 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3; | |
106 | #endif | |
107 | #ifdef CONFIG_SERIAL_CPM_SCC4 | |
108 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4; | |
109 | #endif | |
110 | } | |
111 | ||
6e197696 VB |
112 | /* Get UART number by its id */ |
113 | static int cpm_uart_id2nr(int id) | |
114 | { | |
115 | int i; | |
116 | if (id < UART_NR) { | |
117 | for (i=0; i<UART_NR; i++) { | |
118 | if (cpm_uart_port_map[i] == id) | |
119 | return i; | |
120 | } | |
121 | } | |
122 | ||
123 | /* not found or invalid argument */ | |
124 | return -1; | |
125 | } | |
7ae87036 | 126 | #endif |
6e197696 | 127 | |
1da177e4 | 128 | /* |
311c4627 | 129 | * Check, if transmit buffers are processed |
1da177e4 LT |
130 | */ |
131 | static unsigned int cpm_uart_tx_empty(struct uart_port *port) | |
132 | { | |
133 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d | 134 | cbd_t __iomem *bdp = pinfo->tx_bd_base; |
1da177e4 LT |
135 | int ret = 0; |
136 | ||
137 | while (1) { | |
c1dcfd9d | 138 | if (in_be16(&bdp->cbd_sc) & BD_SC_READY) |
1da177e4 LT |
139 | break; |
140 | ||
c1dcfd9d | 141 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { |
1da177e4 LT |
142 | ret = TIOCSER_TEMT; |
143 | break; | |
144 | } | |
145 | bdp++; | |
146 | } | |
147 | ||
148 | pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); | |
149 | ||
150 | return ret; | |
151 | } | |
152 | ||
153 | static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
154 | { | |
155 | /* Whee. Do nothing. */ | |
156 | } | |
157 | ||
158 | static unsigned int cpm_uart_get_mctrl(struct uart_port *port) | |
159 | { | |
160 | /* Whee. Do nothing. */ | |
161 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
162 | } | |
163 | ||
164 | /* | |
165 | * Stop transmitter | |
166 | */ | |
b129a8cc | 167 | static void cpm_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
168 | { |
169 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
170 | smc_t __iomem *smcp = pinfo->smcp; |
171 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
172 | |
173 | pr_debug("CPM uart[%d]:stop tx\n", port->line); | |
174 | ||
175 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 176 | clrbits8(&smcp->smc_smcm, SMCM_TX); |
1da177e4 | 177 | else |
c1dcfd9d | 178 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX); |
1da177e4 LT |
179 | } |
180 | ||
181 | /* | |
182 | * Start transmitter | |
183 | */ | |
b129a8cc | 184 | static void cpm_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
185 | { |
186 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
187 | smc_t __iomem *smcp = pinfo->smcp; |
188 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
189 | |
190 | pr_debug("CPM uart[%d]:start tx\n", port->line); | |
191 | ||
192 | if (IS_SMC(pinfo)) { | |
c1dcfd9d | 193 | if (in_8(&smcp->smc_smcm) & SMCM_TX) |
1da177e4 LT |
194 | return; |
195 | } else { | |
c1dcfd9d | 196 | if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) |
1da177e4 LT |
197 | return; |
198 | } | |
199 | ||
200 | if (cpm_uart_tx_pump(port) != 0) { | |
311c4627 | 201 | if (IS_SMC(pinfo)) { |
c1dcfd9d | 202 | setbits8(&smcp->smc_smcm, SMCM_TX); |
311c4627 | 203 | } else { |
c1dcfd9d | 204 | setbits16(&sccp->scc_sccm, UART_SCCM_TX); |
311c4627 | 205 | } |
1da177e4 LT |
206 | } |
207 | } | |
208 | ||
209 | /* | |
311c4627 | 210 | * Stop receiver |
1da177e4 LT |
211 | */ |
212 | static void cpm_uart_stop_rx(struct uart_port *port) | |
213 | { | |
214 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
215 | smc_t __iomem *smcp = pinfo->smcp; |
216 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
217 | |
218 | pr_debug("CPM uart[%d]:stop rx\n", port->line); | |
219 | ||
220 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 221 | clrbits8(&smcp->smc_smcm, SMCM_RX); |
1da177e4 | 222 | else |
c1dcfd9d | 223 | clrbits16(&sccp->scc_sccm, UART_SCCM_RX); |
1da177e4 LT |
224 | } |
225 | ||
226 | /* | |
227 | * Enable Modem status interrupts | |
228 | */ | |
229 | static void cpm_uart_enable_ms(struct uart_port *port) | |
230 | { | |
231 | pr_debug("CPM uart[%d]:enable ms\n", port->line); | |
232 | } | |
233 | ||
234 | /* | |
311c4627 | 235 | * Generate a break. |
1da177e4 LT |
236 | */ |
237 | static void cpm_uart_break_ctl(struct uart_port *port, int break_state) | |
238 | { | |
239 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1da177e4 LT |
240 | |
241 | pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, | |
242 | break_state); | |
243 | ||
244 | if (break_state) | |
7ae87036 | 245 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
1da177e4 | 246 | else |
7ae87036 | 247 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
248 | } |
249 | ||
250 | /* | |
251 | * Transmit characters, refill buffer descriptor, if possible | |
252 | */ | |
7d12e780 | 253 | static void cpm_uart_int_tx(struct uart_port *port) |
1da177e4 LT |
254 | { |
255 | pr_debug("CPM uart[%d]:TX INT\n", port->line); | |
256 | ||
257 | cpm_uart_tx_pump(port); | |
258 | } | |
259 | ||
260 | /* | |
261 | * Receive characters | |
262 | */ | |
7d12e780 | 263 | static void cpm_uart_int_rx(struct uart_port *port) |
1da177e4 LT |
264 | { |
265 | int i; | |
c1dcfd9d SW |
266 | unsigned char ch; |
267 | u8 *cp; | |
1da177e4 LT |
268 | struct tty_struct *tty = port->info->tty; |
269 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d | 270 | cbd_t __iomem *bdp; |
1da177e4 LT |
271 | u16 status; |
272 | unsigned int flg; | |
273 | ||
274 | pr_debug("CPM uart[%d]:RX INT\n", port->line); | |
275 | ||
276 | /* Just loop through the closed BDs and copy the characters into | |
277 | * the buffer. | |
278 | */ | |
279 | bdp = pinfo->rx_cur; | |
280 | for (;;) { | |
281 | /* get status */ | |
c1dcfd9d | 282 | status = in_be16(&bdp->cbd_sc); |
1da177e4 LT |
283 | /* If this one is empty, return happy */ |
284 | if (status & BD_SC_EMPTY) | |
285 | break; | |
286 | ||
287 | /* get number of characters, and check spce in flip-buffer */ | |
c1dcfd9d | 288 | i = in_be16(&bdp->cbd_datlen); |
1da177e4 | 289 | |
311c4627 | 290 | /* If we have not enough room in tty flip buffer, then we try |
1da177e4 LT |
291 | * later, which will be the next rx-interrupt or a timeout |
292 | */ | |
76a55431 VB |
293 | if(tty_buffer_request_room(tty, i) < i) { |
294 | printk(KERN_WARNING "No room in flip buffer\n"); | |
295 | return; | |
1da177e4 LT |
296 | } |
297 | ||
298 | /* get pointer */ | |
c1dcfd9d | 299 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
300 | |
301 | /* loop through the buffer */ | |
302 | while (i-- > 0) { | |
303 | ch = *cp++; | |
304 | port->icount.rx++; | |
305 | flg = TTY_NORMAL; | |
306 | ||
307 | if (status & | |
308 | (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) | |
309 | goto handle_error; | |
7d12e780 | 310 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 LT |
311 | continue; |
312 | ||
313 | error_return: | |
76a55431 | 314 | tty_insert_flip_char(tty, ch, flg); |
1da177e4 LT |
315 | |
316 | } /* End while (i--) */ | |
317 | ||
318 | /* This BD is ready to be used again. Clear status. get next */ | |
c1dcfd9d SW |
319 | clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | |
320 | BD_SC_OV | BD_SC_ID); | |
321 | setbits16(&bdp->cbd_sc, BD_SC_EMPTY); | |
1da177e4 | 322 | |
c1dcfd9d | 323 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
324 | bdp = pinfo->rx_bd_base; |
325 | else | |
326 | bdp++; | |
311c4627 | 327 | |
1da177e4 LT |
328 | } /* End for (;;) */ |
329 | ||
330 | /* Write back buffer pointer */ | |
c1dcfd9d | 331 | pinfo->rx_cur = bdp; |
1da177e4 LT |
332 | |
333 | /* activate BH processing */ | |
334 | tty_flip_buffer_push(tty); | |
335 | ||
336 | return; | |
337 | ||
338 | /* Error processing */ | |
339 | ||
340 | handle_error: | |
341 | /* Statistics */ | |
342 | if (status & BD_SC_BR) | |
343 | port->icount.brk++; | |
344 | if (status & BD_SC_PR) | |
345 | port->icount.parity++; | |
346 | if (status & BD_SC_FR) | |
347 | port->icount.frame++; | |
348 | if (status & BD_SC_OV) | |
349 | port->icount.overrun++; | |
350 | ||
351 | /* Mask out ignored conditions */ | |
352 | status &= port->read_status_mask; | |
353 | ||
354 | /* Handle the remaining ones */ | |
355 | if (status & BD_SC_BR) | |
356 | flg = TTY_BREAK; | |
357 | else if (status & BD_SC_PR) | |
358 | flg = TTY_PARITY; | |
359 | else if (status & BD_SC_FR) | |
360 | flg = TTY_FRAME; | |
361 | ||
362 | /* overrun does not affect the current character ! */ | |
363 | if (status & BD_SC_OV) { | |
364 | ch = 0; | |
365 | flg = TTY_OVERRUN; | |
366 | /* We skip this buffer */ | |
367 | /* CHECK: Is really nothing senseful there */ | |
368 | /* ASSUMPTION: it contains nothing valid */ | |
369 | i = 0; | |
370 | } | |
371 | #ifdef SUPPORT_SYSRQ | |
372 | port->sysrq = 0; | |
373 | #endif | |
374 | goto error_return; | |
375 | } | |
376 | ||
377 | /* | |
378 | * Asynchron mode interrupt handler | |
379 | */ | |
7d12e780 | 380 | static irqreturn_t cpm_uart_int(int irq, void *data) |
1da177e4 LT |
381 | { |
382 | u8 events; | |
383 | struct uart_port *port = (struct uart_port *)data; | |
384 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
385 | smc_t __iomem *smcp = pinfo->smcp; |
386 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
387 | |
388 | pr_debug("CPM uart[%d]:IRQ\n", port->line); | |
389 | ||
390 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
391 | events = in_8(&smcp->smc_smce); |
392 | out_8(&smcp->smc_smce, events); | |
1da177e4 LT |
393 | if (events & SMCM_BRKE) |
394 | uart_handle_break(port); | |
395 | if (events & SMCM_RX) | |
7d12e780 | 396 | cpm_uart_int_rx(port); |
1da177e4 | 397 | if (events & SMCM_TX) |
7d12e780 | 398 | cpm_uart_int_tx(port); |
1da177e4 | 399 | } else { |
c1dcfd9d SW |
400 | events = in_be16(&sccp->scc_scce); |
401 | out_be16(&sccp->scc_scce, events); | |
1da177e4 LT |
402 | if (events & UART_SCCM_BRKE) |
403 | uart_handle_break(port); | |
404 | if (events & UART_SCCM_RX) | |
7d12e780 | 405 | cpm_uart_int_rx(port); |
1da177e4 | 406 | if (events & UART_SCCM_TX) |
7d12e780 | 407 | cpm_uart_int_tx(port); |
1da177e4 LT |
408 | } |
409 | return (events) ? IRQ_HANDLED : IRQ_NONE; | |
410 | } | |
411 | ||
412 | static int cpm_uart_startup(struct uart_port *port) | |
413 | { | |
414 | int retval; | |
415 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
416 | ||
417 | pr_debug("CPM uart[%d]:startup\n", port->line); | |
418 | ||
419 | /* Install interrupt handler. */ | |
420 | retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); | |
421 | if (retval) | |
422 | return retval; | |
423 | ||
424 | /* Startup rx-int */ | |
425 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
426 | setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); |
427 | setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); | |
1da177e4 | 428 | } else { |
c1dcfd9d SW |
429 | setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); |
430 | setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); | |
1da177e4 LT |
431 | } |
432 | ||
311c4627 | 433 | if (!(pinfo->flags & FLAG_CONSOLE)) |
7ae87036 | 434 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
435 | return 0; |
436 | } | |
437 | ||
311c4627 KG |
438 | inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) |
439 | { | |
638861d5 KG |
440 | set_current_state(TASK_UNINTERRUPTIBLE); |
441 | schedule_timeout(pinfo->wait_closing); | |
311c4627 KG |
442 | } |
443 | ||
1da177e4 LT |
444 | /* |
445 | * Shutdown the uart | |
446 | */ | |
447 | static void cpm_uart_shutdown(struct uart_port *port) | |
448 | { | |
449 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1da177e4 LT |
450 | |
451 | pr_debug("CPM uart[%d]:shutdown\n", port->line); | |
452 | ||
453 | /* free interrupt handler */ | |
454 | free_irq(port->irq, port); | |
455 | ||
456 | /* If the port is not the console, disable Rx and Tx. */ | |
457 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
311c4627 | 458 | /* Wait for all the BDs marked sent */ |
638861d5 KG |
459 | while(!cpm_uart_tx_empty(port)) { |
460 | set_current_state(TASK_UNINTERRUPTIBLE); | |
311c4627 | 461 | schedule_timeout(2); |
638861d5 KG |
462 | } |
463 | ||
464 | if (pinfo->wait_closing) | |
311c4627 KG |
465 | cpm_uart_wait_until_send(pinfo); |
466 | ||
1da177e4 LT |
467 | /* Stop uarts */ |
468 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
469 | smc_t __iomem *smcp = pinfo->smcp; |
470 | clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
471 | clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); | |
1da177e4 | 472 | } else { |
c1dcfd9d SW |
473 | scc_t __iomem *sccp = pinfo->sccp; |
474 | clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
475 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); | |
1da177e4 LT |
476 | } |
477 | ||
478 | /* Shut them really down and reinit buffer descriptors */ | |
61f5657c | 479 | if (IS_SMC(pinfo)) |
7ae87036 | 480 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
61f5657c | 481 | else |
7ae87036 | 482 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); |
61f5657c | 483 | |
1da177e4 LT |
484 | cpm_uart_initbd(pinfo); |
485 | } | |
486 | } | |
487 | ||
488 | static void cpm_uart_set_termios(struct uart_port *port, | |
1bda8f30 SW |
489 | struct ktermios *termios, |
490 | struct ktermios *old) | |
1da177e4 LT |
491 | { |
492 | int baud; | |
493 | unsigned long flags; | |
494 | u16 cval, scval, prev_mode; | |
495 | int bits, sbits; | |
496 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
497 | smc_t __iomem *smcp = pinfo->smcp; |
498 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
499 | |
500 | pr_debug("CPM uart[%d]:set_termios\n", port->line); | |
501 | ||
502 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
503 | ||
504 | /* Character length programmed into the mode register is the | |
505 | * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, | |
506 | * 1 or 2 stop bits, minus 1. | |
507 | * The value 'bits' counts this for us. | |
508 | */ | |
509 | cval = 0; | |
510 | scval = 0; | |
511 | ||
512 | /* byte size */ | |
513 | switch (termios->c_cflag & CSIZE) { | |
514 | case CS5: | |
515 | bits = 5; | |
516 | break; | |
517 | case CS6: | |
518 | bits = 6; | |
519 | break; | |
520 | case CS7: | |
521 | bits = 7; | |
522 | break; | |
523 | case CS8: | |
524 | bits = 8; | |
525 | break; | |
526 | /* Never happens, but GCC is too dumb to figure it out */ | |
527 | default: | |
528 | bits = 8; | |
529 | break; | |
530 | } | |
531 | sbits = bits - 5; | |
532 | ||
533 | if (termios->c_cflag & CSTOPB) { | |
534 | cval |= SMCMR_SL; /* Two stops */ | |
535 | scval |= SCU_PSMR_SL; | |
536 | bits++; | |
537 | } | |
538 | ||
539 | if (termios->c_cflag & PARENB) { | |
540 | cval |= SMCMR_PEN; | |
541 | scval |= SCU_PSMR_PEN; | |
542 | bits++; | |
543 | if (!(termios->c_cflag & PARODD)) { | |
544 | cval |= SMCMR_PM_EVEN; | |
545 | scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); | |
546 | } | |
547 | } | |
548 | ||
549 | /* | |
550 | * Set up parity check flag | |
551 | */ | |
552 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) | |
553 | ||
554 | port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); | |
555 | if (termios->c_iflag & INPCK) | |
556 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; | |
557 | if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) | |
558 | port->read_status_mask |= BD_SC_BR; | |
559 | ||
560 | /* | |
561 | * Characters to ignore | |
562 | */ | |
563 | port->ignore_status_mask = 0; | |
564 | if (termios->c_iflag & IGNPAR) | |
565 | port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; | |
566 | if (termios->c_iflag & IGNBRK) { | |
567 | port->ignore_status_mask |= BD_SC_BR; | |
568 | /* | |
569 | * If we're ignore parity and break indicators, ignore | |
570 | * overruns too. (For real raw support). | |
571 | */ | |
572 | if (termios->c_iflag & IGNPAR) | |
573 | port->ignore_status_mask |= BD_SC_OV; | |
574 | } | |
575 | /* | |
576 | * !!! ignore all characters if CREAD is not set | |
577 | */ | |
578 | if ((termios->c_cflag & CREAD) == 0) | |
579 | port->read_status_mask &= ~BD_SC_EMPTY; | |
311c4627 | 580 | |
1da177e4 LT |
581 | spin_lock_irqsave(&port->lock, flags); |
582 | ||
583 | /* Start bit has not been added (so don't, because we would just | |
584 | * subtract it later), and we need to add one for the number of | |
585 | * stops bits (there is always at least one). | |
586 | */ | |
587 | bits++; | |
588 | if (IS_SMC(pinfo)) { | |
589 | /* Set the mode register. We want to keep a copy of the | |
590 | * enables, because we want to put them back if they were | |
591 | * present. | |
592 | */ | |
c1dcfd9d SW |
593 | prev_mode = in_be16(&smcp->smc_smcmr); |
594 | out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | SMCMR_SM_UART); | |
595 | setbits16(&smcp->smc_smcmr, (prev_mode & (SMCMR_REN | SMCMR_TEN))); | |
1da177e4 | 596 | } else { |
c1dcfd9d | 597 | out_be16(&sccp->scc_psmr, (sbits << 12) | scval); |
1da177e4 LT |
598 | } |
599 | ||
600 | cpm_set_brg(pinfo->brg - 1, baud); | |
601 | spin_unlock_irqrestore(&port->lock, flags); | |
1da177e4 LT |
602 | } |
603 | ||
604 | static const char *cpm_uart_type(struct uart_port *port) | |
605 | { | |
606 | pr_debug("CPM uart[%d]:uart_type\n", port->line); | |
607 | ||
608 | return port->type == PORT_CPM ? "CPM UART" : NULL; | |
609 | } | |
610 | ||
611 | /* | |
612 | * verify the new serial_struct (for TIOCSSERIAL). | |
613 | */ | |
614 | static int cpm_uart_verify_port(struct uart_port *port, | |
615 | struct serial_struct *ser) | |
616 | { | |
617 | int ret = 0; | |
618 | ||
619 | pr_debug("CPM uart[%d]:verify_port\n", port->line); | |
620 | ||
621 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) | |
622 | ret = -EINVAL; | |
623 | if (ser->irq < 0 || ser->irq >= NR_IRQS) | |
624 | ret = -EINVAL; | |
625 | if (ser->baud_base < 9600) | |
626 | ret = -EINVAL; | |
627 | return ret; | |
628 | } | |
629 | ||
630 | /* | |
631 | * Transmit characters, refill buffer descriptor, if possible | |
632 | */ | |
633 | static int cpm_uart_tx_pump(struct uart_port *port) | |
634 | { | |
c1dcfd9d SW |
635 | cbd_t __iomem *bdp; |
636 | u8 *p; | |
1da177e4 LT |
637 | int count; |
638 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
639 | struct circ_buf *xmit = &port->info->xmit; | |
640 | ||
641 | /* Handle xon/xoff */ | |
642 | if (port->x_char) { | |
643 | /* Pick next descriptor and fill from buffer */ | |
644 | bdp = pinfo->tx_cur; | |
645 | ||
c1dcfd9d | 646 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
311c4627 | 647 | |
03929c76 | 648 | *p++ = port->x_char; |
c1dcfd9d SW |
649 | |
650 | out_be16(&bdp->cbd_datlen, 1); | |
651 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 652 | /* Get next BD. */ |
c1dcfd9d | 653 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
654 | bdp = pinfo->tx_bd_base; |
655 | else | |
656 | bdp++; | |
657 | pinfo->tx_cur = bdp; | |
658 | ||
659 | port->icount.tx++; | |
660 | port->x_char = 0; | |
661 | return 1; | |
662 | } | |
663 | ||
664 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 665 | cpm_uart_stop_tx(port); |
1da177e4 LT |
666 | return 0; |
667 | } | |
668 | ||
669 | /* Pick next descriptor and fill from buffer */ | |
670 | bdp = pinfo->tx_cur; | |
671 | ||
c1dcfd9d SW |
672 | while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && |
673 | xmit->tail != xmit->head) { | |
1da177e4 | 674 | count = 0; |
c1dcfd9d | 675 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
676 | while (count < pinfo->tx_fifosize) { |
677 | *p++ = xmit->buf[xmit->tail]; | |
678 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
679 | port->icount.tx++; | |
680 | count++; | |
681 | if (xmit->head == xmit->tail) | |
682 | break; | |
683 | } | |
c1dcfd9d SW |
684 | out_be16(&bdp->cbd_datlen, count); |
685 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 686 | /* Get next BD. */ |
c1dcfd9d | 687 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
688 | bdp = pinfo->tx_bd_base; |
689 | else | |
690 | bdp++; | |
691 | } | |
692 | pinfo->tx_cur = bdp; | |
693 | ||
694 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
695 | uart_write_wakeup(port); | |
696 | ||
697 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 698 | cpm_uart_stop_tx(port); |
1da177e4 LT |
699 | return 0; |
700 | } | |
701 | ||
702 | return 1; | |
703 | } | |
704 | ||
705 | /* | |
706 | * init buffer descriptors | |
707 | */ | |
708 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo) | |
709 | { | |
710 | int i; | |
711 | u8 *mem_addr; | |
c1dcfd9d | 712 | cbd_t __iomem *bdp; |
1da177e4 LT |
713 | |
714 | pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); | |
715 | ||
716 | /* Set the physical address of the host memory | |
717 | * buffers in the buffer descriptors, and the | |
718 | * virtual address for us to work with. | |
719 | */ | |
720 | mem_addr = pinfo->mem_addr; | |
721 | bdp = pinfo->rx_cur = pinfo->rx_bd_base; | |
722 | for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
723 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
724 | out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
725 | mem_addr += pinfo->rx_fifosize; |
726 | } | |
311c4627 | 727 | |
c1dcfd9d SW |
728 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
729 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
730 | |
731 | /* Set the physical address of the host memory | |
732 | * buffers in the buffer descriptors, and the | |
733 | * virtual address for us to work with. | |
734 | */ | |
735 | mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); | |
736 | bdp = pinfo->tx_cur = pinfo->tx_bd_base; | |
737 | for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
738 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
739 | out_be16(&bdp->cbd_sc, BD_SC_INTRPT); | |
1da177e4 LT |
740 | mem_addr += pinfo->tx_fifosize; |
741 | } | |
311c4627 | 742 | |
c1dcfd9d SW |
743 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
744 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); | |
1da177e4 LT |
745 | } |
746 | ||
747 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) | |
748 | { | |
c1dcfd9d SW |
749 | scc_t __iomem *scp; |
750 | scc_uart_t __iomem *sup; | |
1da177e4 LT |
751 | |
752 | pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); | |
753 | ||
754 | scp = pinfo->sccp; | |
755 | sup = pinfo->sccup; | |
756 | ||
757 | /* Store address */ | |
c1dcfd9d SW |
758 | out_be16(&pinfo->sccup->scc_genscc.scc_rbase, |
759 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
760 | out_be16(&pinfo->sccup->scc_genscc.scc_tbase, | |
761 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
762 | |
763 | /* Set up the uart parameters in the | |
764 | * parameter ram. | |
765 | */ | |
766 | ||
767 | cpm_set_scc_fcr(sup); | |
768 | ||
c1dcfd9d SW |
769 | out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); |
770 | out_be16(&sup->scc_maxidl, pinfo->rx_fifosize); | |
771 | out_be16(&sup->scc_brkcr, 1); | |
772 | out_be16(&sup->scc_parec, 0); | |
773 | out_be16(&sup->scc_frmec, 0); | |
774 | out_be16(&sup->scc_nosec, 0); | |
775 | out_be16(&sup->scc_brkec, 0); | |
776 | out_be16(&sup->scc_uaddr1, 0); | |
777 | out_be16(&sup->scc_uaddr2, 0); | |
778 | out_be16(&sup->scc_toseq, 0); | |
779 | out_be16(&sup->scc_char1, 0x8000); | |
780 | out_be16(&sup->scc_char2, 0x8000); | |
781 | out_be16(&sup->scc_char3, 0x8000); | |
782 | out_be16(&sup->scc_char4, 0x8000); | |
783 | out_be16(&sup->scc_char5, 0x8000); | |
784 | out_be16(&sup->scc_char6, 0x8000); | |
785 | out_be16(&sup->scc_char7, 0x8000); | |
786 | out_be16(&sup->scc_char8, 0x8000); | |
787 | out_be16(&sup->scc_rccm, 0xc0ff); | |
1da177e4 LT |
788 | |
789 | /* Send the CPM an initialize command. | |
790 | */ | |
7ae87036 | 791 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
792 | |
793 | /* Set UART mode, 8 bit, no parity, one stop. | |
794 | * Enable receive and transmit. | |
795 | */ | |
c1dcfd9d SW |
796 | out_be32(&scp->scc_gsmrh, 0); |
797 | out_be32(&scp->scc_gsmrl, | |
798 | SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
1da177e4 LT |
799 | |
800 | /* Enable rx interrupts and clear all pending events. */ | |
c1dcfd9d SW |
801 | out_be16(&scp->scc_sccm, 0); |
802 | out_be16(&scp->scc_scce, 0xffff); | |
803 | out_be16(&scp->scc_dsr, 0x7e7e); | |
804 | out_be16(&scp->scc_psmr, 0x3000); | |
1da177e4 | 805 | |
c1dcfd9d | 806 | setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
1da177e4 LT |
807 | } |
808 | ||
809 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) | |
810 | { | |
c1dcfd9d SW |
811 | smc_t __iomem *sp; |
812 | smc_uart_t __iomem *up; | |
1da177e4 LT |
813 | |
814 | pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); | |
815 | ||
816 | sp = pinfo->smcp; | |
817 | up = pinfo->smcup; | |
818 | ||
819 | /* Store address */ | |
c1dcfd9d SW |
820 | out_be16(&pinfo->smcup->smc_rbase, |
821 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
822 | out_be16(&pinfo->smcup->smc_tbase, | |
823 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
824 | |
825 | /* | |
826 | * In case SMC1 is being relocated... | |
827 | */ | |
828 | #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) | |
c1dcfd9d SW |
829 | out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); |
830 | out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); | |
831 | out_be32(&up->smc_rstate, 0); | |
832 | out_be32(&up->smc_tstate, 0); | |
833 | out_be16(&up->smc_brkcr, 1); /* number of break chars */ | |
834 | out_be16(&up->smc_brkec, 0); | |
1da177e4 LT |
835 | #endif |
836 | ||
837 | /* Set up the uart parameters in the | |
838 | * parameter ram. | |
839 | */ | |
840 | cpm_set_smc_fcr(up); | |
841 | ||
842 | /* Using idle charater time requires some additional tuning. */ | |
c1dcfd9d SW |
843 | out_be16(&up->smc_mrblr, pinfo->rx_fifosize); |
844 | out_be16(&up->smc_maxidl, pinfo->rx_fifosize); | |
845 | out_be16(&up->smc_brklen, 0); | |
846 | out_be16(&up->smc_brkec, 0); | |
847 | out_be16(&up->smc_brkcr, 1); | |
1da177e4 | 848 | |
7ae87036 | 849 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
850 | |
851 | /* Set UART mode, 8 bit, no parity, one stop. | |
852 | * Enable receive and transmit. | |
853 | */ | |
c1dcfd9d | 854 | out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); |
1da177e4 LT |
855 | |
856 | /* Enable only rx interrupts clear all pending events. */ | |
c1dcfd9d SW |
857 | out_8(&sp->smc_smcm, 0); |
858 | out_8(&sp->smc_smce, 0xff); | |
1da177e4 | 859 | |
c1dcfd9d | 860 | setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); |
1da177e4 LT |
861 | } |
862 | ||
863 | /* | |
864 | * Initialize port. This is called from early_console stuff | |
865 | * so we have to be careful here ! | |
866 | */ | |
867 | static int cpm_uart_request_port(struct uart_port *port) | |
868 | { | |
869 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
870 | int ret; | |
871 | ||
872 | pr_debug("CPM uart[%d]:request port\n", port->line); | |
873 | ||
874 | if (pinfo->flags & FLAG_CONSOLE) | |
875 | return 0; | |
876 | ||
1da177e4 | 877 | if (IS_SMC(pinfo)) { |
c1dcfd9d SW |
878 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
879 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 880 | } else { |
c1dcfd9d SW |
881 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
882 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
883 | } |
884 | ||
885 | ret = cpm_uart_allocbuf(pinfo, 0); | |
886 | ||
887 | if (ret) | |
888 | return ret; | |
889 | ||
890 | cpm_uart_initbd(pinfo); | |
311c4627 KG |
891 | if (IS_SMC(pinfo)) |
892 | cpm_uart_init_smc(pinfo); | |
893 | else | |
894 | cpm_uart_init_scc(pinfo); | |
1da177e4 LT |
895 | |
896 | return 0; | |
897 | } | |
898 | ||
899 | static void cpm_uart_release_port(struct uart_port *port) | |
900 | { | |
901 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
902 | ||
903 | if (!(pinfo->flags & FLAG_CONSOLE)) | |
904 | cpm_uart_freebuf(pinfo); | |
905 | } | |
906 | ||
907 | /* | |
908 | * Configure/autoconfigure the port. | |
909 | */ | |
910 | static void cpm_uart_config_port(struct uart_port *port, int flags) | |
911 | { | |
912 | pr_debug("CPM uart[%d]:config_port\n", port->line); | |
913 | ||
914 | if (flags & UART_CONFIG_TYPE) { | |
915 | port->type = PORT_CPM; | |
916 | cpm_uart_request_port(port); | |
917 | } | |
918 | } | |
919 | static struct uart_ops cpm_uart_pops = { | |
920 | .tx_empty = cpm_uart_tx_empty, | |
921 | .set_mctrl = cpm_uart_set_mctrl, | |
922 | .get_mctrl = cpm_uart_get_mctrl, | |
923 | .stop_tx = cpm_uart_stop_tx, | |
924 | .start_tx = cpm_uart_start_tx, | |
925 | .stop_rx = cpm_uart_stop_rx, | |
926 | .enable_ms = cpm_uart_enable_ms, | |
927 | .break_ctl = cpm_uart_break_ctl, | |
928 | .startup = cpm_uart_startup, | |
929 | .shutdown = cpm_uart_shutdown, | |
930 | .set_termios = cpm_uart_set_termios, | |
931 | .type = cpm_uart_type, | |
932 | .release_port = cpm_uart_release_port, | |
933 | .request_port = cpm_uart_request_port, | |
934 | .config_port = cpm_uart_config_port, | |
935 | .verify_port = cpm_uart_verify_port, | |
936 | }; | |
937 | ||
7ae87036 SW |
938 | #ifdef CONFIG_PPC_CPM_NEW_BINDING |
939 | struct uart_cpm_port cpm_uart_ports[UART_NR]; | |
940 | ||
c1dcfd9d SW |
941 | static int cpm_uart_init_port(struct device_node *np, |
942 | struct uart_cpm_port *pinfo) | |
7ae87036 SW |
943 | { |
944 | const u32 *data; | |
c1dcfd9d | 945 | void __iomem *mem, *pram; |
7ae87036 SW |
946 | int len; |
947 | int ret; | |
948 | ||
949 | data = of_get_property(np, "fsl,cpm-brg", &len); | |
950 | if (!data || len != 4) { | |
951 | printk(KERN_ERR "CPM UART %s has no/invalid " | |
952 | "fsl,cpm-brg property.\n", np->name); | |
953 | return -EINVAL; | |
954 | } | |
955 | pinfo->brg = *data; | |
956 | ||
957 | data = of_get_property(np, "fsl,cpm-command", &len); | |
958 | if (!data || len != 4) { | |
959 | printk(KERN_ERR "CPM UART %s has no/invalid " | |
960 | "fsl,cpm-command property.\n", np->name); | |
961 | return -EINVAL; | |
962 | } | |
963 | pinfo->command = *data; | |
964 | ||
965 | mem = of_iomap(np, 0); | |
966 | if (!mem) | |
967 | return -ENOMEM; | |
968 | ||
969 | pram = of_iomap(np, 1); | |
970 | if (!pram) { | |
971 | ret = -ENOMEM; | |
972 | goto out_mem; | |
973 | } | |
974 | ||
975 | if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || | |
976 | of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { | |
977 | pinfo->sccp = mem; | |
978 | pinfo->sccup = pram; | |
979 | } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || | |
980 | of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { | |
981 | pinfo->flags |= FLAG_SMC; | |
982 | pinfo->smcp = mem; | |
983 | pinfo->smcup = pram; | |
984 | } else { | |
985 | ret = -ENODEV; | |
986 | goto out_pram; | |
987 | } | |
988 | ||
989 | pinfo->tx_nrfifos = TX_NUM_FIFO; | |
990 | pinfo->tx_fifosize = TX_BUF_SIZE; | |
991 | pinfo->rx_nrfifos = RX_NUM_FIFO; | |
992 | pinfo->rx_fifosize = RX_BUF_SIZE; | |
993 | ||
994 | pinfo->port.uartclk = ppc_proc_freq; | |
995 | pinfo->port.mapbase = (unsigned long)mem; | |
996 | pinfo->port.type = PORT_CPM; | |
997 | pinfo->port.ops = &cpm_uart_pops, | |
998 | pinfo->port.iotype = UPIO_MEM; | |
999 | spin_lock_init(&pinfo->port.lock); | |
1000 | ||
1001 | pinfo->port.irq = of_irq_to_resource(np, 0, NULL); | |
1002 | if (pinfo->port.irq == NO_IRQ) { | |
1003 | ret = -EINVAL; | |
1004 | goto out_pram; | |
1005 | } | |
1006 | ||
1007 | return cpm_uart_request_port(&pinfo->port); | |
1008 | ||
1009 | out_pram: | |
1010 | iounmap(pram); | |
1011 | out_mem: | |
1012 | iounmap(mem); | |
1013 | return ret; | |
1014 | } | |
1015 | ||
1016 | #else | |
1017 | ||
1da177e4 LT |
1018 | struct uart_cpm_port cpm_uart_ports[UART_NR] = { |
1019 | [UART_SMC1] = { | |
1020 | .port = { | |
1021 | .irq = SMC1_IRQ, | |
1022 | .ops = &cpm_uart_pops, | |
9b4a1617 | 1023 | .iotype = UPIO_MEM, |
076fa0fa | 1024 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SMC1].port.lock), |
1da177e4 LT |
1025 | }, |
1026 | .flags = FLAG_SMC, | |
1027 | .tx_nrfifos = TX_NUM_FIFO, | |
1028 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 1029 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
1030 | .rx_fifosize = RX_BUF_SIZE, |
1031 | .set_lineif = smc1_lineif, | |
1032 | }, | |
1033 | [UART_SMC2] = { | |
1034 | .port = { | |
1035 | .irq = SMC2_IRQ, | |
1036 | .ops = &cpm_uart_pops, | |
9b4a1617 | 1037 | .iotype = UPIO_MEM, |
076fa0fa | 1038 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SMC2].port.lock), |
1da177e4 LT |
1039 | }, |
1040 | .flags = FLAG_SMC, | |
1041 | .tx_nrfifos = TX_NUM_FIFO, | |
1042 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 1043 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
1044 | .rx_fifosize = RX_BUF_SIZE, |
1045 | .set_lineif = smc2_lineif, | |
1046 | #ifdef CONFIG_SERIAL_CPM_ALT_SMC2 | |
1047 | .is_portb = 1, | |
1048 | #endif | |
1049 | }, | |
1050 | [UART_SCC1] = { | |
1051 | .port = { | |
1052 | .irq = SCC1_IRQ, | |
1053 | .ops = &cpm_uart_pops, | |
9b4a1617 | 1054 | .iotype = UPIO_MEM, |
076fa0fa | 1055 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SCC1].port.lock), |
1da177e4 LT |
1056 | }, |
1057 | .tx_nrfifos = TX_NUM_FIFO, | |
1058 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 1059 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
1060 | .rx_fifosize = RX_BUF_SIZE, |
1061 | .set_lineif = scc1_lineif, | |
311c4627 | 1062 | .wait_closing = SCC_WAIT_CLOSING, |
1da177e4 LT |
1063 | }, |
1064 | [UART_SCC2] = { | |
1065 | .port = { | |
1066 | .irq = SCC2_IRQ, | |
1067 | .ops = &cpm_uart_pops, | |
9b4a1617 | 1068 | .iotype = UPIO_MEM, |
076fa0fa | 1069 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SCC2].port.lock), |
1da177e4 LT |
1070 | }, |
1071 | .tx_nrfifos = TX_NUM_FIFO, | |
1072 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 1073 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
1074 | .rx_fifosize = RX_BUF_SIZE, |
1075 | .set_lineif = scc2_lineif, | |
311c4627 | 1076 | .wait_closing = SCC_WAIT_CLOSING, |
1da177e4 LT |
1077 | }, |
1078 | [UART_SCC3] = { | |
1079 | .port = { | |
1080 | .irq = SCC3_IRQ, | |
1081 | .ops = &cpm_uart_pops, | |
9b4a1617 | 1082 | .iotype = UPIO_MEM, |
076fa0fa | 1083 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SCC3].port.lock), |
1da177e4 LT |
1084 | }, |
1085 | .tx_nrfifos = TX_NUM_FIFO, | |
1086 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 1087 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
1088 | .rx_fifosize = RX_BUF_SIZE, |
1089 | .set_lineif = scc3_lineif, | |
311c4627 | 1090 | .wait_closing = SCC_WAIT_CLOSING, |
1da177e4 LT |
1091 | }, |
1092 | [UART_SCC4] = { | |
1093 | .port = { | |
1094 | .irq = SCC4_IRQ, | |
1095 | .ops = &cpm_uart_pops, | |
9b4a1617 | 1096 | .iotype = UPIO_MEM, |
076fa0fa | 1097 | .lock = __SPIN_LOCK_UNLOCKED(cpm_uart_ports[UART_SCC4].port.lock), |
1da177e4 LT |
1098 | }, |
1099 | .tx_nrfifos = TX_NUM_FIFO, | |
1100 | .tx_fifosize = TX_BUF_SIZE, | |
311c4627 | 1101 | .rx_nrfifos = RX_NUM_FIFO, |
1da177e4 LT |
1102 | .rx_fifosize = RX_BUF_SIZE, |
1103 | .set_lineif = scc4_lineif, | |
311c4627 | 1104 | .wait_closing = SCC_WAIT_CLOSING, |
1da177e4 LT |
1105 | }, |
1106 | }; | |
1107 | ||
e27987cd VB |
1108 | int cpm_uart_drv_get_platform_data(struct platform_device *pdev, int is_con) |
1109 | { | |
1110 | struct resource *r; | |
1111 | struct fs_uart_platform_info *pdata = pdev->dev.platform_data; | |
611a15af | 1112 | int idx; /* It is UART_SMCx or UART_SCCx index */ |
e27987cd VB |
1113 | struct uart_cpm_port *pinfo; |
1114 | int line; | |
1115 | u32 mem, pram; | |
1116 | ||
611a15af VB |
1117 | idx = pdata->fs_no = fs_uart_get_id(pdata); |
1118 | ||
6e197696 VB |
1119 | line = cpm_uart_id2nr(idx); |
1120 | if(line < 0) { | |
1121 | printk(KERN_ERR"%s(): port %d is not registered", __FUNCTION__, idx); | |
611a15af | 1122 | return -EINVAL; |
6e197696 | 1123 | } |
e27987cd VB |
1124 | |
1125 | pinfo = (struct uart_cpm_port *) &cpm_uart_ports[idx]; | |
1126 | ||
1127 | pinfo->brg = pdata->brg; | |
1128 | ||
1129 | if (!is_con) { | |
1130 | pinfo->port.line = line; | |
1131 | pinfo->port.flags = UPF_BOOT_AUTOCONF; | |
1132 | } | |
1133 | ||
1134 | if (!(r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"))) | |
1135 | return -EINVAL; | |
3dd0dcbe | 1136 | mem = (u32)ioremap(r->start, r->end - r->start + 1); |
e27987cd VB |
1137 | |
1138 | if (!(r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pram"))) | |
1139 | return -EINVAL; | |
3dd0dcbe | 1140 | pram = (u32)ioremap(r->start, r->end - r->start + 1); |
e27987cd VB |
1141 | |
1142 | if(idx > fsid_smc2_uart) { | |
1143 | pinfo->sccp = (scc_t *)mem; | |
1144 | pinfo->sccup = (scc_uart_t *)pram; | |
1145 | } else { | |
1146 | pinfo->smcp = (smc_t *)mem; | |
1147 | pinfo->smcup = (smc_uart_t *)pram; | |
1148 | } | |
1149 | pinfo->tx_nrfifos = pdata->tx_num_fifo; | |
1150 | pinfo->tx_fifosize = pdata->tx_buf_size; | |
1151 | ||
1152 | pinfo->rx_nrfifos = pdata->rx_num_fifo; | |
1153 | pinfo->rx_fifosize = pdata->rx_buf_size; | |
1154 | ||
1155 | pinfo->port.uartclk = pdata->uart_clk; | |
1156 | pinfo->port.mapbase = (unsigned long)mem; | |
1157 | pinfo->port.irq = platform_get_irq(pdev, 0); | |
1158 | ||
1159 | return 0; | |
1160 | } | |
7ae87036 | 1161 | #endif |
e27987cd | 1162 | |
1da177e4 LT |
1163 | #ifdef CONFIG_SERIAL_CPM_CONSOLE |
1164 | /* | |
1165 | * Print a string to the serial port trying not to disturb | |
1166 | * any possible real use of the port... | |
1167 | * | |
1168 | * Note that this is called with interrupts already disabled | |
1169 | */ | |
1170 | static void cpm_uart_console_write(struct console *co, const char *s, | |
1171 | u_int count) | |
1172 | { | |
7ae87036 SW |
1173 | #ifdef CONFIG_PPC_CPM_NEW_BINDING |
1174 | struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; | |
1175 | #else | |
1da177e4 LT |
1176 | struct uart_cpm_port *pinfo = |
1177 | &cpm_uart_ports[cpm_uart_port_map[co->index]]; | |
7ae87036 | 1178 | #endif |
1da177e4 | 1179 | unsigned int i; |
c1dcfd9d SW |
1180 | cbd_t __iomem *bdp, *bdbase; |
1181 | unsigned char *cp; | |
1da177e4 LT |
1182 | |
1183 | /* Get the address of the host memory buffer. | |
1184 | */ | |
1185 | bdp = pinfo->tx_cur; | |
1186 | bdbase = pinfo->tx_bd_base; | |
1187 | ||
1188 | /* | |
1189 | * Now, do each character. This is not as bad as it looks | |
1190 | * since this is a holding FIFO and not a transmitting FIFO. | |
1191 | * We could add the complexity of filling the entire transmit | |
1192 | * buffer, but we would just wait longer between accesses...... | |
1193 | */ | |
1194 | for (i = 0; i < count; i++, s++) { | |
1195 | /* Wait for transmitter fifo to empty. | |
1196 | * Ready indicates output is ready, and xmt is doing | |
1197 | * that, not that it is ready for us to send. | |
1198 | */ | |
c1dcfd9d | 1199 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) |
1da177e4 LT |
1200 | ; |
1201 | ||
1202 | /* Send the character out. | |
1203 | * If the buffer address is in the CPM DPRAM, don't | |
1204 | * convert it. | |
1205 | */ | |
c1dcfd9d | 1206 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
1207 | *cp = *s; |
1208 | ||
c1dcfd9d SW |
1209 | out_be16(&bdp->cbd_datlen, 1); |
1210 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 1211 | |
c1dcfd9d | 1212 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
1213 | bdp = bdbase; |
1214 | else | |
1215 | bdp++; | |
1216 | ||
1217 | /* if a LF, also do CR... */ | |
1218 | if (*s == 10) { | |
c1dcfd9d | 1219 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) |
1da177e4 LT |
1220 | ; |
1221 | ||
c1dcfd9d | 1222 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 | 1223 | *cp = 13; |
1da177e4 | 1224 | |
c1dcfd9d SW |
1225 | out_be16(&bdp->cbd_datlen, 1); |
1226 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1227 | ||
1228 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) | |
1da177e4 LT |
1229 | bdp = bdbase; |
1230 | else | |
1231 | bdp++; | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | /* | |
1236 | * Finally, Wait for transmitter & holding register to empty | |
1237 | * and restore the IER | |
1238 | */ | |
c1dcfd9d | 1239 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) |
1da177e4 LT |
1240 | ; |
1241 | ||
c1dcfd9d | 1242 | pinfo->tx_cur = bdp; |
1da177e4 LT |
1243 | } |
1244 | ||
e27987cd | 1245 | |
1da177e4 LT |
1246 | static int __init cpm_uart_console_setup(struct console *co, char *options) |
1247 | { | |
1da177e4 LT |
1248 | int baud = 38400; |
1249 | int bits = 8; | |
1250 | int parity = 'n'; | |
1251 | int flow = 'n'; | |
1252 | int ret; | |
7ae87036 SW |
1253 | struct uart_cpm_port *pinfo; |
1254 | struct uart_port *port; | |
1255 | ||
1256 | #ifdef CONFIG_PPC_CPM_NEW_BINDING | |
1257 | struct device_node *np = NULL; | |
1258 | int i = 0; | |
1259 | ||
1260 | if (co->index >= UART_NR) { | |
1261 | printk(KERN_ERR "cpm_uart: console index %d too high\n", | |
1262 | co->index); | |
1263 | return -ENODEV; | |
1264 | } | |
1265 | ||
1266 | do { | |
1267 | np = of_find_node_by_type(np, "serial"); | |
1268 | if (!np) | |
1269 | return -ENODEV; | |
1270 | ||
1271 | if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && | |
1272 | !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && | |
1273 | !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && | |
1274 | !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) | |
1275 | i--; | |
1276 | } while (i++ != co->index); | |
1277 | ||
1278 | pinfo = &cpm_uart_ports[co->index]; | |
1279 | ||
1280 | pinfo->flags |= FLAG_CONSOLE; | |
1281 | port = &pinfo->port; | |
1282 | ||
1283 | ret = cpm_uart_init_port(np, pinfo); | |
1284 | of_node_put(np); | |
1285 | if (ret) | |
1286 | return ret; | |
1287 | ||
1288 | #else | |
1da177e4 | 1289 | |
e27987cd VB |
1290 | struct fs_uart_platform_info *pdata; |
1291 | struct platform_device* pdev = early_uart_get_pdev(co->index); | |
1292 | ||
e27987cd VB |
1293 | if (!pdev) { |
1294 | pr_info("cpm_uart: console: compat mode\n"); | |
1295 | /* compatibility - will be cleaned up */ | |
1296 | cpm_uart_init_portdesc(); | |
8e30a9a2 | 1297 | } |
e27987cd | 1298 | |
8e30a9a2 VB |
1299 | port = |
1300 | (struct uart_port *)&cpm_uart_ports[cpm_uart_port_map[co->index]]; | |
1301 | pinfo = (struct uart_cpm_port *)port; | |
1302 | if (!pdev) { | |
e27987cd VB |
1303 | if (pinfo->set_lineif) |
1304 | pinfo->set_lineif(pinfo); | |
1305 | } else { | |
1306 | pdata = pdev->dev.platform_data; | |
1307 | if (pdata) | |
1308 | if (pdata->init_ioports) | |
d3465c92 | 1309 | pdata->init_ioports(pdata); |
e27987cd VB |
1310 | |
1311 | cpm_uart_drv_get_platform_data(pdev, 1); | |
1312 | } | |
311c4627 | 1313 | |
1da177e4 | 1314 | pinfo->flags |= FLAG_CONSOLE; |
7ae87036 | 1315 | #endif |
1da177e4 LT |
1316 | |
1317 | if (options) { | |
1318 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1319 | } else { | |
3dd0dcbe | 1320 | if ((baud = uart_baudrate()) == -1) |
1da177e4 LT |
1321 | baud = 9600; |
1322 | } | |
1323 | ||
7ae87036 SW |
1324 | #ifdef CONFIG_PPC_EARLY_DEBUG_CPM |
1325 | udbg_putc = NULL; | |
1326 | #endif | |
1327 | ||
d948a29e SW |
1328 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
1329 | ||
1da177e4 | 1330 | if (IS_SMC(pinfo)) { |
c1dcfd9d SW |
1331 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
1332 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 1333 | } else { |
c1dcfd9d SW |
1334 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
1335 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
1336 | } |
1337 | ||
1338 | ret = cpm_uart_allocbuf(pinfo, 1); | |
1339 | ||
1340 | if (ret) | |
1341 | return ret; | |
1342 | ||
1343 | cpm_uart_initbd(pinfo); | |
1344 | ||
1345 | if (IS_SMC(pinfo)) | |
1346 | cpm_uart_init_smc(pinfo); | |
1347 | else | |
1348 | cpm_uart_init_scc(pinfo); | |
1349 | ||
1350 | uart_set_options(port, co, baud, parity, bits, flow); | |
d948a29e | 1351 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
1352 | |
1353 | return 0; | |
1354 | } | |
1355 | ||
36d2f5a1 | 1356 | static struct uart_driver cpm_reg; |
1da177e4 | 1357 | static struct console cpm_scc_uart_console = { |
36d2f5a1 KG |
1358 | .name = "ttyCPM", |
1359 | .write = cpm_uart_console_write, | |
1360 | .device = uart_console_device, | |
1361 | .setup = cpm_uart_console_setup, | |
1362 | .flags = CON_PRINTBUFFER, | |
1363 | .index = -1, | |
1da177e4 LT |
1364 | .data = &cpm_reg, |
1365 | }; | |
1366 | ||
c1dcfd9d | 1367 | static int __init cpm_uart_console_init(void) |
1da177e4 | 1368 | { |
e27987cd VB |
1369 | register_console(&cpm_scc_uart_console); |
1370 | return 0; | |
1da177e4 LT |
1371 | } |
1372 | ||
1373 | console_initcall(cpm_uart_console_init); | |
1374 | ||
1375 | #define CPM_UART_CONSOLE &cpm_scc_uart_console | |
1376 | #else | |
1377 | #define CPM_UART_CONSOLE NULL | |
1378 | #endif | |
1379 | ||
1380 | static struct uart_driver cpm_reg = { | |
1381 | .owner = THIS_MODULE, | |
1382 | .driver_name = "ttyCPM", | |
1383 | .dev_name = "ttyCPM", | |
1384 | .major = SERIAL_CPM_MAJOR, | |
1385 | .minor = SERIAL_CPM_MINOR, | |
1386 | .cons = CPM_UART_CONSOLE, | |
7ae87036 SW |
1387 | .nr = UART_NR, |
1388 | }; | |
1389 | ||
1390 | #ifdef CONFIG_PPC_CPM_NEW_BINDING | |
1391 | static int probe_index; | |
1392 | ||
1393 | static int __devinit cpm_uart_probe(struct of_device *ofdev, | |
1394 | const struct of_device_id *match) | |
1395 | { | |
1396 | int index = probe_index++; | |
1397 | struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; | |
1398 | int ret; | |
1399 | ||
1400 | pinfo->port.line = index; | |
1401 | ||
1402 | if (index >= UART_NR) | |
1403 | return -ENODEV; | |
1404 | ||
1405 | dev_set_drvdata(&ofdev->dev, pinfo); | |
1406 | ||
1407 | ret = cpm_uart_init_port(ofdev->node, pinfo); | |
1408 | if (ret) | |
1409 | return ret; | |
1410 | ||
1411 | return uart_add_one_port(&cpm_reg, &pinfo->port); | |
1412 | } | |
1413 | ||
1414 | static int __devexit cpm_uart_remove(struct of_device *ofdev) | |
1415 | { | |
1416 | struct uart_cpm_port *pinfo = dev_get_drvdata(&ofdev->dev); | |
1417 | return uart_remove_one_port(&cpm_reg, &pinfo->port); | |
1418 | } | |
1419 | ||
1420 | static struct of_device_id cpm_uart_match[] = { | |
1421 | { | |
1422 | .compatible = "fsl,cpm1-smc-uart", | |
1423 | }, | |
1424 | { | |
1425 | .compatible = "fsl,cpm1-scc-uart", | |
1426 | }, | |
1427 | { | |
1428 | .compatible = "fsl,cpm2-smc-uart", | |
1429 | }, | |
1430 | { | |
1431 | .compatible = "fsl,cpm2-scc-uart", | |
1432 | }, | |
1433 | {} | |
1da177e4 | 1434 | }; |
7ae87036 SW |
1435 | |
1436 | static struct of_platform_driver cpm_uart_driver = { | |
1437 | .name = "cpm_uart", | |
1438 | .match_table = cpm_uart_match, | |
1439 | .probe = cpm_uart_probe, | |
1440 | .remove = cpm_uart_remove, | |
1441 | }; | |
1442 | ||
1443 | static int __init cpm_uart_init(void) | |
1444 | { | |
1445 | int ret = uart_register_driver(&cpm_reg); | |
1446 | if (ret) | |
1447 | return ret; | |
1448 | ||
1449 | ret = of_register_platform_driver(&cpm_uart_driver); | |
1450 | if (ret) | |
1451 | uart_unregister_driver(&cpm_reg); | |
1452 | ||
1453 | return ret; | |
1454 | } | |
1455 | ||
1456 | static void __exit cpm_uart_exit(void) | |
1457 | { | |
1458 | of_unregister_platform_driver(&cpm_uart_driver); | |
1459 | uart_unregister_driver(&cpm_reg); | |
1460 | } | |
1461 | #else | |
e27987cd | 1462 | static int cpm_uart_drv_probe(struct device *dev) |
1da177e4 | 1463 | { |
e27987cd VB |
1464 | struct platform_device *pdev = to_platform_device(dev); |
1465 | struct fs_uart_platform_info *pdata; | |
1466 | int ret = -ENODEV; | |
1da177e4 | 1467 | |
e27987cd VB |
1468 | if(!pdev) { |
1469 | printk(KERN_ERR"CPM UART: platform data missing!\n"); | |
1da177e4 | 1470 | return ret; |
e27987cd | 1471 | } |
1da177e4 | 1472 | |
e27987cd | 1473 | pdata = pdev->dev.platform_data; |
1da177e4 | 1474 | |
e27987cd | 1475 | if ((ret = cpm_uart_drv_get_platform_data(pdev, 0))) |
1da177e4 LT |
1476 | return ret; |
1477 | ||
611a15af VB |
1478 | pr_debug("cpm_uart_drv_probe: Adding CPM UART %d\n", cpm_uart_id2nr(pdata->fs_no)); |
1479 | ||
e27987cd | 1480 | if (pdata->init_ioports) |
d3465c92 | 1481 | pdata->init_ioports(pdata); |
1da177e4 | 1482 | |
e27987cd VB |
1483 | ret = uart_add_one_port(&cpm_reg, &cpm_uart_ports[pdata->fs_no].port); |
1484 | ||
1485 | return ret; | |
1da177e4 LT |
1486 | } |
1487 | ||
e27987cd VB |
1488 | static int cpm_uart_drv_remove(struct device *dev) |
1489 | { | |
1490 | struct platform_device *pdev = to_platform_device(dev); | |
1491 | struct fs_uart_platform_info *pdata = pdev->dev.platform_data; | |
1492 | ||
1493 | pr_debug("cpm_uart_drv_remove: Removing CPM UART %d\n", | |
6e197696 | 1494 | cpm_uart_id2nr(pdata->fs_no)); |
e27987cd VB |
1495 | |
1496 | uart_remove_one_port(&cpm_reg, &cpm_uart_ports[pdata->fs_no].port); | |
1497 | return 0; | |
1498 | } | |
1499 | ||
1500 | static struct device_driver cpm_smc_uart_driver = { | |
1501 | .name = "fsl-cpm-smc:uart", | |
1502 | .bus = &platform_bus_type, | |
1503 | .probe = cpm_uart_drv_probe, | |
1504 | .remove = cpm_uart_drv_remove, | |
1505 | }; | |
1506 | ||
1507 | static struct device_driver cpm_scc_uart_driver = { | |
1508 | .name = "fsl-cpm-scc:uart", | |
1509 | .bus = &platform_bus_type, | |
1510 | .probe = cpm_uart_drv_probe, | |
1511 | .remove = cpm_uart_drv_remove, | |
1512 | }; | |
1513 | ||
1514 | /* | |
1515 | This is supposed to match uart devices on platform bus, | |
1516 | */ | |
1517 | static int match_is_uart (struct device* dev, void* data) | |
1da177e4 | 1518 | { |
e27987cd VB |
1519 | struct platform_device* pdev = container_of(dev, struct platform_device, dev); |
1520 | int ret = 0; | |
1521 | /* this was setfunc as uart */ | |
1522 | if(strstr(pdev->name,":uart")) { | |
1523 | ret = 1; | |
1524 | } | |
1525 | return ret; | |
1526 | } | |
1527 | ||
1528 | ||
1529 | static int cpm_uart_init(void) { | |
1530 | ||
1531 | int ret; | |
1da177e4 | 1532 | int i; |
e27987cd VB |
1533 | struct device *dev; |
1534 | printk(KERN_INFO "Serial: CPM driver $Revision: 0.02 $\n"); | |
1535 | ||
1536 | /* lookup the bus for uart devices */ | |
1537 | dev = bus_find_device(&platform_bus_type, NULL, 0, match_is_uart); | |
1538 | ||
1539 | /* There are devices on the bus - all should be OK */ | |
1540 | if (dev) { | |
1541 | cpm_uart_count(); | |
1542 | cpm_reg.nr = cpm_uart_nr; | |
1543 | ||
1544 | if (!(ret = uart_register_driver(&cpm_reg))) { | |
1545 | if ((ret = driver_register(&cpm_smc_uart_driver))) { | |
1546 | uart_unregister_driver(&cpm_reg); | |
1547 | return ret; | |
1548 | } | |
1549 | if ((ret = driver_register(&cpm_scc_uart_driver))) { | |
1550 | driver_unregister(&cpm_scc_uart_driver); | |
1551 | uart_unregister_driver(&cpm_reg); | |
1552 | } | |
1553 | } | |
1554 | } else { | |
1555 | /* No capable platform devices found - falling back to legacy mode */ | |
1556 | pr_info("cpm_uart: WARNING: no UART devices found on platform bus!\n"); | |
1557 | pr_info( | |
1558 | "cpm_uart: the driver will guess configuration, but this mode is no longer supported.\n"); | |
0091cf5a KP |
1559 | |
1560 | /* Don't run this again, if the console driver did it already */ | |
1561 | if (cpm_uart_nr == 0) | |
1562 | cpm_uart_init_portdesc(); | |
e27987cd VB |
1563 | |
1564 | cpm_reg.nr = cpm_uart_nr; | |
1565 | ret = uart_register_driver(&cpm_reg); | |
1566 | ||
1567 | if (ret) | |
1568 | return ret; | |
1569 | ||
1570 | for (i = 0; i < cpm_uart_nr; i++) { | |
1571 | int con = cpm_uart_port_map[i]; | |
1572 | cpm_uart_ports[con].port.line = i; | |
1573 | cpm_uart_ports[con].port.flags = UPF_BOOT_AUTOCONF; | |
0091cf5a KP |
1574 | if (cpm_uart_ports[con].set_lineif) |
1575 | cpm_uart_ports[con].set_lineif(&cpm_uart_ports[con]); | |
e27987cd VB |
1576 | uart_add_one_port(&cpm_reg, &cpm_uart_ports[con].port); |
1577 | } | |
1da177e4 | 1578 | |
1da177e4 | 1579 | } |
e27987cd VB |
1580 | return ret; |
1581 | } | |
1da177e4 | 1582 | |
e27987cd VB |
1583 | static void __exit cpm_uart_exit(void) |
1584 | { | |
1585 | driver_unregister(&cpm_scc_uart_driver); | |
1586 | driver_unregister(&cpm_smc_uart_driver); | |
1da177e4 LT |
1587 | uart_unregister_driver(&cpm_reg); |
1588 | } | |
7ae87036 | 1589 | #endif |
1da177e4 LT |
1590 | |
1591 | module_init(cpm_uart_init); | |
1592 | module_exit(cpm_uart_exit); | |
1593 | ||
1594 | MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); | |
1595 | MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); | |
1596 | MODULE_LICENSE("GPL"); | |
1597 | MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); |