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77accbf5 1/*
1da177e4
LT		 2 * Serial port driver for the ETRAX 100LX chip
3 *
77accbf5 4 * Copyright (C) 1998-2007 Axis Communications AB
1da177e4
LT		 5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
1da177e4
LT		 8 */
9
10static char *serial_version = "$Revision: 1.25 $";
11
1da177e4
LT		 12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/major.h>
21#include <linux/string.h>
22#include <linux/fcntl.h>
23#include <linux/mm.h>
24#include <linux/slab.h>
25#include <linux/init.h>
26#include <asm/uaccess.h>
27#include <linux/kernel.h>
f392ecfa 28#include <linux/mutex.h>
1977f032 29#include <linux/bitops.h>
1da177e4
LT		 30
31#include <asm/io.h>
32#include <asm/irq.h>
77accbf5 33#include <asm/dma.h>
1da177e4 34#include <asm/system.h>
1da177e4
LT		 35#include <linux/delay.h>
36
37#include <asm/arch/svinto.h>
38
39/* non-arch dependent serial structures are in linux/serial.h */
40#include <linux/serial.h>
41/* while we keep our own stuff (struct e100_serial) in a local .h file */
77accbf5 42#include "crisv10.h"
1da177e4 43#include <asm/fasttimer.h>
77accbf5 44#include <asm/arch/io_interface_mux.h>
1da177e4
LT		 45
46#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
47#ifndef CONFIG_ETRAX_FAST_TIMER
48#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
49#endif
50#endif
51
52#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
53 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
54#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
55#endif
56
57#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
58#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
59#endif
60
61/*
62 * All of the compatibilty code so we can compile serial.c against
63 * older kernels is hidden in serial_compat.h
64 */
65#if defined(LOCAL_HEADERS)
66#include "serial_compat.h"
67#endif
68
1da177e4
LT		 69struct tty_driver *serial_driver;
70
1da177e4
LT		 71/* number of characters left in xmit buffer before we ask for more */
72#define WAKEUP_CHARS 256
73
74//#define SERIAL_DEBUG_INTR
75//#define SERIAL_DEBUG_OPEN
76//#define SERIAL_DEBUG_FLOW
77//#define SERIAL_DEBUG_DATA
78//#define SERIAL_DEBUG_THROTTLE
79//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
80//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
81
82/* Enable this to use serial interrupts to handle when you
83 expect the first received event on the serial port to
84 be an error, break or similar. Used to be able to flash IRMA
85 from eLinux */
86#define SERIAL_HANDLE_EARLY_ERRORS
87
1da177e4
LT		 88/* Currently 16 descriptors x 128 bytes = 2048 bytes */
89#define SERIAL_DESCR_BUF_SIZE 256
90
91#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
92#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
93
94/* We don't want to load the system with massive fast timer interrupt
95 * on high baudrates so limit it to 250 us (4kHz) */
96#define MIN_FLUSH_TIME_USEC 250
97
98/* Add an x here to log a lot of timer stuff */
99#define TIMERD(x)
100/* Debug details of interrupt handling */
101#define DINTR1(x) /* irq on/off, errors */
102#define DINTR2(x) /* tx and rx */
103/* Debug flip buffer stuff */
104#define DFLIP(x)
105/* Debug flow control and overview of data flow */
106#define DFLOW(x)
107#define DBAUD(x)
108#define DLOG_INT_TRIG(x)
109
110//#define DEBUG_LOG_INCLUDED
111#ifndef DEBUG_LOG_INCLUDED
112#define DEBUG_LOG(line, string, value)
113#else
114struct debug_log_info
115{
116 unsigned long time;
117 unsigned long timer_data;
118// int line;
119 const char *string;
120 int value;
121};
122#define DEBUG_LOG_SIZE 4096
123
124struct debug_log_info debug_log[DEBUG_LOG_SIZE];
125int debug_log_pos = 0;
126
127#define DEBUG_LOG(_line, _string, _value) do { \
128 if ((_line) == SERIAL_DEBUG_LINE) {\
129 debug_log_func(_line, _string, _value); \
130 }\
131}while(0)
132
133void debug_log_func(int line, const char *string, int value)
134{
135 if (debug_log_pos < DEBUG_LOG_SIZE) {
136 debug_log[debug_log_pos].time = jiffies;
137 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
138// debug_log[debug_log_pos].line = line;
139 debug_log[debug_log_pos].string = string;
140 debug_log[debug_log_pos].value = value;
141 debug_log_pos++;
142 }
143 /*printk(string, value);*/
144}
145#endif
146
147#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
148/* Default number of timer ticks before flushing rx fifo
149 * When using "little data, low latency applications: use 0
150 * When using "much data applications (PPP)" use ~5
151 */
152#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
153#endif
154
155unsigned long timer_data_to_ns(unsigned long timer_data);
156
157static void change_speed(struct e100_serial *info);
158static void rs_throttle(struct tty_struct * tty);
159static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
77accbf5
JN		 160static int rs_write(struct tty_struct *tty,
161 const unsigned char *buf, int count);
1da177e4 162#ifdef CONFIG_ETRAX_RS485
77accbf5
JN		 163static int e100_write_rs485(struct tty_struct *tty,
164 const unsigned char *buf, int count);
1da177e4 165#endif
77accbf5 166static int get_lsr_info(struct e100_serial *info, unsigned int *value);
1da177e4
LT		 167
168
169#define DEF_BAUD 115200 /* 115.2 kbit/s */
170#define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
171#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
172/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
173#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
174
175/* offsets from R_SERIALx_CTRL */
176
177#define REG_DATA 0
178#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
179#define REG_TR_DATA 0
180#define REG_STATUS 1
181#define REG_TR_CTRL 1
182#define REG_REC_CTRL 2
183#define REG_BAUD 3
184#define REG_XOFF 4 /* this is a 32 bit register */
185
186/* The bitfields are the same for all serial ports */
187#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
188#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
189#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
190#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
191#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
192
193#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
194
195/* Values for info->errorcode */
196#define ERRCODE_SET_BREAK (TTY_BREAK)
197#define ERRCODE_INSERT 0x100
198#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
199
200#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
201
202/*
203 * General note regarding the use of IO_* macros in this file:
204 *
205 * We will use the bits defined for DMA channel 6 when using various
206 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
207 * the same for all channels (which of course they are).
208 *
209 * We will also use the bits defined for serial port 0 when writing commands
210 * to the different ports, as these bits too are the same for all ports.
211 */
212
213
214/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
215static const unsigned long e100_ser_int_mask = 0
216#ifdef CONFIG_ETRAX_SERIAL_PORT0
217| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
218#endif
219#ifdef CONFIG_ETRAX_SERIAL_PORT1
220| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
221#endif
222#ifdef CONFIG_ETRAX_SERIAL_PORT2
223| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
224#endif
225#ifdef CONFIG_ETRAX_SERIAL_PORT3
226| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
227#endif
228;
229unsigned long r_alt_ser_baudrate_shadow = 0;
230
231/* this is the data for the four serial ports in the etrax100 */
232/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
233/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
234
235static struct e100_serial rs_table[] = {
236 { .baud = DEF_BAUD,
237 .port = (unsigned char *)R_SERIAL0_CTRL,
238 .irq = 1U << 12, /* uses DMA 6 and 7 */
239 .oclrintradr = R_DMA_CH6_CLR_INTR,
240 .ofirstadr = R_DMA_CH6_FIRST,
241 .ocmdadr = R_DMA_CH6_CMD,
242 .ostatusadr = R_DMA_CH6_STATUS,
243 .iclrintradr = R_DMA_CH7_CLR_INTR,
244 .ifirstadr = R_DMA_CH7_FIRST,
245 .icmdadr = R_DMA_CH7_CMD,
246 .idescradr = R_DMA_CH7_DESCR,
247 .flags = STD_FLAGS,
248 .rx_ctrl = DEF_RX,
249 .tx_ctrl = DEF_TX,
250 .iseteop = 2,
77accbf5
JN		 251 .dma_owner = dma_ser0,
252 .io_if = if_serial_0,
1da177e4
LT		 253#ifdef CONFIG_ETRAX_SERIAL_PORT0
254 .enabled = 1,
255#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
256 .dma_out_enabled = 1,
77accbf5
JN		 257 .dma_out_nbr = SER0_TX_DMA_NBR,
258 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
259 .dma_out_irq_flags = IRQF_DISABLED,
260 .dma_out_irq_description = "serial 0 dma tr",
1da177e4
LT		 261#else
262 .dma_out_enabled = 0,
77accbf5
JN		 263 .dma_out_nbr = UINT_MAX,
264 .dma_out_irq_nbr = 0,
265 .dma_out_irq_flags = 0,
266 .dma_out_irq_description = NULL,
1da177e4
LT		 267#endif
268#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
269 .dma_in_enabled = 1,
77accbf5
JN		 270 .dma_in_nbr = SER0_RX_DMA_NBR,
271 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
272 .dma_in_irq_flags = IRQF_DISABLED,
273 .dma_in_irq_description = "serial 0 dma rec",
1da177e4 274#else
77accbf5
JN		 275 .dma_in_enabled = 0,
276 .dma_in_nbr = UINT_MAX,
277 .dma_in_irq_nbr = 0,
278 .dma_in_irq_flags = 0,
279 .dma_in_irq_description = NULL,
1da177e4
LT		 280#endif
281#else
282 .enabled = 0,
77accbf5 283 .io_if_description = NULL,
1da177e4
LT		 284 .dma_out_enabled = 0,
285 .dma_in_enabled = 0
286#endif
287
288}, /* ttyS0 */
289#ifndef CONFIG_SVINTO_SIM
290 { .baud = DEF_BAUD,
291 .port = (unsigned char *)R_SERIAL1_CTRL,
292 .irq = 1U << 16, /* uses DMA 8 and 9 */
293 .oclrintradr = R_DMA_CH8_CLR_INTR,
294 .ofirstadr = R_DMA_CH8_FIRST,
295 .ocmdadr = R_DMA_CH8_CMD,
296 .ostatusadr = R_DMA_CH8_STATUS,
297 .iclrintradr = R_DMA_CH9_CLR_INTR,
298 .ifirstadr = R_DMA_CH9_FIRST,
299 .icmdadr = R_DMA_CH9_CMD,
300 .idescradr = R_DMA_CH9_DESCR,
301 .flags = STD_FLAGS,
302 .rx_ctrl = DEF_RX,
303 .tx_ctrl = DEF_TX,
304 .iseteop = 3,
77accbf5
JN		 305 .dma_owner = dma_ser1,
306 .io_if = if_serial_1,
1da177e4
LT		 307#ifdef CONFIG_ETRAX_SERIAL_PORT1
308 .enabled = 1,
77accbf5 309 .io_if_description = "ser1",
1da177e4
LT		 310#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
311 .dma_out_enabled = 1,
77accbf5
JN		 312 .dma_out_nbr = SER1_TX_DMA_NBR,
313 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
314 .dma_out_irq_flags = IRQF_DISABLED,
315 .dma_out_irq_description = "serial 1 dma tr",
1da177e4
LT		 316#else
317 .dma_out_enabled = 0,
77accbf5
JN		 318 .dma_out_nbr = UINT_MAX,
319 .dma_out_irq_nbr = 0,
320 .dma_out_irq_flags = 0,
321 .dma_out_irq_description = NULL,
1da177e4
LT		 322#endif
323#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
324 .dma_in_enabled = 1,
77accbf5
JN		 325 .dma_in_nbr = SER1_RX_DMA_NBR,
326 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
327 .dma_in_irq_flags = IRQF_DISABLED,
328 .dma_in_irq_description = "serial 1 dma rec",
1da177e4 329#else
77accbf5
JN		 330 .dma_in_enabled = 0,
331 .dma_in_enabled = 0,
332 .dma_in_nbr = UINT_MAX,
333 .dma_in_irq_nbr = 0,
334 .dma_in_irq_flags = 0,
335 .dma_in_irq_description = NULL,
1da177e4
LT		 336#endif
337#else
338 .enabled = 0,
77accbf5
JN		 339 .io_if_description = NULL,
340 .dma_in_irq_nbr = 0,
1da177e4
LT		 341 .dma_out_enabled = 0,
342 .dma_in_enabled = 0
343#endif
344}, /* ttyS1 */
345
346 { .baud = DEF_BAUD,
347 .port = (unsigned char *)R_SERIAL2_CTRL,
348 .irq = 1U << 4, /* uses DMA 2 and 3 */
349 .oclrintradr = R_DMA_CH2_CLR_INTR,
350 .ofirstadr = R_DMA_CH2_FIRST,
351 .ocmdadr = R_DMA_CH2_CMD,
352 .ostatusadr = R_DMA_CH2_STATUS,
353 .iclrintradr = R_DMA_CH3_CLR_INTR,
354 .ifirstadr = R_DMA_CH3_FIRST,
355 .icmdadr = R_DMA_CH3_CMD,
356 .idescradr = R_DMA_CH3_DESCR,
357 .flags = STD_FLAGS,
358 .rx_ctrl = DEF_RX,
359 .tx_ctrl = DEF_TX,
360 .iseteop = 0,
77accbf5
JN		 361 .dma_owner = dma_ser2,
362 .io_if = if_serial_2,
1da177e4
LT		 363#ifdef CONFIG_ETRAX_SERIAL_PORT2
364 .enabled = 1,
77accbf5 365 .io_if_description = "ser2",
1da177e4
LT		 366#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
367 .dma_out_enabled = 1,
77accbf5
JN		 368 .dma_out_nbr = SER2_TX_DMA_NBR,
369 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
370 .dma_out_irq_flags = IRQF_DISABLED,
371 .dma_out_irq_description = "serial 2 dma tr",
1da177e4
LT		 372#else
373 .dma_out_enabled = 0,
77accbf5
JN		 374 .dma_out_nbr = UINT_MAX,
375 .dma_out_irq_nbr = 0,
376 .dma_out_irq_flags = 0,
377 .dma_out_irq_description = NULL,
1da177e4
LT		 378#endif
379#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
380 .dma_in_enabled = 1,
77accbf5
JN		 381 .dma_in_nbr = SER2_RX_DMA_NBR,
382 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
383 .dma_in_irq_flags = IRQF_DISABLED,
384 .dma_in_irq_description = "serial 2 dma rec",
1da177e4 385#else
77accbf5
JN		 386 .dma_in_enabled = 0,
387 .dma_in_nbr = UINT_MAX,
388 .dma_in_irq_nbr = 0,
389 .dma_in_irq_flags = 0,
390 .dma_in_irq_description = NULL,
1da177e4
LT		 391#endif
392#else
393 .enabled = 0,
77accbf5 394 .io_if_description = NULL,
1da177e4
LT		 395 .dma_out_enabled = 0,
396 .dma_in_enabled = 0
397#endif
398 }, /* ttyS2 */
399
400 { .baud = DEF_BAUD,
401 .port = (unsigned char *)R_SERIAL3_CTRL,
402 .irq = 1U << 8, /* uses DMA 4 and 5 */
403 .oclrintradr = R_DMA_CH4_CLR_INTR,
404 .ofirstadr = R_DMA_CH4_FIRST,
405 .ocmdadr = R_DMA_CH4_CMD,
406 .ostatusadr = R_DMA_CH4_STATUS,
407 .iclrintradr = R_DMA_CH5_CLR_INTR,
408 .ifirstadr = R_DMA_CH5_FIRST,
409 .icmdadr = R_DMA_CH5_CMD,
410 .idescradr = R_DMA_CH5_DESCR,
411 .flags = STD_FLAGS,
412 .rx_ctrl = DEF_RX,
413 .tx_ctrl = DEF_TX,
414 .iseteop = 1,
77accbf5
JN		 415 .dma_owner = dma_ser3,
416 .io_if = if_serial_3,
1da177e4
LT		 417#ifdef CONFIG_ETRAX_SERIAL_PORT3
418 .enabled = 1,
77accbf5 419 .io_if_description = "ser3",
1da177e4
LT		 420#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
421 .dma_out_enabled = 1,
77accbf5
JN		 422 .dma_out_nbr = SER3_TX_DMA_NBR,
423 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
424 .dma_out_irq_flags = IRQF_DISABLED,
425 .dma_out_irq_description = "serial 3 dma tr",
1da177e4
LT		 426#else
427 .dma_out_enabled = 0,
77accbf5
JN		 428 .dma_out_nbr = UINT_MAX,
429 .dma_out_irq_nbr = 0,
430 .dma_out_irq_flags = 0,
431 .dma_out_irq_description = NULL,
1da177e4
LT		 432#endif
433#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
434 .dma_in_enabled = 1,
77accbf5
JN		 435 .dma_in_nbr = SER3_RX_DMA_NBR,
436 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
437 .dma_in_irq_flags = IRQF_DISABLED,
438 .dma_in_irq_description = "serial 3 dma rec",
1da177e4 439#else
77accbf5
JN		 440 .dma_in_enabled = 0,
441 .dma_in_nbr = UINT_MAX,
442 .dma_in_irq_nbr = 0,
443 .dma_in_irq_flags = 0,
444 .dma_in_irq_description = NULL
1da177e4
LT		 445#endif
446#else
447 .enabled = 0,
77accbf5 448 .io_if_description = NULL,
1da177e4
LT		 449 .dma_out_enabled = 0,
450 .dma_in_enabled = 0
451#endif
452 } /* ttyS3 */
453#endif
454};
455
456
457#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
458
606d099c
AC		 459static struct ktermios *serial_termios[NR_PORTS];
460static struct ktermios *serial_termios_locked[NR_PORTS];
1da177e4
LT		 461#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
462static struct fast_timer fast_timers[NR_PORTS];
463#endif
464
465#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
466#define PROCSTAT(x) x
467struct ser_statistics_type {
468 int overrun_cnt;
469 int early_errors_cnt;
470 int ser_ints_ok_cnt;
471 int errors_cnt;
472 unsigned long int processing_flip;
473 unsigned long processing_flip_still_room;
474 unsigned long int timeout_flush_cnt;
475 int rx_dma_ints;
476 int tx_dma_ints;
477 int rx_tot;
478 int tx_tot;
479};
480
481static struct ser_statistics_type ser_stat[NR_PORTS];
482
483#else
484
485#define PROCSTAT(x)
486
487#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
488
489/* RS-485 */
490#if defined(CONFIG_ETRAX_RS485)
491#ifdef CONFIG_ETRAX_FAST_TIMER
492static struct fast_timer fast_timers_rs485[NR_PORTS];
493#endif
494#if defined(CONFIG_ETRAX_RS485_ON_PA)
495static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
496#endif
497#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
498static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
499#endif
500#endif
501
502/* Info and macros needed for each ports extra control/status signals. */
503#define E100_STRUCT_PORT(line, pinname) \
504 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
505 (R_PORT_PA_DATA): ( \
506 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
507 (R_PORT_PB_DATA):&dummy_ser[line]))
508
509#define E100_STRUCT_SHADOW(line, pinname) \
510 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
511 (&port_pa_data_shadow): ( \
512 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
513 (&port_pb_data_shadow):&dummy_ser[line]))
514#define E100_STRUCT_MASK(line, pinname) \
515 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
516 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
517 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
518 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
519
520#define DUMMY_DTR_MASK 1
521#define DUMMY_RI_MASK 2
522#define DUMMY_DSR_MASK 4
523#define DUMMY_CD_MASK 8
524static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
525
526/* If not all status pins are used or disabled, use mixed mode */
527#ifdef CONFIG_ETRAX_SERIAL_PORT0
528
529#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
530
531#if SER0_PA_BITSUM != -4
532# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
533# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
534# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
535# endif
536# endif
537# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
538# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
539# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
540# endif
541# endif
542# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
543# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
544# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
545# endif
546# endif
547# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
548# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
549# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
550# endif
551# endif
552#endif
553
554#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
555
556#if SER0_PB_BITSUM != -4
557# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
558# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
559# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
560# endif
561# endif
562# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
563# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
564# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
565# endif
566# endif
567# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
568# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
569# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
570# endif
571# endif
572# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
573# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
574# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
575# endif
576# endif
577#endif
578
579#endif /* PORT0 */
580
581
582#ifdef CONFIG_ETRAX_SERIAL_PORT1
583
584#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
585
586#if SER1_PA_BITSUM != -4
587# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
588# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
589# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
590# endif
591# endif
592# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
593# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
594# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
595# endif
596# endif
597# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
598# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
599# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
600# endif
601# endif
602# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
603# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
604# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
605# endif
606# endif
607#endif
608
609#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
610
611#if SER1_PB_BITSUM != -4
612# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
613# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
614# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
615# endif
616# endif
617# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
618# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
619# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
620# endif
621# endif
622# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
623# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
624# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
625# endif
626# endif
627# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
628# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
629# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
630# endif
631# endif
632#endif
633
634#endif /* PORT1 */
635
636#ifdef CONFIG_ETRAX_SERIAL_PORT2
637
638#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
639
640#if SER2_PA_BITSUM != -4
641# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
642# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
643# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
644# endif
645# endif
646# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
647# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
648# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
649# endif
650# endif
651# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
652# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
653# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
654# endif
655# endif
656# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
657# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
658# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
659# endif
660# endif
661#endif
662
663#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
664
665#if SER2_PB_BITSUM != -4
666# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
667# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
668# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
669# endif
670# endif
671# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
672# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
673# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
674# endif
675# endif
676# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
677# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
678# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
679# endif
680# endif
681# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
682# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
683# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
684# endif
685# endif
686#endif
687
688#endif /* PORT2 */
689
690#ifdef CONFIG_ETRAX_SERIAL_PORT3
691
692#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
693
694#if SER3_PA_BITSUM != -4
695# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
696# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
697# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
698# endif
699# endif
700# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
701# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
702# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
703# endif
704# endif
705# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
706# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
707# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
708# endif
709# endif
710# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
711# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
712# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
713# endif
714# endif
715#endif
716
717#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
718
719#if SER3_PB_BITSUM != -4
720# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
721# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
722# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
723# endif
724# endif
725# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
726# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
727# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
728# endif
729# endif
730# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
731# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
732# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
733# endif
734# endif
735# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
736# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
737# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
738# endif
739# endif
740#endif
741
742#endif /* PORT3 */
743
744
745#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
746 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
749#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
750#endif
751
752#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
753/* The pins can be mixed on PA and PB */
754#define CONTROL_PINS_PORT_NOT_USED(line) \
755 &dummy_ser[line], &dummy_ser[line], \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
760
761
762struct control_pins
763{
764 volatile unsigned char *dtr_port;
765 unsigned char *dtr_shadow;
766 volatile unsigned char *ri_port;
767 unsigned char *ri_shadow;
768 volatile unsigned char *dsr_port;
769 unsigned char *dsr_shadow;
770 volatile unsigned char *cd_port;
771 unsigned char *cd_shadow;
772
773 unsigned char dtr_mask;
774 unsigned char ri_mask;
775 unsigned char dsr_mask;
776 unsigned char cd_mask;
777};
778
779static const struct control_pins e100_modem_pins[NR_PORTS] =
780{
781 /* Ser 0 */
782 {
783#ifdef CONFIG_ETRAX_SERIAL_PORT0
784 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
785 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
786 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
787 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
788 E100_STRUCT_MASK(0,DTR),
789 E100_STRUCT_MASK(0,RI),
790 E100_STRUCT_MASK(0,DSR),
791 E100_STRUCT_MASK(0,CD)
792#else
793 CONTROL_PINS_PORT_NOT_USED(0)
794#endif
795 },
796
797 /* Ser 1 */
798 {
799#ifdef CONFIG_ETRAX_SERIAL_PORT1
800 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
801 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
802 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
803 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
804 E100_STRUCT_MASK(1,DTR),
805 E100_STRUCT_MASK(1,RI),
806 E100_STRUCT_MASK(1,DSR),
807 E100_STRUCT_MASK(1,CD)
808#else
809 CONTROL_PINS_PORT_NOT_USED(1)
810#endif
811 },
812
813 /* Ser 2 */
814 {
815#ifdef CONFIG_ETRAX_SERIAL_PORT2
816 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
817 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
818 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
819 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
820 E100_STRUCT_MASK(2,DTR),
821 E100_STRUCT_MASK(2,RI),
822 E100_STRUCT_MASK(2,DSR),
823 E100_STRUCT_MASK(2,CD)
824#else
825 CONTROL_PINS_PORT_NOT_USED(2)
826#endif
827 },
828
829 /* Ser 3 */
830 {
831#ifdef CONFIG_ETRAX_SERIAL_PORT3
832 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
833 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
834 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
835 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
836 E100_STRUCT_MASK(3,DTR),
837 E100_STRUCT_MASK(3,RI),
838 E100_STRUCT_MASK(3,DSR),
839 E100_STRUCT_MASK(3,CD)
840#else
841 CONTROL_PINS_PORT_NOT_USED(3)
842#endif
843 }
844};
845#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
846
847/* All pins are on either PA or PB for each serial port */
848#define CONTROL_PINS_PORT_NOT_USED(line) \
849 &dummy_ser[line], &dummy_ser[line], \
850 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
851
852
853struct control_pins
854{
855 volatile unsigned char *port;
856 unsigned char *shadow;
857
858 unsigned char dtr_mask;
859 unsigned char ri_mask;
860 unsigned char dsr_mask;
861 unsigned char cd_mask;
862};
863
864#define dtr_port port
865#define dtr_shadow shadow
866#define ri_port port
867#define ri_shadow shadow
868#define dsr_port port
869#define dsr_shadow shadow
870#define cd_port port
871#define cd_shadow shadow
872
873static const struct control_pins e100_modem_pins[NR_PORTS] =
874{
875 /* Ser 0 */
876 {
877#ifdef CONFIG_ETRAX_SERIAL_PORT0
878 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
879 E100_STRUCT_MASK(0,DTR),
880 E100_STRUCT_MASK(0,RI),
881 E100_STRUCT_MASK(0,DSR),
882 E100_STRUCT_MASK(0,CD)
883#else
884 CONTROL_PINS_PORT_NOT_USED(0)
885#endif
886 },
887
888 /* Ser 1 */
889 {
890#ifdef CONFIG_ETRAX_SERIAL_PORT1
891 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
892 E100_STRUCT_MASK(1,DTR),
893 E100_STRUCT_MASK(1,RI),
894 E100_STRUCT_MASK(1,DSR),
895 E100_STRUCT_MASK(1,CD)
896#else
897 CONTROL_PINS_PORT_NOT_USED(1)
898#endif
899 },
900
901 /* Ser 2 */
902 {
903#ifdef CONFIG_ETRAX_SERIAL_PORT2
904 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
905 E100_STRUCT_MASK(2,DTR),
906 E100_STRUCT_MASK(2,RI),
907 E100_STRUCT_MASK(2,DSR),
908 E100_STRUCT_MASK(2,CD)
909#else
910 CONTROL_PINS_PORT_NOT_USED(2)
911#endif
912 },
913
914 /* Ser 3 */
915 {
916#ifdef CONFIG_ETRAX_SERIAL_PORT3
917 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
918 E100_STRUCT_MASK(3,DTR),
919 E100_STRUCT_MASK(3,RI),
920 E100_STRUCT_MASK(3,DSR),
921 E100_STRUCT_MASK(3,CD)
922#else
923 CONTROL_PINS_PORT_NOT_USED(3)
924#endif
925 }
926};
927#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
928
929#define E100_RTS_MASK 0x20
930#define E100_CTS_MASK 0x40
931
932/* All serial port signals are active low:
933 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
934 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
935 *
936 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
937 */
938
939/* Output */
940#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
941/* Input */
942#define E100_CTS_GET(info) ((info)->port[REG_STATUS] & E100_CTS_MASK)
943
944/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
945/* Is an output */
946#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
947
948/* Normally inputs */
949#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
950#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
951
952/* Input */
953#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
954
955
956/*
957 * tmp_buf is used as a temporary buffer by serial_write. We need to
958 * lock it in case the memcpy_fromfs blocks while swapping in a page,
959 * and some other program tries to do a serial write at the same time.
960 * Since the lock will only come under contention when the system is
961 * swapping and available memory is low, it makes sense to share one
962 * buffer across all the serial ports, since it significantly saves
963 * memory if large numbers of serial ports are open.
964 */
965static unsigned char *tmp_buf;
f392ecfa 966static DEFINE_MUTEX(tmp_buf_mutex);
1da177e4
LT		 967
968/* Calculate the chartime depending on baudrate, numbor of bits etc. */
969static void update_char_time(struct e100_serial * info)
970{
971 tcflag_t cflags = info->tty->termios->c_cflag;
972 int bits;
973
974 /* calc. number of bits / data byte */
975 /* databits + startbit and 1 stopbit */
976 if ((cflags & CSIZE) == CS7)
977 bits = 9;
978 else
979 bits = 10;
980
981 if (cflags & CSTOPB) /* 2 stopbits ? */
982 bits++;
983
984 if (cflags & PARENB) /* parity bit ? */
985 bits++;
986
987 /* calc timeout */
988 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
989 info->flush_time_usec = 4*info->char_time_usec;
990 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
991 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
992
993}
994
995/*
996 * This function maps from the Bxxxx defines in asm/termbits.h into real
997 * baud rates.
998 */
999
1000static int
1001cflag_to_baud(unsigned int cflag)
1002{
1003 static int baud_table[] = {
1004 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
1005 4800, 9600, 19200, 38400 };
1006
1007 static int ext_baud_table[] = {
1008 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
1009 0, 0, 0, 0, 0, 0, 0, 0 };
1010
1011 if (cflag & CBAUDEX)
1012 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1013 else
1014 return baud_table[cflag & CBAUD];
1015}
1016
1017/* and this maps to an etrax100 hardware baud constant */
1018
1019static unsigned char
1020cflag_to_etrax_baud(unsigned int cflag)
1021{
1022 char retval;
1023
1024 static char baud_table[] = {
1025 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1026
1027 static char ext_baud_table[] = {
1028 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1029
1030 if (cflag & CBAUDEX)
1031 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1032 else
1033 retval = baud_table[cflag & CBAUD];
1034
1035 if (retval < 0) {
1036 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1037 retval = 5; /* choose default 9600 instead */
1038 }
1039
1040 return retval | (retval << 4); /* choose same for both TX and RX */
1041}
1042
1043
1044/* Various static support functions */
1045
1046/* Functions to set or clear DTR/RTS on the requested line */
1047/* It is complicated by the fact that RTS is a serial port register, while
1048 * DTR might not be implemented in the HW at all, and if it is, it can be on
1049 * any general port.
1050 */
1051
1052
1053static inline void
1054e100_dtr(struct e100_serial *info, int set)
1055{
1056#ifndef CONFIG_SVINTO_SIM
1057 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1058
1059#ifdef SERIAL_DEBUG_IO
1060 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1061 printk("ser%i shadow before 0x%02X get: %i\n",
1062 info->line, *e100_modem_pins[info->line].dtr_shadow,
1063 E100_DTR_GET(info));
1064#endif
1065 /* DTR is active low */
1066 {
1067 unsigned long flags;
1068
77accbf5 1069 local_irq_save(flags);
1da177e4
LT		 1070 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1071 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1072 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
77accbf5 1073 local_irq_restore(flags);
1da177e4
LT		 1074 }
1075
1076#ifdef SERIAL_DEBUG_IO
1077 printk("ser%i shadow after 0x%02X get: %i\n",
1078 info->line, *e100_modem_pins[info->line].dtr_shadow,
1079 E100_DTR_GET(info));
1080#endif
1081#endif
1082}
1083
1084/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1085 * 0=0V , 1=3.3V
1086 */
1087static inline void
1088e100_rts(struct e100_serial *info, int set)
1089{
1090#ifndef CONFIG_SVINTO_SIM
1091 unsigned long flags;
77accbf5 1092 local_irq_save(flags);
1da177e4
LT		 1093 info->rx_ctrl &= ~E100_RTS_MASK;
1094 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1095 info->port[REG_REC_CTRL] = info->rx_ctrl;
77accbf5 1096 local_irq_restore(flags);
1da177e4
LT		 1097#ifdef SERIAL_DEBUG_IO
1098 printk("ser%i rts %i\n", info->line, set);
1099#endif
1100#endif
1101}
1102
1103
1104/* If this behaves as a modem, RI and CD is an output */
1105static inline void
1106e100_ri_out(struct e100_serial *info, int set)
1107{
1108#ifndef CONFIG_SVINTO_SIM
1109 /* RI is active low */
1110 {
1111 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1112 unsigned long flags;
1113
77accbf5 1114 local_irq_save(flags);
1da177e4
LT		 1115 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1116 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1117 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
77accbf5 1118 local_irq_restore(flags);
1da177e4
LT		 1119 }
1120#endif
1121}
1122static inline void
1123e100_cd_out(struct e100_serial *info, int set)
1124{
1125#ifndef CONFIG_SVINTO_SIM
1126 /* CD is active low */
1127 {
1128 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1129 unsigned long flags;
1130
77accbf5 1131 local_irq_save(flags);
1da177e4
LT		 1132 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1133 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1134 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
77accbf5 1135 local_irq_restore(flags);
1da177e4
LT		 1136 }
1137#endif
1138}
1139
1140static inline void
1141e100_disable_rx(struct e100_serial *info)
1142{
1143#ifndef CONFIG_SVINTO_SIM
1144 /* disable the receiver */
1145 info->port[REG_REC_CTRL] =
1146 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1147#endif
1148}
1149
1150static inline void
1151e100_enable_rx(struct e100_serial *info)
1152{
1153#ifndef CONFIG_SVINTO_SIM
1154 /* enable the receiver */
1155 info->port[REG_REC_CTRL] =
1156 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1157#endif
1158}
1159
1160/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1161
1162static inline void
1163e100_disable_rxdma_irq(struct e100_serial *info)
1164{
1165#ifdef SERIAL_DEBUG_INTR
1166 printk("rxdma_irq(%d): 0\n",info->line);
1167#endif
1168 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1169 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1170}
1171
1172static inline void
1173e100_enable_rxdma_irq(struct e100_serial *info)
1174{
1175#ifdef SERIAL_DEBUG_INTR
1176 printk("rxdma_irq(%d): 1\n",info->line);
1177#endif
1178 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1179 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1180}
1181
1182/* the tx DMA uses only dma_descr interrupt */
1183
41c28ff1 1184static void e100_disable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1185{
1186#ifdef SERIAL_DEBUG_INTR
1187 printk("txdma_irq(%d): 0\n",info->line);
1188#endif
1189 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1190 *R_IRQ_MASK2_CLR = info->irq;
1191}
1192
41c28ff1 1193static void e100_enable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1194{
1195#ifdef SERIAL_DEBUG_INTR
1196 printk("txdma_irq(%d): 1\n",info->line);
1197#endif
1198 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1199 *R_IRQ_MASK2_SET = info->irq;
1200}
1201
41c28ff1 1202static void e100_disable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1203{
1204 unsigned long flags;
1205
1206 /* Disable output DMA channel for the serial port in question
1207 * ( set to something other then serialX)
1208 */
77accbf5 1209 local_irq_save(flags);
1da177e4
LT		 1210 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1211 if (info->line == 0) {
1212 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1213 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1214 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1215 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1216 }
1217 } else if (info->line == 1) {
1218 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1219 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1220 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1221 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1222 }
1223 } else if (info->line == 2) {
1224 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1225 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1226 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1227 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1228 }
1229 } else if (info->line == 3) {
1230 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1231 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1232 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1233 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1234 }
1235 }
1236 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1237 local_irq_restore(flags);
1da177e4
LT		 1238}
1239
1240
41c28ff1 1241static void e100_enable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1242{
1243 unsigned long flags;
1244
77accbf5 1245 local_irq_save(flags);
1da177e4
LT		 1246 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1247 /* Enable output DMA channel for the serial port in question */
1248 if (info->line == 0) {
1249 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1250 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1251 } else if (info->line == 1) {
1252 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1253 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1254 } else if (info->line == 2) {
1255 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1256 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1257 } else if (info->line == 3) {
1258 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1259 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1260 }
1261 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1262 local_irq_restore(flags);
1da177e4
LT		 1263}
1264
41c28ff1 1265static void e100_disable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1266{
1267 unsigned long flags;
1268
1269 /* Disable input DMA channel for the serial port in question
1270 * ( set to something other then serialX)
1271 */
77accbf5 1272 local_irq_save(flags);
1da177e4
LT		 1273 if (info->line == 0) {
1274 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1275 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1276 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1277 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1278 }
1279 } else if (info->line == 1) {
1280 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1281 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1282 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1283 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1284 }
1285 } else if (info->line == 2) {
1286 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1287 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1288 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1289 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1290 }
1291 } else if (info->line == 3) {
1292 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1293 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1294 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1295 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1296 }
1297 }
1298 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1299 local_irq_restore(flags);
1da177e4
LT		 1300}
1301
1302
41c28ff1 1303static void e100_enable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1304{
1305 unsigned long flags;
1306
77accbf5 1307 local_irq_save(flags);
1da177e4
LT		 1308 /* Enable input DMA channel for the serial port in question */
1309 if (info->line == 0) {
1310 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1311 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1312 } else if (info->line == 1) {
1313 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1314 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1315 } else if (info->line == 2) {
1316 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1317 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1318 } else if (info->line == 3) {
1319 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1320 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1321 }
1322 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1323 local_irq_restore(flags);
1da177e4
LT		 1324}
1325
1326#ifdef SERIAL_HANDLE_EARLY_ERRORS
1327/* in order to detect and fix errors on the first byte
1328 we have to use the serial interrupts as well. */
1329
1330static inline void
1331e100_disable_serial_data_irq(struct e100_serial *info)
1332{
1333#ifdef SERIAL_DEBUG_INTR
1334 printk("ser_irq(%d): 0\n",info->line);
1335#endif
1336 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1337 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1338}
1339
1340static inline void
1341e100_enable_serial_data_irq(struct e100_serial *info)
1342{
1343#ifdef SERIAL_DEBUG_INTR
1344 printk("ser_irq(%d): 1\n",info->line);
1345 printk("**** %d = %d\n",
1346 (8+2*info->line),
1347 (1U << (8+2*info->line)));
1348#endif
1349 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1350 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1351}
1352#endif
1353
1354static inline void
1355e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1356{
1357#ifdef SERIAL_DEBUG_INTR
1358 printk("ser_tx_irq(%d): 0\n",info->line);
1359#endif
1360 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1361 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1362}
1363
1364static inline void
1365e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1366{
1367#ifdef SERIAL_DEBUG_INTR
1368 printk("ser_tx_irq(%d): 1\n",info->line);
1369 printk("**** %d = %d\n",
1370 (8+1+2*info->line),
1371 (1U << (8+1+2*info->line)));
1372#endif
1373 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1374 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1375}
1376
1377static inline void e100_enable_rx_irq(struct e100_serial *info)
1378{
1379 if (info->uses_dma_in)
1380 e100_enable_rxdma_irq(info);
1381 else
1382 e100_enable_serial_data_irq(info);
1383}
1384static inline void e100_disable_rx_irq(struct e100_serial *info)
1385{
1386 if (info->uses_dma_in)
1387 e100_disable_rxdma_irq(info);
1388 else
1389 e100_disable_serial_data_irq(info);
1390}
1391
1392#if defined(CONFIG_ETRAX_RS485)
1393/* Enable RS-485 mode on selected port. This is UGLY. */
1394static int
1395e100_enable_rs485(struct tty_struct *tty,struct rs485_control *r)
1396{
1397 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1398
1399#if defined(CONFIG_ETRAX_RS485_ON_PA)
1400 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1401#endif
1402#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1403 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1404 rs485_port_g_bit, 1);
1405#endif
1406#if defined(CONFIG_ETRAX_RS485_LTC1387)
1407 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1408 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1409 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1410 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1411#endif
1412
1413 info->rs485.rts_on_send = 0x01 & r->rts_on_send;
1414 info->rs485.rts_after_sent = 0x01 & r->rts_after_sent;
1415 if (r->delay_rts_before_send >= 1000)
1416 info->rs485.delay_rts_before_send = 1000;
1417 else
1418 info->rs485.delay_rts_before_send = r->delay_rts_before_send;
1419 info->rs485.enabled = r->enabled;
1420/* printk("rts: on send = %i, after = %i, enabled = %i",
1421 info->rs485.rts_on_send,
1422 info->rs485.rts_after_sent,
1423 info->rs485.enabled
1424 );
1425*/
1426 return 0;
1427}
1428
1429static int
77accbf5 1430e100_write_rs485(struct tty_struct *tty,
1da177e4
LT		 1431 const unsigned char *buf, int count)
1432{
1433 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1434 int old_enabled = info->rs485.enabled;
1435
1436 /* rs485 is always implicitly enabled if we're using the ioctl()
1437 * but it doesn't have to be set in the rs485_control
1438 * (to be backward compatible with old apps)
1439 * So we store, set and restore it.
1440 */
1441 info->rs485.enabled = 1;
1442 /* rs_write now deals with RS485 if enabled */
77accbf5 1443 count = rs_write(tty, buf, count);
1da177e4
LT		 1444 info->rs485.enabled = old_enabled;
1445 return count;
1446}
1447
1448#ifdef CONFIG_ETRAX_FAST_TIMER
1449/* Timer function to toggle RTS when using FAST_TIMER */
1450static void rs485_toggle_rts_timer_function(unsigned long data)
1451{
1452 struct e100_serial *info = (struct e100_serial *)data;
1453
1454 fast_timers_rs485[info->line].function = NULL;
1455 e100_rts(info, info->rs485.rts_after_sent);
1456#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1457 e100_enable_rx(info);
1458 e100_enable_rx_irq(info);
1459#endif
1460}
1461#endif
1462#endif /* CONFIG_ETRAX_RS485 */
1463
1464/*
1465 * ------------------------------------------------------------
1466 * rs_stop() and rs_start()
1467 *
1468 * This routines are called before setting or resetting tty->stopped.
1469 * They enable or disable transmitter using the XOFF registers, as necessary.
1470 * ------------------------------------------------------------
1471 */
1472
1473static void
1474rs_stop(struct tty_struct *tty)
1475{
1476 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1477 if (info) {
1478 unsigned long flags;
1479 unsigned long xoff;
1480
77accbf5 1481 local_irq_save(flags);
1da177e4
LT		 1482 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1483 CIRC_CNT(info->xmit.head,
1484 info->xmit.tail,SERIAL_XMIT_SIZE)));
1485
1486 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->tty));
1487 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1488 if (tty->termios->c_iflag & IXON ) {
1489 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1490 }
1491
1492 *((unsigned long *)&info->port[REG_XOFF]) = xoff;
77accbf5 1493 local_irq_restore(flags);
1da177e4
LT		 1494 }
1495}
1496
1497static void
1498rs_start(struct tty_struct *tty)
1499{
1500 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1501 if (info) {
1502 unsigned long flags;
1503 unsigned long xoff;
1504
77accbf5 1505 local_irq_save(flags);
1da177e4
LT		 1506 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1507 CIRC_CNT(info->xmit.head,
1508 info->xmit.tail,SERIAL_XMIT_SIZE)));
1509 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1510 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1511 if (tty->termios->c_iflag & IXON ) {
1512 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1513 }
1514
1515 *((unsigned long *)&info->port[REG_XOFF]) = xoff;
1516 if (!info->uses_dma_out &&
1517 info->xmit.head != info->xmit.tail && info->xmit.buf)
1518 e100_enable_serial_tx_ready_irq(info);
1519
77accbf5 1520 local_irq_restore(flags);
1da177e4
LT		 1521 }
1522}
1523
1524/*
1525 * ----------------------------------------------------------------------
1526 *
1527 * Here starts the interrupt handling routines. All of the following
1528 * subroutines are declared as inline and are folded into
1529 * rs_interrupt(). They were separated out for readability's sake.
1530 *
1531 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1532 * runs with interrupts turned off. People who may want to modify
1533 * rs_interrupt() should try to keep the interrupt handler as fast as
1534 * possible. After you are done making modifications, it is not a bad
1535 * idea to do:
1536 *
1537 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1538 *
1539 * and look at the resulting assemble code in serial.s.
1540 *
1541 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1542 * -----------------------------------------------------------------------
1543 */
1544
1545/*
1546 * This routine is used by the interrupt handler to schedule
1547 * processing in the software interrupt portion of the driver.
1548 */
41c28ff1 1549static void rs_sched_event(struct e100_serial *info, int event)
1da177e4
LT		 1550{
1551 if (info->event & (1 << event))
1552 return;
1553 info->event |= 1 << event;
1554 schedule_work(&info->work);
1555}
1556
1557/* The output DMA channel is free - use it to send as many chars as possible
1558 * NOTES:
1559 * We don't pay attention to info->x_char, which means if the TTY wants to
1560 * use XON/XOFF it will set info->x_char but we won't send any X char!
1561 *
1562 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1563 * buffer containing the X char, and skip updating xmit. We'd also have to
1564 * check if the last sent char was the X char when we enter this function
1565 * the next time, to avoid updating xmit with the sent X value.
1566 */
1567
1568static void
1569transmit_chars_dma(struct e100_serial *info)
1570{
1571 unsigned int c, sentl;
1572 struct etrax_dma_descr *descr;
1573
1574#ifdef CONFIG_SVINTO_SIM
1575 /* This will output too little if tail is not 0 always since
1576 * we don't reloop to send the other part. Anyway this SHOULD be a
1577 * no-op - transmit_chars_dma would never really be called during sim
1578 * since rs_write does not write into the xmit buffer then.
1579 */
1580 if (info->xmit.tail)
1581 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1582 if (info->xmit.head != info->xmit.tail) {
1583 SIMCOUT(info->xmit.buf + info->xmit.tail,
1584 CIRC_CNT(info->xmit.head,
1585 info->xmit.tail,
1586 SERIAL_XMIT_SIZE));
1587 info->xmit.head = info->xmit.tail; /* move back head */
1588 info->tr_running = 0;
1589 }
1590 return;
1591#endif
1592 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1593 *info->oclrintradr =
1594 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1595 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1596
1597#ifdef SERIAL_DEBUG_INTR
1598 if (info->line == SERIAL_DEBUG_LINE)
1599 printk("tc\n");
1600#endif
1601 if (!info->tr_running) {
1602 /* weirdo... we shouldn't get here! */
1603 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1604 return;
1605 }
1606
1607 descr = &info->tr_descr;
1608
1609 /* first get the amount of bytes sent during the last DMA transfer,
1610 and update xmit accordingly */
1611
1612 /* if the stop bit was not set, all data has been sent */
1613 if (!(descr->status & d_stop)) {
1614 sentl = descr->sw_len;
1615 } else
1616 /* otherwise we find the amount of data sent here */
1617 sentl = descr->hw_len;
1618
1619 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1620
1621 /* update stats */
1622 info->icount.tx += sentl;
1623
1624 /* update xmit buffer */
1625 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1626
1627 /* if there is only a few chars left in the buf, wake up the blocked
1628 write if any */
1629 if (CIRC_CNT(info->xmit.head,
1630 info->xmit.tail,
1631 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1632 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1633
1634 /* find out the largest amount of consecutive bytes we want to send now */
1635
1636 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1637
1638 /* Don't send all in one DMA transfer - divide it so we wake up
1639 * application before all is sent
1640 */
1641
1642 if (c >= 4*WAKEUP_CHARS)
1643 c = c/2;
1644
1645 if (c <= 0) {
1646 /* our job here is done, don't schedule any new DMA transfer */
1647 info->tr_running = 0;
1648
1649#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1650 if (info->rs485.enabled) {
1651 /* Set a short timer to toggle RTS */
1652 start_one_shot_timer(&fast_timers_rs485[info->line],
1653 rs485_toggle_rts_timer_function,
1654 (unsigned long)info,
1655 info->char_time_usec*2,
1656 "RS-485");
1657 }
1658#endif /* RS485 */
1659 return;
1660 }
1661
1662 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1663 /* set up the descriptor correctly for output */
1664 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1665 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1666 descr->sw_len = c;
1667 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1668 descr->status = 0;
1669
1670 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1671 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1672
1673 /* DMA is now running (hopefully) */
1674} /* transmit_chars_dma */
1675
1676static void
1677start_transmit(struct e100_serial *info)
1678{
1679#if 0
1680 if (info->line == SERIAL_DEBUG_LINE)
1681 printk("x\n");
1682#endif
1683
1684 info->tr_descr.sw_len = 0;
1685 info->tr_descr.hw_len = 0;
1686 info->tr_descr.status = 0;
1687 info->tr_running = 1;
1688 if (info->uses_dma_out)
1689 transmit_chars_dma(info);
1690 else
1691 e100_enable_serial_tx_ready_irq(info);
1692} /* start_transmit */
1693
1694#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1695static int serial_fast_timer_started = 0;
1696static int serial_fast_timer_expired = 0;
1697static void flush_timeout_function(unsigned long data);
1698#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1699 unsigned long timer_flags; \
77accbf5 1700 local_irq_save(timer_flags); \
1da177e4
LT		 1701 if (fast_timers[info->line].function == NULL) { \
1702 serial_fast_timer_started++; \
1703 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1704 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1705 start_one_shot_timer(&fast_timers[info->line], \
1706 flush_timeout_function, \
1707 (unsigned long)info, \
1708 (usec), \
1709 string); \
1710 } \
1711 else { \
1712 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1713 } \
77accbf5 1714 local_irq_restore(timer_flags); \
1da177e4
LT		 1715}
1716#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1717
1718#else
1719#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1720#define START_FLUSH_FAST_TIMER(info, string)
1721#endif
1722
1723static struct etrax_recv_buffer *
1724alloc_recv_buffer(unsigned int size)
1725{
1726 struct etrax_recv_buffer *buffer;
1727
1728 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1729 return NULL;
1730
1731 buffer->next = NULL;
1732 buffer->length = 0;
1733 buffer->error = TTY_NORMAL;
1734
1735 return buffer;
1736}
1737
1738static void
1739append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1740{
1741 unsigned long flags;
1742
77accbf5 1743 local_irq_save(flags);
1da177e4
LT		 1744
1745 if (!info->first_recv_buffer)
1746 info->first_recv_buffer = buffer;
1747 else
1748 info->last_recv_buffer->next = buffer;
1749
1750 info->last_recv_buffer = buffer;
1751
1752 info->recv_cnt += buffer->length;
1753 if (info->recv_cnt > info->max_recv_cnt)
1754 info->max_recv_cnt = info->recv_cnt;
1755
77accbf5 1756 local_irq_restore(flags);
1da177e4
LT		 1757}
1758
1759static int
1760add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1761{
1762 struct etrax_recv_buffer *buffer;
1763 if (info->uses_dma_in) {
1764 if (!(buffer = alloc_recv_buffer(4)))
1765 return 0;
1766
1767 buffer->length = 1;
1768 buffer->error = flag;
1769 buffer->buffer[0] = data;
1770
1771 append_recv_buffer(info, buffer);
1772
1773 info->icount.rx++;
1774 } else {
1775 struct tty_struct *tty = info->tty;
77accbf5 1776 tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 1777 info->icount.rx++;
1778 }
1779
1780 return 1;
1781}
1782
41c28ff1
AB		 1783static unsigned int handle_descr_data(struct e100_serial *info,
1784 struct etrax_dma_descr *descr,
1785 unsigned int recvl)
1da177e4
LT		 1786{
1787 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1788
1789 if (info->recv_cnt + recvl > 65536) {
1790 printk(KERN_CRIT
1791 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __FUNCTION__, recvl);
1792 return 0;
1793 }
1794
1795 buffer->length = recvl;
1796
1797 if (info->errorcode == ERRCODE_SET_BREAK)
1798 buffer->error = TTY_BREAK;
1799 info->errorcode = 0;
1800
1801 append_recv_buffer(info, buffer);
1802
1803 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1804 panic("%s: Failed to allocate memory for receive buffer!\n", __FUNCTION__);
1805
1806 descr->buf = virt_to_phys(buffer->buffer);
1807
1808 return recvl;
1809}
1810
41c28ff1 1811static unsigned int handle_all_descr_data(struct e100_serial *info)
1da177e4
LT		 1812{
1813 struct etrax_dma_descr *descr;
1814 unsigned int recvl;
1815 unsigned int ret = 0;
1816
1817 while (1)
1818 {
1819 descr = &info->rec_descr[info->cur_rec_descr];
1820
1821 if (descr == phys_to_virt(*info->idescradr))
1822 break;
1823
1824 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1825 info->cur_rec_descr = 0;
1826
1827 /* find out how many bytes were read */
1828
1829 /* if the eop bit was not set, all data has been received */
1830 if (!(descr->status & d_eop)) {
1831 recvl = descr->sw_len;
1832 } else {
1833 /* otherwise we find the amount of data received here */
1834 recvl = descr->hw_len;
1835 }
1836
1837 /* Reset the status information */
1838 descr->status = 0;
1839
1840 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1841 if (info->tty->stopped) {
1842 unsigned char *buf = phys_to_virt(descr->buf);
1843 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1844 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1845 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1846 }
1847 );
1848
1849 /* update stats */
1850 info->icount.rx += recvl;
1851
1852 ret += handle_descr_data(info, descr, recvl);
1853 }
1854
1855 return ret;
1856}
1857
41c28ff1 1858static void receive_chars_dma(struct e100_serial *info)
1da177e4
LT		 1859{
1860 struct tty_struct *tty;
1861 unsigned char rstat;
1862
1863#ifdef CONFIG_SVINTO_SIM
1864 /* No receive in the simulator. Will probably be when the rest of
1865 * the serial interface works, and this piece will just be removed.
1866 */
1867 return;
1868#endif
1869
1870 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1871 *info->iclrintradr =
1872 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1873 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1874
1875 tty = info->tty;
1876 if (!tty) /* Something wrong... */
1877 return;
1878
1879#ifdef SERIAL_HANDLE_EARLY_ERRORS
1880 if (info->uses_dma_in)
1881 e100_enable_serial_data_irq(info);
1882#endif
1883
1884 if (info->errorcode == ERRCODE_INSERT_BREAK)
1885 add_char_and_flag(info, '\0', TTY_BREAK);
1886
1887 handle_all_descr_data(info);
1888
1889 /* Read the status register to detect errors */
1890 rstat = info->port[REG_STATUS];
1891 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1892 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1893 }
1894
1895 if (rstat & SER_ERROR_MASK) {
1896 /* If we got an error, we must reset it by reading the
1897 * data_in field
1898 */
1899 unsigned char data = info->port[REG_DATA];
1900
1901 PROCSTAT(ser_stat[info->line].errors_cnt++);
1902 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1903 ((rstat & SER_ERROR_MASK) << 8) | data);
1904
1905 if (rstat & SER_PAR_ERR_MASK)
1906 add_char_and_flag(info, data, TTY_PARITY);
1907 else if (rstat & SER_OVERRUN_MASK)
1908 add_char_and_flag(info, data, TTY_OVERRUN);
1909 else if (rstat & SER_FRAMING_ERR_MASK)
1910 add_char_and_flag(info, data, TTY_FRAME);
1911 }
1912
1913 START_FLUSH_FAST_TIMER(info, "receive_chars");
1914
1915 /* Restart the receiving DMA */
1916 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1917}
1918
41c28ff1 1919static int start_recv_dma(struct e100_serial *info)
1da177e4
LT		 1920{
1921 struct etrax_dma_descr *descr = info->rec_descr;
1922 struct etrax_recv_buffer *buffer;
1923 int i;
1924
1925 /* Set up the receiving descriptors */
1926 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1927 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1928 panic("%s: Failed to allocate memory for receive buffer!\n", __FUNCTION__);
1929
1930 descr[i].ctrl = d_int;
1931 descr[i].buf = virt_to_phys(buffer->buffer);
1932 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1933 descr[i].hw_len = 0;
1934 descr[i].status = 0;
1935 descr[i].next = virt_to_phys(&descr[i+1]);
1936 }
1937
1938 /* Link the last descriptor to the first */
1939 descr[i-1].next = virt_to_phys(&descr[0]);
1940
1941 /* Start with the first descriptor in the list */
1942 info->cur_rec_descr = 0;
1943
1944 /* Start the DMA */
1945 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1946 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1947
1948 /* Input DMA should be running now */
1949 return 1;
1950}
1951
1952static void
1953start_receive(struct e100_serial *info)
1954{
1955#ifdef CONFIG_SVINTO_SIM
1956 /* No receive in the simulator. Will probably be when the rest of
1957 * the serial interface works, and this piece will just be removed.
1958 */
1959 return;
1960#endif
1da177e4
LT		 1961 if (info->uses_dma_in) {
1962 /* reset the input dma channel to be sure it works */
1963
1964 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1965 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1966 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1967
1968 start_recv_dma(info);
1969 }
1970}
1971
1972
1da177e4
LT		 1973/* the bits in the MASK2 register are laid out like this:
1974 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1975 where I is the input channel and O is the output channel for the port.
1976 info->irq is the bit number for the DMAO_DESCR so to check the others we
1977 shift info->irq to the left.
1978*/
1979
1980/* dma output channel interrupt handler
1981 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1982 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1983*/
1984
1985static irqreturn_t
7d12e780 1986tr_interrupt(int irq, void *dev_id)
1da177e4
LT		 1987{
1988 struct e100_serial *info;
1989 unsigned long ireg;
1990 int i;
1991 int handled = 0;
1992
1993#ifdef CONFIG_SVINTO_SIM
1994 /* No receive in the simulator. Will probably be when the rest of
1995 * the serial interface works, and this piece will just be removed.
1996 */
1997 {
1998 const char *s = "What? tr_interrupt in simulator??\n";
1999 SIMCOUT(s,strlen(s));
2000 }
2001 return IRQ_HANDLED;
2002#endif
2003
2004 /* find out the line that caused this irq and get it from rs_table */
2005
2006 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2007
2008 for (i = 0; i < NR_PORTS; i++) {
2009 info = rs_table + i;
2010 if (!info->enabled || !info->uses_dma_out)
2011 continue;
2012 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2013 if (ireg & info->irq) {
2014 handled = 1;
2015 /* we can send a new dma bunch. make it so. */
2016 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2017 /* Read jiffies_usec first,
2018 * we want this time to be as late as possible
2019 */
2020 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2021 info->last_tx_active_usec = GET_JIFFIES_USEC();
2022 info->last_tx_active = jiffies;
2023 transmit_chars_dma(info);
2024 }
2025
2026 /* FIXME: here we should really check for a change in the
2027 status lines and if so call status_handle(info) */
2028 }
2029 return IRQ_RETVAL(handled);
2030} /* tr_interrupt */
2031
2032/* dma input channel interrupt handler */
2033
2034static irqreturn_t
7d12e780 2035rec_interrupt(int irq, void *dev_id)
1da177e4
LT		 2036{
2037 struct e100_serial *info;
2038 unsigned long ireg;
2039 int i;
2040 int handled = 0;
2041
2042#ifdef CONFIG_SVINTO_SIM
2043 /* No receive in the simulator. Will probably be when the rest of
2044 * the serial interface works, and this piece will just be removed.
2045 */
2046 {
2047 const char *s = "What? rec_interrupt in simulator??\n";
2048 SIMCOUT(s,strlen(s));
2049 }
2050 return IRQ_HANDLED;
2051#endif
2052
2053 /* find out the line that caused this irq and get it from rs_table */
2054
2055 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2056
2057 for (i = 0; i < NR_PORTS; i++) {
2058 info = rs_table + i;
2059 if (!info->enabled || !info->uses_dma_in)
2060 continue;
2061 /* check for both dma_eop and dma_descr for the input dma channel */
2062 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2063 handled = 1;
2064 /* we have received something */
2065 receive_chars_dma(info);
2066 }
2067
2068 /* FIXME: here we should really check for a change in the
2069 status lines and if so call status_handle(info) */
2070 }
2071 return IRQ_RETVAL(handled);
2072} /* rec_interrupt */
2073
41c28ff1 2074static int force_eop_if_needed(struct e100_serial *info)
1da177e4
LT		 2075{
2076 /* We check data_avail bit to determine if data has
2077 * arrived since last time
2078 */
2079 unsigned char rstat = info->port[REG_STATUS];
2080
2081 /* error or datavail? */
2082 if (rstat & SER_ERROR_MASK) {
2083 /* Some error has occurred. If there has been valid data, an
2084 * EOP interrupt will be made automatically. If no data, the
2085 * normal ser_interrupt should be enabled and handle it.
2086 * So do nothing!
2087 */
2088 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2089 rstat | (info->line << 8));
2090 return 0;
2091 }
2092
2093 if (rstat & SER_DATA_AVAIL_MASK) {
2094 /* Ok data, no error, count it */
2095 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2096 rstat | (info->line << 8)));
2097 /* Read data to clear status flags */
2098 (void)info->port[REG_DATA];
2099
2100 info->forced_eop = 0;
2101 START_FLUSH_FAST_TIMER(info, "magic");
2102 return 0;
2103 }
2104
2105 /* hit the timeout, force an EOP for the input
2106 * dma channel if we haven't already
2107 */
2108 if (!info->forced_eop) {
2109 info->forced_eop = 1;
2110 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2111 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2112 FORCE_EOP(info);
2113 }
2114
2115 return 1;
2116}
2117
41c28ff1 2118static void flush_to_flip_buffer(struct e100_serial *info)
1da177e4
LT		 2119{
2120 struct tty_struct *tty;
2121 struct etrax_recv_buffer *buffer;
1da177e4 2122 unsigned long flags;
1da177e4 2123
77accbf5
JN		 2124 local_irq_save(flags);
2125 tty = info->tty;
1da177e4 2126
77accbf5
JN		 2127 if (!tty) {
2128 local_irq_restore(flags);
1da177e4
LT		 2129 return;
2130 }
2131
2090ab05 2132 while ((buffer = info->first_recv_buffer) != NULL) {
1da177e4
LT		 2133 unsigned int count = buffer->length;
2134
77accbf5 2135 tty_insert_flip_string(tty, buffer->buffer, count);
1da177e4 2136 info->recv_cnt -= count;
1da177e4
LT		 2137
2138 if (count == buffer->length) {
2139 info->first_recv_buffer = buffer->next;
2140 kfree(buffer);
2141 } else {
2142 buffer->length -= count;
2143 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2144 buffer->error = TTY_NORMAL;
2145 }
2146 }
2147
2148 if (!info->first_recv_buffer)
2149 info->last_recv_buffer = NULL;
2150
77accbf5 2151 local_irq_restore(flags);
1da177e4 2152
77accbf5 2153 /* This includes a check for low-latency */
1da177e4
LT		 2154 tty_flip_buffer_push(tty);
2155}
2156
41c28ff1 2157static void check_flush_timeout(struct e100_serial *info)
1da177e4
LT		 2158{
2159 /* Flip what we've got (if we can) */
2160 flush_to_flip_buffer(info);
2161
2162 /* We might need to flip later, but not to fast
2163 * since the system is busy processing input... */
2164 if (info->first_recv_buffer)
2165 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2166
2167 /* Force eop last, since data might have come while we're processing
2168 * and if we started the slow timer above, we won't start a fast
2169 * below.
2170 */
2171 force_eop_if_needed(info);
2172}
2173
2174#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2175static void flush_timeout_function(unsigned long data)
2176{
2177 struct e100_serial *info = (struct e100_serial *)data;
2178
2179 fast_timers[info->line].function = NULL;
2180 serial_fast_timer_expired++;
2181 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2182 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2183 check_flush_timeout(info);
2184}
2185
2186#else
2187
2188/* dma fifo/buffer timeout handler
2189 forces an end-of-packet for the dma input channel if no chars
2190 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2191*/
2192
2193static struct timer_list flush_timer;
2194
2195static void
2196timed_flush_handler(unsigned long ptr)
2197{
2198 struct e100_serial *info;
2199 int i;
2200
2201#ifdef CONFIG_SVINTO_SIM
2202 return;
2203#endif
2204
2205 for (i = 0; i < NR_PORTS; i++) {
2206 info = rs_table + i;
2207 if (info->uses_dma_in)
2208 check_flush_timeout(info);
2209 }
2210
2211 /* restart flush timer */
2212 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2213}
2214#endif
2215
2216#ifdef SERIAL_HANDLE_EARLY_ERRORS
2217
2218/* If there is an error (ie break) when the DMA is running and
2219 * there are no bytes in the fifo the DMA is stopped and we get no
2220 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2221 * transfer, and if it is without error we can turn the serial
2222 * interrupts off.
2223 */
2224
2225/*
2226BREAK handling on ETRAX 100:
2227ETRAX will generate interrupt although there is no stop bit between the
2228characters.
2229
2230Depending on how long the break sequence is, the end of the breaksequence
2231will look differently:
2232| indicates start/end of a character.
2233
2234B= Break character (0x00) with framing error.
2235E= Error byte with parity error received after B characters.
2236F= "Faked" valid byte received immediately after B characters.
2237V= Valid byte
2238
22391.
2240 B BL ___________________________ V
2241.._|__________|__________| |valid data |
2242
2243Multiple frame errors with data == 0x00 (B),
2244the timing matches up "perfectly" so no extra ending char is detected.
2245The RXD pin is 1 in the last interrupt, in that case
2246we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2247know if another byte will come and this really is case 2. below
2248(e.g F=0xFF or 0xFE)
2249If RXD pin is 0 we can expect another character (see 2. below).
2250
2251
22522.
2253
2254 B B E or F__________________..__ V
2255.._|__________|__________|______ | |valid data
2256 "valid" or
2257 parity error
2258
2259Multiple frame errors with data == 0x00 (B),
2260but the part of the break trigs is interpreted as a start bit (and possibly
2261some 0 bits followed by a number of 1 bits and a stop bit).
2262Depending on parity settings etc. this last character can be either
2263a fake "valid" char (F) or have a parity error (E).
2264
2265If the character is valid it will be put in the buffer,
2266we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2267will set the flags so the tty will handle it,
2268if it's an error byte it will not be put in the buffer
2269and we set info->errorcode = ERRCODE_INSERT_BREAK.
2270
2271To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2272of the last faulty char (B) and compares it with the current time:
2273If the time elapsed time is less then 2*char_time_usec we will assume
2274it's a faked F char and not a Valid char and set
2275info->errorcode = ERRCODE_SET_BREAK.
2276
2277Flaws in the above solution:
2278~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2279We use the timer to distinguish a F character from a V character,
2280if a V character is to close after the break we might make the wrong decision.
2281
2282TODO: The break will be delayed until an F or V character is received.
2283
2284*/
2285
41c28ff1 2286static
1da177e4
LT		 2287struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2288{
2289 unsigned long data_read;
2290 struct tty_struct *tty = info->tty;
2291
2292 if (!tty) {
2293 printk("!NO TTY!\n");
2294 return info;
2295 }
77accbf5 2296
1da177e4
LT		 2297 /* Read data and status at the same time */
2298 data_read = *((unsigned long *)&info->port[REG_DATA_STATUS32]);
2299more_data:
2300 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2301 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2302 }
2303 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2304
2305 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2306 IO_MASK(R_SERIAL0_READ, par_err) |
2307 IO_MASK(R_SERIAL0_READ, overrun) )) {
2308 /* An error */
2309 info->last_rx_active_usec = GET_JIFFIES_USEC();
2310 info->last_rx_active = jiffies;
2311 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2312 DLOG_INT_TRIG(
2313 if (!log_int_trig1_pos) {
2314 log_int_trig1_pos = log_int_pos;
2315 log_int(rdpc(), 0, 0);
2316 }
2317 );
2318
2319
2320 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2321 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2322 /* Most likely a break, but we get interrupts over and
2323 * over again.
2324 */
2325
2326 if (!info->break_detected_cnt) {
2327 DEBUG_LOG(info->line, "#BRK start\n", 0);
2328 }
2329 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2330 /* The RX pin is high now, so the break
2331 * must be over, but....
2332 * we can't really know if we will get another
2333 * last byte ending the break or not.
2334 * And we don't know if the byte (if any) will
2335 * have an error or look valid.
2336 */
2337 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2338 info->errorcode = ERRCODE_INSERT_BREAK;
2339 }
2340 info->break_detected_cnt++;
2341 } else {
2342 /* The error does not look like a break, but could be
2343 * the end of one
2344 */
2345 if (info->break_detected_cnt) {
2346 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2347 info->errorcode = ERRCODE_INSERT_BREAK;
2348 } else {
77accbf5
JN		 2349 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2350 data_in, data_read);
2351 char flag = TTY_NORMAL;
1da177e4 2352 if (info->errorcode == ERRCODE_INSERT_BREAK) {
77accbf5
JN		 2353 struct tty_struct *tty = info->tty;
2354 tty_insert_flip_char(tty, 0, flag);
1da177e4
LT		 2355 info->icount.rx++;
2356 }
1da177e4
LT		 2357
2358 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2359 info->icount.parity++;
77accbf5 2360 flag = TTY_PARITY;
1da177e4
LT		 2361 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2362 info->icount.overrun++;
77accbf5 2363 flag = TTY_OVERRUN;
1da177e4
LT		 2364 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2365 info->icount.frame++;
77accbf5 2366 flag = TTY_FRAME;
1da177e4 2367 }
77accbf5 2368 tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 2369 info->errorcode = 0;
2370 }
2371 info->break_detected_cnt = 0;
2372 }
2373 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2374 /* No error */
2375 DLOG_INT_TRIG(
2376 if (!log_int_trig1_pos) {
2377 if (log_int_pos >= log_int_size) {
2378 log_int_pos = 0;
2379 }
2380 log_int_trig0_pos = log_int_pos;
2381 log_int(rdpc(), 0, 0);
2382 }
2383 );
77accbf5
JN		 2384 tty_insert_flip_char(tty,
2385 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2386 TTY_NORMAL);
1da177e4
LT		 2387 } else {
2388 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2389 }
2390
2391
1da177e4
LT		 2392 info->icount.rx++;
2393 data_read = *((unsigned long *)&info->port[REG_DATA_STATUS32]);
2394 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2395 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2396 goto more_data;
2397 }
2398
2399 tty_flip_buffer_push(info->tty);
2400 return info;
2401}
2402
41c28ff1 2403static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
1da177e4
LT		 2404{
2405 unsigned char rstat;
2406
2407#ifdef SERIAL_DEBUG_INTR
2408 printk("Interrupt from serport %d\n", i);
2409#endif
2410/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2411 if (!info->uses_dma_in) {
2412 return handle_ser_rx_interrupt_no_dma(info);
2413 }
2414 /* DMA is used */
2415 rstat = info->port[REG_STATUS];
2416 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2417 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2418 }
2419
2420 if (rstat & SER_ERROR_MASK) {
2421 unsigned char data;
2422
2423 info->last_rx_active_usec = GET_JIFFIES_USEC();
2424 info->last_rx_active = jiffies;
2425 /* If we got an error, we must reset it by reading the
2426 * data_in field
2427 */
2428 data = info->port[REG_DATA];
2429 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2430 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2431 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2432 /* Most likely a break, but we get interrupts over and
2433 * over again.
2434 */
2435
2436 if (!info->break_detected_cnt) {
2437 DEBUG_LOG(info->line, "#BRK start\n", 0);
2438 }
2439 if (rstat & SER_RXD_MASK) {
2440 /* The RX pin is high now, so the break
2441 * must be over, but....
2442 * we can't really know if we will get another
2443 * last byte ending the break or not.
2444 * And we don't know if the byte (if any) will
2445 * have an error or look valid.
2446 */
2447 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2448 info->errorcode = ERRCODE_INSERT_BREAK;
2449 }
2450 info->break_detected_cnt++;
2451 } else {
2452 /* The error does not look like a break, but could be
2453 * the end of one
2454 */
2455 if (info->break_detected_cnt) {
2456 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2457 info->errorcode = ERRCODE_INSERT_BREAK;
2458 } else {
2459 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2460 info->icount.brk++;
2461 add_char_and_flag(info, '\0', TTY_BREAK);
2462 }
2463
2464 if (rstat & SER_PAR_ERR_MASK) {
2465 info->icount.parity++;
2466 add_char_and_flag(info, data, TTY_PARITY);
2467 } else if (rstat & SER_OVERRUN_MASK) {
2468 info->icount.overrun++;
2469 add_char_and_flag(info, data, TTY_OVERRUN);
2470 } else if (rstat & SER_FRAMING_ERR_MASK) {
2471 info->icount.frame++;
2472 add_char_and_flag(info, data, TTY_FRAME);
2473 }
2474
2475 info->errorcode = 0;
2476 }
2477 info->break_detected_cnt = 0;
2478 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2479 ((rstat & SER_ERROR_MASK) << 8) | data);
2480 }
2481 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2482 } else { /* It was a valid byte, now let the DMA do the rest */
2483 unsigned long curr_time_u = GET_JIFFIES_USEC();
2484 unsigned long curr_time = jiffies;
2485
2486 if (info->break_detected_cnt) {
2487 /* Detect if this character is a new valid char or the
2488 * last char in a break sequence: If LSBits are 0 and
2489 * MSBits are high AND the time is close to the
2490 * previous interrupt we should discard it.
2491 */
2492 long elapsed_usec =
2493 (curr_time - info->last_rx_active) * (1000000/HZ) +
2494 curr_time_u - info->last_rx_active_usec;
2495 if (elapsed_usec < 2*info->char_time_usec) {
2496 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2497 /* Report as BREAK (error) and let
2498 * receive_chars_dma() handle it
2499 */
2500 info->errorcode = ERRCODE_SET_BREAK;
2501 } else {
2502 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2503 }
2504 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2505 }
2506
2507#ifdef SERIAL_DEBUG_INTR
2508 printk("** OK, disabling ser_interrupts\n");
2509#endif
2510 e100_disable_serial_data_irq(info);
2511 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2512 info->break_detected_cnt = 0;
2513
2514 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2515 }
2516 /* Restarting the DMA never hurts */
2517 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2518 START_FLUSH_FAST_TIMER(info, "ser_int");
2519 return info;
2520} /* handle_ser_rx_interrupt */
2521
41c28ff1 2522static void handle_ser_tx_interrupt(struct e100_serial *info)
1da177e4
LT		 2523{
2524 unsigned long flags;
2525
2526 if (info->x_char) {
2527 unsigned char rstat;
2528 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
77accbf5 2529 local_irq_save(flags);
1da177e4
LT		 2530 rstat = info->port[REG_STATUS];
2531 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2532
2533 info->port[REG_TR_DATA] = info->x_char;
2534 info->icount.tx++;
2535 info->x_char = 0;
2536 /* We must enable since it is disabled in ser_interrupt */
2537 e100_enable_serial_tx_ready_irq(info);
77accbf5 2538 local_irq_restore(flags);
1da177e4
LT		 2539 return;
2540 }
2541 if (info->uses_dma_out) {
2542 unsigned char rstat;
2543 int i;
2544 /* We only use normal tx interrupt when sending x_char */
2545 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
77accbf5 2546 local_irq_save(flags);
1da177e4
LT		 2547 rstat = info->port[REG_STATUS];
2548 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2549 e100_disable_serial_tx_ready_irq(info);
2550 if (info->tty->stopped)
2551 rs_stop(info->tty);
2552 /* Enable the DMA channel and tell it to continue */
2553 e100_enable_txdma_channel(info);
2554 /* Wait 12 cycles before doing the DMA command */
2555 for(i = 6; i > 0; i--)
2556 nop();
2557
2558 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
77accbf5 2559 local_irq_restore(flags);
1da177e4
LT		 2560 return;
2561 }
2562 /* Normal char-by-char interrupt */
2563 if (info->xmit.head == info->xmit.tail
2564 || info->tty->stopped
2565 || info->tty->hw_stopped) {
2566 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n", info->tty->stopped));
2567 e100_disable_serial_tx_ready_irq(info);
2568 info->tr_running = 0;
2569 return;
2570 }
2571 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2572 /* Send a byte, rs485 timing is critical so turn of ints */
77accbf5 2573 local_irq_save(flags);
1da177e4
LT		 2574 info->port[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2575 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2576 info->icount.tx++;
2577 if (info->xmit.head == info->xmit.tail) {
2578#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2579 if (info->rs485.enabled) {
2580 /* Set a short timer to toggle RTS */
2581 start_one_shot_timer(&fast_timers_rs485[info->line],
2582 rs485_toggle_rts_timer_function,
2583 (unsigned long)info,
2584 info->char_time_usec*2,
2585 "RS-485");
2586 }
2587#endif /* RS485 */
2588 info->last_tx_active_usec = GET_JIFFIES_USEC();
2589 info->last_tx_active = jiffies;
2590 e100_disable_serial_tx_ready_irq(info);
2591 info->tr_running = 0;
2592 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2593 } else {
2594 /* We must enable since it is disabled in ser_interrupt */
2595 e100_enable_serial_tx_ready_irq(info);
2596 }
77accbf5 2597 local_irq_restore(flags);
1da177e4
LT		 2598
2599 if (CIRC_CNT(info->xmit.head,
2600 info->xmit.tail,
2601 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2602 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2603
2604} /* handle_ser_tx_interrupt */
2605
2606/* result of time measurements:
2607 * RX duration 54-60 us when doing something, otherwise 6-9 us
2608 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2609 */
2610static irqreturn_t
7d12e780 2611ser_interrupt(int irq, void *dev_id)
1da177e4
LT		 2612{
2613 static volatile int tx_started = 0;
2614 struct e100_serial *info;
2615 int i;
2616 unsigned long flags;
2617 unsigned long irq_mask1_rd;
2618 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2619 int handled = 0;
2620 static volatile unsigned long reentered_ready_mask = 0;
2621
77accbf5 2622 local_irq_save(flags);
1da177e4
LT		 2623 irq_mask1_rd = *R_IRQ_MASK1_RD;
2624 /* First handle all rx interrupts with ints disabled */
2625 info = rs_table;
2626 irq_mask1_rd &= e100_ser_int_mask;
2627 for (i = 0; i < NR_PORTS; i++) {
2628 /* Which line caused the data irq? */
2629 if (irq_mask1_rd & data_mask) {
2630 handled = 1;
2631 handle_ser_rx_interrupt(info);
2632 }
2633 info += 1;
2634 data_mask <<= 2;
2635 }
2636 /* Handle tx interrupts with interrupts enabled so we
2637 * can take care of new data interrupts while transmitting
2638 * We protect the tx part with the tx_started flag.
2639 * We disable the tr_ready interrupts we are about to handle and
2640 * unblock the serial interrupt so new serial interrupts may come.
2641 *
2642 * If we get a new interrupt:
2643 * - it migth be due to synchronous serial ports.
2644 * - serial irq will be blocked by general irq handler.
2645 * - async data will be handled above (sync will be ignored).
2646 * - tx_started flag will prevent us from trying to send again and
2647 * we will exit fast - no need to unblock serial irq.
2648 * - Next (sync) serial interrupt handler will be runned with
2649 * disabled interrupt due to restore_flags() at end of function,
2650 * so sync handler will not be preempted or reentered.
2651 */
2652 if (!tx_started) {
2653 unsigned long ready_mask;
2654 unsigned long
2655 tx_started = 1;
2656 /* Only the tr_ready interrupts left */
2657 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2658 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2659 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2660 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2661 while (irq_mask1_rd) {
2662 /* Disable those we are about to handle */
2663 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2664 /* Unblock the serial interrupt */
2665 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2666
77accbf5 2667 local_irq_enable();
1da177e4
LT		 2668 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2669 info = rs_table;
2670 for (i = 0; i < NR_PORTS; i++) {
2671 /* Which line caused the ready irq? */
2672 if (irq_mask1_rd & ready_mask) {
2673 handled = 1;
2674 handle_ser_tx_interrupt(info);
2675 }
2676 info += 1;
2677 ready_mask <<= 2;
2678 }
2679 /* handle_ser_tx_interrupt enables tr_ready interrupts */
77accbf5 2680 local_irq_disable();
1da177e4
LT		 2681 /* Handle reentered TX interrupt */
2682 irq_mask1_rd = reentered_ready_mask;
2683 }
77accbf5 2684 local_irq_disable();
1da177e4
LT		 2685 tx_started = 0;
2686 } else {
2687 unsigned long ready_mask;
2688 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2689 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2690 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2691 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2692 if (ready_mask) {
2693 reentered_ready_mask |= ready_mask;
2694 /* Disable those we are about to handle */
2695 *R_IRQ_MASK1_CLR = ready_mask;
2696 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2697 }
2698 }
2699
77accbf5 2700 local_irq_restore(flags);
1da177e4
LT		 2701 return IRQ_RETVAL(handled);
2702} /* ser_interrupt */
2703#endif
2704
2705/*
2706 * -------------------------------------------------------------------
2707 * Here ends the serial interrupt routines.
2708 * -------------------------------------------------------------------
2709 */
2710
2711/*
2712 * This routine is used to handle the "bottom half" processing for the
2713 * serial driver, known also the "software interrupt" processing.
2714 * This processing is done at the kernel interrupt level, after the
2715 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2716 * is where time-consuming activities which can not be done in the
2717 * interrupt driver proper are done; the interrupt driver schedules
2718 * them using rs_sched_event(), and they get done here.
2719 */
2720static void
77accbf5 2721do_softint(struct work_struct *work)
1da177e4 2722{
77accbf5 2723 struct e100_serial *info;
1da177e4
LT		 2724 struct tty_struct *tty;
2725
77accbf5
JN		 2726 info = container_of(work, struct e100_serial, work);
2727
1da177e4
LT		 2728 tty = info->tty;
2729 if (!tty)
2730 return;
2731
b963a844
JS		 2732 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2733 tty_wakeup(tty);
1da177e4
LT		 2734}
2735
2736static int
2737startup(struct e100_serial * info)
2738{
2739 unsigned long flags;
2740 unsigned long xmit_page;
2741 int i;
2742
2743 xmit_page = get_zeroed_page(GFP_KERNEL);
2744 if (!xmit_page)
2745 return -ENOMEM;
2746
77accbf5 2747 local_irq_save(flags);
1da177e4
LT		 2748
2749 /* if it was already initialized, skip this */
2750
2751 if (info->flags & ASYNC_INITIALIZED) {
77accbf5 2752 local_irq_restore(flags);
1da177e4
LT		 2753 free_page(xmit_page);
2754 return 0;
2755 }
2756
2757 if (info->xmit.buf)
2758 free_page(xmit_page);
2759 else
2760 info->xmit.buf = (unsigned char *) xmit_page;
2761
2762#ifdef SERIAL_DEBUG_OPEN
2763 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2764#endif
2765
2766#ifdef CONFIG_SVINTO_SIM
2767 /* Bits and pieces collected from below. Better to have them
2768 in one ifdef:ed clause than to mix in a lot of ifdefs,
2769 right? */
2770 if (info->tty)
2771 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2772
2773 info->xmit.head = info->xmit.tail = 0;
2774 info->first_recv_buffer = info->last_recv_buffer = NULL;
2775 info->recv_cnt = info->max_recv_cnt = 0;
2776
2777 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2778 info->rec_descr[i].buf = NULL;
2779
2780 /* No real action in the simulator, but may set info important
2781 to ioctl. */
2782 change_speed(info);
2783#else
2784
2785 /*
2786 * Clear the FIFO buffers and disable them
2787 * (they will be reenabled in change_speed())
2788 */
2789
2790 /*
2791 * Reset the DMA channels and make sure their interrupts are cleared
2792 */
2793
2794 if (info->dma_in_enabled) {
2795 info->uses_dma_in = 1;
2796 e100_enable_rxdma_channel(info);
2797
2798 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2799
2800 /* Wait until reset cycle is complete */
2801 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2802 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2803
2804 /* Make sure the irqs are cleared */
2805 *info->iclrintradr =
2806 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2807 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2808 } else {
2809 e100_disable_rxdma_channel(info);
2810 }
2811
2812 if (info->dma_out_enabled) {
2813 info->uses_dma_out = 1;
2814 e100_enable_txdma_channel(info);
2815 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2816
2817 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2818 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2819
2820 /* Make sure the irqs are cleared */
2821 *info->oclrintradr =
2822 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2823 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2824 } else {
2825 e100_disable_txdma_channel(info);
2826 }
2827
2828 if (info->tty)
2829 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2830
2831 info->xmit.head = info->xmit.tail = 0;
2832 info->first_recv_buffer = info->last_recv_buffer = NULL;
2833 info->recv_cnt = info->max_recv_cnt = 0;
2834
2835 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2836 info->rec_descr[i].buf = 0;
2837
2838 /*
2839 * and set the speed and other flags of the serial port
2840 * this will start the rx/tx as well
2841 */
2842#ifdef SERIAL_HANDLE_EARLY_ERRORS
2843 e100_enable_serial_data_irq(info);
2844#endif
2845 change_speed(info);
2846
2847 /* dummy read to reset any serial errors */
2848
2849 (void)info->port[REG_DATA];
2850
2851 /* enable the interrupts */
2852 if (info->uses_dma_out)
2853 e100_enable_txdma_irq(info);
2854
2855 e100_enable_rx_irq(info);
2856
2857 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2858
2859 /* setup the dma input descriptor and start dma */
2860
2861 start_receive(info);
2862
2863 /* for safety, make sure the descriptors last result is 0 bytes written */
2864
2865 info->tr_descr.sw_len = 0;
2866 info->tr_descr.hw_len = 0;
2867 info->tr_descr.status = 0;
2868
2869 /* enable RTS/DTR last */
2870
2871 e100_rts(info, 1);
2872 e100_dtr(info, 1);
2873
2874#endif /* CONFIG_SVINTO_SIM */
2875
2876 info->flags |= ASYNC_INITIALIZED;
2877
77accbf5 2878 local_irq_restore(flags);
1da177e4
LT		 2879 return 0;
2880}
2881
2882/*
2883 * This routine will shutdown a serial port; interrupts are disabled, and
2884 * DTR is dropped if the hangup on close termio flag is on.
2885 */
2886static void
2887shutdown(struct e100_serial * info)
2888{
2889 unsigned long flags;
2890 struct etrax_dma_descr *descr = info->rec_descr;
2891 struct etrax_recv_buffer *buffer;
2892 int i;
2893
2894#ifndef CONFIG_SVINTO_SIM
2895 /* shut down the transmitter and receiver */
2896 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2897 e100_disable_rx(info);
2898 info->port[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2899
2900 /* disable interrupts, reset dma channels */
2901 if (info->uses_dma_in) {
2902 e100_disable_rxdma_irq(info);
2903 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2904 info->uses_dma_in = 0;
2905 } else {
2906 e100_disable_serial_data_irq(info);
2907 }
2908
2909 if (info->uses_dma_out) {
2910 e100_disable_txdma_irq(info);
2911 info->tr_running = 0;
2912 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2913 info->uses_dma_out = 0;
2914 } else {
2915 e100_disable_serial_tx_ready_irq(info);
2916 info->tr_running = 0;
2917 }
2918
2919#endif /* CONFIG_SVINTO_SIM */
2920
2921 if (!(info->flags & ASYNC_INITIALIZED))
2922 return;
2923
2924#ifdef SERIAL_DEBUG_OPEN
2925 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2926 info->irq);
2927#endif
2928
77accbf5 2929 local_irq_save(flags);
1da177e4
LT		 2930
2931 if (info->xmit.buf) {
2932 free_page((unsigned long)info->xmit.buf);
2933 info->xmit.buf = NULL;
2934 }
2935
2936 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2937 if (descr[i].buf) {
2938 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2939 kfree(buffer);
2940 descr[i].buf = 0;
2941 }
2942
2943 if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) {
2944 /* hang up DTR and RTS if HUPCL is enabled */
2945 e100_dtr(info, 0);
2946 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2947 }
2948
2949 if (info->tty)
2950 set_bit(TTY_IO_ERROR, &info->tty->flags);
2951
2952 info->flags &= ~ASYNC_INITIALIZED;
77accbf5 2953 local_irq_restore(flags);
1da177e4
LT		 2954}
2955
2956
2957/* change baud rate and other assorted parameters */
2958
2959static void
2960change_speed(struct e100_serial *info)
2961{
2962 unsigned int cflag;
2963 unsigned long xoff;
2964 unsigned long flags;
2965 /* first some safety checks */
2966
2967 if (!info->tty || !info->tty->termios)
2968 return;
2969 if (!info->port)
2970 return;
2971
2972 cflag = info->tty->termios->c_cflag;
2973
2974 /* possibly, the tx/rx should be disabled first to do this safely */
2975
2976 /* change baud-rate and write it to the hardware */
2977 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2978 /* Special baudrate */
2979 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2980 unsigned long alt_source =
2981 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2982 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2983 /* R_ALT_SER_BAUDRATE selects the source */
2984 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2985 (unsigned long)info->baud_base, info->custom_divisor));
2986 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2987 /* 0, 2-65535 (0=65536) */
2988 u16 divisor = info->custom_divisor;
2989 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2990 /* baudrate is 3.125MHz/custom_divisor */
2991 alt_source =
2992 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2993 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2994 alt_source = 0x11;
2995 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2996 *R_SERIAL_PRESCALE = divisor;
2997 info->baud = SERIAL_PRESCALE_BASE/divisor;
2998 }
2999#ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
3000 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
3001 info->custom_divisor == 1) ||
3002 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
3003 info->custom_divisor == 8)) {
3004 /* ext_clk selected */
3005 alt_source =
3006 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
3007 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
3008 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
3009 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
3010 }
1da177e4
LT		 3011#endif
3012 else
3013 {
3014 /* Bad baudbase, we don't support using timer0
3015 * for baudrate.
3016 */
3017 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3018 (unsigned long)info->baud_base, info->custom_divisor);
3019 }
3020 r_alt_ser_baudrate_shadow &= ~mask;
3021 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3022 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3023 } else {
3024 /* Normal baudrate */
3025 /* Make sure we use normal baudrate */
3026 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3027 unsigned long alt_source =
3028 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3029 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3030 r_alt_ser_baudrate_shadow &= ~mask;
3031 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3032#ifndef CONFIG_SVINTO_SIM
3033 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3034#endif /* CONFIG_SVINTO_SIM */
3035
3036 info->baud = cflag_to_baud(cflag);
3037#ifndef CONFIG_SVINTO_SIM
3038 info->port[REG_BAUD] = cflag_to_etrax_baud(cflag);
3039#endif /* CONFIG_SVINTO_SIM */
3040 }
3041
3042#ifndef CONFIG_SVINTO_SIM
3043 /* start with default settings and then fill in changes */
77accbf5 3044 local_irq_save(flags);
1da177e4
LT		 3045 /* 8 bit, no/even parity */
3046 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3047 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3048 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3049
3050 /* 8 bit, no/even parity, 1 stop bit, no cts */
3051 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3052 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3053 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3054 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3055 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3056
3057 if ((cflag & CSIZE) == CS7) {
3058 /* set 7 bit mode */
3059 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3060 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3061 }
3062
3063 if (cflag & CSTOPB) {
3064 /* set 2 stop bit mode */
3065 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3066 }
3067
3068 if (cflag & PARENB) {
3069 /* enable parity */
3070 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3071 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3072 }
3073
3074 if (cflag & CMSPAR) {
3075 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3076 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3077 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3078 }
3079 if (cflag & PARODD) {
3080 /* set odd parity (or Mark if CMSPAR) */
3081 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3082 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3083 }
3084
3085 if (cflag & CRTSCTS) {
3086 /* enable automatic CTS handling */
3087 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3088 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3089 }
3090
3091 /* make sure the tx and rx are enabled */
3092
3093 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3094 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3095
3096 /* actually write the control regs to the hardware */
3097
3098 info->port[REG_TR_CTRL] = info->tx_ctrl;
3099 info->port[REG_REC_CTRL] = info->rx_ctrl;
3100 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->tty));
3101 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3102 if (info->tty->termios->c_iflag & IXON ) {
3103 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n", STOP_CHAR(info->tty)));
3104 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3105 }
3106
3107 *((unsigned long *)&info->port[REG_XOFF]) = xoff;
77accbf5 3108 local_irq_restore(flags);
1da177e4
LT		 3109#endif /* !CONFIG_SVINTO_SIM */
3110
3111 update_char_time(info);
3112
3113} /* change_speed */
3114
3115/* start transmitting chars NOW */
3116
3117static void
3118rs_flush_chars(struct tty_struct *tty)
3119{
3120 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3121 unsigned long flags;
3122
3123 if (info->tr_running ||
3124 info->xmit.head == info->xmit.tail ||
3125 tty->stopped ||
3126 tty->hw_stopped ||
3127 !info->xmit.buf)
3128 return;
3129
3130#ifdef SERIAL_DEBUG_FLOW
3131 printk("rs_flush_chars\n");
3132#endif
3133
3134 /* this protection might not exactly be necessary here */
3135
77accbf5 3136 local_irq_save(flags);
1da177e4 3137 start_transmit(info);
77accbf5 3138 local_irq_restore(flags);
1da177e4
LT		 3139}
3140
77accbf5 3141static int rs_raw_write(struct tty_struct *tty,
41c28ff1 3142 const unsigned char *buf, int count)
1da177e4
LT		 3143{
3144 int c, ret = 0;
3145 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3146 unsigned long flags;
3147
3148 /* first some sanity checks */
3149
3150 if (!tty || !info->xmit.buf || !tmp_buf)
3151 return 0;
3152
3153#ifdef SERIAL_DEBUG_DATA
3154 if (info->line == SERIAL_DEBUG_LINE)
3155 printk("rs_raw_write (%d), status %d\n",
3156 count, info->port[REG_STATUS]);
3157#endif
3158
3159#ifdef CONFIG_SVINTO_SIM
3160 /* Really simple. The output is here and now. */
3161 SIMCOUT(buf, count);
3162 return count;
3163#endif
77accbf5 3164 local_save_flags(flags);
1da177e4
LT		 3165 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3166 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3167
3168
77accbf5
JN		 3169 /* The local_irq_disable/restore_flags pairs below are needed
3170 * because the DMA interrupt handler moves the info->xmit values.
3171 * the memcpy needs to be in the critical region unfortunately,
3172 * because we need to read xmit values, memcpy, write xmit values
3173 * in one atomic operation... this could perhaps be avoided by
3174 * more clever design.
1da177e4 3175 */
77accbf5 3176 local_irq_disable();
1da177e4
LT		 3177 while (count) {
3178 c = CIRC_SPACE_TO_END(info->xmit.head,
3179 info->xmit.tail,
3180 SERIAL_XMIT_SIZE);
3181
3182 if (count < c)
3183 c = count;
3184 if (c <= 0)
3185 break;
3186
3187 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3188 info->xmit.head = (info->xmit.head + c) &
3189 (SERIAL_XMIT_SIZE-1);
3190 buf += c;
3191 count -= c;
3192 ret += c;
3193 }
77accbf5 3194 local_irq_restore(flags);
1da177e4
LT		 3195
3196 /* enable transmitter if not running, unless the tty is stopped
3197 * this does not need IRQ protection since if tr_running == 0
3198 * the IRQ's are not running anyway for this port.
3199 */
3200 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3201
3202 if (info->xmit.head != info->xmit.tail &&
3203 !tty->stopped &&
3204 !tty->hw_stopped &&
3205 !info->tr_running) {
3206 start_transmit(info);
3207 }
3208
3209 return ret;
3210} /* raw_raw_write() */
3211
3212static int
77accbf5 3213rs_write(struct tty_struct *tty,
1da177e4
LT		 3214 const unsigned char *buf, int count)
3215{
3216#if defined(CONFIG_ETRAX_RS485)
3217 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3218
3219 if (info->rs485.enabled)
3220 {
3221 /* If we are in RS-485 mode, we need to toggle RTS and disable
3222 * the receiver before initiating a DMA transfer
3223 */
3224#ifdef CONFIG_ETRAX_FAST_TIMER
3225 /* Abort any started timer */
3226 fast_timers_rs485[info->line].function = NULL;
3227 del_fast_timer(&fast_timers_rs485[info->line]);
3228#endif
3229 e100_rts(info, info->rs485.rts_on_send);
3230#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3231 e100_disable_rx(info);
3232 e100_enable_rx_irq(info);
3233#endif
3234
3235 if (info->rs485.delay_rts_before_send > 0)
3236 msleep(info->rs485.delay_rts_before_send);
3237 }
3238#endif /* CONFIG_ETRAX_RS485 */
3239
77accbf5 3240 count = rs_raw_write(tty, buf, count);
1da177e4
LT		 3241
3242#if defined(CONFIG_ETRAX_RS485)
3243 if (info->rs485.enabled)
3244 {
3245 unsigned int val;
3246 /* If we are in RS-485 mode the following has to be done:
3247 * wait until DMA is ready
3248 * wait on transmit shift register
3249 * toggle RTS
3250 * enable the receiver
3251 */
3252
3253 /* Sleep until all sent */
3254 tty_wait_until_sent(tty, 0);
3255#ifdef CONFIG_ETRAX_FAST_TIMER
3256 /* Now sleep a little more so that shift register is empty */
3257 schedule_usleep(info->char_time_usec * 2);
3258#endif
3259 /* wait on transmit shift register */
3260 do{
3261 get_lsr_info(info, &val);
3262 }while (!(val & TIOCSER_TEMT));
3263
3264 e100_rts(info, info->rs485.rts_after_sent);
3265
3266#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3267 e100_enable_rx(info);
3268 e100_enable_rxdma_irq(info);
3269#endif
3270 }
3271#endif /* CONFIG_ETRAX_RS485 */
3272
3273 return count;
3274} /* rs_write */
3275
3276
3277/* how much space is available in the xmit buffer? */
3278
3279static int
3280rs_write_room(struct tty_struct *tty)
3281{
3282 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3283
3284 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3285}
3286
3287/* How many chars are in the xmit buffer?
3288 * This does not include any chars in the transmitter FIFO.
3289 * Use wait_until_sent for waiting for FIFO drain.
3290 */
3291
3292static int
3293rs_chars_in_buffer(struct tty_struct *tty)
3294{
3295 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3296
3297 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3298}
3299
3300/* discard everything in the xmit buffer */
3301
3302static void
3303rs_flush_buffer(struct tty_struct *tty)
3304{
3305 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3306 unsigned long flags;
3307
77accbf5 3308 local_irq_save(flags);
1da177e4 3309 info->xmit.head = info->xmit.tail = 0;
77accbf5 3310 local_irq_restore(flags);
1da177e4 3311
b963a844 3312 tty_wakeup(tty);
1da177e4
LT		 3313}
3314
3315/*
3316 * This function is used to send a high-priority XON/XOFF character to
3317 * the device
3318 *
3319 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3320 * but we do it in handle_ser_tx_interrupt().
3321 * We disable DMA channel and enable tx ready interrupt and write the
3322 * character when possible.
3323 */
3324static void rs_send_xchar(struct tty_struct *tty, char ch)
3325{
3326 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3327 unsigned long flags;
77accbf5 3328 local_irq_save(flags);
1da177e4
LT		 3329 if (info->uses_dma_out) {
3330 /* Put the DMA on hold and disable the channel */
3331 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3332 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3333 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3334 e100_disable_txdma_channel(info);
3335 }
3336
3337 /* Must make sure transmitter is not stopped before we can transmit */
3338 if (tty->stopped)
3339 rs_start(tty);
3340
3341 /* Enable manual transmit interrupt and send from there */
3342 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3343 info->x_char = ch;
3344 e100_enable_serial_tx_ready_irq(info);
77accbf5 3345 local_irq_restore(flags);
1da177e4
LT		 3346}
3347
3348/*
3349 * ------------------------------------------------------------
3350 * rs_throttle()
3351 *
3352 * This routine is called by the upper-layer tty layer to signal that
3353 * incoming characters should be throttled.
3354 * ------------------------------------------------------------
3355 */
3356static void
3357rs_throttle(struct tty_struct * tty)
3358{
3359 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3360#ifdef SERIAL_DEBUG_THROTTLE
3361 char buf[64];
3362
3363 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3364 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3365#endif
3366 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3367
3368 /* Do RTS before XOFF since XOFF might take some time */
3369 if (tty->termios->c_cflag & CRTSCTS) {
3370 /* Turn off RTS line */
3371 e100_rts(info, 0);
3372 }
3373 if (I_IXOFF(tty))
3374 rs_send_xchar(tty, STOP_CHAR(tty));
3375
3376}
3377
3378static void
3379rs_unthrottle(struct tty_struct * tty)
3380{
3381 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3382#ifdef SERIAL_DEBUG_THROTTLE
3383 char buf[64];
3384
3385 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3386 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3387#endif
3388 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3389 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3390 /* Do RTS before XOFF since XOFF might take some time */
3391 if (tty->termios->c_cflag & CRTSCTS) {
3392 /* Assert RTS line */
3393 e100_rts(info, 1);
3394 }
3395
3396 if (I_IXOFF(tty)) {
3397 if (info->x_char)
3398 info->x_char = 0;
3399 else
3400 rs_send_xchar(tty, START_CHAR(tty));
3401 }
3402
3403}
3404
3405/*
3406 * ------------------------------------------------------------
3407 * rs_ioctl() and friends
3408 * ------------------------------------------------------------
3409 */
3410
3411static int
3412get_serial_info(struct e100_serial * info,
3413 struct serial_struct * retinfo)
3414{
3415 struct serial_struct tmp;
3416
3417 /* this is all probably wrong, there are a lot of fields
3418 * here that we don't have in e100_serial and maybe we
3419 * should set them to something else than 0.
3420 */
3421
3422 if (!retinfo)
3423 return -EFAULT;
3424 memset(&tmp, 0, sizeof(tmp));
3425 tmp.type = info->type;
3426 tmp.line = info->line;
3427 tmp.port = (int)info->port;
3428 tmp.irq = info->irq;
3429 tmp.flags = info->flags;
3430 tmp.baud_base = info->baud_base;
3431 tmp.close_delay = info->close_delay;
3432 tmp.closing_wait = info->closing_wait;
3433 tmp.custom_divisor = info->custom_divisor;
3434 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3435 return -EFAULT;
3436 return 0;
3437}
3438
3439static int
3440set_serial_info(struct e100_serial *info,
3441 struct serial_struct *new_info)
3442{
3443 struct serial_struct new_serial;
3444 struct e100_serial old_info;
3445 int retval = 0;
3446
3447 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3448 return -EFAULT;
3449
3450 old_info = *info;
3451
3452 if (!capable(CAP_SYS_ADMIN)) {
3453 if ((new_serial.type != info->type) ||
3454 (new_serial.close_delay != info->close_delay) ||
3455 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3456 (info->flags & ~ASYNC_USR_MASK)))
3457 return -EPERM;
3458 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3459 (new_serial.flags & ASYNC_USR_MASK));
3460 goto check_and_exit;
3461 }
3462
3463 if (info->count > 1)
3464 return -EBUSY;
3465
3466 /*
3467 * OK, past this point, all the error checking has been done.
3468 * At this point, we start making changes.....
3469 */
3470
3471 info->baud_base = new_serial.baud_base;
3472 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3473 (new_serial.flags & ASYNC_FLAGS));
3474 info->custom_divisor = new_serial.custom_divisor;
3475 info->type = new_serial.type;
3476 info->close_delay = new_serial.close_delay;
3477 info->closing_wait = new_serial.closing_wait;
3478 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3479
3480 check_and_exit:
3481 if (info->flags & ASYNC_INITIALIZED) {
3482 change_speed(info);
3483 } else
3484 retval = startup(info);
3485 return retval;
3486}
3487
3488/*
3489 * get_lsr_info - get line status register info
3490 *
3491 * Purpose: Let user call ioctl() to get info when the UART physically
3492 * is emptied. On bus types like RS485, the transmitter must
3493 * release the bus after transmitting. This must be done when
3494 * the transmit shift register is empty, not be done when the
3495 * transmit holding register is empty. This functionality
3496 * allows an RS485 driver to be written in user space.
3497 */
3498static int
3499get_lsr_info(struct e100_serial * info, unsigned int *value)
3500{
3501 unsigned int result = TIOCSER_TEMT;
3502#ifndef CONFIG_SVINTO_SIM
3503 unsigned long curr_time = jiffies;
3504 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3505 unsigned long elapsed_usec =
3506 (curr_time - info->last_tx_active) * 1000000/HZ +
3507 curr_time_usec - info->last_tx_active_usec;
3508
3509 if (info->xmit.head != info->xmit.tail ||
3510 elapsed_usec < 2*info->char_time_usec) {
3511 result = 0;
3512 }
3513#endif
3514
3515 if (copy_to_user(value, &result, sizeof(int)))
3516 return -EFAULT;
3517 return 0;
3518}
3519
3520#ifdef SERIAL_DEBUG_IO
3521struct state_str
3522{
3523 int state;
3524 const char *str;
3525};
3526
3527const struct state_str control_state_str[] = {
3528 {TIOCM_DTR, "DTR" },
3529 {TIOCM_RTS, "RTS"},
3530 {TIOCM_ST, "ST?" },
3531 {TIOCM_SR, "SR?" },
3532 {TIOCM_CTS, "CTS" },
3533 {TIOCM_CD, "CD" },
3534 {TIOCM_RI, "RI" },
3535 {TIOCM_DSR, "DSR" },
3536 {0, NULL }
3537};
3538
3539char *get_control_state_str(int MLines, char *s)
3540{
3541 int i = 0;
3542
3543 s[0]='\0';
3544 while (control_state_str[i].str != NULL) {
3545 if (MLines & control_state_str[i].state) {
3546 if (s[0] != '\0') {
3547 strcat(s, ", ");
3548 }
3549 strcat(s, control_state_str[i].str);
3550 }
3551 i++;
3552 }
3553 return s;
3554}
3555#endif
3556
77accbf5
JN		 3557static void
3558rs_break(struct tty_struct *tty, int break_state)
3559{
3560 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3561 unsigned long flags;
3562
3563 if (!info->port)
3564 return;
3565
3566 local_irq_save(flags);
3567 if (break_state == -1) {
3568 /* Go to manual mode and set the txd pin to 0 */
3569 /* Clear bit 7 (txd) and 6 (tr_enable) */
3570 info->tx_ctrl &= 0x3F;
3571 } else {
3572 /* Set bit 7 (txd) and 6 (tr_enable) */
3573 info->tx_ctrl |= (0x80 | 0x40);
3574 }
3575 info->port[REG_TR_CTRL] = info->tx_ctrl;
3576 local_irq_restore(flags);
3577}
3578
1da177e4 3579static int
77accbf5
JN		 3580rs_tiocmset(struct tty_struct *tty, struct file *file,
3581 unsigned int set, unsigned int clear)
1da177e4 3582{
77accbf5 3583 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1da177e4 3584
77accbf5
JN		 3585 if (clear & TIOCM_RTS)
3586 e100_rts(info, 0);
3587 if (clear & TIOCM_DTR)
3588 e100_dtr(info, 0);
3589 /* Handle FEMALE behaviour */
3590 if (clear & TIOCM_RI)
3591 e100_ri_out(info, 0);
3592 if (clear & TIOCM_CD)
3593 e100_cd_out(info, 0);
3594
3595 if (set & TIOCM_RTS)
3596 e100_rts(info, 1);
3597 if (set & TIOCM_DTR)
3598 e100_dtr(info, 1);
3599 /* Handle FEMALE behaviour */
3600 if (set & TIOCM_RI)
3601 e100_ri_out(info, 1);
3602 if (set & TIOCM_CD)
3603 e100_cd_out(info, 1);
3604 return 0;
3605}
3606
3607static int
3608rs_tiocmget(struct tty_struct *tty, struct file *file)
3609{
3610 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3611 unsigned int result;
1da177e4
LT		 3612
3613 result =
3614 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3615 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3616 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3617 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3618 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3619 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3620
3621#ifdef SERIAL_DEBUG_IO
77accbf5
JN		 3622 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3623 info->line, result, result);
1da177e4
LT		 3624 {
3625 char s[100];
3626
3627 get_control_state_str(result, s);
77accbf5 3628 printk(KERN_DEBUG "state: %s\n", s);
1da177e4
LT		 3629 }
3630#endif
77accbf5 3631 return result;
1da177e4 3632
1da177e4
LT		 3633}
3634
3635
1da177e4
LT		 3636static int
3637rs_ioctl(struct tty_struct *tty, struct file * file,
3638 unsigned int cmd, unsigned long arg)
3639{
3640 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3641
3642 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3643 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3644 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3645 if (tty->flags & (1 << TTY_IO_ERROR))
3646 return -EIO;
3647 }
3648
3649 switch (cmd) {
77accbf5
JN		 3650 case TIOCGSERIAL:
3651 return get_serial_info(info,
3652 (struct serial_struct *) arg);
3653 case TIOCSSERIAL:
3654 return set_serial_info(info,
3655 (struct serial_struct *) arg);
3656 case TIOCSERGETLSR: /* Get line status register */
3657 return get_lsr_info(info, (unsigned int *) arg);
3658
3659 case TIOCSERGSTRUCT:
3660 if (copy_to_user((struct e100_serial *) arg,
3661 info, sizeof(struct e100_serial)))
3662 return -EFAULT;
3663 return 0;
1da177e4
LT		 3664
3665#if defined(CONFIG_ETRAX_RS485)
77accbf5
JN		 3666 case TIOCSERSETRS485:
3667 {
3668 struct rs485_control rs485ctrl;
3669 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3670 sizeof(rs485ctrl)))
3671 return -EFAULT;
1da177e4 3672
77accbf5
JN		 3673 return e100_enable_rs485(tty, &rs485ctrl);
3674 }
1da177e4 3675
77accbf5
JN		 3676 case TIOCSERWRRS485:
3677 {
3678 struct rs485_write rs485wr;
3679 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3680 sizeof(rs485wr)))
3681 return -EFAULT;
1da177e4 3682
77accbf5
JN		 3683 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3684 }
1da177e4
LT		 3685#endif
3686
77accbf5
JN		 3687 default:
3688 return -ENOIOCTLCMD;
1da177e4
LT		 3689 }
3690 return 0;
3691}
3692
3693static void
606d099c 3694rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 3695{
3696 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3697
3698 if (tty->termios->c_cflag == old_termios->c_cflag &&
3699 tty->termios->c_iflag == old_termios->c_iflag)
3700 return;
3701
3702 change_speed(info);
3703
3704 /* Handle turning off CRTSCTS */
3705 if ((old_termios->c_cflag & CRTSCTS) &&
3706 !(tty->termios->c_cflag & CRTSCTS)) {
3707 tty->hw_stopped = 0;
3708 rs_start(tty);
3709 }
3710
3711}
3712
1da177e4
LT		 3713/*
3714 * ------------------------------------------------------------
3715 * rs_close()
3716 *
3717 * This routine is called when the serial port gets closed. First, we
3718 * wait for the last remaining data to be sent. Then, we unlink its
3719 * S structure from the interrupt chain if necessary, and we free
3720 * that IRQ if nothing is left in the chain.
3721 * ------------------------------------------------------------
3722 */
3723static void
3724rs_close(struct tty_struct *tty, struct file * filp)
3725{
3726 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3727 unsigned long flags;
3728
3729 if (!info)
3730 return;
3731
3732 /* interrupts are disabled for this entire function */
3733
77accbf5 3734 local_irq_save(flags);
1da177e4
LT		 3735
3736 if (tty_hung_up_p(filp)) {
77accbf5 3737 local_irq_restore(flags);
1da177e4
LT		 3738 return;
3739 }
3740
3741#ifdef SERIAL_DEBUG_OPEN
3742 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3743 info->line, info->count);
3744#endif
3745 if ((tty->count == 1) && (info->count != 1)) {
3746 /*
3747 * Uh, oh. tty->count is 1, which means that the tty
3748 * structure will be freed. Info->count should always
3749 * be one in these conditions. If it's greater than
3750 * one, we've got real problems, since it means the
3751 * serial port won't be shutdown.
3752 */
3753 printk(KERN_CRIT
3754 "rs_close: bad serial port count; tty->count is 1, "
3755 "info->count is %d\n", info->count);
3756 info->count = 1;
3757 }
3758 if (--info->count < 0) {
3759 printk(KERN_CRIT "rs_close: bad serial port count for ttyS%d: %d\n",
3760 info->line, info->count);
3761 info->count = 0;
3762 }
3763 if (info->count) {
77accbf5 3764 local_irq_restore(flags);
1da177e4
LT		 3765 return;
3766 }
3767 info->flags |= ASYNC_CLOSING;
3768 /*
3769 * Save the termios structure, since this port may have
3770 * separate termios for callout and dialin.
3771 */
3772 if (info->flags & ASYNC_NORMAL_ACTIVE)
3773 info->normal_termios = *tty->termios;
3774 /*
3775 * Now we wait for the transmit buffer to clear; and we notify
3776 * the line discipline to only process XON/XOFF characters.
3777 */
3778 tty->closing = 1;
3779 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3780 tty_wait_until_sent(tty, info->closing_wait);
3781 /*
3782 * At this point we stop accepting input. To do this, we
3783 * disable the serial receiver and the DMA receive interrupt.
3784 */
3785#ifdef SERIAL_HANDLE_EARLY_ERRORS
3786 e100_disable_serial_data_irq(info);
3787#endif
3788
3789#ifndef CONFIG_SVINTO_SIM
3790 e100_disable_rx(info);
3791 e100_disable_rx_irq(info);
3792
3793 if (info->flags & ASYNC_INITIALIZED) {
3794 /*
3795 * Before we drop DTR, make sure the UART transmitter
3796 * has completely drained; this is especially
3797 * important as we have a transmit FIFO!
3798 */
3799 rs_wait_until_sent(tty, HZ);
3800 }
3801#endif
3802
3803 shutdown(info);
3804 if (tty->driver->flush_buffer)
3805 tty->driver->flush_buffer(tty);
3806 if (tty->ldisc.flush_buffer)
3807 tty->ldisc.flush_buffer(tty);
3808 tty->closing = 0;
3809 info->event = 0;
3810 info->tty = 0;
3811 if (info->blocked_open) {
3c76bc5b
NA		 3812 if (info->close_delay)
3813 schedule_timeout_interruptible(info->close_delay);
1da177e4
LT		 3814 wake_up_interruptible(&info->open_wait);
3815 }
3816 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3817 wake_up_interruptible(&info->close_wait);
77accbf5 3818 local_irq_restore(flags);
1da177e4
LT		 3819
3820 /* port closed */
3821
3822#if defined(CONFIG_ETRAX_RS485)
3823 if (info->rs485.enabled) {
3824 info->rs485.enabled = 0;
3825#if defined(CONFIG_ETRAX_RS485_ON_PA)
3826 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3827#endif
3828#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3829 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3830 rs485_port_g_bit, 0);
3831#endif
3832#if defined(CONFIG_ETRAX_RS485_LTC1387)
3833 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3834 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3835 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3836 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3837#endif
3838 }
3839#endif
77accbf5
JN		 3840
3841 /*
3842 * Release any allocated DMA irq's.
3843 */
3844 if (info->dma_in_enabled) {
3845 free_irq(info->dma_in_irq_nbr, info);
3846 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3847 info->uses_dma_in = 0;
3848#ifdef SERIAL_DEBUG_OPEN
3849 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3850 info->dma_in_irq_description);
3851#endif
3852 }
3853 if (info->dma_out_enabled) {
3854 free_irq(info->dma_out_irq_nbr, info);
3855 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3856 info->uses_dma_out = 0;
3857#ifdef SERIAL_DEBUG_OPEN
3858 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3859 info->dma_out_irq_description);
3860#endif
3861 }
1da177e4
LT		 3862}
3863
3864/*
3865 * rs_wait_until_sent() --- wait until the transmitter is empty
3866 */
3867static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3868{
3869 unsigned long orig_jiffies;
3870 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3871 unsigned long curr_time = jiffies;
3872 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3873 long elapsed_usec =
3874 (curr_time - info->last_tx_active) * (1000000/HZ) +
3875 curr_time_usec - info->last_tx_active_usec;
3876
3877 /*
3878 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3879 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3880 */
3881 orig_jiffies = jiffies;
3882 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3883 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3884 (elapsed_usec < 2*info->char_time_usec)) {
3c76bc5b 3885 schedule_timeout_interruptible(1);
1da177e4
LT		 3886 if (signal_pending(current))
3887 break;
3888 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3889 break;
3890 curr_time = jiffies;
3891 curr_time_usec = GET_JIFFIES_USEC();
3892 elapsed_usec =
3893 (curr_time - info->last_tx_active) * (1000000/HZ) +
3894 curr_time_usec - info->last_tx_active_usec;
3895 }
3896 set_current_state(TASK_RUNNING);
3897}
3898
3899/*
3900 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3901 */
3902void
3903rs_hangup(struct tty_struct *tty)
3904{
3905 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3906
3907 rs_flush_buffer(tty);
3908 shutdown(info);
3909 info->event = 0;
3910 info->count = 0;
3911 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3912 info->tty = 0;
3913 wake_up_interruptible(&info->open_wait);
3914}
3915
3916/*
3917 * ------------------------------------------------------------
3918 * rs_open() and friends
3919 * ------------------------------------------------------------
3920 */
3921static int
3922block_til_ready(struct tty_struct *tty, struct file * filp,
3923 struct e100_serial *info)
3924{
3925 DECLARE_WAITQUEUE(wait, current);
3926 unsigned long flags;
3927 int retval;
3928 int do_clocal = 0, extra_count = 0;
3929
3930 /*
3931 * If the device is in the middle of being closed, then block
3932 * until it's done, and then try again.
3933 */
3934 if (tty_hung_up_p(filp) ||
3935 (info->flags & ASYNC_CLOSING)) {
77accbf5
JN		 3936 wait_event_interruptible(info->close_wait,
3937 !(info->flags & ASYNC_CLOSING));
1da177e4
LT		 3938#ifdef SERIAL_DO_RESTART
3939 if (info->flags & ASYNC_HUP_NOTIFY)
3940 return -EAGAIN;
3941 else
3942 return -ERESTARTSYS;
3943#else
3944 return -EAGAIN;
3945#endif
3946 }
3947
3948 /*
3949 * If non-blocking mode is set, or the port is not enabled,
3950 * then make the check up front and then exit.
3951 */
3952 if ((filp->f_flags & O_NONBLOCK) ||
3953 (tty->flags & (1 << TTY_IO_ERROR))) {
3954 info->flags |= ASYNC_NORMAL_ACTIVE;
3955 return 0;
3956 }
3957
3958 if (tty->termios->c_cflag & CLOCAL) {
3959 do_clocal = 1;
3960 }
3961
3962 /*
3963 * Block waiting for the carrier detect and the line to become
3964 * free (i.e., not in use by the callout). While we are in
3965 * this loop, info->count is dropped by one, so that
3966 * rs_close() knows when to free things. We restore it upon
3967 * exit, either normal or abnormal.
3968 */
3969 retval = 0;
3970 add_wait_queue(&info->open_wait, &wait);
3971#ifdef SERIAL_DEBUG_OPEN
3972 printk("block_til_ready before block: ttyS%d, count = %d\n",
3973 info->line, info->count);
3974#endif
77accbf5 3975 local_irq_save(flags);
1da177e4
LT		 3976 if (!tty_hung_up_p(filp)) {
3977 extra_count++;
3978 info->count--;
3979 }
77accbf5 3980 local_irq_restore(flags);
1da177e4
LT		 3981 info->blocked_open++;
3982 while (1) {
77accbf5 3983 local_irq_save(flags);
1da177e4
LT		 3984 /* assert RTS and DTR */
3985 e100_rts(info, 1);
3986 e100_dtr(info, 1);
77accbf5 3987 local_irq_restore(flags);
1da177e4
LT		 3988 set_current_state(TASK_INTERRUPTIBLE);
3989 if (tty_hung_up_p(filp) ||
3990 !(info->flags & ASYNC_INITIALIZED)) {
3991#ifdef SERIAL_DO_RESTART
3992 if (info->flags & ASYNC_HUP_NOTIFY)
3993 retval = -EAGAIN;
3994 else
3995 retval = -ERESTARTSYS;
3996#else
3997 retval = -EAGAIN;
3998#endif
3999 break;
4000 }
4001 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4002 /* && (do_clocal || DCD_IS_ASSERTED) */
4003 break;
4004 if (signal_pending(current)) {
4005 retval = -ERESTARTSYS;
4006 break;
4007 }
4008#ifdef SERIAL_DEBUG_OPEN
4009 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4010 info->line, info->count);
4011#endif
4012 schedule();
4013 }
4014 set_current_state(TASK_RUNNING);
4015 remove_wait_queue(&info->open_wait, &wait);
4016 if (extra_count)
4017 info->count++;
4018 info->blocked_open--;
4019#ifdef SERIAL_DEBUG_OPEN
4020 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4021 info->line, info->count);
4022#endif
4023 if (retval)
4024 return retval;
4025 info->flags |= ASYNC_NORMAL_ACTIVE;
4026 return 0;
4027}
4028
77accbf5
JN		 4029static void
4030deinit_port(struct e100_serial *info)
4031{
4032 if (info->dma_out_enabled) {
4033 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4034 free_irq(info->dma_out_irq_nbr, info);
4035 }
4036 if (info->dma_in_enabled) {
4037 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4038 free_irq(info->dma_in_irq_nbr, info);
4039 }
4040}
4041
1da177e4
LT		 4042/*
4043 * This routine is called whenever a serial port is opened.
4044 * It performs the serial-specific initialization for the tty structure.
4045 */
4046static int
4047rs_open(struct tty_struct *tty, struct file * filp)
4048{
4049 struct e100_serial *info;
4050 int retval, line;
4051 unsigned long page;
77accbf5 4052 int allocated_resources = 0;
1da177e4
LT		 4053
4054 /* find which port we want to open */
1da177e4
LT		 4055 line = tty->index;
4056
4057 if (line < 0 || line >= NR_PORTS)
4058 return -ENODEV;
4059
4060 /* find the corresponding e100_serial struct in the table */
4061 info = rs_table + line;
4062
4063 /* don't allow the opening of ports that are not enabled in the HW config */
4064 if (!info->enabled)
4065 return -ENODEV;
4066
4067#ifdef SERIAL_DEBUG_OPEN
4068 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4069 info->count);
4070#endif
4071
4072 info->count++;
4073 tty->driver_data = info;
4074 info->tty = tty;
4075
4076 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
4077
4078 if (!tmp_buf) {
4079 page = get_zeroed_page(GFP_KERNEL);
4080 if (!page) {
4081 return -ENOMEM;
4082 }
4083 if (tmp_buf)
4084 free_page(page);
4085 else
4086 tmp_buf = (unsigned char *) page;
4087 }
4088
4089 /*
4090 * If the port is in the middle of closing, bail out now
4091 */
4092 if (tty_hung_up_p(filp) ||
4093 (info->flags & ASYNC_CLOSING)) {
77accbf5
JN		 4094 wait_event_interruptible(info->close_wait,
4095 !(info->flags & ASYNC_CLOSING));
1da177e4
LT		 4096#ifdef SERIAL_DO_RESTART
4097 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4098 -EAGAIN : -ERESTARTSYS);
4099#else
4100 return -EAGAIN;
4101#endif
4102 }
4103
77accbf5
JN		 4104 /*
4105 * If DMA is enabled try to allocate the irq's.
4106 */
4107 if (info->count == 1) {
4108 allocated_resources = 1;
4109 if (info->dma_in_enabled) {
4110 if (request_irq(info->dma_in_irq_nbr,
4111 rec_interrupt,
4112 info->dma_in_irq_flags,
4113 info->dma_in_irq_description,
4114 info)) {
4115 printk(KERN_WARNING "DMA irq '%s' busy; "
4116 "falling back to non-DMA mode\n",
4117 info->dma_in_irq_description);
4118 /* Make sure we never try to use DMA in */
4119 /* for the port again. */
4120 info->dma_in_enabled = 0;
4121 } else if (cris_request_dma(info->dma_in_nbr,
4122 info->dma_in_irq_description,
4123 DMA_VERBOSE_ON_ERROR,
4124 info->dma_owner)) {
4125 free_irq(info->dma_in_irq_nbr, info);
4126 printk(KERN_WARNING "DMA '%s' busy; "
4127 "falling back to non-DMA mode\n",
4128 info->dma_in_irq_description);
4129 /* Make sure we never try to use DMA in */
4130 /* for the port again. */
4131 info->dma_in_enabled = 0;
4132 }
4133#ifdef SERIAL_DEBUG_OPEN
4134 else
4135 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4136 info->dma_in_irq_description);
4137#endif
4138 }
4139 if (info->dma_out_enabled) {
4140 if (request_irq(info->dma_out_irq_nbr,
4141 tr_interrupt,
4142 info->dma_out_irq_flags,
4143 info->dma_out_irq_description,
4144 info)) {
4145 printk(KERN_WARNING "DMA irq '%s' busy; "
4146 "falling back to non-DMA mode\n",
4147 info->dma_out_irq_description);
4148 /* Make sure we never try to use DMA out */
4149 /* for the port again. */
4150 info->dma_out_enabled = 0;
4151 } else if (cris_request_dma(info->dma_out_nbr,
4152 info->dma_out_irq_description,
4153 DMA_VERBOSE_ON_ERROR,
4154 info->dma_owner)) {
4155 free_irq(info->dma_out_irq_nbr, info);
4156 printk(KERN_WARNING "DMA '%s' busy; "
4157 "falling back to non-DMA mode\n",
4158 info->dma_out_irq_description);
4159 /* Make sure we never try to use DMA out */
4160 /* for the port again. */
4161 info->dma_out_enabled = 0;
4162 }
4163#ifdef SERIAL_DEBUG_OPEN
4164 else
4165 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4166 info->dma_out_irq_description);
4167#endif
4168 }
4169 }
4170
1da177e4
LT		 4171 /*
4172 * Start up the serial port
4173 */
4174
4175 retval = startup(info);
77accbf5
JN		 4176 if (retval) {
4177 if (allocated_resources)
4178 deinit_port(info);
4179
4180 /* FIXME Decrease count info->count here too? */
1da177e4 4181 return retval;
77accbf5
JN		 4182 }
4183
1da177e4
LT		 4184
4185 retval = block_til_ready(tty, filp, info);
4186 if (retval) {
4187#ifdef SERIAL_DEBUG_OPEN
4188 printk("rs_open returning after block_til_ready with %d\n",
4189 retval);
4190#endif
77accbf5
JN		 4191 if (allocated_resources)
4192 deinit_port(info);
4193
1da177e4
LT		 4194 return retval;
4195 }
4196
4197 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4198 *tty->termios = info->normal_termios;
4199 change_speed(info);
4200 }
4201
4202#ifdef SERIAL_DEBUG_OPEN
4203 printk("rs_open ttyS%d successful...\n", info->line);
4204#endif
4205 DLOG_INT_TRIG( log_int_pos = 0);
4206
4207 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4208 info->icount.rx = 0;
4209 } );
4210
4211 return 0;
4212}
4213
4214/*
4215 * /proc fs routines....
4216 */
4217
41c28ff1 4218static int line_info(char *buf, struct e100_serial *info)
1da177e4
LT		 4219{
4220 char stat_buf[30];
4221 int ret;
4222 unsigned long tmp;
4223
4224 ret = sprintf(buf, "%d: uart:E100 port:%lX irq:%d",
4225 info->line, (unsigned long)info->port, info->irq);
4226
4227 if (!info->port || (info->type == PORT_UNKNOWN)) {
4228 ret += sprintf(buf+ret, "\n");
4229 return ret;
4230 }
4231
4232 stat_buf[0] = 0;
4233 stat_buf[1] = 0;
4234 if (!E100_RTS_GET(info))
4235 strcat(stat_buf, "|RTS");
4236 if (!E100_CTS_GET(info))
4237 strcat(stat_buf, "|CTS");
4238 if (!E100_DTR_GET(info))
4239 strcat(stat_buf, "|DTR");
4240 if (!E100_DSR_GET(info))
4241 strcat(stat_buf, "|DSR");
4242 if (!E100_CD_GET(info))
4243 strcat(stat_buf, "|CD");
4244 if (!E100_RI_GET(info))
4245 strcat(stat_buf, "|RI");
4246
4247 ret += sprintf(buf+ret, " baud:%d", info->baud);
4248
4249 ret += sprintf(buf+ret, " tx:%lu rx:%lu",
4250 (unsigned long)info->icount.tx,
4251 (unsigned long)info->icount.rx);
4252 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4253 if (tmp) {
4254 ret += sprintf(buf+ret, " tx_pend:%lu/%lu",
4255 (unsigned long)tmp,
4256 (unsigned long)SERIAL_XMIT_SIZE);
4257 }
4258
4259 ret += sprintf(buf+ret, " rx_pend:%lu/%lu",
4260 (unsigned long)info->recv_cnt,
4261 (unsigned long)info->max_recv_cnt);
4262
4263#if 1
4264 if (info->tty) {
4265
4266 if (info->tty->stopped)
4267 ret += sprintf(buf+ret, " stopped:%i",
4268 (int)info->tty->stopped);
4269 if (info->tty->hw_stopped)
4270 ret += sprintf(buf+ret, " hw_stopped:%i",
4271 (int)info->tty->hw_stopped);
4272 }
4273
4274 {
4275 unsigned char rstat = info->port[REG_STATUS];
4276 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) )
4277 ret += sprintf(buf+ret, " xoff_detect:1");
4278 }
4279
4280#endif
4281
4282
4283
4284
4285 if (info->icount.frame)
4286 ret += sprintf(buf+ret, " fe:%lu",
4287 (unsigned long)info->icount.frame);
4288
4289 if (info->icount.parity)
4290 ret += sprintf(buf+ret, " pe:%lu",
4291 (unsigned long)info->icount.parity);
4292
4293 if (info->icount.brk)
4294 ret += sprintf(buf+ret, " brk:%lu",
4295 (unsigned long)info->icount.brk);
4296
4297 if (info->icount.overrun)
4298 ret += sprintf(buf+ret, " oe:%lu",
4299 (unsigned long)info->icount.overrun);
4300
4301 /*
4302 * Last thing is the RS-232 status lines
4303 */
4304 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
4305 return ret;
4306}
4307
4308int rs_read_proc(char *page, char **start, off_t off, int count,
4309 int *eof, void *data)
4310{
4311 int i, len = 0, l;
4312 off_t begin = 0;
4313
4314 len += sprintf(page, "serinfo:1.0 driver:%s\n",
4315 serial_version);
4316 for (i = 0; i < NR_PORTS && len < 4000; i++) {
4317 if (!rs_table[i].enabled)
4318 continue;
4319 l = line_info(page + len, &rs_table[i]);
4320 len += l;
4321 if (len+begin > off+count)
4322 goto done;
4323 if (len+begin < off) {
4324 begin += len;
4325 len = 0;
4326 }
4327 }
4328#ifdef DEBUG_LOG_INCLUDED
4329 for (i = 0; i < debug_log_pos; i++) {
4330 len += sprintf(page + len, "%-4i %lu.%lu ", i, debug_log[i].time, timer_data_to_ns(debug_log[i].timer_data));
4331 len += sprintf(page + len, debug_log[i].string, debug_log[i].value);
4332 if (len+begin > off+count)
4333 goto done;
4334 if (len+begin < off) {
4335 begin += len;
4336 len = 0;
4337 }
4338 }
4339 len += sprintf(page + len, "debug_log %i/%i %li bytes\n",
4340 i, DEBUG_LOG_SIZE, begin+len);
4341 debug_log_pos = 0;
4342#endif
4343
4344 *eof = 1;
4345done:
4346 if (off >= len+begin)
4347 return 0;
4348 *start = page + (off-begin);
4349 return ((count < begin+len-off) ? count : begin+len-off);
4350}
4351
4352/* Finally, routines used to initialize the serial driver. */
4353
4354static void
4355show_serial_version(void)
4356{
4357 printk(KERN_INFO
4358 "ETRAX 100LX serial-driver %s, (c) 2000-2004 Axis Communications AB\r\n",
4359 &serial_version[11]); /* "$Revision: x.yy" */
4360}
4361
4362/* rs_init inits the driver at boot (using the module_init chain) */
4363
b68e31d0 4364static const struct tty_operations rs_ops = {
1da177e4
LT		 4365 .open = rs_open,
4366 .close = rs_close,
4367 .write = rs_write,
4368 .flush_chars = rs_flush_chars,
4369 .write_room = rs_write_room,
4370 .chars_in_buffer = rs_chars_in_buffer,
4371 .flush_buffer = rs_flush_buffer,
4372 .ioctl = rs_ioctl,
4373 .throttle = rs_throttle,
4374 .unthrottle = rs_unthrottle,
4375 .set_termios = rs_set_termios,
4376 .stop = rs_stop,
4377 .start = rs_start,
4378 .hangup = rs_hangup,
4379 .break_ctl = rs_break,
4380 .send_xchar = rs_send_xchar,
4381 .wait_until_sent = rs_wait_until_sent,
4382 .read_proc = rs_read_proc,
77accbf5
JN		 4383 .tiocmget = rs_tiocmget,
4384 .tiocmset = rs_tiocmset
1da177e4
LT		 4385};
4386
4387static int __init
4388rs_init(void)
4389{
4390 int i;
4391 struct e100_serial *info;
4392 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4393
4394 if (!driver)
4395 return -ENOMEM;
4396
4397 show_serial_version();
4398
4399 /* Setup the timed flush handler system */
4400
4401#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
77accbf5
JN		 4402 setup_timer(&flush_timer, timed_flush_handler, 0);
4403 mod_timer(&flush_timer, jiffies + 5);
4404#endif
4405
4406#if defined(CONFIG_ETRAX_RS485)
4407#if defined(CONFIG_ETRAX_RS485_ON_PA)
4408 if (cris_io_interface_allocate_pins(if_ser0, 'a', rs485_pa_bit,
4409 rs485_pa_bit)) {
4410 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4411 "RS485 pin\n");
4412 return -EBUSY;
4413 }
4414#endif
4415#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4416 if (cris_io_interface_allocate_pins(if_ser0, 'g', rs485_pa_bit,
4417 rs485_port_g_bit)) {
4418 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4419 "RS485 pin\n");
4420 return -EBUSY;
4421 }
4422#endif
1da177e4
LT		 4423#endif
4424
4425 /* Initialize the tty_driver structure */
4426
4427 driver->driver_name = "serial";
4428 driver->name = "ttyS";
4429 driver->major = TTY_MAJOR;
4430 driver->minor_start = 64;
4431 driver->type = TTY_DRIVER_TYPE_SERIAL;
4432 driver->subtype = SERIAL_TYPE_NORMAL;
4433 driver->init_termios = tty_std_termios;
4434 driver->init_termios.c_cflag =
4435 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
606d099c
AC		 4436 driver->init_termios.c_ispeed = 115200;
4437 driver->init_termios.c_ospeed = 115200;
331b8319 4438 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 4439 driver->termios = serial_termios;
4440 driver->termios_locked = serial_termios_locked;
4441
4442 tty_set_operations(driver, &rs_ops);
4443 serial_driver = driver;
4444 if (tty_register_driver(driver))
4445 panic("Couldn't register serial driver\n");
4446 /* do some initializing for the separate ports */
4447
4448 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
77accbf5
JN		 4449 if (info->enabled) {
4450 if (cris_request_io_interface(info->io_if,
4451 info->io_if_description)) {
4452 printk(KERN_CRIT "ETRAX100LX async serial: "
4453 "Could not allocate IO pins for "
4454 "%s, port %d\n",
4455 info->io_if_description, i);
4456 info->enabled = 0;
4457 }
4458 }
1da177e4
LT		 4459 info->uses_dma_in = 0;
4460 info->uses_dma_out = 0;
4461 info->line = i;
4462 info->tty = 0;
4463 info->type = PORT_ETRAX;
4464 info->tr_running = 0;
4465 info->forced_eop = 0;
4466 info->baud_base = DEF_BAUD_BASE;
4467 info->custom_divisor = 0;
4468 info->flags = 0;
4469 info->close_delay = 5*HZ/10;
4470 info->closing_wait = 30*HZ;
4471 info->x_char = 0;
4472 info->event = 0;
4473 info->count = 0;
4474 info->blocked_open = 0;
4475 info->normal_termios = driver->init_termios;
4476 init_waitqueue_head(&info->open_wait);
4477 init_waitqueue_head(&info->close_wait);
4478 info->xmit.buf = NULL;
4479 info->xmit.tail = info->xmit.head = 0;
4480 info->first_recv_buffer = info->last_recv_buffer = NULL;
4481 info->recv_cnt = info->max_recv_cnt = 0;
4482 info->last_tx_active_usec = 0;
4483 info->last_tx_active = 0;
4484
4485#if defined(CONFIG_ETRAX_RS485)
4486 /* Set sane defaults */
4487 info->rs485.rts_on_send = 0;
4488 info->rs485.rts_after_sent = 1;
4489 info->rs485.delay_rts_before_send = 0;
4490 info->rs485.enabled = 0;
4491#endif
77accbf5 4492 INIT_WORK(&info->work, do_softint);
1da177e4
LT		 4493
4494 if (info->enabled) {
4495 printk(KERN_INFO "%s%d at 0x%x is a builtin UART with DMA\n",
4496 serial_driver->name, info->line, (unsigned int)info->port);
4497 }
4498 }
4499#ifdef CONFIG_ETRAX_FAST_TIMER
4500#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4501 memset(fast_timers, 0, sizeof(fast_timers));
4502#endif
4503#ifdef CONFIG_ETRAX_RS485
4504 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4505#endif
4506 fast_timer_init();
4507#endif
4508
4509#ifndef CONFIG_SVINTO_SIM
77accbf5 4510#ifndef CONFIG_ETRAX_KGDB
1da177e4
LT		 4511 /* Not needed in simulator. May only complicate stuff. */
4512 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4513
77accbf5
JN		 4514 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4515 IRQF_SHARED | IRQF_DISABLED, "serial ", driver))
4516 panic("%s: Failed to request irq8", __FUNCTION__);
1da177e4 4517
1da177e4
LT		 4518#endif
4519#endif /* CONFIG_SVINTO_SIM */
77accbf5 4520
1da177e4
LT		 4521 return 0;
4522}
4523
4524/* this makes sure that rs_init is called during kernel boot */
4525
4526module_init(rs_init);
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