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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/imx.c | |
3 | * | |
4 | * Driver for Motorola IMX serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Author: Sascha Hauer <sascha@saschahauer.de> | |
9 | * Copyright (C) 2004 Pengutronix | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * [29-Mar-2005] Mike Lee | |
26 | * Added hardware handshake | |
27 | */ | |
1da177e4 LT |
28 | |
29 | #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
30 | #define SUPPORT_SYSRQ | |
31 | #endif | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <linux/ioport.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/console.h> | |
37 | #include <linux/sysrq.h> | |
d052d1be | 38 | #include <linux/platform_device.h> |
1da177e4 LT |
39 | #include <linux/tty.h> |
40 | #include <linux/tty_flip.h> | |
41 | #include <linux/serial_core.h> | |
42 | #include <linux/serial.h> | |
43 | ||
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
46 | #include <asm/hardware.h> | |
5b802344 | 47 | #include <asm/arch/imx-uart.h> |
1da177e4 LT |
48 | |
49 | /* We've been assigned a range on the "Low-density serial ports" major */ | |
50 | #define SERIAL_IMX_MAJOR 204 | |
51 | #define MINOR_START 41 | |
52 | ||
53 | #define NR_PORTS 2 | |
54 | ||
55 | #define IMX_ISR_PASS_LIMIT 256 | |
56 | ||
57 | /* | |
58 | * This is the size of our serial port register set. | |
59 | */ | |
60 | #define UART_PORT_SIZE 0x100 | |
61 | ||
62 | /* | |
63 | * This determines how often we check the modem status signals | |
64 | * for any change. They generally aren't connected to an IRQ | |
65 | * so we have to poll them. We also check immediately before | |
66 | * filling the TX fifo incase CTS has been dropped. | |
67 | */ | |
68 | #define MCTRL_TIMEOUT (250*HZ/1000) | |
69 | ||
70 | #define DRIVER_NAME "IMX-uart" | |
71 | ||
72 | struct imx_port { | |
73 | struct uart_port port; | |
74 | struct timer_list timer; | |
75 | unsigned int old_status; | |
5b802344 SH |
76 | int txirq,rxirq,rtsirq; |
77 | int have_rtscts:1; | |
1da177e4 LT |
78 | }; |
79 | ||
80 | /* | |
81 | * Handle any change of modem status signal since we were last called. | |
82 | */ | |
83 | static void imx_mctrl_check(struct imx_port *sport) | |
84 | { | |
85 | unsigned int status, changed; | |
86 | ||
87 | status = sport->port.ops->get_mctrl(&sport->port); | |
88 | changed = status ^ sport->old_status; | |
89 | ||
90 | if (changed == 0) | |
91 | return; | |
92 | ||
93 | sport->old_status = status; | |
94 | ||
95 | if (changed & TIOCM_RI) | |
96 | sport->port.icount.rng++; | |
97 | if (changed & TIOCM_DSR) | |
98 | sport->port.icount.dsr++; | |
99 | if (changed & TIOCM_CAR) | |
100 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | |
101 | if (changed & TIOCM_CTS) | |
102 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | |
103 | ||
104 | wake_up_interruptible(&sport->port.info->delta_msr_wait); | |
105 | } | |
106 | ||
107 | /* | |
108 | * This is our per-port timeout handler, for checking the | |
109 | * modem status signals. | |
110 | */ | |
111 | static void imx_timeout(unsigned long data) | |
112 | { | |
113 | struct imx_port *sport = (struct imx_port *)data; | |
114 | unsigned long flags; | |
115 | ||
116 | if (sport->port.info) { | |
117 | spin_lock_irqsave(&sport->port.lock, flags); | |
118 | imx_mctrl_check(sport); | |
119 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
120 | ||
121 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | |
122 | } | |
123 | } | |
124 | ||
125 | /* | |
126 | * interrupts disabled on entry | |
127 | */ | |
b129a8cc | 128 | static void imx_stop_tx(struct uart_port *port) |
1da177e4 LT |
129 | { |
130 | struct imx_port *sport = (struct imx_port *)port; | |
131 | UCR1((u32)sport->port.membase) &= ~UCR1_TXMPTYEN; | |
132 | } | |
133 | ||
134 | /* | |
135 | * interrupts disabled on entry | |
136 | */ | |
137 | static void imx_stop_rx(struct uart_port *port) | |
138 | { | |
139 | struct imx_port *sport = (struct imx_port *)port; | |
140 | UCR2((u32)sport->port.membase) &= ~UCR2_RXEN; | |
141 | } | |
142 | ||
143 | /* | |
144 | * Set the modem control timer to fire immediately. | |
145 | */ | |
146 | static void imx_enable_ms(struct uart_port *port) | |
147 | { | |
148 | struct imx_port *sport = (struct imx_port *)port; | |
149 | ||
150 | mod_timer(&sport->timer, jiffies); | |
151 | } | |
152 | ||
153 | static inline void imx_transmit_buffer(struct imx_port *sport) | |
154 | { | |
155 | struct circ_buf *xmit = &sport->port.info->xmit; | |
156 | ||
157 | do { | |
158 | /* send xmit->buf[xmit->tail] | |
159 | * out the port here */ | |
160 | URTX0((u32)sport->port.membase) = xmit->buf[xmit->tail]; | |
161 | xmit->tail = (xmit->tail + 1) & | |
162 | (UART_XMIT_SIZE - 1); | |
163 | sport->port.icount.tx++; | |
164 | if (uart_circ_empty(xmit)) | |
165 | break; | |
166 | } while (!(UTS((u32)sport->port.membase) & UTS_TXFULL)); | |
167 | ||
168 | if (uart_circ_empty(xmit)) | |
b129a8cc | 169 | imx_stop_tx(&sport->port); |
1da177e4 LT |
170 | } |
171 | ||
172 | /* | |
173 | * interrupts disabled on entry | |
174 | */ | |
b129a8cc | 175 | static void imx_start_tx(struct uart_port *port) |
1da177e4 LT |
176 | { |
177 | struct imx_port *sport = (struct imx_port *)port; | |
178 | ||
179 | UCR1((u32)sport->port.membase) |= UCR1_TXMPTYEN; | |
180 | ||
181 | if(UTS((u32)sport->port.membase) & UTS_TXEMPTY) | |
182 | imx_transmit_buffer(sport); | |
183 | } | |
184 | ||
ceca629e SH |
185 | static irqreturn_t imx_rtsint(int irq, void *dev_id, struct pt_regs *regs) |
186 | { | |
187 | struct imx_port *sport = (struct imx_port *)dev_id; | |
188 | unsigned int val = USR1((u32)sport->port.membase)&USR1_RTSS; | |
189 | unsigned long flags; | |
190 | ||
191 | spin_lock_irqsave(&sport->port.lock, flags); | |
192 | ||
193 | USR1((u32)sport->port.membase) = USR1_RTSD; | |
194 | uart_handle_cts_change(&sport->port, !!val); | |
195 | wake_up_interruptible(&sport->port.info->delta_msr_wait); | |
196 | ||
197 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
198 | return IRQ_HANDLED; | |
199 | } | |
200 | ||
1da177e4 LT |
201 | static irqreturn_t imx_txint(int irq, void *dev_id, struct pt_regs *regs) |
202 | { | |
203 | struct imx_port *sport = (struct imx_port *)dev_id; | |
204 | struct circ_buf *xmit = &sport->port.info->xmit; | |
205 | unsigned long flags; | |
206 | ||
207 | spin_lock_irqsave(&sport->port.lock,flags); | |
208 | if (sport->port.x_char) | |
209 | { | |
210 | /* Send next char */ | |
211 | URTX0((u32)sport->port.membase) = sport->port.x_char; | |
212 | goto out; | |
213 | } | |
214 | ||
215 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
b129a8cc | 216 | imx_stop_tx(&sport->port); |
1da177e4 LT |
217 | goto out; |
218 | } | |
219 | ||
220 | imx_transmit_buffer(sport); | |
221 | ||
222 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
223 | uart_write_wakeup(&sport->port); | |
224 | ||
225 | out: | |
226 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
227 | return IRQ_HANDLED; | |
228 | } | |
229 | ||
230 | static irqreturn_t imx_rxint(int irq, void *dev_id, struct pt_regs *regs) | |
231 | { | |
232 | struct imx_port *sport = dev_id; | |
233 | unsigned int rx,flg,ignored = 0; | |
234 | struct tty_struct *tty = sport->port.info->tty; | |
235 | unsigned long flags; | |
236 | ||
237 | rx = URXD0((u32)sport->port.membase); | |
238 | spin_lock_irqsave(&sport->port.lock,flags); | |
239 | ||
240 | do { | |
241 | flg = TTY_NORMAL; | |
242 | sport->port.icount.rx++; | |
243 | ||
244 | if( USR2((u32)sport->port.membase) & USR2_BRCD ) { | |
245 | USR2((u32)sport->port.membase) |= USR2_BRCD; | |
246 | if(uart_handle_break(&sport->port)) | |
247 | goto ignore_char; | |
248 | } | |
249 | ||
250 | if (uart_handle_sysrq_char | |
251 | (&sport->port, (unsigned char)rx, regs)) | |
252 | goto ignore_char; | |
253 | ||
254 | if( rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) | |
255 | goto handle_error; | |
256 | ||
257 | error_return: | |
258 | tty_insert_flip_char(tty, rx, flg); | |
259 | ||
1da177e4 LT |
260 | ignore_char: |
261 | rx = URXD0((u32)sport->port.membase); | |
262 | } while(rx & URXD_CHARRDY); | |
263 | ||
264 | out: | |
265 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
266 | tty_flip_buffer_push(tty); | |
267 | return IRQ_HANDLED; | |
268 | ||
269 | handle_error: | |
270 | if (rx & URXD_PRERR) | |
271 | sport->port.icount.parity++; | |
272 | else if (rx & URXD_FRMERR) | |
273 | sport->port.icount.frame++; | |
274 | if (rx & URXD_OVRRUN) | |
275 | sport->port.icount.overrun++; | |
276 | ||
277 | if (rx & sport->port.ignore_status_mask) { | |
278 | if (++ignored > 100) | |
279 | goto out; | |
280 | goto ignore_char; | |
281 | } | |
282 | ||
283 | rx &= sport->port.read_status_mask; | |
284 | ||
285 | if (rx & URXD_PRERR) | |
286 | flg = TTY_PARITY; | |
287 | else if (rx & URXD_FRMERR) | |
288 | flg = TTY_FRAME; | |
289 | if (rx & URXD_OVRRUN) | |
290 | flg = TTY_OVERRUN; | |
291 | ||
292 | #ifdef SUPPORT_SYSRQ | |
293 | sport->port.sysrq = 0; | |
294 | #endif | |
295 | goto error_return; | |
296 | } | |
297 | ||
298 | /* | |
299 | * Return TIOCSER_TEMT when transmitter is not busy. | |
300 | */ | |
301 | static unsigned int imx_tx_empty(struct uart_port *port) | |
302 | { | |
303 | struct imx_port *sport = (struct imx_port *)port; | |
304 | ||
305 | return USR2((u32)sport->port.membase) & USR2_TXDC ? TIOCSER_TEMT : 0; | |
306 | } | |
307 | ||
0f302dc3 SH |
308 | /* |
309 | * We have a modem side uart, so the meanings of RTS and CTS are inverted. | |
310 | */ | |
1da177e4 LT |
311 | static unsigned int imx_get_mctrl(struct uart_port *port) |
312 | { | |
0f302dc3 SH |
313 | struct imx_port *sport = (struct imx_port *)port; |
314 | unsigned int tmp = TIOCM_DSR | TIOCM_CAR; | |
315 | ||
316 | if (USR1((u32)sport->port.membase) & USR1_RTSS) | |
317 | tmp |= TIOCM_CTS; | |
318 | ||
319 | if (UCR2((u32)sport->port.membase) & UCR2_CTS) | |
320 | tmp |= TIOCM_RTS; | |
321 | ||
322 | return tmp; | |
1da177e4 LT |
323 | } |
324 | ||
325 | static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
326 | { | |
0f302dc3 SH |
327 | struct imx_port *sport = (struct imx_port *)port; |
328 | ||
329 | if (mctrl & TIOCM_RTS) | |
330 | UCR2((u32)sport->port.membase) |= UCR2_CTS; | |
331 | else | |
332 | UCR2((u32)sport->port.membase) &= ~UCR2_CTS; | |
1da177e4 LT |
333 | } |
334 | ||
335 | /* | |
336 | * Interrupts always disabled. | |
337 | */ | |
338 | static void imx_break_ctl(struct uart_port *port, int break_state) | |
339 | { | |
340 | struct imx_port *sport = (struct imx_port *)port; | |
341 | unsigned long flags; | |
342 | ||
343 | spin_lock_irqsave(&sport->port.lock, flags); | |
344 | ||
345 | if ( break_state != 0 ) | |
346 | UCR1((u32)sport->port.membase) |= UCR1_SNDBRK; | |
347 | else | |
348 | UCR1((u32)sport->port.membase) &= ~UCR1_SNDBRK; | |
349 | ||
350 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
351 | } | |
352 | ||
353 | #define TXTL 2 /* reset default */ | |
354 | #define RXTL 1 /* reset default */ | |
355 | ||
587897f5 SH |
356 | static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) |
357 | { | |
358 | unsigned int val; | |
359 | unsigned int ufcr_rfdiv; | |
360 | ||
361 | /* set receiver / transmitter trigger level. | |
362 | * RFDIV is set such way to satisfy requested uartclk value | |
363 | */ | |
364 | val = TXTL<<10 | RXTL; | |
365 | ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk; | |
366 | ||
367 | if(!ufcr_rfdiv) | |
368 | ufcr_rfdiv = 1; | |
369 | ||
370 | if(ufcr_rfdiv >= 7) | |
371 | ufcr_rfdiv = 6; | |
372 | else | |
373 | ufcr_rfdiv = 6 - ufcr_rfdiv; | |
374 | ||
375 | val |= UFCR_RFDIV & (ufcr_rfdiv << 7); | |
376 | ||
377 | UFCR((u32)sport->port.membase) = val; | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
1da177e4 LT |
382 | static int imx_startup(struct uart_port *port) |
383 | { | |
384 | struct imx_port *sport = (struct imx_port *)port; | |
385 | int retval; | |
1da177e4 LT |
386 | unsigned long flags; |
387 | ||
587897f5 | 388 | imx_setup_ufcr(sport, 0); |
1da177e4 LT |
389 | |
390 | /* disable the DREN bit (Data Ready interrupt enable) before | |
391 | * requesting IRQs | |
392 | */ | |
393 | UCR4((u32)sport->port.membase) &= ~UCR4_DREN; | |
394 | ||
395 | /* | |
396 | * Allocate the IRQ | |
397 | */ | |
398 | retval = request_irq(sport->rxirq, imx_rxint, 0, | |
399 | DRIVER_NAME, sport); | |
86371d07 | 400 | if (retval) goto error_out1; |
1da177e4 LT |
401 | |
402 | retval = request_irq(sport->txirq, imx_txint, 0, | |
ceca629e | 403 | DRIVER_NAME, sport); |
86371d07 | 404 | if (retval) goto error_out2; |
1da177e4 | 405 | |
f43aaba1 RK |
406 | retval = request_irq(sport->rtsirq, imx_rtsint, |
407 | SA_TRIGGER_FALLING | SA_TRIGGER_RISING, | |
ceca629e SH |
408 | DRIVER_NAME, sport); |
409 | if (retval) goto error_out3; | |
ceca629e | 410 | |
1da177e4 LT |
411 | /* |
412 | * Finally, clear and enable interrupts | |
413 | */ | |
414 | ||
ceca629e | 415 | USR1((u32)sport->port.membase) = USR1_RTSD; |
1da177e4 | 416 | UCR1((u32)sport->port.membase) |= |
ceca629e | 417 | (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); |
1da177e4 LT |
418 | |
419 | UCR2((u32)sport->port.membase) |= (UCR2_RXEN | UCR2_TXEN); | |
420 | /* | |
421 | * Enable modem status interrupts | |
422 | */ | |
423 | spin_lock_irqsave(&sport->port.lock,flags); | |
424 | imx_enable_ms(&sport->port); | |
425 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
426 | ||
427 | return 0; | |
428 | ||
ceca629e SH |
429 | error_out3: |
430 | free_irq(sport->txirq, sport); | |
1da177e4 | 431 | error_out2: |
86371d07 SH |
432 | free_irq(sport->rxirq, sport); |
433 | error_out1: | |
1da177e4 LT |
434 | return retval; |
435 | } | |
436 | ||
437 | static void imx_shutdown(struct uart_port *port) | |
438 | { | |
439 | struct imx_port *sport = (struct imx_port *)port; | |
440 | ||
441 | /* | |
442 | * Stop our timer. | |
443 | */ | |
444 | del_timer_sync(&sport->timer); | |
445 | ||
446 | /* | |
447 | * Free the interrupts | |
448 | */ | |
ceca629e | 449 | free_irq(sport->rtsirq, sport); |
1da177e4 LT |
450 | free_irq(sport->txirq, sport); |
451 | free_irq(sport->rxirq, sport); | |
452 | ||
453 | /* | |
454 | * Disable all interrupts, port and break condition. | |
455 | */ | |
456 | ||
457 | UCR1((u32)sport->port.membase) &= | |
ceca629e | 458 | ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); |
1da177e4 LT |
459 | } |
460 | ||
461 | static void | |
462 | imx_set_termios(struct uart_port *port, struct termios *termios, | |
463 | struct termios *old) | |
464 | { | |
465 | struct imx_port *sport = (struct imx_port *)port; | |
466 | unsigned long flags; | |
467 | unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; | |
468 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
469 | ||
470 | /* | |
471 | * If we don't support modem control lines, don't allow | |
472 | * these to be set. | |
473 | */ | |
474 | if (0) { | |
475 | termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); | |
476 | termios->c_cflag |= CLOCAL; | |
477 | } | |
478 | ||
479 | /* | |
480 | * We only support CS7 and CS8. | |
481 | */ | |
482 | while ((termios->c_cflag & CSIZE) != CS7 && | |
483 | (termios->c_cflag & CSIZE) != CS8) { | |
484 | termios->c_cflag &= ~CSIZE; | |
485 | termios->c_cflag |= old_csize; | |
486 | old_csize = CS8; | |
487 | } | |
488 | ||
489 | if ((termios->c_cflag & CSIZE) == CS8) | |
490 | ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; | |
491 | else | |
492 | ucr2 = UCR2_SRST | UCR2_IRTS; | |
493 | ||
494 | if (termios->c_cflag & CRTSCTS) { | |
5b802344 SH |
495 | if( sport->have_rtscts ) { |
496 | ucr2 &= ~UCR2_IRTS; | |
497 | ucr2 |= UCR2_CTSC; | |
498 | } else { | |
499 | termios->c_cflag &= ~CRTSCTS; | |
500 | } | |
1da177e4 LT |
501 | } |
502 | ||
503 | if (termios->c_cflag & CSTOPB) | |
504 | ucr2 |= UCR2_STPB; | |
505 | if (termios->c_cflag & PARENB) { | |
506 | ucr2 |= UCR2_PREN; | |
3261e362 | 507 | if (termios->c_cflag & PARODD) |
1da177e4 LT |
508 | ucr2 |= UCR2_PROE; |
509 | } | |
510 | ||
511 | /* | |
512 | * Ask the core to calculate the divisor for us. | |
513 | */ | |
514 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
515 | quot = uart_get_divisor(port, baud); | |
516 | ||
517 | spin_lock_irqsave(&sport->port.lock, flags); | |
518 | ||
519 | sport->port.read_status_mask = 0; | |
520 | if (termios->c_iflag & INPCK) | |
521 | sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); | |
522 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
523 | sport->port.read_status_mask |= URXD_BRK; | |
524 | ||
525 | /* | |
526 | * Characters to ignore | |
527 | */ | |
528 | sport->port.ignore_status_mask = 0; | |
529 | if (termios->c_iflag & IGNPAR) | |
530 | sport->port.ignore_status_mask |= URXD_PRERR; | |
531 | if (termios->c_iflag & IGNBRK) { | |
532 | sport->port.ignore_status_mask |= URXD_BRK; | |
533 | /* | |
534 | * If we're ignoring parity and break indicators, | |
535 | * ignore overruns too (for real raw support). | |
536 | */ | |
537 | if (termios->c_iflag & IGNPAR) | |
538 | sport->port.ignore_status_mask |= URXD_OVRRUN; | |
539 | } | |
540 | ||
541 | del_timer_sync(&sport->timer); | |
542 | ||
543 | /* | |
544 | * Update the per-port timeout. | |
545 | */ | |
546 | uart_update_timeout(port, termios->c_cflag, baud); | |
547 | ||
548 | /* | |
549 | * disable interrupts and drain transmitter | |
550 | */ | |
551 | old_ucr1 = UCR1((u32)sport->port.membase); | |
ceca629e | 552 | UCR1((u32)sport->port.membase) &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); |
1da177e4 LT |
553 | |
554 | while ( !(USR2((u32)sport->port.membase) & USR2_TXDC)) | |
555 | barrier(); | |
556 | ||
557 | /* then, disable everything */ | |
558 | old_txrxen = UCR2((u32)sport->port.membase) & ( UCR2_TXEN | UCR2_RXEN ); | |
559 | UCR2((u32)sport->port.membase) &= ~( UCR2_TXEN | UCR2_RXEN); | |
560 | ||
561 | /* set the parity, stop bits and data size */ | |
562 | UCR2((u32)sport->port.membase) = ucr2; | |
563 | ||
564 | /* set the baud rate. We assume uartclk = 16 MHz | |
565 | * | |
566 | * baud * 16 UBIR - 1 | |
567 | * --------- = -------- | |
568 | * uartclk UBMR - 1 | |
569 | */ | |
570 | UBIR((u32)sport->port.membase) = (baud / 100) - 1; | |
571 | UBMR((u32)sport->port.membase) = 10000 - 1; | |
572 | ||
573 | UCR1((u32)sport->port.membase) = old_ucr1; | |
574 | UCR2((u32)sport->port.membase) |= old_txrxen; | |
575 | ||
576 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | |
577 | imx_enable_ms(&sport->port); | |
578 | ||
579 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
580 | } | |
581 | ||
582 | static const char *imx_type(struct uart_port *port) | |
583 | { | |
584 | struct imx_port *sport = (struct imx_port *)port; | |
585 | ||
586 | return sport->port.type == PORT_IMX ? "IMX" : NULL; | |
587 | } | |
588 | ||
589 | /* | |
590 | * Release the memory region(s) being used by 'port'. | |
591 | */ | |
592 | static void imx_release_port(struct uart_port *port) | |
593 | { | |
594 | struct imx_port *sport = (struct imx_port *)port; | |
595 | ||
596 | release_mem_region(sport->port.mapbase, UART_PORT_SIZE); | |
597 | } | |
598 | ||
599 | /* | |
600 | * Request the memory region(s) being used by 'port'. | |
601 | */ | |
602 | static int imx_request_port(struct uart_port *port) | |
603 | { | |
604 | struct imx_port *sport = (struct imx_port *)port; | |
605 | ||
606 | return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, | |
607 | "imx-uart") != NULL ? 0 : -EBUSY; | |
608 | } | |
609 | ||
610 | /* | |
611 | * Configure/autoconfigure the port. | |
612 | */ | |
613 | static void imx_config_port(struct uart_port *port, int flags) | |
614 | { | |
615 | struct imx_port *sport = (struct imx_port *)port; | |
616 | ||
617 | if (flags & UART_CONFIG_TYPE && | |
618 | imx_request_port(&sport->port) == 0) | |
619 | sport->port.type = PORT_IMX; | |
620 | } | |
621 | ||
622 | /* | |
623 | * Verify the new serial_struct (for TIOCSSERIAL). | |
624 | * The only change we allow are to the flags and type, and | |
625 | * even then only between PORT_IMX and PORT_UNKNOWN | |
626 | */ | |
627 | static int | |
628 | imx_verify_port(struct uart_port *port, struct serial_struct *ser) | |
629 | { | |
630 | struct imx_port *sport = (struct imx_port *)port; | |
631 | int ret = 0; | |
632 | ||
633 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) | |
634 | ret = -EINVAL; | |
635 | if (sport->port.irq != ser->irq) | |
636 | ret = -EINVAL; | |
637 | if (ser->io_type != UPIO_MEM) | |
638 | ret = -EINVAL; | |
639 | if (sport->port.uartclk / 16 != ser->baud_base) | |
640 | ret = -EINVAL; | |
641 | if ((void *)sport->port.mapbase != ser->iomem_base) | |
642 | ret = -EINVAL; | |
643 | if (sport->port.iobase != ser->port) | |
644 | ret = -EINVAL; | |
645 | if (ser->hub6 != 0) | |
646 | ret = -EINVAL; | |
647 | return ret; | |
648 | } | |
649 | ||
650 | static struct uart_ops imx_pops = { | |
651 | .tx_empty = imx_tx_empty, | |
652 | .set_mctrl = imx_set_mctrl, | |
653 | .get_mctrl = imx_get_mctrl, | |
654 | .stop_tx = imx_stop_tx, | |
655 | .start_tx = imx_start_tx, | |
656 | .stop_rx = imx_stop_rx, | |
657 | .enable_ms = imx_enable_ms, | |
658 | .break_ctl = imx_break_ctl, | |
659 | .startup = imx_startup, | |
660 | .shutdown = imx_shutdown, | |
661 | .set_termios = imx_set_termios, | |
662 | .type = imx_type, | |
663 | .release_port = imx_release_port, | |
664 | .request_port = imx_request_port, | |
665 | .config_port = imx_config_port, | |
666 | .verify_port = imx_verify_port, | |
667 | }; | |
668 | ||
669 | static struct imx_port imx_ports[] = { | |
670 | { | |
671 | .txirq = UART1_MINT_TX, | |
672 | .rxirq = UART1_MINT_RX, | |
ceca629e | 673 | .rtsirq = UART1_MINT_RTS, |
1da177e4 LT |
674 | .port = { |
675 | .type = PORT_IMX, | |
9b4a1617 | 676 | .iotype = UPIO_MEM, |
1da177e4 LT |
677 | .membase = (void *)IMX_UART1_BASE, |
678 | .mapbase = IMX_UART1_BASE, /* FIXME */ | |
679 | .irq = UART1_MINT_RX, | |
680 | .uartclk = 16000000, | |
681 | .fifosize = 8, | |
ce8337cb | 682 | .flags = UPF_BOOT_AUTOCONF, |
1da177e4 LT |
683 | .ops = &imx_pops, |
684 | .line = 0, | |
685 | }, | |
686 | }, { | |
687 | .txirq = UART2_MINT_TX, | |
688 | .rxirq = UART2_MINT_RX, | |
ceca629e | 689 | .rtsirq = UART2_MINT_RTS, |
1da177e4 LT |
690 | .port = { |
691 | .type = PORT_IMX, | |
9b4a1617 | 692 | .iotype = UPIO_MEM, |
1da177e4 LT |
693 | .membase = (void *)IMX_UART2_BASE, |
694 | .mapbase = IMX_UART2_BASE, /* FIXME */ | |
695 | .irq = UART2_MINT_RX, | |
696 | .uartclk = 16000000, | |
697 | .fifosize = 8, | |
ce8337cb | 698 | .flags = UPF_BOOT_AUTOCONF, |
1da177e4 LT |
699 | .ops = &imx_pops, |
700 | .line = 1, | |
701 | }, | |
702 | } | |
703 | }; | |
704 | ||
705 | /* | |
706 | * Setup the IMX serial ports. | |
707 | * Note also that we support "console=ttySMXx" where "x" is either 0 or 1. | |
708 | * Which serial port this ends up being depends on the machine you're | |
709 | * running this kernel on. I'm not convinced that this is a good idea, | |
710 | * but that's the way it traditionally works. | |
711 | * | |
712 | */ | |
713 | static void __init imx_init_ports(void) | |
714 | { | |
715 | static int first = 1; | |
716 | int i; | |
717 | ||
718 | if (!first) | |
719 | return; | |
720 | first = 0; | |
721 | ||
722 | for (i = 0; i < ARRAY_SIZE(imx_ports); i++) { | |
723 | init_timer(&imx_ports[i].timer); | |
724 | imx_ports[i].timer.function = imx_timeout; | |
725 | imx_ports[i].timer.data = (unsigned long)&imx_ports[i]; | |
726 | } | |
1da177e4 LT |
727 | } |
728 | ||
729 | #ifdef CONFIG_SERIAL_IMX_CONSOLE | |
d358788f RK |
730 | static void imx_console_putchar(struct uart_port *port, int ch) |
731 | { | |
732 | struct imx_port *sport = (struct imx_port *)port; | |
733 | while ((UTS((u32)sport->port.membase) & UTS_TXFULL)) | |
734 | barrier(); | |
735 | URTX0((u32)sport->port.membase) = ch; | |
736 | } | |
1da177e4 LT |
737 | |
738 | /* | |
739 | * Interrupts are disabled on entering | |
740 | */ | |
741 | static void | |
742 | imx_console_write(struct console *co, const char *s, unsigned int count) | |
743 | { | |
744 | struct imx_port *sport = &imx_ports[co->index]; | |
d358788f | 745 | unsigned int old_ucr1, old_ucr2; |
1da177e4 LT |
746 | |
747 | /* | |
748 | * First, save UCR1/2 and then disable interrupts | |
749 | */ | |
750 | old_ucr1 = UCR1((u32)sport->port.membase); | |
751 | old_ucr2 = UCR2((u32)sport->port.membase); | |
752 | ||
753 | UCR1((u32)sport->port.membase) = | |
754 | (old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) | |
ceca629e | 755 | & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); |
1da177e4 LT |
756 | UCR2((u32)sport->port.membase) = old_ucr2 | UCR2_TXEN; |
757 | ||
d358788f | 758 | uart_console_write(&sport->port, s, count, imx_console_putchar); |
1da177e4 LT |
759 | |
760 | /* | |
761 | * Finally, wait for transmitter to become empty | |
762 | * and restore UCR1/2 | |
763 | */ | |
764 | while (!(USR2((u32)sport->port.membase) & USR2_TXDC)); | |
765 | ||
766 | UCR1((u32)sport->port.membase) = old_ucr1; | |
767 | UCR2((u32)sport->port.membase) = old_ucr2; | |
768 | } | |
769 | ||
770 | /* | |
771 | * If the port was already initialised (eg, by a boot loader), | |
772 | * try to determine the current setup. | |
773 | */ | |
774 | static void __init | |
775 | imx_console_get_options(struct imx_port *sport, int *baud, | |
776 | int *parity, int *bits) | |
777 | { | |
587897f5 | 778 | |
1da177e4 LT |
779 | if ( UCR1((u32)sport->port.membase) | UCR1_UARTEN ) { |
780 | /* ok, the port was enabled */ | |
781 | unsigned int ucr2, ubir,ubmr, uartclk; | |
587897f5 SH |
782 | unsigned int baud_raw; |
783 | unsigned int ucfr_rfdiv; | |
1da177e4 LT |
784 | |
785 | ucr2 = UCR2((u32)sport->port.membase); | |
786 | ||
787 | *parity = 'n'; | |
788 | if (ucr2 & UCR2_PREN) { | |
789 | if (ucr2 & UCR2_PROE) | |
790 | *parity = 'o'; | |
791 | else | |
792 | *parity = 'e'; | |
793 | } | |
794 | ||
795 | if (ucr2 & UCR2_WS) | |
796 | *bits = 8; | |
797 | else | |
798 | *bits = 7; | |
799 | ||
800 | ubir = UBIR((u32)sport->port.membase) & 0xffff; | |
801 | ubmr = UBMR((u32)sport->port.membase) & 0xffff; | |
1da177e4 | 802 | |
587897f5 SH |
803 | |
804 | ucfr_rfdiv = (UFCR((u32)sport->port.membase) & UFCR_RFDIV) >> 7; | |
805 | if (ucfr_rfdiv == 6) | |
806 | ucfr_rfdiv = 7; | |
807 | else | |
808 | ucfr_rfdiv = 6 - ucfr_rfdiv; | |
809 | ||
810 | uartclk = imx_get_perclk1(); | |
811 | uartclk /= ucfr_rfdiv; | |
812 | ||
813 | { /* | |
814 | * The next code provides exact computation of | |
815 | * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) | |
816 | * without need of float support or long long division, | |
817 | * which would be required to prevent 32bit arithmetic overflow | |
818 | */ | |
819 | unsigned int mul = ubir + 1; | |
820 | unsigned int div = 16 * (ubmr + 1); | |
821 | unsigned int rem = uartclk % div; | |
822 | ||
823 | baud_raw = (uartclk / div) * mul; | |
824 | baud_raw += (rem * mul + div / 2) / div; | |
825 | *baud = (baud_raw + 50) / 100 * 100; | |
826 | } | |
827 | ||
828 | if(*baud != baud_raw) | |
829 | printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n", | |
830 | baud_raw, *baud); | |
1da177e4 LT |
831 | } |
832 | } | |
833 | ||
834 | static int __init | |
835 | imx_console_setup(struct console *co, char *options) | |
836 | { | |
837 | struct imx_port *sport; | |
838 | int baud = 9600; | |
839 | int bits = 8; | |
840 | int parity = 'n'; | |
841 | int flow = 'n'; | |
842 | ||
843 | /* | |
844 | * Check whether an invalid uart number has been specified, and | |
845 | * if so, search for the first available port that does have | |
846 | * console support. | |
847 | */ | |
848 | if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) | |
849 | co->index = 0; | |
850 | sport = &imx_ports[co->index]; | |
851 | ||
852 | if (options) | |
853 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
854 | else | |
855 | imx_console_get_options(sport, &baud, &parity, &bits); | |
856 | ||
587897f5 SH |
857 | imx_setup_ufcr(sport, 0); |
858 | ||
1da177e4 LT |
859 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); |
860 | } | |
861 | ||
9f4426dd | 862 | static struct uart_driver imx_reg; |
1da177e4 LT |
863 | static struct console imx_console = { |
864 | .name = "ttySMX", | |
865 | .write = imx_console_write, | |
866 | .device = uart_console_device, | |
867 | .setup = imx_console_setup, | |
868 | .flags = CON_PRINTBUFFER, | |
869 | .index = -1, | |
870 | .data = &imx_reg, | |
871 | }; | |
872 | ||
873 | static int __init imx_rs_console_init(void) | |
874 | { | |
875 | imx_init_ports(); | |
876 | register_console(&imx_console); | |
877 | return 0; | |
878 | } | |
879 | console_initcall(imx_rs_console_init); | |
880 | ||
881 | #define IMX_CONSOLE &imx_console | |
882 | #else | |
883 | #define IMX_CONSOLE NULL | |
884 | #endif | |
885 | ||
886 | static struct uart_driver imx_reg = { | |
887 | .owner = THIS_MODULE, | |
888 | .driver_name = DRIVER_NAME, | |
889 | .dev_name = "ttySMX", | |
1da177e4 LT |
890 | .major = SERIAL_IMX_MAJOR, |
891 | .minor = MINOR_START, | |
892 | .nr = ARRAY_SIZE(imx_ports), | |
893 | .cons = IMX_CONSOLE, | |
894 | }; | |
895 | ||
3ae5eaec | 896 | static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 897 | { |
3ae5eaec | 898 | struct imx_port *sport = platform_get_drvdata(dev); |
1da177e4 | 899 | |
9480e307 | 900 | if (sport) |
1da177e4 LT |
901 | uart_suspend_port(&imx_reg, &sport->port); |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
3ae5eaec | 906 | static int serial_imx_resume(struct platform_device *dev) |
1da177e4 | 907 | { |
3ae5eaec | 908 | struct imx_port *sport = platform_get_drvdata(dev); |
1da177e4 | 909 | |
9480e307 | 910 | if (sport) |
1da177e4 LT |
911 | uart_resume_port(&imx_reg, &sport->port); |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
3ae5eaec | 916 | static int serial_imx_probe(struct platform_device *dev) |
1da177e4 | 917 | { |
5b802344 SH |
918 | struct imxuart_platform_data *pdata; |
919 | ||
3ae5eaec | 920 | imx_ports[dev->id].port.dev = &dev->dev; |
5b802344 SH |
921 | |
922 | pdata = (struct imxuart_platform_data *)dev->dev.platform_data; | |
923 | if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) | |
924 | imx_ports[dev->id].have_rtscts = 1; | |
925 | ||
1da177e4 | 926 | uart_add_one_port(&imx_reg, &imx_ports[dev->id].port); |
3ae5eaec | 927 | platform_set_drvdata(dev, &imx_ports[dev->id]); |
1da177e4 LT |
928 | return 0; |
929 | } | |
930 | ||
3ae5eaec | 931 | static int serial_imx_remove(struct platform_device *dev) |
1da177e4 | 932 | { |
3ae5eaec | 933 | struct imx_port *sport = platform_get_drvdata(dev); |
1da177e4 | 934 | |
3ae5eaec | 935 | platform_set_drvdata(dev, NULL); |
1da177e4 LT |
936 | |
937 | if (sport) | |
938 | uart_remove_one_port(&imx_reg, &sport->port); | |
939 | ||
940 | return 0; | |
941 | } | |
942 | ||
3ae5eaec | 943 | static struct platform_driver serial_imx_driver = { |
1da177e4 LT |
944 | .probe = serial_imx_probe, |
945 | .remove = serial_imx_remove, | |
946 | ||
947 | .suspend = serial_imx_suspend, | |
948 | .resume = serial_imx_resume, | |
3ae5eaec RK |
949 | .driver = { |
950 | .name = "imx-uart", | |
951 | }, | |
1da177e4 LT |
952 | }; |
953 | ||
954 | static int __init imx_serial_init(void) | |
955 | { | |
956 | int ret; | |
957 | ||
958 | printk(KERN_INFO "Serial: IMX driver\n"); | |
959 | ||
960 | imx_init_ports(); | |
961 | ||
962 | ret = uart_register_driver(&imx_reg); | |
963 | if (ret) | |
964 | return ret; | |
965 | ||
3ae5eaec | 966 | ret = platform_driver_register(&serial_imx_driver); |
1da177e4 LT |
967 | if (ret != 0) |
968 | uart_unregister_driver(&imx_reg); | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
973 | static void __exit imx_serial_exit(void) | |
974 | { | |
975 | uart_unregister_driver(&imx_reg); | |
c889b896 | 976 | platform_driver_unregister(&serial_imx_driver); |
1da177e4 LT |
977 | } |
978 | ||
979 | module_init(imx_serial_init); | |
980 | module_exit(imx_serial_exit); | |
981 | ||
982 | MODULE_AUTHOR("Sascha Hauer"); | |
983 | MODULE_DESCRIPTION("IMX generic serial port driver"); | |
984 | MODULE_LICENSE("GPL"); |