]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/imx.c | |
3 | * | |
4 | * Driver for Motorola IMX serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Author: Sascha Hauer <sascha@saschahauer.de> | |
9 | * Copyright (C) 2004 Pengutronix | |
10 | * | |
b6e49138 FG |
11 | * Copyright (C) 2009 emlix GmbH |
12 | * Author: Fabian Godehardt (added IrDA support for iMX) | |
13 | * | |
1da177e4 LT |
14 | * This program is free software; you can redistribute it and/or modify |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
27 | * | |
28 | * [29-Mar-2005] Mike Lee | |
29 | * Added hardware handshake | |
30 | */ | |
1da177e4 LT |
31 | |
32 | #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
33 | #define SUPPORT_SYSRQ | |
34 | #endif | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/ioport.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/console.h> | |
40 | #include <linux/sysrq.h> | |
d052d1be | 41 | #include <linux/platform_device.h> |
1da177e4 LT |
42 | #include <linux/tty.h> |
43 | #include <linux/tty_flip.h> | |
44 | #include <linux/serial_core.h> | |
45 | #include <linux/serial.h> | |
38a41fdf | 46 | #include <linux/clk.h> |
b6e49138 | 47 | #include <linux/delay.h> |
534fca06 | 48 | #include <linux/rational.h> |
5a0e3ad6 | 49 | #include <linux/slab.h> |
1da177e4 LT |
50 | |
51 | #include <asm/io.h> | |
52 | #include <asm/irq.h> | |
a09e64fb RK |
53 | #include <mach/hardware.h> |
54 | #include <mach/imx-uart.h> | |
1da177e4 | 55 | |
ff4bfb21 SH |
56 | /* Register definitions */ |
57 | #define URXD0 0x0 /* Receiver Register */ | |
58 | #define URTX0 0x40 /* Transmitter Register */ | |
59 | #define UCR1 0x80 /* Control Register 1 */ | |
60 | #define UCR2 0x84 /* Control Register 2 */ | |
61 | #define UCR3 0x88 /* Control Register 3 */ | |
62 | #define UCR4 0x8c /* Control Register 4 */ | |
63 | #define UFCR 0x90 /* FIFO Control Register */ | |
64 | #define USR1 0x94 /* Status Register 1 */ | |
65 | #define USR2 0x98 /* Status Register 2 */ | |
66 | #define UESC 0x9c /* Escape Character Register */ | |
67 | #define UTIM 0xa0 /* Escape Timer Register */ | |
68 | #define UBIR 0xa4 /* BRM Incremental Register */ | |
69 | #define UBMR 0xa8 /* BRM Modulator Register */ | |
70 | #define UBRC 0xac /* Baud Rate Count Register */ | |
37d6fb62 SH |
71 | #define MX2_ONEMS 0xb0 /* One Millisecond register */ |
72 | #define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */ | |
ff4bfb21 SH |
73 | |
74 | /* UART Control Register Bit Fields.*/ | |
75 | #define URXD_CHARRDY (1<<15) | |
76 | #define URXD_ERR (1<<14) | |
77 | #define URXD_OVRRUN (1<<13) | |
78 | #define URXD_FRMERR (1<<12) | |
79 | #define URXD_BRK (1<<11) | |
80 | #define URXD_PRERR (1<<10) | |
81 | #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ | |
82 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ | |
83 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ | |
84 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ | |
85 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ | |
86 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ | |
87 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ | |
88 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ | |
89 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | |
90 | #define UCR1_SNDBRK (1<<4) /* Send break */ | |
91 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | |
37d6fb62 | 92 | #define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */ |
ff4bfb21 SH |
93 | #define UCR1_DOZE (1<<1) /* Doze */ |
94 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | |
95 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | |
96 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ | |
97 | #define UCR2_CTSC (1<<13) /* CTS pin control */ | |
98 | #define UCR2_CTS (1<<12) /* Clear to send */ | |
99 | #define UCR2_ESCEN (1<<11) /* Escape enable */ | |
100 | #define UCR2_PREN (1<<8) /* Parity enable */ | |
101 | #define UCR2_PROE (1<<7) /* Parity odd/even */ | |
102 | #define UCR2_STPB (1<<6) /* Stop */ | |
103 | #define UCR2_WS (1<<5) /* Word size */ | |
104 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | |
105 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ | |
106 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ | |
107 | #define UCR2_SRST (1<<0) /* SW reset */ | |
108 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ | |
109 | #define UCR3_PARERREN (1<<12) /* Parity enable */ | |
110 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ | |
111 | #define UCR3_DSR (1<<10) /* Data set ready */ | |
112 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | |
113 | #define UCR3_RI (1<<8) /* Ring indicator */ | |
114 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ | |
115 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | |
116 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | |
117 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | |
37d6fb62 SH |
118 | #define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ |
119 | #define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ | |
120 | #define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */ | |
ff4bfb21 SH |
121 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ |
122 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | |
123 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ | |
124 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ | |
125 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ | |
126 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ | |
127 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ | |
128 | #define UCR4_IRSC (1<<5) /* IR special case */ | |
129 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ | |
130 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ | |
131 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ | |
132 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ | |
133 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ | |
134 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ | |
b6e49138 | 135 | #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) |
ff4bfb21 SH |
136 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ |
137 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ | |
138 | #define USR1_RTSS (1<<14) /* RTS pin status */ | |
139 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ | |
140 | #define USR1_RTSD (1<<12) /* RTS delta */ | |
141 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ | |
142 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ | |
143 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ | |
144 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ | |
145 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ | |
146 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ | |
147 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ | |
148 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ | |
149 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ | |
150 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ | |
151 | #define USR2_IDLE (1<<12) /* Idle condition */ | |
152 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ | |
153 | #define USR2_WAKE (1<<7) /* Wake */ | |
154 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ | |
155 | #define USR2_TXDC (1<<3) /* Transmitter complete */ | |
156 | #define USR2_BRCD (1<<2) /* Break condition */ | |
157 | #define USR2_ORE (1<<1) /* Overrun error */ | |
158 | #define USR2_RDR (1<<0) /* Recv data ready */ | |
159 | #define UTS_FRCPERR (1<<13) /* Force parity error */ | |
160 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ | |
161 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ | |
162 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ | |
163 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ | |
164 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ | |
165 | #define UTS_SOFTRST (1<<0) /* Software reset */ | |
166 | ||
1da177e4 | 167 | /* We've been assigned a range on the "Low-density serial ports" major */ |
e3d13ff4 SH |
168 | #define SERIAL_IMX_MAJOR 207 |
169 | #define MINOR_START 16 | |
170 | #define DEV_NAME "ttymxc" | |
9d631b83 | 171 | #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS |
1da177e4 | 172 | |
1da177e4 LT |
173 | /* |
174 | * This determines how often we check the modem status signals | |
175 | * for any change. They generally aren't connected to an IRQ | |
176 | * so we have to poll them. We also check immediately before | |
177 | * filling the TX fifo incase CTS has been dropped. | |
178 | */ | |
179 | #define MCTRL_TIMEOUT (250*HZ/1000) | |
180 | ||
181 | #define DRIVER_NAME "IMX-uart" | |
182 | ||
dbff4e9e SH |
183 | #define UART_NR 8 |
184 | ||
1da177e4 LT |
185 | struct imx_port { |
186 | struct uart_port port; | |
187 | struct timer_list timer; | |
188 | unsigned int old_status; | |
5b802344 | 189 | int txirq,rxirq,rtsirq; |
26bbb3ff | 190 | unsigned int have_rtscts:1; |
b6e49138 FG |
191 | unsigned int use_irda:1; |
192 | unsigned int irda_inv_rx:1; | |
193 | unsigned int irda_inv_tx:1; | |
194 | unsigned short trcv_delay; /* transceiver delay */ | |
38a41fdf | 195 | struct clk *clk; |
1da177e4 LT |
196 | }; |
197 | ||
b6e49138 FG |
198 | #ifdef CONFIG_IRDA |
199 | #define USE_IRDA(sport) ((sport)->use_irda) | |
200 | #else | |
201 | #define USE_IRDA(sport) (0) | |
202 | #endif | |
203 | ||
1da177e4 LT |
204 | /* |
205 | * Handle any change of modem status signal since we were last called. | |
206 | */ | |
207 | static void imx_mctrl_check(struct imx_port *sport) | |
208 | { | |
209 | unsigned int status, changed; | |
210 | ||
211 | status = sport->port.ops->get_mctrl(&sport->port); | |
212 | changed = status ^ sport->old_status; | |
213 | ||
214 | if (changed == 0) | |
215 | return; | |
216 | ||
217 | sport->old_status = status; | |
218 | ||
219 | if (changed & TIOCM_RI) | |
220 | sport->port.icount.rng++; | |
221 | if (changed & TIOCM_DSR) | |
222 | sport->port.icount.dsr++; | |
223 | if (changed & TIOCM_CAR) | |
224 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | |
225 | if (changed & TIOCM_CTS) | |
226 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | |
227 | ||
bdc04e31 | 228 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
1da177e4 LT |
229 | } |
230 | ||
231 | /* | |
232 | * This is our per-port timeout handler, for checking the | |
233 | * modem status signals. | |
234 | */ | |
235 | static void imx_timeout(unsigned long data) | |
236 | { | |
237 | struct imx_port *sport = (struct imx_port *)data; | |
238 | unsigned long flags; | |
239 | ||
ebd2c8f6 | 240 | if (sport->port.state) { |
1da177e4 LT |
241 | spin_lock_irqsave(&sport->port.lock, flags); |
242 | imx_mctrl_check(sport); | |
243 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
244 | ||
245 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | |
246 | } | |
247 | } | |
248 | ||
249 | /* | |
250 | * interrupts disabled on entry | |
251 | */ | |
b129a8cc | 252 | static void imx_stop_tx(struct uart_port *port) |
1da177e4 LT |
253 | { |
254 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
255 | unsigned long temp; |
256 | ||
b6e49138 FG |
257 | if (USE_IRDA(sport)) { |
258 | /* half duplex - wait for end of transmission */ | |
259 | int n = 256; | |
260 | while ((--n > 0) && | |
261 | !(readl(sport->port.membase + USR2) & USR2_TXDC)) { | |
262 | udelay(5); | |
263 | barrier(); | |
264 | } | |
265 | /* | |
266 | * irda transceiver - wait a bit more to avoid | |
267 | * cutoff, hardware dependent | |
268 | */ | |
269 | udelay(sport->trcv_delay); | |
270 | ||
271 | /* | |
272 | * half duplex - reactivate receive mode, | |
273 | * flush receive pipe echo crap | |
274 | */ | |
275 | if (readl(sport->port.membase + USR2) & USR2_TXDC) { | |
276 | temp = readl(sport->port.membase + UCR1); | |
277 | temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); | |
278 | writel(temp, sport->port.membase + UCR1); | |
279 | ||
280 | temp = readl(sport->port.membase + UCR4); | |
281 | temp &= ~(UCR4_TCEN); | |
282 | writel(temp, sport->port.membase + UCR4); | |
283 | ||
284 | while (readl(sport->port.membase + URXD0) & | |
285 | URXD_CHARRDY) | |
286 | barrier(); | |
287 | ||
288 | temp = readl(sport->port.membase + UCR1); | |
289 | temp |= UCR1_RRDYEN; | |
290 | writel(temp, sport->port.membase + UCR1); | |
291 | ||
292 | temp = readl(sport->port.membase + UCR4); | |
293 | temp |= UCR4_DREN; | |
294 | writel(temp, sport->port.membase + UCR4); | |
295 | } | |
296 | return; | |
297 | } | |
298 | ||
ff4bfb21 SH |
299 | temp = readl(sport->port.membase + UCR1); |
300 | writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); | |
1da177e4 LT |
301 | } |
302 | ||
303 | /* | |
304 | * interrupts disabled on entry | |
305 | */ | |
306 | static void imx_stop_rx(struct uart_port *port) | |
307 | { | |
308 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
309 | unsigned long temp; |
310 | ||
311 | temp = readl(sport->port.membase + UCR2); | |
312 | writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2); | |
1da177e4 LT |
313 | } |
314 | ||
315 | /* | |
316 | * Set the modem control timer to fire immediately. | |
317 | */ | |
318 | static void imx_enable_ms(struct uart_port *port) | |
319 | { | |
320 | struct imx_port *sport = (struct imx_port *)port; | |
321 | ||
322 | mod_timer(&sport->timer, jiffies); | |
323 | } | |
324 | ||
325 | static inline void imx_transmit_buffer(struct imx_port *sport) | |
326 | { | |
ebd2c8f6 | 327 | struct circ_buf *xmit = &sport->port.state->xmit; |
1da177e4 | 328 | |
ff4bfb21 | 329 | while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) { |
1da177e4 LT |
330 | /* send xmit->buf[xmit->tail] |
331 | * out the port here */ | |
ff4bfb21 | 332 | writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); |
d3810cd4 | 333 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1da177e4 LT |
334 | sport->port.icount.tx++; |
335 | if (uart_circ_empty(xmit)) | |
336 | break; | |
8c0b254b | 337 | } |
1da177e4 | 338 | |
97775731 FG |
339 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
340 | uart_write_wakeup(&sport->port); | |
341 | ||
1da177e4 | 342 | if (uart_circ_empty(xmit)) |
b129a8cc | 343 | imx_stop_tx(&sport->port); |
1da177e4 LT |
344 | } |
345 | ||
346 | /* | |
347 | * interrupts disabled on entry | |
348 | */ | |
b129a8cc | 349 | static void imx_start_tx(struct uart_port *port) |
1da177e4 LT |
350 | { |
351 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 352 | unsigned long temp; |
1da177e4 | 353 | |
b6e49138 FG |
354 | if (USE_IRDA(sport)) { |
355 | /* half duplex in IrDA mode; have to disable receive mode */ | |
356 | temp = readl(sport->port.membase + UCR4); | |
357 | temp &= ~(UCR4_DREN); | |
358 | writel(temp, sport->port.membase + UCR4); | |
359 | ||
360 | temp = readl(sport->port.membase + UCR1); | |
361 | temp &= ~(UCR1_RRDYEN); | |
362 | writel(temp, sport->port.membase + UCR1); | |
363 | } | |
364 | ||
ff4bfb21 SH |
365 | temp = readl(sport->port.membase + UCR1); |
366 | writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); | |
1da177e4 | 367 | |
b6e49138 FG |
368 | if (USE_IRDA(sport)) { |
369 | temp = readl(sport->port.membase + UCR1); | |
370 | temp |= UCR1_TRDYEN; | |
371 | writel(temp, sport->port.membase + UCR1); | |
372 | ||
373 | temp = readl(sport->port.membase + UCR4); | |
374 | temp |= UCR4_TCEN; | |
375 | writel(temp, sport->port.membase + UCR4); | |
376 | } | |
377 | ||
ff4bfb21 SH |
378 | if (readl(sport->port.membase + UTS) & UTS_TXEMPTY) |
379 | imx_transmit_buffer(sport); | |
1da177e4 LT |
380 | } |
381 | ||
7d12e780 | 382 | static irqreturn_t imx_rtsint(int irq, void *dev_id) |
ceca629e | 383 | { |
15aafa2f | 384 | struct imx_port *sport = dev_id; |
ff4bfb21 | 385 | unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS; |
ceca629e SH |
386 | unsigned long flags; |
387 | ||
388 | spin_lock_irqsave(&sport->port.lock, flags); | |
389 | ||
ff4bfb21 | 390 | writel(USR1_RTSD, sport->port.membase + USR1); |
ceca629e | 391 | uart_handle_cts_change(&sport->port, !!val); |
bdc04e31 | 392 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
ceca629e SH |
393 | |
394 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
395 | return IRQ_HANDLED; | |
396 | } | |
397 | ||
7d12e780 | 398 | static irqreturn_t imx_txint(int irq, void *dev_id) |
1da177e4 | 399 | { |
15aafa2f | 400 | struct imx_port *sport = dev_id; |
ebd2c8f6 | 401 | struct circ_buf *xmit = &sport->port.state->xmit; |
1da177e4 LT |
402 | unsigned long flags; |
403 | ||
404 | spin_lock_irqsave(&sport->port.lock,flags); | |
405 | if (sport->port.x_char) | |
406 | { | |
407 | /* Send next char */ | |
ff4bfb21 | 408 | writel(sport->port.x_char, sport->port.membase + URTX0); |
1da177e4 LT |
409 | goto out; |
410 | } | |
411 | ||
412 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
b129a8cc | 413 | imx_stop_tx(&sport->port); |
1da177e4 LT |
414 | goto out; |
415 | } | |
416 | ||
417 | imx_transmit_buffer(sport); | |
418 | ||
419 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
420 | uart_write_wakeup(&sport->port); | |
421 | ||
422 | out: | |
423 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
424 | return IRQ_HANDLED; | |
425 | } | |
426 | ||
7d12e780 | 427 | static irqreturn_t imx_rxint(int irq, void *dev_id) |
1da177e4 LT |
428 | { |
429 | struct imx_port *sport = dev_id; | |
430 | unsigned int rx,flg,ignored = 0; | |
ebd2c8f6 | 431 | struct tty_struct *tty = sport->port.state->port.tty; |
ff4bfb21 | 432 | unsigned long flags, temp; |
1da177e4 | 433 | |
1da177e4 LT |
434 | spin_lock_irqsave(&sport->port.lock,flags); |
435 | ||
0d3c3938 | 436 | while (readl(sport->port.membase + USR2) & USR2_RDR) { |
1da177e4 LT |
437 | flg = TTY_NORMAL; |
438 | sport->port.icount.rx++; | |
439 | ||
0d3c3938 SH |
440 | rx = readl(sport->port.membase + URXD0); |
441 | ||
ff4bfb21 | 442 | temp = readl(sport->port.membase + USR2); |
864eeed0 | 443 | if (temp & USR2_BRCD) { |
94d32f99 | 444 | writel(USR2_BRCD, sport->port.membase + USR2); |
864eeed0 SH |
445 | if (uart_handle_break(&sport->port)) |
446 | continue; | |
1da177e4 LT |
447 | } |
448 | ||
d3810cd4 | 449 | if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) |
864eeed0 SH |
450 | continue; |
451 | ||
452 | if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) { | |
453 | if (rx & URXD_PRERR) | |
454 | sport->port.icount.parity++; | |
455 | else if (rx & URXD_FRMERR) | |
456 | sport->port.icount.frame++; | |
457 | if (rx & URXD_OVRRUN) | |
458 | sport->port.icount.overrun++; | |
459 | ||
460 | if (rx & sport->port.ignore_status_mask) { | |
461 | if (++ignored > 100) | |
462 | goto out; | |
463 | continue; | |
464 | } | |
465 | ||
466 | rx &= sport->port.read_status_mask; | |
467 | ||
468 | if (rx & URXD_PRERR) | |
469 | flg = TTY_PARITY; | |
470 | else if (rx & URXD_FRMERR) | |
471 | flg = TTY_FRAME; | |
472 | if (rx & URXD_OVRRUN) | |
473 | flg = TTY_OVERRUN; | |
1da177e4 | 474 | |
864eeed0 SH |
475 | #ifdef SUPPORT_SYSRQ |
476 | sport->port.sysrq = 0; | |
477 | #endif | |
478 | } | |
1da177e4 | 479 | |
1da177e4 | 480 | tty_insert_flip_char(tty, rx, flg); |
864eeed0 | 481 | } |
1da177e4 LT |
482 | |
483 | out: | |
484 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
485 | tty_flip_buffer_push(tty); | |
486 | return IRQ_HANDLED; | |
1da177e4 LT |
487 | } |
488 | ||
e3d13ff4 SH |
489 | static irqreturn_t imx_int(int irq, void *dev_id) |
490 | { | |
491 | struct imx_port *sport = dev_id; | |
492 | unsigned int sts; | |
493 | ||
494 | sts = readl(sport->port.membase + USR1); | |
495 | ||
496 | if (sts & USR1_RRDY) | |
497 | imx_rxint(irq, dev_id); | |
498 | ||
499 | if (sts & USR1_TRDY && | |
500 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) | |
501 | imx_txint(irq, dev_id); | |
502 | ||
9fbe6044 | 503 | if (sts & USR1_RTSD) |
e3d13ff4 SH |
504 | imx_rtsint(irq, dev_id); |
505 | ||
506 | return IRQ_HANDLED; | |
507 | } | |
508 | ||
1da177e4 LT |
509 | /* |
510 | * Return TIOCSER_TEMT when transmitter is not busy. | |
511 | */ | |
512 | static unsigned int imx_tx_empty(struct uart_port *port) | |
513 | { | |
514 | struct imx_port *sport = (struct imx_port *)port; | |
515 | ||
ff4bfb21 | 516 | return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; |
1da177e4 LT |
517 | } |
518 | ||
0f302dc3 SH |
519 | /* |
520 | * We have a modem side uart, so the meanings of RTS and CTS are inverted. | |
521 | */ | |
1da177e4 LT |
522 | static unsigned int imx_get_mctrl(struct uart_port *port) |
523 | { | |
d3810cd4 OS |
524 | struct imx_port *sport = (struct imx_port *)port; |
525 | unsigned int tmp = TIOCM_DSR | TIOCM_CAR; | |
0f302dc3 | 526 | |
d3810cd4 OS |
527 | if (readl(sport->port.membase + USR1) & USR1_RTSS) |
528 | tmp |= TIOCM_CTS; | |
0f302dc3 | 529 | |
d3810cd4 OS |
530 | if (readl(sport->port.membase + UCR2) & UCR2_CTS) |
531 | tmp |= TIOCM_RTS; | |
0f302dc3 | 532 | |
d3810cd4 | 533 | return tmp; |
1da177e4 LT |
534 | } |
535 | ||
536 | static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
537 | { | |
d3810cd4 | 538 | struct imx_port *sport = (struct imx_port *)port; |
ff4bfb21 SH |
539 | unsigned long temp; |
540 | ||
541 | temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; | |
0f302dc3 | 542 | |
d3810cd4 | 543 | if (mctrl & TIOCM_RTS) |
ff4bfb21 SH |
544 | temp |= UCR2_CTS; |
545 | ||
546 | writel(temp, sport->port.membase + UCR2); | |
1da177e4 LT |
547 | } |
548 | ||
549 | /* | |
550 | * Interrupts always disabled. | |
551 | */ | |
552 | static void imx_break_ctl(struct uart_port *port, int break_state) | |
553 | { | |
554 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 555 | unsigned long flags, temp; |
1da177e4 LT |
556 | |
557 | spin_lock_irqsave(&sport->port.lock, flags); | |
558 | ||
ff4bfb21 SH |
559 | temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; |
560 | ||
1da177e4 | 561 | if ( break_state != 0 ) |
ff4bfb21 SH |
562 | temp |= UCR1_SNDBRK; |
563 | ||
564 | writel(temp, sport->port.membase + UCR1); | |
1da177e4 LT |
565 | |
566 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
567 | } | |
568 | ||
569 | #define TXTL 2 /* reset default */ | |
570 | #define RXTL 1 /* reset default */ | |
571 | ||
587897f5 SH |
572 | static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) |
573 | { | |
574 | unsigned int val; | |
575 | unsigned int ufcr_rfdiv; | |
576 | ||
577 | /* set receiver / transmitter trigger level. | |
578 | * RFDIV is set such way to satisfy requested uartclk value | |
579 | */ | |
ff4bfb21 | 580 | val = TXTL << 10 | RXTL; |
38a41fdf SH |
581 | ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2) |
582 | / sport->port.uartclk; | |
587897f5 SH |
583 | |
584 | if(!ufcr_rfdiv) | |
585 | ufcr_rfdiv = 1; | |
586 | ||
b6e49138 | 587 | val |= UFCR_RFDIV_REG(ufcr_rfdiv); |
587897f5 | 588 | |
ff4bfb21 | 589 | writel(val, sport->port.membase + UFCR); |
587897f5 SH |
590 | |
591 | return 0; | |
592 | } | |
593 | ||
1da177e4 LT |
594 | static int imx_startup(struct uart_port *port) |
595 | { | |
596 | struct imx_port *sport = (struct imx_port *)port; | |
597 | int retval; | |
ff4bfb21 | 598 | unsigned long flags, temp; |
1da177e4 | 599 | |
587897f5 | 600 | imx_setup_ufcr(sport, 0); |
1da177e4 LT |
601 | |
602 | /* disable the DREN bit (Data Ready interrupt enable) before | |
603 | * requesting IRQs | |
604 | */ | |
ff4bfb21 | 605 | temp = readl(sport->port.membase + UCR4); |
b6e49138 FG |
606 | |
607 | if (USE_IRDA(sport)) | |
608 | temp |= UCR4_IRSC; | |
609 | ||
ff4bfb21 | 610 | writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); |
1da177e4 | 611 | |
b6e49138 FG |
612 | if (USE_IRDA(sport)) { |
613 | /* reset fifo's and state machines */ | |
614 | int i = 100; | |
615 | temp = readl(sport->port.membase + UCR2); | |
616 | temp &= ~UCR2_SRST; | |
617 | writel(temp, sport->port.membase + UCR2); | |
618 | while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && | |
619 | (--i > 0)) { | |
620 | udelay(1); | |
621 | } | |
622 | } | |
623 | ||
1da177e4 | 624 | /* |
e3d13ff4 SH |
625 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later |
626 | * chips only have one interrupt. | |
1da177e4 | 627 | */ |
e3d13ff4 SH |
628 | if (sport->txirq > 0) { |
629 | retval = request_irq(sport->rxirq, imx_rxint, 0, | |
630 | DRIVER_NAME, sport); | |
631 | if (retval) | |
632 | goto error_out1; | |
633 | ||
634 | retval = request_irq(sport->txirq, imx_txint, 0, | |
635 | DRIVER_NAME, sport); | |
636 | if (retval) | |
637 | goto error_out2; | |
638 | ||
b6e49138 FG |
639 | /* do not use RTS IRQ on IrDA */ |
640 | if (!USE_IRDA(sport)) { | |
641 | retval = request_irq(sport->rtsirq, imx_rtsint, | |
642 | (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : | |
643 | IRQF_TRIGGER_FALLING | | |
644 | IRQF_TRIGGER_RISING, | |
645 | DRIVER_NAME, sport); | |
646 | if (retval) | |
647 | goto error_out3; | |
648 | } | |
e3d13ff4 SH |
649 | } else { |
650 | retval = request_irq(sport->port.irq, imx_int, 0, | |
651 | DRIVER_NAME, sport); | |
652 | if (retval) { | |
653 | free_irq(sport->port.irq, sport); | |
654 | goto error_out1; | |
655 | } | |
656 | } | |
ceca629e | 657 | |
1da177e4 LT |
658 | /* |
659 | * Finally, clear and enable interrupts | |
660 | */ | |
ff4bfb21 SH |
661 | writel(USR1_RTSD, sport->port.membase + USR1); |
662 | ||
663 | temp = readl(sport->port.membase + UCR1); | |
789d5258 | 664 | temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; |
b6e49138 FG |
665 | |
666 | if (USE_IRDA(sport)) { | |
667 | temp |= UCR1_IREN; | |
668 | temp &= ~(UCR1_RTSDEN); | |
669 | } | |
670 | ||
ff4bfb21 | 671 | writel(temp, sport->port.membase + UCR1); |
1da177e4 | 672 | |
ff4bfb21 SH |
673 | temp = readl(sport->port.membase + UCR2); |
674 | temp |= (UCR2_RXEN | UCR2_TXEN); | |
675 | writel(temp, sport->port.membase + UCR2); | |
1da177e4 | 676 | |
b6e49138 FG |
677 | if (USE_IRDA(sport)) { |
678 | /* clear RX-FIFO */ | |
679 | int i = 64; | |
680 | while ((--i > 0) && | |
681 | (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { | |
682 | barrier(); | |
683 | } | |
684 | } | |
685 | ||
37d6fb62 SH |
686 | if (!cpu_is_mx1()) { |
687 | temp = readl(sport->port.membase + UCR3); | |
688 | temp |= MX2_UCR3_RXDMUXSEL; | |
689 | writel(temp, sport->port.membase + UCR3); | |
690 | } | |
4411805b | 691 | |
b6e49138 FG |
692 | if (USE_IRDA(sport)) { |
693 | temp = readl(sport->port.membase + UCR4); | |
694 | if (sport->irda_inv_rx) | |
695 | temp |= UCR4_INVR; | |
696 | else | |
697 | temp &= ~(UCR4_INVR); | |
698 | writel(temp | UCR4_DREN, sport->port.membase + UCR4); | |
699 | ||
700 | temp = readl(sport->port.membase + UCR3); | |
701 | if (sport->irda_inv_tx) | |
702 | temp |= UCR3_INVT; | |
703 | else | |
704 | temp &= ~(UCR3_INVT); | |
705 | writel(temp, sport->port.membase + UCR3); | |
706 | } | |
707 | ||
1da177e4 LT |
708 | /* |
709 | * Enable modem status interrupts | |
710 | */ | |
711 | spin_lock_irqsave(&sport->port.lock,flags); | |
712 | imx_enable_ms(&sport->port); | |
713 | spin_unlock_irqrestore(&sport->port.lock,flags); | |
714 | ||
b6e49138 FG |
715 | if (USE_IRDA(sport)) { |
716 | struct imxuart_platform_data *pdata; | |
717 | pdata = sport->port.dev->platform_data; | |
718 | sport->irda_inv_rx = pdata->irda_inv_rx; | |
719 | sport->irda_inv_tx = pdata->irda_inv_tx; | |
720 | sport->trcv_delay = pdata->transceiver_delay; | |
721 | if (pdata->irda_enable) | |
722 | pdata->irda_enable(1); | |
723 | } | |
724 | ||
1da177e4 LT |
725 | return 0; |
726 | ||
ceca629e | 727 | error_out3: |
e3d13ff4 SH |
728 | if (sport->txirq) |
729 | free_irq(sport->txirq, sport); | |
1da177e4 | 730 | error_out2: |
e3d13ff4 SH |
731 | if (sport->rxirq) |
732 | free_irq(sport->rxirq, sport); | |
86371d07 | 733 | error_out1: |
1da177e4 LT |
734 | return retval; |
735 | } | |
736 | ||
737 | static void imx_shutdown(struct uart_port *port) | |
738 | { | |
739 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 740 | unsigned long temp; |
1da177e4 | 741 | |
2e146392 FG |
742 | temp = readl(sport->port.membase + UCR2); |
743 | temp &= ~(UCR2_TXEN); | |
744 | writel(temp, sport->port.membase + UCR2); | |
745 | ||
b6e49138 FG |
746 | if (USE_IRDA(sport)) { |
747 | struct imxuart_platform_data *pdata; | |
748 | pdata = sport->port.dev->platform_data; | |
749 | if (pdata->irda_enable) | |
750 | pdata->irda_enable(0); | |
751 | } | |
752 | ||
1da177e4 LT |
753 | /* |
754 | * Stop our timer. | |
755 | */ | |
756 | del_timer_sync(&sport->timer); | |
757 | ||
758 | /* | |
759 | * Free the interrupts | |
760 | */ | |
e3d13ff4 | 761 | if (sport->txirq > 0) { |
b6e49138 FG |
762 | if (!USE_IRDA(sport)) |
763 | free_irq(sport->rtsirq, sport); | |
e3d13ff4 SH |
764 | free_irq(sport->txirq, sport); |
765 | free_irq(sport->rxirq, sport); | |
766 | } else | |
767 | free_irq(sport->port.irq, sport); | |
1da177e4 LT |
768 | |
769 | /* | |
770 | * Disable all interrupts, port and break condition. | |
771 | */ | |
772 | ||
ff4bfb21 SH |
773 | temp = readl(sport->port.membase + UCR1); |
774 | temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); | |
b6e49138 FG |
775 | if (USE_IRDA(sport)) |
776 | temp &= ~(UCR1_IREN); | |
777 | ||
ff4bfb21 | 778 | writel(temp, sport->port.membase + UCR1); |
1da177e4 LT |
779 | } |
780 | ||
781 | static void | |
606d099c AC |
782 | imx_set_termios(struct uart_port *port, struct ktermios *termios, |
783 | struct ktermios *old) | |
1da177e4 LT |
784 | { |
785 | struct imx_port *sport = (struct imx_port *)port; | |
786 | unsigned long flags; | |
787 | unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; | |
788 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
534fca06 OS |
789 | unsigned int div, ufcr; |
790 | unsigned long num, denom; | |
d7f8d437 | 791 | uint64_t tdiv64; |
1da177e4 LT |
792 | |
793 | /* | |
794 | * If we don't support modem control lines, don't allow | |
795 | * these to be set. | |
796 | */ | |
797 | if (0) { | |
798 | termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); | |
799 | termios->c_cflag |= CLOCAL; | |
800 | } | |
801 | ||
802 | /* | |
803 | * We only support CS7 and CS8. | |
804 | */ | |
805 | while ((termios->c_cflag & CSIZE) != CS7 && | |
806 | (termios->c_cflag & CSIZE) != CS8) { | |
807 | termios->c_cflag &= ~CSIZE; | |
808 | termios->c_cflag |= old_csize; | |
809 | old_csize = CS8; | |
810 | } | |
811 | ||
812 | if ((termios->c_cflag & CSIZE) == CS8) | |
813 | ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; | |
814 | else | |
815 | ucr2 = UCR2_SRST | UCR2_IRTS; | |
816 | ||
817 | if (termios->c_cflag & CRTSCTS) { | |
5b802344 SH |
818 | if( sport->have_rtscts ) { |
819 | ucr2 &= ~UCR2_IRTS; | |
820 | ucr2 |= UCR2_CTSC; | |
821 | } else { | |
822 | termios->c_cflag &= ~CRTSCTS; | |
823 | } | |
1da177e4 LT |
824 | } |
825 | ||
826 | if (termios->c_cflag & CSTOPB) | |
827 | ucr2 |= UCR2_STPB; | |
828 | if (termios->c_cflag & PARENB) { | |
829 | ucr2 |= UCR2_PREN; | |
3261e362 | 830 | if (termios->c_cflag & PARODD) |
1da177e4 LT |
831 | ucr2 |= UCR2_PROE; |
832 | } | |
833 | ||
834 | /* | |
835 | * Ask the core to calculate the divisor for us. | |
836 | */ | |
036bb15e | 837 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); |
1da177e4 LT |
838 | quot = uart_get_divisor(port, baud); |
839 | ||
840 | spin_lock_irqsave(&sport->port.lock, flags); | |
841 | ||
842 | sport->port.read_status_mask = 0; | |
843 | if (termios->c_iflag & INPCK) | |
844 | sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); | |
845 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
846 | sport->port.read_status_mask |= URXD_BRK; | |
847 | ||
848 | /* | |
849 | * Characters to ignore | |
850 | */ | |
851 | sport->port.ignore_status_mask = 0; | |
852 | if (termios->c_iflag & IGNPAR) | |
853 | sport->port.ignore_status_mask |= URXD_PRERR; | |
854 | if (termios->c_iflag & IGNBRK) { | |
855 | sport->port.ignore_status_mask |= URXD_BRK; | |
856 | /* | |
857 | * If we're ignoring parity and break indicators, | |
858 | * ignore overruns too (for real raw support). | |
859 | */ | |
860 | if (termios->c_iflag & IGNPAR) | |
861 | sport->port.ignore_status_mask |= URXD_OVRRUN; | |
862 | } | |
863 | ||
864 | del_timer_sync(&sport->timer); | |
865 | ||
866 | /* | |
867 | * Update the per-port timeout. | |
868 | */ | |
869 | uart_update_timeout(port, termios->c_cflag, baud); | |
870 | ||
871 | /* | |
872 | * disable interrupts and drain transmitter | |
873 | */ | |
ff4bfb21 SH |
874 | old_ucr1 = readl(sport->port.membase + UCR1); |
875 | writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), | |
876 | sport->port.membase + UCR1); | |
1da177e4 | 877 | |
ff4bfb21 | 878 | while ( !(readl(sport->port.membase + USR2) & USR2_TXDC)) |
1da177e4 LT |
879 | barrier(); |
880 | ||
881 | /* then, disable everything */ | |
ff4bfb21 SH |
882 | old_txrxen = readl(sport->port.membase + UCR2); |
883 | writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN), | |
884 | sport->port.membase + UCR2); | |
885 | old_txrxen &= (UCR2_TXEN | UCR2_RXEN); | |
1da177e4 | 886 | |
b6e49138 FG |
887 | if (USE_IRDA(sport)) { |
888 | /* | |
889 | * use maximum available submodule frequency to | |
890 | * avoid missing short pulses due to low sampling rate | |
891 | */ | |
036bb15e | 892 | div = 1; |
b6e49138 FG |
893 | } else { |
894 | div = sport->port.uartclk / (baud * 16); | |
895 | if (div > 7) | |
896 | div = 7; | |
897 | if (!div) | |
898 | div = 1; | |
899 | } | |
036bb15e | 900 | |
534fca06 OS |
901 | rational_best_approximation(16 * div * baud, sport->port.uartclk, |
902 | 1 << 16, 1 << 16, &num, &denom); | |
036bb15e | 903 | |
ebd2c8f6 | 904 | if (port->state && port->state->port.tty) { |
1a2c4b31 SH |
905 | tdiv64 = sport->port.uartclk; |
906 | tdiv64 *= num; | |
907 | do_div(tdiv64, denom * 16 * div); | |
ebd2c8f6 | 908 | tty_encode_baud_rate(sport->port.state->port.tty, |
1a2c4b31 SH |
909 | (speed_t)tdiv64, (speed_t)tdiv64); |
910 | } | |
d7f8d437 | 911 | |
534fca06 OS |
912 | num -= 1; |
913 | denom -= 1; | |
036bb15e SH |
914 | |
915 | ufcr = readl(sport->port.membase + UFCR); | |
b6e49138 | 916 | ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); |
036bb15e SH |
917 | writel(ufcr, sport->port.membase + UFCR); |
918 | ||
534fca06 OS |
919 | writel(num, sport->port.membase + UBIR); |
920 | writel(denom, sport->port.membase + UBMR); | |
921 | ||
37d6fb62 SH |
922 | if (!cpu_is_mx1()) |
923 | writel(sport->port.uartclk / div / 1000, | |
924 | sport->port.membase + MX2_ONEMS); | |
ff4bfb21 SH |
925 | |
926 | writel(old_ucr1, sport->port.membase + UCR1); | |
1da177e4 | 927 | |
ff4bfb21 SH |
928 | /* set the parity, stop bits and data size */ |
929 | writel(ucr2 | old_txrxen, sport->port.membase + UCR2); | |
1da177e4 LT |
930 | |
931 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | |
932 | imx_enable_ms(&sport->port); | |
933 | ||
934 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
935 | } | |
936 | ||
937 | static const char *imx_type(struct uart_port *port) | |
938 | { | |
939 | struct imx_port *sport = (struct imx_port *)port; | |
940 | ||
941 | return sport->port.type == PORT_IMX ? "IMX" : NULL; | |
942 | } | |
943 | ||
944 | /* | |
945 | * Release the memory region(s) being used by 'port'. | |
946 | */ | |
947 | static void imx_release_port(struct uart_port *port) | |
948 | { | |
3d454446 SH |
949 | struct platform_device *pdev = to_platform_device(port->dev); |
950 | struct resource *mmres; | |
1da177e4 | 951 | |
3d454446 SH |
952 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
953 | release_mem_region(mmres->start, mmres->end - mmres->start + 1); | |
1da177e4 LT |
954 | } |
955 | ||
956 | /* | |
957 | * Request the memory region(s) being used by 'port'. | |
958 | */ | |
959 | static int imx_request_port(struct uart_port *port) | |
960 | { | |
3d454446 SH |
961 | struct platform_device *pdev = to_platform_device(port->dev); |
962 | struct resource *mmres; | |
963 | void *ret; | |
964 | ||
965 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
966 | if (!mmres) | |
967 | return -ENODEV; | |
968 | ||
969 | ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1, | |
970 | "imx-uart"); | |
1da177e4 | 971 | |
3d454446 | 972 | return ret ? 0 : -EBUSY; |
1da177e4 LT |
973 | } |
974 | ||
975 | /* | |
976 | * Configure/autoconfigure the port. | |
977 | */ | |
978 | static void imx_config_port(struct uart_port *port, int flags) | |
979 | { | |
980 | struct imx_port *sport = (struct imx_port *)port; | |
981 | ||
982 | if (flags & UART_CONFIG_TYPE && | |
983 | imx_request_port(&sport->port) == 0) | |
984 | sport->port.type = PORT_IMX; | |
985 | } | |
986 | ||
987 | /* | |
988 | * Verify the new serial_struct (for TIOCSSERIAL). | |
989 | * The only change we allow are to the flags and type, and | |
990 | * even then only between PORT_IMX and PORT_UNKNOWN | |
991 | */ | |
992 | static int | |
993 | imx_verify_port(struct uart_port *port, struct serial_struct *ser) | |
994 | { | |
995 | struct imx_port *sport = (struct imx_port *)port; | |
996 | int ret = 0; | |
997 | ||
998 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) | |
999 | ret = -EINVAL; | |
1000 | if (sport->port.irq != ser->irq) | |
1001 | ret = -EINVAL; | |
1002 | if (ser->io_type != UPIO_MEM) | |
1003 | ret = -EINVAL; | |
1004 | if (sport->port.uartclk / 16 != ser->baud_base) | |
1005 | ret = -EINVAL; | |
1006 | if ((void *)sport->port.mapbase != ser->iomem_base) | |
1007 | ret = -EINVAL; | |
1008 | if (sport->port.iobase != ser->port) | |
1009 | ret = -EINVAL; | |
1010 | if (ser->hub6 != 0) | |
1011 | ret = -EINVAL; | |
1012 | return ret; | |
1013 | } | |
1014 | ||
1015 | static struct uart_ops imx_pops = { | |
1016 | .tx_empty = imx_tx_empty, | |
1017 | .set_mctrl = imx_set_mctrl, | |
1018 | .get_mctrl = imx_get_mctrl, | |
1019 | .stop_tx = imx_stop_tx, | |
1020 | .start_tx = imx_start_tx, | |
1021 | .stop_rx = imx_stop_rx, | |
1022 | .enable_ms = imx_enable_ms, | |
1023 | .break_ctl = imx_break_ctl, | |
1024 | .startup = imx_startup, | |
1025 | .shutdown = imx_shutdown, | |
1026 | .set_termios = imx_set_termios, | |
1027 | .type = imx_type, | |
1028 | .release_port = imx_release_port, | |
1029 | .request_port = imx_request_port, | |
1030 | .config_port = imx_config_port, | |
1031 | .verify_port = imx_verify_port, | |
1032 | }; | |
1033 | ||
dbff4e9e | 1034 | static struct imx_port *imx_ports[UART_NR]; |
1da177e4 LT |
1035 | |
1036 | #ifdef CONFIG_SERIAL_IMX_CONSOLE | |
d358788f RK |
1037 | static void imx_console_putchar(struct uart_port *port, int ch) |
1038 | { | |
1039 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
1040 | |
1041 | while (readl(sport->port.membase + UTS) & UTS_TXFULL) | |
d358788f | 1042 | barrier(); |
ff4bfb21 SH |
1043 | |
1044 | writel(ch, sport->port.membase + URTX0); | |
d358788f | 1045 | } |
1da177e4 LT |
1046 | |
1047 | /* | |
1048 | * Interrupts are disabled on entering | |
1049 | */ | |
1050 | static void | |
1051 | imx_console_write(struct console *co, const char *s, unsigned int count) | |
1052 | { | |
dbff4e9e | 1053 | struct imx_port *sport = imx_ports[co->index]; |
37d6fb62 | 1054 | unsigned int old_ucr1, old_ucr2, ucr1; |
1da177e4 LT |
1055 | |
1056 | /* | |
1057 | * First, save UCR1/2 and then disable interrupts | |
1058 | */ | |
37d6fb62 | 1059 | ucr1 = old_ucr1 = readl(sport->port.membase + UCR1); |
ff4bfb21 | 1060 | old_ucr2 = readl(sport->port.membase + UCR2); |
1da177e4 | 1061 | |
37d6fb62 SH |
1062 | if (cpu_is_mx1()) |
1063 | ucr1 |= MX1_UCR1_UARTCLKEN; | |
1064 | ucr1 |= UCR1_UARTEN; | |
1065 | ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); | |
1066 | ||
1067 | writel(ucr1, sport->port.membase + UCR1); | |
ff4bfb21 SH |
1068 | |
1069 | writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2); | |
1da177e4 | 1070 | |
d358788f | 1071 | uart_console_write(&sport->port, s, count, imx_console_putchar); |
1da177e4 LT |
1072 | |
1073 | /* | |
1074 | * Finally, wait for transmitter to become empty | |
1075 | * and restore UCR1/2 | |
1076 | */ | |
ff4bfb21 | 1077 | while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); |
1da177e4 | 1078 | |
ff4bfb21 SH |
1079 | writel(old_ucr1, sport->port.membase + UCR1); |
1080 | writel(old_ucr2, sport->port.membase + UCR2); | |
1da177e4 LT |
1081 | } |
1082 | ||
1083 | /* | |
1084 | * If the port was already initialised (eg, by a boot loader), | |
1085 | * try to determine the current setup. | |
1086 | */ | |
1087 | static void __init | |
1088 | imx_console_get_options(struct imx_port *sport, int *baud, | |
1089 | int *parity, int *bits) | |
1090 | { | |
587897f5 | 1091 | |
2e2eb509 | 1092 | if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { |
1da177e4 LT |
1093 | /* ok, the port was enabled */ |
1094 | unsigned int ucr2, ubir,ubmr, uartclk; | |
587897f5 SH |
1095 | unsigned int baud_raw; |
1096 | unsigned int ucfr_rfdiv; | |
1da177e4 | 1097 | |
ff4bfb21 | 1098 | ucr2 = readl(sport->port.membase + UCR2); |
1da177e4 LT |
1099 | |
1100 | *parity = 'n'; | |
1101 | if (ucr2 & UCR2_PREN) { | |
1102 | if (ucr2 & UCR2_PROE) | |
1103 | *parity = 'o'; | |
1104 | else | |
1105 | *parity = 'e'; | |
1106 | } | |
1107 | ||
1108 | if (ucr2 & UCR2_WS) | |
1109 | *bits = 8; | |
1110 | else | |
1111 | *bits = 7; | |
1112 | ||
ff4bfb21 SH |
1113 | ubir = readl(sport->port.membase + UBIR) & 0xffff; |
1114 | ubmr = readl(sport->port.membase + UBMR) & 0xffff; | |
587897f5 | 1115 | |
ff4bfb21 | 1116 | ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; |
587897f5 SH |
1117 | if (ucfr_rfdiv == 6) |
1118 | ucfr_rfdiv = 7; | |
1119 | else | |
1120 | ucfr_rfdiv = 6 - ucfr_rfdiv; | |
1121 | ||
38a41fdf | 1122 | uartclk = clk_get_rate(sport->clk); |
587897f5 SH |
1123 | uartclk /= ucfr_rfdiv; |
1124 | ||
1125 | { /* | |
1126 | * The next code provides exact computation of | |
1127 | * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) | |
1128 | * without need of float support or long long division, | |
1129 | * which would be required to prevent 32bit arithmetic overflow | |
1130 | */ | |
1131 | unsigned int mul = ubir + 1; | |
1132 | unsigned int div = 16 * (ubmr + 1); | |
1133 | unsigned int rem = uartclk % div; | |
1134 | ||
1135 | baud_raw = (uartclk / div) * mul; | |
1136 | baud_raw += (rem * mul + div / 2) / div; | |
1137 | *baud = (baud_raw + 50) / 100 * 100; | |
1138 | } | |
1139 | ||
1140 | if(*baud != baud_raw) | |
1141 | printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n", | |
1142 | baud_raw, *baud); | |
1da177e4 LT |
1143 | } |
1144 | } | |
1145 | ||
1146 | static int __init | |
1147 | imx_console_setup(struct console *co, char *options) | |
1148 | { | |
1149 | struct imx_port *sport; | |
1150 | int baud = 9600; | |
1151 | int bits = 8; | |
1152 | int parity = 'n'; | |
1153 | int flow = 'n'; | |
1154 | ||
1155 | /* | |
1156 | * Check whether an invalid uart number has been specified, and | |
1157 | * if so, search for the first available port that does have | |
1158 | * console support. | |
1159 | */ | |
1160 | if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) | |
1161 | co->index = 0; | |
dbff4e9e | 1162 | sport = imx_ports[co->index]; |
e76afc4e EL |
1163 | if(sport == NULL) |
1164 | return -ENODEV; | |
1da177e4 LT |
1165 | |
1166 | if (options) | |
1167 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1168 | else | |
1169 | imx_console_get_options(sport, &baud, &parity, &bits); | |
1170 | ||
587897f5 SH |
1171 | imx_setup_ufcr(sport, 0); |
1172 | ||
1da177e4 LT |
1173 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); |
1174 | } | |
1175 | ||
9f4426dd | 1176 | static struct uart_driver imx_reg; |
1da177e4 | 1177 | static struct console imx_console = { |
e3d13ff4 | 1178 | .name = DEV_NAME, |
1da177e4 LT |
1179 | .write = imx_console_write, |
1180 | .device = uart_console_device, | |
1181 | .setup = imx_console_setup, | |
1182 | .flags = CON_PRINTBUFFER, | |
1183 | .index = -1, | |
1184 | .data = &imx_reg, | |
1185 | }; | |
1186 | ||
1da177e4 LT |
1187 | #define IMX_CONSOLE &imx_console |
1188 | #else | |
1189 | #define IMX_CONSOLE NULL | |
1190 | #endif | |
1191 | ||
1192 | static struct uart_driver imx_reg = { | |
1193 | .owner = THIS_MODULE, | |
1194 | .driver_name = DRIVER_NAME, | |
e3d13ff4 | 1195 | .dev_name = DEV_NAME, |
1da177e4 LT |
1196 | .major = SERIAL_IMX_MAJOR, |
1197 | .minor = MINOR_START, | |
1198 | .nr = ARRAY_SIZE(imx_ports), | |
1199 | .cons = IMX_CONSOLE, | |
1200 | }; | |
1201 | ||
3ae5eaec | 1202 | static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1203 | { |
d3810cd4 | 1204 | struct imx_port *sport = platform_get_drvdata(dev); |
1da177e4 | 1205 | |
d3810cd4 OS |
1206 | if (sport) |
1207 | uart_suspend_port(&imx_reg, &sport->port); | |
1da177e4 | 1208 | |
d3810cd4 | 1209 | return 0; |
1da177e4 LT |
1210 | } |
1211 | ||
3ae5eaec | 1212 | static int serial_imx_resume(struct platform_device *dev) |
1da177e4 | 1213 | { |
d3810cd4 | 1214 | struct imx_port *sport = platform_get_drvdata(dev); |
1da177e4 | 1215 | |
d3810cd4 OS |
1216 | if (sport) |
1217 | uart_resume_port(&imx_reg, &sport->port); | |
1da177e4 | 1218 | |
d3810cd4 | 1219 | return 0; |
1da177e4 LT |
1220 | } |
1221 | ||
2582d8c1 | 1222 | static int serial_imx_probe(struct platform_device *pdev) |
1da177e4 | 1223 | { |
dbff4e9e | 1224 | struct imx_port *sport; |
5b802344 | 1225 | struct imxuart_platform_data *pdata; |
dbff4e9e SH |
1226 | void __iomem *base; |
1227 | int ret = 0; | |
1228 | struct resource *res; | |
1229 | ||
1230 | sport = kzalloc(sizeof(*sport), GFP_KERNEL); | |
1231 | if (!sport) | |
1232 | return -ENOMEM; | |
5b802344 | 1233 | |
dbff4e9e SH |
1234 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1235 | if (!res) { | |
1236 | ret = -ENODEV; | |
1237 | goto free; | |
1238 | } | |
1239 | ||
1240 | base = ioremap(res->start, PAGE_SIZE); | |
1241 | if (!base) { | |
1242 | ret = -ENOMEM; | |
1243 | goto free; | |
1244 | } | |
1245 | ||
1246 | sport->port.dev = &pdev->dev; | |
1247 | sport->port.mapbase = res->start; | |
1248 | sport->port.membase = base; | |
1249 | sport->port.type = PORT_IMX, | |
1250 | sport->port.iotype = UPIO_MEM; | |
1251 | sport->port.irq = platform_get_irq(pdev, 0); | |
1252 | sport->rxirq = platform_get_irq(pdev, 0); | |
1253 | sport->txirq = platform_get_irq(pdev, 1); | |
1254 | sport->rtsirq = platform_get_irq(pdev, 2); | |
1255 | sport->port.fifosize = 32; | |
1256 | sport->port.ops = &imx_pops; | |
1257 | sport->port.flags = UPF_BOOT_AUTOCONF; | |
1258 | sport->port.line = pdev->id; | |
1259 | init_timer(&sport->timer); | |
1260 | sport->timer.function = imx_timeout; | |
1261 | sport->timer.data = (unsigned long)sport; | |
38a41fdf | 1262 | |
e65fb009 | 1263 | sport->clk = clk_get(&pdev->dev, "uart"); |
38a41fdf SH |
1264 | if (IS_ERR(sport->clk)) { |
1265 | ret = PTR_ERR(sport->clk); | |
1266 | goto unmap; | |
1267 | } | |
1268 | clk_enable(sport->clk); | |
1269 | ||
1270 | sport->port.uartclk = clk_get_rate(sport->clk); | |
dbff4e9e SH |
1271 | |
1272 | imx_ports[pdev->id] = sport; | |
5b802344 | 1273 | |
2582d8c1 | 1274 | pdata = pdev->dev.platform_data; |
d3810cd4 | 1275 | if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) |
dbff4e9e | 1276 | sport->have_rtscts = 1; |
2582d8c1 | 1277 | |
b6e49138 FG |
1278 | #ifdef CONFIG_IRDA |
1279 | if (pdata && (pdata->flags & IMXUART_IRDA)) | |
1280 | sport->use_irda = 1; | |
1281 | #endif | |
1282 | ||
bbcd18d1 | 1283 | if (pdata && pdata->init) { |
c45e7d7b DA |
1284 | ret = pdata->init(pdev); |
1285 | if (ret) | |
1286 | goto clkput; | |
1287 | } | |
2582d8c1 | 1288 | |
9f322ad0 DG |
1289 | ret = uart_add_one_port(&imx_reg, &sport->port); |
1290 | if (ret) | |
1291 | goto deinit; | |
dbff4e9e | 1292 | platform_set_drvdata(pdev, &sport->port); |
5b802344 | 1293 | |
1da177e4 | 1294 | return 0; |
9f322ad0 | 1295 | deinit: |
bbcd18d1 | 1296 | if (pdata && pdata->exit) |
9f322ad0 | 1297 | pdata->exit(pdev); |
c45e7d7b DA |
1298 | clkput: |
1299 | clk_put(sport->clk); | |
1300 | clk_disable(sport->clk); | |
38a41fdf SH |
1301 | unmap: |
1302 | iounmap(sport->port.membase); | |
dbff4e9e SH |
1303 | free: |
1304 | kfree(sport); | |
1305 | ||
1306 | return ret; | |
1da177e4 LT |
1307 | } |
1308 | ||
2582d8c1 | 1309 | static int serial_imx_remove(struct platform_device *pdev) |
1da177e4 | 1310 | { |
2582d8c1 SH |
1311 | struct imxuart_platform_data *pdata; |
1312 | struct imx_port *sport = platform_get_drvdata(pdev); | |
1da177e4 | 1313 | |
2582d8c1 SH |
1314 | pdata = pdev->dev.platform_data; |
1315 | ||
1316 | platform_set_drvdata(pdev, NULL); | |
1da177e4 | 1317 | |
38a41fdf | 1318 | if (sport) { |
1da177e4 | 1319 | uart_remove_one_port(&imx_reg, &sport->port); |
38a41fdf SH |
1320 | clk_put(sport->clk); |
1321 | } | |
1322 | ||
1323 | clk_disable(sport->clk); | |
1da177e4 | 1324 | |
bbcd18d1 | 1325 | if (pdata && pdata->exit) |
2582d8c1 SH |
1326 | pdata->exit(pdev); |
1327 | ||
dbff4e9e SH |
1328 | iounmap(sport->port.membase); |
1329 | kfree(sport); | |
1330 | ||
1da177e4 LT |
1331 | return 0; |
1332 | } | |
1333 | ||
3ae5eaec | 1334 | static struct platform_driver serial_imx_driver = { |
d3810cd4 OS |
1335 | .probe = serial_imx_probe, |
1336 | .remove = serial_imx_remove, | |
1da177e4 LT |
1337 | |
1338 | .suspend = serial_imx_suspend, | |
1339 | .resume = serial_imx_resume, | |
3ae5eaec | 1340 | .driver = { |
d3810cd4 | 1341 | .name = "imx-uart", |
e169c139 | 1342 | .owner = THIS_MODULE, |
3ae5eaec | 1343 | }, |
1da177e4 LT |
1344 | }; |
1345 | ||
1346 | static int __init imx_serial_init(void) | |
1347 | { | |
1348 | int ret; | |
1349 | ||
1350 | printk(KERN_INFO "Serial: IMX driver\n"); | |
1351 | ||
1da177e4 LT |
1352 | ret = uart_register_driver(&imx_reg); |
1353 | if (ret) | |
1354 | return ret; | |
1355 | ||
3ae5eaec | 1356 | ret = platform_driver_register(&serial_imx_driver); |
1da177e4 LT |
1357 | if (ret != 0) |
1358 | uart_unregister_driver(&imx_reg); | |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | static void __exit imx_serial_exit(void) | |
1364 | { | |
c889b896 | 1365 | platform_driver_unregister(&serial_imx_driver); |
4b300c36 | 1366 | uart_unregister_driver(&imx_reg); |
1da177e4 LT |
1367 | } |
1368 | ||
1369 | module_init(imx_serial_init); | |
1370 | module_exit(imx_serial_exit); | |
1371 | ||
1372 | MODULE_AUTHOR("Sascha Hauer"); | |
1373 | MODULE_DESCRIPTION("IMX generic serial port driver"); | |
1374 | MODULE_LICENSE("GPL"); | |
e169c139 | 1375 | MODULE_ALIAS("platform:imx-uart"); |