]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Driver for Zilog serial chips found on SGI workstations and | |
3 | * servers. This driver could actually be made more generic. | |
4 | * | |
5 | * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the | |
6 | * old drivers/sgi/char/sgiserial.c code which itself is based of the original | |
7 | * drivers/sbus/char/zs.c code. A lot of code has been simply moved over | |
8 | * directly from there but much has been rewritten. Credits therefore go out | |
9 | * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell | |
10 | * for their work there. | |
11 | * | |
12 | * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org) | |
13 | * Copyright (C) 2002 David S. Miller (davem@redhat.com) | |
14 | */ | |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/tty.h> | |
21 | #include <linux/tty_flip.h> | |
22 | #include <linux/major.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/ptrace.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/circ_buf.h> | |
28 | #include <linux/serial.h> | |
29 | #include <linux/sysrq.h> | |
30 | #include <linux/console.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/init.h> | |
33 | ||
34 | #include <asm/io.h> | |
35 | #include <asm/irq.h> | |
36 | #include <asm/sgialib.h> | |
37 | #include <asm/sgi/ioc.h> | |
38 | #include <asm/sgi/hpc3.h> | |
39 | #include <asm/sgi/ip22.h> | |
40 | ||
41 | #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
42 | #define SUPPORT_SYSRQ | |
43 | #endif | |
44 | ||
45 | #include <linux/serial_core.h> | |
46 | ||
47 | #include "ip22zilog.h" | |
48 | ||
49 | void ip22_do_break(void); | |
50 | ||
51 | /* | |
52 | * On IP22 we need to delay after register accesses but we do not need to | |
53 | * flush writes. | |
54 | */ | |
55 | #define ZSDELAY() udelay(5) | |
56 | #define ZSDELAY_LONG() udelay(20) | |
57 | #define ZS_WSYNC(channel) do { } while (0) | |
58 | ||
59 | #define NUM_IP22ZILOG 1 | |
60 | #define NUM_CHANNELS (NUM_IP22ZILOG * 2) | |
61 | ||
62 | #define ZS_CLOCK 3672000 /* Zilog input clock rate. */ | |
63 | #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */ | |
64 | ||
65 | /* | |
66 | * We wrap our port structure around the generic uart_port. | |
67 | */ | |
68 | struct uart_ip22zilog_port { | |
69 | struct uart_port port; | |
70 | ||
71 | /* IRQ servicing chain. */ | |
72 | struct uart_ip22zilog_port *next; | |
73 | ||
74 | /* Current values of Zilog write registers. */ | |
75 | unsigned char curregs[NUM_ZSREGS]; | |
76 | ||
77 | unsigned int flags; | |
78 | #define IP22ZILOG_FLAG_IS_CONS 0x00000004 | |
79 | #define IP22ZILOG_FLAG_IS_KGDB 0x00000008 | |
80 | #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010 | |
81 | #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020 | |
82 | #define IP22ZILOG_FLAG_REGS_HELD 0x00000040 | |
83 | #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080 | |
84 | #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100 | |
85 | ||
86 | unsigned int cflag; | |
87 | ||
88 | /* L1-A keyboard break state. */ | |
89 | int kbd_id; | |
90 | int l1_down; | |
91 | ||
92 | unsigned char parity_mask; | |
93 | unsigned char prev_status; | |
94 | }; | |
95 | ||
96 | #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase)) | |
97 | #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT)) | |
98 | #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \ | |
99 | (UART_ZILOG(PORT)->curregs[REGNUM]) | |
100 | #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \ | |
101 | ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL)) | |
102 | #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS) | |
103 | #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB) | |
104 | #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS) | |
105 | #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A) | |
106 | #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD) | |
107 | #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED) | |
108 | #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE) | |
109 | ||
110 | /* Reading and writing Zilog8530 registers. The delays are to make this | |
111 | * driver work on the IP22 which needs a settling delay after each chip | |
112 | * register access, other machines handle this in hardware via auxiliary | |
113 | * flip-flops which implement the settle time we do in software. | |
114 | * | |
115 | * The port lock must be held and local IRQs must be disabled | |
116 | * when {read,write}_zsreg is invoked. | |
117 | */ | |
118 | static unsigned char read_zsreg(struct zilog_channel *channel, | |
119 | unsigned char reg) | |
120 | { | |
121 | unsigned char retval; | |
122 | ||
123 | writeb(reg, &channel->control); | |
124 | ZSDELAY(); | |
125 | retval = readb(&channel->control); | |
126 | ZSDELAY(); | |
127 | ||
128 | return retval; | |
129 | } | |
130 | ||
131 | static void write_zsreg(struct zilog_channel *channel, | |
132 | unsigned char reg, unsigned char value) | |
133 | { | |
134 | writeb(reg, &channel->control); | |
135 | ZSDELAY(); | |
136 | writeb(value, &channel->control); | |
137 | ZSDELAY(); | |
138 | } | |
139 | ||
140 | static void ip22zilog_clear_fifo(struct zilog_channel *channel) | |
141 | { | |
142 | int i; | |
143 | ||
144 | for (i = 0; i < 32; i++) { | |
145 | unsigned char regval; | |
146 | ||
147 | regval = readb(&channel->control); | |
148 | ZSDELAY(); | |
149 | if (regval & Rx_CH_AV) | |
150 | break; | |
151 | ||
152 | regval = read_zsreg(channel, R1); | |
153 | readb(&channel->data); | |
154 | ZSDELAY(); | |
155 | ||
156 | if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { | |
157 | writeb(ERR_RES, &channel->control); | |
158 | ZSDELAY(); | |
159 | ZS_WSYNC(channel); | |
160 | } | |
161 | } | |
162 | } | |
163 | ||
164 | /* This function must only be called when the TX is not busy. The UART | |
165 | * port lock must be held and local interrupts disabled. | |
166 | */ | |
167 | static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs) | |
168 | { | |
169 | int i; | |
170 | ||
171 | /* Let pending transmits finish. */ | |
172 | for (i = 0; i < 1000; i++) { | |
173 | unsigned char stat = read_zsreg(channel, R1); | |
174 | if (stat & ALL_SNT) | |
175 | break; | |
176 | udelay(100); | |
177 | } | |
178 | ||
179 | writeb(ERR_RES, &channel->control); | |
180 | ZSDELAY(); | |
181 | ZS_WSYNC(channel); | |
182 | ||
183 | ip22zilog_clear_fifo(channel); | |
184 | ||
185 | /* Disable all interrupts. */ | |
186 | write_zsreg(channel, R1, | |
187 | regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); | |
188 | ||
189 | /* Set parity, sync config, stop bits, and clock divisor. */ | |
190 | write_zsreg(channel, R4, regs[R4]); | |
191 | ||
192 | /* Set misc. TX/RX control bits. */ | |
193 | write_zsreg(channel, R10, regs[R10]); | |
194 | ||
195 | /* Set TX/RX controls sans the enable bits. */ | |
196 | write_zsreg(channel, R3, regs[R3] & ~RxENAB); | |
197 | write_zsreg(channel, R5, regs[R5] & ~TxENAB); | |
198 | ||
199 | /* Synchronous mode config. */ | |
200 | write_zsreg(channel, R6, regs[R6]); | |
201 | write_zsreg(channel, R7, regs[R7]); | |
202 | ||
203 | /* Don't mess with the interrupt vector (R2, unused by us) and | |
204 | * master interrupt control (R9). We make sure this is setup | |
205 | * properly at probe time then never touch it again. | |
206 | */ | |
207 | ||
208 | /* Disable baud generator. */ | |
209 | write_zsreg(channel, R14, regs[R14] & ~BRENAB); | |
210 | ||
211 | /* Clock mode control. */ | |
212 | write_zsreg(channel, R11, regs[R11]); | |
213 | ||
214 | /* Lower and upper byte of baud rate generator divisor. */ | |
215 | write_zsreg(channel, R12, regs[R12]); | |
216 | write_zsreg(channel, R13, regs[R13]); | |
7369a8b3 | 217 | |
1da177e4 LT |
218 | /* Now rewrite R14, with BRENAB (if set). */ |
219 | write_zsreg(channel, R14, regs[R14]); | |
220 | ||
221 | /* External status interrupt control. */ | |
222 | write_zsreg(channel, R15, regs[R15]); | |
223 | ||
224 | /* Reset external status interrupts. */ | |
225 | write_zsreg(channel, R0, RES_EXT_INT); | |
226 | write_zsreg(channel, R0, RES_EXT_INT); | |
227 | ||
228 | /* Rewrite R3/R5, this time without enables masked. */ | |
229 | write_zsreg(channel, R3, regs[R3]); | |
230 | write_zsreg(channel, R5, regs[R5]); | |
231 | ||
232 | /* Rewrite R1, this time without IRQ enabled masked. */ | |
233 | write_zsreg(channel, R1, regs[R1]); | |
234 | } | |
235 | ||
236 | /* Reprogram the Zilog channel HW registers with the copies found in the | |
237 | * software state struct. If the transmitter is busy, we defer this update | |
238 | * until the next TX complete interrupt. Else, we do it right now. | |
239 | * | |
240 | * The UART port lock must be held and local interrupts disabled. | |
241 | */ | |
242 | static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up, | |
243 | struct zilog_channel *channel) | |
244 | { | |
245 | if (!ZS_REGS_HELD(up)) { | |
246 | if (ZS_TX_ACTIVE(up)) { | |
247 | up->flags |= IP22ZILOG_FLAG_REGS_HELD; | |
248 | } else { | |
249 | __load_zsregs(channel, up->curregs); | |
250 | } | |
251 | } | |
252 | } | |
253 | ||
254 | static void ip22zilog_receive_chars(struct uart_ip22zilog_port *up, | |
7d12e780 | 255 | struct zilog_channel *channel) |
1da177e4 LT |
256 | { |
257 | struct tty_struct *tty = up->port.info->tty; /* XXX info==NULL? */ | |
258 | ||
259 | while (1) { | |
33f0f88f | 260 | unsigned char ch, r1, flag; |
1da177e4 LT |
261 | |
262 | r1 = read_zsreg(channel, R1); | |
263 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { | |
264 | writeb(ERR_RES, &channel->control); | |
265 | ZSDELAY(); | |
266 | ZS_WSYNC(channel); | |
267 | } | |
268 | ||
269 | ch = readb(&channel->control); | |
270 | ZSDELAY(); | |
271 | ||
272 | /* This funny hack depends upon BRK_ABRT not interfering | |
273 | * with the other bits we care about in R1. | |
274 | */ | |
275 | if (ch & BRK_ABRT) | |
276 | r1 |= BRK_ABRT; | |
277 | ||
278 | ch = readb(&channel->data); | |
279 | ZSDELAY(); | |
280 | ||
281 | ch &= up->parity_mask; | |
282 | ||
283 | if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) { | |
284 | /* Wait for BREAK to deassert to avoid potentially | |
285 | * confusing the PROM. | |
286 | */ | |
287 | while (1) { | |
288 | ch = readb(&channel->control); | |
289 | ZSDELAY(); | |
290 | if (!(ch & BRK_ABRT)) | |
291 | break; | |
292 | } | |
293 | ip22_do_break(); | |
294 | return; | |
295 | } | |
296 | ||
297 | /* A real serial line, record the character and status. */ | |
33f0f88f | 298 | flag = TTY_NORMAL; |
1da177e4 LT |
299 | up->port.icount.rx++; |
300 | if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) { | |
301 | if (r1 & BRK_ABRT) { | |
302 | r1 &= ~(PAR_ERR | CRC_ERR); | |
303 | up->port.icount.brk++; | |
304 | if (uart_handle_break(&up->port)) | |
305 | goto next_char; | |
306 | } | |
307 | else if (r1 & PAR_ERR) | |
308 | up->port.icount.parity++; | |
309 | else if (r1 & CRC_ERR) | |
310 | up->port.icount.frame++; | |
311 | if (r1 & Rx_OVR) | |
312 | up->port.icount.overrun++; | |
313 | r1 &= up->port.read_status_mask; | |
314 | if (r1 & BRK_ABRT) | |
33f0f88f | 315 | flag = TTY_BREAK; |
1da177e4 | 316 | else if (r1 & PAR_ERR) |
33f0f88f | 317 | flag = TTY_PARITY; |
1da177e4 | 318 | else if (r1 & CRC_ERR) |
33f0f88f | 319 | flag = TTY_FRAME; |
1da177e4 | 320 | } |
7d12e780 | 321 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 LT |
322 | goto next_char; |
323 | ||
324 | if (up->port.ignore_status_mask == 0xff || | |
33f0f88f AC |
325 | (r1 & up->port.ignore_status_mask) == 0) |
326 | tty_insert_flip_char(tty, ch, flag); | |
327 | ||
328 | if (r1 & Rx_OVR) | |
329 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
1da177e4 LT |
330 | next_char: |
331 | ch = readb(&channel->control); | |
332 | ZSDELAY(); | |
333 | if (!(ch & Rx_CH_AV)) | |
334 | break; | |
335 | } | |
336 | ||
337 | tty_flip_buffer_push(tty); | |
338 | } | |
339 | ||
340 | static void ip22zilog_status_handle(struct uart_ip22zilog_port *up, | |
7d12e780 | 341 | struct zilog_channel *channel) |
1da177e4 LT |
342 | { |
343 | unsigned char status; | |
344 | ||
345 | status = readb(&channel->control); | |
346 | ZSDELAY(); | |
347 | ||
348 | writeb(RES_EXT_INT, &channel->control); | |
349 | ZSDELAY(); | |
350 | ZS_WSYNC(channel); | |
351 | ||
352 | if (ZS_WANTS_MODEM_STATUS(up)) { | |
353 | if (status & SYNC) | |
354 | up->port.icount.dsr++; | |
355 | ||
356 | /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. | |
357 | * But it does not tell us which bit has changed, we have to keep | |
358 | * track of this ourselves. | |
359 | */ | |
360 | if ((status & DCD) ^ up->prev_status) | |
361 | uart_handle_dcd_change(&up->port, | |
362 | (status & DCD)); | |
363 | if ((status & CTS) ^ up->prev_status) | |
364 | uart_handle_cts_change(&up->port, | |
365 | (status & CTS)); | |
366 | ||
367 | wake_up_interruptible(&up->port.info->delta_msr_wait); | |
368 | } | |
369 | ||
370 | up->prev_status = status; | |
371 | } | |
372 | ||
373 | static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up, | |
374 | struct zilog_channel *channel) | |
375 | { | |
376 | struct circ_buf *xmit; | |
377 | ||
378 | if (ZS_IS_CONS(up)) { | |
379 | unsigned char status = readb(&channel->control); | |
380 | ZSDELAY(); | |
381 | ||
382 | /* TX still busy? Just wait for the next TX done interrupt. | |
383 | * | |
384 | * It can occur because of how we do serial console writes. It would | |
385 | * be nice to transmit console writes just like we normally would for | |
386 | * a TTY line. (ie. buffered and TX interrupt driven). That is not | |
387 | * easy because console writes cannot sleep. One solution might be | |
388 | * to poll on enough port->xmit space becomming free. -DaveM | |
389 | */ | |
390 | if (!(status & Tx_BUF_EMP)) | |
391 | return; | |
392 | } | |
393 | ||
394 | up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE; | |
395 | ||
396 | if (ZS_REGS_HELD(up)) { | |
397 | __load_zsregs(channel, up->curregs); | |
398 | up->flags &= ~IP22ZILOG_FLAG_REGS_HELD; | |
399 | } | |
400 | ||
401 | if (ZS_TX_STOPPED(up)) { | |
402 | up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; | |
403 | goto ack_tx_int; | |
404 | } | |
405 | ||
406 | if (up->port.x_char) { | |
407 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
408 | writeb(up->port.x_char, &channel->data); | |
409 | ZSDELAY(); | |
410 | ZS_WSYNC(channel); | |
411 | ||
412 | up->port.icount.tx++; | |
413 | up->port.x_char = 0; | |
414 | return; | |
415 | } | |
416 | ||
417 | if (up->port.info == NULL) | |
418 | goto ack_tx_int; | |
419 | xmit = &up->port.info->xmit; | |
c4432c41 | 420 | if (uart_circ_empty(xmit)) |
1da177e4 | 421 | goto ack_tx_int; |
1da177e4 LT |
422 | if (uart_tx_stopped(&up->port)) |
423 | goto ack_tx_int; | |
424 | ||
425 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
426 | writeb(xmit->buf[xmit->tail], &channel->data); | |
427 | ZSDELAY(); | |
428 | ZS_WSYNC(channel); | |
429 | ||
430 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
431 | up->port.icount.tx++; | |
432 | ||
433 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
434 | uart_write_wakeup(&up->port); | |
435 | ||
436 | return; | |
437 | ||
438 | ack_tx_int: | |
439 | writeb(RES_Tx_P, &channel->control); | |
440 | ZSDELAY(); | |
441 | ZS_WSYNC(channel); | |
442 | } | |
443 | ||
7d12e780 | 444 | static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id) |
1da177e4 LT |
445 | { |
446 | struct uart_ip22zilog_port *up = dev_id; | |
447 | ||
448 | while (up) { | |
449 | struct zilog_channel *channel | |
450 | = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
451 | unsigned char r3; | |
452 | ||
453 | spin_lock(&up->port.lock); | |
454 | r3 = read_zsreg(channel, R3); | |
455 | ||
456 | /* Channel A */ | |
457 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { | |
458 | writeb(RES_H_IUS, &channel->control); | |
459 | ZSDELAY(); | |
460 | ZS_WSYNC(channel); | |
461 | ||
462 | if (r3 & CHARxIP) | |
7d12e780 | 463 | ip22zilog_receive_chars(up, channel); |
1da177e4 | 464 | if (r3 & CHAEXT) |
7d12e780 | 465 | ip22zilog_status_handle(up, channel); |
1da177e4 LT |
466 | if (r3 & CHATxIP) |
467 | ip22zilog_transmit_chars(up, channel); | |
468 | } | |
469 | spin_unlock(&up->port.lock); | |
470 | ||
471 | /* Channel B */ | |
472 | up = up->next; | |
473 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
474 | ||
475 | spin_lock(&up->port.lock); | |
476 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { | |
477 | writeb(RES_H_IUS, &channel->control); | |
478 | ZSDELAY(); | |
479 | ZS_WSYNC(channel); | |
480 | ||
481 | if (r3 & CHBRxIP) | |
7d12e780 | 482 | ip22zilog_receive_chars(up, channel); |
1da177e4 | 483 | if (r3 & CHBEXT) |
7d12e780 | 484 | ip22zilog_status_handle(up, channel); |
1da177e4 LT |
485 | if (r3 & CHBTxIP) |
486 | ip22zilog_transmit_chars(up, channel); | |
487 | } | |
488 | spin_unlock(&up->port.lock); | |
489 | ||
490 | up = up->next; | |
491 | } | |
492 | ||
493 | return IRQ_HANDLED; | |
494 | } | |
495 | ||
496 | /* A convenient way to quickly get R0 status. The caller must _not_ hold the | |
497 | * port lock, it is acquired here. | |
498 | */ | |
499 | static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port) | |
500 | { | |
501 | struct zilog_channel *channel; | |
1da177e4 LT |
502 | unsigned char status; |
503 | ||
1da177e4 LT |
504 | channel = ZILOG_CHANNEL_FROM_PORT(port); |
505 | status = readb(&channel->control); | |
506 | ZSDELAY(); | |
507 | ||
1da177e4 LT |
508 | return status; |
509 | } | |
510 | ||
511 | /* The port lock is not held. */ | |
512 | static unsigned int ip22zilog_tx_empty(struct uart_port *port) | |
513 | { | |
c5f4644e | 514 | unsigned long flags; |
1da177e4 LT |
515 | unsigned char status; |
516 | unsigned int ret; | |
517 | ||
c5f4644e RK |
518 | spin_lock_irqsave(&port->lock, flags); |
519 | ||
1da177e4 | 520 | status = ip22zilog_read_channel_status(port); |
c5f4644e RK |
521 | |
522 | spin_unlock_irqrestore(&port->lock, flags); | |
523 | ||
1da177e4 LT |
524 | if (status & Tx_BUF_EMP) |
525 | ret = TIOCSER_TEMT; | |
526 | else | |
527 | ret = 0; | |
528 | ||
529 | return ret; | |
530 | } | |
531 | ||
c5f4644e | 532 | /* The port lock is held and interrupts are disabled. */ |
1da177e4 LT |
533 | static unsigned int ip22zilog_get_mctrl(struct uart_port *port) |
534 | { | |
535 | unsigned char status; | |
536 | unsigned int ret; | |
537 | ||
538 | status = ip22zilog_read_channel_status(port); | |
539 | ||
540 | ret = 0; | |
541 | if (status & DCD) | |
542 | ret |= TIOCM_CAR; | |
543 | if (status & SYNC) | |
544 | ret |= TIOCM_DSR; | |
545 | if (status & CTS) | |
546 | ret |= TIOCM_CTS; | |
547 | ||
548 | return ret; | |
549 | } | |
550 | ||
551 | /* The port lock is held and interrupts are disabled. */ | |
552 | static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
553 | { | |
554 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
555 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
556 | unsigned char set_bits, clear_bits; | |
557 | ||
558 | set_bits = clear_bits = 0; | |
559 | ||
560 | if (mctrl & TIOCM_RTS) | |
561 | set_bits |= RTS; | |
562 | else | |
563 | clear_bits |= RTS; | |
564 | if (mctrl & TIOCM_DTR) | |
565 | set_bits |= DTR; | |
566 | else | |
567 | clear_bits |= DTR; | |
568 | ||
7369a8b3 | 569 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
570 | up->curregs[R5] |= set_bits; |
571 | up->curregs[R5] &= ~clear_bits; | |
572 | write_zsreg(channel, R5, up->curregs[R5]); | |
573 | } | |
574 | ||
575 | /* The port lock is held and interrupts are disabled. */ | |
b129a8cc | 576 | static void ip22zilog_stop_tx(struct uart_port *port) |
1da177e4 LT |
577 | { |
578 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
579 | ||
580 | up->flags |= IP22ZILOG_FLAG_TX_STOPPED; | |
581 | } | |
582 | ||
583 | /* The port lock is held and interrupts are disabled. */ | |
b129a8cc | 584 | static void ip22zilog_start_tx(struct uart_port *port) |
1da177e4 LT |
585 | { |
586 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
587 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
588 | unsigned char status; | |
589 | ||
590 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
591 | up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; | |
592 | ||
593 | status = readb(&channel->control); | |
594 | ZSDELAY(); | |
595 | ||
596 | /* TX busy? Just wait for the TX done interrupt. */ | |
597 | if (!(status & Tx_BUF_EMP)) | |
598 | return; | |
599 | ||
600 | /* Send the first character to jump-start the TX done | |
601 | * IRQ sending engine. | |
602 | */ | |
603 | if (port->x_char) { | |
604 | writeb(port->x_char, &channel->data); | |
605 | ZSDELAY(); | |
606 | ZS_WSYNC(channel); | |
607 | ||
608 | port->icount.tx++; | |
609 | port->x_char = 0; | |
610 | } else { | |
611 | struct circ_buf *xmit = &port->info->xmit; | |
612 | ||
613 | writeb(xmit->buf[xmit->tail], &channel->data); | |
614 | ZSDELAY(); | |
615 | ZS_WSYNC(channel); | |
616 | ||
617 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
618 | port->icount.tx++; | |
619 | ||
620 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
621 | uart_write_wakeup(&up->port); | |
622 | } | |
623 | } | |
624 | ||
625 | /* The port lock is held and interrupts are disabled. */ | |
626 | static void ip22zilog_stop_rx(struct uart_port *port) | |
627 | { | |
628 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
629 | struct zilog_channel *channel; | |
630 | ||
631 | if (ZS_IS_CONS(up)) | |
632 | return; | |
633 | ||
634 | channel = ZILOG_CHANNEL_FROM_PORT(port); | |
635 | ||
636 | /* Disable all RX interrupts. */ | |
637 | up->curregs[R1] &= ~RxINT_MASK; | |
638 | ip22zilog_maybe_update_regs(up, channel); | |
639 | } | |
640 | ||
641 | /* The port lock is held. */ | |
642 | static void ip22zilog_enable_ms(struct uart_port *port) | |
643 | { | |
644 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
645 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
646 | unsigned char new_reg; | |
647 | ||
648 | new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); | |
649 | if (new_reg != up->curregs[R15]) { | |
650 | up->curregs[R15] = new_reg; | |
651 | ||
7369a8b3 | 652 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
653 | write_zsreg(channel, R15, up->curregs[R15]); |
654 | } | |
655 | } | |
656 | ||
657 | /* The port lock is not held. */ | |
658 | static void ip22zilog_break_ctl(struct uart_port *port, int break_state) | |
659 | { | |
660 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
661 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
662 | unsigned char set_bits, clear_bits, new_reg; | |
663 | unsigned long flags; | |
664 | ||
665 | set_bits = clear_bits = 0; | |
666 | ||
667 | if (break_state) | |
668 | set_bits |= SND_BRK; | |
669 | else | |
670 | clear_bits |= SND_BRK; | |
671 | ||
672 | spin_lock_irqsave(&port->lock, flags); | |
673 | ||
674 | new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; | |
675 | if (new_reg != up->curregs[R5]) { | |
676 | up->curregs[R5] = new_reg; | |
677 | ||
7369a8b3 | 678 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
679 | write_zsreg(channel, R5, up->curregs[R5]); |
680 | } | |
681 | ||
682 | spin_unlock_irqrestore(&port->lock, flags); | |
683 | } | |
684 | ||
685 | static void __ip22zilog_startup(struct uart_ip22zilog_port *up) | |
686 | { | |
687 | struct zilog_channel *channel; | |
688 | ||
689 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
690 | up->prev_status = readb(&channel->control); | |
691 | ||
692 | /* Enable receiver and transmitter. */ | |
693 | up->curregs[R3] |= RxENAB; | |
694 | up->curregs[R5] |= TxENAB; | |
695 | ||
696 | up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; | |
697 | ip22zilog_maybe_update_regs(up, channel); | |
698 | } | |
699 | ||
700 | static int ip22zilog_startup(struct uart_port *port) | |
701 | { | |
702 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
703 | unsigned long flags; | |
704 | ||
705 | if (ZS_IS_CONS(up)) | |
706 | return 0; | |
707 | ||
708 | spin_lock_irqsave(&port->lock, flags); | |
709 | __ip22zilog_startup(up); | |
710 | spin_unlock_irqrestore(&port->lock, flags); | |
711 | return 0; | |
712 | } | |
713 | ||
714 | /* | |
715 | * The test for ZS_IS_CONS is explained by the following e-mail: | |
716 | ***** | |
717 | * From: Russell King <rmk@arm.linux.org.uk> | |
718 | * Date: Sun, 8 Dec 2002 10:18:38 +0000 | |
719 | * | |
720 | * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote: | |
721 | * > I boot my 2.5 boxes using "console=ttyS0,9600" argument, | |
722 | * > and I noticed that something is not right with reference | |
723 | * > counting in this case. It seems that when the console | |
724 | * > is open by kernel initially, this is not accounted | |
725 | * > as an open, and uart_startup is not called. | |
726 | * | |
727 | * That is correct. We are unable to call uart_startup when the serial | |
728 | * console is initialised because it may need to allocate memory (as | |
729 | * request_irq does) and the memory allocators may not have been | |
730 | * initialised. | |
731 | * | |
732 | * 1. initialise the port into a state where it can send characters in the | |
733 | * console write method. | |
734 | * | |
735 | * 2. don't do the actual hardware shutdown in your shutdown() method (but | |
736 | * do the normal software shutdown - ie, free irqs etc) | |
737 | ***** | |
738 | */ | |
739 | static void ip22zilog_shutdown(struct uart_port *port) | |
740 | { | |
741 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
742 | struct zilog_channel *channel; | |
743 | unsigned long flags; | |
744 | ||
745 | if (ZS_IS_CONS(up)) | |
746 | return; | |
747 | ||
748 | spin_lock_irqsave(&port->lock, flags); | |
749 | ||
750 | channel = ZILOG_CHANNEL_FROM_PORT(port); | |
751 | ||
752 | /* Disable receiver and transmitter. */ | |
753 | up->curregs[R3] &= ~RxENAB; | |
754 | up->curregs[R5] &= ~TxENAB; | |
755 | ||
756 | /* Disable all interrupts and BRK assertion. */ | |
757 | up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); | |
758 | up->curregs[R5] &= ~SND_BRK; | |
759 | ip22zilog_maybe_update_regs(up, channel); | |
760 | ||
761 | spin_unlock_irqrestore(&port->lock, flags); | |
762 | } | |
763 | ||
764 | /* Shared by TTY driver and serial console setup. The port lock is held | |
765 | * and local interrupts are disabled. | |
766 | */ | |
767 | static void | |
768 | ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag, | |
769 | unsigned int iflag, int brg) | |
770 | { | |
771 | ||
772 | up->curregs[R10] = NRZ; | |
773 | up->curregs[R11] = TCBR | RCBR; | |
774 | ||
775 | /* Program BAUD and clock source. */ | |
776 | up->curregs[R4] &= ~XCLK_MASK; | |
777 | up->curregs[R4] |= X16CLK; | |
778 | up->curregs[R12] = brg & 0xff; | |
779 | up->curregs[R13] = (brg >> 8) & 0xff; | |
780 | up->curregs[R14] = BRENAB; | |
781 | ||
782 | /* Character size, stop bits, and parity. */ | |
783 | up->curregs[3] &= ~RxN_MASK; | |
784 | up->curregs[5] &= ~TxN_MASK; | |
785 | switch (cflag & CSIZE) { | |
786 | case CS5: | |
787 | up->curregs[3] |= Rx5; | |
788 | up->curregs[5] |= Tx5; | |
789 | up->parity_mask = 0x1f; | |
790 | break; | |
791 | case CS6: | |
792 | up->curregs[3] |= Rx6; | |
793 | up->curregs[5] |= Tx6; | |
794 | up->parity_mask = 0x3f; | |
795 | break; | |
796 | case CS7: | |
797 | up->curregs[3] |= Rx7; | |
798 | up->curregs[5] |= Tx7; | |
799 | up->parity_mask = 0x7f; | |
800 | break; | |
801 | case CS8: | |
802 | default: | |
803 | up->curregs[3] |= Rx8; | |
804 | up->curregs[5] |= Tx8; | |
805 | up->parity_mask = 0xff; | |
806 | break; | |
807 | }; | |
808 | up->curregs[4] &= ~0x0c; | |
809 | if (cflag & CSTOPB) | |
810 | up->curregs[4] |= SB2; | |
811 | else | |
812 | up->curregs[4] |= SB1; | |
813 | if (cflag & PARENB) | |
814 | up->curregs[4] |= PAR_ENAB; | |
815 | else | |
816 | up->curregs[4] &= ~PAR_ENAB; | |
817 | if (!(cflag & PARODD)) | |
818 | up->curregs[4] |= PAR_EVEN; | |
819 | else | |
820 | up->curregs[4] &= ~PAR_EVEN; | |
821 | ||
822 | up->port.read_status_mask = Rx_OVR; | |
823 | if (iflag & INPCK) | |
824 | up->port.read_status_mask |= CRC_ERR | PAR_ERR; | |
825 | if (iflag & (BRKINT | PARMRK)) | |
826 | up->port.read_status_mask |= BRK_ABRT; | |
827 | ||
828 | up->port.ignore_status_mask = 0; | |
829 | if (iflag & IGNPAR) | |
830 | up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; | |
831 | if (iflag & IGNBRK) { | |
832 | up->port.ignore_status_mask |= BRK_ABRT; | |
833 | if (iflag & IGNPAR) | |
834 | up->port.ignore_status_mask |= Rx_OVR; | |
835 | } | |
836 | ||
837 | if ((cflag & CREAD) == 0) | |
838 | up->port.ignore_status_mask = 0xff; | |
839 | } | |
840 | ||
841 | /* The port lock is not held. */ | |
842 | static void | |
843 | ip22zilog_set_termios(struct uart_port *port, struct termios *termios, | |
844 | struct termios *old) | |
845 | { | |
846 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
847 | unsigned long flags; | |
848 | int baud, brg; | |
849 | ||
850 | baud = uart_get_baud_rate(port, termios, old, 1200, 76800); | |
851 | ||
852 | spin_lock_irqsave(&up->port.lock, flags); | |
853 | ||
854 | brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); | |
855 | ||
856 | ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); | |
857 | ||
858 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
859 | up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; | |
860 | else | |
861 | up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; | |
862 | ||
863 | up->cflag = termios->c_cflag; | |
864 | ||
865 | ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); | |
866 | ||
867 | spin_unlock_irqrestore(&up->port.lock, flags); | |
868 | } | |
869 | ||
870 | static const char *ip22zilog_type(struct uart_port *port) | |
871 | { | |
872 | return "IP22-Zilog"; | |
873 | } | |
874 | ||
875 | /* We do not request/release mappings of the registers here, this | |
876 | * happens at early serial probe time. | |
877 | */ | |
878 | static void ip22zilog_release_port(struct uart_port *port) | |
879 | { | |
880 | } | |
881 | ||
882 | static int ip22zilog_request_port(struct uart_port *port) | |
883 | { | |
884 | return 0; | |
885 | } | |
886 | ||
887 | /* These do not need to do anything interesting either. */ | |
888 | static void ip22zilog_config_port(struct uart_port *port, int flags) | |
889 | { | |
890 | } | |
891 | ||
892 | /* We do not support letting the user mess with the divisor, IRQ, etc. */ | |
893 | static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser) | |
894 | { | |
895 | return -EINVAL; | |
896 | } | |
897 | ||
898 | static struct uart_ops ip22zilog_pops = { | |
899 | .tx_empty = ip22zilog_tx_empty, | |
900 | .set_mctrl = ip22zilog_set_mctrl, | |
901 | .get_mctrl = ip22zilog_get_mctrl, | |
902 | .stop_tx = ip22zilog_stop_tx, | |
903 | .start_tx = ip22zilog_start_tx, | |
904 | .stop_rx = ip22zilog_stop_rx, | |
905 | .enable_ms = ip22zilog_enable_ms, | |
906 | .break_ctl = ip22zilog_break_ctl, | |
907 | .startup = ip22zilog_startup, | |
908 | .shutdown = ip22zilog_shutdown, | |
909 | .set_termios = ip22zilog_set_termios, | |
910 | .type = ip22zilog_type, | |
911 | .release_port = ip22zilog_release_port, | |
912 | .request_port = ip22zilog_request_port, | |
913 | .config_port = ip22zilog_config_port, | |
914 | .verify_port = ip22zilog_verify_port, | |
915 | }; | |
916 | ||
917 | static struct uart_ip22zilog_port *ip22zilog_port_table; | |
918 | static struct zilog_layout **ip22zilog_chip_regs; | |
919 | ||
920 | static struct uart_ip22zilog_port *ip22zilog_irq_chain; | |
921 | static int zilog_irq = -1; | |
922 | ||
923 | static void * __init alloc_one_table(unsigned long size) | |
924 | { | |
925 | void *ret; | |
926 | ||
927 | ret = kmalloc(size, GFP_KERNEL); | |
928 | if (ret != NULL) | |
929 | memset(ret, 0, size); | |
930 | ||
931 | return ret; | |
932 | } | |
933 | ||
934 | static void __init ip22zilog_alloc_tables(void) | |
935 | { | |
936 | ip22zilog_port_table = (struct uart_ip22zilog_port *) | |
937 | alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); | |
938 | ip22zilog_chip_regs = (struct zilog_layout **) | |
939 | alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *)); | |
940 | ||
941 | if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) { | |
942 | panic("IP22-Zilog: Cannot allocate IP22-Zilog tables."); | |
943 | } | |
944 | } | |
945 | ||
946 | /* Get the address of the registers for IP22-Zilog instance CHIP. */ | |
947 | static struct zilog_layout * __init get_zs(int chip) | |
948 | { | |
949 | unsigned long base; | |
950 | ||
951 | if (chip < 0 || chip >= NUM_IP22ZILOG) { | |
952 | panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip); | |
953 | } | |
954 | ||
955 | /* Not probe-able, hard code it. */ | |
956 | base = (unsigned long) &sgioc->uart; | |
957 | ||
958 | zilog_irq = SGI_SERIAL_IRQ; | |
959 | request_mem_region(base, 8, "IP22-Zilog"); | |
960 | ||
961 | return (struct zilog_layout *) base; | |
962 | } | |
963 | ||
964 | #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */ | |
965 | ||
966 | #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE | |
d358788f | 967 | static void ip22zilog_put_char(struct uart_port *port, int ch) |
1da177e4 | 968 | { |
d358788f | 969 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
1da177e4 LT |
970 | int loops = ZS_PUT_CHAR_MAX_DELAY; |
971 | ||
972 | /* This is a timed polling loop so do not switch the explicit | |
973 | * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM | |
974 | */ | |
975 | do { | |
976 | unsigned char val = readb(&channel->control); | |
977 | if (val & Tx_BUF_EMP) { | |
978 | ZSDELAY(); | |
979 | break; | |
980 | } | |
981 | udelay(5); | |
982 | } while (--loops); | |
983 | ||
984 | writeb(ch, &channel->data); | |
985 | ZSDELAY(); | |
986 | ZS_WSYNC(channel); | |
987 | } | |
988 | ||
989 | static void | |
990 | ip22zilog_console_write(struct console *con, const char *s, unsigned int count) | |
991 | { | |
992 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; | |
1da177e4 | 993 | unsigned long flags; |
1da177e4 LT |
994 | |
995 | spin_lock_irqsave(&up->port.lock, flags); | |
d358788f | 996 | uart_console_write(&up->port, s, count, ip22zilog_put_char); |
1da177e4 LT |
997 | udelay(2); |
998 | spin_unlock_irqrestore(&up->port.lock, flags); | |
999 | } | |
1000 | ||
1001 | void | |
1002 | ip22serial_console_termios(struct console *con, char *options) | |
1003 | { | |
1004 | int baud = 9600, bits = 8, cflag; | |
1005 | int parity = 'n'; | |
1006 | int flow = 'n'; | |
1007 | ||
1008 | if (options) | |
1009 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1010 | ||
1011 | cflag = CREAD | HUPCL | CLOCAL; | |
1012 | ||
1013 | switch (baud) { | |
1014 | case 150: cflag |= B150; break; | |
1015 | case 300: cflag |= B300; break; | |
1016 | case 600: cflag |= B600; break; | |
1017 | case 1200: cflag |= B1200; break; | |
1018 | case 2400: cflag |= B2400; break; | |
1019 | case 4800: cflag |= B4800; break; | |
1020 | case 9600: cflag |= B9600; break; | |
1021 | case 19200: cflag |= B19200; break; | |
1022 | case 38400: cflag |= B38400; break; | |
1023 | default: baud = 9600; cflag |= B9600; break; | |
1024 | } | |
1025 | ||
1026 | con->cflag = cflag | CS8; /* 8N1 */ | |
1027 | } | |
1028 | ||
1029 | static int __init ip22zilog_console_setup(struct console *con, char *options) | |
1030 | { | |
1031 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; | |
1032 | unsigned long flags; | |
1033 | int baud, brg; | |
1034 | ||
1035 | printk("Console: ttyS%d (IP22-Zilog)\n", con->index); | |
1036 | ||
1037 | /* Get firmware console settings. */ | |
1038 | ip22serial_console_termios(con, options); | |
1039 | ||
1040 | /* Firmware console speed is limited to 150-->38400 baud so | |
1041 | * this hackish cflag thing is OK. | |
1042 | */ | |
1043 | switch (con->cflag & CBAUD) { | |
1044 | case B150: baud = 150; break; | |
1045 | case B300: baud = 300; break; | |
1046 | case B600: baud = 600; break; | |
1047 | case B1200: baud = 1200; break; | |
1048 | case B2400: baud = 2400; break; | |
1049 | case B4800: baud = 4800; break; | |
1050 | default: case B9600: baud = 9600; break; | |
1051 | case B19200: baud = 19200; break; | |
1052 | case B38400: baud = 38400; break; | |
1053 | }; | |
1054 | ||
1055 | brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); | |
1056 | ||
1057 | spin_lock_irqsave(&up->port.lock, flags); | |
1058 | ||
1059 | up->curregs[R15] = BRKIE; | |
1060 | ip22zilog_convert_to_zs(up, con->cflag, 0, brg); | |
1061 | ||
1062 | __ip22zilog_startup(up); | |
1063 | ||
1064 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | static struct uart_driver ip22zilog_reg; | |
1070 | ||
1071 | static struct console ip22zilog_console = { | |
1072 | .name = "ttyS", | |
1073 | .write = ip22zilog_console_write, | |
1074 | .device = uart_console_device, | |
1075 | .setup = ip22zilog_console_setup, | |
1076 | .flags = CON_PRINTBUFFER, | |
1077 | .index = -1, | |
1078 | .data = &ip22zilog_reg, | |
1079 | }; | |
1080 | #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ | |
1081 | ||
1082 | static struct uart_driver ip22zilog_reg = { | |
1083 | .owner = THIS_MODULE, | |
1084 | .driver_name = "serial", | |
1da177e4 LT |
1085 | .dev_name = "ttyS", |
1086 | .major = TTY_MAJOR, | |
1087 | .minor = 64, | |
1088 | .nr = NUM_CHANNELS, | |
1089 | #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE | |
1090 | .cons = &ip22zilog_console, | |
1091 | #endif | |
1092 | }; | |
1093 | ||
1094 | static void __init ip22zilog_prepare(void) | |
1095 | { | |
1096 | struct uart_ip22zilog_port *up; | |
1097 | struct zilog_layout *rp; | |
1098 | int channel, chip; | |
1099 | ||
1100 | /* | |
1101 | * Temporary fix. | |
1102 | */ | |
1103 | for (channel = 0; channel < NUM_CHANNELS; channel++) | |
1104 | spin_lock_init(&ip22zilog_port_table[channel].port.lock); | |
1105 | ||
1106 | ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; | |
1107 | up = &ip22zilog_port_table[0]; | |
1108 | for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) | |
1109 | up[channel].next = &up[channel - 1]; | |
1110 | up[channel].next = NULL; | |
1111 | ||
1112 | for (chip = 0; chip < NUM_IP22ZILOG; chip++) { | |
1113 | if (!ip22zilog_chip_regs[chip]) { | |
1114 | ip22zilog_chip_regs[chip] = rp = get_zs(chip); | |
1115 | ||
1116 | up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; | |
1117 | up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; | |
1118 | ||
1119 | /* In theory mapbase is the physical address ... */ | |
1120 | up[(chip * 2) + 0].port.mapbase = | |
1121 | (unsigned long) ioremap((unsigned long) &rp->channelB, 8); | |
1122 | up[(chip * 2) + 1].port.mapbase = | |
1123 | (unsigned long) ioremap((unsigned long) &rp->channelA, 8); | |
1124 | } | |
1125 | ||
1126 | /* Channel A */ | |
1127 | up[(chip * 2) + 0].port.iotype = UPIO_MEM; | |
1128 | up[(chip * 2) + 0].port.irq = zilog_irq; | |
1129 | up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; | |
1130 | up[(chip * 2) + 0].port.fifosize = 1; | |
1131 | up[(chip * 2) + 0].port.ops = &ip22zilog_pops; | |
1132 | up[(chip * 2) + 0].port.type = PORT_IP22ZILOG; | |
1133 | up[(chip * 2) + 0].port.flags = 0; | |
1134 | up[(chip * 2) + 0].port.line = (chip * 2) + 0; | |
1135 | up[(chip * 2) + 0].flags = 0; | |
1136 | ||
1137 | /* Channel B */ | |
1138 | up[(chip * 2) + 1].port.iotype = UPIO_MEM; | |
1139 | up[(chip * 2) + 1].port.irq = zilog_irq; | |
1140 | up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; | |
1141 | up[(chip * 2) + 1].port.fifosize = 1; | |
1142 | up[(chip * 2) + 1].port.ops = &ip22zilog_pops; | |
1143 | up[(chip * 2) + 1].port.type = PORT_IP22ZILOG; | |
1da177e4 | 1144 | up[(chip * 2) + 1].port.line = (chip * 2) + 1; |
c65b15cf | 1145 | up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A; |
1da177e4 LT |
1146 | } |
1147 | } | |
1148 | ||
1149 | static void __init ip22zilog_init_hw(void) | |
1150 | { | |
1151 | int i; | |
1152 | ||
1153 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1154 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; | |
1155 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
1156 | unsigned long flags; | |
1157 | int baud, brg; | |
1158 | ||
1159 | spin_lock_irqsave(&up->port.lock, flags); | |
1160 | ||
1161 | if (ZS_IS_CHANNEL_A(up)) { | |
1162 | write_zsreg(channel, R9, FHWRES); | |
1163 | ZSDELAY_LONG(); | |
1164 | (void) read_zsreg(channel, R0); | |
1165 | } | |
1166 | ||
1167 | /* Normal serial TTY. */ | |
1168 | up->parity_mask = 0xff; | |
1169 | up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; | |
1170 | up->curregs[R4] = PAR_EVEN | X16CLK | SB1; | |
1171 | up->curregs[R3] = RxENAB | Rx8; | |
1172 | up->curregs[R5] = TxENAB | Tx8; | |
1173 | up->curregs[R9] = NV | MIE; | |
1174 | up->curregs[R10] = NRZ; | |
1175 | up->curregs[R11] = TCBR | RCBR; | |
1176 | baud = 9600; | |
1177 | brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); | |
1178 | up->curregs[R12] = (brg & 0xff); | |
1179 | up->curregs[R13] = (brg >> 8) & 0xff; | |
1180 | up->curregs[R14] = BRENAB; | |
1181 | __load_zsregs(channel, up->curregs); | |
1182 | /* set master interrupt enable */ | |
1183 | write_zsreg(channel, R9, up->curregs[R9]); | |
1184 | ||
1185 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | static int __init ip22zilog_ports_init(void) | |
1190 | { | |
1191 | int ret; | |
1192 | ||
1193 | printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG); | |
1194 | ||
1195 | ip22zilog_prepare(); | |
1196 | ||
1197 | if (request_irq(zilog_irq, ip22zilog_interrupt, 0, | |
1198 | "IP22-Zilog", ip22zilog_irq_chain)) { | |
1199 | panic("IP22-Zilog: Unable to register zs interrupt handler.\n"); | |
1200 | } | |
1201 | ||
1202 | ip22zilog_init_hw(); | |
1203 | ||
1204 | ret = uart_register_driver(&ip22zilog_reg); | |
1205 | if (ret == 0) { | |
1206 | int i; | |
1207 | ||
1208 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1209 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; | |
1210 | ||
1211 | uart_add_one_port(&ip22zilog_reg, &up->port); | |
1212 | } | |
1213 | } | |
1214 | ||
1215 | return ret; | |
1216 | } | |
1217 | ||
1218 | static int __init ip22zilog_init(void) | |
1219 | { | |
1220 | /* IP22 Zilog setup is hard coded, no probing to do. */ | |
1221 | ip22zilog_alloc_tables(); | |
1222 | ip22zilog_ports_init(); | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
1227 | static void __exit ip22zilog_exit(void) | |
1228 | { | |
1229 | int i; | |
6257b3bd | 1230 | struct uart_ip22zilog_port *up; |
1da177e4 LT |
1231 | |
1232 | for (i = 0; i < NUM_CHANNELS; i++) { | |
6257b3bd | 1233 | up = &ip22zilog_port_table[i]; |
1da177e4 LT |
1234 | |
1235 | uart_remove_one_port(&ip22zilog_reg, &up->port); | |
1236 | } | |
1237 | ||
6257b3bd AL |
1238 | /* Free IO mem */ |
1239 | up = &ip22zilog_port_table[0]; | |
1240 | for (i = 0; i < NUM_IP22ZILOG; i++) { | |
1241 | if (up[(i * 2) + 0].port.mapbase) { | |
1242 | iounmap((void*)up[(i * 2) + 0].port.mapbase); | |
1243 | up[(i * 2) + 0].port.mapbase = 0; | |
1244 | } | |
1245 | if (up[(i * 2) + 1].port.mapbase) { | |
1246 | iounmap((void*)up[(i * 2) + 1].port.mapbase); | |
1247 | up[(i * 2) + 1].port.mapbase = 0; | |
1248 | } | |
1249 | } | |
1250 | ||
1da177e4 LT |
1251 | uart_unregister_driver(&ip22zilog_reg); |
1252 | } | |
1253 | ||
1254 | module_init(ip22zilog_init); | |
1255 | module_exit(ip22zilog_exit); | |
1256 | ||
1257 | /* David wrote it but I'm to blame for the bugs ... */ | |
1258 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); | |
1259 | MODULE_DESCRIPTION("SGI Zilog serial port driver"); | |
1260 | MODULE_LICENSE("GPL"); |