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1da177e4 LT |
1 | /* |
2 | * m32r_sio.c | |
3 | * | |
4 | * Driver for M32R serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * Based on drivers/serial/8250.c. | |
8 | * | |
9 | * Copyright (C) 2001 Russell King. | |
10 | * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | */ | |
17 | ||
18 | /* | |
19 | * A note about mapbase / membase | |
20 | * | |
21 | * mapbase is the physical address of the IO port. Currently, we don't | |
22 | * support this very well, and it may well be dropped from this driver | |
23 | * in future. As such, mapbase should be NULL. | |
24 | * | |
25 | * membase is an 'ioremapped' cookie. This is compatible with the old | |
26 | * serial.c driver, and is currently the preferred form. | |
27 | */ | |
28 | #include <linux/config.h> | |
29 | ||
30 | #if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
31 | #define SUPPORT_SYSRQ | |
32 | #endif | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/tty.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/sysrq.h> | |
40 | #include <linux/serial.h> | |
41 | #include <linux/serialP.h> | |
42 | #include <linux/delay.h> | |
43 | ||
44 | #include <asm/m32r.h> | |
45 | #include <asm/io.h> | |
46 | #include <asm/irq.h> | |
47 | ||
48 | #define PORT_M32R_BASE PORT_M32R_SIO | |
49 | #define PORT_INDEX(x) (x - PORT_M32R_BASE + 1) | |
50 | #define BAUD_RATE 115200 | |
51 | ||
52 | #include <linux/serial_core.h> | |
53 | #include "m32r_sio.h" | |
54 | #include "m32r_sio_reg.h" | |
55 | ||
56 | /* | |
57 | * Debugging. | |
58 | */ | |
59 | #if 0 | |
60 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
61 | #else | |
62 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
63 | #endif | |
64 | ||
65 | #if 0 | |
66 | #define DEBUG_INTR(fmt...) printk(fmt) | |
67 | #else | |
68 | #define DEBUG_INTR(fmt...) do { } while (0) | |
69 | #endif | |
70 | ||
71 | #define PASS_LIMIT 256 | |
72 | ||
73 | /* | |
74 | * We default to IRQ0 for the "no irq" hack. Some | |
75 | * machine types want others as well - they're free | |
76 | * to redefine this in their header file. | |
77 | */ | |
78 | #define is_real_interrupt(irq) ((irq) != 0) | |
79 | ||
80 | #include <asm/serial.h> | |
81 | ||
82 | /* Standard COM flags */ | |
59a675b2 | 83 | #define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST) |
1da177e4 LT |
84 | |
85 | /* | |
86 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
87 | * standard enumeration mechanism. Platforms that can find all | |
88 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
89 | */ | |
90 | #undef SERIAL_PORT_DFNS | |
91 | #if defined(CONFIG_PLAT_USRV) | |
92 | ||
93 | #define SERIAL_PORT_DFNS \ | |
94 | /* UART CLK PORT IRQ FLAGS */ \ | |
95 | { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \ | |
96 | { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */ | |
97 | ||
98 | #else /* !CONFIG_PLAT_USRV */ | |
99 | ||
100 | #if defined(CONFIG_SERIAL_M32R_PLDSIO) | |
101 | #define SERIAL_PORT_DFNS \ | |
102 | { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \ | |
103 | STD_COM_FLAGS }, /* ttyS0 */ | |
104 | #else | |
105 | #define SERIAL_PORT_DFNS \ | |
106 | { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \ | |
107 | STD_COM_FLAGS }, /* ttyS0 */ | |
108 | #endif | |
109 | ||
110 | #endif /* !CONFIG_PLAT_USRV */ | |
111 | ||
112 | static struct old_serial_port old_serial_port[] = { | |
113 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ | |
114 | }; | |
115 | ||
116 | #define UART_NR ARRAY_SIZE(old_serial_port) | |
117 | ||
118 | struct uart_sio_port { | |
119 | struct uart_port port; | |
120 | struct timer_list timer; /* "no irq" timer */ | |
121 | struct list_head list; /* ports on this IRQ */ | |
122 | unsigned short rev; | |
123 | unsigned char acr; | |
124 | unsigned char ier; | |
125 | unsigned char lcr; | |
126 | unsigned char mcr_mask; /* mask of user bits */ | |
127 | unsigned char mcr_force; /* mask of forced bits */ | |
128 | unsigned char lsr_break_flag; | |
129 | ||
130 | /* | |
131 | * We provide a per-port pm hook. | |
132 | */ | |
133 | void (*pm)(struct uart_port *port, | |
134 | unsigned int state, unsigned int old); | |
135 | }; | |
136 | ||
137 | struct irq_info { | |
138 | spinlock_t lock; | |
139 | struct list_head *head; | |
140 | }; | |
141 | ||
142 | static struct irq_info irq_lists[NR_IRQS]; | |
143 | ||
144 | /* | |
145 | * Here we define the default xmit fifo size used for each type of UART. | |
146 | */ | |
147 | static const struct serial_uart_config uart_config[] = { | |
148 | [PORT_UNKNOWN] = { | |
149 | .name = "unknown", | |
150 | .dfl_xmit_fifo_size = 1, | |
151 | .flags = 0, | |
152 | }, | |
153 | [PORT_INDEX(PORT_M32R_SIO)] = { | |
154 | .name = "M32RSIO", | |
155 | .dfl_xmit_fifo_size = 1, | |
156 | .flags = 0, | |
157 | }, | |
158 | }; | |
159 | ||
160 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
161 | ||
162 | #define __sio_in(x) inw((unsigned long)(x)) | |
163 | #define __sio_out(v,x) outw((v),(unsigned long)(x)) | |
164 | ||
165 | static inline void sio_set_baud_rate(unsigned long baud) | |
166 | { | |
167 | unsigned short sbaud; | |
168 | sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1; | |
169 | __sio_out(sbaud, PLD_ESIO0BAUR); | |
170 | } | |
171 | ||
172 | static void sio_reset(void) | |
173 | { | |
174 | unsigned short tmp; | |
175 | ||
176 | tmp = __sio_in(PLD_ESIO0RXB); | |
177 | tmp = __sio_in(PLD_ESIO0RXB); | |
178 | tmp = __sio_in(PLD_ESIO0CR); | |
179 | sio_set_baud_rate(BAUD_RATE); | |
180 | __sio_out(0x0300, PLD_ESIO0CR); | |
181 | __sio_out(0x0003, PLD_ESIO0CR); | |
182 | } | |
183 | ||
184 | static void sio_init(void) | |
185 | { | |
186 | unsigned short tmp; | |
187 | ||
188 | tmp = __sio_in(PLD_ESIO0RXB); | |
189 | tmp = __sio_in(PLD_ESIO0RXB); | |
190 | tmp = __sio_in(PLD_ESIO0CR); | |
191 | __sio_out(0x0300, PLD_ESIO0CR); | |
192 | __sio_out(0x0003, PLD_ESIO0CR); | |
193 | } | |
194 | ||
195 | static void sio_error(int *status) | |
196 | { | |
197 | printk("SIO0 error[%04x]\n", *status); | |
198 | do { | |
199 | sio_init(); | |
200 | } while ((*status = __sio_in(PLD_ESIO0CR)) != 3); | |
201 | } | |
202 | ||
203 | #else /* not CONFIG_SERIAL_M32R_PLDSIO */ | |
204 | ||
205 | #define __sio_in(x) inl(x) | |
206 | #define __sio_out(v,x) outl((v),(x)) | |
207 | ||
208 | static inline void sio_set_baud_rate(unsigned long baud) | |
209 | { | |
210 | unsigned long i, j; | |
211 | ||
212 | i = boot_cpu_data.bus_clock / (baud * 16); | |
213 | j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud; | |
214 | i -= 1; | |
215 | j = (j + 1) >> 1; | |
216 | ||
217 | __sio_out(i, M32R_SIO0_BAUR_PORTL); | |
218 | __sio_out(j, M32R_SIO0_RBAUR_PORTL); | |
219 | } | |
220 | ||
221 | static void sio_reset(void) | |
222 | { | |
223 | __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */ | |
224 | __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */ | |
225 | __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */ | |
226 | sio_set_baud_rate(BAUD_RATE); | |
227 | __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL); | |
228 | __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */ | |
229 | } | |
230 | ||
231 | static void sio_init(void) | |
232 | { | |
233 | unsigned int tmp; | |
234 | ||
235 | tmp = __sio_in(M32R_SIO0_RXB_PORTL); | |
236 | tmp = __sio_in(M32R_SIO0_RXB_PORTL); | |
237 | tmp = __sio_in(M32R_SIO0_STS_PORTL); | |
238 | __sio_out(0x00000003, M32R_SIO0_CR_PORTL); | |
239 | } | |
240 | ||
241 | static void sio_error(int *status) | |
242 | { | |
243 | printk("SIO0 error[%04x]\n", *status); | |
244 | do { | |
245 | sio_init(); | |
246 | } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3); | |
247 | } | |
248 | ||
249 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ | |
250 | ||
251 | static _INLINE_ unsigned int sio_in(struct uart_sio_port *up, int offset) | |
252 | { | |
253 | return __sio_in(up->port.iobase + offset); | |
254 | } | |
255 | ||
256 | static _INLINE_ void sio_out(struct uart_sio_port *up, int offset, int value) | |
257 | { | |
258 | __sio_out(value, up->port.iobase + offset); | |
259 | } | |
260 | ||
261 | static _INLINE_ unsigned int serial_in(struct uart_sio_port *up, int offset) | |
262 | { | |
263 | if (!offset) | |
264 | return 0; | |
265 | ||
266 | return __sio_in(offset); | |
267 | } | |
268 | ||
269 | static _INLINE_ void | |
270 | serial_out(struct uart_sio_port *up, int offset, int value) | |
271 | { | |
272 | if (!offset) | |
273 | return; | |
274 | ||
275 | __sio_out(value, offset); | |
276 | } | |
277 | ||
b129a8cc | 278 | static void m32r_sio_stop_tx(struct uart_port *port) |
1da177e4 LT |
279 | { |
280 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
281 | ||
282 | if (up->ier & UART_IER_THRI) { | |
283 | up->ier &= ~UART_IER_THRI; | |
284 | serial_out(up, UART_IER, up->ier); | |
285 | } | |
286 | } | |
287 | ||
b129a8cc | 288 | static void m32r_sio_start_tx(struct uart_port *port) |
1da177e4 LT |
289 | { |
290 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
291 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
292 | struct circ_buf *xmit = &up->port.info->xmit; | |
293 | ||
294 | if (!(up->ier & UART_IER_THRI)) { | |
295 | up->ier |= UART_IER_THRI; | |
296 | serial_out(up, UART_IER, up->ier); | |
297 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
298 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
299 | up->port.icount.tx++; | |
300 | } | |
301 | while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY); | |
302 | #else | |
303 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
304 | ||
305 | if (!(up->ier & UART_IER_THRI)) { | |
306 | up->ier |= UART_IER_THRI; | |
307 | serial_out(up, UART_IER, up->ier); | |
308 | } | |
309 | #endif | |
310 | } | |
311 | ||
312 | static void m32r_sio_stop_rx(struct uart_port *port) | |
313 | { | |
314 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
315 | ||
316 | up->ier &= ~UART_IER_RLSI; | |
317 | up->port.read_status_mask &= ~UART_LSR_DR; | |
318 | serial_out(up, UART_IER, up->ier); | |
319 | } | |
320 | ||
321 | static void m32r_sio_enable_ms(struct uart_port *port) | |
322 | { | |
323 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
324 | ||
325 | up->ier |= UART_IER_MSI; | |
326 | serial_out(up, UART_IER, up->ier); | |
327 | } | |
328 | ||
329 | static _INLINE_ void receive_chars(struct uart_sio_port *up, int *status, | |
330 | struct pt_regs *regs) | |
331 | { | |
332 | struct tty_struct *tty = up->port.info->tty; | |
333 | unsigned char ch; | |
33f0f88f | 334 | unsigned char flag; |
1da177e4 LT |
335 | int max_count = 256; |
336 | ||
337 | do { | |
1da177e4 | 338 | ch = sio_in(up, SIORXB); |
33f0f88f | 339 | flag = TTY_NORMAL; |
1da177e4 LT |
340 | up->port.icount.rx++; |
341 | ||
342 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
343 | UART_LSR_FE | UART_LSR_OE))) { | |
344 | /* | |
345 | * For statistics only | |
346 | */ | |
347 | if (*status & UART_LSR_BI) { | |
348 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
349 | up->port.icount.brk++; | |
350 | /* | |
351 | * We do the SysRQ and SAK checking | |
352 | * here because otherwise the break | |
353 | * may get masked by ignore_status_mask | |
354 | * or read_status_mask. | |
355 | */ | |
356 | if (uart_handle_break(&up->port)) | |
357 | goto ignore_char; | |
358 | } else if (*status & UART_LSR_PE) | |
359 | up->port.icount.parity++; | |
360 | else if (*status & UART_LSR_FE) | |
361 | up->port.icount.frame++; | |
362 | if (*status & UART_LSR_OE) | |
363 | up->port.icount.overrun++; | |
364 | ||
365 | /* | |
366 | * Mask off conditions which should be ingored. | |
367 | */ | |
368 | *status &= up->port.read_status_mask; | |
369 | ||
370 | if (up->port.line == up->port.cons->index) { | |
371 | /* Recover the break flag from console xmit */ | |
372 | *status |= up->lsr_break_flag; | |
373 | up->lsr_break_flag = 0; | |
374 | } | |
375 | ||
376 | if (*status & UART_LSR_BI) { | |
377 | DEBUG_INTR("handling break...."); | |
33f0f88f | 378 | flag = TTY_BREAK; |
1da177e4 | 379 | } else if (*status & UART_LSR_PE) |
33f0f88f | 380 | flag = TTY_PARITY; |
1da177e4 | 381 | else if (*status & UART_LSR_FE) |
33f0f88f | 382 | flag = TTY_FRAME; |
1da177e4 LT |
383 | } |
384 | if (uart_handle_sysrq_char(&up->port, ch, regs)) | |
385 | goto ignore_char; | |
33f0f88f AC |
386 | if ((*status & up->port.ignore_status_mask) == 0) |
387 | tty_insert_flip_char(tty, ch, flag); | |
388 | ||
389 | if (*status & UART_LSR_OE) { | |
1da177e4 LT |
390 | /* |
391 | * Overrun is special, since it's reported | |
392 | * immediately, and doesn't affect the current | |
393 | * character. | |
394 | */ | |
33f0f88f | 395 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); |
1da177e4 LT |
396 | } |
397 | ignore_char: | |
398 | *status = serial_in(up, UART_LSR); | |
399 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
400 | tty_flip_buffer_push(tty); | |
401 | } | |
402 | ||
403 | static _INLINE_ void transmit_chars(struct uart_sio_port *up) | |
404 | { | |
405 | struct circ_buf *xmit = &up->port.info->xmit; | |
406 | int count; | |
407 | ||
408 | if (up->port.x_char) { | |
409 | #ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */ | |
410 | serial_out(up, UART_TX, up->port.x_char); | |
411 | #endif | |
412 | up->port.icount.tx++; | |
413 | up->port.x_char = 0; | |
414 | return; | |
415 | } | |
416 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
b129a8cc | 417 | m32r_sio_stop_tx(&up->port); |
1da177e4 LT |
418 | return; |
419 | } | |
420 | ||
421 | count = up->port.fifosize; | |
422 | do { | |
423 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
424 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
425 | up->port.icount.tx++; | |
426 | if (uart_circ_empty(xmit)) | |
427 | break; | |
428 | while (!serial_in(up, UART_LSR) & UART_LSR_THRE); | |
429 | ||
430 | } while (--count > 0); | |
431 | ||
432 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
433 | uart_write_wakeup(&up->port); | |
434 | ||
435 | DEBUG_INTR("THRE..."); | |
436 | ||
437 | if (uart_circ_empty(xmit)) | |
b129a8cc | 438 | m32r_sio_stop_tx(&up->port); |
1da177e4 LT |
439 | } |
440 | ||
441 | /* | |
442 | * This handles the interrupt from one port. | |
443 | */ | |
444 | static inline void m32r_sio_handle_port(struct uart_sio_port *up, | |
445 | unsigned int status, struct pt_regs *regs) | |
446 | { | |
447 | DEBUG_INTR("status = %x...", status); | |
448 | ||
449 | if (status & 0x04) | |
450 | receive_chars(up, &status, regs); | |
451 | if (status & 0x01) | |
452 | transmit_chars(up); | |
453 | } | |
454 | ||
455 | /* | |
456 | * This is the serial driver's interrupt routine. | |
457 | * | |
458 | * Arjan thinks the old way was overly complex, so it got simplified. | |
459 | * Alan disagrees, saying that need the complexity to handle the weird | |
460 | * nature of ISA shared interrupts. (This is a special exception.) | |
461 | * | |
462 | * In order to handle ISA shared interrupts properly, we need to check | |
463 | * that all ports have been serviced, and therefore the ISA interrupt | |
464 | * line has been de-asserted. | |
465 | * | |
466 | * This means we need to loop through all ports. checking that they | |
467 | * don't have an interrupt pending. | |
468 | */ | |
469 | static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id, | |
470 | struct pt_regs *regs) | |
471 | { | |
472 | struct irq_info *i = dev_id; | |
473 | struct list_head *l, *end = NULL; | |
474 | int pass_counter = 0; | |
475 | ||
476 | DEBUG_INTR("m32r_sio_interrupt(%d)...", irq); | |
477 | ||
478 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
479 | // if (irq == PLD_IRQ_SIO0_SND) | |
480 | // irq = PLD_IRQ_SIO0_RCV; | |
481 | #else | |
482 | if (irq == M32R_IRQ_SIO0_S) | |
483 | irq = M32R_IRQ_SIO0_R; | |
484 | #endif | |
485 | ||
486 | spin_lock(&i->lock); | |
487 | ||
488 | l = i->head; | |
489 | do { | |
490 | struct uart_sio_port *up; | |
491 | unsigned int sts; | |
492 | ||
493 | up = list_entry(l, struct uart_sio_port, list); | |
494 | ||
495 | sts = sio_in(up, SIOSTS); | |
496 | if (sts & 0x5) { | |
497 | spin_lock(&up->port.lock); | |
498 | m32r_sio_handle_port(up, sts, regs); | |
499 | spin_unlock(&up->port.lock); | |
500 | ||
501 | end = NULL; | |
502 | } else if (end == NULL) | |
503 | end = l; | |
504 | ||
505 | l = l->next; | |
506 | ||
507 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
508 | if (sts & 0xe0) | |
509 | sio_error(&sts); | |
510 | break; | |
511 | } | |
512 | } while (l != end); | |
513 | ||
514 | spin_unlock(&i->lock); | |
515 | ||
516 | DEBUG_INTR("end.\n"); | |
517 | ||
518 | return IRQ_HANDLED; | |
519 | } | |
520 | ||
521 | /* | |
522 | * To support ISA shared interrupts, we need to have one interrupt | |
523 | * handler that ensures that the IRQ line has been deasserted | |
524 | * before returning. Failing to do this will result in the IRQ | |
525 | * line being stuck active, and, since ISA irqs are edge triggered, | |
526 | * no more IRQs will be seen. | |
527 | */ | |
528 | static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up) | |
529 | { | |
530 | spin_lock_irq(&i->lock); | |
531 | ||
532 | if (!list_empty(i->head)) { | |
533 | if (i->head == &up->list) | |
534 | i->head = i->head->next; | |
535 | list_del(&up->list); | |
536 | } else { | |
537 | BUG_ON(i->head != &up->list); | |
538 | i->head = NULL; | |
539 | } | |
540 | ||
541 | spin_unlock_irq(&i->lock); | |
542 | } | |
543 | ||
544 | static int serial_link_irq_chain(struct uart_sio_port *up) | |
545 | { | |
546 | struct irq_info *i = irq_lists + up->port.irq; | |
547 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0; | |
548 | ||
549 | spin_lock_irq(&i->lock); | |
550 | ||
551 | if (i->head) { | |
552 | list_add(&up->list, i->head); | |
553 | spin_unlock_irq(&i->lock); | |
554 | ||
555 | ret = 0; | |
556 | } else { | |
557 | INIT_LIST_HEAD(&up->list); | |
558 | i->head = &up->list; | |
559 | spin_unlock_irq(&i->lock); | |
560 | ||
561 | ret = request_irq(up->port.irq, m32r_sio_interrupt, | |
562 | irq_flags, "SIO0-RX", i); | |
563 | ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt, | |
564 | irq_flags, "SIO0-TX", i); | |
565 | if (ret < 0) | |
566 | serial_do_unlink(i, up); | |
567 | } | |
568 | ||
569 | return ret; | |
570 | } | |
571 | ||
572 | static void serial_unlink_irq_chain(struct uart_sio_port *up) | |
573 | { | |
574 | struct irq_info *i = irq_lists + up->port.irq; | |
575 | ||
576 | BUG_ON(i->head == NULL); | |
577 | ||
578 | if (list_empty(i->head)) { | |
579 | free_irq(up->port.irq, i); | |
580 | free_irq(up->port.irq + 1, i); | |
581 | } | |
582 | ||
583 | serial_do_unlink(i, up); | |
584 | } | |
585 | ||
586 | /* | |
587 | * This function is used to handle ports that do not have an interrupt. | |
588 | */ | |
589 | static void m32r_sio_timeout(unsigned long data) | |
590 | { | |
591 | struct uart_sio_port *up = (struct uart_sio_port *)data; | |
592 | unsigned int timeout; | |
593 | unsigned int sts; | |
594 | ||
595 | sts = sio_in(up, SIOSTS); | |
596 | if (sts & 0x5) { | |
597 | spin_lock(&up->port.lock); | |
598 | m32r_sio_handle_port(up, sts, NULL); | |
599 | spin_unlock(&up->port.lock); | |
600 | } | |
601 | ||
602 | timeout = up->port.timeout; | |
603 | timeout = timeout > 6 ? (timeout / 2 - 2) : 1; | |
604 | mod_timer(&up->timer, jiffies + timeout); | |
605 | } | |
606 | ||
607 | static unsigned int m32r_sio_tx_empty(struct uart_port *port) | |
608 | { | |
609 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
610 | unsigned long flags; | |
611 | unsigned int ret; | |
612 | ||
613 | spin_lock_irqsave(&up->port.lock, flags); | |
614 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
615 | spin_unlock_irqrestore(&up->port.lock, flags); | |
616 | ||
617 | return ret; | |
618 | } | |
619 | ||
620 | static unsigned int m32r_sio_get_mctrl(struct uart_port *port) | |
621 | { | |
622 | return 0; | |
623 | } | |
624 | ||
625 | static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
626 | { | |
627 | ||
628 | } | |
629 | ||
630 | static void m32r_sio_break_ctl(struct uart_port *port, int break_state) | |
631 | { | |
632 | ||
633 | } | |
634 | ||
635 | static int m32r_sio_startup(struct uart_port *port) | |
636 | { | |
637 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
638 | int retval; | |
639 | ||
640 | sio_init(); | |
641 | ||
642 | /* | |
643 | * If the "interrupt" for this port doesn't correspond with any | |
644 | * hardware interrupt, we use a timer-based system. The original | |
645 | * driver used to do this with IRQ0. | |
646 | */ | |
647 | if (!is_real_interrupt(up->port.irq)) { | |
648 | unsigned int timeout = up->port.timeout; | |
649 | ||
650 | timeout = timeout > 6 ? (timeout / 2 - 2) : 1; | |
651 | ||
652 | up->timer.data = (unsigned long)up; | |
653 | mod_timer(&up->timer, jiffies + timeout); | |
654 | } else { | |
655 | retval = serial_link_irq_chain(up); | |
656 | if (retval) | |
657 | return retval; | |
658 | } | |
659 | ||
660 | /* | |
661 | * Finally, enable interrupts. Note: Modem status interrupts | |
662 | * are set via set_termios(), which will be occurring imminently | |
663 | * anyway, so we don't enable them here. | |
664 | * - M32R_SIO: 0x0c | |
665 | * - M32R_PLDSIO: 0x04 | |
666 | */ | |
667 | up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; | |
668 | sio_out(up, SIOTRCR, up->ier); | |
669 | ||
670 | /* | |
671 | * And clear the interrupt registers again for luck. | |
672 | */ | |
673 | sio_reset(); | |
674 | ||
675 | return 0; | |
676 | } | |
677 | ||
678 | static void m32r_sio_shutdown(struct uart_port *port) | |
679 | { | |
680 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
681 | ||
682 | /* | |
683 | * Disable interrupts from this port | |
684 | */ | |
685 | up->ier = 0; | |
686 | sio_out(up, SIOTRCR, 0); | |
687 | ||
688 | /* | |
689 | * Disable break condition and FIFOs | |
690 | */ | |
691 | ||
692 | sio_init(); | |
693 | ||
694 | if (!is_real_interrupt(up->port.irq)) | |
695 | del_timer_sync(&up->timer); | |
696 | else | |
697 | serial_unlink_irq_chain(up); | |
698 | } | |
699 | ||
700 | static unsigned int m32r_sio_get_divisor(struct uart_port *port, | |
701 | unsigned int baud) | |
702 | { | |
703 | return uart_get_divisor(port, baud); | |
704 | } | |
705 | ||
706 | static void m32r_sio_set_termios(struct uart_port *port, | |
707 | struct termios *termios, struct termios *old) | |
708 | { | |
709 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
710 | unsigned char cval = 0; | |
711 | unsigned long flags; | |
712 | unsigned int baud, quot; | |
713 | ||
714 | switch (termios->c_cflag & CSIZE) { | |
715 | case CS5: | |
0a8b80c5 | 716 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
717 | break; |
718 | case CS6: | |
0a8b80c5 | 719 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
720 | break; |
721 | case CS7: | |
0a8b80c5 | 722 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
723 | break; |
724 | default: | |
725 | case CS8: | |
0a8b80c5 | 726 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
727 | break; |
728 | } | |
729 | ||
730 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 731 | cval |= UART_LCR_STOP; |
1da177e4 LT |
732 | if (termios->c_cflag & PARENB) |
733 | cval |= UART_LCR_PARITY; | |
734 | if (!(termios->c_cflag & PARODD)) | |
735 | cval |= UART_LCR_EPAR; | |
736 | #ifdef CMSPAR | |
737 | if (termios->c_cflag & CMSPAR) | |
738 | cval |= UART_LCR_SPAR; | |
739 | #endif | |
740 | ||
741 | /* | |
742 | * Ask the core to calculate the divisor for us. | |
743 | */ | |
744 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
745 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4); | |
746 | #else | |
747 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
748 | #endif | |
749 | quot = m32r_sio_get_divisor(port, baud); | |
750 | ||
751 | /* | |
752 | * Ok, we're now changing the port state. Do it with | |
753 | * interrupts disabled. | |
754 | */ | |
755 | spin_lock_irqsave(&up->port.lock, flags); | |
756 | ||
757 | sio_set_baud_rate(baud); | |
758 | ||
759 | /* | |
760 | * Update the per-port timeout. | |
761 | */ | |
762 | uart_update_timeout(port, termios->c_cflag, baud); | |
763 | ||
764 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
765 | if (termios->c_iflag & INPCK) | |
766 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
767 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
768 | up->port.read_status_mask |= UART_LSR_BI; | |
769 | ||
770 | /* | |
771 | * Characteres to ignore | |
772 | */ | |
773 | up->port.ignore_status_mask = 0; | |
774 | if (termios->c_iflag & IGNPAR) | |
775 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
776 | if (termios->c_iflag & IGNBRK) { | |
777 | up->port.ignore_status_mask |= UART_LSR_BI; | |
778 | /* | |
779 | * If we're ignoring parity and break indicators, | |
780 | * ignore overruns too (for real raw support). | |
781 | */ | |
782 | if (termios->c_iflag & IGNPAR) | |
783 | up->port.ignore_status_mask |= UART_LSR_OE; | |
784 | } | |
785 | ||
786 | /* | |
787 | * ignore all characters if CREAD is not set | |
788 | */ | |
789 | if ((termios->c_cflag & CREAD) == 0) | |
790 | up->port.ignore_status_mask |= UART_LSR_DR; | |
791 | ||
792 | /* | |
793 | * CTS flow control flag and modem status interrupts | |
794 | */ | |
795 | up->ier &= ~UART_IER_MSI; | |
796 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
797 | up->ier |= UART_IER_MSI; | |
798 | ||
799 | serial_out(up, UART_IER, up->ier); | |
800 | ||
801 | up->lcr = cval; /* Save LCR */ | |
802 | spin_unlock_irqrestore(&up->port.lock, flags); | |
803 | } | |
804 | ||
805 | static void m32r_sio_pm(struct uart_port *port, unsigned int state, | |
806 | unsigned int oldstate) | |
807 | { | |
808 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
809 | ||
810 | if (up->pm) | |
811 | up->pm(port, state, oldstate); | |
812 | } | |
813 | ||
814 | /* | |
815 | * Resource handling. This is complicated by the fact that resources | |
816 | * depend on the port type. Maybe we should be claiming the standard | |
817 | * 8250 ports, and then trying to get other resources as necessary? | |
818 | */ | |
819 | static int | |
820 | m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res) | |
821 | { | |
822 | unsigned int size = 8 << up->port.regshift; | |
823 | #ifndef CONFIG_SERIAL_M32R_PLDSIO | |
824 | unsigned long start; | |
825 | #endif | |
826 | int ret = 0; | |
827 | ||
828 | switch (up->port.iotype) { | |
829 | case UPIO_MEM: | |
830 | if (up->port.mapbase) { | |
831 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
832 | *res = request_mem_region(up->port.mapbase, size, "serial"); | |
833 | #else | |
834 | start = up->port.mapbase; | |
835 | *res = request_mem_region(start, size, "serial"); | |
836 | #endif | |
837 | if (!*res) | |
838 | ret = -EBUSY; | |
839 | } | |
840 | break; | |
841 | ||
842 | case UPIO_PORT: | |
843 | *res = request_region(up->port.iobase, size, "serial"); | |
844 | if (!*res) | |
845 | ret = -EBUSY; | |
846 | break; | |
847 | } | |
848 | return ret; | |
849 | } | |
850 | ||
851 | static void m32r_sio_release_port(struct uart_port *port) | |
852 | { | |
853 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
854 | unsigned long start, offset = 0, size = 0; | |
855 | ||
856 | size <<= up->port.regshift; | |
857 | ||
858 | switch (up->port.iotype) { | |
859 | case UPIO_MEM: | |
860 | if (up->port.mapbase) { | |
861 | /* | |
862 | * Unmap the area. | |
863 | */ | |
864 | iounmap(up->port.membase); | |
865 | up->port.membase = NULL; | |
866 | ||
867 | start = up->port.mapbase; | |
868 | ||
869 | if (size) | |
870 | release_mem_region(start + offset, size); | |
871 | release_mem_region(start, 8 << up->port.regshift); | |
872 | } | |
873 | break; | |
874 | ||
875 | case UPIO_PORT: | |
876 | start = up->port.iobase; | |
877 | ||
878 | if (size) | |
879 | release_region(start + offset, size); | |
880 | release_region(start + offset, 8 << up->port.regshift); | |
881 | break; | |
882 | ||
883 | default: | |
884 | break; | |
885 | } | |
886 | } | |
887 | ||
888 | static int m32r_sio_request_port(struct uart_port *port) | |
889 | { | |
890 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
891 | struct resource *res = NULL; | |
892 | int ret = 0; | |
893 | ||
894 | ret = m32r_sio_request_std_resource(up, &res); | |
895 | ||
896 | /* | |
897 | * If we have a mapbase, then request that as well. | |
898 | */ | |
899 | if (ret == 0 && up->port.flags & UPF_IOREMAP) { | |
900 | int size = res->end - res->start + 1; | |
901 | ||
902 | up->port.membase = ioremap(up->port.mapbase, size); | |
903 | if (!up->port.membase) | |
904 | ret = -ENOMEM; | |
905 | } | |
906 | ||
907 | if (ret < 0) { | |
908 | if (res) | |
909 | release_resource(res); | |
910 | } | |
911 | ||
912 | return ret; | |
913 | } | |
914 | ||
915 | static void m32r_sio_config_port(struct uart_port *port, int flags) | |
916 | { | |
917 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
918 | ||
919 | spin_lock_irqsave(&up->port.lock, flags); | |
920 | ||
921 | up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1); | |
922 | up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size; | |
923 | ||
924 | spin_unlock_irqrestore(&up->port.lock, flags); | |
925 | } | |
926 | ||
927 | static int | |
928 | m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser) | |
929 | { | |
930 | if (ser->irq >= NR_IRQS || ser->irq < 0 || | |
931 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || | |
932 | ser->type >= ARRAY_SIZE(uart_config)) | |
933 | return -EINVAL; | |
934 | return 0; | |
935 | } | |
936 | ||
937 | static const char * | |
938 | m32r_sio_type(struct uart_port *port) | |
939 | { | |
940 | int type = port->type; | |
941 | ||
942 | if (type >= ARRAY_SIZE(uart_config)) | |
943 | type = 0; | |
944 | return uart_config[type].name; | |
945 | } | |
946 | ||
947 | static struct uart_ops m32r_sio_pops = { | |
948 | .tx_empty = m32r_sio_tx_empty, | |
949 | .set_mctrl = m32r_sio_set_mctrl, | |
950 | .get_mctrl = m32r_sio_get_mctrl, | |
951 | .stop_tx = m32r_sio_stop_tx, | |
952 | .start_tx = m32r_sio_start_tx, | |
953 | .stop_rx = m32r_sio_stop_rx, | |
954 | .enable_ms = m32r_sio_enable_ms, | |
955 | .break_ctl = m32r_sio_break_ctl, | |
956 | .startup = m32r_sio_startup, | |
957 | .shutdown = m32r_sio_shutdown, | |
958 | .set_termios = m32r_sio_set_termios, | |
959 | .pm = m32r_sio_pm, | |
960 | .type = m32r_sio_type, | |
961 | .release_port = m32r_sio_release_port, | |
962 | .request_port = m32r_sio_request_port, | |
963 | .config_port = m32r_sio_config_port, | |
964 | .verify_port = m32r_sio_verify_port, | |
965 | }; | |
966 | ||
967 | static struct uart_sio_port m32r_sio_ports[UART_NR]; | |
968 | ||
969 | static void __init m32r_sio_init_ports(void) | |
970 | { | |
971 | struct uart_sio_port *up; | |
972 | static int first = 1; | |
973 | int i; | |
974 | ||
975 | if (!first) | |
976 | return; | |
977 | first = 0; | |
978 | ||
979 | for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port); | |
980 | i++, up++) { | |
981 | up->port.iobase = old_serial_port[i].port; | |
982 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); | |
983 | up->port.uartclk = old_serial_port[i].baud_base * 16; | |
984 | up->port.flags = old_serial_port[i].flags; | |
985 | up->port.membase = old_serial_port[i].iomem_base; | |
986 | up->port.iotype = old_serial_port[i].io_type; | |
987 | up->port.regshift = old_serial_port[i].iomem_reg_shift; | |
988 | up->port.ops = &m32r_sio_pops; | |
989 | } | |
990 | } | |
991 | ||
992 | static void __init m32r_sio_register_ports(struct uart_driver *drv) | |
993 | { | |
994 | int i; | |
995 | ||
996 | m32r_sio_init_ports(); | |
997 | ||
998 | for (i = 0; i < UART_NR; i++) { | |
999 | struct uart_sio_port *up = &m32r_sio_ports[i]; | |
1000 | ||
1001 | up->port.line = i; | |
1002 | up->port.ops = &m32r_sio_pops; | |
1003 | init_timer(&up->timer); | |
1004 | up->timer.function = m32r_sio_timeout; | |
1005 | ||
1006 | /* | |
1007 | * ALPHA_KLUDGE_MCR needs to be killed. | |
1008 | */ | |
1009 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | |
1010 | up->mcr_force = ALPHA_KLUDGE_MCR; | |
1011 | ||
1012 | uart_add_one_port(drv, &up->port); | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | #ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE | |
1017 | ||
1018 | /* | |
1019 | * Wait for transmitter & holding register to empty | |
1020 | */ | |
1021 | static inline void wait_for_xmitr(struct uart_sio_port *up) | |
1022 | { | |
1023 | unsigned int status, tmout = 10000; | |
1024 | ||
1025 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1026 | do { | |
1027 | status = sio_in(up, SIOSTS); | |
1028 | ||
1029 | if (--tmout == 0) | |
1030 | break; | |
1031 | udelay(1); | |
1032 | } while ((status & UART_EMPTY) != UART_EMPTY); | |
1033 | ||
1034 | /* Wait up to 1s for flow control if necessary */ | |
1035 | if (up->port.flags & UPF_CONS_FLOW) { | |
1036 | tmout = 1000000; | |
1037 | while (--tmout) | |
1038 | udelay(1); | |
1039 | } | |
1040 | } | |
1041 | ||
d358788f RK |
1042 | static void m32r_sio_console_putchar(struct uart_port *port, int ch) |
1043 | { | |
1044 | struct uart_sio_port *up = (struct uart_sio_port *)port; | |
1045 | ||
1046 | wait_for_xmitr(up); | |
1047 | sio_out(up, SIOTXB, ch); | |
1048 | } | |
1049 | ||
1da177e4 LT |
1050 | /* |
1051 | * Print a string to the serial port trying not to disturb | |
1052 | * any possible real use of the port... | |
1053 | * | |
1054 | * The console_lock must be held when we get here. | |
1055 | */ | |
1056 | static void m32r_sio_console_write(struct console *co, const char *s, | |
1057 | unsigned int count) | |
1058 | { | |
1059 | struct uart_sio_port *up = &m32r_sio_ports[co->index]; | |
1060 | unsigned int ier; | |
1061 | int i; | |
1062 | ||
1063 | /* | |
1064 | * First save the UER then disable the interrupts | |
1065 | */ | |
1066 | ier = sio_in(up, SIOTRCR); | |
1067 | sio_out(up, SIOTRCR, 0); | |
1068 | ||
d358788f | 1069 | uart_console_write(&up->port, s, count, m32r_sio_console_putchar); |
1da177e4 LT |
1070 | |
1071 | /* | |
1072 | * Finally, wait for transmitter to become empty | |
1073 | * and restore the IER | |
1074 | */ | |
1075 | wait_for_xmitr(up); | |
1076 | sio_out(up, SIOTRCR, ier); | |
1077 | } | |
1078 | ||
1079 | static int __init m32r_sio_console_setup(struct console *co, char *options) | |
1080 | { | |
1081 | struct uart_port *port; | |
1082 | int baud = 9600; | |
1083 | int bits = 8; | |
1084 | int parity = 'n'; | |
1085 | int flow = 'n'; | |
1086 | ||
1087 | /* | |
1088 | * Check whether an invalid uart number has been specified, and | |
1089 | * if so, search for the first available port that does have | |
1090 | * console support. | |
1091 | */ | |
1092 | if (co->index >= UART_NR) | |
1093 | co->index = 0; | |
1094 | port = &m32r_sio_ports[co->index].port; | |
1095 | ||
1096 | /* | |
1097 | * Temporary fix. | |
1098 | */ | |
1099 | spin_lock_init(&port->lock); | |
1100 | ||
1101 | if (options) | |
1102 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1103 | ||
1104 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1105 | } | |
1106 | ||
a828b8e4 | 1107 | static struct uart_driver m32r_sio_reg; |
1da177e4 LT |
1108 | static struct console m32r_sio_console = { |
1109 | .name = "ttyS", | |
1110 | .write = m32r_sio_console_write, | |
1111 | .device = uart_console_device, | |
1112 | .setup = m32r_sio_console_setup, | |
1113 | .flags = CON_PRINTBUFFER, | |
1114 | .index = -1, | |
1115 | .data = &m32r_sio_reg, | |
1116 | }; | |
1117 | ||
1118 | static int __init m32r_sio_console_init(void) | |
1119 | { | |
1120 | sio_reset(); | |
1121 | sio_init(); | |
1122 | m32r_sio_init_ports(); | |
1123 | register_console(&m32r_sio_console); | |
1124 | return 0; | |
1125 | } | |
1126 | console_initcall(m32r_sio_console_init); | |
1127 | ||
1128 | #define M32R_SIO_CONSOLE &m32r_sio_console | |
1129 | #else | |
1130 | #define M32R_SIO_CONSOLE NULL | |
1131 | #endif | |
1132 | ||
1133 | static struct uart_driver m32r_sio_reg = { | |
1134 | .owner = THIS_MODULE, | |
1135 | .driver_name = "sio", | |
1136 | .devfs_name = "tts/", | |
1137 | .dev_name = "ttyS", | |
1138 | .major = TTY_MAJOR, | |
1139 | .minor = 64, | |
1140 | .nr = UART_NR, | |
1141 | .cons = M32R_SIO_CONSOLE, | |
1142 | }; | |
1143 | ||
1144 | /** | |
1145 | * m32r_sio_suspend_port - suspend one serial port | |
1146 | * @line: serial line number | |
1147 | * | |
1148 | * Suspend one serial port. | |
1149 | */ | |
1150 | void m32r_sio_suspend_port(int line) | |
1151 | { | |
1152 | uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port); | |
1153 | } | |
1154 | ||
1155 | /** | |
1156 | * m32r_sio_resume_port - resume one serial port | |
1157 | * @line: serial line number | |
1158 | * | |
1159 | * Resume one serial port. | |
1160 | */ | |
1161 | void m32r_sio_resume_port(int line) | |
1162 | { | |
1163 | uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port); | |
1164 | } | |
1165 | ||
1166 | static int __init m32r_sio_init(void) | |
1167 | { | |
1168 | int ret, i; | |
1169 | ||
1170 | printk(KERN_INFO "Serial: M32R SIO driver $Revision: 1.11 $ "); | |
1171 | ||
1172 | for (i = 0; i < NR_IRQS; i++) | |
1173 | spin_lock_init(&irq_lists[i].lock); | |
1174 | ||
1175 | ret = uart_register_driver(&m32r_sio_reg); | |
1176 | if (ret >= 0) | |
1177 | m32r_sio_register_ports(&m32r_sio_reg); | |
1178 | ||
1179 | return ret; | |
1180 | } | |
1181 | ||
1182 | static void __exit m32r_sio_exit(void) | |
1183 | { | |
1184 | int i; | |
1185 | ||
1186 | for (i = 0; i < UART_NR; i++) | |
1187 | uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port); | |
1188 | ||
1189 | uart_unregister_driver(&m32r_sio_reg); | |
1190 | } | |
1191 | ||
1192 | module_init(m32r_sio_init); | |
1193 | module_exit(m32r_sio_exit); | |
1194 | ||
1195 | EXPORT_SYMBOL(m32r_sio_suspend_port); | |
1196 | EXPORT_SYMBOL(m32r_sio_resume_port); | |
1197 | ||
1198 | MODULE_LICENSE("GPL"); | |
1199 | MODULE_DESCRIPTION("Generic M32R SIO serial driver $Revision: 1.11 $"); |