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d843fc6e
FT		 1/*
2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
3 *
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
5 *
06c77e21 6 * (C) Copyright 2010 Intel Corporation
d843fc6e
FT		 7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
d843fc6e 14/* Notes:
06c77e21
FT		 15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
d843fc6e 18 *
06c77e21 19 * 2. In A0 stepping, UART will not support TX half empty flag
d843fc6e 20 *
06c77e21
FT		 21 * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
22 * asserted, only when the HW is reset the DDCD and DDSR will
23 * be triggered
d843fc6e
FT		 24 */
25
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/console.h>
29#include <linux/sysrq.h>
30#include <linux/serial_reg.h>
31#include <linux/circ_buf.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/tty.h>
35#include <linux/tty_flip.h>
36#include <linux/serial_core.h>
37#include <linux/serial_mfd.h>
38#include <linux/dma-mapping.h>
39#include <linux/pci.h>
40#include <linux/io.h>
41#include <linux/debugfs.h>
42
43#define MFD_HSU_A0_STEPPING 1
44
45#define HSU_DMA_BUF_SIZE 2048
46
47#define chan_readl(chan, offset) readl(chan->reg + offset)
48#define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
49
50#define mfd_readl(obj, offset) readl(obj->reg + offset)
51#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
52
669b7a09
FT		 53#define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10)
54
d843fc6e
FT		 55struct hsu_dma_buffer {
56 u8 *buf;
57 dma_addr_t dma_addr;
58 u32 dma_size;
59 u32 ofs;
60};
61
62struct hsu_dma_chan {
63 u32 id;
06c77e21 64 enum dma_data_direction dirt;
d843fc6e 65 struct uart_hsu_port *uport;
669b7a09
FT		 66 void __iomem *reg;
67 struct timer_list rx_timer; /* only needed by RX channel */
d843fc6e
FT		 68};
69
70struct uart_hsu_port {
71 struct uart_port port;
72 unsigned char ier;
73 unsigned char lcr;
74 unsigned char mcr;
75 unsigned int lsr_break_flag;
76 char name[12];
77 int index;
78 struct device *dev;
79
80 struct hsu_dma_chan *txc;
81 struct hsu_dma_chan *rxc;
82 struct hsu_dma_buffer txbuf;
83 struct hsu_dma_buffer rxbuf;
84 int use_dma; /* flag for DMA/PIO */
85 int running;
86 int dma_tx_on;
87};
88
89/* Top level data structure of HSU */
90struct hsu_port {
d843fc6e
FT		 91 void __iomem *reg;
92 unsigned long paddr;
93 unsigned long iolen;
94 u32 irq;
95
96 struct uart_hsu_port port[3];
97 struct hsu_dma_chan chans[10];
98
d843fc6e 99 struct dentry *debugfs;
d843fc6e
FT		 100};
101
d843fc6e
FT		 102static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
103{
104 unsigned int val;
105
106 if (offset > UART_MSR) {
107 offset <<= 2;
108 val = readl(up->port.membase + offset);
109 } else
110 val = (unsigned int)readb(up->port.membase + offset);
111
112 return val;
113}
114
115static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
116{
117 if (offset > UART_MSR) {
118 offset <<= 2;
119 writel(value, up->port.membase + offset);
120 } else {
121 unsigned char val = value & 0xff;
122 writeb(val, up->port.membase + offset);
123 }
124}
125
126#ifdef CONFIG_DEBUG_FS
127
128#define HSU_REGS_BUFSIZE 1024
129
130static int hsu_show_regs_open(struct inode *inode, struct file *file)
131{
132 file->private_data = inode->i_private;
133 return 0;
134}
135
136static ssize_t port_show_regs(struct file *file, char __user *user_buf,
137 size_t count, loff_t *ppos)
138{
139 struct uart_hsu_port *up = file->private_data;
140 char *buf;
141 u32 len = 0;
142 ssize_t ret;
143
144 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
145 if (!buf)
146 return 0;
147
148 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
149 "MFD HSU port[%d] regs:\n", up->index);
150
151 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
152 "=================================\n");
153 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
154 "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
155 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
156 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
157 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
158 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
159 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
160 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
161 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
162 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
163 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
164 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
165 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
166 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
167 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
168 "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
169 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
170 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
171 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
172 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
173
174 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
175 kfree(buf);
176 return ret;
177}
178
179static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
180 size_t count, loff_t *ppos)
181{
182 struct hsu_dma_chan *chan = file->private_data;
183 char *buf;
184 u32 len = 0;
185 ssize_t ret;
186
187 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
188 if (!buf)
189 return 0;
190
191 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
192 "MFD HSU DMA channel [%d] regs:\n", chan->id);
193
194 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
195 "=================================\n");
196 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
197 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
198 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
199 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
200 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
201 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
202 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
203 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
204 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
205 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
206 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
207 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
208 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
209 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
210 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
211 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
212 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
213 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
214 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
215 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
216 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
217 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
218 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
219 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
220
221 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
222 kfree(buf);
223 return ret;
224}
225
226static const struct file_operations port_regs_ops = {
227 .owner = THIS_MODULE,
228 .open = hsu_show_regs_open,
229 .read = port_show_regs,
6038f373 230 .llseek = default_llseek,
d843fc6e
FT		 231};
232
233static const struct file_operations dma_regs_ops = {
234 .owner = THIS_MODULE,
235 .open = hsu_show_regs_open,
236 .read = dma_show_regs,
6038f373 237 .llseek = default_llseek,
d843fc6e
FT		 238};
239
240static int hsu_debugfs_init(struct hsu_port *hsu)
241{
242 int i;
243 char name[32];
244
245 hsu->debugfs = debugfs_create_dir("hsu", NULL);
246 if (!hsu->debugfs)
247 return -ENOMEM;
248
249 for (i = 0; i < 3; i++) {
250 snprintf(name, sizeof(name), "port_%d_regs", i);
251 debugfs_create_file(name, S_IFREG | S_IRUGO,
252 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
253 }
254
255 for (i = 0; i < 6; i++) {
256 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
257 debugfs_create_file(name, S_IFREG | S_IRUGO,
258 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
259 }
260
261 return 0;
262}
263
264static void hsu_debugfs_remove(struct hsu_port *hsu)
265{
266 if (hsu->debugfs)
267 debugfs_remove_recursive(hsu->debugfs);
268}
269
270#else
271static inline int hsu_debugfs_init(struct hsu_port *hsu)
272{
273 return 0;
274}
275
276static inline void hsu_debugfs_remove(struct hsu_port *hsu)
277{
278}
279#endif /* CONFIG_DEBUG_FS */
280
281static void serial_hsu_enable_ms(struct uart_port *port)
282{
283 struct uart_hsu_port *up =
284 container_of(port, struct uart_hsu_port, port);
285
286 up->ier |= UART_IER_MSI;
287 serial_out(up, UART_IER, up->ier);
288}
289
290void hsu_dma_tx(struct uart_hsu_port *up)
291{
292 struct circ_buf *xmit = &up->port.state->xmit;
293 struct hsu_dma_buffer *dbuf = &up->txbuf;
294 int count;
295
296 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
297 if (up->dma_tx_on)
298 return;
299
300 /* Update the circ buf info */
301 xmit->tail += dbuf->ofs;
302 xmit->tail &= UART_XMIT_SIZE - 1;
303
304 up->port.icount.tx += dbuf->ofs;
305 dbuf->ofs = 0;
306
307 /* Disable the channel */
308 chan_writel(up->txc, HSU_CH_CR, 0x0);
309
310 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
311 dma_sync_single_for_device(up->port.dev,
312 dbuf->dma_addr,
313 dbuf->dma_size,
314 DMA_TO_DEVICE);
315
316 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
317 dbuf->ofs = count;
318
319 /* Reprogram the channel */
320 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
321 chan_writel(up->txc, HSU_CH_D0TSR, count);
322
323 /* Reenable the channel */
324 chan_writel(up->txc, HSU_CH_DCR, 0x1
325 | (0x1 << 8)
326 | (0x1 << 16)
327 | (0x1 << 24));
d843fc6e
FT		 328 up->dma_tx_on = 1;
329 chan_writel(up->txc, HSU_CH_CR, 0x1);
330 }
331
332 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
333 uart_write_wakeup(&up->port);
334}
335
336/* The buffer is already cache coherent */
337void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
338{
d843fc6e
FT		 339 dbuf->ofs = 0;
340
341 chan_writel(rxc, HSU_CH_BSR, 32);
342 chan_writel(rxc, HSU_CH_MOTSR, 4);
343
344 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
345 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
346 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
347 | (0x1 << 16)
348 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
349 );
350 chan_writel(rxc, HSU_CH_CR, 0x3);
669b7a09
FT		 351
352 mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
d843fc6e
FT		 353}
354
355/* Protected by spin_lock_irqsave(port->lock) */
356static void serial_hsu_start_tx(struct uart_port *port)
357{
358 struct uart_hsu_port *up =
359 container_of(port, struct uart_hsu_port, port);
360
361 if (up->use_dma) {
362 hsu_dma_tx(up);
363 } else if (!(up->ier & UART_IER_THRI)) {
364 up->ier |= UART_IER_THRI;
365 serial_out(up, UART_IER, up->ier);
366 }
367}
368
369static void serial_hsu_stop_tx(struct uart_port *port)
370{
371 struct uart_hsu_port *up =
372 container_of(port, struct uart_hsu_port, port);
373 struct hsu_dma_chan *txc = up->txc;
374
375 if (up->use_dma)
376 chan_writel(txc, HSU_CH_CR, 0x0);
377 else if (up->ier & UART_IER_THRI) {
378 up->ier &= ~UART_IER_THRI;
379 serial_out(up, UART_IER, up->ier);
380 }
381}
382
383/* This is always called in spinlock protected mode, so
384 * modify timeout timer is safe here */
385void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
386{
387 struct hsu_dma_buffer *dbuf = &up->rxbuf;
388 struct hsu_dma_chan *chan = up->rxc;
389 struct uart_port *port = &up->port;
390 struct tty_struct *tty = port->state->port.tty;
391 int count;
392
393 if (!tty)
394 return;
395
396 /*
06c77e21 397 * First need to know how many is already transferred,
d843fc6e
FT		 398 * then check if its a timeout DMA irq, and return
399 * the trail bytes out, push them up and reenable the
06c77e21 400 * channel
d843fc6e
FT		 401 */
402
06c77e21 403 /* Timeout IRQ, need wait some time, see Errata 2 */
d843fc6e
FT		 404 if (int_sts & 0xf00)
405 udelay(2);
406
407 /* Stop the channel */
408 chan_writel(chan, HSU_CH_CR, 0x0);
409
d843fc6e 410 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
669b7a09 411 if (!count) {
06c77e21 412 /* Restart the channel before we leave */
669b7a09 413 chan_writel(chan, HSU_CH_CR, 0x3);
d843fc6e 414 return;
669b7a09 415 }
669b7a09 416 del_timer(&chan->rx_timer);
d843fc6e
FT		 417
418 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
419 dbuf->dma_size, DMA_FROM_DEVICE);
420
421 /*
06c77e21 422 * Head will only wrap around when we recycle
d843fc6e
FT		 423 * the DMA buffer, and when that happens, we
424 * explicitly set tail to 0. So head will
425 * always be greater than tail.
426 */
427 tty_insert_flip_string(tty, dbuf->buf, count);
428 port->icount.rx += count;
429
430 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
431 dbuf->dma_size, DMA_FROM_DEVICE);
432
433 /* Reprogram the channel */
434 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
435 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
436 chan_writel(chan, HSU_CH_DCR, 0x1
437 | (0x1 << 8)
438 | (0x1 << 16)
439 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
440 );
669b7a09
FT		 441 tty_flip_buffer_push(tty);
442
d843fc6e 443 chan_writel(chan, HSU_CH_CR, 0x3);
669b7a09
FT		 444 chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
445 add_timer(&chan->rx_timer);
d843fc6e 446
d843fc6e
FT		 447}
448
449static void serial_hsu_stop_rx(struct uart_port *port)
450{
451 struct uart_hsu_port *up =
452 container_of(port, struct uart_hsu_port, port);
453 struct hsu_dma_chan *chan = up->rxc;
454
455 if (up->use_dma)
456 chan_writel(chan, HSU_CH_CR, 0x2);
457 else {
458 up->ier &= ~UART_IER_RLSI;
459 up->port.read_status_mask &= ~UART_LSR_DR;
460 serial_out(up, UART_IER, up->ier);
461 }
462}
463
d843fc6e
FT		 464static inline void receive_chars(struct uart_hsu_port *up, int *status)
465{
466 struct tty_struct *tty = up->port.state->port.tty;
467 unsigned int ch, flag;
468 unsigned int max_count = 256;
469
470 if (!tty)
471 return;
472
473 do {
474 ch = serial_in(up, UART_RX);
475 flag = TTY_NORMAL;
476 up->port.icount.rx++;
477
478 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
479 UART_LSR_FE | UART_LSR_OE))) {
480
481 dev_warn(up->dev, "We really rush into ERR/BI case"
482 "status = 0x%02x", *status);
483 /* For statistics only */
484 if (*status & UART_LSR_BI) {
485 *status &= ~(UART_LSR_FE | UART_LSR_PE);
486 up->port.icount.brk++;
487 /*
488 * We do the SysRQ and SAK checking
489 * here because otherwise the break
490 * may get masked by ignore_status_mask
491 * or read_status_mask.
492 */
493 if (uart_handle_break(&up->port))
494 goto ignore_char;
495 } else if (*status & UART_LSR_PE)
496 up->port.icount.parity++;
497 else if (*status & UART_LSR_FE)
498 up->port.icount.frame++;
499 if (*status & UART_LSR_OE)
500 up->port.icount.overrun++;
501
502 /* Mask off conditions which should be ignored. */
503 *status &= up->port.read_status_mask;
504
505#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
506 if (up->port.cons &&
507 up->port.cons->index == up->port.line) {
508 /* Recover the break flag from console xmit */
509 *status |= up->lsr_break_flag;
510 up->lsr_break_flag = 0;
511 }
512#endif
513 if (*status & UART_LSR_BI) {
514 flag = TTY_BREAK;
515 } else if (*status & UART_LSR_PE)
516 flag = TTY_PARITY;
517 else if (*status & UART_LSR_FE)
518 flag = TTY_FRAME;
519 }
520
521 if (uart_handle_sysrq_char(&up->port, ch))
522 goto ignore_char;
523
524 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
525 ignore_char:
526 *status = serial_in(up, UART_LSR);
527 } while ((*status & UART_LSR_DR) && max_count--);
528 tty_flip_buffer_push(tty);
529}
530
531static void transmit_chars(struct uart_hsu_port *up)
532{
533 struct circ_buf *xmit = &up->port.state->xmit;
534 int count;
d843fc6e
FT		 535
536 if (up->port.x_char) {
537 serial_out(up, UART_TX, up->port.x_char);
538 up->port.icount.tx++;
539 up->port.x_char = 0;
540 return;
541 }
542 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
543 serial_hsu_stop_tx(&up->port);
544 return;
545 }
546
547#ifndef MFD_HSU_A0_STEPPING
548 count = up->port.fifosize / 2;
549#else
550 /*
551 * A0 only supports fully empty IRQ, and the first char written
552 * into it won't clear the EMPT bit, so we may need be cautious
553 * by useing a shorter buffer
554 */
d843fc6e
FT		 555 count = up->port.fifosize - 4;
556#endif
557 do {
558 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
559 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
d843fc6e
FT		 560
561 up->port.icount.tx++;
562 if (uart_circ_empty(xmit))
563 break;
564 } while (--count > 0);
565
566 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
567 uart_write_wakeup(&up->port);
568
569 if (uart_circ_empty(xmit))
570 serial_hsu_stop_tx(&up->port);
571}
572
573static inline void check_modem_status(struct uart_hsu_port *up)
574{
575 int status;
576
577 status = serial_in(up, UART_MSR);
578
579 if ((status & UART_MSR_ANY_DELTA) == 0)
580 return;
581
582 if (status & UART_MSR_TERI)
583 up->port.icount.rng++;
584 if (status & UART_MSR_DDSR)
585 up->port.icount.dsr++;
586 /* We may only get DDCD when HW init and reset */
587 if (status & UART_MSR_DDCD)
588 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
06c77e21 589 /* Will start/stop_tx accordingly */
d843fc6e
FT		 590 if (status & UART_MSR_DCTS)
591 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
592
593 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
594}
595
596/*
597 * This handles the interrupt from one port.
598 */
599static irqreturn_t port_irq(int irq, void *dev_id)
600{
601 struct uart_hsu_port *up = dev_id;
602 unsigned int iir, lsr;
603 unsigned long flags;
604
605 if (unlikely(!up->running))
606 return IRQ_NONE;
607
06c77e21 608 spin_lock_irqsave(&up->port.lock, flags);
d843fc6e
FT		 609 if (up->use_dma) {
610 lsr = serial_in(up, UART_LSR);
611 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
612 UART_LSR_FE | UART_LSR_OE)))
613 dev_warn(up->dev,
614 "Got lsr irq while using DMA, lsr = 0x%2x\n",
615 lsr);
616 check_modem_status(up);
06c77e21 617 spin_unlock_irqrestore(&up->port.lock, flags);
d843fc6e
FT		 618 return IRQ_HANDLED;
619 }
620
d843fc6e
FT		 621 iir = serial_in(up, UART_IIR);
622 if (iir & UART_IIR_NO_INT) {
623 spin_unlock_irqrestore(&up->port.lock, flags);
624 return IRQ_NONE;
625 }
626
627 lsr = serial_in(up, UART_LSR);
d843fc6e
FT		 628 if (lsr & UART_LSR_DR)
629 receive_chars(up, &lsr);
06c77e21 630 check_modem_status(up);
d843fc6e
FT		 631
632 /* lsr will be renewed during the receive_chars */
633 if (lsr & UART_LSR_THRE)
634 transmit_chars(up);
635
636 spin_unlock_irqrestore(&up->port.lock, flags);
637 return IRQ_HANDLED;
638}
639
640static inline void dma_chan_irq(struct hsu_dma_chan *chan)
641{
642 struct uart_hsu_port *up = chan->uport;
643 unsigned long flags;
644 u32 int_sts;
645
646 spin_lock_irqsave(&up->port.lock, flags);
647
648 if (!up->use_dma || !up->running)
649 goto exit;
650
651 /*
652 * No matter what situation, need read clear the IRQ status
653 * There is a bug, see Errata 5, HSD 2900918
654 */
655 int_sts = chan_readl(chan, HSU_CH_SR);
656
657 /* Rx channel */
658 if (chan->dirt == DMA_FROM_DEVICE)
659 hsu_dma_rx(up, int_sts);
660
661 /* Tx channel */
662 if (chan->dirt == DMA_TO_DEVICE) {
d843fc6e
FT		 663 chan_writel(chan, HSU_CH_CR, 0x0);
664 up->dma_tx_on = 0;
665 hsu_dma_tx(up);
666 }
667
668exit:
669 spin_unlock_irqrestore(&up->port.lock, flags);
670 return;
671}
672
673static irqreturn_t dma_irq(int irq, void *dev_id)
674{
675 struct hsu_port *hsu = dev_id;
676 u32 int_sts, i;
677
678 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
679
680 /* Currently we only have 6 channels may be used */
681 for (i = 0; i < 6; i++) {
682 if (int_sts & 0x1)
683 dma_chan_irq(&hsu->chans[i]);
684 int_sts >>= 1;
685 }
686
687 return IRQ_HANDLED;
688}
689
690static unsigned int serial_hsu_tx_empty(struct uart_port *port)
691{
692 struct uart_hsu_port *up =
693 container_of(port, struct uart_hsu_port, port);
694 unsigned long flags;
695 unsigned int ret;
696
697 spin_lock_irqsave(&up->port.lock, flags);
698 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
699 spin_unlock_irqrestore(&up->port.lock, flags);
700
701 return ret;
702}
703
704static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
705{
706 struct uart_hsu_port *up =
707 container_of(port, struct uart_hsu_port, port);
708 unsigned char status;
709 unsigned int ret;
710
711 status = serial_in(up, UART_MSR);
712
713 ret = 0;
714 if (status & UART_MSR_DCD)
715 ret |= TIOCM_CAR;
716 if (status & UART_MSR_RI)
717 ret |= TIOCM_RNG;
718 if (status & UART_MSR_DSR)
719 ret |= TIOCM_DSR;
720 if (status & UART_MSR_CTS)
721 ret |= TIOCM_CTS;
722 return ret;
723}
724
725static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
726{
727 struct uart_hsu_port *up =
728 container_of(port, struct uart_hsu_port, port);
729 unsigned char mcr = 0;
730
731 if (mctrl & TIOCM_RTS)
732 mcr |= UART_MCR_RTS;
733 if (mctrl & TIOCM_DTR)
734 mcr |= UART_MCR_DTR;
735 if (mctrl & TIOCM_OUT1)
736 mcr |= UART_MCR_OUT1;
737 if (mctrl & TIOCM_OUT2)
738 mcr |= UART_MCR_OUT2;
739 if (mctrl & TIOCM_LOOP)
740 mcr |= UART_MCR_LOOP;
741
742 mcr |= up->mcr;
743
744 serial_out(up, UART_MCR, mcr);
745}
746
747static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
748{
749 struct uart_hsu_port *up =
750 container_of(port, struct uart_hsu_port, port);
751 unsigned long flags;
752
753 spin_lock_irqsave(&up->port.lock, flags);
754 if (break_state == -1)
755 up->lcr |= UART_LCR_SBC;
756 else
757 up->lcr &= ~UART_LCR_SBC;
758 serial_out(up, UART_LCR, up->lcr);
759 spin_unlock_irqrestore(&up->port.lock, flags);
760}
761
762/*
763 * What special to do:
764 * 1. chose the 64B fifo mode
765 * 2. make sure not to select half empty mode for A0 stepping
766 * 3. start dma or pio depends on configuration
767 * 4. we only allocate dma memory when needed
768 */
769static int serial_hsu_startup(struct uart_port *port)
770{
771 struct uart_hsu_port *up =
772 container_of(port, struct uart_hsu_port, port);
773 unsigned long flags;
774
775 /*
776 * Clear the FIFO buffers and disable them.
777 * (they will be reenabled in set_termios())
778 */
779 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
780 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
781 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
782 serial_out(up, UART_FCR, 0);
783
784 /* Clear the interrupt registers. */
785 (void) serial_in(up, UART_LSR);
786 (void) serial_in(up, UART_RX);
787 (void) serial_in(up, UART_IIR);
788 (void) serial_in(up, UART_MSR);
789
790 /* Now, initialize the UART, default is 8n1 */
791 serial_out(up, UART_LCR, UART_LCR_WLEN8);
792
793 spin_lock_irqsave(&up->port.lock, flags);
794
795 up->port.mctrl |= TIOCM_OUT2;
796 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
797
798 /*
799 * Finally, enable interrupts. Note: Modem status interrupts
800 * are set via set_termios(), which will be occurring imminently
801 * anyway, so we don't enable them here.
802 */
803 if (!up->use_dma)
804 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
805 else
806 up->ier = 0;
807 serial_out(up, UART_IER, up->ier);
808
809 spin_unlock_irqrestore(&up->port.lock, flags);
810
811 /* DMA init */
d843fc6e
FT		 812 if (up->use_dma) {
813 struct hsu_dma_buffer *dbuf;
814 struct circ_buf *xmit = &port->state->xmit;
815
816 up->dma_tx_on = 0;
817
818 /* First allocate the RX buffer */
819 dbuf = &up->rxbuf;
820 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
821 if (!dbuf->buf) {
822 up->use_dma = 0;
823 goto exit;
824 }
825 dbuf->dma_addr = dma_map_single(port->dev,
826 dbuf->buf,
827 HSU_DMA_BUF_SIZE,
828 DMA_FROM_DEVICE);
829 dbuf->dma_size = HSU_DMA_BUF_SIZE;
830
831 /* Start the RX channel right now */
832 hsu_dma_start_rx_chan(up->rxc, dbuf);
833
834 /* Next init the TX DMA */
835 dbuf = &up->txbuf;
836 dbuf->buf = xmit->buf;
837 dbuf->dma_addr = dma_map_single(port->dev,
838 dbuf->buf,
839 UART_XMIT_SIZE,
840 DMA_TO_DEVICE);
841 dbuf->dma_size = UART_XMIT_SIZE;
842
843 /* This should not be changed all around */
844 chan_writel(up->txc, HSU_CH_BSR, 32);
845 chan_writel(up->txc, HSU_CH_MOTSR, 4);
846 dbuf->ofs = 0;
847 }
848
849exit:
850 /* And clear the interrupt registers again for luck. */
851 (void) serial_in(up, UART_LSR);
852 (void) serial_in(up, UART_RX);
853 (void) serial_in(up, UART_IIR);
854 (void) serial_in(up, UART_MSR);
855
856 up->running = 1;
857 return 0;
858}
859
860static void serial_hsu_shutdown(struct uart_port *port)
861{
862 struct uart_hsu_port *up =
863 container_of(port, struct uart_hsu_port, port);
864 unsigned long flags;
865
669b7a09
FT		 866 del_timer_sync(&up->rxc->rx_timer);
867
d843fc6e
FT		 868 /* Disable interrupts from this port */
869 up->ier = 0;
870 serial_out(up, UART_IER, 0);
871 up->running = 0;
872
873 spin_lock_irqsave(&up->port.lock, flags);
874 up->port.mctrl &= ~TIOCM_OUT2;
875 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
876 spin_unlock_irqrestore(&up->port.lock, flags);
877
878 /* Disable break condition and FIFOs */
879 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
880 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
881 UART_FCR_CLEAR_RCVR |
882 UART_FCR_CLEAR_XMIT);
883 serial_out(up, UART_FCR, 0);
884}
885
886static void
887serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
888 struct ktermios *old)
889{
890 struct uart_hsu_port *up =
891 container_of(port, struct uart_hsu_port, port);
892 struct tty_struct *tty = port->state->port.tty;
893 unsigned char cval, fcr = 0;
894 unsigned long flags;
895 unsigned int baud, quot;
896 u32 mul = 0x3600;
897 u32 ps = 0x10;
898
899 switch (termios->c_cflag & CSIZE) {
900 case CS5:
901 cval = UART_LCR_WLEN5;
902 break;
903 case CS6:
904 cval = UART_LCR_WLEN6;
905 break;
906 case CS7:
907 cval = UART_LCR_WLEN7;
908 break;
909 default:
910 case CS8:
911 cval = UART_LCR_WLEN8;
912 break;
913 }
914
915 /* CMSPAR isn't supported by this driver */
916 if (tty)
917 tty->termios->c_cflag &= ~CMSPAR;
918
919 if (termios->c_cflag & CSTOPB)
920 cval |= UART_LCR_STOP;
921 if (termios->c_cflag & PARENB)
922 cval |= UART_LCR_PARITY;
923 if (!(termios->c_cflag & PARODD))
924 cval |= UART_LCR_EPAR;
925
926 /*
927 * For those basic low baud rate we can get the direct
928 * scalar from 2746800, like 115200 = 2746800/24, for those
929 * higher baud rate, we have to handle them case by case,
930 * but DIV reg is never touched as its default value 0x3d09
931 */
932 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
933 quot = uart_get_divisor(port, baud);
934
935 switch (baud) {
936 case 3500000:
937 mul = 0x3345;
938 ps = 0xC;
939 quot = 1;
940 break;
941 case 2500000:
942 mul = 0x2710;
943 ps = 0x10;
944 quot = 1;
945 break;
946 case 18432000:
947 mul = 0x2400;
948 ps = 0x10;
949 quot = 1;
950 break;
951 case 1500000:
952 mul = 0x1D4C;
953 ps = 0xc;
954 quot = 1;
955 break;
956 default:
957 ;
958 }
959
960 if ((up->port.uartclk / quot) < (2400 * 16))
961 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
962 else if ((up->port.uartclk / quot) < (230400 * 16))
963 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
964 else
965 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
966
967 fcr |= UART_FCR_HSU_64B_FIFO;
968#ifdef MFD_HSU_A0_STEPPING
969 /* A0 doesn't support half empty IRQ */
970 fcr |= UART_FCR_FULL_EMPT_TXI;
971#endif
972
973 /*
974 * Ok, we're now changing the port state. Do it with
975 * interrupts disabled.
976 */
977 spin_lock_irqsave(&up->port.lock, flags);
978
979 /* Update the per-port timeout */
980 uart_update_timeout(port, termios->c_cflag, baud);
981
982 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
983 if (termios->c_iflag & INPCK)
984 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
985 if (termios->c_iflag & (BRKINT | PARMRK))
986 up->port.read_status_mask |= UART_LSR_BI;
987
988 /* Characters to ignore */
989 up->port.ignore_status_mask = 0;
990 if (termios->c_iflag & IGNPAR)
991 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
992 if (termios->c_iflag & IGNBRK) {
993 up->port.ignore_status_mask |= UART_LSR_BI;
994 /*
995 * If we're ignoring parity and break indicators,
996 * ignore overruns too (for real raw support).
997 */
998 if (termios->c_iflag & IGNPAR)
999 up->port.ignore_status_mask |= UART_LSR_OE;
1000 }
1001
1002 /* Ignore all characters if CREAD is not set */
1003 if ((termios->c_cflag & CREAD) == 0)
1004 up->port.ignore_status_mask |= UART_LSR_DR;
1005
1006 /*
1007 * CTS flow control flag and modem status interrupts, disable
1008 * MSI by default
1009 */
1010 up->ier &= ~UART_IER_MSI;
1011 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1012 up->ier |= UART_IER_MSI;
1013
1014 serial_out(up, UART_IER, up->ier);
1015
1016 if (termios->c_cflag & CRTSCTS)
1017 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1018 else
1019 up->mcr &= ~UART_MCR_AFE;
1020
1021 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1022 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
1023 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
1024 serial_out(up, UART_LCR, cval); /* reset DLAB */
1025 serial_out(up, UART_MUL, mul); /* set MUL */
1026 serial_out(up, UART_PS, ps); /* set PS */
1027 up->lcr = cval; /* Save LCR */
1028 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1029 serial_out(up, UART_FCR, fcr);
1030 spin_unlock_irqrestore(&up->port.lock, flags);
1031}
1032
1033static void
1034serial_hsu_pm(struct uart_port *port, unsigned int state,
1035 unsigned int oldstate)
1036{
1037}
1038
1039static void serial_hsu_release_port(struct uart_port *port)
1040{
1041}
1042
1043static int serial_hsu_request_port(struct uart_port *port)
1044{
1045 return 0;
1046}
1047
1048static void serial_hsu_config_port(struct uart_port *port, int flags)
1049{
d843fc6e
FT		 1050 struct uart_hsu_port *up =
1051 container_of(port, struct uart_hsu_port, port);
1052 up->port.type = PORT_MFD;
d843fc6e
FT		 1053}
1054
1055static int
1056serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1057{
1058 /* We don't want the core code to modify any port params */
1059 return -EINVAL;
1060}
1061
1062static const char *
1063serial_hsu_type(struct uart_port *port)
1064{
1065 struct uart_hsu_port *up =
1066 container_of(port, struct uart_hsu_port, port);
1067 return up->name;
1068}
1069
1070/* Mainly for uart console use */
1071static struct uart_hsu_port *serial_hsu_ports[3];
1072static struct uart_driver serial_hsu_reg;
1073
1074#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1075
1076#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1077
1078/* Wait for transmitter & holding register to empty */
1079static inline void wait_for_xmitr(struct uart_hsu_port *up)
1080{
1081 unsigned int status, tmout = 1000;
1082
1083 /* Wait up to 1ms for the character to be sent. */
1084 do {
1085 status = serial_in(up, UART_LSR);
1086
1087 if (status & UART_LSR_BI)
1088 up->lsr_break_flag = UART_LSR_BI;
1089
1090 if (--tmout == 0)
1091 break;
1092 udelay(1);
1093 } while (!(status & BOTH_EMPTY));
1094
1095 /* Wait up to 1s for flow control if necessary */
1096 if (up->port.flags & UPF_CONS_FLOW) {
1097 tmout = 1000000;
1098 while (--tmout &&
1099 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1100 udelay(1);
1101 }
1102}
1103
1104static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1105{
1106 struct uart_hsu_port *up =
1107 container_of(port, struct uart_hsu_port, port);
1108
1109 wait_for_xmitr(up);
1110 serial_out(up, UART_TX, ch);
1111}
1112
1113/*
1114 * Print a string to the serial port trying not to disturb
1115 * any possible real use of the port...
1116 *
1117 * The console_lock must be held when we get here.
1118 */
1119static void
1120serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1121{
1122 struct uart_hsu_port *up = serial_hsu_ports[co->index];
1123 unsigned long flags;
1124 unsigned int ier;
1125 int locked = 1;
1126
1127 local_irq_save(flags);
1128 if (up->port.sysrq)
1129 locked = 0;
1130 else if (oops_in_progress) {
1131 locked = spin_trylock(&up->port.lock);
1132 } else
1133 spin_lock(&up->port.lock);
1134
1135 /* First save the IER then disable the interrupts */
1136 ier = serial_in(up, UART_IER);
1137 serial_out(up, UART_IER, 0);
1138
1139 uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1140
1141 /*
1142 * Finally, wait for transmitter to become empty
1143 * and restore the IER
1144 */
1145 wait_for_xmitr(up);
1146 serial_out(up, UART_IER, ier);
1147
1148 if (locked)
1149 spin_unlock(&up->port.lock);
1150 local_irq_restore(flags);
1151}
1152
1153static struct console serial_hsu_console;
1154
1155static int __init
1156serial_hsu_console_setup(struct console *co, char *options)
1157{
1158 struct uart_hsu_port *up;
1159 int baud = 115200;
1160 int bits = 8;
1161 int parity = 'n';
1162 int flow = 'n';
1163 int ret;
1164
1165 if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1166 co->index = 0;
1167 up = serial_hsu_ports[co->index];
1168 if (!up)
1169 return -ENODEV;
1170
1171 if (options)
1172 uart_parse_options(options, &baud, &parity, &bits, &flow);
1173
1174 ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1175
1176 return ret;
1177}
1178
1179static struct console serial_hsu_console = {
1180 .name = "ttyMFD",
1181 .write = serial_hsu_console_write,
1182 .device = uart_console_device,
1183 .setup = serial_hsu_console_setup,
1184 .flags = CON_PRINTBUFFER,
1185 .index = 2,
1186 .data = &serial_hsu_reg,
1187};
1188#endif
1189
1190struct uart_ops serial_hsu_pops = {
1191 .tx_empty = serial_hsu_tx_empty,
1192 .set_mctrl = serial_hsu_set_mctrl,
1193 .get_mctrl = serial_hsu_get_mctrl,
1194 .stop_tx = serial_hsu_stop_tx,
1195 .start_tx = serial_hsu_start_tx,
1196 .stop_rx = serial_hsu_stop_rx,
1197 .enable_ms = serial_hsu_enable_ms,
1198 .break_ctl = serial_hsu_break_ctl,
1199 .startup = serial_hsu_startup,
1200 .shutdown = serial_hsu_shutdown,
1201 .set_termios = serial_hsu_set_termios,
1202 .pm = serial_hsu_pm,
1203 .type = serial_hsu_type,
1204 .release_port = serial_hsu_release_port,
1205 .request_port = serial_hsu_request_port,
1206 .config_port = serial_hsu_config_port,
1207 .verify_port = serial_hsu_verify_port,
1208};
1209
1210static struct uart_driver serial_hsu_reg = {
1211 .owner = THIS_MODULE,
1212 .driver_name = "MFD serial",
1213 .dev_name = "ttyMFD",
1214 .major = TTY_MAJOR,
1215 .minor = 128,
1216 .nr = 3,
1217};
1218
1219#ifdef CONFIG_PM
1220static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1221{
3c4108c8 1222 void *priv = pci_get_drvdata(pdev);
d843fc6e
FT		 1223 struct uart_hsu_port *up;
1224
3c4108c8
FT		 1225 /* Make sure this is not the internal dma controller */
1226 if (priv && (pdev->device != 0x081E)) {
1227 up = priv;
1228 uart_suspend_port(&serial_hsu_reg, &up->port);
1229 }
d843fc6e 1230
3c4108c8
FT		 1231 pci_save_state(pdev);
1232 pci_set_power_state(pdev, pci_choose_state(pdev, state));
d843fc6e
FT		 1233 return 0;
1234}
1235
1236static int serial_hsu_resume(struct pci_dev *pdev)
1237{
3c4108c8 1238 void *priv = pci_get_drvdata(pdev);
d843fc6e 1239 struct uart_hsu_port *up;
3c4108c8 1240 int ret;
d843fc6e 1241
3c4108c8
FT		 1242 pci_set_power_state(pdev, PCI_D0);
1243 pci_restore_state(pdev);
1244
1245 ret = pci_enable_device(pdev);
1246 if (ret)
1247 dev_warn(&pdev->dev,
1248 "HSU: can't re-enable device, try to continue\n");
1249
1250 if (priv && (pdev->device != 0x081E)) {
1251 up = priv;
1252 uart_resume_port(&serial_hsu_reg, &up->port);
1253 }
d843fc6e
FT		 1254 return 0;
1255}
1256#else
1257#define serial_hsu_suspend NULL
1258#define serial_hsu_resume NULL
1259#endif
1260
1261/* temp global pointer before we settle down on using one or four PCI dev */
1262static struct hsu_port *phsu;
1263
1264static int serial_hsu_probe(struct pci_dev *pdev,
1265 const struct pci_device_id *ent)
1266{
1267 struct uart_hsu_port *uport;
1268 int index, ret;
1269
1270 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1271 pdev->vendor, pdev->device);
1272
1273 switch (pdev->device) {
1274 case 0x081B:
1275 index = 0;
1276 break;
1277 case 0x081C:
1278 index = 1;
1279 break;
1280 case 0x081D:
1281 index = 2;
1282 break;
1283 case 0x081E:
1284 /* internal DMA controller */
1285 index = 3;
1286 break;
1287 default:
1288 dev_err(&pdev->dev, "HSU: out of index!");
1289 return -ENODEV;
1290 }
1291
1292 ret = pci_enable_device(pdev);
1293 if (ret)
1294 return ret;
1295
1296 if (index == 3) {
1297 /* DMA controller */
1298 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1299 if (ret) {
1300 dev_err(&pdev->dev, "can not get IRQ\n");
1301 goto err_disable;
1302 }
1303 pci_set_drvdata(pdev, phsu);
1304 } else {
1305 /* UART port 0~2 */
1306 uport = &phsu->port[index];
1307 uport->port.irq = pdev->irq;
1308 uport->port.dev = &pdev->dev;
1309 uport->dev = &pdev->dev;
1310
1311 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1312 if (ret) {
1313 dev_err(&pdev->dev, "can not get IRQ\n");
1314 goto err_disable;
1315 }
1316 uart_add_one_port(&serial_hsu_reg, &uport->port);
1317
1318#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1319 if (index == 2) {
1320 register_console(&serial_hsu_console);
1321 uport->port.cons = &serial_hsu_console;
1322 }
1323#endif
1324 pci_set_drvdata(pdev, uport);
1325 }
1326
1327 return 0;
1328
1329err_disable:
1330 pci_disable_device(pdev);
1331 return ret;
1332}
1333
669b7a09
FT		 1334static void hsu_dma_rx_timeout(unsigned long data)
1335{
1336 struct hsu_dma_chan *chan = (void *)data;
1337 struct uart_hsu_port *up = chan->uport;
1338 struct hsu_dma_buffer *dbuf = &up->rxbuf;
1339 int count = 0;
1340 unsigned long flags;
1341
1342 spin_lock_irqsave(&up->port.lock, flags);
1343
1344 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
1345
1346 if (!count) {
1347 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
1348 goto exit;
1349 }
1350
1351 hsu_dma_rx(up, 0);
1352exit:
1353 spin_unlock_irqrestore(&up->port.lock, flags);
1354}
1355
d843fc6e
FT		 1356static void hsu_global_init(void)
1357{
1358 struct hsu_port *hsu;
1359 struct uart_hsu_port *uport;
1360 struct hsu_dma_chan *dchan;
1361 int i, ret;
1362
1363 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1364 if (!hsu)
1365 return;
1366
1367 /* Get basic io resource and map it */
1368 hsu->paddr = 0xffa28000;
1369 hsu->iolen = 0x1000;
1370
1371 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1372 pr_warning("HSU: error in request mem region\n");
1373
1374 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1375 if (!hsu->reg) {
1376 pr_err("HSU: error in ioremap\n");
1377 ret = -ENOMEM;
1378 goto err_free_region;
1379 }
1380
1381 /* Initialise the 3 UART ports */
1382 uport = hsu->port;
1383 for (i = 0; i < 3; i++) {
1384 uport->port.type = PORT_MFD;
1385 uport->port.iotype = UPIO_MEM;
1386 uport->port.mapbase = (resource_size_t)hsu->paddr
1387 + HSU_PORT_REG_OFFSET
1388 + i * HSU_PORT_REG_LENGTH;
1389 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1390 + i * HSU_PORT_REG_LENGTH;
1391
1392 sprintf(uport->name, "hsu_port%d", i);
1393 uport->port.fifosize = 64;
1394 uport->port.ops = &serial_hsu_pops;
1395 uport->port.line = i;
1396 uport->port.flags = UPF_IOREMAP;
06c77e21 1397 /* set the scalable maxim support rate to 2746800 bps */
d843fc6e
FT		 1398 uport->port.uartclk = 115200 * 24 * 16;
1399
1400 uport->running = 0;
1401 uport->txc = &hsu->chans[i * 2];
1402 uport->rxc = &hsu->chans[i * 2 + 1];
1403
1404 serial_hsu_ports[i] = uport;
1405 uport->index = i;
1406 uport++;
1407 }
1408
1409 /* Initialise 6 dma channels */
1410 dchan = hsu->chans;
1411 for (i = 0; i < 6; i++) {
1412 dchan->id = i;
1413 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1414 dchan->uport = &hsu->port[i/2];
1415 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1416 i * HSU_DMA_CHANS_REG_LENGTH;
669b7a09
FT		 1417
1418 /* Work around for RX */
1419 if (dchan->dirt == DMA_FROM_DEVICE) {
1420 init_timer(&dchan->rx_timer);
1421 dchan->rx_timer.function = hsu_dma_rx_timeout;
1422 dchan->rx_timer.data = (unsigned long)dchan;
1423 }
d843fc6e
FT		 1424 dchan++;
1425 }
1426
1427 phsu = hsu;
1428
1429 hsu_debugfs_init(hsu);
1430 return;
1431
1432err_free_region:
1433 release_mem_region(hsu->paddr, hsu->iolen);
1434 kfree(hsu);
1435 return;
1436}
1437
1438static void serial_hsu_remove(struct pci_dev *pdev)
1439{
1440 struct hsu_port *hsu;
1441 int i;
1442
1443 hsu = pci_get_drvdata(pdev);
1444 if (!hsu)
1445 return;
1446
1447 for (i = 0; i < 3; i++)
1448 uart_remove_one_port(&serial_hsu_reg, &hsu->port[i].port);
1449
1450 pci_set_drvdata(pdev, NULL);
1451 free_irq(hsu->irq, hsu);
1452 pci_disable_device(pdev);
1453}
1454
1455/* First 3 are UART ports, and the 4th is the DMA */
1456static const struct pci_device_id pci_ids[] __devinitdata = {
1457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1459 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1460 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1461 {},
1462};
1463
1464static struct pci_driver hsu_pci_driver = {
1465 .name = "HSU serial",
1466 .id_table = pci_ids,
1467 .probe = serial_hsu_probe,
1468 .remove = __devexit_p(serial_hsu_remove),
1469 .suspend = serial_hsu_suspend,
1470 .resume = serial_hsu_resume,
1471};
1472
1473static int __init hsu_pci_init(void)
1474{
1475 int ret;
1476
1477 hsu_global_init();
1478
1479 ret = uart_register_driver(&serial_hsu_reg);
1480 if (ret)
1481 return ret;
1482
1483 return pci_register_driver(&hsu_pci_driver);
1484}
1485
1486static void __exit hsu_pci_exit(void)
1487{
1488 pci_unregister_driver(&hsu_pci_driver);
1489 uart_unregister_driver(&serial_hsu_reg);
1490
1491 hsu_debugfs_remove(phsu);
1492
1493 kfree(phsu);
1494}
1495
1496module_init(hsu_pci_init);
1497module_exit(hsu_pci_exit);
1498
1499MODULE_LICENSE("GPL v2");
1500MODULE_ALIAS("platform:medfield-hsu");
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