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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/pxa.c | |
3 | * | |
4 | * Based on drivers/serial/8250.c by Russell King. | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Feb 20, 2003 | |
8 | * Copyright: (C) 2003 Monta Vista Software, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * Note 1: This driver is made separate from the already too overloaded | |
16 | * 8250.c because it needs some kirks of its own and that'll make it | |
17 | * easier to add DMA support. | |
18 | * | |
19 | * Note 2: I'm too sick of device allocation policies for serial ports. | |
20 | * If someone else wants to request an "official" allocation of major/minor | |
21 | * for this driver please be my guest. And don't forget that new hardware | |
22 | * to come from Intel might have more than 3 or 4 of those UARTs. Let's | |
23 | * hope for a better port registration and dynamic device allocation scheme | |
24 | * with the serial core maintainer satisfaction to appear soon. | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | |
28 | #if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
29 | #define SUPPORT_SYSRQ | |
30 | #endif | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/console.h> | |
36 | #include <linux/sysrq.h> | |
37 | #include <linux/serial_reg.h> | |
38 | #include <linux/circ_buf.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
d052d1be | 41 | #include <linux/platform_device.h> |
1da177e4 LT |
42 | #include <linux/tty.h> |
43 | #include <linux/tty_flip.h> | |
44 | #include <linux/serial_core.h> | |
b049bd9d | 45 | #include <linux/clk.h> |
290a5589 | 46 | #include <linux/io.h> |
1da177e4 LT |
47 | |
48 | struct uart_pxa_port { | |
49 | struct uart_port port; | |
50 | unsigned char ier; | |
51 | unsigned char lcr; | |
52 | unsigned char mcr; | |
53 | unsigned int lsr_break_flag; | |
b049bd9d | 54 | struct clk *clk; |
1da177e4 LT |
55 | char *name; |
56 | }; | |
57 | ||
58 | static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) | |
59 | { | |
60 | offset <<= 2; | |
61 | return readl(up->port.membase + offset); | |
62 | } | |
63 | ||
64 | static inline void serial_out(struct uart_pxa_port *up, int offset, int value) | |
65 | { | |
66 | offset <<= 2; | |
67 | writel(value, up->port.membase + offset); | |
68 | } | |
69 | ||
70 | static void serial_pxa_enable_ms(struct uart_port *port) | |
71 | { | |
72 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
73 | ||
74 | up->ier |= UART_IER_MSI; | |
75 | serial_out(up, UART_IER, up->ier); | |
76 | } | |
77 | ||
b129a8cc | 78 | static void serial_pxa_stop_tx(struct uart_port *port) |
1da177e4 LT |
79 | { |
80 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
81 | ||
82 | if (up->ier & UART_IER_THRI) { | |
83 | up->ier &= ~UART_IER_THRI; | |
84 | serial_out(up, UART_IER, up->ier); | |
85 | } | |
86 | } | |
87 | ||
88 | static void serial_pxa_stop_rx(struct uart_port *port) | |
89 | { | |
90 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
91 | ||
92 | up->ier &= ~UART_IER_RLSI; | |
93 | up->port.read_status_mask &= ~UART_LSR_DR; | |
94 | serial_out(up, UART_IER, up->ier); | |
95 | } | |
96 | ||
7d12e780 | 97 | static inline void receive_chars(struct uart_pxa_port *up, int *status) |
1da177e4 | 98 | { |
ebd2c8f6 | 99 | struct tty_struct *tty = up->port.state->port.tty; |
1da177e4 LT |
100 | unsigned int ch, flag; |
101 | int max_count = 256; | |
102 | ||
103 | do { | |
1da177e4 LT |
104 | ch = serial_in(up, UART_RX); |
105 | flag = TTY_NORMAL; | |
106 | up->port.icount.rx++; | |
107 | ||
108 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
109 | UART_LSR_FE | UART_LSR_OE))) { | |
110 | /* | |
111 | * For statistics only | |
112 | */ | |
113 | if (*status & UART_LSR_BI) { | |
114 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
115 | up->port.icount.brk++; | |
116 | /* | |
117 | * We do the SysRQ and SAK checking | |
118 | * here because otherwise the break | |
119 | * may get masked by ignore_status_mask | |
120 | * or read_status_mask. | |
121 | */ | |
122 | if (uart_handle_break(&up->port)) | |
123 | goto ignore_char; | |
124 | } else if (*status & UART_LSR_PE) | |
125 | up->port.icount.parity++; | |
126 | else if (*status & UART_LSR_FE) | |
127 | up->port.icount.frame++; | |
128 | if (*status & UART_LSR_OE) | |
129 | up->port.icount.overrun++; | |
130 | ||
131 | /* | |
132 | * Mask off conditions which should be ignored. | |
133 | */ | |
134 | *status &= up->port.read_status_mask; | |
135 | ||
136 | #ifdef CONFIG_SERIAL_PXA_CONSOLE | |
137 | if (up->port.line == up->port.cons->index) { | |
138 | /* Recover the break flag from console xmit */ | |
139 | *status |= up->lsr_break_flag; | |
140 | up->lsr_break_flag = 0; | |
141 | } | |
142 | #endif | |
143 | if (*status & UART_LSR_BI) { | |
144 | flag = TTY_BREAK; | |
145 | } else if (*status & UART_LSR_PE) | |
146 | flag = TTY_PARITY; | |
147 | else if (*status & UART_LSR_FE) | |
148 | flag = TTY_FRAME; | |
149 | } | |
05ab3014 | 150 | |
7d12e780 | 151 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 152 | goto ignore_char; |
05ab3014 RK |
153 | |
154 | uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); | |
155 | ||
1da177e4 LT |
156 | ignore_char: |
157 | *status = serial_in(up, UART_LSR); | |
158 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
159 | tty_flip_buffer_push(tty); | |
160 | } | |
161 | ||
162 | static void transmit_chars(struct uart_pxa_port *up) | |
163 | { | |
ebd2c8f6 | 164 | struct circ_buf *xmit = &up->port.state->xmit; |
1da177e4 LT |
165 | int count; |
166 | ||
167 | if (up->port.x_char) { | |
168 | serial_out(up, UART_TX, up->port.x_char); | |
169 | up->port.icount.tx++; | |
170 | up->port.x_char = 0; | |
171 | return; | |
172 | } | |
173 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
b129a8cc | 174 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
175 | return; |
176 | } | |
177 | ||
178 | count = up->port.fifosize / 2; | |
179 | do { | |
180 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
181 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
182 | up->port.icount.tx++; | |
183 | if (uart_circ_empty(xmit)) | |
184 | break; | |
185 | } while (--count > 0); | |
186 | ||
187 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
188 | uart_write_wakeup(&up->port); | |
189 | ||
190 | ||
191 | if (uart_circ_empty(xmit)) | |
b129a8cc | 192 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
193 | } |
194 | ||
b129a8cc | 195 | static void serial_pxa_start_tx(struct uart_port *port) |
1da177e4 LT |
196 | { |
197 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
198 | ||
199 | if (!(up->ier & UART_IER_THRI)) { | |
200 | up->ier |= UART_IER_THRI; | |
201 | serial_out(up, UART_IER, up->ier); | |
202 | } | |
203 | } | |
204 | ||
205 | static inline void check_modem_status(struct uart_pxa_port *up) | |
206 | { | |
207 | int status; | |
208 | ||
209 | status = serial_in(up, UART_MSR); | |
210 | ||
211 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
212 | return; | |
213 | ||
214 | if (status & UART_MSR_TERI) | |
215 | up->port.icount.rng++; | |
216 | if (status & UART_MSR_DDSR) | |
217 | up->port.icount.dsr++; | |
218 | if (status & UART_MSR_DDCD) | |
219 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
220 | if (status & UART_MSR_DCTS) | |
221 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
222 | ||
bdc04e31 | 223 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
1da177e4 LT |
224 | } |
225 | ||
226 | /* | |
227 | * This handles the interrupt from one port. | |
228 | */ | |
7d12e780 | 229 | static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) |
1da177e4 | 230 | { |
c7bec5ab | 231 | struct uart_pxa_port *up = dev_id; |
1da177e4 LT |
232 | unsigned int iir, lsr; |
233 | ||
234 | iir = serial_in(up, UART_IIR); | |
235 | if (iir & UART_IIR_NO_INT) | |
236 | return IRQ_NONE; | |
237 | lsr = serial_in(up, UART_LSR); | |
238 | if (lsr & UART_LSR_DR) | |
7d12e780 | 239 | receive_chars(up, &lsr); |
1da177e4 LT |
240 | check_modem_status(up); |
241 | if (lsr & UART_LSR_THRE) | |
242 | transmit_chars(up); | |
243 | return IRQ_HANDLED; | |
244 | } | |
245 | ||
246 | static unsigned int serial_pxa_tx_empty(struct uart_port *port) | |
247 | { | |
248 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
249 | unsigned long flags; | |
250 | unsigned int ret; | |
251 | ||
252 | spin_lock_irqsave(&up->port.lock, flags); | |
253 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
254 | spin_unlock_irqrestore(&up->port.lock, flags); | |
255 | ||
256 | return ret; | |
257 | } | |
258 | ||
259 | static unsigned int serial_pxa_get_mctrl(struct uart_port *port) | |
260 | { | |
261 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
1da177e4 LT |
262 | unsigned char status; |
263 | unsigned int ret; | |
264 | ||
1da177e4 | 265 | status = serial_in(up, UART_MSR); |
1da177e4 LT |
266 | |
267 | ret = 0; | |
268 | if (status & UART_MSR_DCD) | |
269 | ret |= TIOCM_CAR; | |
270 | if (status & UART_MSR_RI) | |
271 | ret |= TIOCM_RNG; | |
272 | if (status & UART_MSR_DSR) | |
273 | ret |= TIOCM_DSR; | |
274 | if (status & UART_MSR_CTS) | |
275 | ret |= TIOCM_CTS; | |
276 | return ret; | |
277 | } | |
278 | ||
279 | static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
280 | { | |
281 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
282 | unsigned char mcr = 0; | |
283 | ||
284 | if (mctrl & TIOCM_RTS) | |
285 | mcr |= UART_MCR_RTS; | |
286 | if (mctrl & TIOCM_DTR) | |
287 | mcr |= UART_MCR_DTR; | |
288 | if (mctrl & TIOCM_OUT1) | |
289 | mcr |= UART_MCR_OUT1; | |
290 | if (mctrl & TIOCM_OUT2) | |
291 | mcr |= UART_MCR_OUT2; | |
292 | if (mctrl & TIOCM_LOOP) | |
293 | mcr |= UART_MCR_LOOP; | |
294 | ||
295 | mcr |= up->mcr; | |
296 | ||
297 | serial_out(up, UART_MCR, mcr); | |
298 | } | |
299 | ||
300 | static void serial_pxa_break_ctl(struct uart_port *port, int break_state) | |
301 | { | |
302 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
303 | unsigned long flags; | |
304 | ||
305 | spin_lock_irqsave(&up->port.lock, flags); | |
306 | if (break_state == -1) | |
307 | up->lcr |= UART_LCR_SBC; | |
308 | else | |
309 | up->lcr &= ~UART_LCR_SBC; | |
310 | serial_out(up, UART_LCR, up->lcr); | |
311 | spin_unlock_irqrestore(&up->port.lock, flags); | |
312 | } | |
313 | ||
314 | #if 0 | |
315 | static void serial_pxa_dma_init(struct pxa_uart *up) | |
316 | { | |
317 | up->rxdma = | |
318 | pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up); | |
319 | if (up->rxdma < 0) | |
320 | goto out; | |
321 | up->txdma = | |
322 | pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up); | |
323 | if (up->txdma < 0) | |
324 | goto err_txdma; | |
325 | up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL); | |
326 | if (!up->dmadesc) | |
327 | goto err_alloc; | |
328 | ||
329 | /* ... */ | |
330 | err_alloc: | |
331 | pxa_free_dma(up->txdma); | |
332 | err_rxdma: | |
333 | pxa_free_dma(up->rxdma); | |
334 | out: | |
335 | return; | |
336 | } | |
337 | #endif | |
338 | ||
339 | static int serial_pxa_startup(struct uart_port *port) | |
340 | { | |
341 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
342 | unsigned long flags; | |
343 | int retval; | |
344 | ||
d9e29649 MR |
345 | if (port->line == 3) /* HWUART */ |
346 | up->mcr |= UART_MCR_AFE; | |
347 | else | |
f02aa3f9 | 348 | up->mcr = 0; |
1da177e4 | 349 | |
b049bd9d RK |
350 | up->port.uartclk = clk_get_rate(up->clk); |
351 | ||
1da177e4 LT |
352 | /* |
353 | * Allocate the IRQ | |
354 | */ | |
355 | retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); | |
356 | if (retval) | |
357 | return retval; | |
358 | ||
359 | /* | |
360 | * Clear the FIFO buffers and disable them. | |
361 | * (they will be reenabled in set_termios()) | |
362 | */ | |
363 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
364 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
365 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
366 | serial_out(up, UART_FCR, 0); | |
367 | ||
368 | /* | |
369 | * Clear the interrupt registers. | |
370 | */ | |
371 | (void) serial_in(up, UART_LSR); | |
372 | (void) serial_in(up, UART_RX); | |
373 | (void) serial_in(up, UART_IIR); | |
374 | (void) serial_in(up, UART_MSR); | |
375 | ||
376 | /* | |
377 | * Now, initialize the UART | |
378 | */ | |
379 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
380 | ||
381 | spin_lock_irqsave(&up->port.lock, flags); | |
382 | up->port.mctrl |= TIOCM_OUT2; | |
383 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
384 | spin_unlock_irqrestore(&up->port.lock, flags); | |
385 | ||
386 | /* | |
387 | * Finally, enable interrupts. Note: Modem status interrupts | |
80f7228b | 388 | * are set via set_termios(), which will be occurring imminently |
1da177e4 LT |
389 | * anyway, so we don't enable them here. |
390 | */ | |
391 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; | |
392 | serial_out(up, UART_IER, up->ier); | |
393 | ||
394 | /* | |
395 | * And clear the interrupt registers again for luck. | |
396 | */ | |
397 | (void) serial_in(up, UART_LSR); | |
398 | (void) serial_in(up, UART_RX); | |
399 | (void) serial_in(up, UART_IIR); | |
400 | (void) serial_in(up, UART_MSR); | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
405 | static void serial_pxa_shutdown(struct uart_port *port) | |
406 | { | |
407 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
408 | unsigned long flags; | |
409 | ||
410 | free_irq(up->port.irq, up); | |
411 | ||
412 | /* | |
413 | * Disable interrupts from this port | |
414 | */ | |
415 | up->ier = 0; | |
416 | serial_out(up, UART_IER, 0); | |
417 | ||
418 | spin_lock_irqsave(&up->port.lock, flags); | |
419 | up->port.mctrl &= ~TIOCM_OUT2; | |
420 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
421 | spin_unlock_irqrestore(&up->port.lock, flags); | |
422 | ||
423 | /* | |
424 | * Disable break condition and FIFOs | |
425 | */ | |
426 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
427 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
428 | UART_FCR_CLEAR_RCVR | | |
429 | UART_FCR_CLEAR_XMIT); | |
430 | serial_out(up, UART_FCR, 0); | |
431 | } | |
432 | ||
433 | static void | |
606d099c AC |
434 | serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, |
435 | struct ktermios *old) | |
1da177e4 LT |
436 | { |
437 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
438 | unsigned char cval, fcr = 0; | |
439 | unsigned long flags; | |
440 | unsigned int baud, quot; | |
c934878c | 441 | unsigned int dll; |
1da177e4 LT |
442 | |
443 | switch (termios->c_cflag & CSIZE) { | |
444 | case CS5: | |
0a8b80c5 | 445 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
446 | break; |
447 | case CS6: | |
0a8b80c5 | 448 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
449 | break; |
450 | case CS7: | |
0a8b80c5 | 451 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
452 | break; |
453 | default: | |
454 | case CS8: | |
0a8b80c5 | 455 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
456 | break; |
457 | } | |
458 | ||
459 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 460 | cval |= UART_LCR_STOP; |
1da177e4 LT |
461 | if (termios->c_cflag & PARENB) |
462 | cval |= UART_LCR_PARITY; | |
463 | if (!(termios->c_cflag & PARODD)) | |
464 | cval |= UART_LCR_EPAR; | |
465 | ||
466 | /* | |
467 | * Ask the core to calculate the divisor for us. | |
468 | */ | |
469 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
470 | quot = uart_get_divisor(port, baud); | |
471 | ||
472 | if ((up->port.uartclk / quot) < (2400 * 16)) | |
473 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; | |
d9e29649 | 474 | else if ((up->port.uartclk / quot) < (230400 * 16)) |
1da177e4 | 475 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; |
d9e29649 MR |
476 | else |
477 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; | |
1da177e4 LT |
478 | |
479 | /* | |
480 | * Ok, we're now changing the port state. Do it with | |
481 | * interrupts disabled. | |
482 | */ | |
483 | spin_lock_irqsave(&up->port.lock, flags); | |
484 | ||
485 | /* | |
486 | * Ensure the port will be enabled. | |
487 | * This is required especially for serial console. | |
488 | */ | |
290a5589 | 489 | up->ier |= UART_IER_UUE; |
1da177e4 LT |
490 | |
491 | /* | |
492 | * Update the per-port timeout. | |
493 | */ | |
e6158b4a | 494 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 LT |
495 | |
496 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
497 | if (termios->c_iflag & INPCK) | |
498 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
499 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
500 | up->port.read_status_mask |= UART_LSR_BI; | |
501 | ||
502 | /* | |
503 | * Characters to ignore | |
504 | */ | |
505 | up->port.ignore_status_mask = 0; | |
506 | if (termios->c_iflag & IGNPAR) | |
507 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
508 | if (termios->c_iflag & IGNBRK) { | |
509 | up->port.ignore_status_mask |= UART_LSR_BI; | |
510 | /* | |
511 | * If we're ignoring parity and break indicators, | |
512 | * ignore overruns too (for real raw support). | |
513 | */ | |
514 | if (termios->c_iflag & IGNPAR) | |
515 | up->port.ignore_status_mask |= UART_LSR_OE; | |
516 | } | |
517 | ||
518 | /* | |
519 | * ignore all characters if CREAD is not set | |
520 | */ | |
521 | if ((termios->c_cflag & CREAD) == 0) | |
522 | up->port.ignore_status_mask |= UART_LSR_DR; | |
523 | ||
524 | /* | |
525 | * CTS flow control flag and modem status interrupts | |
526 | */ | |
527 | up->ier &= ~UART_IER_MSI; | |
528 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
529 | up->ier |= UART_IER_MSI; | |
530 | ||
531 | serial_out(up, UART_IER, up->ier); | |
532 | ||
2276f03b RJ |
533 | if (termios->c_cflag & CRTSCTS) |
534 | up->mcr |= UART_MCR_AFE; | |
535 | else | |
536 | up->mcr &= ~UART_MCR_AFE; | |
537 | ||
c934878c | 538 | serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ |
1da177e4 | 539 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ |
c934878c UKK |
540 | |
541 | /* | |
542 | * work around Errata #75 according to Intel(R) PXA27x Processor Family | |
543 | * Specification Update (Nov 2005) | |
544 | */ | |
545 | dll = serial_in(up, UART_DLL); | |
546 | WARN_ON(dll != (quot & 0xff)); | |
547 | ||
1da177e4 | 548 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ |
c934878c | 549 | serial_out(up, UART_LCR, cval); /* reset DLAB */ |
1da177e4 LT |
550 | up->lcr = cval; /* Save LCR */ |
551 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
552 | serial_out(up, UART_FCR, fcr); | |
553 | spin_unlock_irqrestore(&up->port.lock, flags); | |
554 | } | |
555 | ||
556 | static void | |
557 | serial_pxa_pm(struct uart_port *port, unsigned int state, | |
558 | unsigned int oldstate) | |
559 | { | |
560 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
b049bd9d | 561 | |
1da177e4 | 562 | if (!state) |
b049bd9d RK |
563 | clk_enable(up->clk); |
564 | else | |
565 | clk_disable(up->clk); | |
1da177e4 LT |
566 | } |
567 | ||
568 | static void serial_pxa_release_port(struct uart_port *port) | |
569 | { | |
570 | } | |
571 | ||
572 | static int serial_pxa_request_port(struct uart_port *port) | |
573 | { | |
574 | return 0; | |
575 | } | |
576 | ||
577 | static void serial_pxa_config_port(struct uart_port *port, int flags) | |
578 | { | |
579 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
580 | up->port.type = PORT_PXA; | |
581 | } | |
582 | ||
583 | static int | |
584 | serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) | |
585 | { | |
586 | /* we don't want the core code to modify any port params */ | |
587 | return -EINVAL; | |
588 | } | |
589 | ||
590 | static const char * | |
591 | serial_pxa_type(struct uart_port *port) | |
592 | { | |
593 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
594 | return up->name; | |
595 | } | |
596 | ||
e259a3ae | 597 | static struct uart_pxa_port *serial_pxa_ports[4]; |
2d93486c | 598 | static struct uart_driver serial_pxa_reg; |
1da177e4 | 599 | |
fa7f1518 PZ |
600 | #ifdef CONFIG_SERIAL_PXA_CONSOLE |
601 | ||
1da177e4 LT |
602 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
603 | ||
604 | /* | |
605 | * Wait for transmitter & holding register to empty | |
606 | */ | |
607 | static inline void wait_for_xmitr(struct uart_pxa_port *up) | |
608 | { | |
609 | unsigned int status, tmout = 10000; | |
610 | ||
611 | /* Wait up to 10ms for the character(s) to be sent. */ | |
612 | do { | |
613 | status = serial_in(up, UART_LSR); | |
614 | ||
615 | if (status & UART_LSR_BI) | |
616 | up->lsr_break_flag = UART_LSR_BI; | |
617 | ||
618 | if (--tmout == 0) | |
619 | break; | |
620 | udelay(1); | |
621 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
622 | ||
623 | /* Wait up to 1s for flow control if necessary */ | |
624 | if (up->port.flags & UPF_CONS_FLOW) { | |
625 | tmout = 1000000; | |
626 | while (--tmout && | |
627 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | |
628 | udelay(1); | |
629 | } | |
630 | } | |
631 | ||
d358788f RK |
632 | static void serial_pxa_console_putchar(struct uart_port *port, int ch) |
633 | { | |
634 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
635 | ||
636 | wait_for_xmitr(up); | |
637 | serial_out(up, UART_TX, ch); | |
638 | } | |
639 | ||
1da177e4 LT |
640 | /* |
641 | * Print a string to the serial port trying not to disturb | |
642 | * any possible real use of the port... | |
643 | * | |
644 | * The console_lock must be held when we get here. | |
645 | */ | |
646 | static void | |
647 | serial_pxa_console_write(struct console *co, const char *s, unsigned int count) | |
648 | { | |
e259a3ae | 649 | struct uart_pxa_port *up = serial_pxa_ports[co->index]; |
1da177e4 | 650 | unsigned int ier; |
1da177e4 | 651 | |
b049bd9d RK |
652 | clk_enable(up->clk); |
653 | ||
1da177e4 | 654 | /* |
f02aa3f9 | 655 | * First save the IER then disable the interrupts |
1da177e4 LT |
656 | */ |
657 | ier = serial_in(up, UART_IER); | |
658 | serial_out(up, UART_IER, UART_IER_UUE); | |
659 | ||
d358788f | 660 | uart_console_write(&up->port, s, count, serial_pxa_console_putchar); |
1da177e4 LT |
661 | |
662 | /* | |
663 | * Finally, wait for transmitter to become empty | |
664 | * and restore the IER | |
665 | */ | |
666 | wait_for_xmitr(up); | |
667 | serial_out(up, UART_IER, ier); | |
b049bd9d RK |
668 | |
669 | clk_disable(up->clk); | |
1da177e4 LT |
670 | } |
671 | ||
672 | static int __init | |
673 | serial_pxa_console_setup(struct console *co, char *options) | |
674 | { | |
675 | struct uart_pxa_port *up; | |
676 | int baud = 9600; | |
677 | int bits = 8; | |
678 | int parity = 'n'; | |
679 | int flow = 'n'; | |
680 | ||
681 | if (co->index == -1 || co->index >= serial_pxa_reg.nr) | |
682 | co->index = 0; | |
e259a3ae RK |
683 | up = serial_pxa_ports[co->index]; |
684 | if (!up) | |
685 | return -ENODEV; | |
1da177e4 LT |
686 | |
687 | if (options) | |
688 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
689 | ||
690 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
691 | } | |
692 | ||
693 | static struct console serial_pxa_console = { | |
694 | .name = "ttyS", | |
695 | .write = serial_pxa_console_write, | |
696 | .device = uart_console_device, | |
697 | .setup = serial_pxa_console_setup, | |
698 | .flags = CON_PRINTBUFFER, | |
699 | .index = -1, | |
700 | .data = &serial_pxa_reg, | |
701 | }; | |
702 | ||
1da177e4 LT |
703 | #define PXA_CONSOLE &serial_pxa_console |
704 | #else | |
705 | #define PXA_CONSOLE NULL | |
706 | #endif | |
707 | ||
708 | struct uart_ops serial_pxa_pops = { | |
709 | .tx_empty = serial_pxa_tx_empty, | |
710 | .set_mctrl = serial_pxa_set_mctrl, | |
711 | .get_mctrl = serial_pxa_get_mctrl, | |
712 | .stop_tx = serial_pxa_stop_tx, | |
713 | .start_tx = serial_pxa_start_tx, | |
714 | .stop_rx = serial_pxa_stop_rx, | |
715 | .enable_ms = serial_pxa_enable_ms, | |
716 | .break_ctl = serial_pxa_break_ctl, | |
717 | .startup = serial_pxa_startup, | |
718 | .shutdown = serial_pxa_shutdown, | |
719 | .set_termios = serial_pxa_set_termios, | |
720 | .pm = serial_pxa_pm, | |
721 | .type = serial_pxa_type, | |
722 | .release_port = serial_pxa_release_port, | |
723 | .request_port = serial_pxa_request_port, | |
724 | .config_port = serial_pxa_config_port, | |
725 | .verify_port = serial_pxa_verify_port, | |
726 | }; | |
727 | ||
1da177e4 LT |
728 | static struct uart_driver serial_pxa_reg = { |
729 | .owner = THIS_MODULE, | |
730 | .driver_name = "PXA serial", | |
1da177e4 LT |
731 | .dev_name = "ttyS", |
732 | .major = TTY_MAJOR, | |
733 | .minor = 64, | |
e259a3ae | 734 | .nr = 4, |
1da177e4 LT |
735 | .cons = PXA_CONSOLE, |
736 | }; | |
737 | ||
bf56c751 MR |
738 | #ifdef CONFIG_PM |
739 | static int serial_pxa_suspend(struct device *dev) | |
1da177e4 | 740 | { |
bf56c751 | 741 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
1da177e4 | 742 | |
9480e307 | 743 | if (sport) |
1da177e4 LT |
744 | uart_suspend_port(&serial_pxa_reg, &sport->port); |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
bf56c751 | 749 | static int serial_pxa_resume(struct device *dev) |
1da177e4 | 750 | { |
bf56c751 | 751 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
1da177e4 | 752 | |
9480e307 | 753 | if (sport) |
1da177e4 LT |
754 | uart_resume_port(&serial_pxa_reg, &sport->port); |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
47145210 | 759 | static const struct dev_pm_ops serial_pxa_pm_ops = { |
bf56c751 MR |
760 | .suspend = serial_pxa_suspend, |
761 | .resume = serial_pxa_resume, | |
762 | }; | |
763 | #endif | |
764 | ||
3ae5eaec | 765 | static int serial_pxa_probe(struct platform_device *dev) |
1da177e4 | 766 | { |
e259a3ae RK |
767 | struct uart_pxa_port *sport; |
768 | struct resource *mmres, *irqres; | |
769 | int ret; | |
770 | ||
771 | mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
772 | irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0); | |
773 | if (!mmres || !irqres) | |
774 | return -ENODEV; | |
775 | ||
776 | sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); | |
777 | if (!sport) | |
778 | return -ENOMEM; | |
779 | ||
e0d8b13a | 780 | sport->clk = clk_get(&dev->dev, NULL); |
b049bd9d RK |
781 | if (IS_ERR(sport->clk)) { |
782 | ret = PTR_ERR(sport->clk); | |
783 | goto err_free; | |
784 | } | |
785 | ||
e259a3ae RK |
786 | sport->port.type = PORT_PXA; |
787 | sport->port.iotype = UPIO_MEM; | |
788 | sport->port.mapbase = mmres->start; | |
789 | sport->port.irq = irqres->start; | |
790 | sport->port.fifosize = 64; | |
791 | sport->port.ops = &serial_pxa_pops; | |
792 | sport->port.line = dev->id; | |
793 | sport->port.dev = &dev->dev; | |
794 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
b049bd9d | 795 | sport->port.uartclk = clk_get_rate(sport->clk); |
e259a3ae | 796 | |
290a5589 EM |
797 | switch (dev->id) { |
798 | case 0: sport->name = "FFUART"; break; | |
799 | case 1: sport->name = "BTUART"; break; | |
800 | case 2: sport->name = "STUART"; break; | |
801 | case 3: sport->name = "HWUART"; break; | |
802 | default: | |
e259a3ae | 803 | sport->name = "???"; |
290a5589 EM |
804 | break; |
805 | } | |
e259a3ae RK |
806 | |
807 | sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); | |
808 | if (!sport->port.membase) { | |
809 | ret = -ENOMEM; | |
b049bd9d | 810 | goto err_clk; |
e259a3ae RK |
811 | } |
812 | ||
813 | serial_pxa_ports[dev->id] = sport; | |
814 | ||
815 | uart_add_one_port(&serial_pxa_reg, &sport->port); | |
816 | platform_set_drvdata(dev, sport); | |
817 | ||
1da177e4 | 818 | return 0; |
e259a3ae | 819 | |
b049bd9d RK |
820 | err_clk: |
821 | clk_put(sport->clk); | |
e259a3ae RK |
822 | err_free: |
823 | kfree(sport); | |
824 | return ret; | |
1da177e4 LT |
825 | } |
826 | ||
3ae5eaec | 827 | static int serial_pxa_remove(struct platform_device *dev) |
1da177e4 | 828 | { |
3ae5eaec | 829 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 830 | |
3ae5eaec | 831 | platform_set_drvdata(dev, NULL); |
1da177e4 | 832 | |
e259a3ae | 833 | uart_remove_one_port(&serial_pxa_reg, &sport->port); |
b049bd9d | 834 | clk_put(sport->clk); |
e259a3ae | 835 | kfree(sport); |
1da177e4 LT |
836 | |
837 | return 0; | |
838 | } | |
839 | ||
3ae5eaec | 840 | static struct platform_driver serial_pxa_driver = { |
1da177e4 LT |
841 | .probe = serial_pxa_probe, |
842 | .remove = serial_pxa_remove, | |
843 | ||
3ae5eaec RK |
844 | .driver = { |
845 | .name = "pxa2xx-uart", | |
e169c139 | 846 | .owner = THIS_MODULE, |
bf56c751 MR |
847 | #ifdef CONFIG_PM |
848 | .pm = &serial_pxa_pm_ops, | |
849 | #endif | |
3ae5eaec | 850 | }, |
1da177e4 LT |
851 | }; |
852 | ||
853 | int __init serial_pxa_init(void) | |
854 | { | |
855 | int ret; | |
856 | ||
857 | ret = uart_register_driver(&serial_pxa_reg); | |
858 | if (ret != 0) | |
859 | return ret; | |
860 | ||
3ae5eaec | 861 | ret = platform_driver_register(&serial_pxa_driver); |
1da177e4 LT |
862 | if (ret != 0) |
863 | uart_unregister_driver(&serial_pxa_reg); | |
864 | ||
865 | return ret; | |
866 | } | |
867 | ||
868 | void __exit serial_pxa_exit(void) | |
869 | { | |
3ae5eaec | 870 | platform_driver_unregister(&serial_pxa_driver); |
1da177e4 LT |
871 | uart_unregister_driver(&serial_pxa_reg); |
872 | } | |
873 | ||
874 | module_init(serial_pxa_init); | |
875 | module_exit(serial_pxa_exit); | |
876 | ||
877 | MODULE_LICENSE("GPL"); | |
e169c139 | 878 | MODULE_ALIAS("platform:pxa2xx-uart"); |