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1da177e4
LT		 1/*
2 * linux/drivers/serial/pxa.c
3 *
4 * Based on drivers/serial/8250.c by Russell King.
5 *
6 * Author: Nicolas Pitre
7 * Created: Feb 20, 2003
8 * Copyright: (C) 2003 Monta Vista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * Note 1: This driver is made separate from the already too overloaded
16 * 8250.c because it needs some kirks of its own and that'll make it
17 * easier to add DMA support.
18 *
19 * Note 2: I'm too sick of device allocation policies for serial ports.
20 * If someone else wants to request an "official" allocation of major/minor
21 * for this driver please be my guest. And don't forget that new hardware
22 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
23 * hope for a better port registration and dynamic device allocation scheme
24 * with the serial core maintainer satisfaction to appear soon.
25 */
26
27#include <linux/config.h>
28
29#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/ioport.h>
35#include <linux/init.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
38#include <linux/serial_reg.h>
39#include <linux/circ_buf.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
d052d1be 42#include <linux/platform_device.h>
1da177e4
LT		 43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46
47#include <asm/io.h>
48#include <asm/hardware.h>
49#include <asm/irq.h>
50#include <asm/arch/pxa-regs.h>
51
52
53struct uart_pxa_port {
54 struct uart_port port;
55 unsigned char ier;
56 unsigned char lcr;
57 unsigned char mcr;
58 unsigned int lsr_break_flag;
59 unsigned int cken;
60 char *name;
61};
62
63static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
64{
65 offset <<= 2;
66 return readl(up->port.membase + offset);
67}
68
69static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
70{
71 offset <<= 2;
72 writel(value, up->port.membase + offset);
73}
74
75static void serial_pxa_enable_ms(struct uart_port *port)
76{
77 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
78
79 up->ier |= UART_IER_MSI;
80 serial_out(up, UART_IER, up->ier);
81}
82
b129a8cc 83static void serial_pxa_stop_tx(struct uart_port *port)
1da177e4
LT		 84{
85 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
86
87 if (up->ier & UART_IER_THRI) {
88 up->ier &= ~UART_IER_THRI;
89 serial_out(up, UART_IER, up->ier);
90 }
91}
92
93static void serial_pxa_stop_rx(struct uart_port *port)
94{
95 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
96
97 up->ier &= ~UART_IER_RLSI;
98 up->port.read_status_mask &= ~UART_LSR_DR;
99 serial_out(up, UART_IER, up->ier);
100}
101
102static inline void
103receive_chars(struct uart_pxa_port *up, int *status, struct pt_regs *regs)
104{
105 struct tty_struct *tty = up->port.info->tty;
106 unsigned int ch, flag;
107 int max_count = 256;
108
109 do {
1da177e4
LT		 110 ch = serial_in(up, UART_RX);
111 flag = TTY_NORMAL;
112 up->port.icount.rx++;
113
114 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
115 UART_LSR_FE | UART_LSR_OE))) {
116 /*
117 * For statistics only
118 */
119 if (*status & UART_LSR_BI) {
120 *status &= ~(UART_LSR_FE | UART_LSR_PE);
121 up->port.icount.brk++;
122 /*
123 * We do the SysRQ and SAK checking
124 * here because otherwise the break
125 * may get masked by ignore_status_mask
126 * or read_status_mask.
127 */
128 if (uart_handle_break(&up->port))
129 goto ignore_char;
130 } else if (*status & UART_LSR_PE)
131 up->port.icount.parity++;
132 else if (*status & UART_LSR_FE)
133 up->port.icount.frame++;
134 if (*status & UART_LSR_OE)
135 up->port.icount.overrun++;
136
137 /*
138 * Mask off conditions which should be ignored.
139 */
140 *status &= up->port.read_status_mask;
141
142#ifdef CONFIG_SERIAL_PXA_CONSOLE
143 if (up->port.line == up->port.cons->index) {
144 /* Recover the break flag from console xmit */
145 *status |= up->lsr_break_flag;
146 up->lsr_break_flag = 0;
147 }
148#endif
149 if (*status & UART_LSR_BI) {
150 flag = TTY_BREAK;
151 } else if (*status & UART_LSR_PE)
152 flag = TTY_PARITY;
153 else if (*status & UART_LSR_FE)
154 flag = TTY_FRAME;
155 }
05ab3014 156
1da177e4
LT		 157 if (uart_handle_sysrq_char(&up->port, ch, regs))
158 goto ignore_char;
05ab3014
RK		 159
160 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
161
1da177e4
LT		 162 ignore_char:
163 *status = serial_in(up, UART_LSR);
164 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
165 tty_flip_buffer_push(tty);
166}
167
168static void transmit_chars(struct uart_pxa_port *up)
169{
170 struct circ_buf *xmit = &up->port.info->xmit;
171 int count;
172
173 if (up->port.x_char) {
174 serial_out(up, UART_TX, up->port.x_char);
175 up->port.icount.tx++;
176 up->port.x_char = 0;
177 return;
178 }
179 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
b129a8cc 180 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 181 return;
182 }
183
184 count = up->port.fifosize / 2;
185 do {
186 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
187 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
188 up->port.icount.tx++;
189 if (uart_circ_empty(xmit))
190 break;
191 } while (--count > 0);
192
193 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
194 uart_write_wakeup(&up->port);
195
196
197 if (uart_circ_empty(xmit))
b129a8cc 198 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 199}
200
b129a8cc 201static void serial_pxa_start_tx(struct uart_port *port)
1da177e4
LT		 202{
203 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
204
205 if (!(up->ier & UART_IER_THRI)) {
206 up->ier |= UART_IER_THRI;
207 serial_out(up, UART_IER, up->ier);
208 }
209}
210
211static inline void check_modem_status(struct uart_pxa_port *up)
212{
213 int status;
214
215 status = serial_in(up, UART_MSR);
216
217 if ((status & UART_MSR_ANY_DELTA) == 0)
218 return;
219
220 if (status & UART_MSR_TERI)
221 up->port.icount.rng++;
222 if (status & UART_MSR_DDSR)
223 up->port.icount.dsr++;
224 if (status & UART_MSR_DDCD)
225 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
226 if (status & UART_MSR_DCTS)
227 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
228
229 wake_up_interruptible(&up->port.info->delta_msr_wait);
230}
231
232/*
233 * This handles the interrupt from one port.
234 */
235static inline irqreturn_t
236serial_pxa_irq(int irq, void *dev_id, struct pt_regs *regs)
237{
238 struct uart_pxa_port *up = (struct uart_pxa_port *)dev_id;
239 unsigned int iir, lsr;
240
241 iir = serial_in(up, UART_IIR);
242 if (iir & UART_IIR_NO_INT)
243 return IRQ_NONE;
244 lsr = serial_in(up, UART_LSR);
245 if (lsr & UART_LSR_DR)
246 receive_chars(up, &lsr, regs);
247 check_modem_status(up);
248 if (lsr & UART_LSR_THRE)
249 transmit_chars(up);
250 return IRQ_HANDLED;
251}
252
253static unsigned int serial_pxa_tx_empty(struct uart_port *port)
254{
255 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
256 unsigned long flags;
257 unsigned int ret;
258
259 spin_lock_irqsave(&up->port.lock, flags);
260 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
261 spin_unlock_irqrestore(&up->port.lock, flags);
262
263 return ret;
264}
265
266static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
267{
268 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
1da177e4
LT		 269 unsigned char status;
270 unsigned int ret;
271
1da177e4 272 status = serial_in(up, UART_MSR);
1da177e4
LT		 273
274 ret = 0;
275 if (status & UART_MSR_DCD)
276 ret |= TIOCM_CAR;
277 if (status & UART_MSR_RI)
278 ret |= TIOCM_RNG;
279 if (status & UART_MSR_DSR)
280 ret |= TIOCM_DSR;
281 if (status & UART_MSR_CTS)
282 ret |= TIOCM_CTS;
283 return ret;
284}
285
286static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
287{
288 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
289 unsigned char mcr = 0;
290
291 if (mctrl & TIOCM_RTS)
292 mcr |= UART_MCR_RTS;
293 if (mctrl & TIOCM_DTR)
294 mcr |= UART_MCR_DTR;
295 if (mctrl & TIOCM_OUT1)
296 mcr |= UART_MCR_OUT1;
297 if (mctrl & TIOCM_OUT2)
298 mcr |= UART_MCR_OUT2;
299 if (mctrl & TIOCM_LOOP)
300 mcr |= UART_MCR_LOOP;
301
302 mcr |= up->mcr;
303
304 serial_out(up, UART_MCR, mcr);
305}
306
307static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
308{
309 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
310 unsigned long flags;
311
312 spin_lock_irqsave(&up->port.lock, flags);
313 if (break_state == -1)
314 up->lcr |= UART_LCR_SBC;
315 else
316 up->lcr &= ~UART_LCR_SBC;
317 serial_out(up, UART_LCR, up->lcr);
318 spin_unlock_irqrestore(&up->port.lock, flags);
319}
320
321#if 0
322static void serial_pxa_dma_init(struct pxa_uart *up)
323{
324 up->rxdma =
325 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up);
326 if (up->rxdma < 0)
327 goto out;
328 up->txdma =
329 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up);
330 if (up->txdma < 0)
331 goto err_txdma;
332 up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL);
333 if (!up->dmadesc)
334 goto err_alloc;
335
336 /* ... */
337err_alloc:
338 pxa_free_dma(up->txdma);
339err_rxdma:
340 pxa_free_dma(up->rxdma);
341out:
342 return;
343}
344#endif
345
346static int serial_pxa_startup(struct uart_port *port)
347{
348 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
349 unsigned long flags;
350 int retval;
351
d9e29649
MR		 352 if (port->line == 3) /* HWUART */
353 up->mcr |= UART_MCR_AFE;
354 else
f02aa3f9 355 up->mcr = 0;
1da177e4
LT		 356
357 /*
358 * Allocate the IRQ
359 */
360 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
361 if (retval)
362 return retval;
363
364 /*
365 * Clear the FIFO buffers and disable them.
366 * (they will be reenabled in set_termios())
367 */
368 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
369 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
370 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
371 serial_out(up, UART_FCR, 0);
372
373 /*
374 * Clear the interrupt registers.
375 */
376 (void) serial_in(up, UART_LSR);
377 (void) serial_in(up, UART_RX);
378 (void) serial_in(up, UART_IIR);
379 (void) serial_in(up, UART_MSR);
380
381 /*
382 * Now, initialize the UART
383 */
384 serial_out(up, UART_LCR, UART_LCR_WLEN8);
385
386 spin_lock_irqsave(&up->port.lock, flags);
387 up->port.mctrl |= TIOCM_OUT2;
388 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
389 spin_unlock_irqrestore(&up->port.lock, flags);
390
391 /*
392 * Finally, enable interrupts. Note: Modem status interrupts
393 * are set via set_termios(), which will be occuring imminently
394 * anyway, so we don't enable them here.
395 */
396 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
397 serial_out(up, UART_IER, up->ier);
398
399 /*
400 * And clear the interrupt registers again for luck.
401 */
402 (void) serial_in(up, UART_LSR);
403 (void) serial_in(up, UART_RX);
404 (void) serial_in(up, UART_IIR);
405 (void) serial_in(up, UART_MSR);
406
407 return 0;
408}
409
410static void serial_pxa_shutdown(struct uart_port *port)
411{
412 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
413 unsigned long flags;
414
415 free_irq(up->port.irq, up);
416
417 /*
418 * Disable interrupts from this port
419 */
420 up->ier = 0;
421 serial_out(up, UART_IER, 0);
422
423 spin_lock_irqsave(&up->port.lock, flags);
424 up->port.mctrl &= ~TIOCM_OUT2;
425 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
426 spin_unlock_irqrestore(&up->port.lock, flags);
427
428 /*
429 * Disable break condition and FIFOs
430 */
431 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
432 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
433 UART_FCR_CLEAR_RCVR |
434 UART_FCR_CLEAR_XMIT);
435 serial_out(up, UART_FCR, 0);
436}
437
438static void
439serial_pxa_set_termios(struct uart_port *port, struct termios *termios,
440 struct termios *old)
441{
442 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
443 unsigned char cval, fcr = 0;
444 unsigned long flags;
445 unsigned int baud, quot;
446
447 switch (termios->c_cflag & CSIZE) {
448 case CS5:
0a8b80c5 449 cval = UART_LCR_WLEN5;
1da177e4
LT		 450 break;
451 case CS6:
0a8b80c5 452 cval = UART_LCR_WLEN6;
1da177e4
LT		 453 break;
454 case CS7:
0a8b80c5 455 cval = UART_LCR_WLEN7;
1da177e4
LT		 456 break;
457 default:
458 case CS8:
0a8b80c5 459 cval = UART_LCR_WLEN8;
1da177e4
LT		 460 break;
461 }
462
463 if (termios->c_cflag & CSTOPB)
0a8b80c5 464 cval |= UART_LCR_STOP;
1da177e4
LT		 465 if (termios->c_cflag & PARENB)
466 cval |= UART_LCR_PARITY;
467 if (!(termios->c_cflag & PARODD))
468 cval |= UART_LCR_EPAR;
469
470 /*
471 * Ask the core to calculate the divisor for us.
472 */
473 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
474 quot = uart_get_divisor(port, baud);
475
476 if ((up->port.uartclk / quot) < (2400 * 16))
477 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
d9e29649 478 else if ((up->port.uartclk / quot) < (230400 * 16))
1da177e4 479 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
d9e29649
MR		 480 else
481 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
1da177e4
LT		 482
483 /*
484 * Ok, we're now changing the port state. Do it with
485 * interrupts disabled.
486 */
487 spin_lock_irqsave(&up->port.lock, flags);
488
489 /*
490 * Ensure the port will be enabled.
491 * This is required especially for serial console.
492 */
493 up->ier |= IER_UUE;
494
495 /*
496 * Update the per-port timeout.
497 */
e6158b4a 498 uart_update_timeout(port, termios->c_cflag, baud);
1da177e4
LT		 499
500 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
501 if (termios->c_iflag & INPCK)
502 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
503 if (termios->c_iflag & (BRKINT | PARMRK))
504 up->port.read_status_mask |= UART_LSR_BI;
505
506 /*
507 * Characters to ignore
508 */
509 up->port.ignore_status_mask = 0;
510 if (termios->c_iflag & IGNPAR)
511 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
512 if (termios->c_iflag & IGNBRK) {
513 up->port.ignore_status_mask |= UART_LSR_BI;
514 /*
515 * If we're ignoring parity and break indicators,
516 * ignore overruns too (for real raw support).
517 */
518 if (termios->c_iflag & IGNPAR)
519 up->port.ignore_status_mask |= UART_LSR_OE;
520 }
521
522 /*
523 * ignore all characters if CREAD is not set
524 */
525 if ((termios->c_cflag & CREAD) == 0)
526 up->port.ignore_status_mask |= UART_LSR_DR;
527
528 /*
529 * CTS flow control flag and modem status interrupts
530 */
531 up->ier &= ~UART_IER_MSI;
532 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
533 up->ier |= UART_IER_MSI;
534
535 serial_out(up, UART_IER, up->ier);
536
537 serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
538 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
539 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
540 serial_out(up, UART_LCR, cval); /* reset DLAB */
541 up->lcr = cval; /* Save LCR */
542 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
543 serial_out(up, UART_FCR, fcr);
544 spin_unlock_irqrestore(&up->port.lock, flags);
545}
546
547static void
548serial_pxa_pm(struct uart_port *port, unsigned int state,
549 unsigned int oldstate)
550{
551 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
552 pxa_set_cken(up->cken, !state);
553 if (!state)
554 udelay(1);
555}
556
557static void serial_pxa_release_port(struct uart_port *port)
558{
559}
560
561static int serial_pxa_request_port(struct uart_port *port)
562{
563 return 0;
564}
565
566static void serial_pxa_config_port(struct uart_port *port, int flags)
567{
568 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
569 up->port.type = PORT_PXA;
570}
571
572static int
573serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
574{
575 /* we don't want the core code to modify any port params */
576 return -EINVAL;
577}
578
579static const char *
580serial_pxa_type(struct uart_port *port)
581{
582 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
583 return up->name;
584}
585
586#ifdef CONFIG_SERIAL_PXA_CONSOLE
587
2d93486c
VS		 588static struct uart_pxa_port serial_pxa_ports[];
589static struct uart_driver serial_pxa_reg;
1da177e4
LT		 590
591#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
592
593/*
594 * Wait for transmitter & holding register to empty
595 */
596static inline void wait_for_xmitr(struct uart_pxa_port *up)
597{
598 unsigned int status, tmout = 10000;
599
600 /* Wait up to 10ms for the character(s) to be sent. */
601 do {
602 status = serial_in(up, UART_LSR);
603
604 if (status & UART_LSR_BI)
605 up->lsr_break_flag = UART_LSR_BI;
606
607 if (--tmout == 0)
608 break;
609 udelay(1);
610 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
611
612 /* Wait up to 1s for flow control if necessary */
613 if (up->port.flags & UPF_CONS_FLOW) {
614 tmout = 1000000;
615 while (--tmout &&
616 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
617 udelay(1);
618 }
619}
620
d358788f
RK		 621static void serial_pxa_console_putchar(struct uart_port *port, int ch)
622{
623 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
624
625 wait_for_xmitr(up);
626 serial_out(up, UART_TX, ch);
627}
628
1da177e4
LT		 629/*
630 * Print a string to the serial port trying not to disturb
631 * any possible real use of the port...
632 *
633 * The console_lock must be held when we get here.
634 */
635static void
636serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
637{
638 struct uart_pxa_port *up = &serial_pxa_ports[co->index];
639 unsigned int ier;
1da177e4
LT		 640
641 /*
f02aa3f9 642 * First save the IER then disable the interrupts
1da177e4
LT		 643 */
644 ier = serial_in(up, UART_IER);
645 serial_out(up, UART_IER, UART_IER_UUE);
646
d358788f 647 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
1da177e4
LT		 648
649 /*
650 * Finally, wait for transmitter to become empty
651 * and restore the IER
652 */
653 wait_for_xmitr(up);
654 serial_out(up, UART_IER, ier);
655}
656
657static int __init
658serial_pxa_console_setup(struct console *co, char *options)
659{
660 struct uart_pxa_port *up;
661 int baud = 9600;
662 int bits = 8;
663 int parity = 'n';
664 int flow = 'n';
665
666 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
667 co->index = 0;
668 up = &serial_pxa_ports[co->index];
669
670 if (options)
671 uart_parse_options(options, &baud, &parity, &bits, &flow);
672
673 return uart_set_options(&up->port, co, baud, parity, bits, flow);
674}
675
676static struct console serial_pxa_console = {
677 .name = "ttyS",
678 .write = serial_pxa_console_write,
679 .device = uart_console_device,
680 .setup = serial_pxa_console_setup,
681 .flags = CON_PRINTBUFFER,
682 .index = -1,
683 .data = &serial_pxa_reg,
684};
685
686static int __init
687serial_pxa_console_init(void)
688{
689 register_console(&serial_pxa_console);
690 return 0;
691}
692
693console_initcall(serial_pxa_console_init);
694
695#define PXA_CONSOLE &serial_pxa_console
696#else
697#define PXA_CONSOLE NULL
698#endif
699
700struct uart_ops serial_pxa_pops = {
701 .tx_empty = serial_pxa_tx_empty,
702 .set_mctrl = serial_pxa_set_mctrl,
703 .get_mctrl = serial_pxa_get_mctrl,
704 .stop_tx = serial_pxa_stop_tx,
705 .start_tx = serial_pxa_start_tx,
706 .stop_rx = serial_pxa_stop_rx,
707 .enable_ms = serial_pxa_enable_ms,
708 .break_ctl = serial_pxa_break_ctl,
709 .startup = serial_pxa_startup,
710 .shutdown = serial_pxa_shutdown,
711 .set_termios = serial_pxa_set_termios,
712 .pm = serial_pxa_pm,
713 .type = serial_pxa_type,
714 .release_port = serial_pxa_release_port,
715 .request_port = serial_pxa_request_port,
716 .config_port = serial_pxa_config_port,
717 .verify_port = serial_pxa_verify_port,
718};
719
720static struct uart_pxa_port serial_pxa_ports[] = {
721 { /* FFUART */
722 .name = "FFUART",
723 .cken = CKEN6_FFUART,
724 .port = {
725 .type = PORT_PXA,
726 .iotype = UPIO_MEM,
727 .membase = (void *)&FFUART,
728 .mapbase = __PREG(FFUART),
729 .irq = IRQ_FFUART,
730 .uartclk = 921600 * 16,
731 .fifosize = 64,
732 .ops = &serial_pxa_pops,
733 .line = 0,
734 },
735 }, { /* BTUART */
736 .name = "BTUART",
737 .cken = CKEN7_BTUART,
738 .port = {
739 .type = PORT_PXA,
740 .iotype = UPIO_MEM,
741 .membase = (void *)&BTUART,
742 .mapbase = __PREG(BTUART),
743 .irq = IRQ_BTUART,
744 .uartclk = 921600 * 16,
745 .fifosize = 64,
746 .ops = &serial_pxa_pops,
747 .line = 1,
748 },
749 }, { /* STUART */
750 .name = "STUART",
751 .cken = CKEN5_STUART,
752 .port = {
753 .type = PORT_PXA,
754 .iotype = UPIO_MEM,
755 .membase = (void *)&STUART,
756 .mapbase = __PREG(STUART),
757 .irq = IRQ_STUART,
758 .uartclk = 921600 * 16,
759 .fifosize = 64,
760 .ops = &serial_pxa_pops,
761 .line = 2,
762 },
d9e29649
MR		 763 }, { /* HWUART */
764 .name = "HWUART",
765 .cken = CKEN4_HWUART,
766 .port = {
767 .type = PORT_PXA,
768 .iotype = UPIO_MEM,
769 .membase = (void *)&HWUART,
770 .mapbase = __PREG(HWUART),
771 .irq = IRQ_HWUART,
772 .uartclk = 921600 * 16,
773 .fifosize = 64,
774 .ops = &serial_pxa_pops,
775 .line = 3,
776 },
1da177e4
LT		 777 }
778};
779
780static struct uart_driver serial_pxa_reg = {
781 .owner = THIS_MODULE,
782 .driver_name = "PXA serial",
1da177e4
LT		 783 .dev_name = "ttyS",
784 .major = TTY_MAJOR,
785 .minor = 64,
786 .nr = ARRAY_SIZE(serial_pxa_ports),
787 .cons = PXA_CONSOLE,
788};
789
3ae5eaec 790static int serial_pxa_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 791{
3ae5eaec 792 struct uart_pxa_port *sport = platform_get_drvdata(dev);
1da177e4 793
9480e307 794 if (sport)
1da177e4
LT		 795 uart_suspend_port(&serial_pxa_reg, &sport->port);
796
797 return 0;
798}
799
3ae5eaec 800static int serial_pxa_resume(struct platform_device *dev)
1da177e4 801{
3ae5eaec 802 struct uart_pxa_port *sport = platform_get_drvdata(dev);
1da177e4 803
9480e307 804 if (sport)
1da177e4
LT		 805 uart_resume_port(&serial_pxa_reg, &sport->port);
806
807 return 0;
808}
809
3ae5eaec 810static int serial_pxa_probe(struct platform_device *dev)
1da177e4 811{
3ae5eaec 812 serial_pxa_ports[dev->id].port.dev = &dev->dev;
1da177e4 813 uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port);
3ae5eaec 814 platform_set_drvdata(dev, &serial_pxa_ports[dev->id]);
1da177e4
LT		 815 return 0;
816}
817
3ae5eaec 818static int serial_pxa_remove(struct platform_device *dev)
1da177e4 819{
3ae5eaec 820 struct uart_pxa_port *sport = platform_get_drvdata(dev);
1da177e4 821
3ae5eaec 822 platform_set_drvdata(dev, NULL);
1da177e4
LT		 823
824 if (sport)
825 uart_remove_one_port(&serial_pxa_reg, &sport->port);
826
827 return 0;
828}
829
3ae5eaec 830static struct platform_driver serial_pxa_driver = {
1da177e4
LT		 831 .probe = serial_pxa_probe,
832 .remove = serial_pxa_remove,
833
834 .suspend = serial_pxa_suspend,
835 .resume = serial_pxa_resume,
3ae5eaec
RK		 836 .driver = {
837 .name = "pxa2xx-uart",
838 },
1da177e4
LT		 839};
840
841int __init serial_pxa_init(void)
842{
843 int ret;
844
845 ret = uart_register_driver(&serial_pxa_reg);
846 if (ret != 0)
847 return ret;
848
3ae5eaec 849 ret = platform_driver_register(&serial_pxa_driver);
1da177e4
LT		 850 if (ret != 0)
851 uart_unregister_driver(&serial_pxa_reg);
852
853 return ret;
854}
855
856void __exit serial_pxa_exit(void)
857{
3ae5eaec 858 platform_driver_unregister(&serial_pxa_driver);
1da177e4
LT		 859 uart_unregister_driver(&serial_pxa_reg);
860}
861
862module_init(serial_pxa_init);
863module_exit(serial_pxa_exit);
864
865MODULE_LICENSE("GPL");
866
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