]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | #include <linux/serial_core.h> |
e108b2ca | 2 | #include <asm/io.h> |
1da177e4 | 3 | #include <asm/gpio.h> |
3ea6bc3d | 4 | |
1da177e4 LT |
5 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) |
6 | #include <asm/regs306x.h> | |
7 | #endif | |
8 | #if defined(CONFIG_H8S2678) | |
9 | #include <asm/regs267x.h> | |
10 | #endif | |
1da177e4 | 11 | |
0fbde950 MD |
12 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
13 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
14 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
15 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
1da177e4 LT |
16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | |
18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
1da177e4 LT |
19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
20 | # define SCIF0 0xA4400000 | |
21 | # define SCIF2 0xA4410000 | |
b7a76e4b PM |
22 | # define SCSMR_Ir 0xA44A0000 |
23 | # define IRDA_SCIF SCIF0 | |
1da177e4 LT |
24 | # define SCPCR 0xA4000116 |
25 | # define SCPDR 0xA4000136 | |
26 | ||
27 | /* Set the clock source, | |
28 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | |
29 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | |
30 | */ | |
31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | |
31a49c4b YS |
32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
33 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
3ea6bc3d | 34 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
fd88cac9 PM |
35 | # define PORT_PTCR 0xA405011EUL |
36 | # define PORT_PVCR 0xA4050122UL | |
37 | # define SCIF_ORER 0x0200 /* overrun error bit */ | |
1da177e4 | 38 | #elif defined(CONFIG_SH_RTS7751R2D) |
7abc404a | 39 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ |
1da177e4 LT |
40 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
41 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
42 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
05627486 PM |
43 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
44 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
45 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
46 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
47 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
48 | defined(CONFIG_CPU_SUBTYPE_SH7751R) | |
1da177e4 LT |
49 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
50 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
51 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
52 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | |
53 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
54 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | |
1da177e4 | 55 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
b7a76e4b PM |
56 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
57 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | |
58 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | |
1da177e4 LT |
59 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
60 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
2b1bd1ac | 61 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
e108b2ca | 62 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
9465a54f NI |
63 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
64 | # define PACR 0xa4050100 | |
65 | # define PBCR 0xa4050102 | |
66 | # define SCSCR_INIT(port) 0x3B | |
e108b2ca PM |
67 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
68 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | |
69 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | |
70 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | |
71 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | |
72 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | |
41504c39 | 73 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
346b7463 MD |
74 | # define PADR 0xA4050120 |
75 | # define PSDR 0xA405013e | |
76 | # define PWDR 0xA4050166 | |
77 | # define PSCR 0xA405011E | |
41504c39 PM |
78 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
79 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
9109a30e MD |
80 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
81 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
82 | # define SCSPTR0 SCPDR0 | |
83 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
84 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
178dd0cd PM |
85 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
86 | # define SCSPTR0 0xa4050160 | |
87 | # define SCSPTR1 0xa405013e | |
88 | # define SCSPTR2 0xa4050160 | |
89 | # define SCSPTR3 0xa405013e | |
90 | # define SCSPTR4 0xa4050128 | |
91 | # define SCSPTR5 0xa4050128 | |
92 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
93 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
1da177e4 | 94 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
1da177e4 LT |
95 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
96 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
97 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
1da177e4 | 98 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
1da177e4 LT |
99 | # define SCIF_BASE_ADDR 0x01030000 |
100 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | |
101 | # define SCIF_PTR2_OFFS 0x0000020 | |
102 | # define SCIF_LSR2_OFFS 0x0000024 | |
1da177e4 LT |
103 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
104 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | |
f9669187 | 105 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
1da177e4 | 106 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
1da177e4 | 107 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
1da177e4 LT |
108 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
109 | #elif defined(CONFIG_H8S2678) | |
1da177e4 | 110 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
1da177e4 | 111 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
7d740a06 YS |
112 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
113 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
114 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | |
c63847a3 | 115 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
7d740a06 | 116 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
c63847a3 | 117 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
b7a76e4b PM |
118 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
119 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | |
120 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | |
121 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | |
122 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
123 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | |
b7a76e4b PM |
124 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
125 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
126 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | |
e108b2ca | 127 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
b7a76e4b | 128 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
32351a28 PM |
129 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
130 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | |
131 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | |
132 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | |
133 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | |
134 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | |
135 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | |
34aeb43e | 136 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
32351a28 | 137 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
2825999e PG |
138 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ |
139 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | |
a8f67f4b PM |
140 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
141 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
9d4436a6 YS |
142 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ |
143 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | |
144 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | |
145 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | |
2825999e PG |
146 | # if defined(CONFIG_CPU_SUBTYPE_SH7201) |
147 | # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ | |
148 | # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ | |
149 | # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ | |
150 | # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ | |
151 | # endif | |
9d4436a6 | 152 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
9d4436a6 YS |
153 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
154 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | |
155 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | |
156 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | |
157 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
158 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
2b1bd1ac PM |
159 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
160 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | |
161 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | |
162 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ | |
163 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | |
164 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | |
165 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
1da177e4 LT |
166 | #else |
167 | # error CPU subtype not defined | |
168 | #endif | |
169 | ||
170 | /* SCSCR */ | |
171 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ | |
172 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | |
173 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | |
174 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | |
05627486 PM |
175 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
176 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
177 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
a8884e34 | 178 | defined(CONFIG_CPU_SUBTYPE_SH7722) || \ |
05627486 PM |
179 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
180 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
181 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
c63847a3 | 182 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
05627486 | 183 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
2b1bd1ac PM |
184 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
185 | defined(CONFIG_CPU_SUBTYPE_SHX3) | |
1da177e4 LT |
186 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
187 | #else | |
188 | #define SCI_CTRL_FLAGS_REIE 0 | |
189 | #endif | |
190 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
191 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
192 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ | |
193 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ | |
194 | ||
195 | /* SCxSR SCI */ | |
196 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
197 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
198 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
199 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
200 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
201 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
202 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
203 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
204 | ||
205 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | |
206 | ||
207 | /* SCxSR SCIF */ | |
208 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
209 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
210 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
211 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
212 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
213 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
214 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
215 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
216 | ||
3ea6bc3d | 217 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b YS |
218 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
219 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
c63847a3 NI |
220 | # define SCIF_ORER 0x0200 |
221 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | |
222 | # define SCIF_RFDC_MASK 0x007f | |
223 | # define SCIF_TXROOM_MAX 64 | |
224 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | |
225 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK ) | |
226 | # define SCIF_RFDC_MASK 0x007f | |
227 | # define SCIF_TXROOM_MAX 64 | |
228 | /* SH7763 SCIF2 support */ | |
229 | # define SCIF2_RFDC_MASK 0x001f | |
230 | # define SCIF2_TXROOM_MAX 16 | |
1da177e4 | 231 | #else |
c63847a3 NI |
232 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
233 | # define SCIF_RFDC_MASK 0x001f | |
234 | # define SCIF_TXROOM_MAX 16 | |
1da177e4 LT |
235 | #endif |
236 | ||
d830fa45 PM |
237 | #ifndef SCIF_ORER |
238 | #define SCIF_ORER 0x0000 | |
239 | #endif | |
240 | ||
15c73aaa PM |
241 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
242 | #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | |
243 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | |
244 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
245 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
246 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
247 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
d830fa45 | 248 | #define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) |
15c73aaa | 249 | |
3ea6bc3d | 250 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b YS |
251 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
252 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
15c73aaa PM |
253 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
254 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) | |
255 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) | |
256 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) | |
1da177e4 | 257 | #else |
1da177e4 LT |
258 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
259 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
260 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
261 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
262 | #endif | |
263 | ||
264 | /* SCFCR */ | |
265 | #define SCFCR_RFRST 0x0002 | |
266 | #define SCFCR_TFRST 0x0004 | |
267 | #define SCFCR_TCRST 0x4000 | |
268 | #define SCFCR_MCE 0x0008 | |
269 | ||
270 | #define SCI_MAJOR 204 | |
271 | #define SCI_MINOR_START 8 | |
272 | ||
273 | /* Generic serial flags */ | |
274 | #define SCI_RX_THROTTLE 0x0000001 | |
275 | ||
276 | #define SCI_MAGIC 0xbabeface | |
277 | ||
278 | /* | |
279 | * Events are used to schedule things to happen at timer-interrupt | |
280 | * time, instead of at rs interrupt time. | |
281 | */ | |
282 | #define SCI_EVENT_WRITE_WAKEUP 0 | |
283 | ||
1da177e4 | 284 | #define SCI_IN(size, offset) \ |
b7a76e4b | 285 | if ((size) == 8) { \ |
7ff731ae | 286 | return ioread8(port->membase + (offset)); \ |
b7a76e4b | 287 | } else { \ |
7ff731ae | 288 | return ioread16(port->membase + (offset)); \ |
1da177e4 LT |
289 | } |
290 | #define SCI_OUT(size, offset, value) \ | |
b7a76e4b | 291 | if ((size) == 8) { \ |
7ff731ae | 292 | iowrite8(value, port->membase + (offset)); \ |
3d2c2f3e | 293 | } else if ((size) == 16) { \ |
7ff731ae | 294 | iowrite16(value, port->membase + (offset)); \ |
1da177e4 LT |
295 | } |
296 | ||
297 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | |
298 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
299 | { \ | |
1a22f08d YS |
300 | if (port->type == PORT_SCIF) { \ |
301 | SCI_IN(scif_size, scif_offset) \ | |
302 | } else { /* PORT_SCI or PORT_SCIFA */ \ | |
303 | SCI_IN(sci_size, sci_offset); \ | |
1da177e4 LT |
304 | } \ |
305 | } \ | |
306 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
307 | { \ | |
1a22f08d YS |
308 | if (port->type == PORT_SCIF) { \ |
309 | SCI_OUT(scif_size, scif_offset, value) \ | |
310 | } else { /* PORT_SCI or PORT_SCIFA */ \ | |
311 | SCI_OUT(sci_size, sci_offset, value); \ | |
1da177e4 LT |
312 | } \ |
313 | } | |
314 | ||
315 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
316 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
317 | { \ | |
b7a76e4b | 318 | SCI_IN(scif_size, scif_offset); \ |
1da177e4 LT |
319 | } \ |
320 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
321 | { \ | |
322 | SCI_OUT(scif_size, scif_offset, value); \ | |
323 | } | |
324 | ||
325 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | |
326 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | |
327 | { \ | |
b7a76e4b | 328 | SCI_IN(sci_size, sci_offset); \ |
1da177e4 LT |
329 | } \ |
330 | static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ | |
331 | { \ | |
332 | SCI_OUT(sci_size, sci_offset, value); \ | |
333 | } | |
334 | ||
335 | #ifdef CONFIG_CPU_SH3 | |
9465a54f NI |
336 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
337 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
338 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
339 | h8_sci_offset, h8_sci_size) \ | |
340 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
341 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
342 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
3ea6bc3d | 343 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b YS |
344 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
345 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
1da177e4 LT |
346 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
347 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
348 | #else | |
349 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
350 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
351 | h8_sci_offset, h8_sci_size) \ | |
352 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) | |
353 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
354 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | |
355 | #endif | |
356 | #elif defined(__H8300H__) || defined(__H8300S__) | |
357 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
358 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
359 | h8_sci_offset, h8_sci_size) \ | |
360 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | |
361 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) | |
178dd0cd PM |
362 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
363 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ | |
364 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) | |
365 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | |
366 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
1da177e4 LT |
367 | #else |
368 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
369 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
370 | h8_sci_offset, h8_sci_size) \ | |
371 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
372 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
373 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
374 | #endif | |
375 | ||
3ea6bc3d | 376 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b YS |
377 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
378 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
9465a54f | 379 | |
1da177e4 LT |
380 | SCIF_FNS(SCSMR, 0x00, 16) |
381 | SCIF_FNS(SCBRR, 0x04, 8) | |
382 | SCIF_FNS(SCSCR, 0x08, 16) | |
383 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
384 | SCIF_FNS(SCFER, 0x10, 16) | |
385 | SCIF_FNS(SCxSR, 0x14, 16) | |
386 | SCIF_FNS(SCFCR, 0x18, 16) | |
387 | SCIF_FNS(SCFDR, 0x1c, 16) | |
388 | SCIF_FNS(SCxTDR, 0x20, 8) | |
389 | SCIF_FNS(SCxRDR, 0x24, 8) | |
390 | SCIF_FNS(SCLSR, 0x24, 16) | |
178dd0cd PM |
391 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
392 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) | |
393 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) | |
394 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) | |
395 | SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) | |
396 | SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) | |
397 | SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) | |
f686359e | 398 | SCIx_FNS(SCSPTR, 0, 0, 0, 0) |
178dd0cd PM |
399 | SCIF_FNS(SCTDSR, 0x0c, 8) |
400 | SCIF_FNS(SCFER, 0x10, 16) | |
401 | SCIF_FNS(SCFCR, 0x18, 16) | |
402 | SCIF_FNS(SCFDR, 0x1c, 16) | |
403 | SCIF_FNS(SCLSR, 0x24, 16) | |
1da177e4 LT |
404 | #else |
405 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | |
406 | /* name off sz off sz off sz off sz off sz*/ | |
407 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | |
408 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | |
409 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | |
410 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |
411 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | |
412 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | |
413 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | |
32351a28 PM |
414 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
415 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
416 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
c2697968 | 417 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
b7a76e4b PM |
418 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
419 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
420 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
421 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
c2697968 | 422 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
c63847a3 NI |
423 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) |
424 | SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) | |
c2697968 PM |
425 | SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) |
426 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) | |
427 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
428 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
429 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
b7a76e4b | 430 | #else |
1da177e4 | 431 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
9b4e466f MD |
432 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) |
433 | SCIF_FNS(SCSPTR, 0, 0, 0, 0) | |
434 | #else | |
1da177e4 | 435 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) |
9b4e466f | 436 | #endif |
1da177e4 LT |
437 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) |
438 | #endif | |
b7a76e4b | 439 | #endif |
1da177e4 LT |
440 | #define sci_in(port, reg) sci_##reg##_in(port) |
441 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | |
442 | ||
443 | /* H8/300 series SCI pins assignment */ | |
444 | #if defined(__H8300H__) || defined(__H8300S__) | |
445 | static const struct __attribute__((packed)) { | |
446 | int port; /* GPIO port no */ | |
447 | unsigned short rx,tx; /* GPIO bit no */ | |
448 | } h8300_sci_pins[] = { | |
449 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
450 | { /* SCI0 */ | |
451 | .port = H8300_GPIO_P9, | |
452 | .rx = H8300_GPIO_B2, | |
453 | .tx = H8300_GPIO_B0, | |
454 | }, | |
455 | { /* SCI1 */ | |
456 | .port = H8300_GPIO_P9, | |
457 | .rx = H8300_GPIO_B3, | |
458 | .tx = H8300_GPIO_B1, | |
459 | }, | |
460 | { /* SCI2 */ | |
461 | .port = H8300_GPIO_PB, | |
462 | .rx = H8300_GPIO_B7, | |
463 | .tx = H8300_GPIO_B6, | |
464 | } | |
465 | #elif defined(CONFIG_H8S2678) | |
466 | { /* SCI0 */ | |
467 | .port = H8300_GPIO_P3, | |
468 | .rx = H8300_GPIO_B2, | |
469 | .tx = H8300_GPIO_B0, | |
470 | }, | |
471 | { /* SCI1 */ | |
472 | .port = H8300_GPIO_P3, | |
473 | .rx = H8300_GPIO_B3, | |
474 | .tx = H8300_GPIO_B1, | |
475 | }, | |
476 | { /* SCI2 */ | |
477 | .port = H8300_GPIO_P5, | |
478 | .rx = H8300_GPIO_B1, | |
479 | .tx = H8300_GPIO_B0, | |
480 | } | |
481 | #endif | |
482 | }; | |
483 | #endif | |
484 | ||
0fbde950 MD |
485 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
486 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
487 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
488 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
1da177e4 LT |
489 | static inline int sci_rxd_in(struct uart_port *port) |
490 | { | |
491 | if (port->mapbase == 0xfffffe80) | |
492 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
493 | if (port->mapbase == 0xa4000150) | |
494 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
495 | if (port->mapbase == 0xa4000140) | |
496 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
497 | return 1; | |
498 | } | |
499 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
500 | static inline int sci_rxd_in(struct uart_port *port) | |
501 | { | |
502 | if (port->mapbase == SCIF0) | |
503 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
504 | if (port->mapbase == SCIF2) | |
505 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
506 | return 1; | |
507 | } | |
9465a54f | 508 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
e108b2ca PM |
509 | static inline int sci_rxd_in(struct uart_port *port) |
510 | { | |
9465a54f NI |
511 | return sci_in(port,SCxSR)&0x0010 ? 1 : 0; |
512 | } | |
31a49c4b YS |
513 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
514 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
3ea6bc3d MB |
515 | static inline int sci_rxd_in(struct uart_port *port) |
516 | { | |
517 | if (port->mapbase == 0xa4430000) | |
518 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | |
519 | else if (port->mapbase == 0xa4438000) | |
520 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | |
521 | return 1; | |
522 | } | |
05627486 PM |
523 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
524 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
525 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
526 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
527 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
961e9ff9 | 528 | defined(CONFIG_CPU_SUBTYPE_SH7091) |
1da177e4 LT |
529 | static inline int sci_rxd_in(struct uart_port *port) |
530 | { | |
1da177e4 LT |
531 | if (port->mapbase == 0xffe00000) |
532 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
1da177e4 LT |
533 | if (port->mapbase == 0xffe80000) |
534 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
1da177e4 LT |
535 | return 1; |
536 | } | |
961e9ff9 NI |
537 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
538 | static inline int sci_rxd_in(struct uart_port *port) | |
539 | { | |
540 | if (port->mapbase == 0xffe80000) | |
541 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
542 | return 1; | |
543 | } | |
1da177e4 LT |
544 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
545 | static inline int sci_rxd_in(struct uart_port *port) | |
546 | { | |
547 | if (port->mapbase == 0xfe600000) | |
548 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
549 | if (port->mapbase == 0xfe610000) | |
550 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
551 | if (port->mapbase == 0xfe620000) | |
552 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 553 | return 1; |
1da177e4 | 554 | } |
e108b2ca PM |
555 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
556 | static inline int sci_rxd_in(struct uart_port *port) | |
557 | { | |
558 | if (port->mapbase == 0xffe00000) | |
559 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
560 | if (port->mapbase == 0xffe10000) | |
561 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
562 | if (port->mapbase == 0xffe20000) | |
563 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
564 | if (port->mapbase == 0xffe30000) | |
565 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
566 | return 1; | |
567 | } | |
346b7463 | 568 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
41504c39 PM |
569 | static inline int sci_rxd_in(struct uart_port *port) |
570 | { | |
571 | if (port->mapbase == 0xffe00000) | |
572 | return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | |
573 | return 1; | |
574 | } | |
346b7463 MD |
575 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
576 | static inline int sci_rxd_in(struct uart_port *port) | |
577 | { | |
578 | if (port->mapbase == 0xffe00000) | |
579 | return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ | |
580 | if (port->mapbase == 0xffe10000) | |
581 | return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ | |
582 | if (port->mapbase == 0xffe20000) | |
583 | return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ | |
584 | ||
585 | return 1; | |
586 | } | |
178dd0cd PM |
587 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
588 | static inline int sci_rxd_in(struct uart_port *port) | |
589 | { | |
590 | if (port->mapbase == 0xffe00000) | |
591 | return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ | |
592 | if (port->mapbase == 0xffe10000) | |
593 | return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ | |
594 | if (port->mapbase == 0xffe20000) | |
595 | return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ | |
596 | if (port->mapbase == 0xa4e30000) | |
597 | return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ | |
598 | if (port->mapbase == 0xa4e40000) | |
599 | return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ | |
600 | if (port->mapbase == 0xa4e50000) | |
601 | return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ | |
602 | return 1; | |
603 | } | |
1da177e4 LT |
604 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
605 | static inline int sci_rxd_in(struct uart_port *port) | |
606 | { | |
aeffd54a | 607 | return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ |
1da177e4 LT |
608 | } |
609 | #elif defined(__H8300H__) || defined(__H8300S__) | |
610 | static inline int sci_rxd_in(struct uart_port *port) | |
611 | { | |
612 | int ch = (port->mapbase - SMR0) >> 3; | |
613 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | |
614 | } | |
7d740a06 YS |
615 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
616 | static inline int sci_rxd_in(struct uart_port *port) | |
617 | { | |
618 | if (port->mapbase == 0xffe00000) | |
619 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
620 | if (port->mapbase == 0xffe08000) | |
621 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
c63847a3 NI |
622 | if (port->mapbase == 0xffe10000) |
623 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ | |
624 | ||
7d740a06 YS |
625 | return 1; |
626 | } | |
b7a76e4b PM |
627 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
628 | static inline int sci_rxd_in(struct uart_port *port) | |
629 | { | |
630 | if (port->mapbase == 0xff923000) | |
631 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
632 | if (port->mapbase == 0xff924000) | |
633 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
634 | if (port->mapbase == 0xff925000) | |
635 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 636 | return 1; |
b7a76e4b PM |
637 | } |
638 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
639 | static inline int sci_rxd_in(struct uart_port *port) | |
640 | { | |
641 | if (port->mapbase == 0xffe00000) | |
642 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
643 | if (port->mapbase == 0xffe10000) | |
644 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 645 | return 1; |
b7a76e4b | 646 | } |
32351a28 PM |
647 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
648 | static inline int sci_rxd_in(struct uart_port *port) | |
649 | { | |
650 | if (port->mapbase == 0xffea0000) | |
651 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
652 | if (port->mapbase == 0xffeb0000) | |
653 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
654 | if (port->mapbase == 0xffec0000) | |
655 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
656 | if (port->mapbase == 0xffed0000) | |
657 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
658 | if (port->mapbase == 0xffee0000) | |
659 | return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | |
660 | if (port->mapbase == 0xffef0000) | |
661 | return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | |
662 | return 1; | |
663 | } | |
2825999e PG |
664 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ |
665 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | |
a8f67f4b PM |
666 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
667 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
9d4436a6 YS |
668 | static inline int sci_rxd_in(struct uart_port *port) |
669 | { | |
670 | if (port->mapbase == 0xfffe8000) | |
671 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
672 | if (port->mapbase == 0xfffe8800) | |
673 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
674 | if (port->mapbase == 0xfffe9000) | |
675 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
676 | if (port->mapbase == 0xfffe9800) | |
677 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
2825999e PG |
678 | #if defined(CONFIG_CPU_SUBTYPE_SH7201) |
679 | if (port->mapbase == 0xfffeA000) | |
680 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
681 | if (port->mapbase == 0xfffeA800) | |
682 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
683 | if (port->mapbase == 0xfffeB000) | |
684 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
685 | if (port->mapbase == 0xfffeB800) | |
686 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
687 | #endif | |
31388750 | 688 | return 1; |
9d4436a6 YS |
689 | } |
690 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
691 | static inline int sci_rxd_in(struct uart_port *port) | |
692 | { | |
693 | if (port->mapbase == 0xf8400000) | |
694 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
695 | if (port->mapbase == 0xf8410000) | |
696 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
697 | if (port->mapbase == 0xf8420000) | |
698 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 699 | return 1; |
9d4436a6 | 700 | } |
2b1bd1ac PM |
701 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
702 | static inline int sci_rxd_in(struct uart_port *port) | |
703 | { | |
704 | if (port->mapbase == 0xffc30000) | |
705 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
706 | if (port->mapbase == 0xffc40000) | |
707 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
708 | if (port->mapbase == 0xffc50000) | |
709 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
710 | if (port->mapbase == 0xffc60000) | |
711 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
1760b7d7 | 712 | return 1; |
2b1bd1ac | 713 | } |
1da177e4 LT |
714 | #endif |
715 | ||
716 | /* | |
717 | * Values for the BitRate Register (SCBRR) | |
718 | * | |
719 | * The values are actually divisors for a frequency which can | |
720 | * be internal to the SH3 (14.7456MHz) or derived from an external | |
721 | * clock source. This driver assumes the internal clock is used; | |
722 | * to support using an external clock source, config options or | |
723 | * possibly command-line options would need to be added. | |
724 | * | |
725 | * Also, to support speeds below 2400 (why?) the lower 2 bits of | |
726 | * the SCSMR register would also need to be set to non-zero values. | |
727 | * | |
728 | * -- Greg Banks 27Feb2000 | |
729 | * | |
730 | * Answer: The SCBRR register is only eight bits, and the value in | |
731 | * it gets larger with lower baud rates. At around 2400 (depending on | |
732 | * the peripherial module clock) you run out of bits. However the | |
733 | * lower two bits of SCSMR allow the module clock to be divided down, | |
734 | * scaling the value which is needed in SCBRR. | |
735 | * | |
736 | * -- Stuart Menefy - 23 May 2000 | |
737 | * | |
738 | * I meant, why would anyone bother with bitrates below 2400. | |
739 | * | |
740 | * -- Greg Banks - 7Jul2000 | |
741 | * | |
742 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper | |
743 | * tape reader as a console! | |
744 | * | |
745 | * -- Mitch Davis - 15 Jul 2000 | |
746 | */ | |
747 | ||
c63847a3 | 748 | #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
32351a28 | 749 | defined(CONFIG_CPU_SUBTYPE_SH7785) |
b7a76e4b | 750 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
3ea6bc3d | 751 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b YS |
752 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
753 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
b7a76e4b | 754 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
178dd0cd | 755 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
ba1d2818 NI |
756 | static inline int scbrr_calc(struct uart_port *port, int bps, int clk) |
757 | { | |
758 | if (port->type == PORT_SCIF) | |
759 | return (clk+16*bps)/(32*bps)-1; | |
760 | else | |
761 | return ((clk*2)+16*bps)/(16*bps)-1; | |
762 | } | |
763 | #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) | |
b7a76e4b | 764 | #elif defined(__H8300H__) || defined(__H8300S__) |
a2159b52 | 765 | #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) |
b7a76e4b PM |
766 | #else /* Generic SH */ |
767 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | |
1da177e4 | 768 | #endif |