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[SPARC]: sparc32 side of of_device layer IRQ resolution.
[mirror_ubuntu-bionic-kernel.git] / drivers / serial / sunzilog.c
CommitLineData
1da177e4
LT		 1/*
2 * sunzilog.c
3 *
4 * Driver for Zilog serial chips found on Sun workstations and
5 * servers. This driver could actually be made more generic.
6 *
7 * This is based on the old drivers/sbus/char/zs.c code. A lot
8 * of code has been simply moved over directly from there but
9 * much has been rewritten. Credits therefore go out to Eddie
10 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
11 * work there.
12 *
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
14 */
15
16#include <linux/config.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/major.h>
25#include <linux/string.h>
26#include <linux/ptrace.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/circ_buf.h>
30#include <linux/serial.h>
31#include <linux/sysrq.h>
32#include <linux/console.h>
33#include <linux/spinlock.h>
34#ifdef CONFIG_SERIO
35#include <linux/serio.h>
36#endif
37#include <linux/init.h>
38
39#include <asm/io.h>
40#include <asm/irq.h>
41#ifdef CONFIG_SPARC64
42#include <asm/fhc.h>
43#endif
44#include <asm/sbus.h>
45
46#if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47#define SUPPORT_SYSRQ
48#endif
49
50#include <linux/serial_core.h>
51
52#include "suncore.h"
53#include "sunzilog.h"
54
55/* On 32-bit sparcs we need to delay after register accesses
56 * to accommodate sun4 systems, but we do not need to flush writes.
57 * On 64-bit sparc we only need to flush single writes to ensure
58 * completion.
59 */
60#ifndef CONFIG_SPARC64
61#define ZSDELAY() udelay(5)
62#define ZSDELAY_LONG() udelay(20)
63#define ZS_WSYNC(channel) do { } while (0)
64#else
65#define ZSDELAY()
66#define ZSDELAY_LONG()
67#define ZS_WSYNC(__channel) \
68 sbus_readb(&((__channel)->control))
69#endif
70
71static int num_sunzilog;
72#define NUM_SUNZILOG num_sunzilog
73#define NUM_CHANNELS (NUM_SUNZILOG * 2)
74
75#define KEYBOARD_LINE 0x2
76#define MOUSE_LINE 0x3
77
78#define ZS_CLOCK 4915200 /* Zilog input clock rate. */
79#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
80
81/*
82 * We wrap our port structure around the generic uart_port.
83 */
84struct uart_sunzilog_port {
85 struct uart_port port;
86
87 /* IRQ servicing chain. */
88 struct uart_sunzilog_port *next;
89
90 /* Current values of Zilog write registers. */
91 unsigned char curregs[NUM_ZSREGS];
92
93 unsigned int flags;
94#define SUNZILOG_FLAG_CONS_KEYB 0x00000001
95#define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
96#define SUNZILOG_FLAG_IS_CONS 0x00000004
97#define SUNZILOG_FLAG_IS_KGDB 0x00000008
98#define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
99#define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
100#define SUNZILOG_FLAG_REGS_HELD 0x00000040
101#define SUNZILOG_FLAG_TX_STOPPED 0x00000080
102#define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
103
104 unsigned int cflag;
105
106 unsigned char parity_mask;
107 unsigned char prev_status;
108
109#ifdef CONFIG_SERIO
110 struct serio *serio;
111 int serio_open;
112#endif
113};
114
115#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
116#define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
117
118#define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
119#define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
120#define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
121#define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
122#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
123#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
124#define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
125#define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
126#define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
127
128/* Reading and writing Zilog8530 registers. The delays are to make this
129 * driver work on the Sun4 which needs a settling delay after each chip
130 * register access, other machines handle this in hardware via auxiliary
131 * flip-flops which implement the settle time we do in software.
132 *
133 * The port lock must be held and local IRQs must be disabled
134 * when {read,write}_zsreg is invoked.
135 */
136static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
137 unsigned char reg)
138{
139 unsigned char retval;
140
141 sbus_writeb(reg, &channel->control);
142 ZSDELAY();
143 retval = sbus_readb(&channel->control);
144 ZSDELAY();
145
146 return retval;
147}
148
149static void write_zsreg(struct zilog_channel __iomem *channel,
150 unsigned char reg, unsigned char value)
151{
152 sbus_writeb(reg, &channel->control);
153 ZSDELAY();
154 sbus_writeb(value, &channel->control);
155 ZSDELAY();
156}
157
158static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
159{
160 int i;
161
162 for (i = 0; i < 32; i++) {
163 unsigned char regval;
164
165 regval = sbus_readb(&channel->control);
166 ZSDELAY();
167 if (regval & Rx_CH_AV)
168 break;
169
170 regval = read_zsreg(channel, R1);
171 sbus_readb(&channel->data);
172 ZSDELAY();
173
174 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
175 sbus_writeb(ERR_RES, &channel->control);
176 ZSDELAY();
177 ZS_WSYNC(channel);
178 }
179 }
180}
181
182/* This function must only be called when the TX is not busy. The UART
183 * port lock must be held and local interrupts disabled.
184 */
185static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
186{
187 int i;
188
189 /* Let pending transmits finish. */
190 for (i = 0; i < 1000; i++) {
191 unsigned char stat = read_zsreg(channel, R1);
192 if (stat & ALL_SNT)
193 break;
194 udelay(100);
195 }
196
197 sbus_writeb(ERR_RES, &channel->control);
198 ZSDELAY();
199 ZS_WSYNC(channel);
200
201 sunzilog_clear_fifo(channel);
202
203 /* Disable all interrupts. */
204 write_zsreg(channel, R1,
205 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
206
207 /* Set parity, sync config, stop bits, and clock divisor. */
208 write_zsreg(channel, R4, regs[R4]);
209
210 /* Set misc. TX/RX control bits. */
211 write_zsreg(channel, R10, regs[R10]);
212
213 /* Set TX/RX controls sans the enable bits. */
214 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
215 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
216
217 /* Synchronous mode config. */
218 write_zsreg(channel, R6, regs[R6]);
219 write_zsreg(channel, R7, regs[R7]);
220
221 /* Don't mess with the interrupt vector (R2, unused by us) and
222 * master interrupt control (R9). We make sure this is setup
223 * properly at probe time then never touch it again.
224 */
225
226 /* Disable baud generator. */
227 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
228
229 /* Clock mode control. */
230 write_zsreg(channel, R11, regs[R11]);
231
232 /* Lower and upper byte of baud rate generator divisor. */
233 write_zsreg(channel, R12, regs[R12]);
234 write_zsreg(channel, R13, regs[R13]);
235
236 /* Now rewrite R14, with BRENAB (if set). */
237 write_zsreg(channel, R14, regs[R14]);
238
239 /* External status interrupt control. */
240 write_zsreg(channel, R15, regs[R15]);
241
242 /* Reset external status interrupts. */
243 write_zsreg(channel, R0, RES_EXT_INT);
244 write_zsreg(channel, R0, RES_EXT_INT);
245
246 /* Rewrite R3/R5, this time without enables masked. */
247 write_zsreg(channel, R3, regs[R3]);
248 write_zsreg(channel, R5, regs[R5]);
249
250 /* Rewrite R1, this time without IRQ enabled masked. */
251 write_zsreg(channel, R1, regs[R1]);
252}
253
254/* Reprogram the Zilog channel HW registers with the copies found in the
255 * software state struct. If the transmitter is busy, we defer this update
256 * until the next TX complete interrupt. Else, we do it right now.
257 *
258 * The UART port lock must be held and local interrupts disabled.
259 */
260static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
261 struct zilog_channel __iomem *channel)
262{
263 if (!ZS_REGS_HELD(up)) {
264 if (ZS_TX_ACTIVE(up)) {
265 up->flags |= SUNZILOG_FLAG_REGS_HELD;
266 } else {
267 __load_zsregs(channel, up->curregs);
268 }
269 }
270}
271
272static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
273{
274 unsigned int cur_cflag = up->cflag;
275 int brg, new_baud;
276
277 up->cflag &= ~CBAUD;
278 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
279
280 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
281 up->curregs[R12] = (brg & 0xff);
282 up->curregs[R13] = (brg >> 8) & 0xff;
283 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
284}
285
286static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
287 unsigned char ch, int is_break,
288 struct pt_regs *regs)
289{
290 if (ZS_IS_KEYB(up)) {
291 /* Stop-A is handled by drivers/char/keyboard.c now. */
292#ifdef CONFIG_SERIO
293 if (up->serio_open)
294 serio_interrupt(up->serio, ch, 0, regs);
295#endif
296 } else if (ZS_IS_MOUSE(up)) {
297 int ret = suncore_mouse_baud_detection(ch, is_break);
298
299 switch (ret) {
300 case 2:
301 sunzilog_change_mouse_baud(up);
302 /* fallthru */
303 case 1:
304 break;
305
306 case 0:
307#ifdef CONFIG_SERIO
308 if (up->serio_open)
309 serio_interrupt(up->serio, ch, 0, regs);
310#endif
311 break;
312 };
313 }
314}
315
316static struct tty_struct *
317sunzilog_receive_chars(struct uart_sunzilog_port *up,
318 struct zilog_channel __iomem *channel,
319 struct pt_regs *regs)
320{
321 struct tty_struct *tty;
33f0f88f 322 unsigned char ch, r1, flag;
1da177e4
LT		 323
324 tty = NULL;
325 if (up->port.info != NULL && /* Unopened serial console */
326 up->port.info->tty != NULL) /* Keyboard || mouse */
327 tty = up->port.info->tty;
328
329 for (;;) {
330
331 r1 = read_zsreg(channel, R1);
332 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
333 sbus_writeb(ERR_RES, &channel->control);
334 ZSDELAY();
335 ZS_WSYNC(channel);
336 }
337
338 ch = sbus_readb(&channel->control);
339 ZSDELAY();
340
341 /* This funny hack depends upon BRK_ABRT not interfering
342 * with the other bits we care about in R1.
343 */
344 if (ch & BRK_ABRT)
345 r1 |= BRK_ABRT;
346
347 if (!(ch & Rx_CH_AV))
348 break;
349
350 ch = sbus_readb(&channel->data);
351 ZSDELAY();
352
353 ch &= up->parity_mask;
354
355 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
356 sunzilog_kbdms_receive_chars(up, ch, 0, regs);
357 continue;
358 }
359
360 if (tty == NULL) {
361 uart_handle_sysrq_char(&up->port, ch, regs);
362 continue;
363 }
364
1da177e4 365 /* A real serial line, record the character and status. */
33f0f88f 366 flag = TTY_NORMAL;
1da177e4
LT		 367 up->port.icount.rx++;
368 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
369 if (r1 & BRK_ABRT) {
370 r1 &= ~(PAR_ERR | CRC_ERR);
371 up->port.icount.brk++;
372 if (uart_handle_break(&up->port))
373 continue;
374 }
375 else if (r1 & PAR_ERR)
376 up->port.icount.parity++;
377 else if (r1 & CRC_ERR)
378 up->port.icount.frame++;
379 if (r1 & Rx_OVR)
380 up->port.icount.overrun++;
381 r1 &= up->port.read_status_mask;
382 if (r1 & BRK_ABRT)
33f0f88f 383 flag = TTY_BREAK;
1da177e4 384 else if (r1 & PAR_ERR)
33f0f88f 385 flag = TTY_PARITY;
1da177e4 386 else if (r1 & CRC_ERR)
33f0f88f 387 flag = TTY_FRAME;
1da177e4
LT		 388 }
389 if (uart_handle_sysrq_char(&up->port, ch, regs))
390 continue;
391
392 if (up->port.ignore_status_mask == 0xff ||
393 (r1 & up->port.ignore_status_mask) == 0) {
33f0f88f 394 tty_insert_flip_char(tty, ch, flag);
1da177e4 395 }
33f0f88f
AC		 396 if (r1 & Rx_OVR)
397 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1da177e4
LT		 398 }
399
400 return tty;
401}
402
403static void sunzilog_status_handle(struct uart_sunzilog_port *up,
404 struct zilog_channel __iomem *channel,
405 struct pt_regs *regs)
406{
407 unsigned char status;
408
409 status = sbus_readb(&channel->control);
410 ZSDELAY();
411
412 sbus_writeb(RES_EXT_INT, &channel->control);
413 ZSDELAY();
414 ZS_WSYNC(channel);
415
416 if (status & BRK_ABRT) {
417 if (ZS_IS_MOUSE(up))
418 sunzilog_kbdms_receive_chars(up, 0, 1, regs);
419 if (ZS_IS_CONS(up)) {
420 /* Wait for BREAK to deassert to avoid potentially
421 * confusing the PROM.
422 */
423 while (1) {
424 status = sbus_readb(&channel->control);
425 ZSDELAY();
426 if (!(status & BRK_ABRT))
427 break;
428 }
429 sun_do_break();
430 return;
431 }
432 }
433
434 if (ZS_WANTS_MODEM_STATUS(up)) {
435 if (status & SYNC)
436 up->port.icount.dsr++;
437
438 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
439 * But it does not tell us which bit has changed, we have to keep
440 * track of this ourselves.
441 */
442 if ((status ^ up->prev_status) ^ DCD)
443 uart_handle_dcd_change(&up->port,
444 (status & DCD));
445 if ((status ^ up->prev_status) ^ CTS)
446 uart_handle_cts_change(&up->port,
447 (status & CTS));
448
449 wake_up_interruptible(&up->port.info->delta_msr_wait);
450 }
451
452 up->prev_status = status;
453}
454
455static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
456 struct zilog_channel __iomem *channel)
457{
458 struct circ_buf *xmit;
459
460 if (ZS_IS_CONS(up)) {
461 unsigned char status = sbus_readb(&channel->control);
462 ZSDELAY();
463
464 /* TX still busy? Just wait for the next TX done interrupt.
465 *
466 * It can occur because of how we do serial console writes. It would
467 * be nice to transmit console writes just like we normally would for
468 * a TTY line. (ie. buffered and TX interrupt driven). That is not
469 * easy because console writes cannot sleep. One solution might be
470 * to poll on enough port->xmit space becomming free. -DaveM
471 */
472 if (!(status & Tx_BUF_EMP))
473 return;
474 }
475
476 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
477
478 if (ZS_REGS_HELD(up)) {
479 __load_zsregs(channel, up->curregs);
480 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
481 }
482
483 if (ZS_TX_STOPPED(up)) {
484 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
485 goto ack_tx_int;
486 }
487
488 if (up->port.x_char) {
489 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
490 sbus_writeb(up->port.x_char, &channel->data);
491 ZSDELAY();
492 ZS_WSYNC(channel);
493
494 up->port.icount.tx++;
495 up->port.x_char = 0;
496 return;
497 }
498
499 if (up->port.info == NULL)
500 goto ack_tx_int;
501 xmit = &up->port.info->xmit;
b8df110f 502 if (uart_circ_empty(xmit))
1da177e4 503 goto ack_tx_int;
b8df110f 504
1da177e4
LT		 505 if (uart_tx_stopped(&up->port))
506 goto ack_tx_int;
507
508 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
509 sbus_writeb(xmit->buf[xmit->tail], &channel->data);
510 ZSDELAY();
511 ZS_WSYNC(channel);
512
513 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
514 up->port.icount.tx++;
515
516 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
517 uart_write_wakeup(&up->port);
518
519 return;
520
521ack_tx_int:
522 sbus_writeb(RES_Tx_P, &channel->control);
523 ZSDELAY();
524 ZS_WSYNC(channel);
525}
526
527static irqreturn_t sunzilog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
528{
529 struct uart_sunzilog_port *up = dev_id;
530
531 while (up) {
532 struct zilog_channel __iomem *channel
533 = ZILOG_CHANNEL_FROM_PORT(&up->port);
534 struct tty_struct *tty;
535 unsigned char r3;
536
537 spin_lock(&up->port.lock);
538 r3 = read_zsreg(channel, R3);
539
540 /* Channel A */
541 tty = NULL;
542 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
543 sbus_writeb(RES_H_IUS, &channel->control);
544 ZSDELAY();
545 ZS_WSYNC(channel);
546
547 if (r3 & CHARxIP)
548 tty = sunzilog_receive_chars(up, channel, regs);
549 if (r3 & CHAEXT)
550 sunzilog_status_handle(up, channel, regs);
551 if (r3 & CHATxIP)
552 sunzilog_transmit_chars(up, channel);
553 }
554 spin_unlock(&up->port.lock);
555
556 if (tty)
557 tty_flip_buffer_push(tty);
558
559 /* Channel B */
560 up = up->next;
561 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
562
563 spin_lock(&up->port.lock);
564 tty = NULL;
565 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
566 sbus_writeb(RES_H_IUS, &channel->control);
567 ZSDELAY();
568 ZS_WSYNC(channel);
569
570 if (r3 & CHBRxIP)
571 tty = sunzilog_receive_chars(up, channel, regs);
572 if (r3 & CHBEXT)
573 sunzilog_status_handle(up, channel, regs);
574 if (r3 & CHBTxIP)
575 sunzilog_transmit_chars(up, channel);
576 }
577 spin_unlock(&up->port.lock);
578
579 if (tty)
580 tty_flip_buffer_push(tty);
581
582 up = up->next;
583 }
584
585 return IRQ_HANDLED;
586}
587
588/* A convenient way to quickly get R0 status. The caller must _not_ hold the
589 * port lock, it is acquired here.
590 */
591static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
592{
593 struct zilog_channel __iomem *channel;
1da177e4
LT		 594 unsigned char status;
595
1da177e4
LT		 596 channel = ZILOG_CHANNEL_FROM_PORT(port);
597 status = sbus_readb(&channel->control);
598 ZSDELAY();
599
1da177e4
LT		 600 return status;
601}
602
603/* The port lock is not held. */
604static unsigned int sunzilog_tx_empty(struct uart_port *port)
605{
c5f4644e 606 unsigned long flags;
1da177e4
LT		 607 unsigned char status;
608 unsigned int ret;
609
c5f4644e
RK		 610 spin_lock_irqsave(&port->lock, flags);
611
1da177e4 612 status = sunzilog_read_channel_status(port);
c5f4644e
RK		 613
614 spin_unlock_irqrestore(&port->lock, flags);
615
1da177e4
LT		 616 if (status & Tx_BUF_EMP)
617 ret = TIOCSER_TEMT;
618 else
619 ret = 0;
620
621 return ret;
622}
623
c5f4644e 624/* The port lock is held and interrupts are disabled. */
1da177e4
LT		 625static unsigned int sunzilog_get_mctrl(struct uart_port *port)
626{
627 unsigned char status;
628 unsigned int ret;
629
630 status = sunzilog_read_channel_status(port);
631
632 ret = 0;
633 if (status & DCD)
634 ret |= TIOCM_CAR;
635 if (status & SYNC)
636 ret |= TIOCM_DSR;
637 if (status & CTS)
638 ret |= TIOCM_CTS;
639
640 return ret;
641}
642
643/* The port lock is held and interrupts are disabled. */
644static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
645{
646 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
647 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
648 unsigned char set_bits, clear_bits;
649
650 set_bits = clear_bits = 0;
651
652 if (mctrl & TIOCM_RTS)
653 set_bits |= RTS;
654 else
655 clear_bits |= RTS;
656 if (mctrl & TIOCM_DTR)
657 set_bits |= DTR;
658 else
659 clear_bits |= DTR;
660
661 /* NOTE: Not subject to 'transmitter active' rule. */
662 up->curregs[R5] |= set_bits;
663 up->curregs[R5] &= ~clear_bits;
664 write_zsreg(channel, R5, up->curregs[R5]);
665}
666
667/* The port lock is held and interrupts are disabled. */
b129a8cc 668static void sunzilog_stop_tx(struct uart_port *port)
1da177e4
LT		 669{
670 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
671
672 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
673}
674
675/* The port lock is held and interrupts are disabled. */
b129a8cc 676static void sunzilog_start_tx(struct uart_port *port)
1da177e4
LT		 677{
678 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
679 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
680 unsigned char status;
681
682 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
683 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
684
685 status = sbus_readb(&channel->control);
686 ZSDELAY();
687
688 /* TX busy? Just wait for the TX done interrupt. */
689 if (!(status & Tx_BUF_EMP))
690 return;
691
692 /* Send the first character to jump-start the TX done
693 * IRQ sending engine.
694 */
695 if (port->x_char) {
696 sbus_writeb(port->x_char, &channel->data);
697 ZSDELAY();
698 ZS_WSYNC(channel);
699
700 port->icount.tx++;
701 port->x_char = 0;
702 } else {
703 struct circ_buf *xmit = &port->info->xmit;
704
705 sbus_writeb(xmit->buf[xmit->tail], &channel->data);
706 ZSDELAY();
707 ZS_WSYNC(channel);
708
709 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
710 port->icount.tx++;
711
712 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
713 uart_write_wakeup(&up->port);
714 }
715}
716
717/* The port lock is held. */
718static void sunzilog_stop_rx(struct uart_port *port)
719{
720 struct uart_sunzilog_port *up = UART_ZILOG(port);
721 struct zilog_channel __iomem *channel;
722
723 if (ZS_IS_CONS(up))
724 return;
725
726 channel = ZILOG_CHANNEL_FROM_PORT(port);
727
728 /* Disable all RX interrupts. */
729 up->curregs[R1] &= ~RxINT_MASK;
730 sunzilog_maybe_update_regs(up, channel);
731}
732
733/* The port lock is held. */
734static void sunzilog_enable_ms(struct uart_port *port)
735{
736 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
737 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
738 unsigned char new_reg;
739
740 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
741 if (new_reg != up->curregs[R15]) {
742 up->curregs[R15] = new_reg;
743
744 /* NOTE: Not subject to 'transmitter active' rule. */
745 write_zsreg(channel, R15, up->curregs[R15]);
746 }
747}
748
749/* The port lock is not held. */
750static void sunzilog_break_ctl(struct uart_port *port, int break_state)
751{
752 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
753 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
754 unsigned char set_bits, clear_bits, new_reg;
755 unsigned long flags;
756
757 set_bits = clear_bits = 0;
758
759 if (break_state)
760 set_bits |= SND_BRK;
761 else
762 clear_bits |= SND_BRK;
763
764 spin_lock_irqsave(&port->lock, flags);
765
766 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
767 if (new_reg != up->curregs[R5]) {
768 up->curregs[R5] = new_reg;
769
770 /* NOTE: Not subject to 'transmitter active' rule. */
771 write_zsreg(channel, R5, up->curregs[R5]);
772 }
773
774 spin_unlock_irqrestore(&port->lock, flags);
775}
776
777static void __sunzilog_startup(struct uart_sunzilog_port *up)
778{
779 struct zilog_channel __iomem *channel;
780
781 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
782 up->prev_status = sbus_readb(&channel->control);
783
784 /* Enable receiver and transmitter. */
785 up->curregs[R3] |= RxENAB;
786 up->curregs[R5] |= TxENAB;
787
788 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
789 sunzilog_maybe_update_regs(up, channel);
790}
791
792static int sunzilog_startup(struct uart_port *port)
793{
794 struct uart_sunzilog_port *up = UART_ZILOG(port);
795 unsigned long flags;
796
797 if (ZS_IS_CONS(up))
798 return 0;
799
800 spin_lock_irqsave(&port->lock, flags);
801 __sunzilog_startup(up);
802 spin_unlock_irqrestore(&port->lock, flags);
803 return 0;
804}
805
806/*
807 * The test for ZS_IS_CONS is explained by the following e-mail:
808 *****
809 * From: Russell King <rmk@arm.linux.org.uk>
810 * Date: Sun, 8 Dec 2002 10:18:38 +0000
811 *
812 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
813 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
814 * > and I noticed that something is not right with reference
815 * > counting in this case. It seems that when the console
816 * > is open by kernel initially, this is not accounted
817 * > as an open, and uart_startup is not called.
818 *
819 * That is correct. We are unable to call uart_startup when the serial
820 * console is initialised because it may need to allocate memory (as
821 * request_irq does) and the memory allocators may not have been
822 * initialised.
823 *
824 * 1. initialise the port into a state where it can send characters in the
825 * console write method.
826 *
827 * 2. don't do the actual hardware shutdown in your shutdown() method (but
828 * do the normal software shutdown - ie, free irqs etc)
829 *****
830 */
831static void sunzilog_shutdown(struct uart_port *port)
832{
833 struct uart_sunzilog_port *up = UART_ZILOG(port);
834 struct zilog_channel __iomem *channel;
835 unsigned long flags;
836
837 if (ZS_IS_CONS(up))
838 return;
839
840 spin_lock_irqsave(&port->lock, flags);
841
842 channel = ZILOG_CHANNEL_FROM_PORT(port);
843
844 /* Disable receiver and transmitter. */
845 up->curregs[R3] &= ~RxENAB;
846 up->curregs[R5] &= ~TxENAB;
847
848 /* Disable all interrupts and BRK assertion. */
849 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
850 up->curregs[R5] &= ~SND_BRK;
851 sunzilog_maybe_update_regs(up, channel);
852
853 spin_unlock_irqrestore(&port->lock, flags);
854}
855
856/* Shared by TTY driver and serial console setup. The port lock is held
857 * and local interrupts are disabled.
858 */
859static void
860sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
861 unsigned int iflag, int brg)
862{
863
864 up->curregs[R10] = NRZ;
865 up->curregs[R11] = TCBR | RCBR;
866
867 /* Program BAUD and clock source. */
868 up->curregs[R4] &= ~XCLK_MASK;
869 up->curregs[R4] |= X16CLK;
870 up->curregs[R12] = brg & 0xff;
871 up->curregs[R13] = (brg >> 8) & 0xff;
872 up->curregs[R14] = BRSRC | BRENAB;
873
874 /* Character size, stop bits, and parity. */
875 up->curregs[3] &= ~RxN_MASK;
876 up->curregs[5] &= ~TxN_MASK;
877 switch (cflag & CSIZE) {
878 case CS5:
879 up->curregs[3] |= Rx5;
880 up->curregs[5] |= Tx5;
881 up->parity_mask = 0x1f;
882 break;
883 case CS6:
884 up->curregs[3] |= Rx6;
885 up->curregs[5] |= Tx6;
886 up->parity_mask = 0x3f;
887 break;
888 case CS7:
889 up->curregs[3] |= Rx7;
890 up->curregs[5] |= Tx7;
891 up->parity_mask = 0x7f;
892 break;
893 case CS8:
894 default:
895 up->curregs[3] |= Rx8;
896 up->curregs[5] |= Tx8;
897 up->parity_mask = 0xff;
898 break;
899 };
900 up->curregs[4] &= ~0x0c;
901 if (cflag & CSTOPB)
902 up->curregs[4] |= SB2;
903 else
904 up->curregs[4] |= SB1;
905 if (cflag & PARENB)
906 up->curregs[4] |= PAR_ENAB;
907 else
908 up->curregs[4] &= ~PAR_ENAB;
909 if (!(cflag & PARODD))
910 up->curregs[4] |= PAR_EVEN;
911 else
912 up->curregs[4] &= ~PAR_EVEN;
913
914 up->port.read_status_mask = Rx_OVR;
915 if (iflag & INPCK)
916 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
917 if (iflag & (BRKINT | PARMRK))
918 up->port.read_status_mask |= BRK_ABRT;
919
920 up->port.ignore_status_mask = 0;
921 if (iflag & IGNPAR)
922 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
923 if (iflag & IGNBRK) {
924 up->port.ignore_status_mask |= BRK_ABRT;
925 if (iflag & IGNPAR)
926 up->port.ignore_status_mask |= Rx_OVR;
927 }
928
929 if ((cflag & CREAD) == 0)
930 up->port.ignore_status_mask = 0xff;
931}
932
933/* The port lock is not held. */
934static void
935sunzilog_set_termios(struct uart_port *port, struct termios *termios,
936 struct termios *old)
937{
938 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
939 unsigned long flags;
940 int baud, brg;
941
942 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
943
944 spin_lock_irqsave(&up->port.lock, flags);
945
946 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
947
948 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
949
950 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
951 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
952 else
953 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
954
955 up->cflag = termios->c_cflag;
956
957 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
958
959 uart_update_timeout(port, termios->c_cflag, baud);
960
961 spin_unlock_irqrestore(&up->port.lock, flags);
962}
963
964static const char *sunzilog_type(struct uart_port *port)
965{
966 return "SunZilog";
967}
968
969/* We do not request/release mappings of the registers here, this
970 * happens at early serial probe time.
971 */
972static void sunzilog_release_port(struct uart_port *port)
973{
974}
975
976static int sunzilog_request_port(struct uart_port *port)
977{
978 return 0;
979}
980
981/* These do not need to do anything interesting either. */
982static void sunzilog_config_port(struct uart_port *port, int flags)
983{
984}
985
986/* We do not support letting the user mess with the divisor, IRQ, etc. */
987static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
988{
989 return -EINVAL;
990}
991
992static struct uart_ops sunzilog_pops = {
993 .tx_empty = sunzilog_tx_empty,
994 .set_mctrl = sunzilog_set_mctrl,
995 .get_mctrl = sunzilog_get_mctrl,
996 .stop_tx = sunzilog_stop_tx,
997 .start_tx = sunzilog_start_tx,
998 .stop_rx = sunzilog_stop_rx,
999 .enable_ms = sunzilog_enable_ms,
1000 .break_ctl = sunzilog_break_ctl,
1001 .startup = sunzilog_startup,
1002 .shutdown = sunzilog_shutdown,
1003 .set_termios = sunzilog_set_termios,
1004 .type = sunzilog_type,
1005 .release_port = sunzilog_release_port,
1006 .request_port = sunzilog_request_port,
1007 .config_port = sunzilog_config_port,
1008 .verify_port = sunzilog_verify_port,
1009};
1010
1011static struct uart_sunzilog_port *sunzilog_port_table;
1012static struct zilog_layout __iomem **sunzilog_chip_regs;
1013
1014static struct uart_sunzilog_port *sunzilog_irq_chain;
1015static int zilog_irq = -1;
1016
1017static struct uart_driver sunzilog_reg = {
1018 .owner = THIS_MODULE,
1019 .driver_name = "ttyS",
1da177e4
LT		 1020 .dev_name = "ttyS",
1021 .major = TTY_MAJOR,
1022};
1023
1024static void * __init alloc_one_table(unsigned long size)
1025{
1026 void *ret;
1027
1028 ret = kmalloc(size, GFP_KERNEL);
1029 if (ret != NULL)
1030 memset(ret, 0, size);
1031
1032 return ret;
1033}
1034
1035static void __init sunzilog_alloc_tables(void)
1036{
1037 sunzilog_port_table =
1038 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_sunzilog_port));
1039 sunzilog_chip_regs =
1040 alloc_one_table(NUM_SUNZILOG * sizeof(struct zilog_layout __iomem *));
1041
1042 if (sunzilog_port_table == NULL || sunzilog_chip_regs == NULL) {
1043 prom_printf("SunZilog: Cannot allocate tables.\n");
1044 prom_halt();
1045 }
1046}
1047
1048#ifdef CONFIG_SPARC64
1049
1050/* We used to attempt to use the address property of the Zilog device node
1051 * but that totally is not necessary on sparc64.
1052 */
1053static struct zilog_layout __iomem * __init get_zs_sun4u(int chip, int zsnode)
1054{
37616578 1055 void __iomem *mapped_addr;
1da177e4
LT		 1056 unsigned int sun4u_ino;
1057 struct sbus_bus *sbus = NULL;
1058 struct sbus_dev *sdev = NULL;
1059 int err;
1060
1061 if (central_bus == NULL) {
1062 for_each_sbus(sbus) {
1063 for_each_sbusdev(sdev, sbus) {
1064 if (sdev->prom_node == zsnode)
1065 goto found;
1066 }
1067 }
1068 }
1069 found:
1070 if (sdev == NULL && central_bus == NULL) {
1071 prom_printf("SunZilog: sdev&&central == NULL for "
1072 "Zilog %d in get_zs_sun4u.\n", chip);
1073 prom_halt();
1074 }
1075 if (central_bus == NULL) {
1076 mapped_addr =
1077 sbus_ioremap(&sdev->resource[0], 0,
1078 PAGE_SIZE,
1079 "Zilog Registers");
1080 } else {
1081 struct linux_prom_registers zsregs[1];
1082
1083 err = prom_getproperty(zsnode, "reg",
1084 (char *) &zsregs[0],
1085 sizeof(zsregs));
1086 if (err == -1) {
1087 prom_printf("SunZilog: Cannot map "
1088 "Zilog %d regs on "
1089 "central bus.\n", chip);
1090 prom_halt();
1091 }
1092 apply_fhc_ranges(central_bus->child,
1093 &zsregs[0], 1);
1094 apply_central_ranges(central_bus, &zsregs[0], 1);
37616578
WLII		 1095 mapped_addr = (void __iomem *)
1096 ((((u64)zsregs[0].which_io)<<32UL) |
1097 ((u64)zsregs[0].phys_addr));
1da177e4
LT		 1098 }
1099
1100 if (zilog_irq == -1) {
1101 if (central_bus) {
1102 unsigned long iclr, imap;
1103
1104 iclr = central_bus->child->fhc_regs.uregs
1105 + FHC_UREGS_ICLR;
1106 imap = central_bus->child->fhc_regs.uregs
1107 + FHC_UREGS_IMAP;
cecc4e92 1108 zilog_irq = build_irq(0, iclr, imap);
1da177e4
LT		 1109 } else {
1110 err = prom_getproperty(zsnode, "interrupts",
1111 (char *) &sun4u_ino,
1112 sizeof(sun4u_ino));
1113 zilog_irq = sbus_build_irq(sbus_root, sun4u_ino);
1114 }
1115 }
1116
1117 return (struct zilog_layout __iomem *) mapped_addr;
1118}
1119#else /* CONFIG_SPARC64 */
1120
1121/*
1122 * XXX The sun4d case is utterly screwed: it tries to re-walk the tree
1123 * (for the 3rd time) in order to find bootbus and cpu. Streamline it.
1124 */
1125static struct zilog_layout __iomem * __init get_zs_sun4cmd(int chip, int node)
1126{
1127 struct linux_prom_irqs irq_info[2];
1128 void __iomem *mapped_addr = NULL;
1129 int zsnode, cpunode, bbnode;
1130 struct linux_prom_registers zsreg[4];
1131 struct resource res;
1132
1133 if (sparc_cpu_model == sun4d) {
1134 int walk;
1135
1136 zsnode = 0;
1137 bbnode = 0;
1138 cpunode = 0;
1139 for (walk = prom_getchild(prom_root_node);
1140 (walk = prom_searchsiblings(walk, "cpu-unit")) != 0;
1141 walk = prom_getsibling(walk)) {
1142 bbnode = prom_getchild(walk);
1143 if (bbnode &&
1144 (bbnode = prom_searchsiblings(bbnode, "bootbus"))) {
1145 if ((zsnode = prom_getchild(bbnode)) == node) {
1146 cpunode = walk;
1147 break;
1148 }
1149 }
1150 }
1151 if (!walk) {
1152 prom_printf("SunZilog: Cannot find the %d'th bootbus on sun4d.\n",
1153 (chip / 2));
1154 prom_halt();
1155 }
1156
1157 if (prom_getproperty(zsnode, "reg",
1158 (char *) zsreg, sizeof(zsreg)) == -1) {
1159 prom_printf("SunZilog: Cannot map Zilog %d\n", chip);
1160 prom_halt();
1161 }
1162 /* XXX Looks like an off by one? */
1163 prom_apply_generic_ranges(bbnode, cpunode, zsreg, 1);
1164 res.start = zsreg[0].phys_addr;
1165 res.end = res.start + (8 - 1);
1166 res.flags = zsreg[0].which_io | IORESOURCE_IO;
1167 mapped_addr = sbus_ioremap(&res, 0, 8, "Zilog Serial");
1168
1169 } else {
1170 zsnode = node;
1171
1172#if 0 /* XXX When was this used? */
1173 if (prom_getintdefault(zsnode, "slave", -1) != chipid) {
1174 zsnode = prom_getsibling(zsnode);
1175 continue;
1176 }
1177#endif
1178
1179 /*
1180 * "address" is only present on ports that OBP opened
1181 * (from Mitch Bradley's "Hitchhiker's Guide to OBP").
1182 * We do not use it.
1183 */
1184
1185 if (prom_getproperty(zsnode, "reg",
1186 (char *) zsreg, sizeof(zsreg)) == -1) {
1187 prom_printf("SunZilog: Cannot map Zilog %d\n", chip);
1188 prom_halt();
1189 }
1190 if (sparc_cpu_model == sun4m) /* Crude. Pass parent. XXX */
1191 prom_apply_obio_ranges(zsreg, 1);
1192 res.start = zsreg[0].phys_addr;
1193 res.end = res.start + (8 - 1);
1194 res.flags = zsreg[0].which_io | IORESOURCE_IO;
1195 mapped_addr = sbus_ioremap(&res, 0, 8, "Zilog Serial");
1196 }
1197
1198 if (prom_getproperty(zsnode, "intr",
1199 (char *) irq_info, sizeof(irq_info))
1200 % sizeof(struct linux_prom_irqs)) {
1201 prom_printf("SunZilog: Cannot get IRQ property for Zilog %d.\n",
1202 chip);
1203 prom_halt();
1204 }
1205 if (zilog_irq == -1) {
1206 zilog_irq = irq_info[0].pri;
1207 } else if (zilog_irq != irq_info[0].pri) {
1208 /* XXX. Dumb. Should handle per-chip IRQ, for add-ons. */
1209 prom_printf("SunZilog: Inconsistent IRQ layout for Zilog %d.\n",
1210 chip);
1211 prom_halt();
1212 }
1213
1214 return (struct zilog_layout __iomem *) mapped_addr;
1215}
1216#endif /* !(CONFIG_SPARC64) */
1217
1218/* Get the address of the registers for SunZilog instance CHIP. */
1219static struct zilog_layout __iomem * __init get_zs(int chip, int node)
1220{
1221 if (chip < 0 || chip >= NUM_SUNZILOG) {
1222 prom_printf("SunZilog: Illegal chip number %d in get_zs.\n", chip);
1223 prom_halt();
1224 }
1225
1226#ifdef CONFIG_SPARC64
1227 return get_zs_sun4u(chip, node);
1228#else
1229
1230 if (sparc_cpu_model == sun4) {
1231 struct resource res;
1232
1233 /* Not probe-able, hard code it. */
1234 switch (chip) {
1235 case 0:
1236 res.start = 0xf1000000;
1237 break;
1238 case 1:
1239 res.start = 0xf0000000;
1240 break;
1241 };
1242 zilog_irq = 12;
1243 res.end = (res.start + (8 - 1));
1244 res.flags = IORESOURCE_IO;
1245 return sbus_ioremap(&res, 0, 8, "SunZilog");
1246 }
1247
1248 return get_zs_sun4cmd(chip, node);
1249#endif
1250}
1251
1252#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1253
d358788f 1254static void sunzilog_putchar(struct uart_port *port, int ch)
1da177e4 1255{
d358788f 1256 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
1da177e4
LT		 1257 int loops = ZS_PUT_CHAR_MAX_DELAY;
1258
1259 /* This is a timed polling loop so do not switch the explicit
1260 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1261 */
1262 do {
1263 unsigned char val = sbus_readb(&channel->control);
1264 if (val & Tx_BUF_EMP) {
1265 ZSDELAY();
1266 break;
1267 }
1268 udelay(5);
1269 } while (--loops);
1270
1271 sbus_writeb(ch, &channel->data);
1272 ZSDELAY();
1273 ZS_WSYNC(channel);
1274}
1275
1276#ifdef CONFIG_SERIO
1277
1278static DEFINE_SPINLOCK(sunzilog_serio_lock);
1279
1280static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1281{
1282 struct uart_sunzilog_port *up = serio->port_data;
1283 unsigned long flags;
1284
1285 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1286
d358788f 1287 sunzilog_putchar(&up->port, ch);
1da177e4
LT		 1288
1289 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1290
1291 return 0;
1292}
1293
1294static int sunzilog_serio_open(struct serio *serio)
1295{
1296 struct uart_sunzilog_port *up = serio->port_data;
1297 unsigned long flags;
1298 int ret;
1299
1300 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1301 if (!up->serio_open) {
1302 up->serio_open = 1;
1303 ret = 0;
1304 } else
1305 ret = -EBUSY;
1306 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1307
1308 return ret;
1309}
1310
1311static void sunzilog_serio_close(struct serio *serio)
1312{
1313 struct uart_sunzilog_port *up = serio->port_data;
1314 unsigned long flags;
1315
1316 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1317 up->serio_open = 0;
1318 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1319}
1320
1321#endif /* CONFIG_SERIO */
1322
1323#ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1324static void
1325sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1326{
1327 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1da177e4 1328 unsigned long flags;
1da177e4
LT		 1329
1330 spin_lock_irqsave(&up->port.lock, flags);
d358788f 1331 uart_console_write(&up->port, s, count, sunzilog_putchar);
1da177e4
LT		 1332 udelay(2);
1333 spin_unlock_irqrestore(&up->port.lock, flags);
1334}
1335
1336static int __init sunzilog_console_setup(struct console *con, char *options)
1337{
1338 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1339 unsigned long flags;
1340 int baud, brg;
1341
1342 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1343 (sunzilog_reg.minor - 64) + con->index, con->index);
1344
1345 /* Get firmware console settings. */
1346 sunserial_console_termios(con);
1347
1348 /* Firmware console speed is limited to 150-->38400 baud so
1349 * this hackish cflag thing is OK.
1350 */
1351 switch (con->cflag & CBAUD) {
1352 case B150: baud = 150; break;
1353 case B300: baud = 300; break;
1354 case B600: baud = 600; break;
1355 case B1200: baud = 1200; break;
1356 case B2400: baud = 2400; break;
1357 case B4800: baud = 4800; break;
1358 default: case B9600: baud = 9600; break;
1359 case B19200: baud = 19200; break;
1360 case B38400: baud = 38400; break;
1361 };
1362
1363 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1364
1365 spin_lock_irqsave(&up->port.lock, flags);
1366
1367 up->curregs[R15] = BRKIE;
1368 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1369
1370 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1371 __sunzilog_startup(up);
1372
1373 spin_unlock_irqrestore(&up->port.lock, flags);
1374
1375 return 0;
1376}
1377
1378static struct console sunzilog_console = {
1379 .name = "ttyS",
1380 .write = sunzilog_console_write,
1381 .device = uart_console_device,
1382 .setup = sunzilog_console_setup,
1383 .flags = CON_PRINTBUFFER,
1384 .index = -1,
1385 .data = &sunzilog_reg,
1386};
1da177e4
LT		 1387
1388static int __init sunzilog_console_init(void)
1389{
1390 int i;
1391
1392 if (con_is_present())
1393 return 0;
1394
1395 for (i = 0; i < NUM_CHANNELS; i++) {
1396 int this_minor = sunzilog_reg.minor + i;
1397
1398 if ((this_minor - 64) == (serial_console - 1))
1399 break;
1400 }
1401 if (i == NUM_CHANNELS)
1402 return 0;
1403
1404 sunzilog_console.index = i;
1405 sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1406 register_console(&sunzilog_console);
1407 return 0;
1408}
1ddb7c98
DM		 1409
1410static inline struct console *SUNZILOG_CONSOLE(void)
1411{
1412 int i;
1413
1414 if (con_is_present())
1415 return NULL;
1416
1417 for (i = 0; i < NUM_CHANNELS; i++) {
1418 int this_minor = sunzilog_reg.minor + i;
1419
1420 if ((this_minor - 64) == (serial_console - 1))
1421 break;
1422 }
1423 if (i == NUM_CHANNELS)
1424 return NULL;
1425
1426 sunzilog_console.index = i;
1427 sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1428
1429 return &sunzilog_console;
1430}
1431
1da177e4 1432#else
1ddb7c98 1433#define SUNZILOG_CONSOLE() (NULL)
1da177e4
LT		 1434#define sunzilog_console_init() do { } while (0)
1435#endif
1436
1437/*
1438 * We scan the PROM tree recursively. This is the most reliable way
1439 * to find Zilog nodes on various platforms. However, we face an extreme
1440 * shortage of kernel stack, so we must be very careful. To that end,
1441 * we scan only to a certain depth, and we use a common property buffer
1442 * in the scan structure.
1443 */
1444#define ZS_PROPSIZE 128
1445#define ZS_SCAN_DEPTH 5
1446
1447struct zs_probe_scan {
1448 int depth;
1449 void (*scanner)(struct zs_probe_scan *t, int node);
1450
1451 int devices;
1452 char prop[ZS_PROPSIZE];
1453};
1454
1455static int __inline__ sunzilog_node_ok(int node, const char *name, int len)
1456{
1457 if (strncmp(name, "zs", len) == 0)
1458 return 1;
1459 /* Don't fold this procedure just yet. Compare to su_node_ok(). */
1460 return 0;
1461}
1462
1463static void __init sunzilog_scan(struct zs_probe_scan *t, int node)
1464{
1465 int len;
1466
1467 for (; node != 0; node = prom_getsibling(node)) {
1468 len = prom_getproperty(node, "name", t->prop, ZS_PROPSIZE);
1469 if (len <= 1)
1470 continue; /* Broken PROM node */
1471 if (sunzilog_node_ok(node, t->prop, len)) {
1472 (*t->scanner)(t, node);
1473 } else {
1474 if (t->depth < ZS_SCAN_DEPTH) {
1475 t->depth++;
1476 sunzilog_scan(t, prom_getchild(node));
1477 --t->depth;
1478 }
1479 }
1480 }
1481}
1482
1483static void __init sunzilog_prepare(void)
1484{
1485 struct uart_sunzilog_port *up;
1486 struct zilog_layout __iomem *rp;
1487 int channel, chip;
1488
1489 /*
1490 * Temporary fix.
1491 */
1492 for (channel = 0; channel < NUM_CHANNELS; channel++)
1493 spin_lock_init(&sunzilog_port_table[channel].port.lock);
1494
1495 sunzilog_irq_chain = up = &sunzilog_port_table[0];
1496 for (channel = 0; channel < NUM_CHANNELS - 1; channel++)
1497 up[channel].next = &up[channel + 1];
1498 up[channel].next = NULL;
1499
1500 for (chip = 0; chip < NUM_SUNZILOG; chip++) {
1501 rp = sunzilog_chip_regs[chip];
1502 up[(chip * 2) + 0].port.membase = (void __iomem *)&rp->channelA;
1503 up[(chip * 2) + 1].port.membase = (void __iomem *)&rp->channelB;
1504
1505 /* Channel A */
9b4a1617 1506 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1da177e4
LT		 1507 up[(chip * 2) + 0].port.irq = zilog_irq;
1508 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1509 up[(chip * 2) + 0].port.fifosize = 1;
1510 up[(chip * 2) + 0].port.ops = &sunzilog_pops;
1511 up[(chip * 2) + 0].port.type = PORT_SUNZILOG;
1512 up[(chip * 2) + 0].port.flags = 0;
1513 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1514 up[(chip * 2) + 0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1515
1516 /* Channel B */
9b4a1617 1517 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1da177e4
LT		 1518 up[(chip * 2) + 1].port.irq = zilog_irq;
1519 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1520 up[(chip * 2) + 1].port.fifosize = 1;
1521 up[(chip * 2) + 1].port.ops = &sunzilog_pops;
1522 up[(chip * 2) + 1].port.type = PORT_SUNZILOG;
1523 up[(chip * 2) + 1].port.flags = 0;
1524 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1525 up[(chip * 2) + 1].flags |= 0;
1526 }
1527}
1528
1529static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
1530{
1531 int baud, brg;
1532
1533 if (channel == KEYBOARD_LINE) {
1534 up->flags |= SUNZILOG_FLAG_CONS_KEYB;
1535 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1536 baud = 1200;
1537 } else {
1538 up->flags |= SUNZILOG_FLAG_CONS_MOUSE;
1539 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1540 baud = 4800;
1541 }
c6387a48
DM		 1542 printk(KERN_INFO "zs%d at 0x%p (irq = %d) is a SunZilog\n",
1543 channel, up->port.membase, zilog_irq);
1da177e4
LT		 1544
1545 up->curregs[R15] = BRKIE;
1546 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1547 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1548 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1549 __sunzilog_startup(up);
1550}
1551
1552#ifdef CONFIG_SERIO
1553static void __init sunzilog_register_serio(struct uart_sunzilog_port *up, int channel)
1554{
1555 struct serio *serio;
1556
1557 up->serio = serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
1558 if (serio) {
1559 memset(serio, 0, sizeof(*serio));
1560
1561 serio->port_data = up;
1562
1563 serio->id.type = SERIO_RS232;
1564 if (channel == KEYBOARD_LINE) {
1565 serio->id.proto = SERIO_SUNKBD;
1566 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1567 } else {
1568 serio->id.proto = SERIO_SUN;
1569 serio->id.extra = 1;
1570 strlcpy(serio->name, "zsms", sizeof(serio->name));
1571 }
1572 strlcpy(serio->phys,
1573 (channel == KEYBOARD_LINE ? "zs/serio0" : "zs/serio1"),
1574 sizeof(serio->phys));
1575
1576 serio->write = sunzilog_serio_write;
1577 serio->open = sunzilog_serio_open;
1578 serio->close = sunzilog_serio_close;
1579
1580 serio_register_port(serio);
1581 } else {
1582 printk(KERN_WARNING "zs%d: not enough memory for serio port\n",
1583 channel);
1584 }
1585}
1586#endif
1587
1588static void __init sunzilog_init_hw(void)
1589{
1590 int i;
1591
1592 for (i = 0; i < NUM_CHANNELS; i++) {
1593 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1594 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1595 unsigned long flags;
1596 int baud, brg;
1597
1598 spin_lock_irqsave(&up->port.lock, flags);
1599
1600 if (ZS_IS_CHANNEL_A(up)) {
1601 write_zsreg(channel, R9, FHWRES);
1602 ZSDELAY_LONG();
1603 (void) read_zsreg(channel, R0);
1604 }
1605
1606 if (i == KEYBOARD_LINE || i == MOUSE_LINE) {
1607 sunzilog_init_kbdms(up, i);
1608 up->curregs[R9] |= (NV | MIE);
1609 write_zsreg(channel, R9, up->curregs[R9]);
1610 } else {
1611 /* Normal serial TTY. */
1612 up->parity_mask = 0xff;
1613 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1614 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1615 up->curregs[R3] = RxENAB | Rx8;
1616 up->curregs[R5] = TxENAB | Tx8;
1617 up->curregs[R9] = NV | MIE;
1618 up->curregs[R10] = NRZ;
1619 up->curregs[R11] = TCBR | RCBR;
1620 baud = 9600;
1621 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1622 up->curregs[R12] = (brg & 0xff);
1623 up->curregs[R13] = (brg >> 8) & 0xff;
1624 up->curregs[R14] = BRSRC | BRENAB;
1625 __load_zsregs(channel, up->curregs);
1626 write_zsreg(channel, R9, up->curregs[R9]);
1627 }
1628
1629 spin_unlock_irqrestore(&up->port.lock, flags);
1630
1631#ifdef CONFIG_SERIO
1632 if (i == KEYBOARD_LINE || i == MOUSE_LINE)
1633 sunzilog_register_serio(up, i);
1634#endif
1635 }
1636}
1637
1638static struct zilog_layout __iomem * __init get_zs(int chip, int node);
1639
1640static void __init sunzilog_scan_probe(struct zs_probe_scan *t, int node)
1641{
1642 sunzilog_chip_regs[t->devices] = get_zs(t->devices, node);
1643 t->devices++;
1644}
1645
1646static int __init sunzilog_ports_init(void)
1647{
1648 struct zs_probe_scan scan;
1649 int ret;
1650 int uart_count;
1651 int i;
1652
1653 printk(KERN_DEBUG "SunZilog: %d chips.\n", NUM_SUNZILOG);
1654
1655 scan.scanner = sunzilog_scan_probe;
1656 scan.depth = 0;
1657 scan.devices = 0;
1658 sunzilog_scan(&scan, prom_getchild(prom_root_node));
1659
1660 sunzilog_prepare();
1661
1662 if (request_irq(zilog_irq, sunzilog_interrupt, SA_SHIRQ,
1663 "SunZilog", sunzilog_irq_chain)) {
1664 prom_printf("SunZilog: Unable to register zs interrupt handler.\n");
1665 prom_halt();
1666 }
1667
1668 sunzilog_init_hw();
1669
1670 /* We can only init this once we have probed the Zilogs
1671 * in the system. Do not count channels assigned to keyboards
1672 * or mice when we are deciding how many ports to register.
1673 */
1674 uart_count = 0;
1675 for (i = 0; i < NUM_CHANNELS; i++) {
1676 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1677
1678 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1679 continue;
1680
1681 uart_count++;
1682 }
1683
1684 sunzilog_reg.nr = uart_count;
1da177e4 1685 sunzilog_reg.minor = sunserial_current_minor;
1da177e4
LT		 1686
1687 ret = uart_register_driver(&sunzilog_reg);
1688 if (ret == 0) {
f5deb807 1689 sunzilog_reg.tty_driver->name_base = sunzilog_reg.minor - 64;
1ddb7c98
DM		 1690 sunzilog_reg.cons = SUNZILOG_CONSOLE();
1691
1692 sunserial_current_minor += uart_count;
1693
1da177e4
LT		 1694 for (i = 0; i < NUM_CHANNELS; i++) {
1695 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1696
1697 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1698 continue;
1699
1700 if (uart_add_one_port(&sunzilog_reg, &up->port)) {
1701 printk(KERN_ERR
1702 "SunZilog: failed to add port zs%d\n", i);
1703 }
1704 }
1705 }
1706
1707 return ret;
1708}
1709
1710static void __init sunzilog_scan_count(struct zs_probe_scan *t, int node)
1711{
1712 t->devices++;
1713}
1714
1715static int __init sunzilog_ports_count(void)
1716{
1717 struct zs_probe_scan scan;
1718
1719 /* Sun4 Zilog setup is hard coded, no probing to do. */
1720 if (sparc_cpu_model == sun4)
1721 return 2;
1722
1723 scan.scanner = sunzilog_scan_count;
1724 scan.depth = 0;
1725 scan.devices = 0;
1726
1727 sunzilog_scan(&scan, prom_getchild(prom_root_node));
1728
1729 return scan.devices;
1730}
1731
1732static int __init sunzilog_init(void)
1733{
1734
1735 NUM_SUNZILOG = sunzilog_ports_count();
1736 if (NUM_SUNZILOG == 0)
1737 return -ENODEV;
1738
1739 sunzilog_alloc_tables();
1740
1741 sunzilog_ports_init();
1742
1743 return 0;
1744}
1745
1746static void __exit sunzilog_exit(void)
1747{
1748 int i;
1749
1750 for (i = 0; i < NUM_CHANNELS; i++) {
1751 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1752
1753 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1754#ifdef CONFIG_SERIO
1755 if (up->serio) {
1756 serio_unregister_port(up->serio);
1757 up->serio = NULL;
1758 }
1759#endif
1760 } else
1761 uart_remove_one_port(&sunzilog_reg, &up->port);
1762 }
1763
1764 uart_unregister_driver(&sunzilog_reg);
1765}
1766
1767module_init(sunzilog_init);
1768module_exit(sunzilog_exit);
1769
1770MODULE_AUTHOR("David S. Miller");
1771MODULE_DESCRIPTION("Sun Zilog serial port driver");
1772MODULE_LICENSE("GPL");
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