[mirror_ubuntu-artful-kernel.git] / drivers / sh / intc / core.c

/*
 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
 *
 * Copyright (C) 2007, 2008 Magnus Damm
 * Copyright (C) 2009, 2010 Paul Mundt
 *
 * Based on intc2.c and ipr.c
 *
 * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
 * Copyright (C) 2000  Kazumoto Kojima
 * Copyright (C) 2001  David J. Mckay (david.mckay@st.com)
 * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
 * Copyright (C) 2005, 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#define pr_fmt(fmt) "intc: " fmt

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/sh_intc.h>
#include <linux/sysdev.h>
#include <linux/syscore_ops.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/radix-tree.h>
#include "internals.h"

LIST_HEAD(intc_list);
DEFINE_RAW_SPINLOCK(intc_big_lock);
unsigned int nr_intc_controllers;

/*
 * Default priority level
 * - this needs to be at least 2 for 5-bit priorities on 7780
 */
static unsigned int default_prio_level = 2;	/* 2 - 16 */
static unsigned int intc_prio_level[NR_IRQS];	/* for now */

unsigned int intc_get_dfl_prio_level(void)
{
	return default_prio_level;
}

unsigned int intc_get_prio_level(unsigned int irq)
{
	return intc_prio_level[irq];
}

void intc_set_prio_level(unsigned int irq, unsigned int level)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&intc_big_lock, flags);
	intc_prio_level[irq] = level;
	raw_spin_unlock_irqrestore(&intc_big_lock, flags);
}

static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
{
	generic_handle_irq((unsigned int)get_irq_data(irq));
}

static void __init intc_register_irq(struct intc_desc *desc,
				     struct intc_desc_int *d,
				     intc_enum enum_id,
				     unsigned int irq)
{
	struct intc_handle_int *hp;
	struct irq_data *irq_data;
	unsigned int data[2], primary;
	unsigned long flags;

	/*
	 * Register the IRQ position with the global IRQ map, then insert
	 * it in to the radix tree.
	 */
	irq_reserve_irq(irq);

	raw_spin_lock_irqsave(&intc_big_lock, flags);
	radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
	raw_spin_unlock_irqrestore(&intc_big_lock, flags);

	/*
	 * Prefer single interrupt source bitmap over other combinations:
	 *
	 * 1. bitmap, single interrupt source
	 * 2. priority, single interrupt source
	 * 3. bitmap, multiple interrupt sources (groups)
	 * 4. priority, multiple interrupt sources (groups)
	 */
	data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
	data[1] = intc_get_prio_handle(desc, d, enum_id, 0);

	primary = 0;
	if (!data[0] && data[1])
		primary = 1;

	if (!data[0] && !data[1])
		pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
			   irq, irq2evt(irq));

	data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
	data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);

	if (!data[primary])
		primary ^= 1;

	BUG_ON(!data[primary]); /* must have primary masking method */

	irq_data = irq_get_irq_data(irq);

	disable_irq_nosync(irq);
	set_irq_chip_and_handler_name(irq, &d->chip,
				      handle_level_irq, "level");
	set_irq_chip_data(irq, (void *)data[primary]);

	/*
	 * set priority level
	 */
	intc_set_prio_level(irq, intc_get_dfl_prio_level());

	/* enable secondary masking method if present */
	if (data[!primary])
		_intc_enable(irq_data, data[!primary]);

	/* add irq to d->prio list if priority is available */
	if (data[1]) {
		hp = d->prio + d->nr_prio;
		hp->irq = irq;
		hp->handle = data[1];

		if (primary) {
			/*
			 * only secondary priority should access registers, so
			 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
			 */
			hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
			hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
		}
		d->nr_prio++;
	}

	/* add irq to d->sense list if sense is available */
	data[0] = intc_get_sense_handle(desc, d, enum_id);
	if (data[0]) {
		(d->sense + d->nr_sense)->irq = irq;
		(d->sense + d->nr_sense)->handle = data[0];
		d->nr_sense++;
	}

	/* irq should be disabled by default */
	d->chip.irq_mask(irq_data);

	intc_set_ack_handle(irq, desc, d, enum_id);
	intc_set_dist_handle(irq, desc, d, enum_id);

	activate_irq(irq);
}

static unsigned int __init save_reg(struct intc_desc_int *d,
				    unsigned int cnt,
				    unsigned long value,
				    unsigned int smp)
{
	if (value) {
		value = intc_phys_to_virt(d, value);

		d->reg[cnt] = value;
#ifdef CONFIG_SMP
		d->smp[cnt] = smp;
#endif
		return 1;
	}

	return 0;
}

int __init register_intc_controller(struct intc_desc *desc)
{
	unsigned int i, k, smp;
	struct intc_hw_desc *hw = &desc->hw;
	struct intc_desc_int *d;
	struct resource *res;

	pr_info("Registered controller '%s' with %u IRQs\n",
		desc->name, hw->nr_vectors);

	d = kzalloc(sizeof(*d), GFP_NOWAIT);
	if (!d)
		goto err0;

	INIT_LIST_HEAD(&d->list);
	list_add_tail(&d->list, &intc_list);

	raw_spin_lock_init(&d->lock);
	INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);

	d->index = nr_intc_controllers;

	if (desc->num_resources) {
		d->nr_windows = desc->num_resources;
		d->window = kzalloc(d->nr_windows * sizeof(*d->window),
				    GFP_NOWAIT);
		if (!d->window)
			goto err1;

		for (k = 0; k < d->nr_windows; k++) {
			res = desc->resource + k;
			WARN_ON(resource_type(res) != IORESOURCE_MEM);
			d->window[k].phys = res->start;
			d->window[k].size = resource_size(res);
			d->window[k].virt = ioremap_nocache(res->start,
							 resource_size(res));
			if (!d->window[k].virt)
				goto err2;
		}
	}

	d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
#ifdef CONFIG_INTC_BALANCING
	if (d->nr_reg)
		d->nr_reg += hw->nr_mask_regs;
#endif
	d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
	d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
	d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
	d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;

	d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
	if (!d->reg)
		goto err2;

#ifdef CONFIG_SMP
	d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
	if (!d->smp)
		goto err3;
#endif
	k = 0;

	if (hw->mask_regs) {
		for (i = 0; i < hw->nr_mask_regs; i++) {
			smp = IS_SMP(hw->mask_regs[i]);
			k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
			k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
#ifdef CONFIG_INTC_BALANCING
			k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
#endif
		}
	}

	if (hw->prio_regs) {
		d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
				  GFP_NOWAIT);
		if (!d->prio)
			goto err4;

		for (i = 0; i < hw->nr_prio_regs; i++) {
			smp = IS_SMP(hw->prio_regs[i]);
			k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
			k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
		}
	}

	if (hw->sense_regs) {
		d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
				   GFP_NOWAIT);
		if (!d->sense)
			goto err5;

		for (i = 0; i < hw->nr_sense_regs; i++)
			k += save_reg(d, k, hw->sense_regs[i].reg, 0);
	}

	if (hw->subgroups)
		for (i = 0; i < hw->nr_subgroups; i++)
			if (hw->subgroups[i].reg)
				k+= save_reg(d, k, hw->subgroups[i].reg, 0);

	memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
	d->chip.name = desc->name;

	if (hw->ack_regs)
		for (i = 0; i < hw->nr_ack_regs; i++)
			k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
	else
		d->chip.irq_mask_ack = d->chip.irq_disable;

	/* disable bits matching force_disable before registering irqs */
	if (desc->force_disable)
		intc_enable_disable_enum(desc, d, desc->force_disable, 0);

	/* disable bits matching force_enable before registering irqs */
	if (desc->force_enable)
		intc_enable_disable_enum(desc, d, desc->force_enable, 0);

	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */

	/* register the vectors one by one */
	for (i = 0; i < hw->nr_vectors; i++) {
		struct intc_vect *vect = hw->vectors + i;
		unsigned int irq = evt2irq(vect->vect);
		int res;

		if (!vect->enum_id)
			continue;

		res = irq_alloc_desc_at(irq, numa_node_id());
		if (res != irq && res != -EEXIST) {
			pr_err("can't get irq_desc for %d\n", irq);
			continue;
		}

		intc_irq_xlate_set(irq, vect->enum_id, d);
		intc_register_irq(desc, d, vect->enum_id, irq);

		for (k = i + 1; k < hw->nr_vectors; k++) {
			struct intc_vect *vect2 = hw->vectors + k;
			unsigned int irq2 = evt2irq(vect2->vect);

			if (vect->enum_id != vect2->enum_id)
				continue;

			/*
			 * In the case of multi-evt handling and sparse
			 * IRQ support, each vector still needs to have
			 * its own backing irq_desc.
			 */
			res = irq_alloc_desc_at(irq2, numa_node_id());
			if (res != irq2 && res != -EEXIST) {
				pr_err("can't get irq_desc for %d\n", irq2);
				continue;
			}

			vect2->enum_id = 0;

			/* redirect this interrupts to the first one */
			set_irq_chip(irq2, &dummy_irq_chip);
			set_irq_chained_handler(irq2, intc_redirect_irq);
			set_irq_data(irq2, (void *)irq);
		}
	}

	intc_subgroup_init(desc, d);

	/* enable bits matching force_enable after registering irqs */
	if (desc->force_enable)
		intc_enable_disable_enum(desc, d, desc->force_enable, 1);

	nr_intc_controllers++;

	return 0;
err5:
	kfree(d->prio);
err4:
#ifdef CONFIG_SMP
	kfree(d->smp);
err3:
#endif
	kfree(d->reg);
err2:
	for (k = 0; k < d->nr_windows; k++)
		if (d->window[k].virt)
			iounmap(d->window[k].virt);

	kfree(d->window);
err1:
	kfree(d);
err0:
	pr_err("unable to allocate INTC memory\n");

	return -ENOMEM;
}

static int intc_suspend(void)
{
	struct intc_desc_int *d;

	list_for_each_entry(d, &intc_list, list) {
		int irq;

		/* enable wakeup irqs belonging to this intc controller */
		for_each_active_irq(irq) {
			struct irq_data *data;
			struct irq_desc *desc;
			struct irq_chip *chip;

			data = irq_get_irq_data(irq);
			chip = irq_data_get_irq_chip(data);
			if (chip != &d->chip)
				continue;
			desc = irq_to_desc(irq);
			if ((desc->status & IRQ_WAKEUP))
				chip->irq_enable(data);
		}
	}

	return 0;
}

static void intc_resume(void)
{
	struct intc_desc_int *d;

	list_for_each_entry(d, &intc_list, list) {
		int irq;

		for_each_active_irq(irq) {
			struct irq_data *data;
			struct irq_desc *desc;
			struct irq_chip *chip;

			data = irq_get_irq_data(irq);
			chip = irq_data_get_irq_chip(data);
			/*
			 * This will catch the redirect and VIRQ cases
			 * due to the dummy_irq_chip being inserted.
			 */
			if (chip != &d->chip)
				continue;
			desc = irq_to_desc(irq);
			if (desc->status & IRQ_DISABLED)
				chip->irq_disable(data);
			else
				chip->irq_enable(data);
		}
	}
}

struct syscore_ops intc_syscore_ops = {
	.suspend	= intc_suspend,
	.resume		= intc_resume,
};

struct sysdev_class intc_sysdev_class = {
	.name		= "intc",
};

static ssize_t
show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
{
	struct intc_desc_int *d;

	d = container_of(dev, struct intc_desc_int, sysdev);

	return sprintf(buf, "%s\n", d->chip.name);
}

static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);

static int __init register_intc_sysdevs(void)
{
	struct intc_desc_int *d;
	int error;

	register_syscore_ops(&intc_syscore_ops);

	error = sysdev_class_register(&intc_sysdev_class);
	if (!error) {
		list_for_each_entry(d, &intc_list, list) {
			d->sysdev.id = d->index;
			d->sysdev.cls = &intc_sysdev_class;
			error = sysdev_register(&d->sysdev);
			if (error == 0)
				error = sysdev_create_file(&d->sysdev,
							   &attr_name);
			if (error)
				break;
		}
	}

	if (error)
		pr_err("sysdev registration error\n");

	return error;
}
device_initcall(register_intc_sysdevs);
Commit	Line	Data
2be6bb0c PM	1	/*
	2	* Shared interrupt handling code for IPR and INTC2 types of IRQs.
	3	*
	4	* Copyright (C) 2007, 2008 Magnus Damm
	5	* Copyright (C) 2009, 2010 Paul Mundt
	6	*
	7	* Based on intc2.c and ipr.c
	8	*
	9	* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
	10	* Copyright (C) 2000 Kazumoto Kojima
	11	* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
	12	* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
	13	* Copyright (C) 2005, 2006 Paul Mundt
	14	*
	15	* This file is subject to the terms and conditions of the GNU General Public
	16	* License. See the file "COPYING" in the main directory of this archive
	17	* for more details.
	18	*/
	19	#define pr_fmt(fmt) "intc: " fmt
	20
	21	#include <linux/init.h>
	22	#include <linux/irq.h>
	23	#include <linux/io.h>
	24	#include <linux/slab.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/sh_intc.h>
	27	#include <linux/sysdev.h>
a696b89c	28	#include <linux/syscore_ops.h>
2be6bb0c PM	29	#include <linux/list.h>
	30	#include <linux/spinlock.h>
	31	#include <linux/radix-tree.h>
	32	#include "internals.h"
	33
	34	LIST_HEAD(intc_list);
	35	DEFINE_RAW_SPINLOCK(intc_big_lock);
	36	unsigned int nr_intc_controllers;
	37
	38	/*
	39	* Default priority level
	40	* - this needs to be at least 2 for 5-bit priorities on 7780
	41	*/
	42	static unsigned int default_prio_level = 2; /* 2 - 16 */
	43	static unsigned int intc_prio_level[NR_IRQS]; /* for now */
	44
	45	unsigned int intc_get_dfl_prio_level(void)
	46	{
	47	return default_prio_level;
	48	}
	49
	50	unsigned int intc_get_prio_level(unsigned int irq)
	51	{
	52	return intc_prio_level[irq];
	53	}
	54
	55	void intc_set_prio_level(unsigned int irq, unsigned int level)
	56	{
	57	unsigned long flags;
	58
	59	raw_spin_lock_irqsave(&intc_big_lock, flags);
	60	intc_prio_level[irq] = level;
	61	raw_spin_unlock_irqrestore(&intc_big_lock, flags);
	62	}
	63
	64	static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
	65	{
	66	generic_handle_irq((unsigned int)get_irq_data(irq));
	67	}
	68
	69	static void __init intc_register_irq(struct intc_desc *desc,
	70	struct intc_desc_int *d,
	71	intc_enum enum_id,
	72	unsigned int irq)
	73	{
	74	struct intc_handle_int *hp;
26599a94	75	struct irq_data *irq_data;
2be6bb0c PM	76	unsigned int data[2], primary;
	77	unsigned long flags;
	78
	79	/*
	80	* Register the IRQ position with the global IRQ map, then insert
	81	* it in to the radix tree.
	82	*/
20f95e0b	83	irq_reserve_irq(irq);
2be6bb0c PM	84
	85	raw_spin_lock_irqsave(&intc_big_lock, flags);
	86	radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
	87	raw_spin_unlock_irqrestore(&intc_big_lock, flags);
	88
	89	/*
	90	* Prefer single interrupt source bitmap over other combinations:
	91	*
	92	* 1. bitmap, single interrupt source
	93	* 2. priority, single interrupt source
	94	* 3. bitmap, multiple interrupt sources (groups)
	95	* 4. priority, multiple interrupt sources (groups)
	96	*/
	97	data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
	98	data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
	99
	100	primary = 0;
	101	if (!data[0] && data[1])
	102	primary = 1;
	103
	104	if (!data[0] && !data[1])
	105	pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
	106	irq, irq2evt(irq));
	107
	108	data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
	109	data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
	110
	111	if (!data[primary])
	112	primary ^= 1;
	113
	114	BUG_ON(!data[primary]); /* must have primary masking method */
	115
26599a94 PM	116	irq_data = irq_get_irq_data(irq);
26599a94 PM	117
2be6bb0c PM	118	disable_irq_nosync(irq);
	119	set_irq_chip_and_handler_name(irq, &d->chip,
	120	handle_level_irq, "level");
	121	set_irq_chip_data(irq, (void *)data[primary]);
	122
	123	/*
	124	* set priority level
	125	*/
	126	intc_set_prio_level(irq, intc_get_dfl_prio_level());
	127
	128	/* enable secondary masking method if present */
	129	if (data[!primary])
26599a94	130	_intc_enable(irq_data, data[!primary]);
2be6bb0c PM	131
	132	/* add irq to d->prio list if priority is available */
	133	if (data[1]) {
	134	hp = d->prio + d->nr_prio;
	135	hp->irq = irq;
	136	hp->handle = data[1];
	137
	138	if (primary) {
	139	/*
	140	* only secondary priority should access registers, so
	141	* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
	142	*/
	143	hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
	144	hp->handle \|= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
	145	}
	146	d->nr_prio++;
	147	}
	148
	149	/* add irq to d->sense list if sense is available */
	150	data[0] = intc_get_sense_handle(desc, d, enum_id);
	151	if (data[0]) {
	152	(d->sense + d->nr_sense)->irq = irq;
	153	(d->sense + d->nr_sense)->handle = data[0];
	154	d->nr_sense++;
	155	}
	156
	157	/* irq should be disabled by default */
26599a94	158	d->chip.irq_mask(irq_data);
2be6bb0c PM	159
	160	intc_set_ack_handle(irq, desc, d, enum_id);
	161	intc_set_dist_handle(irq, desc, d, enum_id);
	162
	163	activate_irq(irq);
	164	}
	165
	166	static unsigned int __init save_reg(struct intc_desc_int *d,
	167	unsigned int cnt,
	168	unsigned long value,
	169	unsigned int smp)
	170	{
	171	if (value) {
	172	value = intc_phys_to_virt(d, value);
	173
	174	d->reg[cnt] = value;
	175	#ifdef CONFIG_SMP
	176	d->smp[cnt] = smp;
	177	#endif
	178	return 1;
	179	}
	180
	181	return 0;
	182	}
	183
	184	int __init register_intc_controller(struct intc_desc *desc)
	185	{
	186	unsigned int i, k, smp;
	187	struct intc_hw_desc *hw = &desc->hw;
	188	struct intc_desc_int *d;
	189	struct resource *res;
	190
	191	pr_info("Registered controller '%s' with %u IRQs\n",
	192	desc->name, hw->nr_vectors);
	193
	194	d = kzalloc(sizeof(*d), GFP_NOWAIT);
	195	if (!d)
	196	goto err0;
	197
	198	INIT_LIST_HEAD(&d->list);
	199	list_add_tail(&d->list, &intc_list);
	200
	201	raw_spin_lock_init(&d->lock);
30f2ba38	202	INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
2be6bb0c PM	203
	204	d->index = nr_intc_controllers;
	205
	206	if (desc->num_resources) {
	207	d->nr_windows = desc->num_resources;
	208	d->window = kzalloc(d->nr_windows * sizeof(*d->window),
	209	GFP_NOWAIT);
	210	if (!d->window)
	211	goto err1;
	212
	213	for (k = 0; k < d->nr_windows; k++) {
	214	res = desc->resource + k;
	215	WARN_ON(resource_type(res) != IORESOURCE_MEM);
	216	d->window[k].phys = res->start;
	217	d->window[k].size = resource_size(res);
	218	d->window[k].virt = ioremap_nocache(res->start,
	219	resource_size(res));
	220	if (!d->window[k].virt)
	221	goto err2;
	222	}
	223	}
	224
	225	d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
	226	#ifdef CONFIG_INTC_BALANCING
	227	if (d->nr_reg)
	228	d->nr_reg += hw->nr_mask_regs;
	229	#endif
	230	d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
	231	d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
	232	d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
	233	d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
	234
	235	d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
	236	if (!d->reg)
	237	goto err2;
	238
	239	#ifdef CONFIG_SMP
	240	d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
	241	if (!d->smp)
	242	goto err3;
	243	#endif
	244	k = 0;
	245
	246	if (hw->mask_regs) {
	247	for (i = 0; i < hw->nr_mask_regs; i++) {
	248	smp = IS_SMP(hw->mask_regs[i]);
	249	k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
	250	k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
	251	#ifdef CONFIG_INTC_BALANCING
	252	k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
	253	#endif
	254	}
	255	}
	256
	257	if (hw->prio_regs) {
	258	d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
	259	GFP_NOWAIT);
	260	if (!d->prio)
	261	goto err4;
	262
	263	for (i = 0; i < hw->nr_prio_regs; i++) {
	264	smp = IS_SMP(hw->prio_regs[i]);
	265	k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
	266	k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
267	}
268	}
269
270	if (hw->sense_regs) {
271	d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
272	GFP_NOWAIT);
273	if (!d->sense)
274	goto err5;
275
276	for (i = 0; i < hw->nr_sense_regs; i++)
277	k += save_reg(d, k, hw->sense_regs[i].reg, 0);
278	}
279
280	if (hw->subgroups)
281	for (i = 0; i < hw->nr_subgroups; i++)
282	if (hw->subgroups[i].reg)
283	k+= save_reg(d, k, hw->subgroups[i].reg, 0);
284
285	memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
286	d->chip.name = desc->name;
287
288	if (hw->ack_regs)
289	for (i = 0; i < hw->nr_ack_regs; i++)
290	k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
291	else
26599a94	292	d->chip.irq_mask_ack = d->chip.irq_disable;
2be6bb0c PM	293
	294	/* disable bits matching force_disable before registering irqs */
	295	if (desc->force_disable)
	296	intc_enable_disable_enum(desc, d, desc->force_disable, 0);
	297
	298	/* disable bits matching force_enable before registering irqs */
	299	if (desc->force_enable)
	300	intc_enable_disable_enum(desc, d, desc->force_enable, 0);
	301
	302	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
	303
	304	/* register the vectors one by one */
	305	for (i = 0; i < hw->nr_vectors; i++) {
	306	struct intc_vect *vect = hw->vectors + i;
	307	unsigned int irq = evt2irq(vect->vect);
c4318baf	308	int res;
2be6bb0c PM	309
	310	if (!vect->enum_id)
	311	continue;
	312
c4318baf TG	313	res = irq_alloc_desc_at(irq, numa_node_id());
c4318baf TG	314	if (res != irq && res != -EEXIST) {
2be6bb0c PM	315	pr_err("can't get irq_desc for %d\n", irq);
	316	continue;
	317	}
	318
	319	intc_irq_xlate_set(irq, vect->enum_id, d);
	320	intc_register_irq(desc, d, vect->enum_id, irq);
	321
	322	for (k = i + 1; k < hw->nr_vectors; k++) {
	323	struct intc_vect *vect2 = hw->vectors + k;
	324	unsigned int irq2 = evt2irq(vect2->vect);
	325
	326	if (vect->enum_id != vect2->enum_id)
	327	continue;
	328
	329	/*
	330	* In the case of multi-evt handling and sparse
	331	* IRQ support, each vector still needs to have
	332	* its own backing irq_desc.
	333	*/
c4318baf TG	334	res = irq_alloc_desc_at(irq2, numa_node_id());
c4318baf TG	335	if (res != irq2 && res != -EEXIST) {
2be6bb0c PM	336	pr_err("can't get irq_desc for %d\n", irq2);
	337	continue;
	338	}
	339
	340	vect2->enum_id = 0;
	341
	342	/* redirect this interrupts to the first one */
	343	set_irq_chip(irq2, &dummy_irq_chip);
	344	set_irq_chained_handler(irq2, intc_redirect_irq);
	345	set_irq_data(irq2, (void *)irq);
	346	}
	347	}
	348
	349	intc_subgroup_init(desc, d);
	350
	351	/* enable bits matching force_enable after registering irqs */
	352	if (desc->force_enable)
	353	intc_enable_disable_enum(desc, d, desc->force_enable, 1);
	354
	355	nr_intc_controllers++;
	356
	357	return 0;
	358	err5:
	359	kfree(d->prio);
	360	err4:
	361	#ifdef CONFIG_SMP
	362	kfree(d->smp);
	363	err3:
	364	#endif
	365	kfree(d->reg);
	366	err2:
	367	for (k = 0; k < d->nr_windows; k++)
	368	if (d->window[k].virt)
	369	iounmap(d->window[k].virt);
	370
	371	kfree(d->window);
	372	err1:
	373	kfree(d);
	374	err0:
	375	pr_err("unable to allocate INTC memory\n");
	376
	377	return -ENOMEM;
	378	}
	379
a696b89c	380	static int intc_suspend(void)
2be6bb0c PM	381	{
	382	struct intc_desc_int *d;
	383
a696b89c RW	384	list_for_each_entry(d, &intc_list, list) {
a696b89c RW	385	int irq;
2be6bb0c	386
a696b89c RW	387	/* enable wakeup irqs belonging to this intc controller */
	388	for_each_active_irq(irq) {
	389	struct irq_data *data;
	390	struct irq_desc *desc;
	391	struct irq_chip *chip;
2be6bb0c	392
a696b89c RW	393	data = irq_get_irq_data(irq);
	394	chip = irq_data_get_irq_chip(data);
	395	if (chip != &d->chip)
	396	continue;
	397	desc = irq_to_desc(irq);
	398	if ((desc->status & IRQ_WAKEUP))
	399	chip->irq_enable(data);
	400	}
	401	}
	402
	403	return 0;
	404	}
2be6bb0c	405
a696b89c	406	static void intc_resume(void)
2be6bb0c PM	407	{
2be6bb0c PM	408	struct intc_desc_int *d;
2be6bb0c	409
a696b89c RW	410	list_for_each_entry(d, &intc_list, list) {
a696b89c RW	411	int irq;
2be6bb0c	412
63111a3a	413	for_each_active_irq(irq) {
a696b89c RW	414	struct irq_data *data;
	415	struct irq_desc *desc;
	416	struct irq_chip *chip;
	417
26599a94 PM	418	data = irq_get_irq_data(irq);
26599a94 PM	419	chip = irq_data_get_irq_chip(data);
2be6bb0c PM	420	/*
	421	* This will catch the redirect and VIRQ cases
	422	* due to the dummy_irq_chip being inserted.
	423	*/
26599a94	424	if (chip != &d->chip)
2be6bb0c	425	continue;
a696b89c	426	desc = irq_to_desc(irq);
2be6bb0c	427	if (desc->status & IRQ_DISABLED)
26599a94	428	chip->irq_disable(data);
2be6bb0c	429	else
26599a94	430	chip->irq_enable(data);
2be6bb0c	431	}
2be6bb0c	432	}
2be6bb0c PM	433	}
2be6bb0c PM	434
a696b89c RW	435	struct syscore_ops intc_syscore_ops = {
	436	.suspend = intc_suspend,
	437	.resume = intc_resume,
	438	};
2be6bb0c PM	439
	440	struct sysdev_class intc_sysdev_class = {
	441	.name = "intc",
2be6bb0c PM	442	};
2be6bb0c PM	443
a696b89c RW	444	static ssize_t
	445	show_intc_name(struct sys_device dev, struct sysdev_attribute attr, char *buf)
	446	{
	447	struct intc_desc_int *d;
	448
	449	d = container_of(dev, struct intc_desc_int, sysdev);
	450
	451	return sprintf(buf, "%s\n", d->chip.name);
	452	}
	453
	454	static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
	455
2be6bb0c PM	456	static int __init register_intc_sysdevs(void)
	457	{
	458	struct intc_desc_int *d;
	459	int error;
	460
a696b89c RW	461	register_syscore_ops(&intc_syscore_ops);
a696b89c RW	462
2be6bb0c PM	463	error = sysdev_class_register(&intc_sysdev_class);
	464	if (!error) {
	465	list_for_each_entry(d, &intc_list, list) {
	466	d->sysdev.id = d->index;
	467	d->sysdev.cls = &intc_sysdev_class;
	468	error = sysdev_register(&d->sysdev);
	469	if (error == 0)
	470	error = sysdev_create_file(&d->sysdev,
	471	&attr_name);
	472	if (error)
	473	break;
	474	}
	475	}
	476
	477	if (error)
	478	pr_err("sysdev registration error\n");
	479
	480	return error;
	481	}
	482	device_initcall(register_intc_sysdevs);