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Commit | Line | Data |
---|---|---|
2967dab1 | 1 | /* |
b3c185a7 | 2 | * SuperH Pin Function Controller support. |
2967dab1 MD |
3 | * |
4 | * Copyright (C) 2008 Magnus Damm | |
b3c185a7 | 5 | * Copyright (C) 2009 - 2012 Paul Mundt |
2967dab1 MD |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
a2d3afff | 11 | #define pr_fmt(fmt) "sh_pfc " KBUILD_MODNAME ": " fmt |
b72421d8 | 12 | |
2967dab1 MD |
13 | #include <linux/errno.h> |
14 | #include <linux/kernel.h> | |
b3c185a7 | 15 | #include <linux/sh_pfc.h> |
2967dab1 | 16 | #include <linux/module.h> |
2967dab1 MD |
17 | #include <linux/err.h> |
18 | #include <linux/io.h> | |
2967dab1 | 19 | #include <linux/bitops.h> |
b0e10211 MD |
20 | #include <linux/slab.h> |
21 | #include <linux/ioport.h> | |
ca5481c6 | 22 | #include <linux/pinctrl/machine.h> |
b0e10211 | 23 | |
b3c185a7 PM |
24 | static struct sh_pfc *sh_pfc __read_mostly; |
25 | ||
26 | static inline bool sh_pfc_initialized(void) | |
27 | { | |
28 | return !!sh_pfc; | |
29 | } | |
30 | ||
31 | static void pfc_iounmap(struct sh_pfc *pfc) | |
b0e10211 MD |
32 | { |
33 | int k; | |
34 | ||
b3c185a7 PM |
35 | for (k = 0; k < pfc->num_resources; k++) |
36 | if (pfc->window[k].virt) | |
37 | iounmap(pfc->window[k].virt); | |
b0e10211 | 38 | |
b3c185a7 PM |
39 | kfree(pfc->window); |
40 | pfc->window = NULL; | |
b0e10211 MD |
41 | } |
42 | ||
b3c185a7 | 43 | static int pfc_ioremap(struct sh_pfc *pfc) |
b0e10211 MD |
44 | { |
45 | struct resource *res; | |
46 | int k; | |
47 | ||
b3c185a7 | 48 | if (!pfc->num_resources) |
b0e10211 MD |
49 | return 0; |
50 | ||
b3c185a7 | 51 | pfc->window = kzalloc(pfc->num_resources * sizeof(*pfc->window), |
b0e10211 | 52 | GFP_NOWAIT); |
b3c185a7 | 53 | if (!pfc->window) |
b0e10211 MD |
54 | goto err1; |
55 | ||
b3c185a7 PM |
56 | for (k = 0; k < pfc->num_resources; k++) { |
57 | res = pfc->resource + k; | |
b0e10211 | 58 | WARN_ON(resource_type(res) != IORESOURCE_MEM); |
b3c185a7 PM |
59 | pfc->window[k].phys = res->start; |
60 | pfc->window[k].size = resource_size(res); | |
61 | pfc->window[k].virt = ioremap_nocache(res->start, | |
b0e10211 | 62 | resource_size(res)); |
b3c185a7 | 63 | if (!pfc->window[k].virt) |
b0e10211 MD |
64 | goto err2; |
65 | } | |
66 | ||
67 | return 0; | |
68 | ||
69 | err2: | |
b3c185a7 | 70 | pfc_iounmap(pfc); |
b0e10211 MD |
71 | err1: |
72 | return -1; | |
73 | } | |
74 | ||
b3c185a7 | 75 | static void __iomem *pfc_phys_to_virt(struct sh_pfc *pfc, |
b0e10211 MD |
76 | unsigned long address) |
77 | { | |
78 | struct pfc_window *window; | |
79 | int k; | |
80 | ||
81 | /* scan through physical windows and convert address */ | |
b3c185a7 PM |
82 | for (k = 0; k < pfc->num_resources; k++) { |
83 | window = pfc->window + k; | |
b0e10211 MD |
84 | |
85 | if (address < window->phys) | |
86 | continue; | |
87 | ||
88 | if (address >= (window->phys + window->size)) | |
89 | continue; | |
90 | ||
91 | return window->virt + (address - window->phys); | |
92 | } | |
93 | ||
94 | /* no windows defined, register must be 1:1 mapped virt:phys */ | |
95 | return (void __iomem *)address; | |
96 | } | |
2967dab1 | 97 | |
2967dab1 MD |
98 | static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) |
99 | { | |
100 | if (enum_id < r->begin) | |
101 | return 0; | |
102 | ||
103 | if (enum_id > r->end) | |
104 | return 0; | |
105 | ||
106 | return 1; | |
107 | } | |
108 | ||
b0e10211 | 109 | static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg, |
3292094e MD |
110 | unsigned long reg_width) |
111 | { | |
112 | switch (reg_width) { | |
113 | case 8: | |
b0e10211 | 114 | return ioread8(mapped_reg); |
3292094e | 115 | case 16: |
b0e10211 | 116 | return ioread16(mapped_reg); |
3292094e | 117 | case 32: |
b0e10211 | 118 | return ioread32(mapped_reg); |
3292094e MD |
119 | } |
120 | ||
121 | BUG(); | |
122 | return 0; | |
123 | } | |
124 | ||
b0e10211 | 125 | static void gpio_write_raw_reg(void __iomem *mapped_reg, |
3292094e MD |
126 | unsigned long reg_width, |
127 | unsigned long data) | |
128 | { | |
129 | switch (reg_width) { | |
130 | case 8: | |
b0e10211 | 131 | iowrite8(data, mapped_reg); |
3292094e MD |
132 | return; |
133 | case 16: | |
b0e10211 | 134 | iowrite16(data, mapped_reg); |
3292094e MD |
135 | return; |
136 | case 32: | |
b0e10211 | 137 | iowrite32(data, mapped_reg); |
3292094e MD |
138 | return; |
139 | } | |
140 | ||
141 | BUG(); | |
142 | } | |
143 | ||
b3c185a7 | 144 | int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos) |
92554d97 MD |
145 | { |
146 | unsigned long pos; | |
147 | ||
148 | pos = dr->reg_width - (in_pos + 1); | |
149 | ||
150 | pr_debug("read_bit: addr = %lx, pos = %ld, " | |
151 | "r_width = %ld\n", dr->reg, pos, dr->reg_width); | |
152 | ||
153 | return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; | |
154 | } | |
b3c185a7 | 155 | EXPORT_SYMBOL_GPL(sh_pfc_read_bit); |
92554d97 | 156 | |
b3c185a7 PM |
157 | void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, |
158 | unsigned long value) | |
3292094e MD |
159 | { |
160 | unsigned long pos; | |
161 | ||
162 | pos = dr->reg_width - (in_pos + 1); | |
163 | ||
ca6f2d7f | 164 | pr_debug("write_bit addr = %lx, value = %d, pos = %ld, " |
fd2cb0ce PM |
165 | "r_width = %ld\n", |
166 | dr->reg, !!value, pos, dr->reg_width); | |
3292094e MD |
167 | |
168 | if (value) | |
169 | set_bit(pos, &dr->reg_shadow); | |
170 | else | |
171 | clear_bit(pos, &dr->reg_shadow); | |
172 | ||
b0e10211 | 173 | gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); |
3292094e | 174 | } |
b3c185a7 | 175 | EXPORT_SYMBOL_GPL(sh_pfc_write_bit); |
3292094e | 176 | |
b3c185a7 | 177 | static void config_reg_helper(struct sh_pfc *pfc, |
18925e11 MD |
178 | struct pinmux_cfg_reg *crp, |
179 | unsigned long in_pos, | |
180 | void __iomem **mapped_regp, | |
181 | unsigned long *maskp, | |
182 | unsigned long *posp) | |
2967dab1 | 183 | { |
f78a26f5 MD |
184 | int k; |
185 | ||
b3c185a7 | 186 | *mapped_regp = pfc_phys_to_virt(pfc, crp->reg); |
2967dab1 | 187 | |
f78a26f5 MD |
188 | if (crp->field_width) { |
189 | *maskp = (1 << crp->field_width) - 1; | |
190 | *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); | |
191 | } else { | |
192 | *maskp = (1 << crp->var_field_width[in_pos]) - 1; | |
193 | *posp = crp->reg_width; | |
194 | for (k = 0; k <= in_pos; k++) | |
195 | *posp -= crp->var_field_width[k]; | |
196 | } | |
18925e11 MD |
197 | } |
198 | ||
b3c185a7 | 199 | static int read_config_reg(struct sh_pfc *pfc, |
18925e11 MD |
200 | struct pinmux_cfg_reg *crp, |
201 | unsigned long field) | |
202 | { | |
203 | void __iomem *mapped_reg; | |
204 | unsigned long mask, pos; | |
205 | ||
b3c185a7 | 206 | config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 207 | |
18925e11 | 208 | pr_debug("read_reg: addr = %lx, field = %ld, " |
fd2cb0ce | 209 | "r_width = %ld, f_width = %ld\n", |
18925e11 | 210 | crp->reg, field, crp->reg_width, crp->field_width); |
2967dab1 | 211 | |
18925e11 | 212 | return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask; |
0fc64cc0 MD |
213 | } |
214 | ||
b3c185a7 | 215 | static void write_config_reg(struct sh_pfc *pfc, |
18925e11 MD |
216 | struct pinmux_cfg_reg *crp, |
217 | unsigned long field, unsigned long value) | |
0fc64cc0 | 218 | { |
18925e11 | 219 | void __iomem *mapped_reg; |
e499ada8 | 220 | unsigned long mask, pos, data; |
0fc64cc0 | 221 | |
b3c185a7 | 222 | config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 223 | |
18925e11 | 224 | pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " |
fd2cb0ce | 225 | "r_width = %ld, f_width = %ld\n", |
18925e11 | 226 | crp->reg, value, field, crp->reg_width, crp->field_width); |
0fc64cc0 MD |
227 | |
228 | mask = ~(mask << pos); | |
229 | value = value << pos; | |
2967dab1 | 230 | |
e499ada8 MD |
231 | data = gpio_read_raw_reg(mapped_reg, crp->reg_width); |
232 | data &= mask; | |
233 | data |= value; | |
234 | ||
b3c185a7 PM |
235 | if (pfc->unlock_reg) |
236 | gpio_write_raw_reg(pfc_phys_to_virt(pfc, pfc->unlock_reg), | |
e499ada8 MD |
237 | 32, ~data); |
238 | ||
239 | gpio_write_raw_reg(mapped_reg, crp->reg_width, data); | |
2967dab1 MD |
240 | } |
241 | ||
b3c185a7 | 242 | static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio) |
2967dab1 | 243 | { |
b3c185a7 | 244 | struct pinmux_gpio *gpiop = &pfc->gpios[gpio]; |
2967dab1 MD |
245 | struct pinmux_data_reg *data_reg; |
246 | int k, n; | |
247 | ||
b3c185a7 | 248 | if (!enum_in_range(gpiop->enum_id, &pfc->data)) |
2967dab1 MD |
249 | return -1; |
250 | ||
251 | k = 0; | |
252 | while (1) { | |
b3c185a7 | 253 | data_reg = pfc->data_regs + k; |
2967dab1 MD |
254 | |
255 | if (!data_reg->reg_width) | |
256 | break; | |
257 | ||
b3c185a7 | 258 | data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg); |
b0e10211 | 259 | |
2967dab1 | 260 | for (n = 0; n < data_reg->reg_width; n++) { |
18801be7 MD |
261 | if (data_reg->enum_ids[n] == gpiop->enum_id) { |
262 | gpiop->flags &= ~PINMUX_FLAG_DREG; | |
263 | gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); | |
264 | gpiop->flags &= ~PINMUX_FLAG_DBIT; | |
265 | gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); | |
2967dab1 | 266 | return 0; |
2967dab1 MD |
267 | } |
268 | } | |
269 | k++; | |
270 | } | |
271 | ||
18801be7 MD |
272 | BUG(); |
273 | ||
2967dab1 MD |
274 | return -1; |
275 | } | |
276 | ||
b3c185a7 | 277 | static void setup_data_regs(struct sh_pfc *pfc) |
3292094e MD |
278 | { |
279 | struct pinmux_data_reg *drp; | |
280 | int k; | |
281 | ||
b3c185a7 PM |
282 | for (k = pfc->first_gpio; k <= pfc->last_gpio; k++) |
283 | setup_data_reg(pfc, k); | |
3292094e MD |
284 | |
285 | k = 0; | |
286 | while (1) { | |
b3c185a7 | 287 | drp = pfc->data_regs + k; |
3292094e MD |
288 | |
289 | if (!drp->reg_width) | |
290 | break; | |
291 | ||
b0e10211 MD |
292 | drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg, |
293 | drp->reg_width); | |
3292094e MD |
294 | k++; |
295 | } | |
296 | } | |
297 | ||
b3c185a7 | 298 | int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, |
18801be7 MD |
299 | struct pinmux_data_reg **drp, int *bitp) |
300 | { | |
b3c185a7 | 301 | struct pinmux_gpio *gpiop = &pfc->gpios[gpio]; |
18801be7 MD |
302 | int k, n; |
303 | ||
b3c185a7 | 304 | if (!enum_in_range(gpiop->enum_id, &pfc->data)) |
18801be7 MD |
305 | return -1; |
306 | ||
307 | k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; | |
308 | n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; | |
b3c185a7 | 309 | *drp = pfc->data_regs + k; |
18801be7 MD |
310 | *bitp = n; |
311 | return 0; | |
312 | } | |
b3c185a7 | 313 | EXPORT_SYMBOL_GPL(sh_pfc_get_data_reg); |
18801be7 | 314 | |
b3c185a7 | 315 | static int get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, |
ad4a07ff MD |
316 | struct pinmux_cfg_reg **crp, |
317 | int *fieldp, int *valuep, | |
2967dab1 MD |
318 | unsigned long **cntp) |
319 | { | |
320 | struct pinmux_cfg_reg *config_reg; | |
f78a26f5 MD |
321 | unsigned long r_width, f_width, curr_width, ncomb; |
322 | int k, m, n, pos, bit_pos; | |
2967dab1 MD |
323 | |
324 | k = 0; | |
325 | while (1) { | |
b3c185a7 | 326 | config_reg = pfc->cfg_regs + k; |
2967dab1 MD |
327 | |
328 | r_width = config_reg->reg_width; | |
329 | f_width = config_reg->field_width; | |
330 | ||
331 | if (!r_width) | |
332 | break; | |
f78a26f5 MD |
333 | |
334 | pos = 0; | |
335 | m = 0; | |
336 | for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { | |
337 | if (f_width) | |
338 | curr_width = f_width; | |
339 | else | |
340 | curr_width = config_reg->var_field_width[m]; | |
341 | ||
342 | ncomb = 1 << curr_width; | |
343 | for (n = 0; n < ncomb; n++) { | |
344 | if (config_reg->enum_ids[pos + n] == enum_id) { | |
345 | *crp = config_reg; | |
346 | *fieldp = m; | |
347 | *valuep = n; | |
348 | *cntp = &config_reg->cnt[m]; | |
349 | return 0; | |
350 | } | |
2967dab1 | 351 | } |
f78a26f5 MD |
352 | pos += ncomb; |
353 | m++; | |
2967dab1 MD |
354 | } |
355 | k++; | |
356 | } | |
357 | ||
358 | return -1; | |
359 | } | |
360 | ||
b3c185a7 PM |
361 | int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, |
362 | pinmux_enum_t *enum_idp) | |
2967dab1 | 363 | { |
b3c185a7 PM |
364 | pinmux_enum_t enum_id = pfc->gpios[gpio].enum_id; |
365 | pinmux_enum_t *data = pfc->gpio_data; | |
2967dab1 MD |
366 | int k; |
367 | ||
b3c185a7 PM |
368 | if (!enum_in_range(enum_id, &pfc->data)) { |
369 | if (!enum_in_range(enum_id, &pfc->mark)) { | |
2967dab1 MD |
370 | pr_err("non data/mark enum_id for gpio %d\n", gpio); |
371 | return -1; | |
372 | } | |
373 | } | |
374 | ||
375 | if (pos) { | |
376 | *enum_idp = data[pos + 1]; | |
377 | return pos + 1; | |
378 | } | |
379 | ||
b3c185a7 | 380 | for (k = 0; k < pfc->gpio_data_size; k++) { |
2967dab1 MD |
381 | if (data[k] == enum_id) { |
382 | *enum_idp = data[k + 1]; | |
383 | return k + 1; | |
384 | } | |
385 | } | |
386 | ||
387 | pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); | |
388 | return -1; | |
389 | } | |
b3c185a7 | 390 | EXPORT_SYMBOL_GPL(sh_pfc_gpio_to_enum); |
2967dab1 | 391 | |
b3c185a7 PM |
392 | int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, |
393 | int cfg_mode) | |
2967dab1 MD |
394 | { |
395 | struct pinmux_cfg_reg *cr = NULL; | |
396 | pinmux_enum_t enum_id; | |
397 | struct pinmux_range *range; | |
ad4a07ff | 398 | int in_range, pos, field, value; |
2967dab1 MD |
399 | unsigned long *cntp; |
400 | ||
401 | switch (pinmux_type) { | |
402 | ||
403 | case PINMUX_TYPE_FUNCTION: | |
404 | range = NULL; | |
405 | break; | |
406 | ||
407 | case PINMUX_TYPE_OUTPUT: | |
b3c185a7 | 408 | range = &pfc->output; |
2967dab1 MD |
409 | break; |
410 | ||
411 | case PINMUX_TYPE_INPUT: | |
b3c185a7 | 412 | range = &pfc->input; |
2967dab1 MD |
413 | break; |
414 | ||
415 | case PINMUX_TYPE_INPUT_PULLUP: | |
b3c185a7 | 416 | range = &pfc->input_pu; |
2967dab1 MD |
417 | break; |
418 | ||
419 | case PINMUX_TYPE_INPUT_PULLDOWN: | |
b3c185a7 | 420 | range = &pfc->input_pd; |
2967dab1 MD |
421 | break; |
422 | ||
423 | default: | |
424 | goto out_err; | |
425 | } | |
426 | ||
427 | pos = 0; | |
428 | enum_id = 0; | |
ad4a07ff MD |
429 | field = 0; |
430 | value = 0; | |
2967dab1 | 431 | while (1) { |
b3c185a7 | 432 | pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id); |
2967dab1 MD |
433 | if (pos <= 0) |
434 | goto out_err; | |
435 | ||
436 | if (!enum_id) | |
437 | break; | |
438 | ||
50dd3145 | 439 | /* first check if this is a function enum */ |
b3c185a7 | 440 | in_range = enum_in_range(enum_id, &pfc->function); |
50dd3145 MD |
441 | if (!in_range) { |
442 | /* not a function enum */ | |
443 | if (range) { | |
444 | /* | |
445 | * other range exists, so this pin is | |
446 | * a regular GPIO pin that now is being | |
447 | * bound to a specific direction. | |
448 | * | |
449 | * for this case we only allow function enums | |
450 | * and the enums that match the other range. | |
451 | */ | |
452 | in_range = enum_in_range(enum_id, range); | |
453 | ||
454 | /* | |
455 | * special case pass through for fixed | |
456 | * input-only or output-only pins without | |
457 | * function enum register association. | |
458 | */ | |
459 | if (in_range && enum_id == range->force) | |
460 | continue; | |
461 | } else { | |
462 | /* | |
463 | * no other range exists, so this pin | |
464 | * must then be of the function type. | |
465 | * | |
466 | * allow function type pins to select | |
467 | * any combination of function/in/out | |
468 | * in their MARK lists. | |
469 | */ | |
470 | in_range = 1; | |
471 | } | |
42eed42b MD |
472 | } |
473 | ||
2967dab1 MD |
474 | if (!in_range) |
475 | continue; | |
476 | ||
b3c185a7 | 477 | if (get_config_reg(pfc, enum_id, &cr, |
ad4a07ff | 478 | &field, &value, &cntp) != 0) |
2967dab1 MD |
479 | goto out_err; |
480 | ||
481 | switch (cfg_mode) { | |
482 | case GPIO_CFG_DRYRUN: | |
18925e11 | 483 | if (!*cntp || |
b3c185a7 | 484 | (read_config_reg(pfc, cr, field) != value)) |
2967dab1 MD |
485 | continue; |
486 | break; | |
487 | ||
488 | case GPIO_CFG_REQ: | |
b3c185a7 | 489 | write_config_reg(pfc, cr, field, value); |
2967dab1 MD |
490 | *cntp = *cntp + 1; |
491 | break; | |
492 | ||
493 | case GPIO_CFG_FREE: | |
494 | *cntp = *cntp - 1; | |
495 | break; | |
496 | } | |
497 | } | |
498 | ||
499 | return 0; | |
500 | out_err: | |
501 | return -1; | |
502 | } | |
b3c185a7 | 503 | EXPORT_SYMBOL_GPL(sh_pfc_config_gpio); |
2967dab1 | 504 | |
b3c185a7 | 505 | int register_sh_pfc(struct sh_pfc *pfc) |
2967dab1 | 506 | { |
b3c185a7 | 507 | int (*initroutine)(struct sh_pfc *) = NULL; |
0fc64cc0 | 508 | int ret; |
2967dab1 | 509 | |
06d5631f PM |
510 | /* |
511 | * Ensure that the type encoding fits | |
512 | */ | |
513 | BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1)); | |
514 | ||
b3c185a7 PM |
515 | if (sh_pfc) |
516 | return -EBUSY; | |
2967dab1 | 517 | |
b3c185a7 PM |
518 | ret = pfc_ioremap(pfc); |
519 | if (unlikely(ret < 0)) | |
b0e10211 MD |
520 | return ret; |
521 | ||
b3c185a7 | 522 | spin_lock_init(&pfc->lock); |
69edbba0 | 523 | |
ca5481c6 | 524 | pinctrl_provide_dummies(); |
b3c185a7 | 525 | setup_data_regs(pfc); |
69edbba0 | 526 | |
b3c185a7 | 527 | sh_pfc = pfc; |
b0e10211 | 528 | |
ca5481c6 PM |
529 | /* |
530 | * Initialize pinctrl bindings first | |
531 | */ | |
532 | initroutine = symbol_request(sh_pfc_register_pinctrl); | |
533 | if (initroutine) { | |
534 | ret = (*initroutine)(pfc); | |
535 | symbol_put_addr(initroutine); | |
536 | ||
537 | if (unlikely(ret != 0)) | |
538 | goto err; | |
159ac073 PM |
539 | } else { |
540 | pr_err("failed to initialize pinctrl bindings\n"); | |
541 | goto err; | |
ca5481c6 PM |
542 | } |
543 | ||
544 | /* | |
545 | * Then the GPIO chip | |
546 | */ | |
b3c185a7 PM |
547 | initroutine = symbol_request(sh_pfc_register_gpiochip); |
548 | if (initroutine) { | |
ca5481c6 | 549 | ret = (*initroutine)(pfc); |
b3c185a7 | 550 | symbol_put_addr(initroutine); |
ca5481c6 PM |
551 | |
552 | /* | |
553 | * If the GPIO chip fails to come up we still leave the | |
554 | * PFC state as it is, given that there are already | |
555 | * extant users of it that have succeeded by this point. | |
556 | */ | |
557 | if (unlikely(ret != 0)) { | |
558 | pr_notice("failed to init GPIO chip, ignoring...\n"); | |
559 | ret = 0; | |
560 | } | |
b3c185a7 | 561 | } |
b72421d8 | 562 | |
ca5481c6 PM |
563 | pr_info("%s support registered\n", pfc->name); |
564 | ||
b3c185a7 | 565 | return 0; |
ca5481c6 PM |
566 | |
567 | err: | |
568 | pfc_iounmap(pfc); | |
569 | sh_pfc = NULL; | |
570 | ||
571 | return ret; | |
b72421d8 | 572 | } |