]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/soc/fsl/qbman/qman.c
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
soc/fsl/qbman: add QMAN_REV32
[mirror_ubuntu-eoan-kernel.git] / drivers / soc / fsl / qbman / qman.c
CommitLineData
c535e923
CM		 1/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Freescale Semiconductor nor the
11 * names of its contributors may be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * ALTERNATIVELY, this software may be distributed under the terms of the
15 * GNU General Public License ("GPL") as published by the Free Software
16 * Foundation, either version 2 of that License or (at your option) any
17 * later version.
18 *
19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include "qman_priv.h"
32
33#define DQRR_MAXFILL 15
34#define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */
35#define IRQNAME "QMan portal %d"
36#define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
37#define QMAN_POLL_LIMIT 32
38#define QMAN_PIRQ_DQRR_ITHRESH 12
39#define QMAN_PIRQ_MR_ITHRESH 4
40#define QMAN_PIRQ_IPERIOD 100
41
42/* Portal register assists */
43
44/* Cache-inhibited register offsets */
45#define QM_REG_EQCR_PI_CINH 0x0000
46#define QM_REG_EQCR_CI_CINH 0x0004
47#define QM_REG_EQCR_ITR 0x0008
48#define QM_REG_DQRR_PI_CINH 0x0040
49#define QM_REG_DQRR_CI_CINH 0x0044
50#define QM_REG_DQRR_ITR 0x0048
51#define QM_REG_DQRR_DCAP 0x0050
52#define QM_REG_DQRR_SDQCR 0x0054
53#define QM_REG_DQRR_VDQCR 0x0058
54#define QM_REG_DQRR_PDQCR 0x005c
55#define QM_REG_MR_PI_CINH 0x0080
56#define QM_REG_MR_CI_CINH 0x0084
57#define QM_REG_MR_ITR 0x0088
58#define QM_REG_CFG 0x0100
59#define QM_REG_ISR 0x0e00
60#define QM_REG_IER 0x0e04
61#define QM_REG_ISDR 0x0e08
62#define QM_REG_IIR 0x0e0c
63#define QM_REG_ITPR 0x0e14
64
65/* Cache-enabled register offsets */
66#define QM_CL_EQCR 0x0000
67#define QM_CL_DQRR 0x1000
68#define QM_CL_MR 0x2000
69#define QM_CL_EQCR_PI_CENA 0x3000
70#define QM_CL_EQCR_CI_CENA 0x3100
71#define QM_CL_DQRR_PI_CENA 0x3200
72#define QM_CL_DQRR_CI_CENA 0x3300
73#define QM_CL_MR_PI_CENA 0x3400
74#define QM_CL_MR_CI_CENA 0x3500
75#define QM_CL_CR 0x3800
76#define QM_CL_RR0 0x3900
77#define QM_CL_RR1 0x3940
78
79/*
80 * BTW, the drivers (and h/w programming model) already obtain the required
81 * synchronisation for portal accesses and data-dependencies. Use of barrier()s
82 * or other order-preserving primitives simply degrade performance. Hence the
83 * use of the __raw_*() interfaces, which simply ensure that the compiler treats
84 * the portal registers as volatile
85 */
86
87/* Cache-enabled ring access */
88#define qm_cl(base, idx) ((void *)base + ((idx) << 6))
89
90/*
91 * Portal modes.
92 * Enum types;
93 * pmode == production mode
94 * cmode == consumption mode,
95 * dmode == h/w dequeue mode.
96 * Enum values use 3 letter codes. First letter matches the portal mode,
97 * remaining two letters indicate;
98 * ci == cache-inhibited portal register
99 * ce == cache-enabled portal register
100 * vb == in-band valid-bit (cache-enabled)
101 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
102 * As for "enum qm_dqrr_dmode", it should be self-explanatory.
103 */
104enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
105 qm_eqcr_pci = 0, /* PI index, cache-inhibited */
106 qm_eqcr_pce = 1, /* PI index, cache-enabled */
107 qm_eqcr_pvb = 2 /* valid-bit */
108};
109enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
110 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
111 qm_dqrr_dpull = 1 /* PDQCR */
112};
113enum qm_dqrr_pmode { /* s/w-only */
114 qm_dqrr_pci, /* reads DQRR_PI_CINH */
115 qm_dqrr_pce, /* reads DQRR_PI_CENA */
116 qm_dqrr_pvb /* reads valid-bit */
117};
118enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
119 qm_dqrr_cci = 0, /* CI index, cache-inhibited */
120 qm_dqrr_cce = 1, /* CI index, cache-enabled */
121 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
122};
123enum qm_mr_pmode { /* s/w-only */
124 qm_mr_pci, /* reads MR_PI_CINH */
125 qm_mr_pce, /* reads MR_PI_CENA */
126 qm_mr_pvb /* reads valid-bit */
127};
128enum qm_mr_cmode { /* matches QCSP_CFG::MM */
129 qm_mr_cci = 0, /* CI index, cache-inhibited */
130 qm_mr_cce = 1 /* CI index, cache-enabled */
131};
132
133/* --- Portal structures --- */
134
135#define QM_EQCR_SIZE 8
136#define QM_DQRR_SIZE 16
137#define QM_MR_SIZE 8
138
139/* "Enqueue Command" */
140struct qm_eqcr_entry {
141 u8 _ncw_verb; /* writes to this are non-coherent */
142 u8 dca;
18058822 143 __be16 seqnum;
b5399452 144 u8 __reserved[4];
18058822
CM		 145 __be32 fqid; /* 24-bit */
146 __be32 tag;
c535e923
CM		 147 struct qm_fd fd;
148 u8 __reserved3[32];
149} __packed;
150#define QM_EQCR_VERB_VBIT 0x80
151#define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
152#define QM_EQCR_VERB_CMD_ENQUEUE 0x01
153#define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
154#define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
155#define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
156
157struct qm_eqcr {
158 struct qm_eqcr_entry *ring, *cursor;
159 u8 ci, available, ithresh, vbit;
160#ifdef CONFIG_FSL_DPAA_CHECKING
161 u32 busy;
162 enum qm_eqcr_pmode pmode;
163#endif
164};
165
166struct qm_dqrr {
167 const struct qm_dqrr_entry *ring, *cursor;
168 u8 pi, ci, fill, ithresh, vbit;
169#ifdef CONFIG_FSL_DPAA_CHECKING
170 enum qm_dqrr_dmode dmode;
171 enum qm_dqrr_pmode pmode;
172 enum qm_dqrr_cmode cmode;
173#endif
174};
175
176struct qm_mr {
177 union qm_mr_entry *ring, *cursor;
178 u8 pi, ci, fill, ithresh, vbit;
179#ifdef CONFIG_FSL_DPAA_CHECKING
180 enum qm_mr_pmode pmode;
181 enum qm_mr_cmode cmode;
182#endif
183};
184
185/* MC (Management Command) command */
7ff07da0
CM		 186/* "FQ" command layout */
187struct qm_mcc_fq {
c535e923
CM		 188 u8 _ncw_verb;
189 u8 __reserved1[3];
18058822 190 __be32 fqid; /* 24-bit */
c535e923
CM		 191 u8 __reserved2[56];
192} __packed;
c535e923 193
7ff07da0
CM		 194/* "CGR" command layout */
195struct qm_mcc_cgr {
c535e923
CM		 196 u8 _ncw_verb;
197 u8 __reserved1[30];
198 u8 cgid;
199 u8 __reserved2[32];
200};
201
c535e923
CM		 202#define QM_MCC_VERB_VBIT 0x80
203#define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
204#define QM_MCC_VERB_INITFQ_PARKED 0x40
205#define QM_MCC_VERB_INITFQ_SCHED 0x41
206#define QM_MCC_VERB_QUERYFQ 0x44
207#define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
208#define QM_MCC_VERB_QUERYWQ 0x46
209#define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
210#define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
211#define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
212#define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
213#define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
214#define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
215#define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
216#define QM_MCC_VERB_INITCGR 0x50
217#define QM_MCC_VERB_MODIFYCGR 0x51
218#define QM_MCC_VERB_CGRTESTWRITE 0x52
219#define QM_MCC_VERB_QUERYCGR 0x58
220#define QM_MCC_VERB_QUERYCONGESTION 0x59
221union qm_mc_command {
222 struct {
223 u8 _ncw_verb; /* writes to this are non-coherent */
224 u8 __reserved[63];
225 };
226 struct qm_mcc_initfq initfq;
c535e923 227 struct qm_mcc_initcgr initcgr;
7ff07da0
CM		 228 struct qm_mcc_fq fq;
229 struct qm_mcc_cgr cgr;
c535e923
CM		 230};
231
232/* MC (Management Command) result */
233/* "Query FQ" */
234struct qm_mcr_queryfq {
235 u8 verb;
236 u8 result;
237 u8 __reserved1[8];
238 struct qm_fqd fqd; /* the FQD fields are here */
239 u8 __reserved2[30];
240} __packed;
241
242/* "Alter FQ State Commands" */
243struct qm_mcr_alterfq {
244 u8 verb;
245 u8 result;
246 u8 fqs; /* Frame Queue Status */
247 u8 __reserved1[61];
248};
249#define QM_MCR_VERB_RRID 0x80
250#define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
251#define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
252#define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
253#define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
254#define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
255#define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
256#define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
257#define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
258#define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
259#define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
260#define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
261#define QM_MCR_RESULT_NULL 0x00
262#define QM_MCR_RESULT_OK 0xf0
263#define QM_MCR_RESULT_ERR_FQID 0xf1
264#define QM_MCR_RESULT_ERR_FQSTATE 0xf2
265#define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
266#define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
267#define QM_MCR_RESULT_PENDING 0xf8
268#define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
269#define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
270#define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
271#define QM_MCR_TIMEOUT 10000 /* us */
272union qm_mc_result {
273 struct {
274 u8 verb;
275 u8 result;
276 u8 __reserved1[62];
277 };
278 struct qm_mcr_queryfq queryfq;
279 struct qm_mcr_alterfq alterfq;
280 struct qm_mcr_querycgr querycgr;
281 struct qm_mcr_querycongestion querycongestion;
282 struct qm_mcr_querywq querywq;
283 struct qm_mcr_queryfq_np queryfq_np;
284};
285
286struct qm_mc {
287 union qm_mc_command *cr;
288 union qm_mc_result *rr;
289 u8 rridx, vbit;
290#ifdef CONFIG_FSL_DPAA_CHECKING
291 enum {
292 /* Can be _mc_start()ed */
293 qman_mc_idle,
294 /* Can be _mc_commit()ed or _mc_abort()ed */
295 qman_mc_user,
296 /* Can only be _mc_retry()ed */
297 qman_mc_hw
298 } state;
299#endif
300};
301
302struct qm_addr {
e6e2df69
RP		 303 void *ce; /* cache-enabled */
304 __be32 *ce_be; /* same value as above but for direct access */
c535e923
CM		 305 void __iomem *ci; /* cache-inhibited */
306};
307
308struct qm_portal {
309 /*
310 * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to
311 * and including 'mc' fits within a cacheline (yay!). The 'config' part
312 * is setup-only, so isn't a cause for a concern. In other words, don't
313 * rearrange this structure on a whim, there be dragons ...
314 */
315 struct qm_addr addr;
316 struct qm_eqcr eqcr;
317 struct qm_dqrr dqrr;
318 struct qm_mr mr;
319 struct qm_mc mc;
320} ____cacheline_aligned;
321
322/* Cache-inhibited register access. */
323static inline u32 qm_in(struct qm_portal *p, u32 offset)
324{
e6e2df69 325 return ioread32be(p->addr.ci + offset);
c535e923
CM		 326}
327
328static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)
329{
e6e2df69 330 iowrite32be(val, p->addr.ci + offset);
c535e923
CM		 331}
332
333/* Cache Enabled Portal Access */
334static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset)
335{
336 dpaa_invalidate(p->addr.ce + offset);
337}
338
339static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)
340{
341 dpaa_touch_ro(p->addr.ce + offset);
342}
343
344static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)
345{
e6e2df69 346 return be32_to_cpu(*(p->addr.ce_be + (offset/4)));
c535e923
CM		 347}
348
349/* --- EQCR API --- */
350
351#define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry))
352#define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT)
353
354/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
355static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p)
356{
357 uintptr_t addr = (uintptr_t)p;
358
359 addr &= ~EQCR_CARRY;
360
361 return (struct qm_eqcr_entry *)addr;
362}
363
364/* Bit-wise logic to convert a ring pointer to a ring index */
365static int eqcr_ptr2idx(struct qm_eqcr_entry *e)
366{
367 return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1);
368}
369
370/* Increment the 'cursor' ring pointer, taking 'vbit' into account */
371static inline void eqcr_inc(struct qm_eqcr *eqcr)
372{
373 /* increment to the next EQCR pointer and handle overflow and 'vbit' */
374 struct qm_eqcr_entry *partial = eqcr->cursor + 1;
375
376 eqcr->cursor = eqcr_carryclear(partial);
377 if (partial != eqcr->cursor)
378 eqcr->vbit ^= QM_EQCR_VERB_VBIT;
379}
380
381static inline int qm_eqcr_init(struct qm_portal *portal,
382 enum qm_eqcr_pmode pmode,
383 unsigned int eq_stash_thresh,
384 int eq_stash_prio)
385{
386 struct qm_eqcr *eqcr = &portal->eqcr;
387 u32 cfg;
388 u8 pi;
389
390 eqcr->ring = portal->addr.ce + QM_CL_EQCR;
391 eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
392 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
393 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
394 eqcr->cursor = eqcr->ring + pi;
395 eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ?
396 QM_EQCR_VERB_VBIT : 0;
397 eqcr->available = QM_EQCR_SIZE - 1 -
398 dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
399 eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR);
400#ifdef CONFIG_FSL_DPAA_CHECKING
401 eqcr->busy = 0;
402 eqcr->pmode = pmode;
403#endif
404 cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) |
405 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
406 (eq_stash_prio << 26) | /* QCSP_CFG: EP */
407 ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */
408 qm_out(portal, QM_REG_CFG, cfg);
409 return 0;
410}
411
412static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal)
413{
414 return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7;
415}
416
417static inline void qm_eqcr_finish(struct qm_portal *portal)
418{
419 struct qm_eqcr *eqcr = &portal->eqcr;
420 u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
421 u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
422
423 DPAA_ASSERT(!eqcr->busy);
424 if (pi != eqcr_ptr2idx(eqcr->cursor))
57907a73 425 pr_crit("losing uncommitted EQCR entries\n");
c535e923
CM		 426 if (ci != eqcr->ci)
427 pr_crit("missing existing EQCR completions\n");
428 if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
429 pr_crit("EQCR destroyed unquiesced\n");
430}
431
432static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
433 *portal)
434{
435 struct qm_eqcr *eqcr = &portal->eqcr;
436
437 DPAA_ASSERT(!eqcr->busy);
438 if (!eqcr->available)
439 return NULL;
440
441#ifdef CONFIG_FSL_DPAA_CHECKING
442 eqcr->busy = 1;
443#endif
444 dpaa_zero(eqcr->cursor);
445 return eqcr->cursor;
446}
447
448static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
449 *portal)
450{
451 struct qm_eqcr *eqcr = &portal->eqcr;
452 u8 diff, old_ci;
453
454 DPAA_ASSERT(!eqcr->busy);
455 if (!eqcr->available) {
456 old_ci = eqcr->ci;
457 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) &
458 (QM_EQCR_SIZE - 1);
459 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
460 eqcr->available += diff;
461 if (!diff)
462 return NULL;
463 }
464#ifdef CONFIG_FSL_DPAA_CHECKING
465 eqcr->busy = 1;
466#endif
467 dpaa_zero(eqcr->cursor);
468 return eqcr->cursor;
469}
470
471static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
472{
473 DPAA_ASSERT(eqcr->busy);
18058822 474 DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK));
c535e923
CM		 475 DPAA_ASSERT(eqcr->available >= 1);
476}
477
478static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
479{
480 struct qm_eqcr *eqcr = &portal->eqcr;
481 struct qm_eqcr_entry *eqcursor;
482
483 eqcr_commit_checks(eqcr);
484 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
485 dma_wmb();
486 eqcursor = eqcr->cursor;
487 eqcursor->_ncw_verb = myverb | eqcr->vbit;
488 dpaa_flush(eqcursor);
489 eqcr_inc(eqcr);
490 eqcr->available--;
491#ifdef CONFIG_FSL_DPAA_CHECKING
492 eqcr->busy = 0;
493#endif
494}
495
496static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
497{
498 qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA);
499}
500
501static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
502{
503 struct qm_eqcr *eqcr = &portal->eqcr;
504 u8 diff, old_ci = eqcr->ci;
505
506 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1);
507 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
508 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
509 eqcr->available += diff;
510 return diff;
511}
512
513static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
514{
515 struct qm_eqcr *eqcr = &portal->eqcr;
516
517 eqcr->ithresh = ithresh;
518 qm_out(portal, QM_REG_EQCR_ITR, ithresh);
519}
520
521static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
522{
523 struct qm_eqcr *eqcr = &portal->eqcr;
524
525 return eqcr->available;
526}
527
528static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
529{
530 struct qm_eqcr *eqcr = &portal->eqcr;
531
532 return QM_EQCR_SIZE - 1 - eqcr->available;
533}
534
535/* --- DQRR API --- */
536
537#define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry))
538#define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT)
539
540static const struct qm_dqrr_entry *dqrr_carryclear(
541 const struct qm_dqrr_entry *p)
542{
543 uintptr_t addr = (uintptr_t)p;
544
545 addr &= ~DQRR_CARRY;
546
547 return (const struct qm_dqrr_entry *)addr;
548}
549
550static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e)
551{
552 return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1);
553}
554
555static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e)
556{
557 return dqrr_carryclear(e + 1);
558}
559
560static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
561{
562 qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) |
563 ((mf & (QM_DQRR_SIZE - 1)) << 20));
564}
565
566static inline int qm_dqrr_init(struct qm_portal *portal,
567 const struct qm_portal_config *config,
568 enum qm_dqrr_dmode dmode,
569 enum qm_dqrr_pmode pmode,
570 enum qm_dqrr_cmode cmode, u8 max_fill)
571{
572 struct qm_dqrr *dqrr = &portal->dqrr;
573 u32 cfg;
574
575 /* Make sure the DQRR will be idle when we enable */
576 qm_out(portal, QM_REG_DQRR_SDQCR, 0);
577 qm_out(portal, QM_REG_DQRR_VDQCR, 0);
578 qm_out(portal, QM_REG_DQRR_PDQCR, 0);
579 dqrr->ring = portal->addr.ce + QM_CL_DQRR;
580 dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
581 dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
582 dqrr->cursor = dqrr->ring + dqrr->ci;
583 dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
584 dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ?
585 QM_DQRR_VERB_VBIT : 0;
586 dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR);
587#ifdef CONFIG_FSL_DPAA_CHECKING
588 dqrr->dmode = dmode;
589 dqrr->pmode = pmode;
590 dqrr->cmode = cmode;
591#endif
592 /* Invalidate every ring entry before beginning */
593 for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
594 dpaa_invalidate(qm_cl(dqrr->ring, cfg));
595 cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) |
596 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
597 ((dmode & 1) << 18) | /* DP */
598 ((cmode & 3) << 16) | /* DCM */
599 0xa0 | /* RE+SE */
600 (0 ? 0x40 : 0) | /* Ignore RP */
601 (0 ? 0x10 : 0); /* Ignore SP */
602 qm_out(portal, QM_REG_CFG, cfg);
603 qm_dqrr_set_maxfill(portal, max_fill);
604 return 0;
605}
606
607static inline void qm_dqrr_finish(struct qm_portal *portal)
608{
609#ifdef CONFIG_FSL_DPAA_CHECKING
610 struct qm_dqrr *dqrr = &portal->dqrr;
611
612 if (dqrr->cmode != qm_dqrr_cdc &&
613 dqrr->ci != dqrr_ptr2idx(dqrr->cursor))
614 pr_crit("Ignoring completed DQRR entries\n");
615#endif
616}
617
618static inline const struct qm_dqrr_entry *qm_dqrr_current(
619 struct qm_portal *portal)
620{
621 struct qm_dqrr *dqrr = &portal->dqrr;
622
623 if (!dqrr->fill)
624 return NULL;
625 return dqrr->cursor;
626}
627
628static inline u8 qm_dqrr_next(struct qm_portal *portal)
629{
630 struct qm_dqrr *dqrr = &portal->dqrr;
631
632 DPAA_ASSERT(dqrr->fill);
633 dqrr->cursor = dqrr_inc(dqrr->cursor);
634 return --dqrr->fill;
635}
636
637static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
638{
639 struct qm_dqrr *dqrr = &portal->dqrr;
640 struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
641
642 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
643#ifndef CONFIG_FSL_PAMU
644 /*
645 * If PAMU is not available we need to invalidate the cache.
646 * When PAMU is available the cache is updated by stash
647 */
648 dpaa_invalidate_touch_ro(res);
649#endif
e6e2df69 650 if ((res->verb & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
c535e923
CM		 651 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
652 if (!dqrr->pi)
653 dqrr->vbit ^= QM_DQRR_VERB_VBIT;
654 dqrr->fill++;
655 }
656}
657
658static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
659 const struct qm_dqrr_entry *dq,
660 int park)
661{
662 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
663 int idx = dqrr_ptr2idx(dq);
664
665 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
666 DPAA_ASSERT((dqrr->ring + idx) == dq);
667 DPAA_ASSERT(idx < QM_DQRR_SIZE);
668 qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
669 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
670 idx); /* DQRR_DCAP::DCAP_CI */
671}
672
673static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask)
674{
675 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
676
677 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
678 qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
679 (bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
680}
681
682static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
683{
684 qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr);
685}
686
687static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
688{
689 qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr);
690}
691
692static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
693{
694 qm_out(portal, QM_REG_DQRR_ITR, ithresh);
695}
696
697/* --- MR API --- */
698
699#define MR_SHIFT ilog2(sizeof(union qm_mr_entry))
700#define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT)
701
702static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p)
703{
704 uintptr_t addr = (uintptr_t)p;
705
706 addr &= ~MR_CARRY;
707
708 return (union qm_mr_entry *)addr;
709}
710
711static inline int mr_ptr2idx(const union qm_mr_entry *e)
712{
713 return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1);
714}
715
716static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e)
717{
718 return mr_carryclear(e + 1);
719}
720
721static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode,
722 enum qm_mr_cmode cmode)
723{
724 struct qm_mr *mr = &portal->mr;
725 u32 cfg;
726
727 mr->ring = portal->addr.ce + QM_CL_MR;
728 mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1);
729 mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1);
730 mr->cursor = mr->ring + mr->ci;
731 mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
732 mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE)
733 ? QM_MR_VERB_VBIT : 0;
734 mr->ithresh = qm_in(portal, QM_REG_MR_ITR);
735#ifdef CONFIG_FSL_DPAA_CHECKING
736 mr->pmode = pmode;
737 mr->cmode = cmode;
738#endif
739 cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) |
740 ((cmode & 1) << 8); /* QCSP_CFG:MM */
741 qm_out(portal, QM_REG_CFG, cfg);
742 return 0;
743}
744
745static inline void qm_mr_finish(struct qm_portal *portal)
746{
747 struct qm_mr *mr = &portal->mr;
748
749 if (mr->ci != mr_ptr2idx(mr->cursor))
750 pr_crit("Ignoring completed MR entries\n");
751}
752
753static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal)
754{
755 struct qm_mr *mr = &portal->mr;
756
757 if (!mr->fill)
758 return NULL;
759 return mr->cursor;
760}
761
762static inline int qm_mr_next(struct qm_portal *portal)
763{
764 struct qm_mr *mr = &portal->mr;
765
766 DPAA_ASSERT(mr->fill);
767 mr->cursor = mr_inc(mr->cursor);
768 return --mr->fill;
769}
770
771static inline void qm_mr_pvb_update(struct qm_portal *portal)
772{
773 struct qm_mr *mr = &portal->mr;
774 union qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
775
776 DPAA_ASSERT(mr->pmode == qm_mr_pvb);
e6e2df69
RP		 777
778 if ((res->verb & QM_MR_VERB_VBIT) == mr->vbit) {
c535e923
CM		 779 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
780 if (!mr->pi)
781 mr->vbit ^= QM_MR_VERB_VBIT;
782 mr->fill++;
783 res = mr_inc(res);
784 }
785 dpaa_invalidate_touch_ro(res);
786}
787
788static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
789{
790 struct qm_mr *mr = &portal->mr;
791
792 DPAA_ASSERT(mr->cmode == qm_mr_cci);
793 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
794 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
795}
796
797static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
798{
799 struct qm_mr *mr = &portal->mr;
800
801 DPAA_ASSERT(mr->cmode == qm_mr_cci);
802 mr->ci = mr_ptr2idx(mr->cursor);
803 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
804}
805
806static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
807{
808 qm_out(portal, QM_REG_MR_ITR, ithresh);
809}
810
811/* --- Management command API --- */
812
813static inline int qm_mc_init(struct qm_portal *portal)
814{
815 struct qm_mc *mc = &portal->mc;
816
817 mc->cr = portal->addr.ce + QM_CL_CR;
818 mc->rr = portal->addr.ce + QM_CL_RR0;
e6e2df69 819 mc->rridx = (mc->cr->_ncw_verb & QM_MCC_VERB_VBIT)
c535e923
CM		 820 ? 0 : 1;
821 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
822#ifdef CONFIG_FSL_DPAA_CHECKING
823 mc->state = qman_mc_idle;
824#endif
825 return 0;
826}
827
828static inline void qm_mc_finish(struct qm_portal *portal)
829{
830#ifdef CONFIG_FSL_DPAA_CHECKING
831 struct qm_mc *mc = &portal->mc;
832
833 DPAA_ASSERT(mc->state == qman_mc_idle);
834 if (mc->state != qman_mc_idle)
835 pr_crit("Losing incomplete MC command\n");
836#endif
837}
838
839static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal)
840{
841 struct qm_mc *mc = &portal->mc;
842
843 DPAA_ASSERT(mc->state == qman_mc_idle);
844#ifdef CONFIG_FSL_DPAA_CHECKING
845 mc->state = qman_mc_user;
846#endif
847 dpaa_zero(mc->cr);
848 return mc->cr;
849}
850
851static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
852{
853 struct qm_mc *mc = &portal->mc;
854 union qm_mc_result *rr = mc->rr + mc->rridx;
855
856 DPAA_ASSERT(mc->state == qman_mc_user);
857 dma_wmb();
858 mc->cr->_ncw_verb = myverb | mc->vbit;
859 dpaa_flush(mc->cr);
860 dpaa_invalidate_touch_ro(rr);
861#ifdef CONFIG_FSL_DPAA_CHECKING
862 mc->state = qman_mc_hw;
863#endif
864}
865
866static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)
867{
868 struct qm_mc *mc = &portal->mc;
869 union qm_mc_result *rr = mc->rr + mc->rridx;
870
871 DPAA_ASSERT(mc->state == qman_mc_hw);
872 /*
873 * The inactive response register's verb byte always returns zero until
874 * its command is submitted and completed. This includes the valid-bit,
875 * in case you were wondering...
876 */
e6e2df69 877 if (!rr->verb) {
c535e923
CM		 878 dpaa_invalidate_touch_ro(rr);
879 return NULL;
880 }
881 mc->rridx ^= 1;
882 mc->vbit ^= QM_MCC_VERB_VBIT;
883#ifdef CONFIG_FSL_DPAA_CHECKING
884 mc->state = qman_mc_idle;
885#endif
886 return rr;
887}
888
889static inline int qm_mc_result_timeout(struct qm_portal *portal,
890 union qm_mc_result **mcr)
891{
892 int timeout = QM_MCR_TIMEOUT;
893
894 do {
895 *mcr = qm_mc_result(portal);
896 if (*mcr)
897 break;
898 udelay(1);
899 } while (--timeout);
900
901 return timeout;
902}
903
904static inline void fq_set(struct qman_fq *fq, u32 mask)
905{
f5bd2299 906 fq->flags |= mask;
c535e923
CM		 907}
908
909static inline void fq_clear(struct qman_fq *fq, u32 mask)
910{
f5bd2299 911 fq->flags &= ~mask;
c535e923
CM		 912}
913
914static inline int fq_isset(struct qman_fq *fq, u32 mask)
915{
916 return fq->flags & mask;
917}
918
919static inline int fq_isclear(struct qman_fq *fq, u32 mask)
920{
921 return !(fq->flags & mask);
922}
923
924struct qman_portal {
925 struct qm_portal p;
926 /* PORTAL_BITS_*** - dynamic, strictly internal */
927 unsigned long bits;
928 /* interrupt sources processed by portal_isr(), configurable */
929 unsigned long irq_sources;
930 u32 use_eqcr_ci_stashing;
931 /* only 1 volatile dequeue at a time */
932 struct qman_fq *vdqcr_owned;
933 u32 sdqcr;
934 /* probing time config params for cpu-affine portals */
935 const struct qm_portal_config *config;
c535e923
CM		 936 /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
937 struct qman_cgrs *cgrs;
938 /* linked-list of CSCN handlers. */
939 struct list_head cgr_cbs;
940 /* list lock */
941 spinlock_t cgr_lock;
942 struct work_struct congestion_work;
943 struct work_struct mr_work;
944 char irqname[MAX_IRQNAME];
945};
946
947static cpumask_t affine_mask;
948static DEFINE_SPINLOCK(affine_mask_lock);
949static u16 affine_channels[NR_CPUS];
950static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal);
951struct qman_portal *affine_portals[NR_CPUS];
952
953static inline struct qman_portal *get_affine_portal(void)
954{
955 return &get_cpu_var(qman_affine_portal);
956}
957
958static inline void put_affine_portal(void)
959{
960 put_cpu_var(qman_affine_portal);
961}
962
963static struct workqueue_struct *qm_portal_wq;
964
965int qman_wq_alloc(void)
966{
967 qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1);
968 if (!qm_portal_wq)
969 return -ENOMEM;
970 return 0;
971}
972
973/*
974 * This is what everything can wait on, even if it migrates to a different cpu
975 * to the one whose affine portal it is waiting on.
976 */
977static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
978
979static struct qman_fq **fq_table;
980static u32 num_fqids;
981
982int qman_alloc_fq_table(u32 _num_fqids)
983{
984 num_fqids = _num_fqids;
985
986 fq_table = vzalloc(num_fqids * 2 * sizeof(struct qman_fq *));
987 if (!fq_table)
988 return -ENOMEM;
989
990 pr_debug("Allocated fq lookup table at %p, entry count %u\n",
991 fq_table, num_fqids * 2);
992 return 0;
993}
994
995static struct qman_fq *idx_to_fq(u32 idx)
996{
997 struct qman_fq *fq;
998
999#ifdef CONFIG_FSL_DPAA_CHECKING
1000 if (WARN_ON(idx >= num_fqids * 2))
1001 return NULL;
1002#endif
1003 fq = fq_table[idx];
1004 DPAA_ASSERT(!fq || idx == fq->idx);
1005
1006 return fq;
1007}
1008
1009/*
1010 * Only returns full-service fq objects, not enqueue-only
1011 * references (QMAN_FQ_FLAG_NO_MODIFY).
1012 */
1013static struct qman_fq *fqid_to_fq(u32 fqid)
1014{
1015 return idx_to_fq(fqid * 2);
1016}
1017
1018static struct qman_fq *tag_to_fq(u32 tag)
1019{
1020#if BITS_PER_LONG == 64
1021 return idx_to_fq(tag);
1022#else
1023 return (struct qman_fq *)tag;
1024#endif
1025}
1026
1027static u32 fq_to_tag(struct qman_fq *fq)
1028{
1029#if BITS_PER_LONG == 64
1030 return fq->idx;
1031#else
1032 return (u32)fq;
1033#endif
1034}
1035
1036static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
1037static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1038 unsigned int poll_limit);
1039static void qm_congestion_task(struct work_struct *work);
1040static void qm_mr_process_task(struct work_struct *work);
1041
1042static irqreturn_t portal_isr(int irq, void *ptr)
1043{
1044 struct qman_portal *p = ptr;
1045
1046 u32 clear = QM_DQAVAIL_MASK | p->irq_sources;
1047 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources;
1048
1049 if (unlikely(!is))
1050 return IRQ_NONE;
1051
1052 /* DQRR-handling if it's interrupt-driven */
1053 if (is & QM_PIRQ_DQRI)
1054 __poll_portal_fast(p, QMAN_POLL_LIMIT);
1055 /* Handling of anything else that's interrupt-driven */
1056 clear |= __poll_portal_slow(p, is);
1057 qm_out(&p->p, QM_REG_ISR, clear);
1058 return IRQ_HANDLED;
1059}
1060
1061static int drain_mr_fqrni(struct qm_portal *p)
1062{
1063 const union qm_mr_entry *msg;
1064loop:
1065 msg = qm_mr_current(p);
1066 if (!msg) {
1067 /*
1068 * if MR was full and h/w had other FQRNI entries to produce, we
1069 * need to allow it time to produce those entries once the
1070 * existing entries are consumed. A worst-case situation
1071 * (fully-loaded system) means h/w sequencers may have to do 3-4
1072 * other things before servicing the portal's MR pump, each of
1073 * which (if slow) may take ~50 qman cycles (which is ~200
1074 * processor cycles). So rounding up and then multiplying this
1075 * worst-case estimate by a factor of 10, just to be
1076 * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
1077 * one entry at a time, so h/w has an opportunity to produce new
1078 * entries well before the ring has been fully consumed, so
1079 * we're being *really* paranoid here.
1080 */
7ce2e934 1081 msleep(1);
c535e923
CM		 1082 msg = qm_mr_current(p);
1083 if (!msg)
1084 return 0;
1085 }
1086 if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
1087 /* We aren't draining anything but FQRNIs */
1088 pr_err("Found verb 0x%x in MR\n", msg->verb);
1089 return -1;
1090 }
1091 qm_mr_next(p);
1092 qm_mr_cci_consume(p, 1);
1093 goto loop;
1094}
1095
1096static int qman_create_portal(struct qman_portal *portal,
1097 const struct qm_portal_config *c,
1098 const struct qman_cgrs *cgrs)
1099{
1100 struct qm_portal *p;
c535e923
CM		 1101 int ret;
1102 u32 isdr;
1103
1104 p = &portal->p;
1105
1106#ifdef CONFIG_FSL_PAMU
1107 /* PAMU is required for stashing */
1108 portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
1109#else
1110 portal->use_eqcr_ci_stashing = 0;
1111#endif
1112 /*
1113 * prep the low-level portal struct with the mapped addresses from the
1114 * config, everything that follows depends on it and "config" is more
1115 * for (de)reference
1116 */
e6e2df69
RP		 1117 p->addr.ce = c->addr_virt_ce;
1118 p->addr.ce_be = c->addr_virt_ce;
1119 p->addr.ci = c->addr_virt_ci;
c535e923
CM		 1120 /*
1121 * If CI-stashing is used, the current defaults use a threshold of 3,
1122 * and stash with high-than-DQRR priority.
1123 */
1124 if (qm_eqcr_init(p, qm_eqcr_pvb,
1125 portal->use_eqcr_ci_stashing ? 3 : 0, 1)) {
1126 dev_err(c->dev, "EQCR initialisation failed\n");
1127 goto fail_eqcr;
1128 }
1129 if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
1130 qm_dqrr_cdc, DQRR_MAXFILL)) {
1131 dev_err(c->dev, "DQRR initialisation failed\n");
1132 goto fail_dqrr;
1133 }
1134 if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
1135 dev_err(c->dev, "MR initialisation failed\n");
1136 goto fail_mr;
1137 }
1138 if (qm_mc_init(p)) {
1139 dev_err(c->dev, "MC initialisation failed\n");
1140 goto fail_mc;
1141 }
1142 /* static interrupt-gating controls */
1143 qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH);
1144 qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH);
1145 qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD);
1146 portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL);
1147 if (!portal->cgrs)
1148 goto fail_cgrs;
1149 /* initial snapshot is no-depletion */
1150 qman_cgrs_init(&portal->cgrs[1]);
1151 if (cgrs)
1152 portal->cgrs[0] = *cgrs;
1153 else
1154 /* if the given mask is NULL, assume all CGRs can be seen */
1155 qman_cgrs_fill(&portal->cgrs[0]);
1156 INIT_LIST_HEAD(&portal->cgr_cbs);
1157 spin_lock_init(&portal->cgr_lock);
1158 INIT_WORK(&portal->congestion_work, qm_congestion_task);
1159 INIT_WORK(&portal->mr_work, qm_mr_process_task);
1160 portal->bits = 0;
1161 portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
1162 QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
1163 QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
c535e923
CM		 1164 isdr = 0xffffffff;
1165 qm_out(p, QM_REG_ISDR, isdr);
1166 portal->irq_sources = 0;
1167 qm_out(p, QM_REG_IER, 0);
1168 qm_out(p, QM_REG_ISR, 0xffffffff);
1169 snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
1170 if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
1171 dev_err(c->dev, "request_irq() failed\n");
1172 goto fail_irq;
1173 }
1174 if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
1175 irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
1176 dev_err(c->dev, "irq_set_affinity() failed\n");
1177 goto fail_affinity;
1178 }
1179
1180 /* Need EQCR to be empty before continuing */
1181 isdr &= ~QM_PIRQ_EQCI;
1182 qm_out(p, QM_REG_ISDR, isdr);
1183 ret = qm_eqcr_get_fill(p);
1184 if (ret) {
1185 dev_err(c->dev, "EQCR unclean\n");
1186 goto fail_eqcr_empty;
1187 }
1188 isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
1189 qm_out(p, QM_REG_ISDR, isdr);
1190 if (qm_dqrr_current(p)) {
1191 dev_err(c->dev, "DQRR unclean\n");
1192 qm_dqrr_cdc_consume_n(p, 0xffff);
1193 }
1194 if (qm_mr_current(p) && drain_mr_fqrni(p)) {
1195 /* special handling, drain just in case it's a few FQRNIs */
1196 const union qm_mr_entry *e = qm_mr_current(p);
1197
b6e969db
CM		 1198 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x, addr 0x%llx\n",
1199 e->verb, e->ern.rc, qm_fd_addr_get64(&e->ern.fd));
c535e923
CM		 1200 goto fail_dqrr_mr_empty;
1201 }
1202 /* Success */
1203 portal->config = c;
1204 qm_out(p, QM_REG_ISDR, 0);
1205 qm_out(p, QM_REG_IIR, 0);
1206 /* Write a sane SDQCR */
1207 qm_dqrr_sdqcr_set(p, portal->sdqcr);
1208 return 0;
1209
1210fail_dqrr_mr_empty:
1211fail_eqcr_empty:
1212fail_affinity:
1213 free_irq(c->irq, portal);
1214fail_irq:
c535e923
CM		 1215 kfree(portal->cgrs);
1216fail_cgrs:
1217 qm_mc_finish(p);
1218fail_mc:
1219 qm_mr_finish(p);
1220fail_mr:
1221 qm_dqrr_finish(p);
1222fail_dqrr:
1223 qm_eqcr_finish(p);
1224fail_eqcr:
1225 return -EIO;
1226}
1227
1228struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
1229 const struct qman_cgrs *cgrs)
1230{
1231 struct qman_portal *portal;
1232 int err;
1233
1234 portal = &per_cpu(qman_affine_portal, c->cpu);
1235 err = qman_create_portal(portal, c, cgrs);
1236 if (err)
1237 return NULL;
1238
1239 spin_lock(&affine_mask_lock);
1240 cpumask_set_cpu(c->cpu, &affine_mask);
1241 affine_channels[c->cpu] = c->channel;
1242 affine_portals[c->cpu] = portal;
1243 spin_unlock(&affine_mask_lock);
1244
1245 return portal;
1246}
1247
1248static void qman_destroy_portal(struct qman_portal *qm)
1249{
1250 const struct qm_portal_config *pcfg;
1251
1252 /* Stop dequeues on the portal */
1253 qm_dqrr_sdqcr_set(&qm->p, 0);
1254
1255 /*
1256 * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
1257 * something related to QM_PIRQ_EQCI, this may need fixing.
1258 * Also, due to the prefetching model used for CI updates in the enqueue
1259 * path, this update will only invalidate the CI cacheline *after*
1260 * working on it, so we need to call this twice to ensure a full update
1261 * irrespective of where the enqueue processing was at when the teardown
1262 * began.
1263 */
1264 qm_eqcr_cce_update(&qm->p);
1265 qm_eqcr_cce_update(&qm->p);
1266 pcfg = qm->config;
1267
1268 free_irq(pcfg->irq, qm);
1269
1270 kfree(qm->cgrs);
1271 qm_mc_finish(&qm->p);
1272 qm_mr_finish(&qm->p);
1273 qm_dqrr_finish(&qm->p);
1274 qm_eqcr_finish(&qm->p);
1275
c535e923
CM		 1276 qm->config = NULL;
1277}
1278
1279const struct qm_portal_config *qman_destroy_affine_portal(void)
1280{
1281 struct qman_portal *qm = get_affine_portal();
1282 const struct qm_portal_config *pcfg;
1283 int cpu;
1284
1285 pcfg = qm->config;
1286 cpu = pcfg->cpu;
1287
1288 qman_destroy_portal(qm);
1289
1290 spin_lock(&affine_mask_lock);
1291 cpumask_clear_cpu(cpu, &affine_mask);
1292 spin_unlock(&affine_mask_lock);
1293 put_affine_portal();
1294 return pcfg;
1295}
1296
1297/* Inline helper to reduce nesting in __poll_portal_slow() */
1298static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
1299 const union qm_mr_entry *msg, u8 verb)
1300{
1301 switch (verb) {
1302 case QM_MR_VERB_FQRL:
1303 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
1304 fq_clear(fq, QMAN_FQ_STATE_ORL);
1305 break;
1306 case QM_MR_VERB_FQRN:
1307 DPAA_ASSERT(fq->state == qman_fq_state_parked ||
1308 fq->state == qman_fq_state_sched);
1309 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
1310 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
1311 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
1312 fq_set(fq, QMAN_FQ_STATE_NE);
1313 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
1314 fq_set(fq, QMAN_FQ_STATE_ORL);
1315 fq->state = qman_fq_state_retired;
1316 break;
1317 case QM_MR_VERB_FQPN:
1318 DPAA_ASSERT(fq->state == qman_fq_state_sched);
1319 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
1320 fq->state = qman_fq_state_parked;
1321 }
1322}
1323
1324static void qm_congestion_task(struct work_struct *work)
1325{
1326 struct qman_portal *p = container_of(work, struct qman_portal,
1327 congestion_work);
1328 struct qman_cgrs rr, c;
1329 union qm_mc_result *mcr;
1330 struct qman_cgr *cgr;
1331
1332 spin_lock(&p->cgr_lock);
1333 qm_mc_start(&p->p);
1334 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1335 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1336 spin_unlock(&p->cgr_lock);
1337 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
e21c7316 1338 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
c535e923
CM		 1339 return;
1340 }
1341 /* mask out the ones I'm not interested in */
1342 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state,
1343 &p->cgrs[0]);
1344 /* check previous snapshot for delta, enter/exit congestion */
1345 qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
1346 /* update snapshot */
1347 qman_cgrs_cp(&p->cgrs[1], &rr);
1348 /* Invoke callback */
1349 list_for_each_entry(cgr, &p->cgr_cbs, node)
1350 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
1351 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
1352 spin_unlock(&p->cgr_lock);
e21c7316 1353 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
c535e923
CM		 1354}
1355
1356static void qm_mr_process_task(struct work_struct *work)
1357{
1358 struct qman_portal *p = container_of(work, struct qman_portal,
1359 mr_work);
1360 const union qm_mr_entry *msg;
1361 struct qman_fq *fq;
1362 u8 verb, num = 0;
1363
1364 preempt_disable();
1365
1366 while (1) {
1367 qm_mr_pvb_update(&p->p);
1368 msg = qm_mr_current(&p->p);
1369 if (!msg)
1370 break;
1371
1372 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
1373 /* The message is a software ERN iff the 0x20 bit is clear */
1374 if (verb & 0x20) {
1375 switch (verb) {
1376 case QM_MR_VERB_FQRNI:
1377 /* nada, we drop FQRNIs on the floor */
1378 break;
1379 case QM_MR_VERB_FQRN:
1380 case QM_MR_VERB_FQRL:
1381 /* Lookup in the retirement table */
d6753c7e 1382 fq = fqid_to_fq(qm_fqid_get(&msg->fq));
c535e923
CM		 1383 if (WARN_ON(!fq))
1384 break;
1385 fq_state_change(p, fq, msg, verb);
1386 if (fq->cb.fqs)
1387 fq->cb.fqs(p, fq, msg);
1388 break;
1389 case QM_MR_VERB_FQPN:
1390 /* Parked */
18058822 1391 fq = tag_to_fq(be32_to_cpu(msg->fq.context_b));
c535e923
CM		 1392 fq_state_change(p, fq, msg, verb);
1393 if (fq->cb.fqs)
1394 fq->cb.fqs(p, fq, msg);
1395 break;
1396 case QM_MR_VERB_DC_ERN:
1397 /* DCP ERN */
1398 pr_crit_once("Leaking DCP ERNs!\n");
1399 break;
1400 default:
1401 pr_crit("Invalid MR verb 0x%02x\n", verb);
1402 }
1403 } else {
1404 /* Its a software ERN */
18058822 1405 fq = tag_to_fq(be32_to_cpu(msg->ern.tag));
c535e923
CM		 1406 fq->cb.ern(p, fq, msg);
1407 }
1408 num++;
1409 qm_mr_next(&p->p);
1410 }
1411
1412 qm_mr_cci_consume(&p->p, num);
e21c7316 1413 qman_p_irqsource_add(p, QM_PIRQ_MRI);
c535e923
CM		 1414 preempt_enable();
1415}
1416
1417static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
1418{
1419 if (is & QM_PIRQ_CSCI) {
e21c7316 1420 qman_p_irqsource_remove(p, QM_PIRQ_CSCI);
c535e923
CM		 1421 queue_work_on(smp_processor_id(), qm_portal_wq,
1422 &p->congestion_work);
1423 }
1424
1425 if (is & QM_PIRQ_EQRI) {
1426 qm_eqcr_cce_update(&p->p);
1427 qm_eqcr_set_ithresh(&p->p, 0);
1428 wake_up(&affine_queue);
1429 }
1430
1431 if (is & QM_PIRQ_MRI) {
e21c7316 1432 qman_p_irqsource_remove(p, QM_PIRQ_MRI);
c535e923
CM		 1433 queue_work_on(smp_processor_id(), qm_portal_wq,
1434 &p->mr_work);
1435 }
1436
1437 return is;
1438}
1439
1440/*
1441 * remove some slowish-path stuff from the "fast path" and make sure it isn't
1442 * inlined.
1443 */
1444static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
1445{
1446 p->vdqcr_owned = NULL;
1447 fq_clear(fq, QMAN_FQ_STATE_VDQCR);
1448 wake_up(&affine_queue);
1449}
1450
1451/*
1452 * The only states that would conflict with other things if they ran at the
1453 * same time on the same cpu are:
1454 *
1455 * (i) setting/clearing vdqcr_owned, and
1456 * (ii) clearing the NE (Not Empty) flag.
1457 *
1458 * Both are safe. Because;
1459 *
1460 * (i) this clearing can only occur after qman_volatile_dequeue() has set the
1461 * vdqcr_owned field (which it does before setting VDQCR), and
1462 * qman_volatile_dequeue() blocks interrupts and preemption while this is
1463 * done so that we can't interfere.
1464 * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
1465 * with (i) that API prevents us from interfering until it's safe.
1466 *
1467 * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far
1468 * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
1469 * advantage comes from this function not having to "lock" anything at all.
1470 *
1471 * Note also that the callbacks are invoked at points which are safe against the
1472 * above potential conflicts, but that this function itself is not re-entrant
1473 * (this is because the function tracks one end of each FIFO in the portal and
1474 * we do *not* want to lock that). So the consequence is that it is safe for
1475 * user callbacks to call into any QMan API.
1476 */
1477static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1478 unsigned int poll_limit)
1479{
1480 const struct qm_dqrr_entry *dq;
1481 struct qman_fq *fq;
1482 enum qman_cb_dqrr_result res;
1483 unsigned int limit = 0;
1484
1485 do {
1486 qm_dqrr_pvb_update(&p->p);
1487 dq = qm_dqrr_current(&p->p);
1488 if (!dq)
1489 break;
1490
1491 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
1492 /*
efe848cd 1493 * VDQCR: don't trust context_b as the FQ may have
c535e923
CM		 1494 * been configured for h/w consumption and we're
1495 * draining it post-retirement.
1496 */
1497 fq = p->vdqcr_owned;
1498 /*
1499 * We only set QMAN_FQ_STATE_NE when retiring, so we
1500 * only need to check for clearing it when doing
1501 * volatile dequeues. It's one less thing to check
1502 * in the critical path (SDQCR).
1503 */
1504 if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1505 fq_clear(fq, QMAN_FQ_STATE_NE);
1506 /*
1507 * This is duplicated from the SDQCR code, but we
1508 * have stuff to do before *and* after this callback,
1509 * and we don't want multiple if()s in the critical
1510 * path (SDQCR).
1511 */
1512 res = fq->cb.dqrr(p, fq, dq);
1513 if (res == qman_cb_dqrr_stop)
1514 break;
1515 /* Check for VDQCR completion */
1516 if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1517 clear_vdqcr(p, fq);
1518 } else {
efe848cd 1519 /* SDQCR: context_b points to the FQ */
18058822 1520 fq = tag_to_fq(be32_to_cpu(dq->context_b));
c535e923
CM		 1521 /* Now let the callback do its stuff */
1522 res = fq->cb.dqrr(p, fq, dq);
1523 /*
1524 * The callback can request that we exit without
1525 * consuming this entry nor advancing;
1526 */
1527 if (res == qman_cb_dqrr_stop)
1528 break;
1529 }
1530 /* Interpret 'dq' from a driver perspective. */
1531 /*
1532 * Parking isn't possible unless HELDACTIVE was set. NB,
1533 * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1534 * check for HELDACTIVE to cover both.
1535 */
1536 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1537 (res != qman_cb_dqrr_park));
1538 /* just means "skip it, I'll consume it myself later on" */
1539 if (res != qman_cb_dqrr_defer)
1540 qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1541 res == qman_cb_dqrr_park);
1542 /* Move forward */
1543 qm_dqrr_next(&p->p);
1544 /*
1545 * Entry processed and consumed, increment our counter. The
1546 * callback can request that we exit after consuming the
1547 * entry, and we also exit if we reach our processing limit,
1548 * so loop back only if neither of these conditions is met.
1549 */
1550 } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1551
1552 return limit;
1553}
1554
1555void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
1556{
1557 unsigned long irqflags;
1558
1559 local_irq_save(irqflags);
f5bd2299 1560 p->irq_sources |= bits & QM_PIRQ_VISIBLE;
c535e923
CM		 1561 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1562 local_irq_restore(irqflags);
1563}
1564EXPORT_SYMBOL(qman_p_irqsource_add);
1565
1566void qman_p_irqsource_remove(struct qman_portal *p, u32 bits)
1567{
1568 unsigned long irqflags;
1569 u32 ier;
1570
1571 /*
1572 * Our interrupt handler only processes+clears status register bits that
1573 * are in p->irq_sources. As we're trimming that mask, if one of them
1574 * were to assert in the status register just before we remove it from
1575 * the enable register, there would be an interrupt-storm when we
1576 * release the IRQ lock. So we wait for the enable register update to
1577 * take effect in h/w (by reading it back) and then clear all other bits
1578 * in the status register. Ie. we clear them from ISR once it's certain
1579 * IER won't allow them to reassert.
1580 */
1581 local_irq_save(irqflags);
1582 bits &= QM_PIRQ_VISIBLE;
f5bd2299 1583 p->irq_sources &= ~bits;
c535e923
CM		 1584 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1585 ier = qm_in(&p->p, QM_REG_IER);
1586 /*
1587 * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a
1588 * data-dependency, ie. to protect against re-ordering.
1589 */
1590 qm_out(&p->p, QM_REG_ISR, ~ier);
1591 local_irq_restore(irqflags);
1592}
1593EXPORT_SYMBOL(qman_p_irqsource_remove);
1594
1595const cpumask_t *qman_affine_cpus(void)
1596{
1597 return &affine_mask;
1598}
1599EXPORT_SYMBOL(qman_affine_cpus);
1600
1601u16 qman_affine_channel(int cpu)
1602{
1603 if (cpu < 0) {
1604 struct qman_portal *portal = get_affine_portal();
1605
1606 cpu = portal->config->cpu;
1607 put_affine_portal();
1608 }
1609 WARN_ON(!cpumask_test_cpu(cpu, &affine_mask));
1610 return affine_channels[cpu];
1611}
1612EXPORT_SYMBOL(qman_affine_channel);
1613
1614struct qman_portal *qman_get_affine_portal(int cpu)
1615{
1616 return affine_portals[cpu];
1617}
1618EXPORT_SYMBOL(qman_get_affine_portal);
1619
1620int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit)
1621{
1622 return __poll_portal_fast(p, limit);
1623}
1624EXPORT_SYMBOL(qman_p_poll_dqrr);
1625
1626void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools)
1627{
1628 unsigned long irqflags;
1629
1630 local_irq_save(irqflags);
1631 pools &= p->config->pools;
1632 p->sdqcr |= pools;
1633 qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1634 local_irq_restore(irqflags);
1635}
1636EXPORT_SYMBOL(qman_p_static_dequeue_add);
1637
1638/* Frame queue API */
1639
1640static const char *mcr_result_str(u8 result)
1641{
1642 switch (result) {
1643 case QM_MCR_RESULT_NULL:
1644 return "QM_MCR_RESULT_NULL";
1645 case QM_MCR_RESULT_OK:
1646 return "QM_MCR_RESULT_OK";
1647 case QM_MCR_RESULT_ERR_FQID:
1648 return "QM_MCR_RESULT_ERR_FQID";
1649 case QM_MCR_RESULT_ERR_FQSTATE:
1650 return "QM_MCR_RESULT_ERR_FQSTATE";
1651 case QM_MCR_RESULT_ERR_NOTEMPTY:
1652 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1653 case QM_MCR_RESULT_PENDING:
1654 return "QM_MCR_RESULT_PENDING";
1655 case QM_MCR_RESULT_ERR_BADCOMMAND:
1656 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1657 }
1658 return "<unknown MCR result>";
1659}
1660
1661int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1662{
1663 if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1664 int ret = qman_alloc_fqid(&fqid);
1665
1666 if (ret)
1667 return ret;
1668 }
1669 fq->fqid = fqid;
1670 fq->flags = flags;
1671 fq->state = qman_fq_state_oos;
1672 fq->cgr_groupid = 0;
1673
1674 /* A context_b of 0 is allegedly special, so don't use that fqid */
1675 if (fqid == 0 || fqid >= num_fqids) {
1676 WARN(1, "bad fqid %d\n", fqid);
1677 return -EINVAL;
1678 }
1679
1680 fq->idx = fqid * 2;
1681 if (flags & QMAN_FQ_FLAG_NO_MODIFY)
1682 fq->idx++;
1683
1684 WARN_ON(fq_table[fq->idx]);
1685 fq_table[fq->idx] = fq;
1686
1687 return 0;
1688}
1689EXPORT_SYMBOL(qman_create_fq);
1690
1691void qman_destroy_fq(struct qman_fq *fq)
1692{
1693 /*
1694 * We don't need to lock the FQ as it is a pre-condition that the FQ be
1695 * quiesced. Instead, run some checks.
1696 */
1697 switch (fq->state) {
1698 case qman_fq_state_parked:
1699 case qman_fq_state_oos:
1700 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1701 qman_release_fqid(fq->fqid);
1702
1703 DPAA_ASSERT(fq_table[fq->idx]);
1704 fq_table[fq->idx] = NULL;
1705 return;
1706 default:
1707 break;
1708 }
1709 DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1710}
1711EXPORT_SYMBOL(qman_destroy_fq);
1712
1713u32 qman_fq_fqid(struct qman_fq *fq)
1714{
1715 return fq->fqid;
1716}
1717EXPORT_SYMBOL(qman_fq_fqid);
1718
1719int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1720{
1721 union qm_mc_command *mcc;
1722 union qm_mc_result *mcr;
1723 struct qman_portal *p;
1724 u8 res, myverb;
1725 int ret = 0;
1726
1727 myverb = (flags & QMAN_INITFQ_FLAG_SCHED)
1728 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1729
1730 if (fq->state != qman_fq_state_oos &&
1731 fq->state != qman_fq_state_parked)
1732 return -EINVAL;
1733#ifdef CONFIG_FSL_DPAA_CHECKING
1734 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1735 return -EINVAL;
1736#endif
18058822 1737 if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) {
c535e923 1738 /* And can't be set at the same time as TDTHRESH */
18058822 1739 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH)
c535e923
CM		 1740 return -EINVAL;
1741 }
1742 /* Issue an INITFQ_[PARKED|SCHED] management command */
1743 p = get_affine_portal();
1744 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1745 (fq->state != qman_fq_state_oos &&
1746 fq->state != qman_fq_state_parked)) {
1747 ret = -EBUSY;
1748 goto out;
1749 }
1750 mcc = qm_mc_start(&p->p);
1751 if (opts)
1752 mcc->initfq = *opts;
d6753c7e 1753 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 1754 mcc->initfq.count = 0;
1755 /*
efe848cd 1756 * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a
c535e923
CM		 1757 * demux pointer. Otherwise, the caller-provided value is allowed to
1758 * stand, don't overwrite it.
1759 */
1760 if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1761 dma_addr_t phys_fq;
1762
18058822
CM		 1763 mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB);
1764 mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq));
c535e923
CM		 1765 /*
1766 * and the physical address - NB, if the user wasn't trying to
1767 * set CONTEXTA, clear the stashing settings.
1768 */
18058822
CM		 1769 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1770 QM_INITFQ_WE_CONTEXTA)) {
1771 mcc->initfq.we_mask |=
1772 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
c535e923
CM		 1773 memset(&mcc->initfq.fqd.context_a, 0,
1774 sizeof(mcc->initfq.fqd.context_a));
1775 } else {
0fbeac3b
CM		 1776 struct qman_portal *p = qman_dma_portal;
1777
1778 phys_fq = dma_map_single(p->config->dev, fq,
1779 sizeof(*fq), DMA_TO_DEVICE);
1780 if (dma_mapping_error(p->config->dev, phys_fq)) {
1781 dev_err(p->config->dev, "dma_mapping failed\n");
1782 ret = -EIO;
1783 goto out;
1784 }
1785
c535e923
CM		 1786 qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1787 }
1788 }
1789 if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1790 int wq = 0;
1791
18058822
CM		 1792 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1793 QM_INITFQ_WE_DESTWQ)) {
1794 mcc->initfq.we_mask |=
1795 cpu_to_be16(QM_INITFQ_WE_DESTWQ);
c535e923
CM		 1796 wq = 4;
1797 }
1798 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
1799 }
1800 qm_mc_commit(&p->p, myverb);
1801 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1802 dev_err(p->config->dev, "MCR timeout\n");
1803 ret = -ETIMEDOUT;
1804 goto out;
1805 }
1806
1807 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1808 res = mcr->result;
1809 if (res != QM_MCR_RESULT_OK) {
1810 ret = -EIO;
1811 goto out;
1812 }
1813 if (opts) {
18058822
CM		 1814 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) {
1815 if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE)
c535e923
CM		 1816 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1817 else
1818 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1819 }
18058822 1820 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID)
c535e923
CM		 1821 fq->cgr_groupid = opts->fqd.cgid;
1822 }
1823 fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1824 qman_fq_state_sched : qman_fq_state_parked;
1825
1826out:
1827 put_affine_portal();
1828 return ret;
1829}
1830EXPORT_SYMBOL(qman_init_fq);
1831
1832int qman_schedule_fq(struct qman_fq *fq)
1833{
1834 union qm_mc_command *mcc;
1835 union qm_mc_result *mcr;
1836 struct qman_portal *p;
1837 int ret = 0;
1838
1839 if (fq->state != qman_fq_state_parked)
1840 return -EINVAL;
1841#ifdef CONFIG_FSL_DPAA_CHECKING
1842 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1843 return -EINVAL;
1844#endif
1845 /* Issue a ALTERFQ_SCHED management command */
1846 p = get_affine_portal();
1847 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1848 fq->state != qman_fq_state_parked) {
1849 ret = -EBUSY;
1850 goto out;
1851 }
1852 mcc = qm_mc_start(&p->p);
d6753c7e 1853 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 1854 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1855 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1856 dev_err(p->config->dev, "ALTER_SCHED timeout\n");
1857 ret = -ETIMEDOUT;
1858 goto out;
1859 }
1860
1861 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1862 if (mcr->result != QM_MCR_RESULT_OK) {
1863 ret = -EIO;
1864 goto out;
1865 }
1866 fq->state = qman_fq_state_sched;
1867out:
1868 put_affine_portal();
1869 return ret;
1870}
1871EXPORT_SYMBOL(qman_schedule_fq);
1872
1873int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1874{
1875 union qm_mc_command *mcc;
1876 union qm_mc_result *mcr;
1877 struct qman_portal *p;
1878 int ret;
1879 u8 res;
1880
1881 if (fq->state != qman_fq_state_parked &&
1882 fq->state != qman_fq_state_sched)
1883 return -EINVAL;
1884#ifdef CONFIG_FSL_DPAA_CHECKING
1885 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1886 return -EINVAL;
1887#endif
1888 p = get_affine_portal();
1889 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1890 fq->state == qman_fq_state_retired ||
1891 fq->state == qman_fq_state_oos) {
1892 ret = -EBUSY;
1893 goto out;
1894 }
1895 mcc = qm_mc_start(&p->p);
d6753c7e 1896 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 1897 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1898 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1899 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n");
1900 ret = -ETIMEDOUT;
1901 goto out;
1902 }
1903
1904 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
1905 res = mcr->result;
1906 /*
1907 * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
1908 * and defer the flags until FQRNI or FQRN (respectively) show up. But
1909 * "Friendly" is to process OK immediately, and not set CHANGING. We do
1910 * friendly, otherwise the caller doesn't necessarily have a fully
1911 * "retired" FQ on return even if the retirement was immediate. However
1912 * this does mean some code duplication between here and
1913 * fq_state_change().
1914 */
1915 if (res == QM_MCR_RESULT_OK) {
1916 ret = 0;
1917 /* Process 'fq' right away, we'll ignore FQRNI */
1918 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
1919 fq_set(fq, QMAN_FQ_STATE_NE);
1920 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
1921 fq_set(fq, QMAN_FQ_STATE_ORL);
1922 if (flags)
1923 *flags = fq->flags;
1924 fq->state = qman_fq_state_retired;
1925 if (fq->cb.fqs) {
1926 /*
1927 * Another issue with supporting "immediate" retirement
1928 * is that we're forced to drop FQRNIs, because by the
1929 * time they're seen it may already be "too late" (the
1930 * fq may have been OOS'd and free()'d already). But if
1931 * the upper layer wants a callback whether it's
1932 * immediate or not, we have to fake a "MR" entry to
1933 * look like an FQRNI...
1934 */
1935 union qm_mr_entry msg;
1936
1937 msg.verb = QM_MR_VERB_FQRNI;
1938 msg.fq.fqs = mcr->alterfq.fqs;
d6753c7e 1939 qm_fqid_set(&msg.fq, fq->fqid);
18058822 1940 msg.fq.context_b = cpu_to_be32(fq_to_tag(fq));
c535e923
CM		 1941 fq->cb.fqs(p, fq, &msg);
1942 }
1943 } else if (res == QM_MCR_RESULT_PENDING) {
1944 ret = 1;
1945 fq_set(fq, QMAN_FQ_STATE_CHANGING);
1946 } else {
1947 ret = -EIO;
1948 }
1949out:
1950 put_affine_portal();
1951 return ret;
1952}
1953EXPORT_SYMBOL(qman_retire_fq);
1954
1955int qman_oos_fq(struct qman_fq *fq)
1956{
1957 union qm_mc_command *mcc;
1958 union qm_mc_result *mcr;
1959 struct qman_portal *p;
1960 int ret = 0;
1961
1962 if (fq->state != qman_fq_state_retired)
1963 return -EINVAL;
1964#ifdef CONFIG_FSL_DPAA_CHECKING
1965 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1966 return -EINVAL;
1967#endif
1968 p = get_affine_portal();
1969 if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) ||
1970 fq->state != qman_fq_state_retired) {
1971 ret = -EBUSY;
1972 goto out;
1973 }
1974 mcc = qm_mc_start(&p->p);
d6753c7e 1975 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 1976 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
1977 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1978 ret = -ETIMEDOUT;
1979 goto out;
1980 }
1981 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
1982 if (mcr->result != QM_MCR_RESULT_OK) {
1983 ret = -EIO;
1984 goto out;
1985 }
1986 fq->state = qman_fq_state_oos;
1987out:
1988 put_affine_portal();
1989 return ret;
1990}
1991EXPORT_SYMBOL(qman_oos_fq);
1992
1993int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
1994{
1995 union qm_mc_command *mcc;
1996 union qm_mc_result *mcr;
1997 struct qman_portal *p = get_affine_portal();
1998 int ret = 0;
1999
2000 mcc = qm_mc_start(&p->p);
d6753c7e 2001 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 2002 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2003 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2004 ret = -ETIMEDOUT;
2005 goto out;
2006 }
2007
2008 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2009 if (mcr->result == QM_MCR_RESULT_OK)
2010 *fqd = mcr->queryfq.fqd;
2011 else
2012 ret = -EIO;
2013out:
2014 put_affine_portal();
2015 return ret;
2016}
2017
8496272d 2018int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
c535e923
CM		 2019{
2020 union qm_mc_command *mcc;
2021 union qm_mc_result *mcr;
2022 struct qman_portal *p = get_affine_portal();
2023 int ret = 0;
2024
2025 mcc = qm_mc_start(&p->p);
d6753c7e 2026 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 2027 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2028 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2029 ret = -ETIMEDOUT;
2030 goto out;
2031 }
2032
2033 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2034 if (mcr->result == QM_MCR_RESULT_OK)
2035 *np = mcr->queryfq_np;
2036 else if (mcr->result == QM_MCR_RESULT_ERR_FQID)
2037 ret = -ERANGE;
2038 else
2039 ret = -EIO;
2040out:
2041 put_affine_portal();
2042 return ret;
2043}
8496272d 2044EXPORT_SYMBOL(qman_query_fq_np);
c535e923
CM		 2045
2046static int qman_query_cgr(struct qman_cgr *cgr,
2047 struct qm_mcr_querycgr *cgrd)
2048{
2049 union qm_mc_command *mcc;
2050 union qm_mc_result *mcr;
2051 struct qman_portal *p = get_affine_portal();
2052 int ret = 0;
2053
2054 mcc = qm_mc_start(&p->p);
7ff07da0 2055 mcc->cgr.cgid = cgr->cgrid;
c535e923
CM		 2056 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
2057 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2058 ret = -ETIMEDOUT;
2059 goto out;
2060 }
2061 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
2062 if (mcr->result == QM_MCR_RESULT_OK)
2063 *cgrd = mcr->querycgr;
2064 else {
2065 dev_err(p->config->dev, "QUERY_CGR failed: %s\n",
2066 mcr_result_str(mcr->result));
2067 ret = -EIO;
2068 }
2069out:
2070 put_affine_portal();
2071 return ret;
2072}
2073
2074int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result)
2075{
2076 struct qm_mcr_querycgr query_cgr;
2077 int err;
2078
2079 err = qman_query_cgr(cgr, &query_cgr);
2080 if (err)
2081 return err;
2082
2083 *result = !!query_cgr.cgr.cs;
2084 return 0;
2085}
2086EXPORT_SYMBOL(qman_query_cgr_congested);
2087
2088/* internal function used as a wait_event() expression */
2089static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr)
2090{
2091 unsigned long irqflags;
2092 int ret = -EBUSY;
2093
2094 local_irq_save(irqflags);
2095 if (p->vdqcr_owned)
2096 goto out;
2097 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2098 goto out;
2099
2100 fq_set(fq, QMAN_FQ_STATE_VDQCR);
2101 p->vdqcr_owned = fq;
2102 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2103 ret = 0;
2104out:
2105 local_irq_restore(irqflags);
2106 return ret;
2107}
2108
2109static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr)
2110{
2111 int ret;
2112
2113 *p = get_affine_portal();
2114 ret = set_p_vdqcr(*p, fq, vdqcr);
2115 put_affine_portal();
2116 return ret;
2117}
2118
2119static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq,
2120 u32 vdqcr, u32 flags)
2121{
2122 int ret = 0;
2123
2124 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2125 ret = wait_event_interruptible(affine_queue,
2126 !set_vdqcr(p, fq, vdqcr));
2127 else
2128 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr));
2129 return ret;
2130}
2131
2132int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr)
2133{
2134 struct qman_portal *p;
2135 int ret;
2136
2137 if (fq->state != qman_fq_state_parked &&
2138 fq->state != qman_fq_state_retired)
2139 return -EINVAL;
2140 if (vdqcr & QM_VDQCR_FQID_MASK)
2141 return -EINVAL;
2142 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2143 return -EBUSY;
2144 vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2145 if (flags & QMAN_VOLATILE_FLAG_WAIT)
2146 ret = wait_vdqcr_start(&p, fq, vdqcr, flags);
2147 else
2148 ret = set_vdqcr(&p, fq, vdqcr);
2149 if (ret)
2150 return ret;
2151 /* VDQCR is set */
2152 if (flags & QMAN_VOLATILE_FLAG_FINISH) {
2153 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2154 /*
2155 * NB: don't propagate any error - the caller wouldn't
2156 * know whether the VDQCR was issued or not. A signal
2157 * could arrive after returning anyway, so the caller
2158 * can check signal_pending() if that's an issue.
2159 */
2160 wait_event_interruptible(affine_queue,
2161 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2162 else
2163 wait_event(affine_queue,
2164 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2165 }
2166 return 0;
2167}
2168EXPORT_SYMBOL(qman_volatile_dequeue);
2169
2170static void update_eqcr_ci(struct qman_portal *p, u8 avail)
2171{
2172 if (avail)
2173 qm_eqcr_cce_prefetch(&p->p);
2174 else
2175 qm_eqcr_cce_update(&p->p);
2176}
2177
2178int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)
2179{
2180 struct qman_portal *p;
2181 struct qm_eqcr_entry *eq;
2182 unsigned long irqflags;
2183 u8 avail;
2184
2185 p = get_affine_portal();
2186 local_irq_save(irqflags);
2187
2188 if (p->use_eqcr_ci_stashing) {
2189 /*
2190 * The stashing case is easy, only update if we need to in
2191 * order to try and liberate ring entries.
2192 */
2193 eq = qm_eqcr_start_stash(&p->p);
2194 } else {
2195 /*
2196 * The non-stashing case is harder, need to prefetch ahead of
2197 * time.
2198 */
2199 avail = qm_eqcr_get_avail(&p->p);
2200 if (avail < 2)
2201 update_eqcr_ci(p, avail);
2202 eq = qm_eqcr_start_no_stash(&p->p);
2203 }
2204
2205 if (unlikely(!eq))
2206 goto out;
2207
d6753c7e 2208 qm_fqid_set(eq, fq->fqid);
18058822 2209 eq->tag = cpu_to_be32(fq_to_tag(fq));
c535e923
CM		 2210 eq->fd = *fd;
2211
2212 qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);
2213out:
2214 local_irq_restore(irqflags);
2215 put_affine_portal();
2216 return 0;
2217}
2218EXPORT_SYMBOL(qman_enqueue);
2219
2220static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags,
2221 struct qm_mcc_initcgr *opts)
2222{
2223 union qm_mc_command *mcc;
2224 union qm_mc_result *mcr;
2225 struct qman_portal *p = get_affine_portal();
2226 u8 verb = QM_MCC_VERB_MODIFYCGR;
2227 int ret = 0;
2228
2229 mcc = qm_mc_start(&p->p);
2230 if (opts)
2231 mcc->initcgr = *opts;
2232 mcc->initcgr.cgid = cgr->cgrid;
2233 if (flags & QMAN_CGR_FLAG_USE_INIT)
2234 verb = QM_MCC_VERB_INITCGR;
2235 qm_mc_commit(&p->p, verb);
2236 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2237 ret = -ETIMEDOUT;
2238 goto out;
2239 }
2240
2241 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2242 if (mcr->result != QM_MCR_RESULT_OK)
2243 ret = -EIO;
2244
2245out:
2246 put_affine_portal();
2247 return ret;
2248}
2249
2250#define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
496bfa11
CM		 2251
2252/* congestion state change notification target update control */
2253static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val)
2254{
2255 if (qman_ip_rev >= QMAN_REV30)
18058822
CM		 2256 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi |
2257 QM_CGR_TARG_UDP_CTRL_WRITE_BIT);
496bfa11 2258 else
18058822 2259 cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi));
496bfa11
CM		 2260}
2261
2262static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val)
2263{
2264 if (qman_ip_rev >= QMAN_REV30)
18058822 2265 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi);
496bfa11 2266 else
18058822 2267 cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi));
496bfa11 2268}
c535e923
CM		 2269
2270static u8 qman_cgr_cpus[CGR_NUM];
2271
2272void qman_init_cgr_all(void)
2273{
2274 struct qman_cgr cgr;
2275 int err_cnt = 0;
2276
2277 for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) {
2278 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL))
2279 err_cnt++;
2280 }
2281
2282 if (err_cnt)
2283 pr_err("Warning: %d error%s while initialising CGR h/w\n",
2284 err_cnt, (err_cnt > 1) ? "s" : "");
2285}
2286
2287int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2288 struct qm_mcc_initcgr *opts)
2289{
2290 struct qm_mcr_querycgr cgr_state;
c535e923
CM		 2291 int ret;
2292 struct qman_portal *p;
2293
2294 /*
2295 * We have to check that the provided CGRID is within the limits of the
2296 * data-structures, for obvious reasons. However we'll let h/w take
2297 * care of determining whether it's within the limits of what exists on
2298 * the SoC.
2299 */
2300 if (cgr->cgrid >= CGR_NUM)
2301 return -EINVAL;
2302
2303 preempt_disable();
2304 p = get_affine_portal();
2305 qman_cgr_cpus[cgr->cgrid] = smp_processor_id();
2306 preempt_enable();
2307
2308 cgr->chan = p->config->channel;
2309 spin_lock(&p->cgr_lock);
2310
2311 if (opts) {
e5caf693
CM		 2312 struct qm_mcc_initcgr local_opts = *opts;
2313
c535e923
CM		 2314 ret = qman_query_cgr(cgr, &cgr_state);
2315 if (ret)
2316 goto out;
e5caf693 2317
496bfa11 2318 qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p),
18058822
CM		 2319 be32_to_cpu(cgr_state.cgr.cscn_targ));
2320 local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG);
c535e923
CM		 2321
2322 /* send init if flags indicate so */
e5caf693 2323 if (flags & QMAN_CGR_FLAG_USE_INIT)
c535e923
CM		 2324 ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2325 &local_opts);
2326 else
2327 ret = qm_modify_cgr(cgr, 0, &local_opts);
2328 if (ret)
2329 goto out;
2330 }
2331
2332 list_add(&cgr->node, &p->cgr_cbs);
2333
2334 /* Determine if newly added object requires its callback to be called */
2335 ret = qman_query_cgr(cgr, &cgr_state);
2336 if (ret) {
2337 /* we can't go back, so proceed and return success */
2338 dev_err(p->config->dev, "CGR HW state partially modified\n");
2339 ret = 0;
2340 goto out;
2341 }
2342 if (cgr->cb && cgr_state.cgr.cscn_en &&
2343 qman_cgrs_get(&p->cgrs[1], cgr->cgrid))
2344 cgr->cb(p, cgr, 1);
2345out:
2346 spin_unlock(&p->cgr_lock);
2347 put_affine_portal();
2348 return ret;
2349}
2350EXPORT_SYMBOL(qman_create_cgr);
2351
2352int qman_delete_cgr(struct qman_cgr *cgr)
2353{
2354 unsigned long irqflags;
2355 struct qm_mcr_querycgr cgr_state;
2356 struct qm_mcc_initcgr local_opts;
2357 int ret = 0;
2358 struct qman_cgr *i;
2359 struct qman_portal *p = get_affine_portal();
2360
2361 if (cgr->chan != p->config->channel) {
2362 /* attempt to delete from other portal than creator */
2363 dev_err(p->config->dev, "CGR not owned by current portal");
2364 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n",
2365 cgr->chan, p->config->channel);
2366
2367 ret = -EINVAL;
2368 goto put_portal;
2369 }
2370 memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2371 spin_lock_irqsave(&p->cgr_lock, irqflags);
2372 list_del(&cgr->node);
2373 /*
2374 * If there are no other CGR objects for this CGRID in the list,
2375 * update CSCN_TARG accordingly
2376 */
2377 list_for_each_entry(i, &p->cgr_cbs, node)
2378 if (i->cgrid == cgr->cgrid && i->cb)
2379 goto release_lock;
2380 ret = qman_query_cgr(cgr, &cgr_state);
2381 if (ret) {
2382 /* add back to the list */
2383 list_add(&cgr->node, &p->cgr_cbs);
2384 goto release_lock;
2385 }
496bfa11 2386
18058822 2387 local_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG);
496bfa11 2388 qm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p),
18058822 2389 be32_to_cpu(cgr_state.cgr.cscn_targ));
496bfa11 2390
c535e923
CM		 2391 ret = qm_modify_cgr(cgr, 0, &local_opts);
2392 if (ret)
2393 /* add back to the list */
2394 list_add(&cgr->node, &p->cgr_cbs);
2395release_lock:
2396 spin_unlock_irqrestore(&p->cgr_lock, irqflags);
2397put_portal:
2398 put_affine_portal();
2399 return ret;
2400}
2401EXPORT_SYMBOL(qman_delete_cgr);
2402
2403struct cgr_comp {
2404 struct qman_cgr *cgr;
2405 struct completion completion;
2406};
2407
2408static int qman_delete_cgr_thread(void *p)
2409{
2410 struct cgr_comp *cgr_comp = (struct cgr_comp *)p;
2411 int ret;
2412
2413 ret = qman_delete_cgr(cgr_comp->cgr);
2414 complete(&cgr_comp->completion);
2415
2416 return ret;
2417}
2418
2419void qman_delete_cgr_safe(struct qman_cgr *cgr)
2420{
2421 struct task_struct *thread;
2422 struct cgr_comp cgr_comp;
2423
2424 preempt_disable();
2425 if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) {
2426 init_completion(&cgr_comp.completion);
2427 cgr_comp.cgr = cgr;
2428 thread = kthread_create(qman_delete_cgr_thread, &cgr_comp,
2429 "cgr_del");
2430
2431 if (IS_ERR(thread))
2432 goto out;
2433
2434 kthread_bind(thread, qman_cgr_cpus[cgr->cgrid]);
2435 wake_up_process(thread);
2436 wait_for_completion(&cgr_comp.completion);
2437 preempt_enable();
2438 return;
2439 }
2440out:
2441 qman_delete_cgr(cgr);
2442 preempt_enable();
2443}
2444EXPORT_SYMBOL(qman_delete_cgr_safe);
2445
2446/* Cleanup FQs */
2447
2448static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
2449{
2450 const union qm_mr_entry *msg;
2451 int found = 0;
2452
2453 qm_mr_pvb_update(p);
2454 msg = qm_mr_current(p);
2455 while (msg) {
2456 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v)
2457 found = 1;
2458 qm_mr_next(p);
2459 qm_mr_cci_consume_to_current(p);
2460 qm_mr_pvb_update(p);
2461 msg = qm_mr_current(p);
2462 }
2463 return found;
2464}
2465
2466static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
2467 bool wait)
2468{
2469 const struct qm_dqrr_entry *dqrr;
2470 int found = 0;
2471
2472 do {
2473 qm_dqrr_pvb_update(p);
2474 dqrr = qm_dqrr_current(p);
2475 if (!dqrr)
2476 cpu_relax();
2477 } while (wait && !dqrr);
2478
2479 while (dqrr) {
d6753c7e 2480 if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s))
c535e923
CM		 2481 found = 1;
2482 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
2483 qm_dqrr_pvb_update(p);
2484 qm_dqrr_next(p);
2485 dqrr = qm_dqrr_current(p);
2486 }
2487 return found;
2488}
2489
2490#define qm_mr_drain(p, V) \
2491 _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
2492
2493#define qm_dqrr_drain(p, f, S) \
2494 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
2495
2496#define qm_dqrr_drain_wait(p, f, S) \
2497 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
2498
2499#define qm_dqrr_drain_nomatch(p) \
2500 _qm_dqrr_consume_and_match(p, 0, 0, false)
2501
2502static int qman_shutdown_fq(u32 fqid)
2503{
2504 struct qman_portal *p;
2505 struct device *dev;
2506 union qm_mc_command *mcc;
2507 union qm_mc_result *mcr;
2508 int orl_empty, drain = 0, ret = 0;
2509 u32 channel, wq, res;
2510 u8 state;
2511
2512 p = get_affine_portal();
2513 dev = p->config->dev;
2514 /* Determine the state of the FQID */
2515 mcc = qm_mc_start(&p->p);
d6753c7e 2516 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2517 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2518 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2519 dev_err(dev, "QUERYFQ_NP timeout\n");
2520 ret = -ETIMEDOUT;
2521 goto out;
2522 }
2523
2524 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2525 state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2526 if (state == QM_MCR_NP_STATE_OOS)
2527 goto out; /* Already OOS, no need to do anymore checks */
2528
2529 /* Query which channel the FQ is using */
2530 mcc = qm_mc_start(&p->p);
d6753c7e 2531 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2532 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2533 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2534 dev_err(dev, "QUERYFQ timeout\n");
2535 ret = -ETIMEDOUT;
2536 goto out;
2537 }
2538
2539 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2540 /* Need to store these since the MCR gets reused */
2541 channel = qm_fqd_get_chan(&mcr->queryfq.fqd);
2542 wq = qm_fqd_get_wq(&mcr->queryfq.fqd);
2543
2544 switch (state) {
2545 case QM_MCR_NP_STATE_TEN_SCHED:
2546 case QM_MCR_NP_STATE_TRU_SCHED:
2547 case QM_MCR_NP_STATE_ACTIVE:
2548 case QM_MCR_NP_STATE_PARKED:
2549 orl_empty = 0;
2550 mcc = qm_mc_start(&p->p);
d6753c7e 2551 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2552 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
2553 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2554 dev_err(dev, "QUERYFQ_NP timeout\n");
2555 ret = -ETIMEDOUT;
2556 goto out;
2557 }
2558 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2559 QM_MCR_VERB_ALTER_RETIRE);
2560 res = mcr->result; /* Make a copy as we reuse MCR below */
2561
2562 if (res == QM_MCR_RESULT_PENDING) {
2563 /*
2564 * Need to wait for the FQRN in the message ring, which
2565 * will only occur once the FQ has been drained. In
2566 * order for the FQ to drain the portal needs to be set
2567 * to dequeue from the channel the FQ is scheduled on
2568 */
2569 int found_fqrn = 0;
2570 u16 dequeue_wq = 0;
2571
2572 /* Flag that we need to drain FQ */
2573 drain = 1;
2574
2575 if (channel >= qm_channel_pool1 &&
2576 channel < qm_channel_pool1 + 15) {
2577 /* Pool channel, enable the bit in the portal */
2578 dequeue_wq = (channel -
2579 qm_channel_pool1 + 1)<<4 | wq;
2580 } else if (channel < qm_channel_pool1) {
2581 /* Dedicated channel */
2582 dequeue_wq = wq;
2583 } else {
2584 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x",
2585 fqid, channel);
2586 ret = -EBUSY;
2587 goto out;
2588 }
2589 /* Set the sdqcr to drain this channel */
2590 if (channel < qm_channel_pool1)
2591 qm_dqrr_sdqcr_set(&p->p,
2592 QM_SDQCR_TYPE_ACTIVE |
2593 QM_SDQCR_CHANNELS_DEDICATED);
2594 else
2595 qm_dqrr_sdqcr_set(&p->p,
2596 QM_SDQCR_TYPE_ACTIVE |
2597 QM_SDQCR_CHANNELS_POOL_CONV
2598 (channel));
2599 do {
2600 /* Keep draining DQRR while checking the MR*/
2601 qm_dqrr_drain_nomatch(&p->p);
2602 /* Process message ring too */
2603 found_fqrn = qm_mr_drain(&p->p, FQRN);
2604 cpu_relax();
2605 } while (!found_fqrn);
2606
2607 }
2608 if (res != QM_MCR_RESULT_OK &&
2609 res != QM_MCR_RESULT_PENDING) {
2610 dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n",
2611 fqid, res);
2612 ret = -EIO;
2613 goto out;
2614 }
2615 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2616 /*
2617 * ORL had no entries, no need to wait until the
2618 * ERNs come in
2619 */
2620 orl_empty = 1;
2621 }
2622 /*
2623 * Retirement succeeded, check to see if FQ needs
2624 * to be drained
2625 */
2626 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2627 /* FQ is Not Empty, drain using volatile DQ commands */
2628 do {
2629 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2630
2631 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2632 /*
2633 * Wait for a dequeue and process the dequeues,
2634 * making sure to empty the ring completely
2635 */
2636 } while (qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
2637 }
2638 qm_dqrr_sdqcr_set(&p->p, 0);
2639
2640 while (!orl_empty) {
2641 /* Wait for the ORL to have been completely drained */
2642 orl_empty = qm_mr_drain(&p->p, FQRL);
2643 cpu_relax();
2644 }
2645 mcc = qm_mc_start(&p->p);
d6753c7e 2646 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2647 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2648 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2649 ret = -ETIMEDOUT;
2650 goto out;
2651 }
2652
2653 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2654 QM_MCR_VERB_ALTER_OOS);
2655 if (mcr->result != QM_MCR_RESULT_OK) {
2656 dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n",
2657 fqid, mcr->result);
2658 ret = -EIO;
2659 goto out;
2660 }
2661 break;
2662
2663 case QM_MCR_NP_STATE_RETIRED:
2664 /* Send OOS Command */
2665 mcc = qm_mc_start(&p->p);
d6753c7e 2666 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2667 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2668 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2669 ret = -ETIMEDOUT;
2670 goto out;
2671 }
2672
2673 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2674 QM_MCR_VERB_ALTER_OOS);
2675 if (mcr->result) {
2676 dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n",
2677 fqid, mcr->result);
2678 ret = -EIO;
2679 goto out;
2680 }
2681 break;
2682
2683 case QM_MCR_NP_STATE_OOS:
2684 /* Done */
2685 break;
2686
2687 default:
2688 ret = -EIO;
2689 }
2690
2691out:
2692 put_affine_portal();
2693 return ret;
2694}
2695
2696const struct qm_portal_config *qman_get_qm_portal_config(
2697 struct qman_portal *portal)
2698{
2699 return portal->config;
2700}
021ba010 2701EXPORT_SYMBOL(qman_get_qm_portal_config);
c535e923
CM		 2702
2703struct gen_pool *qm_fqalloc; /* FQID allocator */
2704struct gen_pool *qm_qpalloc; /* pool-channel allocator */
2705struct gen_pool *qm_cgralloc; /* CGR ID allocator */
2706
2707static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)
2708{
2709 unsigned long addr;
2710
2711 addr = gen_pool_alloc(p, cnt);
2712 if (!addr)
2713 return -ENOMEM;
2714
2715 *result = addr & ~DPAA_GENALLOC_OFF;
2716
2717 return 0;
2718}
2719
2720int qman_alloc_fqid_range(u32 *result, u32 count)
2721{
2722 return qman_alloc_range(qm_fqalloc, result, count);
2723}
2724EXPORT_SYMBOL(qman_alloc_fqid_range);
2725
2726int qman_alloc_pool_range(u32 *result, u32 count)
2727{
2728 return qman_alloc_range(qm_qpalloc, result, count);
2729}
2730EXPORT_SYMBOL(qman_alloc_pool_range);
2731
2732int qman_alloc_cgrid_range(u32 *result, u32 count)
2733{
2734 return qman_alloc_range(qm_cgralloc, result, count);
2735}
2736EXPORT_SYMBOL(qman_alloc_cgrid_range);
2737
2738int qman_release_fqid(u32 fqid)
2739{
2740 int ret = qman_shutdown_fq(fqid);
2741
2742 if (ret) {
2743 pr_debug("FQID %d leaked\n", fqid);
2744 return ret;
2745 }
2746
2747 gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1);
2748 return 0;
2749}
2750EXPORT_SYMBOL(qman_release_fqid);
2751
2752static int qpool_cleanup(u32 qp)
2753{
2754 /*
2755 * We query all FQDs starting from
2756 * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs
2757 * whose destination channel is the pool-channel being released.
2758 * When a non-OOS FQD is found we attempt to clean it up
2759 */
2760 struct qman_fq fq = {
2761 .fqid = QM_FQID_RANGE_START
2762 };
2763 int err;
2764
2765 do {
2766 struct qm_mcr_queryfq_np np;
2767
2768 err = qman_query_fq_np(&fq, &np);
d95cb0d3 2769 if (err == -ERANGE)
c535e923
CM		 2770 /* FQID range exceeded, found no problems */
2771 return 0;
d95cb0d3
CM		 2772 else if (WARN_ON(err))
2773 return err;
2774
c535e923
CM		 2775 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2776 struct qm_fqd fqd;
2777
2778 err = qman_query_fq(&fq, &fqd);
2779 if (WARN_ON(err))
d95cb0d3 2780 return err;
c535e923
CM		 2781 if (qm_fqd_get_chan(&fqd) == qp) {
2782 /* The channel is the FQ's target, clean it */
2783 err = qman_shutdown_fq(fq.fqid);
2784 if (err)
2785 /*
2786 * Couldn't shut down the FQ
2787 * so the pool must be leaked
2788 */
2789 return err;
2790 }
2791 }
2792 /* Move to the next FQID */
2793 fq.fqid++;
2794 } while (1);
2795}
2796
2797int qman_release_pool(u32 qp)
2798{
2799 int ret;
2800
2801 ret = qpool_cleanup(qp);
2802 if (ret) {
2803 pr_debug("CHID %d leaked\n", qp);
2804 return ret;
2805 }
2806
2807 gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1);
2808 return 0;
2809}
2810EXPORT_SYMBOL(qman_release_pool);
2811
2812static int cgr_cleanup(u32 cgrid)
2813{
2814 /*
2815 * query all FQDs starting from FQID 1 until we get an "invalid FQID"
2816 * error, looking for non-OOS FQDs whose CGR is the CGR being released
2817 */
2818 struct qman_fq fq = {
d95cb0d3 2819 .fqid = QM_FQID_RANGE_START
c535e923
CM		 2820 };
2821 int err;
2822
2823 do {
2824 struct qm_mcr_queryfq_np np;
2825
2826 err = qman_query_fq_np(&fq, &np);
d95cb0d3 2827 if (err == -ERANGE)
c535e923
CM		 2828 /* FQID range exceeded, found no problems */
2829 return 0;
d95cb0d3
CM		 2830 else if (WARN_ON(err))
2831 return err;
2832
c535e923
CM		 2833 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2834 struct qm_fqd fqd;
2835
2836 err = qman_query_fq(&fq, &fqd);
2837 if (WARN_ON(err))
d95cb0d3 2838 return err;
18058822 2839 if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE &&
c535e923
CM		 2840 fqd.cgid == cgrid) {
2841 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
2842 cgrid, fq.fqid);
2843 return -EIO;
2844 }
2845 }
2846 /* Move to the next FQID */
2847 fq.fqid++;
2848 } while (1);
2849}
2850
2851int qman_release_cgrid(u32 cgrid)
2852{
2853 int ret;
2854
2855 ret = cgr_cleanup(cgrid);
2856 if (ret) {
2857 pr_debug("CGRID %d leaked\n", cgrid);
2858 return ret;
2859 }
2860
2861 gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1);
2862 return 0;
2863}
2864EXPORT_SYMBOL(qman_release_cgrid);
Ubuntu Eoan Linux kernel mirror