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dt-bindings: soc/fsl: Update reserved memory binding for QBMan
[mirror_ubuntu-eoan-kernel.git] / drivers / soc / fsl / qbman / qman.c
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c535e923
CM		 1/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Freescale Semiconductor nor the
11 * names of its contributors may be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * ALTERNATIVELY, this software may be distributed under the terms of the
15 * GNU General Public License ("GPL") as published by the Free Software
16 * Foundation, either version 2 of that License or (at your option) any
17 * later version.
18 *
19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include "qman_priv.h"
32
33#define DQRR_MAXFILL 15
34#define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */
35#define IRQNAME "QMan portal %d"
36#define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
37#define QMAN_POLL_LIMIT 32
38#define QMAN_PIRQ_DQRR_ITHRESH 12
39#define QMAN_PIRQ_MR_ITHRESH 4
40#define QMAN_PIRQ_IPERIOD 100
41
42/* Portal register assists */
43
44/* Cache-inhibited register offsets */
45#define QM_REG_EQCR_PI_CINH 0x0000
46#define QM_REG_EQCR_CI_CINH 0x0004
47#define QM_REG_EQCR_ITR 0x0008
48#define QM_REG_DQRR_PI_CINH 0x0040
49#define QM_REG_DQRR_CI_CINH 0x0044
50#define QM_REG_DQRR_ITR 0x0048
51#define QM_REG_DQRR_DCAP 0x0050
52#define QM_REG_DQRR_SDQCR 0x0054
53#define QM_REG_DQRR_VDQCR 0x0058
54#define QM_REG_DQRR_PDQCR 0x005c
55#define QM_REG_MR_PI_CINH 0x0080
56#define QM_REG_MR_CI_CINH 0x0084
57#define QM_REG_MR_ITR 0x0088
58#define QM_REG_CFG 0x0100
59#define QM_REG_ISR 0x0e00
60#define QM_REG_IER 0x0e04
61#define QM_REG_ISDR 0x0e08
62#define QM_REG_IIR 0x0e0c
63#define QM_REG_ITPR 0x0e14
64
65/* Cache-enabled register offsets */
66#define QM_CL_EQCR 0x0000
67#define QM_CL_DQRR 0x1000
68#define QM_CL_MR 0x2000
69#define QM_CL_EQCR_PI_CENA 0x3000
70#define QM_CL_EQCR_CI_CENA 0x3100
71#define QM_CL_DQRR_PI_CENA 0x3200
72#define QM_CL_DQRR_CI_CENA 0x3300
73#define QM_CL_MR_PI_CENA 0x3400
74#define QM_CL_MR_CI_CENA 0x3500
75#define QM_CL_CR 0x3800
76#define QM_CL_RR0 0x3900
77#define QM_CL_RR1 0x3940
78
79/*
80 * BTW, the drivers (and h/w programming model) already obtain the required
81 * synchronisation for portal accesses and data-dependencies. Use of barrier()s
82 * or other order-preserving primitives simply degrade performance. Hence the
83 * use of the __raw_*() interfaces, which simply ensure that the compiler treats
84 * the portal registers as volatile
85 */
86
87/* Cache-enabled ring access */
88#define qm_cl(base, idx) ((void *)base + ((idx) << 6))
89
90/*
91 * Portal modes.
92 * Enum types;
93 * pmode == production mode
94 * cmode == consumption mode,
95 * dmode == h/w dequeue mode.
96 * Enum values use 3 letter codes. First letter matches the portal mode,
97 * remaining two letters indicate;
98 * ci == cache-inhibited portal register
99 * ce == cache-enabled portal register
100 * vb == in-band valid-bit (cache-enabled)
101 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
102 * As for "enum qm_dqrr_dmode", it should be self-explanatory.
103 */
104enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
105 qm_eqcr_pci = 0, /* PI index, cache-inhibited */
106 qm_eqcr_pce = 1, /* PI index, cache-enabled */
107 qm_eqcr_pvb = 2 /* valid-bit */
108};
109enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
110 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
111 qm_dqrr_dpull = 1 /* PDQCR */
112};
113enum qm_dqrr_pmode { /* s/w-only */
114 qm_dqrr_pci, /* reads DQRR_PI_CINH */
115 qm_dqrr_pce, /* reads DQRR_PI_CENA */
116 qm_dqrr_pvb /* reads valid-bit */
117};
118enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
119 qm_dqrr_cci = 0, /* CI index, cache-inhibited */
120 qm_dqrr_cce = 1, /* CI index, cache-enabled */
121 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
122};
123enum qm_mr_pmode { /* s/w-only */
124 qm_mr_pci, /* reads MR_PI_CINH */
125 qm_mr_pce, /* reads MR_PI_CENA */
126 qm_mr_pvb /* reads valid-bit */
127};
128enum qm_mr_cmode { /* matches QCSP_CFG::MM */
129 qm_mr_cci = 0, /* CI index, cache-inhibited */
130 qm_mr_cce = 1 /* CI index, cache-enabled */
131};
132
133/* --- Portal structures --- */
134
135#define QM_EQCR_SIZE 8
136#define QM_DQRR_SIZE 16
137#define QM_MR_SIZE 8
138
139/* "Enqueue Command" */
140struct qm_eqcr_entry {
141 u8 _ncw_verb; /* writes to this are non-coherent */
142 u8 dca;
18058822 143 __be16 seqnum;
b5399452 144 u8 __reserved[4];
18058822
CM		 145 __be32 fqid; /* 24-bit */
146 __be32 tag;
c535e923
CM		 147 struct qm_fd fd;
148 u8 __reserved3[32];
149} __packed;
150#define QM_EQCR_VERB_VBIT 0x80
151#define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
152#define QM_EQCR_VERB_CMD_ENQUEUE 0x01
153#define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
154#define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
155#define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
156
157struct qm_eqcr {
158 struct qm_eqcr_entry *ring, *cursor;
159 u8 ci, available, ithresh, vbit;
160#ifdef CONFIG_FSL_DPAA_CHECKING
161 u32 busy;
162 enum qm_eqcr_pmode pmode;
163#endif
164};
165
166struct qm_dqrr {
167 const struct qm_dqrr_entry *ring, *cursor;
168 u8 pi, ci, fill, ithresh, vbit;
169#ifdef CONFIG_FSL_DPAA_CHECKING
170 enum qm_dqrr_dmode dmode;
171 enum qm_dqrr_pmode pmode;
172 enum qm_dqrr_cmode cmode;
173#endif
174};
175
176struct qm_mr {
177 union qm_mr_entry *ring, *cursor;
178 u8 pi, ci, fill, ithresh, vbit;
179#ifdef CONFIG_FSL_DPAA_CHECKING
180 enum qm_mr_pmode pmode;
181 enum qm_mr_cmode cmode;
182#endif
183};
184
185/* MC (Management Command) command */
7ff07da0
CM		 186/* "FQ" command layout */
187struct qm_mcc_fq {
c535e923
CM		 188 u8 _ncw_verb;
189 u8 __reserved1[3];
18058822 190 __be32 fqid; /* 24-bit */
c535e923
CM		 191 u8 __reserved2[56];
192} __packed;
c535e923 193
7ff07da0
CM		 194/* "CGR" command layout */
195struct qm_mcc_cgr {
c535e923
CM		 196 u8 _ncw_verb;
197 u8 __reserved1[30];
198 u8 cgid;
199 u8 __reserved2[32];
200};
201
c535e923
CM		 202#define QM_MCC_VERB_VBIT 0x80
203#define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
204#define QM_MCC_VERB_INITFQ_PARKED 0x40
205#define QM_MCC_VERB_INITFQ_SCHED 0x41
206#define QM_MCC_VERB_QUERYFQ 0x44
207#define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
208#define QM_MCC_VERB_QUERYWQ 0x46
209#define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
210#define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
211#define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
212#define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
213#define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
214#define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
215#define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
216#define QM_MCC_VERB_INITCGR 0x50
217#define QM_MCC_VERB_MODIFYCGR 0x51
218#define QM_MCC_VERB_CGRTESTWRITE 0x52
219#define QM_MCC_VERB_QUERYCGR 0x58
220#define QM_MCC_VERB_QUERYCONGESTION 0x59
221union qm_mc_command {
222 struct {
223 u8 _ncw_verb; /* writes to this are non-coherent */
224 u8 __reserved[63];
225 };
226 struct qm_mcc_initfq initfq;
c535e923 227 struct qm_mcc_initcgr initcgr;
7ff07da0
CM		 228 struct qm_mcc_fq fq;
229 struct qm_mcc_cgr cgr;
c535e923
CM		 230};
231
232/* MC (Management Command) result */
233/* "Query FQ" */
234struct qm_mcr_queryfq {
235 u8 verb;
236 u8 result;
237 u8 __reserved1[8];
238 struct qm_fqd fqd; /* the FQD fields are here */
239 u8 __reserved2[30];
240} __packed;
241
242/* "Alter FQ State Commands" */
243struct qm_mcr_alterfq {
244 u8 verb;
245 u8 result;
246 u8 fqs; /* Frame Queue Status */
247 u8 __reserved1[61];
248};
249#define QM_MCR_VERB_RRID 0x80
250#define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
251#define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
252#define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
253#define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
254#define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
255#define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
256#define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
257#define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
258#define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
259#define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
260#define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
261#define QM_MCR_RESULT_NULL 0x00
262#define QM_MCR_RESULT_OK 0xf0
263#define QM_MCR_RESULT_ERR_FQID 0xf1
264#define QM_MCR_RESULT_ERR_FQSTATE 0xf2
265#define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
266#define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
267#define QM_MCR_RESULT_PENDING 0xf8
268#define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
269#define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
270#define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
271#define QM_MCR_TIMEOUT 10000 /* us */
272union qm_mc_result {
273 struct {
274 u8 verb;
275 u8 result;
276 u8 __reserved1[62];
277 };
278 struct qm_mcr_queryfq queryfq;
279 struct qm_mcr_alterfq alterfq;
280 struct qm_mcr_querycgr querycgr;
281 struct qm_mcr_querycongestion querycongestion;
282 struct qm_mcr_querywq querywq;
283 struct qm_mcr_queryfq_np queryfq_np;
284};
285
286struct qm_mc {
287 union qm_mc_command *cr;
288 union qm_mc_result *rr;
289 u8 rridx, vbit;
290#ifdef CONFIG_FSL_DPAA_CHECKING
291 enum {
292 /* Can be _mc_start()ed */
293 qman_mc_idle,
294 /* Can be _mc_commit()ed or _mc_abort()ed */
295 qman_mc_user,
296 /* Can only be _mc_retry()ed */
297 qman_mc_hw
298 } state;
299#endif
300};
301
302struct qm_addr {
303 void __iomem *ce; /* cache-enabled */
304 void __iomem *ci; /* cache-inhibited */
305};
306
307struct qm_portal {
308 /*
309 * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to
310 * and including 'mc' fits within a cacheline (yay!). The 'config' part
311 * is setup-only, so isn't a cause for a concern. In other words, don't
312 * rearrange this structure on a whim, there be dragons ...
313 */
314 struct qm_addr addr;
315 struct qm_eqcr eqcr;
316 struct qm_dqrr dqrr;
317 struct qm_mr mr;
318 struct qm_mc mc;
319} ____cacheline_aligned;
320
321/* Cache-inhibited register access. */
322static inline u32 qm_in(struct qm_portal *p, u32 offset)
323{
5a42f1ec 324 return be32_to_cpu(__raw_readl(p->addr.ci + offset));
c535e923
CM		 325}
326
327static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)
328{
5a42f1ec 329 __raw_writel(cpu_to_be32(val), p->addr.ci + offset);
c535e923
CM		 330}
331
332/* Cache Enabled Portal Access */
333static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset)
334{
335 dpaa_invalidate(p->addr.ce + offset);
336}
337
338static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)
339{
340 dpaa_touch_ro(p->addr.ce + offset);
341}
342
343static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)
344{
5a42f1ec 345 return be32_to_cpu(__raw_readl(p->addr.ce + offset));
c535e923
CM		 346}
347
348/* --- EQCR API --- */
349
350#define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry))
351#define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT)
352
353/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
354static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p)
355{
356 uintptr_t addr = (uintptr_t)p;
357
358 addr &= ~EQCR_CARRY;
359
360 return (struct qm_eqcr_entry *)addr;
361}
362
363/* Bit-wise logic to convert a ring pointer to a ring index */
364static int eqcr_ptr2idx(struct qm_eqcr_entry *e)
365{
366 return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1);
367}
368
369/* Increment the 'cursor' ring pointer, taking 'vbit' into account */
370static inline void eqcr_inc(struct qm_eqcr *eqcr)
371{
372 /* increment to the next EQCR pointer and handle overflow and 'vbit' */
373 struct qm_eqcr_entry *partial = eqcr->cursor + 1;
374
375 eqcr->cursor = eqcr_carryclear(partial);
376 if (partial != eqcr->cursor)
377 eqcr->vbit ^= QM_EQCR_VERB_VBIT;
378}
379
380static inline int qm_eqcr_init(struct qm_portal *portal,
381 enum qm_eqcr_pmode pmode,
382 unsigned int eq_stash_thresh,
383 int eq_stash_prio)
384{
385 struct qm_eqcr *eqcr = &portal->eqcr;
386 u32 cfg;
387 u8 pi;
388
389 eqcr->ring = portal->addr.ce + QM_CL_EQCR;
390 eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
391 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
392 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
393 eqcr->cursor = eqcr->ring + pi;
394 eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ?
395 QM_EQCR_VERB_VBIT : 0;
396 eqcr->available = QM_EQCR_SIZE - 1 -
397 dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
398 eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR);
399#ifdef CONFIG_FSL_DPAA_CHECKING
400 eqcr->busy = 0;
401 eqcr->pmode = pmode;
402#endif
403 cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) |
404 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
405 (eq_stash_prio << 26) | /* QCSP_CFG: EP */
406 ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */
407 qm_out(portal, QM_REG_CFG, cfg);
408 return 0;
409}
410
411static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal)
412{
413 return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7;
414}
415
416static inline void qm_eqcr_finish(struct qm_portal *portal)
417{
418 struct qm_eqcr *eqcr = &portal->eqcr;
419 u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
420 u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
421
422 DPAA_ASSERT(!eqcr->busy);
423 if (pi != eqcr_ptr2idx(eqcr->cursor))
57907a73 424 pr_crit("losing uncommitted EQCR entries\n");
c535e923
CM		 425 if (ci != eqcr->ci)
426 pr_crit("missing existing EQCR completions\n");
427 if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
428 pr_crit("EQCR destroyed unquiesced\n");
429}
430
431static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
432 *portal)
433{
434 struct qm_eqcr *eqcr = &portal->eqcr;
435
436 DPAA_ASSERT(!eqcr->busy);
437 if (!eqcr->available)
438 return NULL;
439
440#ifdef CONFIG_FSL_DPAA_CHECKING
441 eqcr->busy = 1;
442#endif
443 dpaa_zero(eqcr->cursor);
444 return eqcr->cursor;
445}
446
447static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
448 *portal)
449{
450 struct qm_eqcr *eqcr = &portal->eqcr;
451 u8 diff, old_ci;
452
453 DPAA_ASSERT(!eqcr->busy);
454 if (!eqcr->available) {
455 old_ci = eqcr->ci;
456 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) &
457 (QM_EQCR_SIZE - 1);
458 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
459 eqcr->available += diff;
460 if (!diff)
461 return NULL;
462 }
463#ifdef CONFIG_FSL_DPAA_CHECKING
464 eqcr->busy = 1;
465#endif
466 dpaa_zero(eqcr->cursor);
467 return eqcr->cursor;
468}
469
470static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
471{
472 DPAA_ASSERT(eqcr->busy);
18058822 473 DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK));
c535e923
CM		 474 DPAA_ASSERT(eqcr->available >= 1);
475}
476
477static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
478{
479 struct qm_eqcr *eqcr = &portal->eqcr;
480 struct qm_eqcr_entry *eqcursor;
481
482 eqcr_commit_checks(eqcr);
483 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
484 dma_wmb();
485 eqcursor = eqcr->cursor;
486 eqcursor->_ncw_verb = myverb | eqcr->vbit;
487 dpaa_flush(eqcursor);
488 eqcr_inc(eqcr);
489 eqcr->available--;
490#ifdef CONFIG_FSL_DPAA_CHECKING
491 eqcr->busy = 0;
492#endif
493}
494
495static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
496{
497 qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA);
498}
499
500static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
501{
502 struct qm_eqcr *eqcr = &portal->eqcr;
503 u8 diff, old_ci = eqcr->ci;
504
505 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1);
506 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
507 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
508 eqcr->available += diff;
509 return diff;
510}
511
512static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
513{
514 struct qm_eqcr *eqcr = &portal->eqcr;
515
516 eqcr->ithresh = ithresh;
517 qm_out(portal, QM_REG_EQCR_ITR, ithresh);
518}
519
520static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
521{
522 struct qm_eqcr *eqcr = &portal->eqcr;
523
524 return eqcr->available;
525}
526
527static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
528{
529 struct qm_eqcr *eqcr = &portal->eqcr;
530
531 return QM_EQCR_SIZE - 1 - eqcr->available;
532}
533
534/* --- DQRR API --- */
535
536#define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry))
537#define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT)
538
539static const struct qm_dqrr_entry *dqrr_carryclear(
540 const struct qm_dqrr_entry *p)
541{
542 uintptr_t addr = (uintptr_t)p;
543
544 addr &= ~DQRR_CARRY;
545
546 return (const struct qm_dqrr_entry *)addr;
547}
548
549static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e)
550{
551 return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1);
552}
553
554static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e)
555{
556 return dqrr_carryclear(e + 1);
557}
558
559static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
560{
561 qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) |
562 ((mf & (QM_DQRR_SIZE - 1)) << 20));
563}
564
565static inline int qm_dqrr_init(struct qm_portal *portal,
566 const struct qm_portal_config *config,
567 enum qm_dqrr_dmode dmode,
568 enum qm_dqrr_pmode pmode,
569 enum qm_dqrr_cmode cmode, u8 max_fill)
570{
571 struct qm_dqrr *dqrr = &portal->dqrr;
572 u32 cfg;
573
574 /* Make sure the DQRR will be idle when we enable */
575 qm_out(portal, QM_REG_DQRR_SDQCR, 0);
576 qm_out(portal, QM_REG_DQRR_VDQCR, 0);
577 qm_out(portal, QM_REG_DQRR_PDQCR, 0);
578 dqrr->ring = portal->addr.ce + QM_CL_DQRR;
579 dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
580 dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
581 dqrr->cursor = dqrr->ring + dqrr->ci;
582 dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
583 dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ?
584 QM_DQRR_VERB_VBIT : 0;
585 dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR);
586#ifdef CONFIG_FSL_DPAA_CHECKING
587 dqrr->dmode = dmode;
588 dqrr->pmode = pmode;
589 dqrr->cmode = cmode;
590#endif
591 /* Invalidate every ring entry before beginning */
592 for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
593 dpaa_invalidate(qm_cl(dqrr->ring, cfg));
594 cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) |
595 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
596 ((dmode & 1) << 18) | /* DP */
597 ((cmode & 3) << 16) | /* DCM */
598 0xa0 | /* RE+SE */
599 (0 ? 0x40 : 0) | /* Ignore RP */
600 (0 ? 0x10 : 0); /* Ignore SP */
601 qm_out(portal, QM_REG_CFG, cfg);
602 qm_dqrr_set_maxfill(portal, max_fill);
603 return 0;
604}
605
606static inline void qm_dqrr_finish(struct qm_portal *portal)
607{
608#ifdef CONFIG_FSL_DPAA_CHECKING
609 struct qm_dqrr *dqrr = &portal->dqrr;
610
611 if (dqrr->cmode != qm_dqrr_cdc &&
612 dqrr->ci != dqrr_ptr2idx(dqrr->cursor))
613 pr_crit("Ignoring completed DQRR entries\n");
614#endif
615}
616
617static inline const struct qm_dqrr_entry *qm_dqrr_current(
618 struct qm_portal *portal)
619{
620 struct qm_dqrr *dqrr = &portal->dqrr;
621
622 if (!dqrr->fill)
623 return NULL;
624 return dqrr->cursor;
625}
626
627static inline u8 qm_dqrr_next(struct qm_portal *portal)
628{
629 struct qm_dqrr *dqrr = &portal->dqrr;
630
631 DPAA_ASSERT(dqrr->fill);
632 dqrr->cursor = dqrr_inc(dqrr->cursor);
633 return --dqrr->fill;
634}
635
636static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
637{
638 struct qm_dqrr *dqrr = &portal->dqrr;
639 struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
640
641 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
642#ifndef CONFIG_FSL_PAMU
643 /*
644 * If PAMU is not available we need to invalidate the cache.
645 * When PAMU is available the cache is updated by stash
646 */
647 dpaa_invalidate_touch_ro(res);
648#endif
649 /*
650 * when accessing 'verb', use __raw_readb() to ensure that compiler
651 * inlining doesn't try to optimise out "excess reads".
652 */
653 if ((__raw_readb(&res->verb) & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
654 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
655 if (!dqrr->pi)
656 dqrr->vbit ^= QM_DQRR_VERB_VBIT;
657 dqrr->fill++;
658 }
659}
660
661static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
662 const struct qm_dqrr_entry *dq,
663 int park)
664{
665 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
666 int idx = dqrr_ptr2idx(dq);
667
668 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
669 DPAA_ASSERT((dqrr->ring + idx) == dq);
670 DPAA_ASSERT(idx < QM_DQRR_SIZE);
671 qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
672 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
673 idx); /* DQRR_DCAP::DCAP_CI */
674}
675
676static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask)
677{
678 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
679
680 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
681 qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
682 (bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
683}
684
685static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
686{
687 qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr);
688}
689
690static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
691{
692 qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr);
693}
694
695static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
696{
697 qm_out(portal, QM_REG_DQRR_ITR, ithresh);
698}
699
700/* --- MR API --- */
701
702#define MR_SHIFT ilog2(sizeof(union qm_mr_entry))
703#define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT)
704
705static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p)
706{
707 uintptr_t addr = (uintptr_t)p;
708
709 addr &= ~MR_CARRY;
710
711 return (union qm_mr_entry *)addr;
712}
713
714static inline int mr_ptr2idx(const union qm_mr_entry *e)
715{
716 return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1);
717}
718
719static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e)
720{
721 return mr_carryclear(e + 1);
722}
723
724static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode,
725 enum qm_mr_cmode cmode)
726{
727 struct qm_mr *mr = &portal->mr;
728 u32 cfg;
729
730 mr->ring = portal->addr.ce + QM_CL_MR;
731 mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1);
732 mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1);
733 mr->cursor = mr->ring + mr->ci;
734 mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
735 mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE)
736 ? QM_MR_VERB_VBIT : 0;
737 mr->ithresh = qm_in(portal, QM_REG_MR_ITR);
738#ifdef CONFIG_FSL_DPAA_CHECKING
739 mr->pmode = pmode;
740 mr->cmode = cmode;
741#endif
742 cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) |
743 ((cmode & 1) << 8); /* QCSP_CFG:MM */
744 qm_out(portal, QM_REG_CFG, cfg);
745 return 0;
746}
747
748static inline void qm_mr_finish(struct qm_portal *portal)
749{
750 struct qm_mr *mr = &portal->mr;
751
752 if (mr->ci != mr_ptr2idx(mr->cursor))
753 pr_crit("Ignoring completed MR entries\n");
754}
755
756static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal)
757{
758 struct qm_mr *mr = &portal->mr;
759
760 if (!mr->fill)
761 return NULL;
762 return mr->cursor;
763}
764
765static inline int qm_mr_next(struct qm_portal *portal)
766{
767 struct qm_mr *mr = &portal->mr;
768
769 DPAA_ASSERT(mr->fill);
770 mr->cursor = mr_inc(mr->cursor);
771 return --mr->fill;
772}
773
774static inline void qm_mr_pvb_update(struct qm_portal *portal)
775{
776 struct qm_mr *mr = &portal->mr;
777 union qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
778
779 DPAA_ASSERT(mr->pmode == qm_mr_pvb);
780 /*
781 * when accessing 'verb', use __raw_readb() to ensure that compiler
782 * inlining doesn't try to optimise out "excess reads".
783 */
784 if ((__raw_readb(&res->verb) & QM_MR_VERB_VBIT) == mr->vbit) {
785 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
786 if (!mr->pi)
787 mr->vbit ^= QM_MR_VERB_VBIT;
788 mr->fill++;
789 res = mr_inc(res);
790 }
791 dpaa_invalidate_touch_ro(res);
792}
793
794static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
795{
796 struct qm_mr *mr = &portal->mr;
797
798 DPAA_ASSERT(mr->cmode == qm_mr_cci);
799 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
800 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
801}
802
803static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
804{
805 struct qm_mr *mr = &portal->mr;
806
807 DPAA_ASSERT(mr->cmode == qm_mr_cci);
808 mr->ci = mr_ptr2idx(mr->cursor);
809 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
810}
811
812static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
813{
814 qm_out(portal, QM_REG_MR_ITR, ithresh);
815}
816
817/* --- Management command API --- */
818
819static inline int qm_mc_init(struct qm_portal *portal)
820{
821 struct qm_mc *mc = &portal->mc;
822
823 mc->cr = portal->addr.ce + QM_CL_CR;
824 mc->rr = portal->addr.ce + QM_CL_RR0;
825 mc->rridx = (__raw_readb(&mc->cr->_ncw_verb) & QM_MCC_VERB_VBIT)
826 ? 0 : 1;
827 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
828#ifdef CONFIG_FSL_DPAA_CHECKING
829 mc->state = qman_mc_idle;
830#endif
831 return 0;
832}
833
834static inline void qm_mc_finish(struct qm_portal *portal)
835{
836#ifdef CONFIG_FSL_DPAA_CHECKING
837 struct qm_mc *mc = &portal->mc;
838
839 DPAA_ASSERT(mc->state == qman_mc_idle);
840 if (mc->state != qman_mc_idle)
841 pr_crit("Losing incomplete MC command\n");
842#endif
843}
844
845static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal)
846{
847 struct qm_mc *mc = &portal->mc;
848
849 DPAA_ASSERT(mc->state == qman_mc_idle);
850#ifdef CONFIG_FSL_DPAA_CHECKING
851 mc->state = qman_mc_user;
852#endif
853 dpaa_zero(mc->cr);
854 return mc->cr;
855}
856
857static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
858{
859 struct qm_mc *mc = &portal->mc;
860 union qm_mc_result *rr = mc->rr + mc->rridx;
861
862 DPAA_ASSERT(mc->state == qman_mc_user);
863 dma_wmb();
864 mc->cr->_ncw_verb = myverb | mc->vbit;
865 dpaa_flush(mc->cr);
866 dpaa_invalidate_touch_ro(rr);
867#ifdef CONFIG_FSL_DPAA_CHECKING
868 mc->state = qman_mc_hw;
869#endif
870}
871
872static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)
873{
874 struct qm_mc *mc = &portal->mc;
875 union qm_mc_result *rr = mc->rr + mc->rridx;
876
877 DPAA_ASSERT(mc->state == qman_mc_hw);
878 /*
879 * The inactive response register's verb byte always returns zero until
880 * its command is submitted and completed. This includes the valid-bit,
881 * in case you were wondering...
882 */
883 if (!__raw_readb(&rr->verb)) {
884 dpaa_invalidate_touch_ro(rr);
885 return NULL;
886 }
887 mc->rridx ^= 1;
888 mc->vbit ^= QM_MCC_VERB_VBIT;
889#ifdef CONFIG_FSL_DPAA_CHECKING
890 mc->state = qman_mc_idle;
891#endif
892 return rr;
893}
894
895static inline int qm_mc_result_timeout(struct qm_portal *portal,
896 union qm_mc_result **mcr)
897{
898 int timeout = QM_MCR_TIMEOUT;
899
900 do {
901 *mcr = qm_mc_result(portal);
902 if (*mcr)
903 break;
904 udelay(1);
905 } while (--timeout);
906
907 return timeout;
908}
909
910static inline void fq_set(struct qman_fq *fq, u32 mask)
911{
912 set_bits(mask, &fq->flags);
913}
914
915static inline void fq_clear(struct qman_fq *fq, u32 mask)
916{
917 clear_bits(mask, &fq->flags);
918}
919
920static inline int fq_isset(struct qman_fq *fq, u32 mask)
921{
922 return fq->flags & mask;
923}
924
925static inline int fq_isclear(struct qman_fq *fq, u32 mask)
926{
927 return !(fq->flags & mask);
928}
929
930struct qman_portal {
931 struct qm_portal p;
932 /* PORTAL_BITS_*** - dynamic, strictly internal */
933 unsigned long bits;
934 /* interrupt sources processed by portal_isr(), configurable */
935 unsigned long irq_sources;
936 u32 use_eqcr_ci_stashing;
937 /* only 1 volatile dequeue at a time */
938 struct qman_fq *vdqcr_owned;
939 u32 sdqcr;
940 /* probing time config params for cpu-affine portals */
941 const struct qm_portal_config *config;
c535e923
CM		 942 /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
943 struct qman_cgrs *cgrs;
944 /* linked-list of CSCN handlers. */
945 struct list_head cgr_cbs;
946 /* list lock */
947 spinlock_t cgr_lock;
948 struct work_struct congestion_work;
949 struct work_struct mr_work;
950 char irqname[MAX_IRQNAME];
951};
952
953static cpumask_t affine_mask;
954static DEFINE_SPINLOCK(affine_mask_lock);
955static u16 affine_channels[NR_CPUS];
956static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal);
957struct qman_portal *affine_portals[NR_CPUS];
958
959static inline struct qman_portal *get_affine_portal(void)
960{
961 return &get_cpu_var(qman_affine_portal);
962}
963
964static inline void put_affine_portal(void)
965{
966 put_cpu_var(qman_affine_portal);
967}
968
969static struct workqueue_struct *qm_portal_wq;
970
971int qman_wq_alloc(void)
972{
973 qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1);
974 if (!qm_portal_wq)
975 return -ENOMEM;
976 return 0;
977}
978
979/*
980 * This is what everything can wait on, even if it migrates to a different cpu
981 * to the one whose affine portal it is waiting on.
982 */
983static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
984
985static struct qman_fq **fq_table;
986static u32 num_fqids;
987
988int qman_alloc_fq_table(u32 _num_fqids)
989{
990 num_fqids = _num_fqids;
991
992 fq_table = vzalloc(num_fqids * 2 * sizeof(struct qman_fq *));
993 if (!fq_table)
994 return -ENOMEM;
995
996 pr_debug("Allocated fq lookup table at %p, entry count %u\n",
997 fq_table, num_fqids * 2);
998 return 0;
999}
1000
1001static struct qman_fq *idx_to_fq(u32 idx)
1002{
1003 struct qman_fq *fq;
1004
1005#ifdef CONFIG_FSL_DPAA_CHECKING
1006 if (WARN_ON(idx >= num_fqids * 2))
1007 return NULL;
1008#endif
1009 fq = fq_table[idx];
1010 DPAA_ASSERT(!fq || idx == fq->idx);
1011
1012 return fq;
1013}
1014
1015/*
1016 * Only returns full-service fq objects, not enqueue-only
1017 * references (QMAN_FQ_FLAG_NO_MODIFY).
1018 */
1019static struct qman_fq *fqid_to_fq(u32 fqid)
1020{
1021 return idx_to_fq(fqid * 2);
1022}
1023
1024static struct qman_fq *tag_to_fq(u32 tag)
1025{
1026#if BITS_PER_LONG == 64
1027 return idx_to_fq(tag);
1028#else
1029 return (struct qman_fq *)tag;
1030#endif
1031}
1032
1033static u32 fq_to_tag(struct qman_fq *fq)
1034{
1035#if BITS_PER_LONG == 64
1036 return fq->idx;
1037#else
1038 return (u32)fq;
1039#endif
1040}
1041
1042static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
1043static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1044 unsigned int poll_limit);
1045static void qm_congestion_task(struct work_struct *work);
1046static void qm_mr_process_task(struct work_struct *work);
1047
1048static irqreturn_t portal_isr(int irq, void *ptr)
1049{
1050 struct qman_portal *p = ptr;
1051
1052 u32 clear = QM_DQAVAIL_MASK | p->irq_sources;
1053 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources;
1054
1055 if (unlikely(!is))
1056 return IRQ_NONE;
1057
1058 /* DQRR-handling if it's interrupt-driven */
1059 if (is & QM_PIRQ_DQRI)
1060 __poll_portal_fast(p, QMAN_POLL_LIMIT);
1061 /* Handling of anything else that's interrupt-driven */
1062 clear |= __poll_portal_slow(p, is);
1063 qm_out(&p->p, QM_REG_ISR, clear);
1064 return IRQ_HANDLED;
1065}
1066
1067static int drain_mr_fqrni(struct qm_portal *p)
1068{
1069 const union qm_mr_entry *msg;
1070loop:
1071 msg = qm_mr_current(p);
1072 if (!msg) {
1073 /*
1074 * if MR was full and h/w had other FQRNI entries to produce, we
1075 * need to allow it time to produce those entries once the
1076 * existing entries are consumed. A worst-case situation
1077 * (fully-loaded system) means h/w sequencers may have to do 3-4
1078 * other things before servicing the portal's MR pump, each of
1079 * which (if slow) may take ~50 qman cycles (which is ~200
1080 * processor cycles). So rounding up and then multiplying this
1081 * worst-case estimate by a factor of 10, just to be
1082 * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
1083 * one entry at a time, so h/w has an opportunity to produce new
1084 * entries well before the ring has been fully consumed, so
1085 * we're being *really* paranoid here.
1086 */
7ce2e934 1087 msleep(1);
c535e923
CM		 1088 msg = qm_mr_current(p);
1089 if (!msg)
1090 return 0;
1091 }
1092 if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
1093 /* We aren't draining anything but FQRNIs */
1094 pr_err("Found verb 0x%x in MR\n", msg->verb);
1095 return -1;
1096 }
1097 qm_mr_next(p);
1098 qm_mr_cci_consume(p, 1);
1099 goto loop;
1100}
1101
1102static int qman_create_portal(struct qman_portal *portal,
1103 const struct qm_portal_config *c,
1104 const struct qman_cgrs *cgrs)
1105{
1106 struct qm_portal *p;
c535e923
CM		 1107 int ret;
1108 u32 isdr;
1109
1110 p = &portal->p;
1111
1112#ifdef CONFIG_FSL_PAMU
1113 /* PAMU is required for stashing */
1114 portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
1115#else
1116 portal->use_eqcr_ci_stashing = 0;
1117#endif
1118 /*
1119 * prep the low-level portal struct with the mapped addresses from the
1120 * config, everything that follows depends on it and "config" is more
1121 * for (de)reference
1122 */
1123 p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
1124 p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
1125 /*
1126 * If CI-stashing is used, the current defaults use a threshold of 3,
1127 * and stash with high-than-DQRR priority.
1128 */
1129 if (qm_eqcr_init(p, qm_eqcr_pvb,
1130 portal->use_eqcr_ci_stashing ? 3 : 0, 1)) {
1131 dev_err(c->dev, "EQCR initialisation failed\n");
1132 goto fail_eqcr;
1133 }
1134 if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
1135 qm_dqrr_cdc, DQRR_MAXFILL)) {
1136 dev_err(c->dev, "DQRR initialisation failed\n");
1137 goto fail_dqrr;
1138 }
1139 if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
1140 dev_err(c->dev, "MR initialisation failed\n");
1141 goto fail_mr;
1142 }
1143 if (qm_mc_init(p)) {
1144 dev_err(c->dev, "MC initialisation failed\n");
1145 goto fail_mc;
1146 }
1147 /* static interrupt-gating controls */
1148 qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH);
1149 qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH);
1150 qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD);
1151 portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL);
1152 if (!portal->cgrs)
1153 goto fail_cgrs;
1154 /* initial snapshot is no-depletion */
1155 qman_cgrs_init(&portal->cgrs[1]);
1156 if (cgrs)
1157 portal->cgrs[0] = *cgrs;
1158 else
1159 /* if the given mask is NULL, assume all CGRs can be seen */
1160 qman_cgrs_fill(&portal->cgrs[0]);
1161 INIT_LIST_HEAD(&portal->cgr_cbs);
1162 spin_lock_init(&portal->cgr_lock);
1163 INIT_WORK(&portal->congestion_work, qm_congestion_task);
1164 INIT_WORK(&portal->mr_work, qm_mr_process_task);
1165 portal->bits = 0;
1166 portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
1167 QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
1168 QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
c535e923
CM		 1169 isdr = 0xffffffff;
1170 qm_out(p, QM_REG_ISDR, isdr);
1171 portal->irq_sources = 0;
1172 qm_out(p, QM_REG_IER, 0);
1173 qm_out(p, QM_REG_ISR, 0xffffffff);
1174 snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
1175 if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
1176 dev_err(c->dev, "request_irq() failed\n");
1177 goto fail_irq;
1178 }
1179 if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
1180 irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
1181 dev_err(c->dev, "irq_set_affinity() failed\n");
1182 goto fail_affinity;
1183 }
1184
1185 /* Need EQCR to be empty before continuing */
1186 isdr &= ~QM_PIRQ_EQCI;
1187 qm_out(p, QM_REG_ISDR, isdr);
1188 ret = qm_eqcr_get_fill(p);
1189 if (ret) {
1190 dev_err(c->dev, "EQCR unclean\n");
1191 goto fail_eqcr_empty;
1192 }
1193 isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
1194 qm_out(p, QM_REG_ISDR, isdr);
1195 if (qm_dqrr_current(p)) {
1196 dev_err(c->dev, "DQRR unclean\n");
1197 qm_dqrr_cdc_consume_n(p, 0xffff);
1198 }
1199 if (qm_mr_current(p) && drain_mr_fqrni(p)) {
1200 /* special handling, drain just in case it's a few FQRNIs */
1201 const union qm_mr_entry *e = qm_mr_current(p);
1202
b6e969db
CM		 1203 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x, addr 0x%llx\n",
1204 e->verb, e->ern.rc, qm_fd_addr_get64(&e->ern.fd));
c535e923
CM		 1205 goto fail_dqrr_mr_empty;
1206 }
1207 /* Success */
1208 portal->config = c;
1209 qm_out(p, QM_REG_ISDR, 0);
1210 qm_out(p, QM_REG_IIR, 0);
1211 /* Write a sane SDQCR */
1212 qm_dqrr_sdqcr_set(p, portal->sdqcr);
1213 return 0;
1214
1215fail_dqrr_mr_empty:
1216fail_eqcr_empty:
1217fail_affinity:
1218 free_irq(c->irq, portal);
1219fail_irq:
c535e923
CM		 1220 kfree(portal->cgrs);
1221fail_cgrs:
1222 qm_mc_finish(p);
1223fail_mc:
1224 qm_mr_finish(p);
1225fail_mr:
1226 qm_dqrr_finish(p);
1227fail_dqrr:
1228 qm_eqcr_finish(p);
1229fail_eqcr:
1230 return -EIO;
1231}
1232
1233struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
1234 const struct qman_cgrs *cgrs)
1235{
1236 struct qman_portal *portal;
1237 int err;
1238
1239 portal = &per_cpu(qman_affine_portal, c->cpu);
1240 err = qman_create_portal(portal, c, cgrs);
1241 if (err)
1242 return NULL;
1243
1244 spin_lock(&affine_mask_lock);
1245 cpumask_set_cpu(c->cpu, &affine_mask);
1246 affine_channels[c->cpu] = c->channel;
1247 affine_portals[c->cpu] = portal;
1248 spin_unlock(&affine_mask_lock);
1249
1250 return portal;
1251}
1252
1253static void qman_destroy_portal(struct qman_portal *qm)
1254{
1255 const struct qm_portal_config *pcfg;
1256
1257 /* Stop dequeues on the portal */
1258 qm_dqrr_sdqcr_set(&qm->p, 0);
1259
1260 /*
1261 * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
1262 * something related to QM_PIRQ_EQCI, this may need fixing.
1263 * Also, due to the prefetching model used for CI updates in the enqueue
1264 * path, this update will only invalidate the CI cacheline *after*
1265 * working on it, so we need to call this twice to ensure a full update
1266 * irrespective of where the enqueue processing was at when the teardown
1267 * began.
1268 */
1269 qm_eqcr_cce_update(&qm->p);
1270 qm_eqcr_cce_update(&qm->p);
1271 pcfg = qm->config;
1272
1273 free_irq(pcfg->irq, qm);
1274
1275 kfree(qm->cgrs);
1276 qm_mc_finish(&qm->p);
1277 qm_mr_finish(&qm->p);
1278 qm_dqrr_finish(&qm->p);
1279 qm_eqcr_finish(&qm->p);
1280
c535e923
CM		 1281 qm->config = NULL;
1282}
1283
1284const struct qm_portal_config *qman_destroy_affine_portal(void)
1285{
1286 struct qman_portal *qm = get_affine_portal();
1287 const struct qm_portal_config *pcfg;
1288 int cpu;
1289
1290 pcfg = qm->config;
1291 cpu = pcfg->cpu;
1292
1293 qman_destroy_portal(qm);
1294
1295 spin_lock(&affine_mask_lock);
1296 cpumask_clear_cpu(cpu, &affine_mask);
1297 spin_unlock(&affine_mask_lock);
1298 put_affine_portal();
1299 return pcfg;
1300}
1301
1302/* Inline helper to reduce nesting in __poll_portal_slow() */
1303static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
1304 const union qm_mr_entry *msg, u8 verb)
1305{
1306 switch (verb) {
1307 case QM_MR_VERB_FQRL:
1308 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
1309 fq_clear(fq, QMAN_FQ_STATE_ORL);
1310 break;
1311 case QM_MR_VERB_FQRN:
1312 DPAA_ASSERT(fq->state == qman_fq_state_parked ||
1313 fq->state == qman_fq_state_sched);
1314 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
1315 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
1316 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
1317 fq_set(fq, QMAN_FQ_STATE_NE);
1318 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
1319 fq_set(fq, QMAN_FQ_STATE_ORL);
1320 fq->state = qman_fq_state_retired;
1321 break;
1322 case QM_MR_VERB_FQPN:
1323 DPAA_ASSERT(fq->state == qman_fq_state_sched);
1324 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
1325 fq->state = qman_fq_state_parked;
1326 }
1327}
1328
1329static void qm_congestion_task(struct work_struct *work)
1330{
1331 struct qman_portal *p = container_of(work, struct qman_portal,
1332 congestion_work);
1333 struct qman_cgrs rr, c;
1334 union qm_mc_result *mcr;
1335 struct qman_cgr *cgr;
1336
1337 spin_lock(&p->cgr_lock);
1338 qm_mc_start(&p->p);
1339 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1340 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1341 spin_unlock(&p->cgr_lock);
1342 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
e21c7316 1343 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
c535e923
CM		 1344 return;
1345 }
1346 /* mask out the ones I'm not interested in */
1347 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state,
1348 &p->cgrs[0]);
1349 /* check previous snapshot for delta, enter/exit congestion */
1350 qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
1351 /* update snapshot */
1352 qman_cgrs_cp(&p->cgrs[1], &rr);
1353 /* Invoke callback */
1354 list_for_each_entry(cgr, &p->cgr_cbs, node)
1355 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
1356 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
1357 spin_unlock(&p->cgr_lock);
e21c7316 1358 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
c535e923
CM		 1359}
1360
1361static void qm_mr_process_task(struct work_struct *work)
1362{
1363 struct qman_portal *p = container_of(work, struct qman_portal,
1364 mr_work);
1365 const union qm_mr_entry *msg;
1366 struct qman_fq *fq;
1367 u8 verb, num = 0;
1368
1369 preempt_disable();
1370
1371 while (1) {
1372 qm_mr_pvb_update(&p->p);
1373 msg = qm_mr_current(&p->p);
1374 if (!msg)
1375 break;
1376
1377 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
1378 /* The message is a software ERN iff the 0x20 bit is clear */
1379 if (verb & 0x20) {
1380 switch (verb) {
1381 case QM_MR_VERB_FQRNI:
1382 /* nada, we drop FQRNIs on the floor */
1383 break;
1384 case QM_MR_VERB_FQRN:
1385 case QM_MR_VERB_FQRL:
1386 /* Lookup in the retirement table */
d6753c7e 1387 fq = fqid_to_fq(qm_fqid_get(&msg->fq));
c535e923
CM		 1388 if (WARN_ON(!fq))
1389 break;
1390 fq_state_change(p, fq, msg, verb);
1391 if (fq->cb.fqs)
1392 fq->cb.fqs(p, fq, msg);
1393 break;
1394 case QM_MR_VERB_FQPN:
1395 /* Parked */
18058822 1396 fq = tag_to_fq(be32_to_cpu(msg->fq.context_b));
c535e923
CM		 1397 fq_state_change(p, fq, msg, verb);
1398 if (fq->cb.fqs)
1399 fq->cb.fqs(p, fq, msg);
1400 break;
1401 case QM_MR_VERB_DC_ERN:
1402 /* DCP ERN */
1403 pr_crit_once("Leaking DCP ERNs!\n");
1404 break;
1405 default:
1406 pr_crit("Invalid MR verb 0x%02x\n", verb);
1407 }
1408 } else {
1409 /* Its a software ERN */
18058822 1410 fq = tag_to_fq(be32_to_cpu(msg->ern.tag));
c535e923
CM		 1411 fq->cb.ern(p, fq, msg);
1412 }
1413 num++;
1414 qm_mr_next(&p->p);
1415 }
1416
1417 qm_mr_cci_consume(&p->p, num);
e21c7316 1418 qman_p_irqsource_add(p, QM_PIRQ_MRI);
c535e923
CM		 1419 preempt_enable();
1420}
1421
1422static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
1423{
1424 if (is & QM_PIRQ_CSCI) {
e21c7316 1425 qman_p_irqsource_remove(p, QM_PIRQ_CSCI);
c535e923
CM		 1426 queue_work_on(smp_processor_id(), qm_portal_wq,
1427 &p->congestion_work);
1428 }
1429
1430 if (is & QM_PIRQ_EQRI) {
1431 qm_eqcr_cce_update(&p->p);
1432 qm_eqcr_set_ithresh(&p->p, 0);
1433 wake_up(&affine_queue);
1434 }
1435
1436 if (is & QM_PIRQ_MRI) {
e21c7316 1437 qman_p_irqsource_remove(p, QM_PIRQ_MRI);
c535e923
CM		 1438 queue_work_on(smp_processor_id(), qm_portal_wq,
1439 &p->mr_work);
1440 }
1441
1442 return is;
1443}
1444
1445/*
1446 * remove some slowish-path stuff from the "fast path" and make sure it isn't
1447 * inlined.
1448 */
1449static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
1450{
1451 p->vdqcr_owned = NULL;
1452 fq_clear(fq, QMAN_FQ_STATE_VDQCR);
1453 wake_up(&affine_queue);
1454}
1455
1456/*
1457 * The only states that would conflict with other things if they ran at the
1458 * same time on the same cpu are:
1459 *
1460 * (i) setting/clearing vdqcr_owned, and
1461 * (ii) clearing the NE (Not Empty) flag.
1462 *
1463 * Both are safe. Because;
1464 *
1465 * (i) this clearing can only occur after qman_volatile_dequeue() has set the
1466 * vdqcr_owned field (which it does before setting VDQCR), and
1467 * qman_volatile_dequeue() blocks interrupts and preemption while this is
1468 * done so that we can't interfere.
1469 * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
1470 * with (i) that API prevents us from interfering until it's safe.
1471 *
1472 * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far
1473 * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
1474 * advantage comes from this function not having to "lock" anything at all.
1475 *
1476 * Note also that the callbacks are invoked at points which are safe against the
1477 * above potential conflicts, but that this function itself is not re-entrant
1478 * (this is because the function tracks one end of each FIFO in the portal and
1479 * we do *not* want to lock that). So the consequence is that it is safe for
1480 * user callbacks to call into any QMan API.
1481 */
1482static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1483 unsigned int poll_limit)
1484{
1485 const struct qm_dqrr_entry *dq;
1486 struct qman_fq *fq;
1487 enum qman_cb_dqrr_result res;
1488 unsigned int limit = 0;
1489
1490 do {
1491 qm_dqrr_pvb_update(&p->p);
1492 dq = qm_dqrr_current(&p->p);
1493 if (!dq)
1494 break;
1495
1496 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
1497 /*
efe848cd 1498 * VDQCR: don't trust context_b as the FQ may have
c535e923
CM		 1499 * been configured for h/w consumption and we're
1500 * draining it post-retirement.
1501 */
1502 fq = p->vdqcr_owned;
1503 /*
1504 * We only set QMAN_FQ_STATE_NE when retiring, so we
1505 * only need to check for clearing it when doing
1506 * volatile dequeues. It's one less thing to check
1507 * in the critical path (SDQCR).
1508 */
1509 if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1510 fq_clear(fq, QMAN_FQ_STATE_NE);
1511 /*
1512 * This is duplicated from the SDQCR code, but we
1513 * have stuff to do before *and* after this callback,
1514 * and we don't want multiple if()s in the critical
1515 * path (SDQCR).
1516 */
1517 res = fq->cb.dqrr(p, fq, dq);
1518 if (res == qman_cb_dqrr_stop)
1519 break;
1520 /* Check for VDQCR completion */
1521 if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1522 clear_vdqcr(p, fq);
1523 } else {
efe848cd 1524 /* SDQCR: context_b points to the FQ */
18058822 1525 fq = tag_to_fq(be32_to_cpu(dq->context_b));
c535e923
CM		 1526 /* Now let the callback do its stuff */
1527 res = fq->cb.dqrr(p, fq, dq);
1528 /*
1529 * The callback can request that we exit without
1530 * consuming this entry nor advancing;
1531 */
1532 if (res == qman_cb_dqrr_stop)
1533 break;
1534 }
1535 /* Interpret 'dq' from a driver perspective. */
1536 /*
1537 * Parking isn't possible unless HELDACTIVE was set. NB,
1538 * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1539 * check for HELDACTIVE to cover both.
1540 */
1541 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1542 (res != qman_cb_dqrr_park));
1543 /* just means "skip it, I'll consume it myself later on" */
1544 if (res != qman_cb_dqrr_defer)
1545 qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1546 res == qman_cb_dqrr_park);
1547 /* Move forward */
1548 qm_dqrr_next(&p->p);
1549 /*
1550 * Entry processed and consumed, increment our counter. The
1551 * callback can request that we exit after consuming the
1552 * entry, and we also exit if we reach our processing limit,
1553 * so loop back only if neither of these conditions is met.
1554 */
1555 } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1556
1557 return limit;
1558}
1559
1560void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
1561{
1562 unsigned long irqflags;
1563
1564 local_irq_save(irqflags);
1565 set_bits(bits & QM_PIRQ_VISIBLE, &p->irq_sources);
1566 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1567 local_irq_restore(irqflags);
1568}
1569EXPORT_SYMBOL(qman_p_irqsource_add);
1570
1571void qman_p_irqsource_remove(struct qman_portal *p, u32 bits)
1572{
1573 unsigned long irqflags;
1574 u32 ier;
1575
1576 /*
1577 * Our interrupt handler only processes+clears status register bits that
1578 * are in p->irq_sources. As we're trimming that mask, if one of them
1579 * were to assert in the status register just before we remove it from
1580 * the enable register, there would be an interrupt-storm when we
1581 * release the IRQ lock. So we wait for the enable register update to
1582 * take effect in h/w (by reading it back) and then clear all other bits
1583 * in the status register. Ie. we clear them from ISR once it's certain
1584 * IER won't allow them to reassert.
1585 */
1586 local_irq_save(irqflags);
1587 bits &= QM_PIRQ_VISIBLE;
1588 clear_bits(bits, &p->irq_sources);
1589 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1590 ier = qm_in(&p->p, QM_REG_IER);
1591 /*
1592 * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a
1593 * data-dependency, ie. to protect against re-ordering.
1594 */
1595 qm_out(&p->p, QM_REG_ISR, ~ier);
1596 local_irq_restore(irqflags);
1597}
1598EXPORT_SYMBOL(qman_p_irqsource_remove);
1599
1600const cpumask_t *qman_affine_cpus(void)
1601{
1602 return &affine_mask;
1603}
1604EXPORT_SYMBOL(qman_affine_cpus);
1605
1606u16 qman_affine_channel(int cpu)
1607{
1608 if (cpu < 0) {
1609 struct qman_portal *portal = get_affine_portal();
1610
1611 cpu = portal->config->cpu;
1612 put_affine_portal();
1613 }
1614 WARN_ON(!cpumask_test_cpu(cpu, &affine_mask));
1615 return affine_channels[cpu];
1616}
1617EXPORT_SYMBOL(qman_affine_channel);
1618
1619struct qman_portal *qman_get_affine_portal(int cpu)
1620{
1621 return affine_portals[cpu];
1622}
1623EXPORT_SYMBOL(qman_get_affine_portal);
1624
1625int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit)
1626{
1627 return __poll_portal_fast(p, limit);
1628}
1629EXPORT_SYMBOL(qman_p_poll_dqrr);
1630
1631void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools)
1632{
1633 unsigned long irqflags;
1634
1635 local_irq_save(irqflags);
1636 pools &= p->config->pools;
1637 p->sdqcr |= pools;
1638 qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1639 local_irq_restore(irqflags);
1640}
1641EXPORT_SYMBOL(qman_p_static_dequeue_add);
1642
1643/* Frame queue API */
1644
1645static const char *mcr_result_str(u8 result)
1646{
1647 switch (result) {
1648 case QM_MCR_RESULT_NULL:
1649 return "QM_MCR_RESULT_NULL";
1650 case QM_MCR_RESULT_OK:
1651 return "QM_MCR_RESULT_OK";
1652 case QM_MCR_RESULT_ERR_FQID:
1653 return "QM_MCR_RESULT_ERR_FQID";
1654 case QM_MCR_RESULT_ERR_FQSTATE:
1655 return "QM_MCR_RESULT_ERR_FQSTATE";
1656 case QM_MCR_RESULT_ERR_NOTEMPTY:
1657 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1658 case QM_MCR_RESULT_PENDING:
1659 return "QM_MCR_RESULT_PENDING";
1660 case QM_MCR_RESULT_ERR_BADCOMMAND:
1661 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1662 }
1663 return "<unknown MCR result>";
1664}
1665
1666int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1667{
1668 if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1669 int ret = qman_alloc_fqid(&fqid);
1670
1671 if (ret)
1672 return ret;
1673 }
1674 fq->fqid = fqid;
1675 fq->flags = flags;
1676 fq->state = qman_fq_state_oos;
1677 fq->cgr_groupid = 0;
1678
1679 /* A context_b of 0 is allegedly special, so don't use that fqid */
1680 if (fqid == 0 || fqid >= num_fqids) {
1681 WARN(1, "bad fqid %d\n", fqid);
1682 return -EINVAL;
1683 }
1684
1685 fq->idx = fqid * 2;
1686 if (flags & QMAN_FQ_FLAG_NO_MODIFY)
1687 fq->idx++;
1688
1689 WARN_ON(fq_table[fq->idx]);
1690 fq_table[fq->idx] = fq;
1691
1692 return 0;
1693}
1694EXPORT_SYMBOL(qman_create_fq);
1695
1696void qman_destroy_fq(struct qman_fq *fq)
1697{
1698 /*
1699 * We don't need to lock the FQ as it is a pre-condition that the FQ be
1700 * quiesced. Instead, run some checks.
1701 */
1702 switch (fq->state) {
1703 case qman_fq_state_parked:
1704 case qman_fq_state_oos:
1705 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1706 qman_release_fqid(fq->fqid);
1707
1708 DPAA_ASSERT(fq_table[fq->idx]);
1709 fq_table[fq->idx] = NULL;
1710 return;
1711 default:
1712 break;
1713 }
1714 DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1715}
1716EXPORT_SYMBOL(qman_destroy_fq);
1717
1718u32 qman_fq_fqid(struct qman_fq *fq)
1719{
1720 return fq->fqid;
1721}
1722EXPORT_SYMBOL(qman_fq_fqid);
1723
1724int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1725{
1726 union qm_mc_command *mcc;
1727 union qm_mc_result *mcr;
1728 struct qman_portal *p;
1729 u8 res, myverb;
1730 int ret = 0;
1731
1732 myverb = (flags & QMAN_INITFQ_FLAG_SCHED)
1733 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1734
1735 if (fq->state != qman_fq_state_oos &&
1736 fq->state != qman_fq_state_parked)
1737 return -EINVAL;
1738#ifdef CONFIG_FSL_DPAA_CHECKING
1739 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1740 return -EINVAL;
1741#endif
18058822 1742 if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) {
c535e923 1743 /* And can't be set at the same time as TDTHRESH */
18058822 1744 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH)
c535e923
CM		 1745 return -EINVAL;
1746 }
1747 /* Issue an INITFQ_[PARKED|SCHED] management command */
1748 p = get_affine_portal();
1749 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1750 (fq->state != qman_fq_state_oos &&
1751 fq->state != qman_fq_state_parked)) {
1752 ret = -EBUSY;
1753 goto out;
1754 }
1755 mcc = qm_mc_start(&p->p);
1756 if (opts)
1757 mcc->initfq = *opts;
d6753c7e 1758 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 1759 mcc->initfq.count = 0;
1760 /*
efe848cd 1761 * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a
c535e923
CM		 1762 * demux pointer. Otherwise, the caller-provided value is allowed to
1763 * stand, don't overwrite it.
1764 */
1765 if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1766 dma_addr_t phys_fq;
1767
18058822
CM		 1768 mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB);
1769 mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq));
c535e923
CM		 1770 /*
1771 * and the physical address - NB, if the user wasn't trying to
1772 * set CONTEXTA, clear the stashing settings.
1773 */
18058822
CM		 1774 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1775 QM_INITFQ_WE_CONTEXTA)) {
1776 mcc->initfq.we_mask |=
1777 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
c535e923
CM		 1778 memset(&mcc->initfq.fqd.context_a, 0,
1779 sizeof(mcc->initfq.fqd.context_a));
1780 } else {
0fbeac3b
CM		 1781 struct qman_portal *p = qman_dma_portal;
1782
1783 phys_fq = dma_map_single(p->config->dev, fq,
1784 sizeof(*fq), DMA_TO_DEVICE);
1785 if (dma_mapping_error(p->config->dev, phys_fq)) {
1786 dev_err(p->config->dev, "dma_mapping failed\n");
1787 ret = -EIO;
1788 goto out;
1789 }
1790
c535e923
CM		 1791 qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1792 }
1793 }
1794 if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1795 int wq = 0;
1796
18058822
CM		 1797 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1798 QM_INITFQ_WE_DESTWQ)) {
1799 mcc->initfq.we_mask |=
1800 cpu_to_be16(QM_INITFQ_WE_DESTWQ);
c535e923
CM		 1801 wq = 4;
1802 }
1803 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
1804 }
1805 qm_mc_commit(&p->p, myverb);
1806 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1807 dev_err(p->config->dev, "MCR timeout\n");
1808 ret = -ETIMEDOUT;
1809 goto out;
1810 }
1811
1812 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1813 res = mcr->result;
1814 if (res != QM_MCR_RESULT_OK) {
1815 ret = -EIO;
1816 goto out;
1817 }
1818 if (opts) {
18058822
CM		 1819 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) {
1820 if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE)
c535e923
CM		 1821 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1822 else
1823 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1824 }
18058822 1825 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID)
c535e923
CM		 1826 fq->cgr_groupid = opts->fqd.cgid;
1827 }
1828 fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1829 qman_fq_state_sched : qman_fq_state_parked;
1830
1831out:
1832 put_affine_portal();
1833 return ret;
1834}
1835EXPORT_SYMBOL(qman_init_fq);
1836
1837int qman_schedule_fq(struct qman_fq *fq)
1838{
1839 union qm_mc_command *mcc;
1840 union qm_mc_result *mcr;
1841 struct qman_portal *p;
1842 int ret = 0;
1843
1844 if (fq->state != qman_fq_state_parked)
1845 return -EINVAL;
1846#ifdef CONFIG_FSL_DPAA_CHECKING
1847 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1848 return -EINVAL;
1849#endif
1850 /* Issue a ALTERFQ_SCHED management command */
1851 p = get_affine_portal();
1852 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1853 fq->state != qman_fq_state_parked) {
1854 ret = -EBUSY;
1855 goto out;
1856 }
1857 mcc = qm_mc_start(&p->p);
d6753c7e 1858 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 1859 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1860 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1861 dev_err(p->config->dev, "ALTER_SCHED timeout\n");
1862 ret = -ETIMEDOUT;
1863 goto out;
1864 }
1865
1866 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1867 if (mcr->result != QM_MCR_RESULT_OK) {
1868 ret = -EIO;
1869 goto out;
1870 }
1871 fq->state = qman_fq_state_sched;
1872out:
1873 put_affine_portal();
1874 return ret;
1875}
1876EXPORT_SYMBOL(qman_schedule_fq);
1877
1878int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1879{
1880 union qm_mc_command *mcc;
1881 union qm_mc_result *mcr;
1882 struct qman_portal *p;
1883 int ret;
1884 u8 res;
1885
1886 if (fq->state != qman_fq_state_parked &&
1887 fq->state != qman_fq_state_sched)
1888 return -EINVAL;
1889#ifdef CONFIG_FSL_DPAA_CHECKING
1890 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1891 return -EINVAL;
1892#endif
1893 p = get_affine_portal();
1894 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1895 fq->state == qman_fq_state_retired ||
1896 fq->state == qman_fq_state_oos) {
1897 ret = -EBUSY;
1898 goto out;
1899 }
1900 mcc = qm_mc_start(&p->p);
d6753c7e 1901 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 1902 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1903 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1904 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n");
1905 ret = -ETIMEDOUT;
1906 goto out;
1907 }
1908
1909 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
1910 res = mcr->result;
1911 /*
1912 * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
1913 * and defer the flags until FQRNI or FQRN (respectively) show up. But
1914 * "Friendly" is to process OK immediately, and not set CHANGING. We do
1915 * friendly, otherwise the caller doesn't necessarily have a fully
1916 * "retired" FQ on return even if the retirement was immediate. However
1917 * this does mean some code duplication between here and
1918 * fq_state_change().
1919 */
1920 if (res == QM_MCR_RESULT_OK) {
1921 ret = 0;
1922 /* Process 'fq' right away, we'll ignore FQRNI */
1923 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
1924 fq_set(fq, QMAN_FQ_STATE_NE);
1925 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
1926 fq_set(fq, QMAN_FQ_STATE_ORL);
1927 if (flags)
1928 *flags = fq->flags;
1929 fq->state = qman_fq_state_retired;
1930 if (fq->cb.fqs) {
1931 /*
1932 * Another issue with supporting "immediate" retirement
1933 * is that we're forced to drop FQRNIs, because by the
1934 * time they're seen it may already be "too late" (the
1935 * fq may have been OOS'd and free()'d already). But if
1936 * the upper layer wants a callback whether it's
1937 * immediate or not, we have to fake a "MR" entry to
1938 * look like an FQRNI...
1939 */
1940 union qm_mr_entry msg;
1941
1942 msg.verb = QM_MR_VERB_FQRNI;
1943 msg.fq.fqs = mcr->alterfq.fqs;
d6753c7e 1944 qm_fqid_set(&msg.fq, fq->fqid);
18058822 1945 msg.fq.context_b = cpu_to_be32(fq_to_tag(fq));
c535e923
CM		 1946 fq->cb.fqs(p, fq, &msg);
1947 }
1948 } else if (res == QM_MCR_RESULT_PENDING) {
1949 ret = 1;
1950 fq_set(fq, QMAN_FQ_STATE_CHANGING);
1951 } else {
1952 ret = -EIO;
1953 }
1954out:
1955 put_affine_portal();
1956 return ret;
1957}
1958EXPORT_SYMBOL(qman_retire_fq);
1959
1960int qman_oos_fq(struct qman_fq *fq)
1961{
1962 union qm_mc_command *mcc;
1963 union qm_mc_result *mcr;
1964 struct qman_portal *p;
1965 int ret = 0;
1966
1967 if (fq->state != qman_fq_state_retired)
1968 return -EINVAL;
1969#ifdef CONFIG_FSL_DPAA_CHECKING
1970 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1971 return -EINVAL;
1972#endif
1973 p = get_affine_portal();
1974 if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) ||
1975 fq->state != qman_fq_state_retired) {
1976 ret = -EBUSY;
1977 goto out;
1978 }
1979 mcc = qm_mc_start(&p->p);
d6753c7e 1980 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 1981 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
1982 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1983 ret = -ETIMEDOUT;
1984 goto out;
1985 }
1986 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
1987 if (mcr->result != QM_MCR_RESULT_OK) {
1988 ret = -EIO;
1989 goto out;
1990 }
1991 fq->state = qman_fq_state_oos;
1992out:
1993 put_affine_portal();
1994 return ret;
1995}
1996EXPORT_SYMBOL(qman_oos_fq);
1997
1998int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
1999{
2000 union qm_mc_command *mcc;
2001 union qm_mc_result *mcr;
2002 struct qman_portal *p = get_affine_portal();
2003 int ret = 0;
2004
2005 mcc = qm_mc_start(&p->p);
d6753c7e 2006 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 2007 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2008 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2009 ret = -ETIMEDOUT;
2010 goto out;
2011 }
2012
2013 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2014 if (mcr->result == QM_MCR_RESULT_OK)
2015 *fqd = mcr->queryfq.fqd;
2016 else
2017 ret = -EIO;
2018out:
2019 put_affine_portal();
2020 return ret;
2021}
2022
8496272d 2023int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
c535e923
CM		 2024{
2025 union qm_mc_command *mcc;
2026 union qm_mc_result *mcr;
2027 struct qman_portal *p = get_affine_portal();
2028 int ret = 0;
2029
2030 mcc = qm_mc_start(&p->p);
d6753c7e 2031 qm_fqid_set(&mcc->fq, fq->fqid);
c535e923
CM		 2032 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2033 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2034 ret = -ETIMEDOUT;
2035 goto out;
2036 }
2037
2038 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2039 if (mcr->result == QM_MCR_RESULT_OK)
2040 *np = mcr->queryfq_np;
2041 else if (mcr->result == QM_MCR_RESULT_ERR_FQID)
2042 ret = -ERANGE;
2043 else
2044 ret = -EIO;
2045out:
2046 put_affine_portal();
2047 return ret;
2048}
8496272d 2049EXPORT_SYMBOL(qman_query_fq_np);
c535e923
CM		 2050
2051static int qman_query_cgr(struct qman_cgr *cgr,
2052 struct qm_mcr_querycgr *cgrd)
2053{
2054 union qm_mc_command *mcc;
2055 union qm_mc_result *mcr;
2056 struct qman_portal *p = get_affine_portal();
2057 int ret = 0;
2058
2059 mcc = qm_mc_start(&p->p);
7ff07da0 2060 mcc->cgr.cgid = cgr->cgrid;
c535e923
CM		 2061 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
2062 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2063 ret = -ETIMEDOUT;
2064 goto out;
2065 }
2066 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
2067 if (mcr->result == QM_MCR_RESULT_OK)
2068 *cgrd = mcr->querycgr;
2069 else {
2070 dev_err(p->config->dev, "QUERY_CGR failed: %s\n",
2071 mcr_result_str(mcr->result));
2072 ret = -EIO;
2073 }
2074out:
2075 put_affine_portal();
2076 return ret;
2077}
2078
2079int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result)
2080{
2081 struct qm_mcr_querycgr query_cgr;
2082 int err;
2083
2084 err = qman_query_cgr(cgr, &query_cgr);
2085 if (err)
2086 return err;
2087
2088 *result = !!query_cgr.cgr.cs;
2089 return 0;
2090}
2091EXPORT_SYMBOL(qman_query_cgr_congested);
2092
2093/* internal function used as a wait_event() expression */
2094static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr)
2095{
2096 unsigned long irqflags;
2097 int ret = -EBUSY;
2098
2099 local_irq_save(irqflags);
2100 if (p->vdqcr_owned)
2101 goto out;
2102 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2103 goto out;
2104
2105 fq_set(fq, QMAN_FQ_STATE_VDQCR);
2106 p->vdqcr_owned = fq;
2107 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2108 ret = 0;
2109out:
2110 local_irq_restore(irqflags);
2111 return ret;
2112}
2113
2114static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr)
2115{
2116 int ret;
2117
2118 *p = get_affine_portal();
2119 ret = set_p_vdqcr(*p, fq, vdqcr);
2120 put_affine_portal();
2121 return ret;
2122}
2123
2124static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq,
2125 u32 vdqcr, u32 flags)
2126{
2127 int ret = 0;
2128
2129 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2130 ret = wait_event_interruptible(affine_queue,
2131 !set_vdqcr(p, fq, vdqcr));
2132 else
2133 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr));
2134 return ret;
2135}
2136
2137int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr)
2138{
2139 struct qman_portal *p;
2140 int ret;
2141
2142 if (fq->state != qman_fq_state_parked &&
2143 fq->state != qman_fq_state_retired)
2144 return -EINVAL;
2145 if (vdqcr & QM_VDQCR_FQID_MASK)
2146 return -EINVAL;
2147 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2148 return -EBUSY;
2149 vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2150 if (flags & QMAN_VOLATILE_FLAG_WAIT)
2151 ret = wait_vdqcr_start(&p, fq, vdqcr, flags);
2152 else
2153 ret = set_vdqcr(&p, fq, vdqcr);
2154 if (ret)
2155 return ret;
2156 /* VDQCR is set */
2157 if (flags & QMAN_VOLATILE_FLAG_FINISH) {
2158 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2159 /*
2160 * NB: don't propagate any error - the caller wouldn't
2161 * know whether the VDQCR was issued or not. A signal
2162 * could arrive after returning anyway, so the caller
2163 * can check signal_pending() if that's an issue.
2164 */
2165 wait_event_interruptible(affine_queue,
2166 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2167 else
2168 wait_event(affine_queue,
2169 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2170 }
2171 return 0;
2172}
2173EXPORT_SYMBOL(qman_volatile_dequeue);
2174
2175static void update_eqcr_ci(struct qman_portal *p, u8 avail)
2176{
2177 if (avail)
2178 qm_eqcr_cce_prefetch(&p->p);
2179 else
2180 qm_eqcr_cce_update(&p->p);
2181}
2182
2183int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)
2184{
2185 struct qman_portal *p;
2186 struct qm_eqcr_entry *eq;
2187 unsigned long irqflags;
2188 u8 avail;
2189
2190 p = get_affine_portal();
2191 local_irq_save(irqflags);
2192
2193 if (p->use_eqcr_ci_stashing) {
2194 /*
2195 * The stashing case is easy, only update if we need to in
2196 * order to try and liberate ring entries.
2197 */
2198 eq = qm_eqcr_start_stash(&p->p);
2199 } else {
2200 /*
2201 * The non-stashing case is harder, need to prefetch ahead of
2202 * time.
2203 */
2204 avail = qm_eqcr_get_avail(&p->p);
2205 if (avail < 2)
2206 update_eqcr_ci(p, avail);
2207 eq = qm_eqcr_start_no_stash(&p->p);
2208 }
2209
2210 if (unlikely(!eq))
2211 goto out;
2212
d6753c7e 2213 qm_fqid_set(eq, fq->fqid);
18058822 2214 eq->tag = cpu_to_be32(fq_to_tag(fq));
c535e923
CM		 2215 eq->fd = *fd;
2216
2217 qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);
2218out:
2219 local_irq_restore(irqflags);
2220 put_affine_portal();
2221 return 0;
2222}
2223EXPORT_SYMBOL(qman_enqueue);
2224
2225static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags,
2226 struct qm_mcc_initcgr *opts)
2227{
2228 union qm_mc_command *mcc;
2229 union qm_mc_result *mcr;
2230 struct qman_portal *p = get_affine_portal();
2231 u8 verb = QM_MCC_VERB_MODIFYCGR;
2232 int ret = 0;
2233
2234 mcc = qm_mc_start(&p->p);
2235 if (opts)
2236 mcc->initcgr = *opts;
2237 mcc->initcgr.cgid = cgr->cgrid;
2238 if (flags & QMAN_CGR_FLAG_USE_INIT)
2239 verb = QM_MCC_VERB_INITCGR;
2240 qm_mc_commit(&p->p, verb);
2241 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2242 ret = -ETIMEDOUT;
2243 goto out;
2244 }
2245
2246 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2247 if (mcr->result != QM_MCR_RESULT_OK)
2248 ret = -EIO;
2249
2250out:
2251 put_affine_portal();
2252 return ret;
2253}
2254
2255#define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
496bfa11
CM		 2256
2257/* congestion state change notification target update control */
2258static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val)
2259{
2260 if (qman_ip_rev >= QMAN_REV30)
18058822
CM		 2261 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi |
2262 QM_CGR_TARG_UDP_CTRL_WRITE_BIT);
496bfa11 2263 else
18058822 2264 cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi));
496bfa11
CM		 2265}
2266
2267static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val)
2268{
2269 if (qman_ip_rev >= QMAN_REV30)
18058822 2270 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi);
496bfa11 2271 else
18058822 2272 cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi));
496bfa11 2273}
c535e923
CM		 2274
2275static u8 qman_cgr_cpus[CGR_NUM];
2276
2277void qman_init_cgr_all(void)
2278{
2279 struct qman_cgr cgr;
2280 int err_cnt = 0;
2281
2282 for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) {
2283 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL))
2284 err_cnt++;
2285 }
2286
2287 if (err_cnt)
2288 pr_err("Warning: %d error%s while initialising CGR h/w\n",
2289 err_cnt, (err_cnt > 1) ? "s" : "");
2290}
2291
2292int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2293 struct qm_mcc_initcgr *opts)
2294{
2295 struct qm_mcr_querycgr cgr_state;
c535e923
CM		 2296 int ret;
2297 struct qman_portal *p;
2298
2299 /*
2300 * We have to check that the provided CGRID is within the limits of the
2301 * data-structures, for obvious reasons. However we'll let h/w take
2302 * care of determining whether it's within the limits of what exists on
2303 * the SoC.
2304 */
2305 if (cgr->cgrid >= CGR_NUM)
2306 return -EINVAL;
2307
2308 preempt_disable();
2309 p = get_affine_portal();
2310 qman_cgr_cpus[cgr->cgrid] = smp_processor_id();
2311 preempt_enable();
2312
2313 cgr->chan = p->config->channel;
2314 spin_lock(&p->cgr_lock);
2315
2316 if (opts) {
e5caf693
CM		 2317 struct qm_mcc_initcgr local_opts = *opts;
2318
c535e923
CM		 2319 ret = qman_query_cgr(cgr, &cgr_state);
2320 if (ret)
2321 goto out;
e5caf693 2322
496bfa11 2323 qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p),
18058822
CM		 2324 be32_to_cpu(cgr_state.cgr.cscn_targ));
2325 local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG);
c535e923
CM		 2326
2327 /* send init if flags indicate so */
e5caf693 2328 if (flags & QMAN_CGR_FLAG_USE_INIT)
c535e923
CM		 2329 ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2330 &local_opts);
2331 else
2332 ret = qm_modify_cgr(cgr, 0, &local_opts);
2333 if (ret)
2334 goto out;
2335 }
2336
2337 list_add(&cgr->node, &p->cgr_cbs);
2338
2339 /* Determine if newly added object requires its callback to be called */
2340 ret = qman_query_cgr(cgr, &cgr_state);
2341 if (ret) {
2342 /* we can't go back, so proceed and return success */
2343 dev_err(p->config->dev, "CGR HW state partially modified\n");
2344 ret = 0;
2345 goto out;
2346 }
2347 if (cgr->cb && cgr_state.cgr.cscn_en &&
2348 qman_cgrs_get(&p->cgrs[1], cgr->cgrid))
2349 cgr->cb(p, cgr, 1);
2350out:
2351 spin_unlock(&p->cgr_lock);
2352 put_affine_portal();
2353 return ret;
2354}
2355EXPORT_SYMBOL(qman_create_cgr);
2356
2357int qman_delete_cgr(struct qman_cgr *cgr)
2358{
2359 unsigned long irqflags;
2360 struct qm_mcr_querycgr cgr_state;
2361 struct qm_mcc_initcgr local_opts;
2362 int ret = 0;
2363 struct qman_cgr *i;
2364 struct qman_portal *p = get_affine_portal();
2365
2366 if (cgr->chan != p->config->channel) {
2367 /* attempt to delete from other portal than creator */
2368 dev_err(p->config->dev, "CGR not owned by current portal");
2369 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n",
2370 cgr->chan, p->config->channel);
2371
2372 ret = -EINVAL;
2373 goto put_portal;
2374 }
2375 memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2376 spin_lock_irqsave(&p->cgr_lock, irqflags);
2377 list_del(&cgr->node);
2378 /*
2379 * If there are no other CGR objects for this CGRID in the list,
2380 * update CSCN_TARG accordingly
2381 */
2382 list_for_each_entry(i, &p->cgr_cbs, node)
2383 if (i->cgrid == cgr->cgrid && i->cb)
2384 goto release_lock;
2385 ret = qman_query_cgr(cgr, &cgr_state);
2386 if (ret) {
2387 /* add back to the list */
2388 list_add(&cgr->node, &p->cgr_cbs);
2389 goto release_lock;
2390 }
496bfa11 2391
18058822 2392 local_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG);
496bfa11 2393 qm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p),
18058822 2394 be32_to_cpu(cgr_state.cgr.cscn_targ));
496bfa11 2395
c535e923
CM		 2396 ret = qm_modify_cgr(cgr, 0, &local_opts);
2397 if (ret)
2398 /* add back to the list */
2399 list_add(&cgr->node, &p->cgr_cbs);
2400release_lock:
2401 spin_unlock_irqrestore(&p->cgr_lock, irqflags);
2402put_portal:
2403 put_affine_portal();
2404 return ret;
2405}
2406EXPORT_SYMBOL(qman_delete_cgr);
2407
2408struct cgr_comp {
2409 struct qman_cgr *cgr;
2410 struct completion completion;
2411};
2412
2413static int qman_delete_cgr_thread(void *p)
2414{
2415 struct cgr_comp *cgr_comp = (struct cgr_comp *)p;
2416 int ret;
2417
2418 ret = qman_delete_cgr(cgr_comp->cgr);
2419 complete(&cgr_comp->completion);
2420
2421 return ret;
2422}
2423
2424void qman_delete_cgr_safe(struct qman_cgr *cgr)
2425{
2426 struct task_struct *thread;
2427 struct cgr_comp cgr_comp;
2428
2429 preempt_disable();
2430 if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) {
2431 init_completion(&cgr_comp.completion);
2432 cgr_comp.cgr = cgr;
2433 thread = kthread_create(qman_delete_cgr_thread, &cgr_comp,
2434 "cgr_del");
2435
2436 if (IS_ERR(thread))
2437 goto out;
2438
2439 kthread_bind(thread, qman_cgr_cpus[cgr->cgrid]);
2440 wake_up_process(thread);
2441 wait_for_completion(&cgr_comp.completion);
2442 preempt_enable();
2443 return;
2444 }
2445out:
2446 qman_delete_cgr(cgr);
2447 preempt_enable();
2448}
2449EXPORT_SYMBOL(qman_delete_cgr_safe);
2450
2451/* Cleanup FQs */
2452
2453static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
2454{
2455 const union qm_mr_entry *msg;
2456 int found = 0;
2457
2458 qm_mr_pvb_update(p);
2459 msg = qm_mr_current(p);
2460 while (msg) {
2461 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v)
2462 found = 1;
2463 qm_mr_next(p);
2464 qm_mr_cci_consume_to_current(p);
2465 qm_mr_pvb_update(p);
2466 msg = qm_mr_current(p);
2467 }
2468 return found;
2469}
2470
2471static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
2472 bool wait)
2473{
2474 const struct qm_dqrr_entry *dqrr;
2475 int found = 0;
2476
2477 do {
2478 qm_dqrr_pvb_update(p);
2479 dqrr = qm_dqrr_current(p);
2480 if (!dqrr)
2481 cpu_relax();
2482 } while (wait && !dqrr);
2483
2484 while (dqrr) {
d6753c7e 2485 if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s))
c535e923
CM		 2486 found = 1;
2487 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
2488 qm_dqrr_pvb_update(p);
2489 qm_dqrr_next(p);
2490 dqrr = qm_dqrr_current(p);
2491 }
2492 return found;
2493}
2494
2495#define qm_mr_drain(p, V) \
2496 _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
2497
2498#define qm_dqrr_drain(p, f, S) \
2499 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
2500
2501#define qm_dqrr_drain_wait(p, f, S) \
2502 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
2503
2504#define qm_dqrr_drain_nomatch(p) \
2505 _qm_dqrr_consume_and_match(p, 0, 0, false)
2506
2507static int qman_shutdown_fq(u32 fqid)
2508{
2509 struct qman_portal *p;
2510 struct device *dev;
2511 union qm_mc_command *mcc;
2512 union qm_mc_result *mcr;
2513 int orl_empty, drain = 0, ret = 0;
2514 u32 channel, wq, res;
2515 u8 state;
2516
2517 p = get_affine_portal();
2518 dev = p->config->dev;
2519 /* Determine the state of the FQID */
2520 mcc = qm_mc_start(&p->p);
d6753c7e 2521 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2522 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2523 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2524 dev_err(dev, "QUERYFQ_NP timeout\n");
2525 ret = -ETIMEDOUT;
2526 goto out;
2527 }
2528
2529 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2530 state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2531 if (state == QM_MCR_NP_STATE_OOS)
2532 goto out; /* Already OOS, no need to do anymore checks */
2533
2534 /* Query which channel the FQ is using */
2535 mcc = qm_mc_start(&p->p);
d6753c7e 2536 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2537 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2538 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2539 dev_err(dev, "QUERYFQ timeout\n");
2540 ret = -ETIMEDOUT;
2541 goto out;
2542 }
2543
2544 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2545 /* Need to store these since the MCR gets reused */
2546 channel = qm_fqd_get_chan(&mcr->queryfq.fqd);
2547 wq = qm_fqd_get_wq(&mcr->queryfq.fqd);
2548
2549 switch (state) {
2550 case QM_MCR_NP_STATE_TEN_SCHED:
2551 case QM_MCR_NP_STATE_TRU_SCHED:
2552 case QM_MCR_NP_STATE_ACTIVE:
2553 case QM_MCR_NP_STATE_PARKED:
2554 orl_empty = 0;
2555 mcc = qm_mc_start(&p->p);
d6753c7e 2556 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2557 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
2558 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2559 dev_err(dev, "QUERYFQ_NP timeout\n");
2560 ret = -ETIMEDOUT;
2561 goto out;
2562 }
2563 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2564 QM_MCR_VERB_ALTER_RETIRE);
2565 res = mcr->result; /* Make a copy as we reuse MCR below */
2566
2567 if (res == QM_MCR_RESULT_PENDING) {
2568 /*
2569 * Need to wait for the FQRN in the message ring, which
2570 * will only occur once the FQ has been drained. In
2571 * order for the FQ to drain the portal needs to be set
2572 * to dequeue from the channel the FQ is scheduled on
2573 */
2574 int found_fqrn = 0;
2575 u16 dequeue_wq = 0;
2576
2577 /* Flag that we need to drain FQ */
2578 drain = 1;
2579
2580 if (channel >= qm_channel_pool1 &&
2581 channel < qm_channel_pool1 + 15) {
2582 /* Pool channel, enable the bit in the portal */
2583 dequeue_wq = (channel -
2584 qm_channel_pool1 + 1)<<4 | wq;
2585 } else if (channel < qm_channel_pool1) {
2586 /* Dedicated channel */
2587 dequeue_wq = wq;
2588 } else {
2589 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x",
2590 fqid, channel);
2591 ret = -EBUSY;
2592 goto out;
2593 }
2594 /* Set the sdqcr to drain this channel */
2595 if (channel < qm_channel_pool1)
2596 qm_dqrr_sdqcr_set(&p->p,
2597 QM_SDQCR_TYPE_ACTIVE |
2598 QM_SDQCR_CHANNELS_DEDICATED);
2599 else
2600 qm_dqrr_sdqcr_set(&p->p,
2601 QM_SDQCR_TYPE_ACTIVE |
2602 QM_SDQCR_CHANNELS_POOL_CONV
2603 (channel));
2604 do {
2605 /* Keep draining DQRR while checking the MR*/
2606 qm_dqrr_drain_nomatch(&p->p);
2607 /* Process message ring too */
2608 found_fqrn = qm_mr_drain(&p->p, FQRN);
2609 cpu_relax();
2610 } while (!found_fqrn);
2611
2612 }
2613 if (res != QM_MCR_RESULT_OK &&
2614 res != QM_MCR_RESULT_PENDING) {
2615 dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n",
2616 fqid, res);
2617 ret = -EIO;
2618 goto out;
2619 }
2620 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2621 /*
2622 * ORL had no entries, no need to wait until the
2623 * ERNs come in
2624 */
2625 orl_empty = 1;
2626 }
2627 /*
2628 * Retirement succeeded, check to see if FQ needs
2629 * to be drained
2630 */
2631 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2632 /* FQ is Not Empty, drain using volatile DQ commands */
2633 do {
2634 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2635
2636 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2637 /*
2638 * Wait for a dequeue and process the dequeues,
2639 * making sure to empty the ring completely
2640 */
2641 } while (qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
2642 }
2643 qm_dqrr_sdqcr_set(&p->p, 0);
2644
2645 while (!orl_empty) {
2646 /* Wait for the ORL to have been completely drained */
2647 orl_empty = qm_mr_drain(&p->p, FQRL);
2648 cpu_relax();
2649 }
2650 mcc = qm_mc_start(&p->p);
d6753c7e 2651 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2652 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2653 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2654 ret = -ETIMEDOUT;
2655 goto out;
2656 }
2657
2658 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2659 QM_MCR_VERB_ALTER_OOS);
2660 if (mcr->result != QM_MCR_RESULT_OK) {
2661 dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n",
2662 fqid, mcr->result);
2663 ret = -EIO;
2664 goto out;
2665 }
2666 break;
2667
2668 case QM_MCR_NP_STATE_RETIRED:
2669 /* Send OOS Command */
2670 mcc = qm_mc_start(&p->p);
d6753c7e 2671 qm_fqid_set(&mcc->fq, fqid);
c535e923
CM		 2672 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2673 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2674 ret = -ETIMEDOUT;
2675 goto out;
2676 }
2677
2678 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2679 QM_MCR_VERB_ALTER_OOS);
2680 if (mcr->result) {
2681 dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n",
2682 fqid, mcr->result);
2683 ret = -EIO;
2684 goto out;
2685 }
2686 break;
2687
2688 case QM_MCR_NP_STATE_OOS:
2689 /* Done */
2690 break;
2691
2692 default:
2693 ret = -EIO;
2694 }
2695
2696out:
2697 put_affine_portal();
2698 return ret;
2699}
2700
2701const struct qm_portal_config *qman_get_qm_portal_config(
2702 struct qman_portal *portal)
2703{
2704 return portal->config;
2705}
021ba010 2706EXPORT_SYMBOL(qman_get_qm_portal_config);
c535e923
CM		 2707
2708struct gen_pool *qm_fqalloc; /* FQID allocator */
2709struct gen_pool *qm_qpalloc; /* pool-channel allocator */
2710struct gen_pool *qm_cgralloc; /* CGR ID allocator */
2711
2712static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)
2713{
2714 unsigned long addr;
2715
2716 addr = gen_pool_alloc(p, cnt);
2717 if (!addr)
2718 return -ENOMEM;
2719
2720 *result = addr & ~DPAA_GENALLOC_OFF;
2721
2722 return 0;
2723}
2724
2725int qman_alloc_fqid_range(u32 *result, u32 count)
2726{
2727 return qman_alloc_range(qm_fqalloc, result, count);
2728}
2729EXPORT_SYMBOL(qman_alloc_fqid_range);
2730
2731int qman_alloc_pool_range(u32 *result, u32 count)
2732{
2733 return qman_alloc_range(qm_qpalloc, result, count);
2734}
2735EXPORT_SYMBOL(qman_alloc_pool_range);
2736
2737int qman_alloc_cgrid_range(u32 *result, u32 count)
2738{
2739 return qman_alloc_range(qm_cgralloc, result, count);
2740}
2741EXPORT_SYMBOL(qman_alloc_cgrid_range);
2742
2743int qman_release_fqid(u32 fqid)
2744{
2745 int ret = qman_shutdown_fq(fqid);
2746
2747 if (ret) {
2748 pr_debug("FQID %d leaked\n", fqid);
2749 return ret;
2750 }
2751
2752 gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1);
2753 return 0;
2754}
2755EXPORT_SYMBOL(qman_release_fqid);
2756
2757static int qpool_cleanup(u32 qp)
2758{
2759 /*
2760 * We query all FQDs starting from
2761 * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs
2762 * whose destination channel is the pool-channel being released.
2763 * When a non-OOS FQD is found we attempt to clean it up
2764 */
2765 struct qman_fq fq = {
2766 .fqid = QM_FQID_RANGE_START
2767 };
2768 int err;
2769
2770 do {
2771 struct qm_mcr_queryfq_np np;
2772
2773 err = qman_query_fq_np(&fq, &np);
d95cb0d3 2774 if (err == -ERANGE)
c535e923
CM		 2775 /* FQID range exceeded, found no problems */
2776 return 0;
d95cb0d3
CM		 2777 else if (WARN_ON(err))
2778 return err;
2779
c535e923
CM		 2780 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2781 struct qm_fqd fqd;
2782
2783 err = qman_query_fq(&fq, &fqd);
2784 if (WARN_ON(err))
d95cb0d3 2785 return err;
c535e923
CM		 2786 if (qm_fqd_get_chan(&fqd) == qp) {
2787 /* The channel is the FQ's target, clean it */
2788 err = qman_shutdown_fq(fq.fqid);
2789 if (err)
2790 /*
2791 * Couldn't shut down the FQ
2792 * so the pool must be leaked
2793 */
2794 return err;
2795 }
2796 }
2797 /* Move to the next FQID */
2798 fq.fqid++;
2799 } while (1);
2800}
2801
2802int qman_release_pool(u32 qp)
2803{
2804 int ret;
2805
2806 ret = qpool_cleanup(qp);
2807 if (ret) {
2808 pr_debug("CHID %d leaked\n", qp);
2809 return ret;
2810 }
2811
2812 gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1);
2813 return 0;
2814}
2815EXPORT_SYMBOL(qman_release_pool);
2816
2817static int cgr_cleanup(u32 cgrid)
2818{
2819 /*
2820 * query all FQDs starting from FQID 1 until we get an "invalid FQID"
2821 * error, looking for non-OOS FQDs whose CGR is the CGR being released
2822 */
2823 struct qman_fq fq = {
d95cb0d3 2824 .fqid = QM_FQID_RANGE_START
c535e923
CM		 2825 };
2826 int err;
2827
2828 do {
2829 struct qm_mcr_queryfq_np np;
2830
2831 err = qman_query_fq_np(&fq, &np);
d95cb0d3 2832 if (err == -ERANGE)
c535e923
CM		 2833 /* FQID range exceeded, found no problems */
2834 return 0;
d95cb0d3
CM		 2835 else if (WARN_ON(err))
2836 return err;
2837
c535e923
CM		 2838 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2839 struct qm_fqd fqd;
2840
2841 err = qman_query_fq(&fq, &fqd);
2842 if (WARN_ON(err))
d95cb0d3 2843 return err;
18058822 2844 if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE &&
c535e923
CM		 2845 fqd.cgid == cgrid) {
2846 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
2847 cgrid, fq.fqid);
2848 return -EIO;
2849 }
2850 }
2851 /* Move to the next FQID */
2852 fq.fqid++;
2853 } while (1);
2854}
2855
2856int qman_release_cgrid(u32 cgrid)
2857{
2858 int ret;
2859
2860 ret = cgr_cleanup(cgrid);
2861 if (ret) {
2862 pr_debug("CGRID %d leaked\n", cgrid);
2863 return ret;
2864 }
2865
2866 gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1);
2867 return 0;
2868}
2869EXPORT_SYMBOL(qman_release_cgrid);
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