[mirror_ubuntu-bionic-kernel.git] / drivers / soc / fsl / qe / gpio.c

/*
 * QUICC Engine GPIOs
 *
 * Copyright (c) MontaVista Software, Inc. 2008.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio/driver.h>
/* FIXME: needed for gpio_to_chip() get rid of this */
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <soc/fsl/qe/qe.h>

struct qe_gpio_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	unsigned long pin_flags[QE_PIO_PINS];
#define QE_PIN_REQUESTED 0

	/* shadowed data register to clear/set bits safely */
	u32 cpdata;

	/* saved_regs used to restore dedicated functions */
	struct qe_pio_regs saved_regs;
};

static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct qe_gpio_chip *qe_gc =
		container_of(mm_gc, struct qe_gpio_chip, mm_gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	qe_gc->cpdata = in_be32(&regs->cpdata);
	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
}

static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	return !!(in_be32(&regs->cpdata) & pin_mask);
}

static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (val)
		qe_gc->cpdata |= pin_mask;
	else
		qe_gc->cpdata &= ~pin_mask;

	out_be32(&regs->cpdata, qe_gc->cpdata);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}

static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
	unsigned long flags;

	qe_gpio_set(gc, gpio, val);

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

struct qe_pin {
	/*
	 * The qe_gpio_chip name is unfortunate, we should change that to
	 * something like qe_pio_controller. Someday.
	 */
	struct qe_gpio_chip *controller;
	int num;
};

/**
 * qe_pin_request - Request a QE pin
 * @np:		device node to get a pin from
 * @index:	index of a pin in the device tree
 * Context:	non-atomic
 *
 * This function return qe_pin so that you could use it with the rest of
 * the QE Pin Multiplexing API.
 */
struct qe_pin *qe_pin_request(struct device_node *np, int index)
{
	struct qe_pin *qe_pin;
	struct gpio_chip *gc;
	struct of_mm_gpio_chip *mm_gc;
	struct qe_gpio_chip *qe_gc;
	int err;
	unsigned long flags;

	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	if (!qe_pin) {
		pr_debug("%s: can't allocate memory\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	err = of_get_gpio(np, index);
	if (err < 0)
		goto err0;
	gc = gpio_to_chip(err);
	if (WARN_ON(!gc))
		goto err0;

	if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
		pr_debug("%s: tried to get a non-qe pin\n", __func__);
		err = -EINVAL;
		goto err0;
	}

	mm_gc = to_of_mm_gpio_chip(gc);
	qe_gc = gpiochip_get_data(gc);

	spin_lock_irqsave(&qe_gc->lock, flags);

	err -= gc->base;
	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
		qe_pin->controller = qe_gc;
		qe_pin->num = err;
		err = 0;
	} else {
		err = -EBUSY;
	}

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	if (!err)
		return qe_pin;
err0:
	kfree(qe_pin);
	pr_debug("%s failed with status %d\n", __func__, err);
	return ERR_PTR(err);
}
EXPORT_SYMBOL(qe_pin_request);

/**
 * qe_pin_free - Free a pin
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function frees the qe_pin structure and makes a pin available
 * for further qe_pin_request() calls.
 */
void qe_pin_free(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	unsigned long flags;
	const int pin = qe_pin->num;

	spin_lock_irqsave(&qe_gc->lock, flags);
	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	spin_unlock_irqrestore(&qe_gc->lock, flags);

	kfree(qe_pin);
}
EXPORT_SYMBOL(qe_pin_free);

/**
 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function resets a pin to a dedicated peripheral function that
 * has been set up by the firmware.
 */
void qe_pin_set_dedicated(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	int pin = qe_pin->num;
	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (second_reg) {
		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	} else {
		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	}

	if (sregs->cpdata & mask1)
		qe_gc->cpdata |= mask1;
	else
		qe_gc->cpdata &= ~mask1;

	out_be32(&regs->cpdata, qe_gc->cpdata);
	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_dedicated);

/**
 * qe_pin_set_gpio - Set a pin to the GPIO mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function sets a pin to the GPIO mode.
 */
void qe_pin_set_gpio(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	/* Let's make it input by default, GPIO API is able to change that. */
	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_gpio);

static int __init qe_add_gpiochips(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
		int ret;
		struct qe_gpio_chip *qe_gc;
		struct of_mm_gpio_chip *mm_gc;
		struct gpio_chip *gc;

		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
		if (!qe_gc) {
			ret = -ENOMEM;
			goto err;
		}

		spin_lock_init(&qe_gc->lock);

		mm_gc = &qe_gc->mm_gc;
		gc = &mm_gc->gc;

		mm_gc->save_regs = qe_gpio_save_regs;
		gc->ngpio = QE_PIO_PINS;
		gc->direction_input = qe_gpio_dir_in;
		gc->direction_output = qe_gpio_dir_out;
		gc->get = qe_gpio_get;
		gc->set = qe_gpio_set;

		ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
		if (ret)
			goto err;
		continue;
err:
		pr_err("%pOF: registration failed with status %d\n",
		       np, ret);
		kfree(qe_gc);
		/* try others anyway */
	}
	return 0;
}
arch_initcall(qe_add_gpiochips);
Commit	Line	Data
32def337 AV	1	/*
	2	* QUICC Engine GPIOs
	3	*
	4	* Copyright (c) MontaVista Software, Inc. 2008.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
d14b3dd6	15	#include <linux/init.h>
32def337	16	#include <linux/spinlock.h>
1b9e8904	17	#include <linux/err.h>
32def337 AV	18	#include <linux/io.h>
	19	#include <linux/of.h>
	20	#include <linux/of_gpio.h>
1e714e54 LW	21	#include <linux/gpio/driver.h>
1e714e54 LW	22	/* FIXME: needed for gpio_to_chip() get rid of this */
32def337	23	#include <linux/gpio.h>
5a0e3ad6	24	#include <linux/slab.h>
66b15db6	25	#include <linux/export.h>
7aa1aa6e	26	#include <soc/fsl/qe/qe.h>
32def337 AV	27
	28	struct qe_gpio_chip {
	29	struct of_mm_gpio_chip mm_gc;
	30	spinlock_t lock;
	31
1b9e8904 AV	32	unsigned long pin_flags[QE_PIO_PINS];
	33	#define QE_PIN_REQUESTED 0
	34
32def337 AV	35	/* shadowed data register to clear/set bits safely */
32def337 AV	36	u32 cpdata;
1b9e8904 AV	37
	38	/* saved_regs used to restore dedicated functions */
	39	struct qe_pio_regs saved_regs;
32def337 AV	40	};
32def337 AV	41
32def337 AV	42	static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
32def337 AV	43	{
5dc6f3fe CL	44	struct qe_gpio_chip *qe_gc =
5dc6f3fe CL	45	container_of(mm_gc, struct qe_gpio_chip, mm_gc);
32def337 AV	46	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	47
	48	qe_gc->cpdata = in_be32(&regs->cpdata);
1b9e8904 AV	49	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	50	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	51	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	52	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	53	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	54	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
32def337 AV	55	}
	56
	57	static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	58	{
	59	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	60	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	61	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	62
e847396b	63	return !!(in_be32(&regs->cpdata) & pin_mask);
32def337 AV	64	}
	65
	66	static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	67	{
	68	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
1e714e54	69	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
32def337 AV	70	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	71	unsigned long flags;
	72	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	73
	74	spin_lock_irqsave(&qe_gc->lock, flags);
	75
	76	if (val)
	77	qe_gc->cpdata \|= pin_mask;
	78	else
	79	qe_gc->cpdata &= ~pin_mask;
	80
	81	out_be32(&regs->cpdata, qe_gc->cpdata);
	82
	83	spin_unlock_irqrestore(&qe_gc->lock, flags);
	84	}
	85
	86	static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	87	{
	88	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
1e714e54	89	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
32def337 AV	90	unsigned long flags;
	91
	92	spin_lock_irqsave(&qe_gc->lock, flags);
	93
	94	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
	95
	96	spin_unlock_irqrestore(&qe_gc->lock, flags);
	97
	98	return 0;
	99	}
	100
	101	static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	102	{
	103	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
1e714e54	104	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
32def337 AV	105	unsigned long flags;
32def337 AV	106
1dcd8ffc MB	107	qe_gpio_set(gc, gpio, val);
1dcd8ffc MB	108
32def337 AV	109	spin_lock_irqsave(&qe_gc->lock, flags);
	110
	111	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
	112
	113	spin_unlock_irqrestore(&qe_gc->lock, flags);
	114
32def337 AV	115	return 0;
	116	}
	117
1b9e8904 AV	118	struct qe_pin {
	119	/*
	120	* The qe_gpio_chip name is unfortunate, we should change that to
	121	* something like qe_pio_controller. Someday.
	122	*/
	123	struct qe_gpio_chip *controller;
	124	int num;
	125	};
	126
	127	/**
	128	* qe_pin_request - Request a QE pin
	129	* @np: device node to get a pin from
	130	* @index: index of a pin in the device tree
	131	* Context: non-atomic
	132	*
	133	* This function return qe_pin so that you could use it with the rest of
	134	* the QE Pin Multiplexing API.
	135	*/
	136	struct qe_pin qe_pin_request(struct device_node np, int index)
	137	{
	138	struct qe_pin *qe_pin;
a19e3da5	139	struct gpio_chip *gc;
1b9e8904 AV	140	struct of_mm_gpio_chip *mm_gc;
	141	struct qe_gpio_chip *qe_gc;
	142	int err;
1b9e8904 AV	143	unsigned long flags;
	144
	145	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	146	if (!qe_pin) {
	147	pr_debug("%s: can't allocate memory\n", __func__);
	148	return ERR_PTR(-ENOMEM);
	149	}
	150
1a2d397a GL	151	err = of_get_gpio(np, index);
	152	if (err < 0)
	153	goto err0;
	154	gc = gpio_to_chip(err);
	155	if (WARN_ON(!gc))
1b9e8904	156	goto err0;
1b9e8904	157
1a2d397a	158	if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
1b9e8904 AV	159	pr_debug("%s: tried to get a non-qe pin\n", __func__);
1b9e8904 AV	160	err = -EINVAL;
1a2d397a	161	goto err0;
1b9e8904 AV	162	}
1b9e8904 AV	163
a19e3da5	164	mm_gc = to_of_mm_gpio_chip(gc);
1e714e54	165	qe_gc = gpiochip_get_data(gc);
1b9e8904 AV	166
	167	spin_lock_irqsave(&qe_gc->lock, flags);
	168
1a2d397a	169	err -= gc->base;
1b9e8904 AV	170	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
	171	qe_pin->controller = qe_gc;
	172	qe_pin->num = err;
	173	err = 0;
	174	} else {
	175	err = -EBUSY;
	176	}
	177
	178	spin_unlock_irqrestore(&qe_gc->lock, flags);
	179
	180	if (!err)
	181	return qe_pin;
1b9e8904 AV	182	err0:
	183	kfree(qe_pin);
	184	pr_debug("%s failed with status %d\n", __func__, err);
	185	return ERR_PTR(err);
	186	}
	187	EXPORT_SYMBOL(qe_pin_request);
	188
	189	/**
	190	* qe_pin_free - Free a pin
	191	* @qe_pin: pointer to the qe_pin structure
	192	* Context: any
	193	*
	194	* This function frees the qe_pin structure and makes a pin available
	195	* for further qe_pin_request() calls.
	196	*/
	197	void qe_pin_free(struct qe_pin *qe_pin)
	198	{
	199	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	200	unsigned long flags;
	201	const int pin = qe_pin->num;
	202
	203	spin_lock_irqsave(&qe_gc->lock, flags);
	204	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	205	spin_unlock_irqrestore(&qe_gc->lock, flags);
	206
	207	kfree(qe_pin);
	208	}
	209	EXPORT_SYMBOL(qe_pin_free);
	210
	211	/**
	212	* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
	213	* @qe_pin: pointer to the qe_pin structure
	214	* Context: any
	215	*
	216	* This function resets a pin to a dedicated peripheral function that
	217	* has been set up by the firmware.
	218	*/
	219	void qe_pin_set_dedicated(struct qe_pin *qe_pin)
	220	{
	221	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	222	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	223	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	224	int pin = qe_pin->num;
	225	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	226	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	227	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	228	unsigned long flags;
	229
	230	spin_lock_irqsave(&qe_gc->lock, flags);
	231
	232	if (second_reg) {
	233	clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
	234	clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	235	} else {
	236	clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
	237	clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	238	}
	239
	240	if (sregs->cpdata & mask1)
	241	qe_gc->cpdata \|= mask1;
	242	else
	243	qe_gc->cpdata &= ~mask1;
	244
	245	out_be32(&regs->cpdata, qe_gc->cpdata);
246	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
247
248	spin_unlock_irqrestore(&qe_gc->lock, flags);
249	}
250	EXPORT_SYMBOL(qe_pin_set_dedicated);
251
252	/**
253	* qe_pin_set_gpio - Set a pin to the GPIO mode
254	* @qe_pin: pointer to the qe_pin structure
255	* Context: any
256	*
257	* This function sets a pin to the GPIO mode.
258	*/
259	void qe_pin_set_gpio(struct qe_pin *qe_pin)
260	{
261	struct qe_gpio_chip *qe_gc = qe_pin->controller;
262	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
263	unsigned long flags;
264
265	spin_lock_irqsave(&qe_gc->lock, flags);
266
267	/* Let's make it input by default, GPIO API is able to change that. */
268	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
269
270	spin_unlock_irqrestore(&qe_gc->lock, flags);
271	}
272	EXPORT_SYMBOL(qe_pin_set_gpio);
273
d14b3dd6	274	static int __init qe_add_gpiochips(void)
32def337 AV	275	{
	276	struct device_node *np;
	277
	278	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
	279	int ret;
	280	struct qe_gpio_chip *qe_gc;
	281	struct of_mm_gpio_chip *mm_gc;
32def337 AV	282	struct gpio_chip *gc;
	283
	284	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
	285	if (!qe_gc) {
	286	ret = -ENOMEM;
	287	goto err;
	288	}
	289
	290	spin_lock_init(&qe_gc->lock);
	291
	292	mm_gc = &qe_gc->mm_gc;
a19e3da5	293	gc = &mm_gc->gc;
32def337 AV	294
32def337 AV	295	mm_gc->save_regs = qe_gpio_save_regs;
32def337 AV	296	gc->ngpio = QE_PIO_PINS;
	297	gc->direction_input = qe_gpio_dir_in;
	298	gc->direction_output = qe_gpio_dir_out;
	299	gc->get = qe_gpio_get;
	300	gc->set = qe_gpio_set;
	301
1e714e54	302	ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
32def337 AV	303	if (ret)
	304	goto err;
	305	continue;
	306	err:
37c342cb RH	307	pr_err("%pOF: registration failed with status %d\n",
37c342cb RH	308	np, ret);
32def337 AV	309	kfree(qe_gc);
	310	/* try others anyway */
	311	}
d14b3dd6	312	return 0;
32def337	313	}
d14b3dd6	314	arch_initcall(qe_add_gpiochips);