[mirror_ubuntu-bionic-kernel.git] / drivers / soc / fsl / qe / gpio.c

/*
 * QUICC Engine GPIOs
 *
 * Copyright (c) MontaVista Software, Inc. 2008.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio/driver.h>
/* FIXME: needed for gpio_to_chip() get rid of this */
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <soc/fsl/qe/qe.h>

struct qe_gpio_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	unsigned long pin_flags[QE_PIO_PINS];
#define QE_PIN_REQUESTED 0

	/* shadowed data register to clear/set bits safely */
	u32 cpdata;

	/* saved_regs used to restore dedicated functions */
	struct qe_pio_regs saved_regs;
};

static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct qe_gpio_chip *qe_gc = gpiochip_get_data(&mm_gc->gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	qe_gc->cpdata = in_be32(&regs->cpdata);
	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
}

static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	return !!(in_be32(&regs->cpdata) & pin_mask);
}

static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (val)
		qe_gc->cpdata |= pin_mask;
	else
		qe_gc->cpdata &= ~pin_mask;

	out_be32(&regs->cpdata, qe_gc->cpdata);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}

static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
	unsigned long flags;

	qe_gpio_set(gc, gpio, val);

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

struct qe_pin {
	/*
	 * The qe_gpio_chip name is unfortunate, we should change that to
	 * something like qe_pio_controller. Someday.
	 */
	struct qe_gpio_chip *controller;
	int num;
};

/**
 * qe_pin_request - Request a QE pin
 * @np:		device node to get a pin from
 * @index:	index of a pin in the device tree
 * Context:	non-atomic
 *
 * This function return qe_pin so that you could use it with the rest of
 * the QE Pin Multiplexing API.
 */
struct qe_pin *qe_pin_request(struct device_node *np, int index)
{
	struct qe_pin *qe_pin;
	struct gpio_chip *gc;
	struct of_mm_gpio_chip *mm_gc;
	struct qe_gpio_chip *qe_gc;
	int err;
	unsigned long flags;

	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	if (!qe_pin) {
		pr_debug("%s: can't allocate memory\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	err = of_get_gpio(np, index);
	if (err < 0)
		goto err0;
	gc = gpio_to_chip(err);
	if (WARN_ON(!gc))
		goto err0;

	if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
		pr_debug("%s: tried to get a non-qe pin\n", __func__);
		err = -EINVAL;
		goto err0;
	}

	mm_gc = to_of_mm_gpio_chip(gc);
	qe_gc = gpiochip_get_data(gc);

	spin_lock_irqsave(&qe_gc->lock, flags);

	err -= gc->base;
	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
		qe_pin->controller = qe_gc;
		qe_pin->num = err;
		err = 0;
	} else {
		err = -EBUSY;
	}

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	if (!err)
		return qe_pin;
err0:
	kfree(qe_pin);
	pr_debug("%s failed with status %d\n", __func__, err);
	return ERR_PTR(err);
}
EXPORT_SYMBOL(qe_pin_request);

/**
 * qe_pin_free - Free a pin
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function frees the qe_pin structure and makes a pin available
 * for further qe_pin_request() calls.
 */
void qe_pin_free(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	unsigned long flags;
	const int pin = qe_pin->num;

	spin_lock_irqsave(&qe_gc->lock, flags);
	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	spin_unlock_irqrestore(&qe_gc->lock, flags);

	kfree(qe_pin);
}
EXPORT_SYMBOL(qe_pin_free);

/**
 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function resets a pin to a dedicated peripheral function that
 * has been set up by the firmware.
 */
void qe_pin_set_dedicated(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	int pin = qe_pin->num;
	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (second_reg) {
		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	} else {
		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	}

	if (sregs->cpdata & mask1)
		qe_gc->cpdata |= mask1;
	else
		qe_gc->cpdata &= ~mask1;

	out_be32(&regs->cpdata, qe_gc->cpdata);
	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_dedicated);

/**
 * qe_pin_set_gpio - Set a pin to the GPIO mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function sets a pin to the GPIO mode.
 */
void qe_pin_set_gpio(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	/* Let's make it input by default, GPIO API is able to change that. */
	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_gpio);

static int __init qe_add_gpiochips(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
		int ret;
		struct qe_gpio_chip *qe_gc;
		struct of_mm_gpio_chip *mm_gc;
		struct gpio_chip *gc;

		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
		if (!qe_gc) {
			ret = -ENOMEM;
			goto err;
		}

		spin_lock_init(&qe_gc->lock);

		mm_gc = &qe_gc->mm_gc;
		gc = &mm_gc->gc;

		mm_gc->save_regs = qe_gpio_save_regs;
		gc->ngpio = QE_PIO_PINS;
		gc->direction_input = qe_gpio_dir_in;
		gc->direction_output = qe_gpio_dir_out;
		gc->get = qe_gpio_get;
		gc->set = qe_gpio_set;

		ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
		if (ret)
			goto err;
		continue;
err:
		pr_err("%s: registration failed with status %d\n",
		       np->full_name, ret);
		kfree(qe_gc);
		/* try others anyway */
	}
	return 0;
}
arch_initcall(qe_add_gpiochips);
Commit	Line	Data
32def337 AV	1	/*
	2	* QUICC Engine GPIOs
	3	*
	4	* Copyright (c) MontaVista Software, Inc. 2008.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
d14b3dd6	15	#include <linux/init.h>
32def337	16	#include <linux/spinlock.h>
1b9e8904	17	#include <linux/err.h>
32def337 AV	18	#include <linux/io.h>
	19	#include <linux/of.h>
	20	#include <linux/of_gpio.h>
1e714e54 LW	21	#include <linux/gpio/driver.h>
1e714e54 LW	22	/* FIXME: needed for gpio_to_chip() get rid of this */
32def337	23	#include <linux/gpio.h>
5a0e3ad6	24	#include <linux/slab.h>
66b15db6	25	#include <linux/export.h>
7aa1aa6e	26	#include <soc/fsl/qe/qe.h>
32def337 AV	27
	28	struct qe_gpio_chip {
	29	struct of_mm_gpio_chip mm_gc;
	30	spinlock_t lock;
	31
1b9e8904 AV	32	unsigned long pin_flags[QE_PIO_PINS];
	33	#define QE_PIN_REQUESTED 0
	34
32def337 AV	35	/* shadowed data register to clear/set bits safely */
32def337 AV	36	u32 cpdata;
1b9e8904 AV	37
	38	/* saved_regs used to restore dedicated functions */
	39	struct qe_pio_regs saved_regs;
32def337 AV	40	};
32def337 AV	41
32def337 AV	42	static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
32def337 AV	43	{
1e714e54	44	struct qe_gpio_chip *qe_gc = gpiochip_get_data(&mm_gc->gc);
32def337 AV	45	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	46
	47	qe_gc->cpdata = in_be32(&regs->cpdata);
1b9e8904 AV	48	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	49	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	50	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	51	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	52	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	53	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
32def337 AV	54	}
	55
	56	static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	57	{
	58	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	59	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	60	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	61
e847396b	62	return !!(in_be32(&regs->cpdata) & pin_mask);
32def337 AV	63	}
	64
	65	static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	66	{
	67	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
1e714e54	68	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
32def337 AV	69	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	70	unsigned long flags;
	71	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	72
	73	spin_lock_irqsave(&qe_gc->lock, flags);
	74
	75	if (val)
	76	qe_gc->cpdata \|= pin_mask;
	77	else
	78	qe_gc->cpdata &= ~pin_mask;
	79
	80	out_be32(&regs->cpdata, qe_gc->cpdata);
	81
	82	spin_unlock_irqrestore(&qe_gc->lock, flags);
	83	}
	84
	85	static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	86	{
	87	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
1e714e54	88	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
32def337 AV	89	unsigned long flags;
	90
	91	spin_lock_irqsave(&qe_gc->lock, flags);
	92
	93	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
	94
	95	spin_unlock_irqrestore(&qe_gc->lock, flags);
	96
	97	return 0;
	98	}
	99
	100	static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	101	{
	102	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
1e714e54	103	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
32def337 AV	104	unsigned long flags;
32def337 AV	105
1dcd8ffc MB	106	qe_gpio_set(gc, gpio, val);
1dcd8ffc MB	107
32def337 AV	108	spin_lock_irqsave(&qe_gc->lock, flags);
	109
	110	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
	111
	112	spin_unlock_irqrestore(&qe_gc->lock, flags);
	113
32def337 AV	114	return 0;
	115	}
	116
1b9e8904 AV	117	struct qe_pin {
	118	/*
	119	* The qe_gpio_chip name is unfortunate, we should change that to
	120	* something like qe_pio_controller. Someday.
	121	*/
	122	struct qe_gpio_chip *controller;
	123	int num;
	124	};
	125
	126	/**
	127	* qe_pin_request - Request a QE pin
	128	* @np: device node to get a pin from
	129	* @index: index of a pin in the device tree
	130	* Context: non-atomic
	131	*
	132	* This function return qe_pin so that you could use it with the rest of
	133	* the QE Pin Multiplexing API.
	134	*/
	135	struct qe_pin qe_pin_request(struct device_node np, int index)
	136	{
	137	struct qe_pin *qe_pin;
a19e3da5	138	struct gpio_chip *gc;
1b9e8904 AV	139	struct of_mm_gpio_chip *mm_gc;
	140	struct qe_gpio_chip *qe_gc;
	141	int err;
1b9e8904 AV	142	unsigned long flags;
	143
	144	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	145	if (!qe_pin) {
	146	pr_debug("%s: can't allocate memory\n", __func__);
	147	return ERR_PTR(-ENOMEM);
	148	}
	149
1a2d397a GL	150	err = of_get_gpio(np, index);
	151	if (err < 0)
	152	goto err0;
	153	gc = gpio_to_chip(err);
	154	if (WARN_ON(!gc))
1b9e8904	155	goto err0;
1b9e8904	156
1a2d397a	157	if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
1b9e8904 AV	158	pr_debug("%s: tried to get a non-qe pin\n", __func__);
1b9e8904 AV	159	err = -EINVAL;
1a2d397a	160	goto err0;
1b9e8904 AV	161	}
1b9e8904 AV	162
a19e3da5	163	mm_gc = to_of_mm_gpio_chip(gc);
1e714e54	164	qe_gc = gpiochip_get_data(gc);
1b9e8904 AV	165
	166	spin_lock_irqsave(&qe_gc->lock, flags);
	167
1a2d397a	168	err -= gc->base;
1b9e8904 AV	169	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
	170	qe_pin->controller = qe_gc;
	171	qe_pin->num = err;
	172	err = 0;
	173	} else {
	174	err = -EBUSY;
	175	}
	176
	177	spin_unlock_irqrestore(&qe_gc->lock, flags);
	178
	179	if (!err)
	180	return qe_pin;
1b9e8904 AV	181	err0:
	182	kfree(qe_pin);
	183	pr_debug("%s failed with status %d\n", __func__, err);
	184	return ERR_PTR(err);
	185	}
	186	EXPORT_SYMBOL(qe_pin_request);
	187
	188	/**
	189	* qe_pin_free - Free a pin
	190	* @qe_pin: pointer to the qe_pin structure
	191	* Context: any
	192	*
	193	* This function frees the qe_pin structure and makes a pin available
	194	* for further qe_pin_request() calls.
	195	*/
	196	void qe_pin_free(struct qe_pin *qe_pin)
	197	{
	198	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	199	unsigned long flags;
	200	const int pin = qe_pin->num;
	201
	202	spin_lock_irqsave(&qe_gc->lock, flags);
	203	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	204	spin_unlock_irqrestore(&qe_gc->lock, flags);
	205
	206	kfree(qe_pin);
	207	}
	208	EXPORT_SYMBOL(qe_pin_free);
	209
	210	/**
	211	* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
	212	* @qe_pin: pointer to the qe_pin structure
	213	* Context: any
	214	*
	215	* This function resets a pin to a dedicated peripheral function that
	216	* has been set up by the firmware.
	217	*/
	218	void qe_pin_set_dedicated(struct qe_pin *qe_pin)
	219	{
	220	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	221	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	222	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	223	int pin = qe_pin->num;
	224	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	225	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	226	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	227	unsigned long flags;
	228
	229	spin_lock_irqsave(&qe_gc->lock, flags);
	230
	231	if (second_reg) {
	232	clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
	233	clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	234	} else {
	235	clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
	236	clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	237	}
	238
	239	if (sregs->cpdata & mask1)
	240	qe_gc->cpdata \|= mask1;
	241	else
	242	qe_gc->cpdata &= ~mask1;
	243
	244	out_be32(&regs->cpdata, qe_gc->cpdata);
245	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
246
247	spin_unlock_irqrestore(&qe_gc->lock, flags);
248	}
249	EXPORT_SYMBOL(qe_pin_set_dedicated);
250
251	/**
252	* qe_pin_set_gpio - Set a pin to the GPIO mode
253	* @qe_pin: pointer to the qe_pin structure
254	* Context: any
255	*
256	* This function sets a pin to the GPIO mode.
257	*/
258	void qe_pin_set_gpio(struct qe_pin *qe_pin)
259	{
260	struct qe_gpio_chip *qe_gc = qe_pin->controller;
261	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
262	unsigned long flags;
263
264	spin_lock_irqsave(&qe_gc->lock, flags);
265
266	/* Let's make it input by default, GPIO API is able to change that. */
267	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
268
269	spin_unlock_irqrestore(&qe_gc->lock, flags);
270	}
271	EXPORT_SYMBOL(qe_pin_set_gpio);
272
d14b3dd6	273	static int __init qe_add_gpiochips(void)
32def337 AV	274	{
	275	struct device_node *np;
	276
	277	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
	278	int ret;
	279	struct qe_gpio_chip *qe_gc;
	280	struct of_mm_gpio_chip *mm_gc;
32def337 AV	281	struct gpio_chip *gc;
	282
	283	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
	284	if (!qe_gc) {
	285	ret = -ENOMEM;
	286	goto err;
	287	}
	288
	289	spin_lock_init(&qe_gc->lock);
	290
	291	mm_gc = &qe_gc->mm_gc;
a19e3da5	292	gc = &mm_gc->gc;
32def337 AV	293
32def337 AV	294	mm_gc->save_regs = qe_gpio_save_regs;
32def337 AV	295	gc->ngpio = QE_PIO_PINS;
	296	gc->direction_input = qe_gpio_dir_in;
	297	gc->direction_output = qe_gpio_dir_out;
	298	gc->get = qe_gpio_get;
	299	gc->set = qe_gpio_set;
	300
1e714e54	301	ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
32def337 AV	302	if (ret)
	303	goto err;
	304	continue;
	305	err:
	306	pr_err("%s: registration failed with status %d\n",
	307	np->full_name, ret);
	308	kfree(qe_gc);
	309	/* try others anyway */
	310	}
d14b3dd6	311	return 0;
32def337	312	}
d14b3dd6	313	arch_initcall(qe_add_gpiochips);