[mirror_ubuntu-focal-kernel.git] / drivers / soc / fsl / qe / qe_ic.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * drivers/soc/fsl/qe/qe_ic.h
 *
 * QUICC ENGINE Interrupt Controller Header
 *
 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Li Yang <leoli@freescale.com>
 * Based on code from Shlomi Gridish <gridish@freescale.com>
 */
#ifndef _POWERPC_SYSDEV_QE_IC_H
#define _POWERPC_SYSDEV_QE_IC_H

#include <soc/fsl/qe/qe_ic.h>

#define NR_QE_IC_INTS		64

/* QE IC registers offset */
#define QEIC_CICR		0x00
#define QEIC_CIVEC		0x04
#define QEIC_CRIPNR		0x08
#define QEIC_CIPNR		0x0c
#define QEIC_CIPXCC		0x10
#define QEIC_CIPYCC		0x14
#define QEIC_CIPWCC		0x18
#define QEIC_CIPZCC		0x1c
#define QEIC_CIMR		0x20
#define QEIC_CRIMR		0x24
#define QEIC_CICNR		0x28
#define QEIC_CIPRTA		0x30
#define QEIC_CIPRTB		0x34
#define QEIC_CRICR		0x3c
#define QEIC_CHIVEC		0x60

/* Interrupt priority registers */
#define CIPCC_SHIFT_PRI0	29
#define CIPCC_SHIFT_PRI1	26
#define CIPCC_SHIFT_PRI2	23
#define CIPCC_SHIFT_PRI3	20
#define CIPCC_SHIFT_PRI4	13
#define CIPCC_SHIFT_PRI5	10
#define CIPCC_SHIFT_PRI6	7
#define CIPCC_SHIFT_PRI7	4

/* CICR priority modes */
#define CICR_GWCC		0x00040000
#define CICR_GXCC		0x00020000
#define CICR_GYCC		0x00010000
#define CICR_GZCC		0x00080000
#define CICR_GRTA		0x00200000
#define CICR_GRTB		0x00400000
#define CICR_HPIT_SHIFT		8
#define CICR_HPIT_MASK		0x00000300
#define CICR_HP_SHIFT		24
#define CICR_HP_MASK		0x3f000000

/* CICNR */
#define CICNR_WCC1T_SHIFT	20
#define CICNR_ZCC1T_SHIFT	28
#define CICNR_YCC1T_SHIFT	12
#define CICNR_XCC1T_SHIFT	4

/* CRICR */
#define CRICR_RTA1T_SHIFT	20
#define CRICR_RTB1T_SHIFT	28

/* Signal indicator */
#define SIGNAL_MASK		3
#define SIGNAL_HIGH		2
#define SIGNAL_LOW		0

struct qe_ic {
	/* Control registers offset */
	volatile u32 __iomem *regs;

	/* The remapper for this QEIC */
	struct irq_domain *irqhost;

	/* The "linux" controller struct */
	struct irq_chip hc_irq;

	/* VIRQ numbers of QE high/low irqs */
	unsigned int virq_high;
	unsigned int virq_low;
};

/*
 * QE interrupt controller internal structure
 */
struct qe_ic_info {
	u32	mask;	  /* location of this source at the QIMR register. */
	u32	mask_reg; /* Mask register offset */
	u8	pri_code; /* for grouped interrupts sources - the interrupt
			     code as appears at the group priority register */
	u32	pri_reg;  /* Group priority register offset */
};

#endif /* _POWERPC_SYSDEV_QE_IC_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
98658538	2	/*
7aa1aa6e	3	* drivers/soc/fsl/qe/qe_ic.h
98658538 LY	4	*
	5	* QUICC ENGINE Interrupt Controller Header
	6	*
8a56e1ee	7	* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
98658538 LY	8	*
	9	* Author: Li Yang <leoli@freescale.com>
	10	* Based on code from Shlomi Gridish <gridish@freescale.com>
98658538 LY	11	*/
	12	#ifndef _POWERPC_SYSDEV_QE_IC_H
	13	#define _POWERPC_SYSDEV_QE_IC_H
	14
7aa1aa6e	15	#include <soc/fsl/qe/qe_ic.h>
98658538 LY	16
	17	#define NR_QE_IC_INTS 64
	18
	19	/* QE IC registers offset */
	20	#define QEIC_CICR 0x00
	21	#define QEIC_CIVEC 0x04
	22	#define QEIC_CRIPNR 0x08
	23	#define QEIC_CIPNR 0x0c
	24	#define QEIC_CIPXCC 0x10
	25	#define QEIC_CIPYCC 0x14
	26	#define QEIC_CIPWCC 0x18
	27	#define QEIC_CIPZCC 0x1c
	28	#define QEIC_CIMR 0x20
	29	#define QEIC_CRIMR 0x24
	30	#define QEIC_CICNR 0x28
	31	#define QEIC_CIPRTA 0x30
	32	#define QEIC_CIPRTB 0x34
	33	#define QEIC_CRICR 0x3c
	34	#define QEIC_CHIVEC 0x60
	35
	36	/* Interrupt priority registers */
	37	#define CIPCC_SHIFT_PRI0 29
	38	#define CIPCC_SHIFT_PRI1 26
	39	#define CIPCC_SHIFT_PRI2 23
	40	#define CIPCC_SHIFT_PRI3 20
	41	#define CIPCC_SHIFT_PRI4 13
	42	#define CIPCC_SHIFT_PRI5 10
	43	#define CIPCC_SHIFT_PRI6 7
	44	#define CIPCC_SHIFT_PRI7 4
	45
	46	/* CICR priority modes */
	47	#define CICR_GWCC 0x00040000
	48	#define CICR_GXCC 0x00020000
	49	#define CICR_GYCC 0x00010000
	50	#define CICR_GZCC 0x00080000
	51	#define CICR_GRTA 0x00200000
	52	#define CICR_GRTB 0x00400000
	53	#define CICR_HPIT_SHIFT 8
	54	#define CICR_HPIT_MASK 0x00000300
	55	#define CICR_HP_SHIFT 24
	56	#define CICR_HP_MASK 0x3f000000
	57
	58	/* CICNR */
	59	#define CICNR_WCC1T_SHIFT 20
	60	#define CICNR_ZCC1T_SHIFT 28
	61	#define CICNR_YCC1T_SHIFT 12
	62	#define CICNR_XCC1T_SHIFT 4
	63
	64	/* CRICR */
	65	#define CRICR_RTA1T_SHIFT 20
	66	#define CRICR_RTB1T_SHIFT 28
	67
	68	/* Signal indicator */
	69	#define SIGNAL_MASK 3
	70	#define SIGNAL_HIGH 2
	71	#define SIGNAL_LOW 0
	72
	73	struct qe_ic {
	74	/* Control registers offset */
	75	volatile u32 __iomem *regs;
	76
	77	/* The remapper for this QEIC */
bae1d8f1	78	struct irq_domain *irqhost;
98658538 LY	79
	80	/* The "linux" controller struct */
	81	struct irq_chip hc_irq;
	82
98658538 LY	83	/* VIRQ numbers of QE high/low irqs */
	84	unsigned int virq_high;
	85	unsigned int virq_low;
	86	};
	87
	88	/*
	89	* QE interrupt controller internal structure
	90	*/
	91	struct qe_ic_info {
	92	u32 mask; /* location of this source at the QIMR register. */
	93	u32 mask_reg; /* Mask register offset */
	94	u8 pri_code; /* for grouped interrupts sources - the interrupt
	95	code as appears at the group priority register */
	96	u32 pri_reg; /* Group priority register offset */
	97	};
	98
	99	#endif /* _POWERPC_SYSDEV_QE_IC_H */