[mirror_ubuntu-focal-kernel.git] / drivers / soc / fsl / qe / qe_tdm.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Authors:	Zhao Qiang <qiang.zhao@nxp.com>
 *
 * Description:
 * QE TDM API Set - TDM specific routines implementations.
 */
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <soc/fsl/qe/qe_tdm.h>

static int set_tdm_framer(const char *tdm_framer_type)
{
	if (strcmp(tdm_framer_type, "e1") == 0)
		return TDM_FRAMER_E1;
	else if (strcmp(tdm_framer_type, "t1") == 0)
		return TDM_FRAMER_T1;
	else
		return -EINVAL;
}

static void set_si_param(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
{
	struct si_mode_info *si_info = &ut_info->si_info;

	if (utdm->tdm_mode == TDM_INTERNAL_LOOPBACK) {
		si_info->simr_crt = 1;
		si_info->simr_rfsd = 0;
	}
}

int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
		     struct ucc_tdm_info *ut_info)
{
	const char *sprop;
	int ret = 0;
	u32 val;

	sprop = of_get_property(np, "fsl,rx-sync-clock", NULL);
	if (sprop) {
		ut_info->uf_info.rx_sync = qe_clock_source(sprop);
		if ((ut_info->uf_info.rx_sync < QE_CLK_NONE) ||
		    (ut_info->uf_info.rx_sync > QE_RSYNC_PIN)) {
			pr_err("QE-TDM: Invalid rx-sync-clock property\n");
			return -EINVAL;
		}
	} else {
		pr_err("QE-TDM: Invalid rx-sync-clock property\n");
		return -EINVAL;
	}

	sprop = of_get_property(np, "fsl,tx-sync-clock", NULL);
	if (sprop) {
		ut_info->uf_info.tx_sync = qe_clock_source(sprop);
		if ((ut_info->uf_info.tx_sync < QE_CLK_NONE) ||
		    (ut_info->uf_info.tx_sync > QE_TSYNC_PIN)) {
			pr_err("QE-TDM: Invalid tx-sync-clock property\n");
		return -EINVAL;
		}
	} else {
		pr_err("QE-TDM: Invalid tx-sync-clock property\n");
		return -EINVAL;
	}

	ret = of_property_read_u32_index(np, "fsl,tx-timeslot-mask", 0, &val);
	if (ret) {
		pr_err("QE-TDM: Invalid tx-timeslot-mask property\n");
		return -EINVAL;
	}
	utdm->tx_ts_mask = val;

	ret = of_property_read_u32_index(np, "fsl,rx-timeslot-mask", 0, &val);
	if (ret) {
		ret = -EINVAL;
		pr_err("QE-TDM: Invalid rx-timeslot-mask property\n");
		return ret;
	}
	utdm->rx_ts_mask = val;

	ret = of_property_read_u32_index(np, "fsl,tdm-id", 0, &val);
	if (ret) {
		ret = -EINVAL;
		pr_err("QE-TDM: No fsl,tdm-id property for this UCC\n");
		return ret;
	}
	utdm->tdm_port = val;
	ut_info->uf_info.tdm_num = utdm->tdm_port;

	if (of_property_read_bool(np, "fsl,tdm-internal-loopback"))
		utdm->tdm_mode = TDM_INTERNAL_LOOPBACK;
	else
		utdm->tdm_mode = TDM_NORMAL;

	sprop = of_get_property(np, "fsl,tdm-framer-type", NULL);
	if (!sprop) {
		ret = -EINVAL;
		pr_err("QE-TDM: No tdm-framer-type property for UCC\n");
		return ret;
	}
	ret = set_tdm_framer(sprop);
	if (ret < 0)
		return -EINVAL;
	utdm->tdm_framer_type = ret;

	ret = of_property_read_u32_index(np, "fsl,siram-entry-id", 0, &val);
	if (ret) {
		ret = -EINVAL;
		pr_err("QE-TDM: No siram entry id for UCC\n");
		return ret;
	}
	utdm->siram_entry_id = val;

	set_si_param(utdm, ut_info);
	return ret;
}
EXPORT_SYMBOL(ucc_of_parse_tdm);

void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
{
	struct si1 __iomem *si_regs;
	u16 __iomem *siram;
	u16 siram_entry_valid;
	u16 siram_entry_closed;
	u16 ucc_num;
	u8 csel;
	u16 sixmr;
	u16 tdm_port;
	u32 siram_entry_id;
	u32 mask;
	int i;

	si_regs = utdm->si_regs;
	siram = utdm->siram;
	ucc_num = ut_info->uf_info.ucc_num;
	tdm_port = utdm->tdm_port;
	siram_entry_id = utdm->siram_entry_id;

	if (utdm->tdm_framer_type == TDM_FRAMER_T1)
		utdm->num_of_ts = 24;
	if (utdm->tdm_framer_type == TDM_FRAMER_E1)
		utdm->num_of_ts = 32;

	/* set siram table */
	csel = (ucc_num < 4) ? ucc_num + 9 : ucc_num - 3;

	siram_entry_valid = SIR_CSEL(csel) | SIR_BYTE | SIR_CNT(0);
	siram_entry_closed = SIR_IDLE | SIR_BYTE | SIR_CNT(0);

	for (i = 0; i < utdm->num_of_ts; i++) {
		mask = 0x01 << i;

		if (utdm->tx_ts_mask & mask)
			iowrite16be(siram_entry_valid,
				    &siram[siram_entry_id * 32 + i]);
		else
			iowrite16be(siram_entry_closed,
				    &siram[siram_entry_id * 32 + i]);

		if (utdm->rx_ts_mask & mask)
			iowrite16be(siram_entry_valid,
				    &siram[siram_entry_id * 32 + 0x200 +  i]);
		else
			iowrite16be(siram_entry_closed,
				    &siram[siram_entry_id * 32 + 0x200 +  i]);
	}

	setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
		  SIR_LAST);
	setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
		  SIR_LAST);

	/* Set SIxMR register */
	sixmr = SIMR_SAD(siram_entry_id);

	sixmr &= ~SIMR_SDM_MASK;

	if (utdm->tdm_mode == TDM_INTERNAL_LOOPBACK)
		sixmr |= SIMR_SDM_INTERNAL_LOOPBACK;
	else
		sixmr |= SIMR_SDM_NORMAL;

	sixmr |= SIMR_RFSD(ut_info->si_info.simr_rfsd) |
			SIMR_TFSD(ut_info->si_info.simr_tfsd);

	if (ut_info->si_info.simr_crt)
		sixmr |= SIMR_CRT;
	if (ut_info->si_info.simr_sl)
		sixmr |= SIMR_SL;
	if (ut_info->si_info.simr_ce)
		sixmr |= SIMR_CE;
	if (ut_info->si_info.simr_fe)
		sixmr |= SIMR_FE;
	if (ut_info->si_info.simr_gm)
		sixmr |= SIMR_GM;

	switch (tdm_port) {
	case 0:
		iowrite16be(sixmr, &si_regs->sixmr1[0]);
		break;
	case 1:
		iowrite16be(sixmr, &si_regs->sixmr1[1]);
		break;
	case 2:
		iowrite16be(sixmr, &si_regs->sixmr1[2]);
		break;
	case 3:
		iowrite16be(sixmr, &si_regs->sixmr1[3]);
		break;
	default:
		pr_err("QE-TDM: can not find tdm sixmr reg\n");
		break;
	}
}
EXPORT_SYMBOL(ucc_tdm_init);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
35ef1c20 ZQ	2	/*
	3	* Copyright (C) 2015 Freescale Semiconductor, Inc. All rights reserved.
	4	*
	5	* Authors: Zhao Qiang <qiang.zhao@nxp.com>
	6	*
	7	* Description:
	8	* QE TDM API Set - TDM specific routines implementations.
35ef1c20 ZQ	9	*/
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/of_address.h>
	13	#include <linux/of_irq.h>
	14	#include <linux/of_platform.h>
	15	#include <soc/fsl/qe/qe_tdm.h>
	16
	17	static int set_tdm_framer(const char *tdm_framer_type)
	18	{
	19	if (strcmp(tdm_framer_type, "e1") == 0)
	20	return TDM_FRAMER_E1;
	21	else if (strcmp(tdm_framer_type, "t1") == 0)
	22	return TDM_FRAMER_T1;
	23	else
	24	return -EINVAL;
	25	}
	26
	27	static void set_si_param(struct ucc_tdm utdm, struct ucc_tdm_info ut_info)
	28	{
	29	struct si_mode_info *si_info = &ut_info->si_info;
	30
	31	if (utdm->tdm_mode == TDM_INTERNAL_LOOPBACK) {
	32	si_info->simr_crt = 1;
	33	si_info->simr_rfsd = 0;
	34	}
	35	}
	36
	37	int ucc_of_parse_tdm(struct device_node np, struct ucc_tdm utdm,
	38	struct ucc_tdm_info *ut_info)
	39	{
	40	const char *sprop;
	41	int ret = 0;
	42	u32 val;
35ef1c20 ZQ	43
	44	sprop = of_get_property(np, "fsl,rx-sync-clock", NULL);
	45	if (sprop) {
	46	ut_info->uf_info.rx_sync = qe_clock_source(sprop);
	47	if ((ut_info->uf_info.rx_sync < QE_CLK_NONE) \|\|
	48	(ut_info->uf_info.rx_sync > QE_RSYNC_PIN)) {
	49	pr_err("QE-TDM: Invalid rx-sync-clock property\n");
	50	return -EINVAL;
	51	}
	52	} else {
	53	pr_err("QE-TDM: Invalid rx-sync-clock property\n");
	54	return -EINVAL;
	55	}
	56
	57	sprop = of_get_property(np, "fsl,tx-sync-clock", NULL);
	58	if (sprop) {
	59	ut_info->uf_info.tx_sync = qe_clock_source(sprop);
	60	if ((ut_info->uf_info.tx_sync < QE_CLK_NONE) \|\|
	61	(ut_info->uf_info.tx_sync > QE_TSYNC_PIN)) {
	62	pr_err("QE-TDM: Invalid tx-sync-clock property\n");
	63	return -EINVAL;
	64	}
	65	} else {
	66	pr_err("QE-TDM: Invalid tx-sync-clock property\n");
	67	return -EINVAL;
	68	}
	69
	70	ret = of_property_read_u32_index(np, "fsl,tx-timeslot-mask", 0, &val);
	71	if (ret) {
	72	pr_err("QE-TDM: Invalid tx-timeslot-mask property\n");
	73	return -EINVAL;
	74	}
	75	utdm->tx_ts_mask = val;
	76
	77	ret = of_property_read_u32_index(np, "fsl,rx-timeslot-mask", 0, &val);
	78	if (ret) {
	79	ret = -EINVAL;
	80	pr_err("QE-TDM: Invalid rx-timeslot-mask property\n");
	81	return ret;
	82	}
	83	utdm->rx_ts_mask = val;
	84
	85	ret = of_property_read_u32_index(np, "fsl,tdm-id", 0, &val);
	86	if (ret) {
	87	ret = -EINVAL;
	88	pr_err("QE-TDM: No fsl,tdm-id property for this UCC\n");
	89	return ret;
	90	}
	91	utdm->tdm_port = val;
	92	ut_info->uf_info.tdm_num = utdm->tdm_port;
	93
74c269f6	94	if (of_property_read_bool(np, "fsl,tdm-internal-loopback"))
35ef1c20 ZQ	95	utdm->tdm_mode = TDM_INTERNAL_LOOPBACK;
	96	else
	97	utdm->tdm_mode = TDM_NORMAL;
	98
	99	sprop = of_get_property(np, "fsl,tdm-framer-type", NULL);
	100	if (!sprop) {
	101	ret = -EINVAL;
	102	pr_err("QE-TDM: No tdm-framer-type property for UCC\n");
	103	return ret;
	104	}
	105	ret = set_tdm_framer(sprop);
	106	if (ret < 0)
	107	return -EINVAL;
	108	utdm->tdm_framer_type = ret;
	109
	110	ret = of_property_read_u32_index(np, "fsl,siram-entry-id", 0, &val);
	111	if (ret) {
	112	ret = -EINVAL;
	113	pr_err("QE-TDM: No siram entry id for UCC\n");
	114	return ret;
	115	}
	116	utdm->siram_entry_id = val;
	117
	118	set_si_param(utdm, ut_info);
35ef1c20 ZQ	119	return ret;
35ef1c20 ZQ	120	}
4ba25162	121	EXPORT_SYMBOL(ucc_of_parse_tdm);
35ef1c20 ZQ	122
	123	void ucc_tdm_init(struct ucc_tdm utdm, struct ucc_tdm_info ut_info)
	124	{
	125	struct si1 __iomem *si_regs;
	126	u16 __iomem *siram;
	127	u16 siram_entry_valid;
	128	u16 siram_entry_closed;
	129	u16 ucc_num;
	130	u8 csel;
	131	u16 sixmr;
	132	u16 tdm_port;
	133	u32 siram_entry_id;
	134	u32 mask;
	135	int i;
	136
	137	si_regs = utdm->si_regs;
	138	siram = utdm->siram;
	139	ucc_num = ut_info->uf_info.ucc_num;
	140	tdm_port = utdm->tdm_port;
	141	siram_entry_id = utdm->siram_entry_id;
	142
	143	if (utdm->tdm_framer_type == TDM_FRAMER_T1)
	144	utdm->num_of_ts = 24;
	145	if (utdm->tdm_framer_type == TDM_FRAMER_E1)
	146	utdm->num_of_ts = 32;
	147
	148	/* set siram table */
	149	csel = (ucc_num < 4) ? ucc_num + 9 : ucc_num - 3;
	150
	151	siram_entry_valid = SIR_CSEL(csel) \| SIR_BYTE \| SIR_CNT(0);
	152	siram_entry_closed = SIR_IDLE \| SIR_BYTE \| SIR_CNT(0);
	153
	154	for (i = 0; i < utdm->num_of_ts; i++) {
	155	mask = 0x01 << i;
	156
	157	if (utdm->tx_ts_mask & mask)
	158	iowrite16be(siram_entry_valid,
	159	&siram[siram_entry_id * 32 + i]);
	160	else
	161	iowrite16be(siram_entry_closed,
	162	&siram[siram_entry_id * 32 + i]);
	163
	164	if (utdm->rx_ts_mask & mask)
	165	iowrite16be(siram_entry_valid,
	166	&siram[siram_entry_id * 32 + 0x200 + i]);
	167	else
	168	iowrite16be(siram_entry_closed,
	169	&siram[siram_entry_id * 32 + 0x200 + i]);
	170	}
	171
	172	setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
	173	SIR_LAST);
	174	setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
	175	SIR_LAST);
	176
	177	/* Set SIxMR register */
	178	sixmr = SIMR_SAD(siram_entry_id);
	179
	180	sixmr &= ~SIMR_SDM_MASK;
	181
	182	if (utdm->tdm_mode == TDM_INTERNAL_LOOPBACK)
	183	sixmr \|= SIMR_SDM_INTERNAL_LOOPBACK;
	184	else
	185	sixmr \|= SIMR_SDM_NORMAL;
186
187	sixmr \|= SIMR_RFSD(ut_info->si_info.simr_rfsd) \|
188	SIMR_TFSD(ut_info->si_info.simr_tfsd);
189
190	if (ut_info->si_info.simr_crt)
191	sixmr \|= SIMR_CRT;
192	if (ut_info->si_info.simr_sl)
193	sixmr \|= SIMR_SL;
194	if (ut_info->si_info.simr_ce)
195	sixmr \|= SIMR_CE;
196	if (ut_info->si_info.simr_fe)
197	sixmr \|= SIMR_FE;
198	if (ut_info->si_info.simr_gm)
199	sixmr \|= SIMR_GM;
200
201	switch (tdm_port) {
202	case 0:
203	iowrite16be(sixmr, &si_regs->sixmr1[0]);
204	break;
205	case 1:
206	iowrite16be(sixmr, &si_regs->sixmr1[1]);
207	break;
208	case 2:
209	iowrite16be(sixmr, &si_regs->sixmr1[2]);
210	break;
211	case 3:
212	iowrite16be(sixmr, &si_regs->sixmr1[3]);
213	break;
214	default:
215	pr_err("QE-TDM: can not find tdm sixmr reg\n");
216	break;
217	}
218	}
4ba25162	219	EXPORT_SYMBOL(ucc_tdm_init);