[mirror_ubuntu-jammy-kernel.git] / drivers / soc / fsl / qe / ucc_fast.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Authors: 	Shlomi Gridish <gridish@freescale.com>
 * 		Li Yang <leoli@freescale.com>
 *
 * Description:
 * QE UCC Fast API Set - UCC Fast specific routines implementations.
 */
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/export.h>

#include <asm/io.h>
#include <soc/fsl/qe/immap_qe.h>
#include <soc/fsl/qe/qe.h>

#include <soc/fsl/qe/ucc.h>
#include <soc/fsl/qe/ucc_fast.h>

void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
{
	printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num);
	printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);

	printk(KERN_INFO "gumr  : addr=0x%p, val=0x%08x\n",
		  &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
	printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
		  &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
	printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
	printk(KERN_INFO "udsr  : addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
	printk(KERN_INFO "ucce  : addr=0x%p, val=0x%08x\n",
		  &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
	printk(KERN_INFO "uccm  : addr=0x%p, val=0x%08x\n",
		  &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
	printk(KERN_INFO "uccs  : addr=0x%p, val=0x%02x\n",
		  &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
	printk(KERN_INFO "urfb  : addr=0x%p, val=0x%08x\n",
		  &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
	printk(KERN_INFO "urfs  : addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
	printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
	printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
	printk(KERN_INFO "utfb  : addr=0x%p, val=0x%08x\n",
		  &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
	printk(KERN_INFO "utfs  : addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
	printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
	printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
	printk(KERN_INFO "utpt  : addr=0x%p, val=0x%04x\n",
		  &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
	printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
		  &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
	printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
		  &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
}
EXPORT_SYMBOL(ucc_fast_dump_regs);

u32 ucc_fast_get_qe_cr_subblock(int uccf_num)
{
	switch (uccf_num) {
	case 0: return QE_CR_SUBBLOCK_UCCFAST1;
	case 1: return QE_CR_SUBBLOCK_UCCFAST2;
	case 2: return QE_CR_SUBBLOCK_UCCFAST3;
	case 3: return QE_CR_SUBBLOCK_UCCFAST4;
	case 4: return QE_CR_SUBBLOCK_UCCFAST5;
	case 5: return QE_CR_SUBBLOCK_UCCFAST6;
	case 6: return QE_CR_SUBBLOCK_UCCFAST7;
	case 7: return QE_CR_SUBBLOCK_UCCFAST8;
	default: return QE_CR_SUBBLOCK_INVALID;
	}
}
EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);

void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
{
	out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
}
EXPORT_SYMBOL(ucc_fast_transmit_on_demand);

void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
{
	struct ucc_fast __iomem *uf_regs;
	u32 gumr;

	uf_regs = uccf->uf_regs;

	/* Enable reception and/or transmission on this UCC. */
	gumr = in_be32(&uf_regs->gumr);
	if (mode & COMM_DIR_TX) {
		gumr |= UCC_FAST_GUMR_ENT;
		uccf->enabled_tx = 1;
	}
	if (mode & COMM_DIR_RX) {
		gumr |= UCC_FAST_GUMR_ENR;
		uccf->enabled_rx = 1;
	}
	out_be32(&uf_regs->gumr, gumr);
}
EXPORT_SYMBOL(ucc_fast_enable);

void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
{
	struct ucc_fast __iomem *uf_regs;
	u32 gumr;

	uf_regs = uccf->uf_regs;

	/* Disable reception and/or transmission on this UCC. */
	gumr = in_be32(&uf_regs->gumr);
	if (mode & COMM_DIR_TX) {
		gumr &= ~UCC_FAST_GUMR_ENT;
		uccf->enabled_tx = 0;
	}
	if (mode & COMM_DIR_RX) {
		gumr &= ~UCC_FAST_GUMR_ENR;
		uccf->enabled_rx = 0;
	}
	out_be32(&uf_regs->gumr, gumr);
}
EXPORT_SYMBOL(ucc_fast_disable);

int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
{
	struct ucc_fast_private *uccf;
	struct ucc_fast __iomem *uf_regs;
	u32 gumr;
	int ret;

	if (!uf_info)
		return -EINVAL;

	/* check if the UCC port number is in range. */
	if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
		printk(KERN_ERR "%s: illegal UCC number\n", __func__);
		return -EINVAL;
	}

	/* Check that 'max_rx_buf_length' is properly aligned (4). */
	if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
		printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
			__func__);
		return -EINVAL;
	}

	/* Validate Virtual Fifo register values */
	if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
		printk(KERN_ERR "%s: urfs is too small\n", __func__);
		return -EINVAL;
	}

	if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
		printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
		return -EINVAL;
	}

	if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
		printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
		return -EINVAL;
	}

	if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
		printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
		return -EINVAL;
	}

	if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
		printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
		return -EINVAL;
	}

	if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
		printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
		return -EINVAL;
	}

	if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
		printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
		return -EINVAL;
	}

	uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
	if (!uccf) {
		printk(KERN_ERR "%s: Cannot allocate private data\n",
			__func__);
		return -ENOMEM;
	}

	/* Fill fast UCC structure */
	uccf->uf_info = uf_info;
	/* Set the PHY base address */
	uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
	if (uccf->uf_regs == NULL) {
		printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
		kfree(uccf);
		return -ENOMEM;
	}

	uccf->enabled_tx = 0;
	uccf->enabled_rx = 0;
	uccf->stopped_tx = 0;
	uccf->stopped_rx = 0;
	uf_regs = uccf->uf_regs;
	uccf->p_ucce = &uf_regs->ucce;
	uccf->p_uccm = &uf_regs->uccm;
#ifdef CONFIG_UGETH_TX_ON_DEMAND
	uccf->p_utodr = &uf_regs->utodr;
#endif
#ifdef STATISTICS
	uccf->tx_frames = 0;
	uccf->rx_frames = 0;
	uccf->rx_discarded = 0;
#endif				/* STATISTICS */

	/* Set UCC to fast type */
	ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
	if (ret) {
		printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
		ucc_fast_free(uccf);
		return ret;
	}

	uccf->mrblr = uf_info->max_rx_buf_length;

	/* Set GUMR */
	/* For more details see the hardware spec. */
	gumr = uf_info->ttx_trx;
	if (uf_info->tci)
		gumr |= UCC_FAST_GUMR_TCI;
	if (uf_info->cdp)
		gumr |= UCC_FAST_GUMR_CDP;
	if (uf_info->ctsp)
		gumr |= UCC_FAST_GUMR_CTSP;
	if (uf_info->cds)
		gumr |= UCC_FAST_GUMR_CDS;
	if (uf_info->ctss)
		gumr |= UCC_FAST_GUMR_CTSS;
	if (uf_info->txsy)
		gumr |= UCC_FAST_GUMR_TXSY;
	if (uf_info->rsyn)
		gumr |= UCC_FAST_GUMR_RSYN;
	gumr |= uf_info->synl;
	if (uf_info->rtsm)
		gumr |= UCC_FAST_GUMR_RTSM;
	gumr |= uf_info->renc;
	if (uf_info->revd)
		gumr |= UCC_FAST_GUMR_REVD;
	gumr |= uf_info->tenc;
	gumr |= uf_info->tcrc;
	gumr |= uf_info->mode;
	out_be32(&uf_regs->gumr, gumr);

	/* Allocate memory for Tx Virtual Fifo */
	uccf->ucc_fast_tx_virtual_fifo_base_offset =
	    qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
	if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
		printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
			__func__);
		uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
		ucc_fast_free(uccf);
		return -ENOMEM;
	}

	/* Allocate memory for Rx Virtual Fifo */
	uccf->ucc_fast_rx_virtual_fifo_base_offset =
		qe_muram_alloc(uf_info->urfs +
			   UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
			   UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
	if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
		printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
			__func__);
		uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
		ucc_fast_free(uccf);
		return -ENOMEM;
	}

	/* Set Virtual Fifo registers */
	out_be16(&uf_regs->urfs, uf_info->urfs);
	out_be16(&uf_regs->urfet, uf_info->urfet);
	out_be16(&uf_regs->urfset, uf_info->urfset);
	out_be16(&uf_regs->utfs, uf_info->utfs);
	out_be16(&uf_regs->utfet, uf_info->utfet);
	out_be16(&uf_regs->utftt, uf_info->utftt);
	/* utfb, urfb are offsets from MURAM base */
	out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
	out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);

	/* Mux clocking */
	/* Grant Support */
	ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
	/* Breakpoint Support */
	ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
	/* Set Tsa or NMSI mode. */
	ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
	/* If NMSI (not Tsa), set Tx and Rx clock. */
	if (!uf_info->tsa) {
		/* Rx clock routing */
		if ((uf_info->rx_clock != QE_CLK_NONE) &&
		    ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
					COMM_DIR_RX)) {
			printk(KERN_ERR "%s: illegal value for RX clock\n",
			       __func__);
			ucc_fast_free(uccf);
			return -EINVAL;
		}
		/* Tx clock routing */
		if ((uf_info->tx_clock != QE_CLK_NONE) &&
		    ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
					COMM_DIR_TX)) {
			printk(KERN_ERR "%s: illegal value for TX clock\n",
			       __func__);
			ucc_fast_free(uccf);
			return -EINVAL;
		}
	} else {
		/* tdm Rx clock routing */
		if ((uf_info->rx_clock != QE_CLK_NONE) &&
		    ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->rx_clock,
					 COMM_DIR_RX)) {
			pr_err("%s: illegal value for RX clock", __func__);
			ucc_fast_free(uccf);
			return -EINVAL;
		}

		/* tdm Tx clock routing */
		if ((uf_info->tx_clock != QE_CLK_NONE) &&
		    ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->tx_clock,
					 COMM_DIR_TX)) {
			pr_err("%s: illegal value for TX clock", __func__);
			ucc_fast_free(uccf);
			return -EINVAL;
		}

		/* tdm Rx sync clock routing */
		if ((uf_info->rx_sync != QE_CLK_NONE) &&
		    ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->rx_sync,
					  COMM_DIR_RX)) {
			pr_err("%s: illegal value for RX clock", __func__);
			ucc_fast_free(uccf);
			return -EINVAL;
		}

		/* tdm Tx sync clock routing */
		if ((uf_info->tx_sync != QE_CLK_NONE) &&
		    ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->tx_sync,
					  COMM_DIR_TX)) {
			pr_err("%s: illegal value for TX clock", __func__);
			ucc_fast_free(uccf);
			return -EINVAL;
		}
	}

	/* Set interrupt mask register at UCC level. */
	out_be32(&uf_regs->uccm, uf_info->uccm_mask);

	/* First, clear anything pending at UCC level,
	 * otherwise, old garbage may come through
	 * as soon as the dam is opened. */

	/* Writing '1' clears */
	out_be32(&uf_regs->ucce, 0xffffffff);

	*uccf_ret = uccf;
	return 0;
}
EXPORT_SYMBOL(ucc_fast_init);

void ucc_fast_free(struct ucc_fast_private * uccf)
{
	if (!uccf)
		return;

	if (uccf->ucc_fast_tx_virtual_fifo_base_offset)
		qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset);

	if (uccf->ucc_fast_rx_virtual_fifo_base_offset)
		qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);

	if (uccf->uf_regs)
		iounmap(uccf->uf_regs);

	kfree(uccf);
}
EXPORT_SYMBOL(ucc_fast_free);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
98658538	2	/*
8a56e1ee	3	* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
98658538 LY	4	*
	5	* Authors: Shlomi Gridish <gridish@freescale.com>
	6	* Li Yang <leoli@freescale.com>
	7	*
5af68af5 TT	8	* Description:
5af68af5 TT	9	* QE UCC Fast API Set - UCC Fast specific routines implementations.
98658538 LY	10	*/
98658538 LY	11	#include <linux/kernel.h>
98658538 LY	12	#include <linux/errno.h>
	13	#include <linux/slab.h>
	14	#include <linux/stddef.h>
	15	#include <linux/interrupt.h>
4c35630c	16	#include <linux/err.h>
4b16f8e2	17	#include <linux/export.h>
98658538 LY	18
98658538 LY	19	#include <asm/io.h>
7aa1aa6e ZQ	20	#include <soc/fsl/qe/immap_qe.h>
7aa1aa6e ZQ	21	#include <soc/fsl/qe/qe.h>
98658538	22
7aa1aa6e ZQ	23	#include <soc/fsl/qe/ucc.h>
7aa1aa6e ZQ	24	#include <soc/fsl/qe/ucc_fast.h>
98658538	25
98658538 LY	26	void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
98658538 LY	27	{
6b0b594b TT	28	printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num);
	29	printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
	30
	31	printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
	32	&uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
	33	printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
	34	&uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
	35	printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
	36	&uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
	37	printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
	38	&uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
	39	printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
	40	&uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
	41	printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
	42	&uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
	43	printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
7e1cc9c5	44	&uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
6b0b594b TT	45	printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
	46	&uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
	47	printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
	48	&uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
	49	printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
	50	&uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
	51	printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
	52	&uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
	53	printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
	54	&uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
	55	printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
	56	&uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
	57	printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
	58	&uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
	59	printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
	60	&uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
	61	printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
	62	&uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
	63	printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
	64	&uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
	65	printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
7e1cc9c5	66	&uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
98658538	67	}
65482ccf	68	EXPORT_SYMBOL(ucc_fast_dump_regs);
98658538 LY	69
	70	u32 ucc_fast_get_qe_cr_subblock(int uccf_num)
	71	{
	72	switch (uccf_num) {
5af68af5	73	case 0: return QE_CR_SUBBLOCK_UCCFAST1;
98658538 LY	74	case 1: return QE_CR_SUBBLOCK_UCCFAST2;
	75	case 2: return QE_CR_SUBBLOCK_UCCFAST3;
	76	case 3: return QE_CR_SUBBLOCK_UCCFAST4;
	77	case 4: return QE_CR_SUBBLOCK_UCCFAST5;
	78	case 5: return QE_CR_SUBBLOCK_UCCFAST6;
	79	case 6: return QE_CR_SUBBLOCK_UCCFAST7;
5af68af5	80	case 7: return QE_CR_SUBBLOCK_UCCFAST8;
98658538 LY	81	default: return QE_CR_SUBBLOCK_INVALID;
	82	}
	83	}
65482ccf	84	EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
98658538 LY	85
	86	void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
	87	{
	88	out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
	89	}
65482ccf	90	EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
98658538 LY	91
	92	void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
	93	{
7e1cc9c5	94	struct ucc_fast __iomem *uf_regs;
98658538 LY	95	u32 gumr;
	96
	97	uf_regs = uccf->uf_regs;
	98
	99	/* Enable reception and/or transmission on this UCC. */
	100	gumr = in_be32(&uf_regs->gumr);
	101	if (mode & COMM_DIR_TX) {
	102	gumr \|= UCC_FAST_GUMR_ENT;
	103	uccf->enabled_tx = 1;
	104	}
	105	if (mode & COMM_DIR_RX) {
	106	gumr \|= UCC_FAST_GUMR_ENR;
	107	uccf->enabled_rx = 1;
	108	}
	109	out_be32(&uf_regs->gumr, gumr);
	110	}
65482ccf	111	EXPORT_SYMBOL(ucc_fast_enable);
98658538 LY	112
	113	void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
	114	{
7e1cc9c5	115	struct ucc_fast __iomem *uf_regs;
98658538 LY	116	u32 gumr;
	117
	118	uf_regs = uccf->uf_regs;
	119
	120	/* Disable reception and/or transmission on this UCC. */
	121	gumr = in_be32(&uf_regs->gumr);
	122	if (mode & COMM_DIR_TX) {
	123	gumr &= ~UCC_FAST_GUMR_ENT;
	124	uccf->enabled_tx = 0;
	125	}
	126	if (mode & COMM_DIR_RX) {
	127	gumr &= ~UCC_FAST_GUMR_ENR;
	128	uccf->enabled_rx = 0;
	129	}
	130	out_be32(&uf_regs->gumr, gumr);
	131	}
65482ccf	132	EXPORT_SYMBOL(ucc_fast_disable);
98658538 LY	133
	134	int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
	135	{
	136	struct ucc_fast_private *uccf;
7e1cc9c5	137	struct ucc_fast __iomem *uf_regs;
5af68af5	138	u32 gumr;
98658538 LY	139	int ret;
98658538 LY	140
98658538 LY	141	if (!uf_info)
	142	return -EINVAL;
	143
	144	/* check if the UCC port number is in range. */
	145	if ((uf_info->ucc_num < 0) \|\| (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
e48b1b45	146	printk(KERN_ERR "%s: illegal UCC number\n", __func__);
98658538 LY	147	return -EINVAL;
	148	}
	149
	150	/* Check that 'max_rx_buf_length' is properly aligned (4). */
	151	if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
6b0b594b	152	printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
e48b1b45	153	__func__);
98658538 LY	154	return -EINVAL;
	155	}
	156
	157	/* Validate Virtual Fifo register values */
	158	if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
e48b1b45	159	printk(KERN_ERR "%s: urfs is too small\n", __func__);
98658538 LY	160	return -EINVAL;
	161	}
	162
	163	if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
e48b1b45	164	printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
98658538 LY	165	return -EINVAL;
	166	}
	167
	168	if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
e48b1b45	169	printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
98658538 LY	170	return -EINVAL;
	171	}
	172
	173	if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
e48b1b45	174	printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
98658538 LY	175	return -EINVAL;
	176	}
	177
	178	if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
e48b1b45	179	printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
98658538 LY	180	return -EINVAL;
	181	}
	182
	183	if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
e48b1b45	184	printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
98658538 LY	185	return -EINVAL;
	186	}
	187
	188	if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
e48b1b45	189	printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
98658538 LY	190	return -EINVAL;
	191	}
	192
f8485350	193	uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
98658538	194	if (!uccf) {
6b0b594b	195	printk(KERN_ERR "%s: Cannot allocate private data\n",
e48b1b45	196	__func__);
98658538 LY	197	return -ENOMEM;
98658538 LY	198	}
98658538 LY	199
	200	/* Fill fast UCC structure */
	201	uccf->uf_info = uf_info;
	202	/* Set the PHY base address */
5af68af5	203	uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
98658538	204	if (uccf->uf_regs == NULL) {
e48b1b45	205	printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
61a4e9e9	206	kfree(uccf);
98658538 LY	207	return -ENOMEM;
	208	}
	209
	210	uccf->enabled_tx = 0;
	211	uccf->enabled_rx = 0;
	212	uccf->stopped_tx = 0;
	213	uccf->stopped_rx = 0;
	214	uf_regs = uccf->uf_regs;
7e1cc9c5 AF	215	uccf->p_ucce = &uf_regs->ucce;
7e1cc9c5 AF	216	uccf->p_uccm = &uf_regs->uccm;
d5b9049d	217	#ifdef CONFIG_UGETH_TX_ON_DEMAND
7e1cc9c5	218	uccf->p_utodr = &uf_regs->utodr;
d5b9049d	219	#endif
98658538 LY	220	#ifdef STATISTICS
	221	uccf->tx_frames = 0;
	222	uccf->rx_frames = 0;
	223	uccf->rx_discarded = 0;
	224	#endif /* STATISTICS */
	225
98658538	226	/* Set UCC to fast type */
6b0b594b TT	227	ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
6b0b594b TT	228	if (ret) {
e48b1b45	229	printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
98658538 LY	230	ucc_fast_free(uccf);
	231	return ret;
	232	}
	233
	234	uccf->mrblr = uf_info->max_rx_buf_length;
	235
	236	/* Set GUMR */
	237	/* For more details see the hardware spec. */
5af68af5	238	gumr = uf_info->ttx_trx;
98658538 LY	239	if (uf_info->tci)
98658538 LY	240	gumr \|= UCC_FAST_GUMR_TCI;
98658538 LY	241	if (uf_info->cdp)
	242	gumr \|= UCC_FAST_GUMR_CDP;
	243	if (uf_info->ctsp)
	244	gumr \|= UCC_FAST_GUMR_CTSP;
	245	if (uf_info->cds)
	246	gumr \|= UCC_FAST_GUMR_CDS;
	247	if (uf_info->ctss)
	248	gumr \|= UCC_FAST_GUMR_CTSS;
	249	if (uf_info->txsy)
	250	gumr \|= UCC_FAST_GUMR_TXSY;
	251	if (uf_info->rsyn)
	252	gumr \|= UCC_FAST_GUMR_RSYN;
	253	gumr \|= uf_info->synl;
	254	if (uf_info->rtsm)
	255	gumr \|= UCC_FAST_GUMR_RTSM;
	256	gumr \|= uf_info->renc;
	257	if (uf_info->revd)
	258	gumr \|= UCC_FAST_GUMR_REVD;
	259	gumr \|= uf_info->tenc;
	260	gumr \|= uf_info->tcrc;
	261	gumr \|= uf_info->mode;
	262	out_be32(&uf_regs->gumr, gumr);
	263
	264	/* Allocate memory for Tx Virtual Fifo */
	265	uccf->ucc_fast_tx_virtual_fifo_base_offset =
	266	qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
4c35630c	267	if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
6b0b594b	268	printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
e48b1b45	269	__func__);
98658538 LY	270	uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
	271	ucc_fast_free(uccf);
	272	return -ENOMEM;
	273	}
	274
	275	/* Allocate memory for Rx Virtual Fifo */
	276	uccf->ucc_fast_rx_virtual_fifo_base_offset =
5af68af5	277	qe_muram_alloc(uf_info->urfs +
98658538 LY	278	UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
98658538 LY	279	UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
4c35630c	280	if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
6b0b594b	281	printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
e48b1b45	282	__func__);
98658538 LY	283	uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
	284	ucc_fast_free(uccf);
	285	return -ENOMEM;
	286	}
	287
	288	/* Set Virtual Fifo registers */
	289	out_be16(&uf_regs->urfs, uf_info->urfs);
	290	out_be16(&uf_regs->urfet, uf_info->urfet);
	291	out_be16(&uf_regs->urfset, uf_info->urfset);
	292	out_be16(&uf_regs->utfs, uf_info->utfs);
	293	out_be16(&uf_regs->utfet, uf_info->utfet);
	294	out_be16(&uf_regs->utftt, uf_info->utftt);
	295	/* utfb, urfb are offsets from MURAM base */
	296	out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
	297	out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
	298
	299	/* Mux clocking */
	300	/* Grant Support */
	301	ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
	302	/* Breakpoint Support */
	303	ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
	304	/* Set Tsa or NMSI mode. */
	305	ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
	306	/* If NMSI (not Tsa), set Tx and Rx clock. */
	307	if (!uf_info->tsa) {
	308	/* Rx clock routing */
5af68af5 TT	309	if ((uf_info->rx_clock != QE_CLK_NONE) &&
	310	ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
	311	COMM_DIR_RX)) {
6b0b594b	312	printk(KERN_ERR "%s: illegal value for RX clock\n",
e48b1b45	313	__func__);
5af68af5 TT	314	ucc_fast_free(uccf);
5af68af5 TT	315	return -EINVAL;
98658538 LY	316	}
98658538 LY	317	/* Tx clock routing */
5af68af5 TT	318	if ((uf_info->tx_clock != QE_CLK_NONE) &&
	319	ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
	320	COMM_DIR_TX)) {
6b0b594b	321	printk(KERN_ERR "%s: illegal value for TX clock\n",
e48b1b45	322	__func__);
5af68af5 TT	323	ucc_fast_free(uccf);
5af68af5 TT	324	return -EINVAL;
98658538	325	}
bb8b2062 ZQ	326	} else {
	327	/* tdm Rx clock routing */
	328	if ((uf_info->rx_clock != QE_CLK_NONE) &&
	329	ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->rx_clock,
	330	COMM_DIR_RX)) {
	331	pr_err("%s: illegal value for RX clock", __func__);
	332	ucc_fast_free(uccf);
	333	return -EINVAL;
	334	}
	335
	336	/* tdm Tx clock routing */
	337	if ((uf_info->tx_clock != QE_CLK_NONE) &&
	338	ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->tx_clock,
	339	COMM_DIR_TX)) {
	340	pr_err("%s: illegal value for TX clock", __func__);
	341	ucc_fast_free(uccf);
	342	return -EINVAL;
	343	}
	344
	345	/* tdm Rx sync clock routing */
	346	if ((uf_info->rx_sync != QE_CLK_NONE) &&
	347	ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->rx_sync,
	348	COMM_DIR_RX)) {
	349	pr_err("%s: illegal value for RX clock", __func__);
	350	ucc_fast_free(uccf);
	351	return -EINVAL;
	352	}
	353
	354	/* tdm Tx sync clock routing */
	355	if ((uf_info->tx_sync != QE_CLK_NONE) &&
	356	ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->tx_sync,
	357	COMM_DIR_TX)) {
	358	pr_err("%s: illegal value for TX clock", __func__);
	359	ucc_fast_free(uccf);
	360	return -EINVAL;
	361	}
98658538 LY	362	}
	363
	364	/* Set interrupt mask register at UCC level. */
	365	out_be32(&uf_regs->uccm, uf_info->uccm_mask);
	366
	367	/* First, clear anything pending at UCC level,
	368	* otherwise, old garbage may come through
5af68af5 TT	369	* as soon as the dam is opened. */
	370
	371	/* Writing '1' clears */
98658538 LY	372	out_be32(&uf_regs->ucce, 0xffffffff);
	373
	374	*uccf_ret = uccf;
	375	return 0;
	376	}
65482ccf	377	EXPORT_SYMBOL(ucc_fast_init);
98658538 LY	378
	379	void ucc_fast_free(struct ucc_fast_private * uccf)
	380	{
	381	if (!uccf)
	382	return;
	383
	384	if (uccf->ucc_fast_tx_virtual_fifo_base_offset)
	385	qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset);
	386
	387	if (uccf->ucc_fast_rx_virtual_fifo_base_offset)
	388	qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);
	389
61a4e9e9 TT	390	if (uccf->uf_regs)
	391	iounmap(uccf->uf_regs);
	392
98658538 LY	393	kfree(uccf);
98658538 LY	394	}
65482ccf	395	EXPORT_SYMBOL(ucc_fast_free);